164 lines · c
1// REQUIRES: arm-registered-target2// RUN: %clang_cc1 -triple arm64-apple-ios9 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK3// RUN: %clang_cc1 -triple armv7-apple-ios9 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK4// RUN: %clang_cc1 -triple x86_64-apple-macos10.13 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK5 6typedef __fp16 half4 __attribute__ ((vector_size (8)));7typedef short short4 __attribute__ ((vector_size (8)));8 9half4 hv0, hv1;10short4 sv0;11 12// CHECK-LABEL: testFP16Vec013// CHECK: %[[V0:.*]] = load <4 x half>, ptr @hv0, align 814// CHECK: %[[CONV:.*]] = fpext <4 x half> %[[V0]] to <4 x float>15// CHECK: %[[V1:.*]] = load <4 x half>, ptr @hv1, align 816// CHECK: %[[CONV1:.*]] = fpext <4 x half> %[[V1]] to <4 x float>17// CHECK: %[[ADD:.*]] = fadd <4 x float> %[[CONV]], %[[CONV1]]18// CHECK: %[[CONV2:.*]] = fptrunc <4 x float> %[[ADD]] to <4 x half>19// CHECK: store <4 x half> %[[CONV2]], ptr @hv0, align 820// CHECK: %[[V2:.*]] = load <4 x half>, ptr @hv0, align 821// CHECK: %[[CONV3:.*]] = fpext <4 x half> %[[V2]] to <4 x float>22// CHECK: %[[V3:.*]] = load <4 x half>, ptr @hv1, align 823// CHECK: %[[CONV4:.*]] = fpext <4 x half> %[[V3]] to <4 x float>24// CHECK: %[[SUB:.*]] = fsub <4 x float> %[[CONV3]], %[[CONV4]]25// CHECK: %[[CONV5:.*]] = fptrunc <4 x float> %[[SUB]] to <4 x half>26// CHECK: store <4 x half> %[[CONV5]], ptr @hv0, align 827// CHECK: %[[V4:.*]] = load <4 x half>, ptr @hv0, align 828// CHECK: %[[CONV6:.*]] = fpext <4 x half> %[[V4]] to <4 x float>29// CHECK: %[[V5:.*]] = load <4 x half>, ptr @hv1, align 830// CHECK: %[[CONV7:.*]] = fpext <4 x half> %[[V5]] to <4 x float>31// CHECK: %[[MUL:.*]] = fmul <4 x float> %[[CONV6]], %[[CONV7]]32// CHECK: %[[CONV8:.*]] = fptrunc <4 x float> %[[MUL]] to <4 x half>33// CHECK: store <4 x half> %[[CONV8]], ptr @hv0, align 834// CHECK: %[[V6:.*]] = load <4 x half>, ptr @hv0, align 835// CHECK: %[[CONV9:.*]] = fpext <4 x half> %[[V6]] to <4 x float>36// CHECK: %[[V7:.*]] = load <4 x half>, ptr @hv1, align 837// CHECK: %[[CONV10:.*]] = fpext <4 x half> %[[V7]] to <4 x float>38// CHECK: %[[DIV:.*]] = fdiv <4 x float> %[[CONV9]], %[[CONV10]]39// CHECK: %[[CONV11:.*]] = fptrunc <4 x float> %[[DIV]] to <4 x half>40// CHECK: store <4 x half> %[[CONV11]], ptr @hv0, align 841 42void testFP16Vec0() {43 hv0 = hv0 + hv1;44 hv0 = hv0 - hv1;45 hv0 = hv0 * hv1;46 hv0 = hv0 / hv1;47}48 49// CHECK-LABEL: testFP16Vec150// CHECK: %[[V0:.*]] = load <4 x half>, ptr @hv1, align 851// CHECK: %[[CONV:.*]] = fpext <4 x half> %[[V0]] to <4 x float>52// CHECK: %[[V1:.*]] = load <4 x half>, ptr @hv0, align 853// CHECK: %[[CONV1:.*]] = fpext <4 x half> %[[V1]] to <4 x float>54// CHECK: %[[ADD:.*]] = fadd <4 x float> %[[CONV1]], %[[CONV]]55// CHECK: %[[CONV2:.*]] = fptrunc <4 x float> %[[ADD]] to <4 x half>56// CHECK: store <4 x half> %[[CONV2]], ptr @hv0, align 857// CHECK: %[[V2:.*]] = load <4 x half>, ptr @hv1, align 858// CHECK: %[[CONV3:.*]] = fpext <4 x half> %[[V2]] to <4 x float>59// CHECK: %[[V3:.*]] = load <4 x half>, ptr @hv0, align 860// CHECK: %[[CONV4:.*]] = fpext <4 x half> %[[V3]] to <4 x float>61// CHECK: %[[SUB:.*]] = fsub <4 x float> %[[CONV4]], %[[CONV3]]62// CHECK: %[[CONV5:.*]] = fptrunc <4 x float> %[[SUB]] to <4 x half>63// CHECK: store <4 x half> %[[CONV5]], ptr @hv0, align 864// CHECK: %[[V4:.*]] = load <4 x half>, ptr @hv1, align 865// CHECK: %[[CONV6:.*]] = fpext <4 x half> %[[V4]] to <4 x float>66// CHECK: %[[V5:.*]] = load <4 x half>, ptr @hv0, align 867// CHECK: %[[CONV7:.*]] = fpext <4 x half> %[[V5]] to <4 x float>68// CHECK: %[[MUL:.*]] = fmul <4 x float> %[[CONV7]], %[[CONV6]]69// CHECK: %[[CONV8:.*]] = fptrunc <4 x float> %[[MUL]] to <4 x half>70// CHECK: store <4 x half> %[[CONV8]], ptr @hv0, align 871// CHECK: %[[V6:.*]] = load <4 x half>, ptr @hv1, align 872// CHECK: %[[CONV9:.*]] = fpext <4 x half> %[[V6]] to <4 x float>73// CHECK: %[[V7:.*]] = load <4 x half>, ptr @hv0, align 874// CHECK: %[[CONV10:.*]] = fpext <4 x half> %[[V7]] to <4 x float>75// CHECK: %[[DIV:.*]] = fdiv <4 x float> %[[CONV10]], %[[CONV9]]76// CHECK: %[[CONV11:.*]] = fptrunc <4 x float> %[[DIV]] to <4 x half>77// CHECK: store <4 x half> %[[CONV11]], ptr @hv0, align 878 79void testFP16Vec1() {80 hv0 += hv1;81 hv0 -= hv1;82 hv0 *= hv1;83 hv0 /= hv1;84}85 86// CHECK-LABEL: testFP16Vec287// CHECK: %[[CADDR:.*]] = alloca i32, align 488// CHECK: store i32 %[[C:.*]], ptr %[[CADDR]], align 489// CHECK: %[[V0:.*]] = load i32, ptr %[[CADDR]], align 490// CHECK: %[[TOBOOL:.*]] = icmp ne i32 %[[V0]], 091// CHECK: br i1 %[[TOBOOL]], label %{{.*}}, label %{{.*}}92//93// CHECK: %[[V1:.*]] = load <4 x half>, ptr @hv0, align 894// CHECK: br label %{{.*}}95//96// CHECK: %[[V2:.*]] = load <4 x half>, ptr @hv1, align 897// CHECK: br label %{{.*}}98//99// CHECK: %[[COND:.*]] = phi <4 x half> [ %[[V1]], %{{.*}} ], [ %[[V2]], %{{.*}} ]100// CHECK: store <4 x half> %[[COND]], ptr @hv0, align 8101 102void testFP16Vec2(int c) {103 hv0 = c ? hv0 : hv1;104}105 106// CHECK-LABEL: testFP16Vec3107// CHECK: %[[V0:.*]] = load <4 x half>, ptr @hv0, align 8108// CHECK: %[[CONV:.*]] = fpext <4 x half> %[[V0]] to <4 x float>109// CHECK: %[[V1:.*]] = load <4 x half>, ptr @hv1, align 8110// CHECK: %[[CONV1:.*]] = fpext <4 x half> %[[V1]] to <4 x float>111// CHECK: %[[CMP:.*]] = fcmp oeq <4 x float> %[[CONV]], %[[CONV1]]112// CHECK: %[[SEXT:.*]] = sext <4 x i1> %[[CMP]] to <4 x i32>113// CHECK: %[[CONV2:.*]] = trunc <4 x i32> %[[SEXT]] to <4 x i16>114// CHECK: store <4 x i16> %[[CONV2]], ptr @sv0, align 8115// CHECK: %[[V2:.*]] = load <4 x half>, ptr @hv0, align 8116// CHECK: %[[CONV3:.*]] = fpext <4 x half> %[[V2]] to <4 x float>117// CHECK: %[[V3:.*]] = load <4 x half>, ptr @hv1, align 8118// CHECK: %[[CONV4:.*]] = fpext <4 x half> %[[V3]] to <4 x float>119// CHECK: %[[CMP5:.*]] = fcmp une <4 x float> %[[CONV3]], %[[CONV4]]120// CHECK: %[[SEXT6:.*]] = sext <4 x i1> %[[CMP5]] to <4 x i32>121// CHECK: %[[CONV7:.*]] = trunc <4 x i32> %[[SEXT6]] to <4 x i16>122// CHECK: store <4 x i16> %[[CONV7]], ptr @sv0, align 8123// CHECK: %[[V4:.*]] = load <4 x half>, ptr @hv0, align 8124// CHECK: %[[CONV8:.*]] = fpext <4 x half> %[[V4]] to <4 x float>125// CHECK: %[[V5:.*]] = load <4 x half>, ptr @hv1, align 8126// CHECK: %[[CONV9:.*]] = fpext <4 x half> %[[V5]] to <4 x float>127// CHECK: %[[CMP10:.*]] = fcmp olt <4 x float> %[[CONV8]], %[[CONV9]]128// CHECK: %[[SEXT11:.*]] = sext <4 x i1> %[[CMP10]] to <4 x i32>129// CHECK: %[[CONV12:.*]] = trunc <4 x i32> %[[SEXT11]] to <4 x i16>130// CHECK: store <4 x i16> %[[CONV12]], ptr @sv0, align 8131// CHECK: %[[V6:.*]] = load <4 x half>, ptr @hv0, align 8132// CHECK: %[[CONV13:.*]] = fpext <4 x half> %[[V6]] to <4 x float>133// CHECK: %[[V7:.*]] = load <4 x half>, ptr @hv1, align 8134// CHECK: %[[CONV14:.*]] = fpext <4 x half> %[[V7]] to <4 x float>135// CHECK: %[[CMP15:.*]] = fcmp ogt <4 x float> %[[CONV13]], %[[CONV14]]136// CHECK: %[[SEXT16:.*]] = sext <4 x i1> %[[CMP15]] to <4 x i32>137// CHECK: %[[CONV17:.*]] = trunc <4 x i32> %[[SEXT16]] to <4 x i16>138// CHECK: store <4 x i16> %[[CONV17]], ptr @sv0, align 8139// CHECK: %[[V8:.*]] = load <4 x half>, ptr @hv0, align 8140// CHECK: %[[CONV18:.*]] = fpext <4 x half> %[[V8]] to <4 x float>141// CHECK: %[[V9:.*]] = load <4 x half>, ptr @hv1, align 8142// CHECK: %[[CONV19:.*]] = fpext <4 x half> %[[V9]] to <4 x float>143// CHECK: %[[CMP20:.*]] = fcmp ole <4 x float> %[[CONV18]], %[[CONV19]]144// CHECK: %[[SEXT21:.*]] = sext <4 x i1> %[[CMP20]] to <4 x i32>145// CHECK: %[[CONV22:.*]] = trunc <4 x i32> %[[SEXT21]] to <4 x i16>146// CHECK: store <4 x i16> %[[CONV22]], ptr @sv0, align 8147// CHECK: %[[V10:.*]] = load <4 x half>, ptr @hv0, align 8148// CHECK: %[[CONV23:.*]] = fpext <4 x half> %[[V10]] to <4 x float>149// CHECK: %[[V11:.*]] = load <4 x half>, ptr @hv1, align 8150// CHECK: %[[CONV24:.*]] = fpext <4 x half> %[[V11]] to <4 x float>151// CHECK: %[[CMP25:.*]] = fcmp oge <4 x float> %[[CONV23]], %[[CONV24]]152// CHECK: %[[SEXT26:.*]] = sext <4 x i1> %[[CMP25]] to <4 x i32>153// CHECK: %[[CONV27:.*]] = trunc <4 x i32> %[[SEXT26]] to <4 x i16>154// CHECK: store <4 x i16> %[[CONV27]], ptr @sv0, align 8155 156void testFP16Vec3() {157 sv0 = hv0 == hv1;158 sv0 = hv0 != hv1;159 sv0 = hv0 < hv1;160 sv0 = hv0 > hv1;161 sv0 = hv0 <= hv1;162 sv0 = hv0 >= hv1;163}164