50 lines · c
1// RUN: %clang -target mipsel-unknown-linux -S -o - -emit-llvm %s \2// RUN: | FileCheck %s3 4// This checks that the frontend will accept inline asm constraints5// c', 'l' and 'x'.6 7int main(void)8{9 // 'c': 16 bit address register for Mips16, GPR for all others10 // I am using 'c' to constrain both the target and one of the source11 // registers. We are looking for syntactical correctness.12 // CHECK: %{{[0-9]+}} = call i32 asm sideeffect "addi $0,$1,$2 \0A\09\09", "=c,c,I,~{$1}"(i32 %{{[0-9]+}}, i32 %{{[0-9]+}}) [[NUW:#[0-9]+]], !srcloc !{{[0-9]+}}13 int __s, __v = 17;14 int __t;15 __asm__ __volatile__(16 "addi %0,%1,%2 \n\t\t"17 : "=c" (__t)18 : "c" (__s), "I" (__v));19 20 // 'l': lo register21 // We are making it clear that destination register is lo with the22 // use of the 'l' constraint ("=l").23 // CHECK: %{{[0-9]+}} = call i32 asm sideeffect "mtlo $1 \0A\09\09", "=l,r,~{lo},~{$1}"(i32 %{{[0-9]+}}) [[NUW]], !srcloc !{{[0-9]+}}24 int i_temp = 44;25 int i_result;26 __asm__ __volatile__(27 "mtlo %1 \n\t\t"28 : "=l" (i_result)29 : "r" (i_temp)30 : "lo");31 32 // 'x': Combined lo/hi registers33 // We are specifying that destination registers are the hi/lo pair with the34 // use of the 'x' constraint ("=x").35 // CHECK: %{{[0-9]+}} = call i64 asm sideeffect "mthi $1 \0A\09\09mtlo $2 \0A\09\09", "=x,r,r,~{$1}"(i32 %{{[0-9]+}}, i32 %{{[0-9]+}}) [[NUW]], !srcloc !{{[0-9]+}}36 int i_hi = 3;37 int i_lo = 2;38 long long ll_result = 0;39 __asm__ __volatile__(40 "mthi %1 \n\t\t"41 "mtlo %2 \n\t\t"42 : "=x" (ll_result)43 : "r" (i_hi), "r" (i_lo)44 : );45 46 return 0;47}48 49// CHECK: attributes [[NUW]] = { nounwind }50