486 lines · c
1// RUN: %clang_cc1 -ffreestanding -fms-extensions -Wno-implicit-function-declaration \2// RUN: -triple x86_64--darwin -Oz -emit-llvm %s -o - \3// RUN: | FileCheck %s4// RUN: %clang_cc1 -ffreestanding -fms-extensions -Wno-implicit-function-declaration \5// RUN: -triple x86_64--linux -Oz -emit-llvm %s -o - \6// RUN: | FileCheck %s7// RUN: %clang_cc1 -ffreestanding -fms-extensions -Wno-implicit-function-declaration \8// RUN: -triple aarch64--darwin -Oz -emit-llvm %s -o - \9// RUN: | FileCheck %s --check-prefix=CHECK-ARM-ARM6410// RUN: %clang_cc1 -ffreestanding -fms-extensions -Wno-implicit-function-declaration \11// RUN: -triple aarch64--darwin -Oz -emit-llvm %s -o - \12// RUN: | FileCheck %s --check-prefix=CHECK-ARM13// RUN: %clang_cc1 -ffreestanding -fms-extensions -Wno-implicit-function-declaration \14// RUN: -triple armv7--darwin -Oz -emit-llvm %s -o - \15// RUN: | FileCheck %s --check-prefix=CHECK-ARM16 17// RUN: %clang_cc1 -x c++ -std=c++11 \18// RUN: -ffreestanding -fms-extensions -Wno-implicit-function-declaration \19// RUN: -triple x86_64--darwin -Oz -emit-llvm %s -o - \20// RUN: | FileCheck %s21// RUN: %clang_cc1 -x c++ -std=c++11 \22// RUN: -ffreestanding -fms-extensions -Wno-implicit-function-declaration \23// RUN: -triple x86_64--linux -Oz -emit-llvm %s -o - \24// RUN: | FileCheck %s25// RUN: %clang_cc1 -x c++ -std=c++11 \26// RUN: -ffreestanding -fms-extensions -Wno-implicit-function-declaration \27// RUN: -triple aarch64--darwin -Oz -emit-llvm %s -o - \28// RUN: | FileCheck %s --check-prefix=CHECK-ARM-ARM6429// RUN: %clang_cc1 -x c++ -std=c++11 \30// RUN: -ffreestanding -fms-extensions -Wno-implicit-function-declaration \31// RUN: -triple aarch64--darwin -Oz -emit-llvm %s -o - \32// RUN: | FileCheck %s --check-prefix=CHECK-ARM33// RUN: %clang_cc1 -x c++ -std=c++11 \34// RUN: -ffreestanding -fms-extensions -Wno-implicit-function-declaration \35// RUN: -triple armv7--darwin -Oz -emit-llvm %s -o - \36// RUN: | FileCheck %s --check-prefix=CHECK-ARM37 38// LP64 targets use 'long' as 'int' for MS intrinsics (-fms-extensions)39#ifdef __LP64__40#define LONG int41#else42#define LONG long43#endif44 45#ifdef __cplusplus46extern "C" {47#endif48 49unsigned char test_BitScanForward(unsigned LONG *Index, unsigned LONG Mask) {50 return _BitScanForward(Index, Mask);51}52// CHECK: define{{.*}}i8 @test_BitScanForward(ptr {{.*}}%Index, i32 {{[a-z_ ]*}}%Mask){{.*}}{53// CHECK: [[ISNOTZERO:%[a-z0-9._]+]] = icmp eq i32 %Mask, 054// CHECK: br i1 [[ISNOTZERO]], label %[[END_LABEL:[a-z0-9._]+]], label %[[ISNOTZERO_LABEL:[a-z0-9._]+]]55// CHECK: [[END_LABEL]]:56// CHECK: [[RESULT:%[a-z0-9._]+]] = phi i8 [ 0, %[[ISZERO_LABEL:[a-z0-9._]+]] ], [ 1, %[[ISNOTZERO_LABEL]] ]57// CHECK: ret i8 [[RESULT]]58// CHECK: [[ISNOTZERO_LABEL]]:59// CHECK: [[INDEX:%[0-9]+]] = tail call range(i32 0, 33) i32 @llvm.cttz.i32(i32 %Mask, i1 true)60// CHECK: store i32 [[INDEX]], ptr %Index, align 461// CHECK: br label %[[END_LABEL]]62 63unsigned char test_BitScanReverse(unsigned LONG *Index, unsigned LONG Mask) {64 return _BitScanReverse(Index, Mask);65}66// CHECK: define{{.*}}i8 @test_BitScanReverse(ptr {{.*}}%Index, i32 {{[a-z_ ]*}}%Mask){{.*}}{67// CHECK: [[ISNOTZERO:%[0-9]+]] = icmp eq i32 %Mask, 068// CHECK: br i1 [[ISNOTZERO]], label %[[END_LABEL:[a-z0-9._]+]], label %[[ISNOTZERO_LABEL:[a-z0-9._]+]]69// CHECK: [[END_LABEL]]:70// CHECK: [[RESULT:%[a-z0-9._]+]] = phi i8 [ 0, %[[ISZERO_LABEL:[a-z0-9._]+]] ], [ 1, %[[ISNOTZERO_LABEL]] ]71// CHECK: ret i8 [[RESULT]]72// CHECK: [[ISNOTZERO_LABEL]]:73// CHECK: [[REVINDEX:%[0-9]+]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 %Mask, i1 true)74// CHECK: [[INDEX:%[0-9]+]] = xor i32 [[REVINDEX]], 3175// CHECK: store i32 [[INDEX]], ptr %Index, align 476// CHECK: br label %[[END_LABEL]]77 78#if defined(__x86_64__)79unsigned char test_BitScanForward64(unsigned LONG *Index, unsigned __int64 Mask) {80 return _BitScanForward64(Index, Mask);81}82// CHECK: define{{.*}}i8 @test_BitScanForward64(ptr {{.*}}%Index, i64 {{[a-z_ ]*}}%Mask){{.*}}{83// CHECK: [[ISNOTZERO:%[a-z0-9._]+]] = icmp eq i64 %Mask, 084// CHECK: br i1 [[ISNOTZERO]], label %[[END_LABEL:[a-z0-9._]+]], label %[[ISNOTZERO_LABEL:[a-z0-9._]+]]85// CHECK: [[END_LABEL]]:86// CHECK: [[RESULT:%[a-z0-9._]+]] = phi i8 [ 0, %[[ISZERO_LABEL:[a-z0-9._]+]] ], [ 1, %[[ISNOTZERO_LABEL]] ]87// CHECK: ret i8 [[RESULT]]88// CHECK: [[ISNOTZERO_LABEL]]:89// CHECK: [[INDEX:%[0-9]+]] = tail call range(i64 0, 65) i64 @llvm.cttz.i64(i64 %Mask, i1 true)90// CHECK: [[TRUNC_INDEX:%[0-9]+]] = trunc nuw nsw i64 [[INDEX]] to i3291// CHECK: store i32 [[TRUNC_INDEX]], ptr %Index, align 492// CHECK: br label %[[END_LABEL]]93 94unsigned char test_BitScanReverse64(unsigned LONG *Index, unsigned __int64 Mask) {95 return _BitScanReverse64(Index, Mask);96}97// CHECK: define{{.*}}i8 @test_BitScanReverse64(ptr {{.*}}%Index, i64 {{[a-z_ ]*}}%Mask){{.*}}{98// CHECK: [[ISNOTZERO:%[0-9]+]] = icmp eq i64 %Mask, 099// CHECK: br i1 [[ISNOTZERO]], label %[[END_LABEL:[a-z0-9._]+]], label %[[ISNOTZERO_LABEL:[a-z0-9._]+]]100// CHECK: [[END_LABEL]]:101// CHECK: [[RESULT:%[a-z0-9._]+]] = phi i8 [ 0, %[[ISZERO_LABEL:[a-z0-9._]+]] ], [ 1, %[[ISNOTZERO_LABEL]] ]102// CHECK: ret i8 [[RESULT]]103// CHECK: [[ISNOTZERO_LABEL]]:104// CHECK: [[REVINDEX:%[0-9]+]] = tail call range(i64 0, 65) i64 @llvm.ctlz.i64(i64 %Mask, i1 true)105// CHECK: [[TRUNC_REVINDEX:%[0-9]+]] = trunc nuw nsw i64 [[REVINDEX]] to i32106// CHECK: [[INDEX:%[0-9]+]] = xor i32 [[TRUNC_REVINDEX]], 63107// CHECK: store i32 [[INDEX]], ptr %Index, align 4108// CHECK: br label %[[END_LABEL]]109#endif110 111LONG test_InterlockedExchange(LONG volatile *value, LONG mask) {112 return _InterlockedExchange(value, mask);113}114// CHECK: define{{.*}}i32 @test_InterlockedExchange(ptr{{.*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{115// CHECK: [[RESULT:%[0-9]+]] = atomicrmw xchg ptr %value, i32 %mask seq_cst, align 4116// CHECK: ret i32 [[RESULT:%[0-9]+]]117// CHECK: }118 119LONG test_InterlockedExchangeAdd(LONG volatile *value, LONG mask) {120 return _InterlockedExchangeAdd(value, mask);121}122// CHECK: define{{.*}}i32 @test_InterlockedExchangeAdd(ptr{{.*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{123// CHECK: [[RESULT:%[0-9]+]] = atomicrmw add ptr %value, i32 %mask seq_cst, align 4124// CHECK: ret i32 [[RESULT:%[0-9]+]]125// CHECK: }126 127LONG test_InterlockedExchangeSub(LONG volatile *value, LONG mask) {128 return _InterlockedExchangeSub(value, mask);129}130// CHECK: define{{.*}}i32 @test_InterlockedExchangeSub(ptr{{.*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{131// CHECK: [[RESULT:%[0-9]+]] = atomicrmw sub ptr %value, i32 %mask seq_cst, align 4132// CHECK: ret i32 [[RESULT:%[0-9]+]]133// CHECK: }134 135LONG test_InterlockedOr(LONG volatile *value, LONG mask) {136 return _InterlockedOr(value, mask);137}138// CHECK: define{{.*}}i32 @test_InterlockedOr(ptr{{.*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{139// CHECK: [[RESULT:%[0-9]+]] = atomicrmw or ptr %value, i32 %mask seq_cst, align 4140// CHECK: ret i32 [[RESULT:%[0-9]+]]141// CHECK: }142 143LONG test_InterlockedXor(LONG volatile *value, LONG mask) {144 return _InterlockedXor(value, mask);145}146// CHECK: define{{.*}}i32 @test_InterlockedXor(ptr{{.*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{147// CHECK: [[RESULT:%[0-9]+]] = atomicrmw xor ptr %value, i32 %mask seq_cst, align 4148// CHECK: ret i32 [[RESULT:%[0-9]+]]149// CHECK: }150 151LONG test_InterlockedAnd(LONG volatile *value, LONG mask) {152 return _InterlockedAnd(value, mask);153}154// CHECK: define{{.*}}i32 @test_InterlockedAnd(ptr{{.*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{155// CHECK: [[RESULT:%[0-9]+]] = atomicrmw and ptr %value, i32 %mask seq_cst, align 4156// CHECK: ret i32 [[RESULT:%[0-9]+]]157// CHECK: }158 159LONG test_InterlockedCompareExchange(LONG volatile *Destination, LONG Exchange, LONG Comperand) {160 return _InterlockedCompareExchange(Destination, Exchange, Comperand);161}162// CHECK: define{{.*}}i32 @test_InterlockedCompareExchange(ptr{{[a-z_ ]*}}%Destination, i32{{[a-z_ ]*}}%Exchange, i32{{[a-z_ ]*}}%Comperand){{.*}}{163// CHECK: [[TMP:%[0-9]+]] = cmpxchg volatile ptr %Destination, i32 %Comperand, i32 %Exchange seq_cst seq_cst, align 4164// CHECK: [[RESULT:%[0-9]+]] = extractvalue { i32, i1 } [[TMP]], 0165// CHECK: ret i32 [[RESULT]]166// CHECK: }167 168LONG test_InterlockedIncrement(LONG volatile *Addend) {169 return _InterlockedIncrement(Addend);170}171// CHECK: define{{.*}}i32 @test_InterlockedIncrement(ptr{{.*}}%Addend){{.*}}{172// CHECK: [[TMP:%[0-9]+]] = atomicrmw add ptr %Addend, i32 1 seq_cst, align 4173// CHECK: [[RESULT:%[0-9]+]] = add i32 [[TMP]], 1174// CHECK: ret i32 [[RESULT]]175// CHECK: }176 177LONG test_InterlockedDecrement(LONG volatile *Addend) {178 return _InterlockedDecrement(Addend);179}180// CHECK: define{{.*}}i32 @test_InterlockedDecrement(ptr{{.*}}%Addend){{.*}}{181// CHECK: [[TMP:%[0-9]+]] = atomicrmw sub ptr %Addend, i32 1 seq_cst, align 4182// CHECK: [[RESULT:%[0-9]+]] = add i32 [[TMP]], -1183// CHECK: ret i32 [[RESULT]]184// CHECK: }185 186unsigned short test__lzcnt16(unsigned short x) {187 return __lzcnt16(x);188}189// CHECK: i16 @test__lzcnt16190// CHECK: [[RESULT:%[0-9]+]] = tail call range(i16 0, 17) i16 @llvm.ctlz.i16(i16 %x, i1 false)191// CHECK: ret i16 [[RESULT]]192// CHECK: }193 194unsigned int test__lzcnt(unsigned int x) {195 return __lzcnt(x);196}197// CHECK: i32 @test__lzcnt198// CHECK: [[RESULT:%[0-9]+]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 %x, i1 false)199// CHECK: ret i32 [[RESULT]]200// CHECK: }201 202unsigned __int64 test__lzcnt64(unsigned __int64 x) {203 return __lzcnt64(x);204}205// CHECK: i64 @test__lzcnt64206// CHECK: [[RESULT:%[0-9]+]] = tail call range(i64 0, 65) i64 @llvm.ctlz.i64(i64 %x, i1 false)207// CHECK: ret i64 [[RESULT]]208// CHECK: }209 210unsigned short test__popcnt16(unsigned short x) {211 return __popcnt16(x);212}213// CHECK: i16 @test__popcnt16214// CHECK: [[RESULT:%[0-9]+]] = tail call range(i16 0, 17) i16 @llvm.ctpop.i16(i16 %x)215// CHECK: ret i16 [[RESULT]]216// CHECK: }217 218unsigned int test__popcnt(unsigned int x) {219 return __popcnt(x);220}221// CHECK: i32 @test__popcnt222// CHECK: [[RESULT:%[0-9]+]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 %x)223// CHECK: ret i32 [[RESULT]]224// CHECK: }225 226unsigned __int64 test__popcnt64(unsigned __int64 x) {227 return __popcnt64(x);228}229// CHECK: i64 @test__popcnt64230// CHECK: [[RESULT:%[0-9]+]] = tail call range(i64 0, 65) i64 @llvm.ctpop.i64(i64 %x)231// CHECK: ret i64 [[RESULT]]232// CHECK: }233 234#if defined(__aarch64__)235LONG test_InterlockedAdd(LONG volatile *Addend, LONG Value) {236 return _InterlockedAdd(Addend, Value);237}238 239// CHECK-ARM-ARM64: define{{.*}}i32 @test_InterlockedAdd(ptr{{.*}}%Addend, i32 noundef %Value) {{.*}} {240// CHECK-ARM-ARM64: %[[OLDVAL:[0-9]+]] = atomicrmw add ptr %Addend, i32 %Value seq_cst, align 4241// CHECK-ARM-ARM64: %[[NEWVAL:[0-9]+]] = add i32 %[[OLDVAL:[0-9]+]], %Value242// CHECK-ARM-ARM64: ret i32 %[[NEWVAL:[0-9]+]]243 244__int64 test_InterlockedAdd64(__int64 volatile *Addend, __int64 Value) {245 return _InterlockedAdd64(Addend, Value);246}247 248// CHECK-ARM-ARM64: define{{.*}}i64 @test_InterlockedAdd64(ptr{{.*}}%Addend, i64 noundef %Value) {{.*}} {249// CHECK-ARM-ARM64: %[[OLDVAL:[0-9]+]] = atomicrmw add ptr %Addend, i64 %Value seq_cst, align 8250// CHECK-ARM-ARM64: %[[NEWVAL:[0-9]+]] = add i64 %[[OLDVAL:[0-9]+]], %Value251// CHECK-ARM-ARM64: ret i64 %[[NEWVAL:[0-9]+]]252#endif253 254#if defined(__arm__) || defined(__aarch64__)255LONG test_InterlockedExchangeAdd_acq(LONG volatile *value, LONG mask) {256 return _InterlockedExchangeAdd_acq(value, mask);257}258// CHECK-ARM: define{{.*}}i32 @test_InterlockedExchangeAdd_acq(ptr{{.*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{259// CHECK-ARM: [[RESULT:%[0-9]+]] = atomicrmw add ptr %value, i32 %mask acquire, align 4260// CHECK-ARM: ret i32 [[RESULT:%[0-9]+]]261// CHECK-ARM: }262LONG test_InterlockedExchangeAdd_rel(LONG volatile *value, LONG mask) {263 return _InterlockedExchangeAdd_rel(value, mask);264}265// CHECK-ARM: define{{.*}}i32 @test_InterlockedExchangeAdd_rel(ptr{{.*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{266// CHECK-ARM: [[RESULT:%[0-9]+]] = atomicrmw add ptr %value, i32 %mask release, align 4267// CHECK-ARM: ret i32 [[RESULT:%[0-9]+]]268// CHECK-ARM: }269LONG test_InterlockedExchangeAdd_nf(LONG volatile *value, LONG mask) {270 return _InterlockedExchangeAdd_nf(value, mask);271}272// CHECK-ARM: define{{.*}}i32 @test_InterlockedExchangeAdd_nf(ptr{{.*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{273// CHECK-ARM: [[RESULT:%[0-9]+]] = atomicrmw add ptr %value, i32 %mask monotonic, align 4274// CHECK-ARM: ret i32 [[RESULT:%[0-9]+]]275// CHECK-ARM: }276 277LONG test_InterlockedExchange_acq(LONG volatile *value, LONG mask) {278 return _InterlockedExchange_acq(value, mask);279}280// CHECK-ARM: define{{.*}}i32 @test_InterlockedExchange_acq(ptr{{.*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{281// CHECK-ARM: [[RESULT:%[0-9]+]] = atomicrmw xchg ptr %value, i32 %mask acquire, align 4282// CHECK-ARM: ret i32 [[RESULT:%[0-9]+]]283// CHECK-ARM: }284LONG test_InterlockedExchange_rel(LONG volatile *value, LONG mask) {285 return _InterlockedExchange_rel(value, mask);286}287// CHECK-ARM: define{{.*}}i32 @test_InterlockedExchange_rel(ptr{{.*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{288// CHECK-ARM: [[RESULT:%[0-9]+]] = atomicrmw xchg ptr %value, i32 %mask release, align 4289// CHECK-ARM: ret i32 [[RESULT:%[0-9]+]]290// CHECK-ARM: }291LONG test_InterlockedExchange_nf(LONG volatile *value, LONG mask) {292 return _InterlockedExchange_nf(value, mask);293}294// CHECK-ARM: define{{.*}}i32 @test_InterlockedExchange_nf(ptr{{.*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{295// CHECK-ARM: [[RESULT:%[0-9]+]] = atomicrmw xchg ptr %value, i32 %mask monotonic, align 4296// CHECK-ARM: ret i32 [[RESULT:%[0-9]+]]297// CHECK-ARM: }298 299LONG test_InterlockedCompareExchange_acq(LONG volatile *Destination, LONG Exchange, LONG Comperand) {300 return _InterlockedCompareExchange_acq(Destination, Exchange, Comperand);301}302// CHECK-ARM: define{{.*}}i32 @test_InterlockedCompareExchange_acq(ptr{{.*}}%Destination, i32{{[a-z_ ]*}}%Exchange, i32{{[a-z_ ]*}}%Comperand){{.*}}{303// CHECK-ARM: [[TMP:%[0-9]+]] = cmpxchg volatile ptr %Destination, i32 %Comperand, i32 %Exchange acquire acquire, align 4304// CHECK-ARM: [[RESULT:%[0-9]+]] = extractvalue { i32, i1 } [[TMP]], 0305// CHECK-ARM: ret i32 [[RESULT]]306// CHECK-ARM: }307 308LONG test_InterlockedCompareExchange_rel(LONG volatile *Destination, LONG Exchange, LONG Comperand) {309 return _InterlockedCompareExchange_rel(Destination, Exchange, Comperand);310}311// CHECK-ARM: define{{.*}}i32 @test_InterlockedCompareExchange_rel(ptr{{.*}}%Destination, i32{{[a-z_ ]*}}%Exchange, i32{{[a-z_ ]*}}%Comperand){{.*}}{312// CHECK-ARM: [[TMP:%[0-9]+]] = cmpxchg volatile ptr %Destination, i32 %Comperand, i32 %Exchange release monotonic, align 4313// CHECK-ARM: [[RESULT:%[0-9]+]] = extractvalue { i32, i1 } [[TMP]], 0314// CHECK-ARM: ret i32 [[RESULT]]315// CHECK-ARM: }316 317LONG test_InterlockedCompareExchange_nf(LONG volatile *Destination, LONG Exchange, LONG Comperand) {318 return _InterlockedCompareExchange_nf(Destination, Exchange, Comperand);319}320// CHECK-ARM: define{{.*}}i32 @test_InterlockedCompareExchange_nf(ptr{{.*}}%Destination, i32{{[a-z_ ]*}}%Exchange, i32{{[a-z_ ]*}}%Comperand){{.*}}{321// CHECK-ARM: [[TMP:%[0-9]+]] = cmpxchg volatile ptr %Destination, i32 %Comperand, i32 %Exchange monotonic monotonic, align 4322// CHECK-ARM: [[RESULT:%[0-9]+]] = extractvalue { i32, i1 } [[TMP]], 0323// CHECK-ARM: ret i32 [[RESULT]]324// CHECK-ARM: }325 326LONG test_InterlockedOr_acq(LONG volatile *value, LONG mask) {327 return _InterlockedOr_acq(value, mask);328}329// CHECK-ARM: define{{.*}}i32 @test_InterlockedOr_acq(ptr{{.*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{330// CHECK-ARM: [[RESULT:%[0-9]+]] = atomicrmw or ptr %value, i32 %mask acquire, align 4331// CHECK-ARM: ret i32 [[RESULT:%[0-9]+]]332// CHECK-ARM: }333 334LONG test_InterlockedOr_rel(LONG volatile *value, LONG mask) {335 return _InterlockedOr_rel(value, mask);336}337// CHECK-ARM: define{{.*}}i32 @test_InterlockedOr_rel(ptr{{.*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{338// CHECK-ARM: [[RESULT:%[0-9]+]] = atomicrmw or ptr %value, i32 %mask release, align 4339// CHECK-ARM: ret i32 [[RESULT:%[0-9]+]]340// CHECK-ARM: }341 342LONG test_InterlockedOr_nf(LONG volatile *value, LONG mask) {343 return _InterlockedOr_nf(value, mask);344}345// CHECK-ARM: define{{.*}}i32 @test_InterlockedOr_nf(ptr{{.*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{346// CHECK-ARM: [[RESULT:%[0-9]+]] = atomicrmw or ptr %value, i32 %mask monotonic, align 4347// CHECK-ARM: ret i32 [[RESULT:%[0-9]+]]348// CHECK-ARM: }349 350LONG test_InterlockedXor_acq(LONG volatile *value, LONG mask) {351 return _InterlockedXor_acq(value, mask);352}353// CHECK-ARM: define{{.*}}i32 @test_InterlockedXor_acq(ptr{{.*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{354// CHECK-ARM: [[RESULT:%[0-9]+]] = atomicrmw xor ptr %value, i32 %mask acquire, align 4355// CHECK-ARM: ret i32 [[RESULT:%[0-9]+]]356// CHECK-ARM: }357 358LONG test_InterlockedXor_rel(LONG volatile *value, LONG mask) {359 return _InterlockedXor_rel(value, mask);360}361// CHECK-ARM: define{{.*}}i32 @test_InterlockedXor_rel(ptr{{.*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{362// CHECK-ARM: [[RESULT:%[0-9]+]] = atomicrmw xor ptr %value, i32 %mask release, align 4363// CHECK-ARM: ret i32 [[RESULT:%[0-9]+]]364// CHECK-ARM: }365 366LONG test_InterlockedXor_nf(LONG volatile *value, LONG mask) {367 return _InterlockedXor_nf(value, mask);368}369// CHECK-ARM: define{{.*}}i32 @test_InterlockedXor_nf(ptr{{.*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{370// CHECK-ARM: [[RESULT:%[0-9]+]] = atomicrmw xor ptr %value, i32 %mask monotonic, align 4371// CHECK-ARM: ret i32 [[RESULT:%[0-9]+]]372// CHECK-ARM: }373 374LONG test_InterlockedAnd_acq(LONG volatile *value, LONG mask) {375 return _InterlockedAnd_acq(value, mask);376}377// CHECK-ARM: define{{.*}}i32 @test_InterlockedAnd_acq(ptr{{.*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{378// CHECK-ARM: [[RESULT:%[0-9]+]] = atomicrmw and ptr %value, i32 %mask acquire, align 4379// CHECK-ARM: ret i32 [[RESULT:%[0-9]+]]380// CHECK-ARM: }381 382LONG test_InterlockedAnd_rel(LONG volatile *value, LONG mask) {383 return _InterlockedAnd_rel(value, mask);384}385// CHECK-ARM: define{{.*}}i32 @test_InterlockedAnd_rel(ptr{{.*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{386// CHECK-ARM: [[RESULT:%[0-9]+]] = atomicrmw and ptr %value, i32 %mask release, align 4387// CHECK-ARM: ret i32 [[RESULT:%[0-9]+]]388// CHECK-ARM: }389 390LONG test_InterlockedAnd_nf(LONG volatile *value, LONG mask) {391 return _InterlockedAnd_nf(value, mask);392}393// CHECK-ARM: define{{.*}}i32 @test_InterlockedAnd_nf(ptr{{.*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{394// CHECK-ARM: [[RESULT:%[0-9]+]] = atomicrmw and ptr %value, i32 %mask monotonic, align 4395// CHECK-ARM: ret i32 [[RESULT:%[0-9]+]]396// CHECK-ARM: }397 398 399LONG test_InterlockedIncrement_acq(LONG volatile *Addend) {400 return _InterlockedIncrement_acq(Addend);401}402// CHECK-ARM: define{{.*}}i32 @test_InterlockedIncrement_acq(ptr{{.*}}%Addend){{.*}}{403// CHECK-ARM: [[TMP:%[0-9]+]] = atomicrmw add ptr %Addend, i32 1 acquire, align 4404// CHECK-ARM: [[RESULT:%[0-9]+]] = add i32 [[TMP]], 1405// CHECK-ARM: ret i32 [[RESULT]]406// CHECK-ARM: }407 408LONG test_InterlockedIncrement_rel(LONG volatile *Addend) {409 return _InterlockedIncrement_rel(Addend);410}411// CHECK-ARM: define{{.*}}i32 @test_InterlockedIncrement_rel(ptr{{.*}}%Addend){{.*}}{412// CHECK-ARM: [[TMP:%[0-9]+]] = atomicrmw add ptr %Addend, i32 1 release, align 4413// CHECK-ARM: [[RESULT:%[0-9]+]] = add i32 [[TMP]], 1414// CHECK-ARM: ret i32 [[RESULT]]415// CHECK-ARM: }416 417LONG test_InterlockedIncrement_nf(LONG volatile *Addend) {418 return _InterlockedIncrement_nf(Addend);419}420// CHECK-ARM: define{{.*}}i32 @test_InterlockedIncrement_nf(ptr{{.*}}%Addend){{.*}}{421// CHECK-ARM: [[TMP:%[0-9]+]] = atomicrmw add ptr %Addend, i32 1 monotonic, align 4422// CHECK-ARM: [[RESULT:%[0-9]+]] = add i32 [[TMP]], 1423// CHECK-ARM: ret i32 [[RESULT]]424// CHECK-ARM: }425 426LONG test_InterlockedDecrement_acq(LONG volatile *Addend) {427 return _InterlockedDecrement_acq(Addend);428}429// CHECK-ARM: define{{.*}}i32 @test_InterlockedDecrement_acq(ptr{{.*}}%Addend){{.*}}{430// CHECK-ARM: [[TMP:%[0-9]+]] = atomicrmw sub ptr %Addend, i32 1 acquire, align 4431// CHECK-ARM: [[RESULT:%[0-9]+]] = add i32 [[TMP]], -1432// CHECK-ARM: ret i32 [[RESULT]]433// CHECK-ARM: }434 435LONG test_InterlockedDecrement_rel(LONG volatile *Addend) {436 return _InterlockedDecrement_rel(Addend);437}438// CHECK-ARM: define{{.*}}i32 @test_InterlockedDecrement_rel(ptr{{.*}}%Addend){{.*}}{439// CHECK-ARM: [[TMP:%[0-9]+]] = atomicrmw sub ptr %Addend, i32 1 release, align 4440// CHECK-ARM: [[RESULT:%[0-9]+]] = add i32 [[TMP]], -1441// CHECK-ARM: ret i32 [[RESULT]]442// CHECK-ARM: }443 444LONG test_InterlockedDecrement_nf(LONG volatile *Addend) {445 return _InterlockedDecrement_nf(Addend);446}447// CHECK-ARM: define{{.*}}i32 @test_InterlockedDecrement_nf(ptr{{.*}}%Addend){{.*}}{448// CHECK-ARM: [[TMP:%[0-9]+]] = atomicrmw sub ptr %Addend, i32 1 monotonic, align 4449// CHECK-ARM: [[RESULT:%[0-9]+]] = add i32 [[TMP]], -1450// CHECK-ARM: ret i32 [[RESULT]]451// CHECK-ARM: }452#endif453 454#ifdef __cplusplus455}456#endif457 458 459// Test constexpr handling.460#if defined(__cplusplus) && (__cplusplus >= 201103L)461 462char popcnt16_0[__popcnt16(0x0000) == 0 ? 1 : -1];463char popcnt16_1[__popcnt16(0x10F0) == 5 ? 1 : -1];464 465char popcnt_0[__popcnt(0x00000000) == 0 ? 1 : -1];466char popcnt_1[__popcnt(0x100000F0) == 5 ? 1 : -1];467 468char popcnt64_0[__popcnt64(0x0000000000000000ULL) == 0 ? 1 : -1];469char popcnt64_1[__popcnt64(0xF00000F000000001ULL) == 9 ? 1 : -1];470 471#define BITSIZE(x) (sizeof(x) * 8)472char lzcnt16_0[__lzcnt16(1) == BITSIZE(short) - 1 ? 1 : -1];473char lzcnt16_1[__lzcnt16(1 << (BITSIZE(short) - 1)) == 0 ? 1 : -1];474char lzcnt16_2[__lzcnt16(0) == BITSIZE(short) ? 1 : -1];475 476char lzcnt_0[__lzcnt(1) == BITSIZE(int) - 1 ? 1 : -1];477char lzcnt_1[__lzcnt(1 << (BITSIZE(int) - 1)) == 0 ? 1 : -1];478char lzcnt_2[__lzcnt(0) == BITSIZE(int) ? 1 : -1];479 480char lzcnt64_0[__lzcnt64(1ULL) == BITSIZE(__int64) - 1 ? 1 : -1];481char lzcnt64_1[__lzcnt64(1ULL << (BITSIZE(__int64) - 1)) == 0 ? 1 : -1];482char lzcnt64_2[__lzcnt64(0ULL) == BITSIZE(__int64) ? 1 : -1];483#undef BITSIZE484 485#endif486