275 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 52// RUN: %clang_cc1 %s -emit-llvm -o - -triple=amdgcn-amd-amdhsa -ffreestanding \3// RUN: -fvisibility=hidden | FileCheck --check-prefixes=AMDGCN,AMDGCN_CL_DEF %s4// RUN: %clang_cc1 %s -emit-llvm -o - -triple=amdgcn-amd-amdhsa -ffreestanding \5// RUN: -cl-std=CL2.0 -fvisibility=hidden | FileCheck --check-prefixes=AMDGCN,AMDGCN_CL_20 %s6// RUN: %clang_cc1 %s -emit-llvm -o - -triple=spirv64-unknown-unknown -ffreestanding \7// RUN: -fvisibility=hidden | FileCheck --check-prefix=SPIRV %s8// RUN: %clang_cc1 %s -emit-llvm -o - -triple=x86_64-unknown-linux-gnu -ffreestanding \9// RUN: -fvisibility=hidden | FileCheck --check-prefix=X86_64 %s10 11// AMDGCN-LABEL: define hidden void @fe1a(12// AMDGCN-SAME: ) #[[ATTR0:[0-9]+]] {13// AMDGCN-NEXT: [[ENTRY:.*:]]14// AMDGCN-NEXT: fence syncscope("workgroup") release15// AMDGCN-NEXT: ret void16//17// SPIRV-LABEL: define hidden spir_func void @fe1a(18// SPIRV-SAME: ) #[[ATTR0:[0-9]+]] {19// SPIRV-NEXT: [[ENTRY:.*:]]20// SPIRV-NEXT: fence syncscope("workgroup") release21// SPIRV-NEXT: ret void22//23// X86_64-LABEL: define hidden void @fe1a(24// X86_64-SAME: ) #[[ATTR0:[0-9]+]] {25// X86_64-NEXT: [[ENTRY:.*:]]26// X86_64-NEXT: fence release27// X86_64-NEXT: ret void28//29void fe1a() {30 __scoped_atomic_thread_fence(__ATOMIC_RELEASE, __MEMORY_SCOPE_WRKGRP);31}32 33// AMDGCN-LABEL: define hidden void @fe1b(34// AMDGCN-SAME: i32 noundef [[ORD:%.*]]) #[[ATTR0]] {35// AMDGCN-NEXT: [[ENTRY:.*:]]36// AMDGCN-NEXT: [[ORD_ADDR:%.*]] = alloca i32, align 4, addrspace(5)37// AMDGCN-NEXT: [[ORD_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ORD_ADDR]] to ptr38// AMDGCN-NEXT: store i32 [[ORD]], ptr [[ORD_ADDR_ASCAST]], align 439// AMDGCN-NEXT: [[TMP0:%.*]] = load i32, ptr [[ORD_ADDR_ASCAST]], align 440// AMDGCN-NEXT: switch i32 [[TMP0]], label %[[ATOMIC_SCOPE_CONTINUE:.*]] [41// AMDGCN-NEXT: i32 1, label %[[ACQUIRE:.*]]42// AMDGCN-NEXT: i32 2, label %[[ACQUIRE]]43// AMDGCN-NEXT: i32 3, label %[[RELEASE:.*]]44// AMDGCN-NEXT: i32 4, label %[[ACQREL:.*]]45// AMDGCN-NEXT: i32 5, label %[[SEQCST:.*]]46// AMDGCN-NEXT: ]47// AMDGCN: [[ATOMIC_SCOPE_CONTINUE]]:48// AMDGCN-NEXT: ret void49// AMDGCN: [[ACQUIRE]]:50// AMDGCN-NEXT: fence syncscope("workgroup") acquire51// AMDGCN-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]52// AMDGCN: [[RELEASE]]:53// AMDGCN-NEXT: fence syncscope("workgroup") release54// AMDGCN-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]55// AMDGCN: [[ACQREL]]:56// AMDGCN-NEXT: fence syncscope("workgroup") acq_rel57// AMDGCN-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]58// AMDGCN: [[SEQCST]]:59// AMDGCN-NEXT: fence syncscope("workgroup") seq_cst60// AMDGCN-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]61//62// SPIRV-LABEL: define hidden spir_func void @fe1b(63// SPIRV-SAME: i32 noundef [[ORD:%.*]]) #[[ATTR0]] {64// SPIRV-NEXT: [[ENTRY:.*:]]65// SPIRV-NEXT: [[ORD_ADDR:%.*]] = alloca i32, align 466// SPIRV-NEXT: store i32 [[ORD]], ptr [[ORD_ADDR]], align 467// SPIRV-NEXT: [[TMP0:%.*]] = load i32, ptr [[ORD_ADDR]], align 468// SPIRV-NEXT: switch i32 [[TMP0]], label %[[ATOMIC_SCOPE_CONTINUE:.*]] [69// SPIRV-NEXT: i32 1, label %[[ACQUIRE:.*]]70// SPIRV-NEXT: i32 2, label %[[ACQUIRE]]71// SPIRV-NEXT: i32 3, label %[[RELEASE:.*]]72// SPIRV-NEXT: i32 4, label %[[ACQREL:.*]]73// SPIRV-NEXT: i32 5, label %[[SEQCST:.*]]74// SPIRV-NEXT: ]75// SPIRV: [[ATOMIC_SCOPE_CONTINUE]]:76// SPIRV-NEXT: ret void77// SPIRV: [[ACQUIRE]]:78// SPIRV-NEXT: fence syncscope("workgroup") acquire79// SPIRV-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]80// SPIRV: [[RELEASE]]:81// SPIRV-NEXT: fence syncscope("workgroup") release82// SPIRV-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]83// SPIRV: [[ACQREL]]:84// SPIRV-NEXT: fence syncscope("workgroup") acq_rel85// SPIRV-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]86// SPIRV: [[SEQCST]]:87// SPIRV-NEXT: fence syncscope("workgroup") seq_cst88// SPIRV-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]89//90// X86_64-LABEL: define hidden void @fe1b(91// X86_64-SAME: i32 noundef [[ORD:%.*]]) #[[ATTR0]] {92// X86_64-NEXT: [[ENTRY:.*:]]93// X86_64-NEXT: [[ORD_ADDR:%.*]] = alloca i32, align 494// X86_64-NEXT: store i32 [[ORD]], ptr [[ORD_ADDR]], align 495// X86_64-NEXT: [[TMP0:%.*]] = load i32, ptr [[ORD_ADDR]], align 496// X86_64-NEXT: switch i32 [[TMP0]], label %[[ATOMIC_SCOPE_CONTINUE:.*]] [97// X86_64-NEXT: i32 1, label %[[ACQUIRE:.*]]98// X86_64-NEXT: i32 2, label %[[ACQUIRE]]99// X86_64-NEXT: i32 3, label %[[RELEASE:.*]]100// X86_64-NEXT: i32 4, label %[[ACQREL:.*]]101// X86_64-NEXT: i32 5, label %[[SEQCST:.*]]102// X86_64-NEXT: ]103// X86_64: [[ATOMIC_SCOPE_CONTINUE]]:104// X86_64-NEXT: ret void105// X86_64: [[ACQUIRE]]:106// X86_64-NEXT: fence acquire107// X86_64-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]108// X86_64: [[RELEASE]]:109// X86_64-NEXT: fence release110// X86_64-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]111// X86_64: [[ACQREL]]:112// X86_64-NEXT: fence acq_rel113// X86_64-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]114// X86_64: [[SEQCST]]:115// X86_64-NEXT: fence seq_cst116// X86_64-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]117//118void fe1b(int ord) {119 __scoped_atomic_thread_fence(ord, __MEMORY_SCOPE_WRKGRP);120}121 122// AMDGCN-LABEL: define hidden void @fe1c(123// AMDGCN-SAME: i32 noundef [[SCOPE:%.*]]) #[[ATTR0]] {124// AMDGCN-NEXT: [[ENTRY:.*:]]125// AMDGCN-NEXT: [[SCOPE_ADDR:%.*]] = alloca i32, align 4, addrspace(5)126// AMDGCN-NEXT: [[SCOPE_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SCOPE_ADDR]] to ptr127// AMDGCN-NEXT: store i32 [[SCOPE]], ptr [[SCOPE_ADDR_ASCAST]], align 4128// AMDGCN-NEXT: [[TMP0:%.*]] = load i32, ptr [[SCOPE_ADDR_ASCAST]], align 4129// AMDGCN-NEXT: switch i32 [[TMP0]], label %[[ATOMIC_SCOPE_CONTINUE:.*]] [130// AMDGCN-NEXT: i32 0, label %[[SYSTEM_SCOPE:.*]]131// AMDGCN-NEXT: i32 1, label %[[DEVICE_SCOPE:.*]]132// AMDGCN-NEXT: i32 2, label %[[WORKGROUP_SCOPE:.*]]133// AMDGCN-NEXT: i32 5, label %[[CLUSTER_SCOPE:.*]]134// AMDGCN-NEXT: i32 3, label %[[WAVEFRONT_SCOPE:.*]]135// AMDGCN-NEXT: i32 4, label %[[SINGLE_SCOPE:.*]]136// AMDGCN-NEXT: ]137// AMDGCN: [[ATOMIC_SCOPE_CONTINUE]]:138// AMDGCN-NEXT: ret void139// AMDGCN: [[SYSTEM_SCOPE]]:140// AMDGCN-NEXT: fence release141// AMDGCN-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]142// AMDGCN: [[DEVICE_SCOPE]]:143// AMDGCN-NEXT: fence syncscope("agent") release144// AMDGCN-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]145// AMDGCN: [[WORKGROUP_SCOPE]]:146// AMDGCN-NEXT: fence syncscope("workgroup") release147// AMDGCN-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]148// AMDGCN: [[CLUSTER_SCOPE]]:149// AMDGCN-NEXT: fence syncscope("cluster") release150// AMDGCN-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]151// AMDGCN: [[WAVEFRONT_SCOPE]]:152// AMDGCN-NEXT: fence syncscope("wavefront") release153// AMDGCN-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]154// AMDGCN: [[SINGLE_SCOPE]]:155// AMDGCN-NEXT: fence syncscope("singlethread") release156// AMDGCN-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]157//158// SPIRV-LABEL: define hidden spir_func void @fe1c(159// SPIRV-SAME: i32 noundef [[SCOPE:%.*]]) #[[ATTR0]] {160// SPIRV-NEXT: [[ENTRY:.*:]]161// SPIRV-NEXT: [[SCOPE_ADDR:%.*]] = alloca i32, align 4162// SPIRV-NEXT: store i32 [[SCOPE]], ptr [[SCOPE_ADDR]], align 4163// SPIRV-NEXT: [[TMP0:%.*]] = load i32, ptr [[SCOPE_ADDR]], align 4164// SPIRV-NEXT: switch i32 [[TMP0]], label %[[ATOMIC_SCOPE_CONTINUE:.*]] [165// SPIRV-NEXT: i32 0, label %[[SYSTEM_SCOPE:.*]]166// SPIRV-NEXT: i32 1, label %[[DEVICE_SCOPE:.*]]167// SPIRV-NEXT: i32 2, label %[[WORKGROUP_SCOPE:.*]]168// SPIRV-NEXT: i32 5, label %[[CLUSTER_SCOPE:.*]]169// SPIRV-NEXT: i32 3, label %[[WAVEFRONT_SCOPE:.*]]170// SPIRV-NEXT: i32 4, label %[[SINGLE_SCOPE:.*]]171// SPIRV-NEXT: ]172// SPIRV: [[ATOMIC_SCOPE_CONTINUE]]:173// SPIRV-NEXT: ret void174// SPIRV: [[SYSTEM_SCOPE]]:175// SPIRV-NEXT: fence release176// SPIRV-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]177// SPIRV: [[DEVICE_SCOPE]]:178// SPIRV-NEXT: fence syncscope("device") release179// SPIRV-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]180// SPIRV: [[WORKGROUP_SCOPE]]:181// SPIRV-NEXT: fence syncscope("workgroup") release182// SPIRV-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]183// SPIRV: [[CLUSTER_SCOPE]]:184// SPIRV-NEXT: fence syncscope("workgroup") release185// SPIRV-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]186// SPIRV: [[WAVEFRONT_SCOPE]]:187// SPIRV-NEXT: fence syncscope("subgroup") release188// SPIRV-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]189// SPIRV: [[SINGLE_SCOPE]]:190// SPIRV-NEXT: fence syncscope("singlethread") release191// SPIRV-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]192//193// X86_64-LABEL: define hidden void @fe1c(194// X86_64-SAME: i32 noundef [[SCOPE:%.*]]) #[[ATTR0]] {195// X86_64-NEXT: [[ENTRY:.*:]]196// X86_64-NEXT: [[SCOPE_ADDR:%.*]] = alloca i32, align 4197// X86_64-NEXT: store i32 [[SCOPE]], ptr [[SCOPE_ADDR]], align 4198// X86_64-NEXT: [[TMP0:%.*]] = load i32, ptr [[SCOPE_ADDR]], align 4199// X86_64-NEXT: switch i32 [[TMP0]], label %[[ATOMIC_SCOPE_CONTINUE:.*]] [200// X86_64-NEXT: i32 0, label %[[SYSTEM_SCOPE:.*]]201// X86_64-NEXT: i32 1, label %[[DEVICE_SCOPE:.*]]202// X86_64-NEXT: i32 2, label %[[WORKGROUP_SCOPE:.*]]203// X86_64-NEXT: i32 5, label %[[CLUSTER_SCOPE:.*]]204// X86_64-NEXT: i32 3, label %[[WAVEFRONT_SCOPE:.*]]205// X86_64-NEXT: i32 4, label %[[SINGLE_SCOPE:.*]]206// X86_64-NEXT: ]207// X86_64: [[ATOMIC_SCOPE_CONTINUE]]:208// X86_64-NEXT: ret void209// X86_64: [[SYSTEM_SCOPE]]:210// X86_64-NEXT: fence release211// X86_64-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]212// X86_64: [[DEVICE_SCOPE]]:213// X86_64-NEXT: fence release214// X86_64-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]215// X86_64: [[WORKGROUP_SCOPE]]:216// X86_64-NEXT: fence release217// X86_64-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]218// X86_64: [[CLUSTER_SCOPE]]:219// X86_64-NEXT: fence release220// X86_64-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]221// X86_64: [[WAVEFRONT_SCOPE]]:222// X86_64-NEXT: fence release223// X86_64-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]224// X86_64: [[SINGLE_SCOPE]]:225// X86_64-NEXT: fence release226// X86_64-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]227//228void fe1c(int scope) {229 __scoped_atomic_thread_fence(__ATOMIC_RELEASE, scope);230}231 232// AMDGCN-LABEL: define hidden void @fe2a(233// AMDGCN-SAME: ) #[[ATTR0]] {234// AMDGCN-NEXT: [[ENTRY:.*:]]235// AMDGCN-NEXT: ret void236//237// SPIRV-LABEL: define hidden spir_func void @fe2a(238// SPIRV-SAME: ) #[[ATTR0]] {239// SPIRV-NEXT: [[ENTRY:.*:]]240// SPIRV-NEXT: ret void241//242// X86_64-LABEL: define hidden void @fe2a(243// X86_64-SAME: ) #[[ATTR0]] {244// X86_64-NEXT: [[ENTRY:.*:]]245// X86_64-NEXT: ret void246//247void fe2a() {248 __scoped_atomic_thread_fence(999, __MEMORY_SCOPE_SYSTEM);249}250 251// AMDGCN-LABEL: define hidden void @fe2b(252// AMDGCN-SAME: ) #[[ATTR0]] {253// AMDGCN-NEXT: [[ENTRY:.*:]]254// AMDGCN-NEXT: fence release255// AMDGCN-NEXT: ret void256//257// SPIRV-LABEL: define hidden spir_func void @fe2b(258// SPIRV-SAME: ) #[[ATTR0]] {259// SPIRV-NEXT: [[ENTRY:.*:]]260// SPIRV-NEXT: fence release261// SPIRV-NEXT: ret void262//263// X86_64-LABEL: define hidden void @fe2b(264// X86_64-SAME: ) #[[ATTR0]] {265// X86_64-NEXT: [[ENTRY:.*:]]266// X86_64-NEXT: fence release267// X86_64-NEXT: ret void268//269void fe2b() {270 __scoped_atomic_thread_fence(__ATOMIC_RELEASE, 999);271}272//// NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:273// AMDGCN_CL_20: {{.*}}274// AMDGCN_CL_DEF: {{.*}}275