224 lines · cpp
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py2// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve \3// RUN: -disable-O0-optnone \4// RUN: -emit-llvm -o - %s | opt -S -passes=sroa | FileCheck %s5 6// REQUIRES: aarch64-registered-target7 8#include <arm_sve.h>9 10// CHECK-LABEL: @_Z9cond_boolu10__SVBool_tS_(11// CHECK-NEXT: entry:12// CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 16 x i1> [[A:%.*]], [[B:%.*]]13// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 16 x i1> [[CMP]], <vscale x 16 x i1> [[A]], <vscale x 16 x i1> [[B]]14// CHECK-NEXT: ret <vscale x 16 x i1> [[VECTOR_SELECT]]15//16svbool_t cond_bool(svbool_t a, svbool_t b) {17 return a < b ? a : b;18}19 20// CHECK-LABEL: @_Z7cond_i8u10__SVInt8_tS_(21// CHECK-NEXT: entry:22// CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 16 x i8> [[A:%.*]], [[B:%.*]]23// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 16 x i1> [[CMP]] to <vscale x 16 x i8>24// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 16 x i8> [[CONV]], zeroinitializer25// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 16 x i1> [[VECTOR_COND]], <vscale x 16 x i8> [[A]], <vscale x 16 x i8> [[B]]26// CHECK-NEXT: ret <vscale x 16 x i8> [[VECTOR_SELECT]]27//28svint8_t cond_i8(svint8_t a, svint8_t b) {29 return a < b ? a : b;30}31 32// CHECK-LABEL: @_Z7cond_u8u11__SVUint8_tS_(33// CHECK-NEXT: entry:34// CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 16 x i8> [[A:%.*]], [[B:%.*]]35// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 16 x i1> [[CMP]] to <vscale x 16 x i8>36// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 16 x i8> [[CONV]], zeroinitializer37// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 16 x i1> [[VECTOR_COND]], <vscale x 16 x i8> [[A]], <vscale x 16 x i8> [[B]]38// CHECK-NEXT: ret <vscale x 16 x i8> [[VECTOR_SELECT]]39//40svuint8_t cond_u8(svuint8_t a, svuint8_t b) {41 return a < b ? a : b;42}43 44// CHECK-LABEL: @_Z8cond_i16u11__SVInt16_tS_(45// CHECK-NEXT: entry:46// CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 8 x i16> [[A:%.*]], [[B:%.*]]47// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 8 x i1> [[CMP]] to <vscale x 8 x i16>48// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 8 x i16> [[CONV]], zeroinitializer49// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 8 x i1> [[VECTOR_COND]], <vscale x 8 x i16> [[A]], <vscale x 8 x i16> [[B]]50// CHECK-NEXT: ret <vscale x 8 x i16> [[VECTOR_SELECT]]51//52svint16_t cond_i16(svint16_t a, svint16_t b) {53 return a < b ? a : b;54}55 56// CHECK-LABEL: @_Z8cond_u16u12__SVUint16_tS_(57// CHECK-NEXT: entry:58// CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 8 x i16> [[A:%.*]], [[B:%.*]]59// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 8 x i1> [[CMP]] to <vscale x 8 x i16>60// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 8 x i16> [[CONV]], zeroinitializer61// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 8 x i1> [[VECTOR_COND]], <vscale x 8 x i16> [[A]], <vscale x 8 x i16> [[B]]62// CHECK-NEXT: ret <vscale x 8 x i16> [[VECTOR_SELECT]]63//64svuint16_t cond_u16(svuint16_t a, svuint16_t b) {65 return a < b ? a : b;66}67 68// CHECK-LABEL: @_Z8cond_i32u11__SVInt32_tS_(69// CHECK-NEXT: entry:70// CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 4 x i32> [[A:%.*]], [[B:%.*]]71// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 4 x i1> [[CMP]] to <vscale x 4 x i32>72// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 4 x i32> [[CONV]], zeroinitializer73// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 4 x i1> [[VECTOR_COND]], <vscale x 4 x i32> [[A]], <vscale x 4 x i32> [[B]]74// CHECK-NEXT: ret <vscale x 4 x i32> [[VECTOR_SELECT]]75//76svint32_t cond_i32(svint32_t a, svint32_t b) {77 return a < b ? a : b;78}79 80// CHECK-LABEL: @_Z8cond_u32u12__SVUint32_tS_(81// CHECK-NEXT: entry:82// CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 4 x i32> [[A:%.*]], [[B:%.*]]83// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 4 x i1> [[CMP]] to <vscale x 4 x i32>84// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 4 x i32> [[CONV]], zeroinitializer85// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 4 x i1> [[VECTOR_COND]], <vscale x 4 x i32> [[A]], <vscale x 4 x i32> [[B]]86// CHECK-NEXT: ret <vscale x 4 x i32> [[VECTOR_SELECT]]87//88svuint32_t cond_u32(svuint32_t a, svuint32_t b) {89 return a < b ? a : b;90}91 92// CHECK-LABEL: @_Z8cond_i64u11__SVInt64_tS_(93// CHECK-NEXT: entry:94// CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 2 x i64> [[A:%.*]], [[B:%.*]]95// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 2 x i1> [[CMP]] to <vscale x 2 x i64>96// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 2 x i64> [[CONV]], zeroinitializer97// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 2 x i1> [[VECTOR_COND]], <vscale x 2 x i64> [[A]], <vscale x 2 x i64> [[B]]98// CHECK-NEXT: ret <vscale x 2 x i64> [[VECTOR_SELECT]]99//100svint64_t cond_i64(svint64_t a, svint64_t b) {101 return a < b ? a : b;102}103 104// CHECK-LABEL: @_Z8cond_u64u12__SVUint64_tS_(105// CHECK-NEXT: entry:106// CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 2 x i64> [[A:%.*]], [[B:%.*]]107// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 2 x i1> [[CMP]] to <vscale x 2 x i64>108// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 2 x i64> [[CONV]], zeroinitializer109// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 2 x i1> [[VECTOR_COND]], <vscale x 2 x i64> [[A]], <vscale x 2 x i64> [[B]]110// CHECK-NEXT: ret <vscale x 2 x i64> [[VECTOR_SELECT]]111//112svuint64_t cond_u64(svuint64_t a, svuint64_t b) {113 return a < b ? a : b;114}115 116// CHECK-LABEL: @_Z8cond_f16u13__SVFloat16_tS_(117// CHECK-NEXT: entry:118// CHECK-NEXT: [[CMP:%.*]] = fcmp olt <vscale x 8 x half> [[A:%.*]], [[B:%.*]]119// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 8 x i1> [[CMP]] to <vscale x 8 x i16>120// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 8 x i16> [[CONV]], zeroinitializer121// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 8 x i1> [[VECTOR_COND]], <vscale x 8 x half> [[A]], <vscale x 8 x half> [[B]]122// CHECK-NEXT: ret <vscale x 8 x half> [[VECTOR_SELECT]]123//124svfloat16_t cond_f16(svfloat16_t a, svfloat16_t b) {125 return a < b ? a : b;126}127 128// CHECK-LABEL: @_Z8cond_f32u13__SVFloat32_tS_(129// CHECK-NEXT: entry:130// CHECK-NEXT: [[CMP:%.*]] = fcmp olt <vscale x 4 x float> [[A:%.*]], [[B:%.*]]131// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 4 x i1> [[CMP]] to <vscale x 4 x i32>132// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 4 x i32> [[CONV]], zeroinitializer133// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 4 x i1> [[VECTOR_COND]], <vscale x 4 x float> [[A]], <vscale x 4 x float> [[B]]134// CHECK-NEXT: ret <vscale x 4 x float> [[VECTOR_SELECT]]135//136svfloat32_t cond_f32(svfloat32_t a, svfloat32_t b) {137 return a < b ? a : b;138}139 140// CHECK-LABEL: @_Z8cond_f64u13__SVFloat64_tS_(141// CHECK-NEXT: entry:142// CHECK-NEXT: [[CMP:%.*]] = fcmp olt <vscale x 2 x double> [[A:%.*]], [[B:%.*]]143// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 2 x i1> [[CMP]] to <vscale x 2 x i64>144// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 2 x i64> [[CONV]], zeroinitializer145// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 2 x i1> [[VECTOR_COND]], <vscale x 2 x double> [[A]], <vscale x 2 x double> [[B]]146// CHECK-NEXT: ret <vscale x 2 x double> [[VECTOR_SELECT]]147//148svfloat64_t cond_f64(svfloat64_t a, svfloat64_t b) {149 return a < b ? a : b;150}151 152// CHECK-LABEL: @_Z14cond_i32_splatu11__SVInt32_t(153// CHECK-NEXT: entry:154// CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 4 x i32> [[A:%.*]], zeroinitializer155// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 4 x i1> [[CMP]] to <vscale x 4 x i32>156// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 4 x i32> [[CONV]], zeroinitializer157// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 4 x i1> [[VECTOR_COND]], <vscale x 4 x i32> [[A]], <vscale x 4 x i32> zeroinitializer158// CHECK-NEXT: ret <vscale x 4 x i32> [[VECTOR_SELECT]]159//160svint32_t cond_i32_splat(svint32_t a) {161 return a < 0 ? a : 0;162}163 164// CHECK-LABEL: @_Z14cond_u32_splatu12__SVUint32_t(165// CHECK-NEXT: entry:166// CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 4 x i32> [[A:%.*]], splat (i32 1)167// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 4 x i1> [[CMP]] to <vscale x 4 x i32>168// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 4 x i32> [[CONV]], zeroinitializer169// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 4 x i1> [[VECTOR_COND]], <vscale x 4 x i32> [[A]], <vscale x 4 x i32> splat (i32 1)170// CHECK-NEXT: ret <vscale x 4 x i32> [[VECTOR_SELECT]]171//172svuint32_t cond_u32_splat(svuint32_t a) {173 return a < 1u ? a : 1u;174}175 176// CHECK-LABEL: @_Z14cond_i64_splatu11__SVInt64_t(177// CHECK-NEXT: entry:178// CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 2 x i64> [[A:%.*]], zeroinitializer179// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 2 x i1> [[CMP]] to <vscale x 2 x i64>180// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 2 x i64> [[CONV]], zeroinitializer181// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 2 x i1> [[VECTOR_COND]], <vscale x 2 x i64> [[A]], <vscale x 2 x i64> zeroinitializer182// CHECK-NEXT: ret <vscale x 2 x i64> [[VECTOR_SELECT]]183//184svint64_t cond_i64_splat(svint64_t a) {185 return a < 0l ? a : 0l;186}187 188// CHECK-LABEL: @_Z14cond_u64_splatu12__SVUint64_t(189// CHECK-NEXT: entry:190// CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 2 x i64> [[A:%.*]], splat (i64 1)191// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 2 x i1> [[CMP]] to <vscale x 2 x i64>192// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 2 x i64> [[CONV]], zeroinitializer193// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 2 x i1> [[VECTOR_COND]], <vscale x 2 x i64> [[A]], <vscale x 2 x i64> splat (i64 1)194// CHECK-NEXT: ret <vscale x 2 x i64> [[VECTOR_SELECT]]195//196svuint64_t cond_u64_splat(svuint64_t a) {197 return a < 1ul ? a : 1ul;198}199 200// CHECK-LABEL: @_Z14cond_f32_splatu13__SVFloat32_t(201// CHECK-NEXT: entry:202// CHECK-NEXT: [[CMP:%.*]] = fcmp olt <vscale x 4 x float> [[A:%.*]], zeroinitializer203// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 4 x i1> [[CMP]] to <vscale x 4 x i32>204// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 4 x i32> [[CONV]], zeroinitializer205// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 4 x i1> [[VECTOR_COND]], <vscale x 4 x float> [[A]], <vscale x 4 x float> zeroinitializer206// CHECK-NEXT: ret <vscale x 4 x float> [[VECTOR_SELECT]]207//208svfloat32_t cond_f32_splat(svfloat32_t a) {209 return a < 0.f ? a : 0.f;210}211 212// CHECK-LABEL: @_Z14cond_f64_splatu13__SVFloat64_t(213// CHECK-NEXT: entry:214// CHECK-NEXT: [[CMP:%.*]] = fcmp olt <vscale x 2 x double> [[A:%.*]], zeroinitializer215// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 2 x i1> [[CMP]] to <vscale x 2 x i64>216// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 2 x i64> [[CONV]], zeroinitializer217// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 2 x i1> [[VECTOR_COND]], <vscale x 2 x double> [[A]], <vscale x 2 x double> zeroinitializer218// CHECK-NEXT: ret <vscale x 2 x double> [[VECTOR_SELECT]]219//220svfloat64_t cond_f64_splat(svfloat64_t a) {221 return a < 0. ? a : 0.;222}223 224