394 lines · cpp
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-globals all --include-generated-funcs --version 42// RUN: %clang_cc1 -std=c++11 -triple riscv64-linux-gnu -target-feature +i -target-feature +m -emit-llvm %s -o - | FileCheck %s3 4__attribute__((target_clones("default", "arch=+m"))) int foo1(void) {5 return 1;6}7__attribute__((target_clones("default", "arch=+zbb", "arch=+m"))) int foo2(void) { return 2; }8__attribute__((target_clones("default", "arch=+zbb,+c"))) int foo3(void) { return 3; }9__attribute__((target_clones("default", "arch=+zbb,+v"))) int10foo4(void) {11 return 4;12}13__attribute__((target_clones("default"))) int foo5(void) { return 5; }14__attribute__((target_clones("default", "arch=+zvkt"))) int foo6(void) { return 2; }15 16__attribute__((target_clones("default", "arch=+zbb", "arch=+zba", "arch=+zbb,+zba"))) int foo7(void) { return 2; }17__attribute__((target_clones("default", "arch=+zbb;priority=2", "arch=+zba;priority=1", "arch=+zbb,+zba;priority=3"))) int foo8(void) { return 2; }18__attribute__((target_clones("default", "arch=+zbb;priority=1", "priority=2;arch=+zba", "priority=3;arch=+zbb,+zba"))) int foo9(void) { return 2; }19 20int bar() { return foo1() + foo2() + foo3() + foo4() + foo5()+ foo6() + foo7() + foo8() + foo9(); }21 22//.23// CHECK: @__riscv_feature_bits = external dso_local global { i32, [2 x i64] }24// CHECK: @_Z4foo1v.ifunc = weak_odr alias i32 (), ptr @_Z4foo1v25// CHECK: @_Z4foo2v.ifunc = weak_odr alias i32 (), ptr @_Z4foo2v26// CHECK: @_Z4foo3v.ifunc = weak_odr alias i32 (), ptr @_Z4foo3v27// CHECK: @_Z4foo4v.ifunc = weak_odr alias i32 (), ptr @_Z4foo4v28// CHECK: @_Z4foo5v.ifunc = weak_odr alias i32 (), ptr @_Z4foo5v29// CHECK: @_Z4foo6v.ifunc = weak_odr alias i32 (), ptr @_Z4foo6v30// CHECK: @_Z4foo7v.ifunc = weak_odr alias i32 (), ptr @_Z4foo7v31// CHECK: @_Z4foo8v.ifunc = weak_odr alias i32 (), ptr @_Z4foo8v32// CHECK: @_Z4foo9v.ifunc = weak_odr alias i32 (), ptr @_Z4foo9v33// CHECK: @_Z4foo1v = weak_odr ifunc i32 (), ptr @_Z4foo1v.resolver34// CHECK: @_Z4foo2v = weak_odr ifunc i32 (), ptr @_Z4foo2v.resolver35// CHECK: @_Z4foo3v = weak_odr ifunc i32 (), ptr @_Z4foo3v.resolver36// CHECK: @_Z4foo4v = weak_odr ifunc i32 (), ptr @_Z4foo4v.resolver37// CHECK: @_Z4foo5v = weak_odr ifunc i32 (), ptr @_Z4foo5v.resolver38// CHECK: @_Z4foo6v = weak_odr ifunc i32 (), ptr @_Z4foo6v.resolver39// CHECK: @_Z4foo7v = weak_odr ifunc i32 (), ptr @_Z4foo7v.resolver40// CHECK: @_Z4foo8v = weak_odr ifunc i32 (), ptr @_Z4foo8v.resolver41// CHECK: @_Z4foo9v = weak_odr ifunc i32 (), ptr @_Z4foo9v.resolver42//.43// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo1v.default(44// CHECK-SAME: ) #[[ATTR0:[0-9]+]] {45// CHECK-NEXT: entry:46// CHECK-NEXT: ret i32 147//48//49// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo1v._m(50// CHECK-SAME: ) #[[ATTR0]] {51// CHECK-NEXT: entry:52// CHECK-NEXT: ret i32 153//54//55// CHECK-LABEL: define weak_odr ptr @_Z4foo1v.resolver(56// CHECK-SAME: ) #[[ATTR_RESOLVER:[0-9]+]] comdat {57// CHECK-NEXT: resolver_entry:58// CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null)59// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 860// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 409661// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 409662// CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]63// CHECK: resolver_return:64// CHECK-NEXT: ret ptr @_Z4foo1v._m65// CHECK: resolver_else:66// CHECK-NEXT: ret ptr @_Z4foo1v.default67//68//69// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo2v.default(70// CHECK-SAME: ) #[[ATTR0]] {71// CHECK-NEXT: entry:72// CHECK-NEXT: ret i32 273//74//75// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo2v._zbb(76// CHECK-SAME: ) #[[ATTR1:[0-9]+]] {77// CHECK-NEXT: entry:78// CHECK-NEXT: ret i32 279//80//81// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo2v._m(82// CHECK-SAME: ) #[[ATTR0]] {83// CHECK-NEXT: entry:84// CHECK-NEXT: ret i32 285//86//87// CHECK-LABEL: define weak_odr ptr @_Z4foo2v.resolver(88// CHECK-SAME: ) #[[ATTR_RESOLVER]] comdat {89// CHECK-NEXT: resolver_entry:90// CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null)91// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 892// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 26843545693// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 26843545694// CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]95// CHECK: resolver_return:96// CHECK-NEXT: ret ptr @_Z4foo2v._zbb97// CHECK: resolver_else:98// CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 899// CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], 4096100// CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 4096101// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]102// CHECK: resolver_return1:103// CHECK-NEXT: ret ptr @_Z4foo2v._m104// CHECK: resolver_else2:105// CHECK-NEXT: ret ptr @_Z4foo2v.default106//107//108// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo3v.default(109// CHECK-SAME: ) #[[ATTR0]] {110// CHECK-NEXT: entry:111// CHECK-NEXT: ret i32 3112//113//114// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo3v._c_zbb(115// CHECK-SAME: ) #[[ATTR2:[0-9]+]] {116// CHECK-NEXT: entry:117// CHECK-NEXT: ret i32 3118//119//120// CHECK-LABEL: define weak_odr ptr @_Z4foo3v.resolver(121// CHECK-SAME: ) #[[ATTR_RESOLVER]] comdat {122// CHECK-NEXT: resolver_entry:123// CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null)124// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8125// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 268435460126// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 268435460127// CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]128// CHECK: resolver_return:129// CHECK-NEXT: ret ptr @_Z4foo3v._c_zbb130// CHECK: resolver_else:131// CHECK-NEXT: ret ptr @_Z4foo3v.default132//133//134// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo4v.default(135// CHECK-SAME: ) #[[ATTR0]] {136// CHECK-NEXT: entry:137// CHECK-NEXT: ret i32 4138//139//140// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo4v._v_zbb(141// CHECK-SAME: ) #[[ATTR3:[0-9]+]] {142// CHECK-NEXT: entry:143// CHECK-NEXT: ret i32 4144//145//146// CHECK-LABEL: define weak_odr ptr @_Z4foo4v.resolver(147// CHECK-SAME: ) #[[ATTR_RESOLVER]] comdat {148// CHECK-NEXT: resolver_entry:149// CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null)150// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8151// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 270532608152// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 270532608153// CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]154// CHECK: resolver_return:155// CHECK-NEXT: ret ptr @_Z4foo4v._v_zbb156// CHECK: resolver_else:157// CHECK-NEXT: ret ptr @_Z4foo4v.default158//159//160// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo5v.default(161// CHECK-SAME: ) #[[ATTR0]] {162// CHECK-NEXT: entry:163// CHECK-NEXT: ret i32 5164//165//166// CHECK-LABEL: define weak_odr ptr @_Z4foo5v.resolver(167// CHECK-SAME: ) #[[ATTR_RESOLVER]] comdat {168// CHECK-NEXT: resolver_entry:169// CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null)170// CHECK-NEXT: ret ptr @_Z4foo5v.default171//172//173// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo6v.default(174// CHECK-SAME: ) #[[ATTR0]] {175// CHECK-NEXT: entry:176// CHECK-NEXT: ret i32 2177//178//179// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo6v._zvkt(180// CHECK-SAME: ) #[[ATTR4:[0-9]+]] {181// CHECK-NEXT: entry:182// CHECK-NEXT: ret i32 2183//184//185// CHECK-LABEL: define weak_odr ptr @_Z4foo6v.resolver(186// CHECK-SAME: ) #[[ATTR_RESOLVER]] comdat {187// CHECK-NEXT: resolver_entry:188// CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null)189// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8190// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 576460752303423488191// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 576460752303423488192// CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]193// CHECK: resolver_return:194// CHECK-NEXT: ret ptr @_Z4foo6v._zvkt195// CHECK: resolver_else:196// CHECK-NEXT: ret ptr @_Z4foo6v.default197//198//199// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo7v.default(200// CHECK-SAME: ) #[[ATTR0]] {201// CHECK-NEXT: entry:202// CHECK-NEXT: ret i32 2203//204//205// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo7v._zbb(206// CHECK-SAME: ) #[[ATTR1]] {207// CHECK-NEXT: entry:208// CHECK-NEXT: ret i32 2209//210//211// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo7v._zba(212// CHECK-SAME: ) #[[ATTR5:[0-9]+]] {213// CHECK-NEXT: entry:214// CHECK-NEXT: ret i32 2215//216//217// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo7v._zba_zbb(218// CHECK-SAME: ) #[[ATTR6:[0-9]+]] {219// CHECK-NEXT: entry:220// CHECK-NEXT: ret i32 2221//222//223// CHECK-LABEL: define weak_odr ptr @_Z4foo7v.resolver(224// CHECK-SAME: ) #[[ATTR_RESOLVER]] comdat {225// CHECK-NEXT: resolver_entry:226// CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null)227// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8228// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 268435456229// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 268435456230// CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]231// CHECK: resolver_return:232// CHECK-NEXT: ret ptr @_Z4foo7v._zbb233// CHECK: resolver_else:234// CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8235// CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], 134217728236// CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 134217728237// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]238// CHECK: resolver_return1:239// CHECK-NEXT: ret ptr @_Z4foo7v._zba240// CHECK: resolver_else2:241// CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8242// CHECK-NEXT: [[TMP7:%.*]] = and i64 [[TMP6]], 402653184243// CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 402653184244// CHECK-NEXT: br i1 [[TMP8]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]245// CHECK: resolver_return3:246// CHECK-NEXT: ret ptr @_Z4foo7v._zba_zbb247// CHECK: resolver_else4:248// CHECK-NEXT: ret ptr @_Z4foo7v.default249//250//251// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo8v.default(252// CHECK-SAME: ) #[[ATTR0]] {253// CHECK-NEXT: entry:254// CHECK-NEXT: ret i32 2255//256//257// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo8v._zbb(258// CHECK-SAME: ) #[[ATTR1]] {259// CHECK-NEXT: entry:260// CHECK-NEXT: ret i32 2261//262//263// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo8v._zba(264// CHECK-SAME: ) #[[ATTR5]] {265// CHECK-NEXT: entry:266// CHECK-NEXT: ret i32 2267//268//269// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo8v._zba_zbb(270// CHECK-SAME: ) #[[ATTR6]] {271// CHECK-NEXT: entry:272// CHECK-NEXT: ret i32 2273//274//275// CHECK-LABEL: define weak_odr ptr @_Z4foo8v.resolver(276// CHECK-SAME: ) #[[ATTR_RESOLVER]] comdat {277// CHECK-NEXT: resolver_entry:278// CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null)279// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8280// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 402653184281// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 402653184282// CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]283// CHECK: resolver_return:284// CHECK-NEXT: ret ptr @_Z4foo8v._zba_zbb285// CHECK: resolver_else:286// CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8287// CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], 268435456288// CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 268435456289// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]290// CHECK: resolver_return1:291// CHECK-NEXT: ret ptr @_Z4foo8v._zbb292// CHECK: resolver_else2:293// CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8294// CHECK-NEXT: [[TMP7:%.*]] = and i64 [[TMP6]], 134217728295// CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 134217728296// CHECK-NEXT: br i1 [[TMP8]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]297// CHECK: resolver_return3:298// CHECK-NEXT: ret ptr @_Z4foo8v._zba299// CHECK: resolver_else4:300// CHECK-NEXT: ret ptr @_Z4foo8v.default301//302//303// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo9v.default(304// CHECK-SAME: ) #[[ATTR0]] {305// CHECK-NEXT: entry:306// CHECK-NEXT: ret i32 2307//308//309// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo9v._zbb(310// CHECK-SAME: ) #[[ATTR1]] {311// CHECK-NEXT: entry:312// CHECK-NEXT: ret i32 2313//314//315// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo9v._zba(316// CHECK-SAME: ) #[[ATTR5]] {317// CHECK-NEXT: entry:318// CHECK-NEXT: ret i32 2319//320//321// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo9v._zba_zbb(322// CHECK-SAME: ) #[[ATTR6]] {323// CHECK-NEXT: entry:324// CHECK-NEXT: ret i32 2325//326//327// CHECK-LABEL: define weak_odr ptr @_Z4foo9v.resolver(328// CHECK-SAME: ) #[[ATTR_RESOLVER]] comdat {329// CHECK-NEXT: resolver_entry:330// CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null)331// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8332// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 402653184333// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 402653184334// CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]335// CHECK: resolver_return:336// CHECK-NEXT: ret ptr @_Z4foo9v._zba_zbb337// CHECK: resolver_else:338// CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8339// CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], 134217728340// CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 134217728341// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]342// CHECK: resolver_return1:343// CHECK-NEXT: ret ptr @_Z4foo9v._zba344// CHECK: resolver_else2:345// CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8346// CHECK-NEXT: [[TMP7:%.*]] = and i64 [[TMP6]], 268435456347// CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 268435456348// CHECK-NEXT: br i1 [[TMP8]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]349// CHECK: resolver_return3:350// CHECK-NEXT: ret ptr @_Z4foo9v._zbb351// CHECK: resolver_else4:352// CHECK-NEXT: ret ptr @_Z4foo9v.default353//354//355// CHECK-LABEL: define dso_local noundef signext i32 @_Z3barv(356// CHECK-SAME: ) #[[ATTR0]] {357// CHECK-NEXT: entry:358// CHECK-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z4foo1v()359// CHECK-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_Z4foo2v()360// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]]361// CHECK-NEXT: [[CALL2:%.*]] = call noundef signext i32 @_Z4foo3v()362// CHECK-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CALL2]]363// CHECK-NEXT: [[CALL4:%.*]] = call noundef signext i32 @_Z4foo4v()364// CHECK-NEXT: [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CALL4]]365// CHECK-NEXT: [[CALL6:%.*]] = call noundef signext i32 @_Z4foo5v()366// CHECK-NEXT: [[ADD7:%.*]] = add nsw i32 [[ADD5]], [[CALL6]]367// CHECK-NEXT: [[CALL8:%.*]] = call noundef signext i32 @_Z4foo6v()368// CHECK-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD7]], [[CALL8]]369// CHECK-NEXT: [[CALL10:%.*]] = call noundef signext i32 @_Z4foo7v()370// CHECK-NEXT: [[ADD11:%.*]] = add nsw i32 [[ADD9]], [[CALL10]]371// CHECK-NEXT: [[CALL12:%.*]] = call noundef signext i32 @_Z4foo8v()372// CHECK-NEXT: [[ADD13:%.*]] = add nsw i32 [[ADD11]], [[CALL12]]373// CHECK-NEXT: [[CALL14:%.*]] = call noundef signext i32 @_Z4foo9v()374// CHECK-NEXT: [[ADD15:%.*]] = add nsw i32 [[ADD13]], [[CALL14]]375// CHECK-NEXT: ret i32 [[ADD15]]376//377//.378// CHECK: attributes #[[ATTR0]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zmmul" }379// CHECK: attributes #[[ATTR_RESOLVER]] = { disable_sanitizer_instrumentation }380// CHECK: attributes #[[ATTR1]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zbb,+zmmul" }381// CHECK: attributes #[[ATTR2]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+c,+i,+m,+zbb,+zca,+zmmul" }382// CHECK: attributes #[[ATTR3]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+m,+v,+zbb,+zicsr,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }383// CHECK: attributes #[[ATTR4]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zmmul,+zvkt" }384// CHECK: attributes #[[ATTR5]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zba,+zmmul" }385// CHECK: attributes #[[ATTR6]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zba,+zbb,+zmmul" }386//.387// CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}388// CHECK: [[META1:![0-9]+]] = !{i32 1, !"target-abi", !"lp64"}389// CHECK: [[META2:![0-9]+]] = !{i32 6, !"riscv-isa", [[META3:![0-9]+]]}390// CHECK: [[META3]] = !{!"rv64i2p1_m2p0_zmmul1p0"}391// CHECK: [[META4:![0-9]+]] = !{i32 8, !"SmallDataLimit", i32 0}392// CHECK: [[META5:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}393//.394