131 lines · cpp
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 52// RUN: %clang_cc1 -std=c++20 -triple=x86_64-linux-gnu -emit-llvm -o - %s | FileCheck %s3 4 5template <unsigned Size>6struct S {7 char data[Size];8};9 10// CHECK-LABEL: define dso_local noundef zeroext i1 @_Z21test_compare_exchangePU7_Atomic1SILj3EEPS0_S0_(11// CHECK-SAME: ptr noundef [[A:%.*]], ptr noundef [[EXPECTED:%.*]], i24 [[DESIRED_COERCE:%.*]]) #[[ATTR0:[0-9]+]] {12// CHECK-NEXT: [[ENTRY:.*:]]13// CHECK-NEXT: [[DESIRED:%.*]] = alloca [[STRUCT_S:%.*]], align 114// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 815// CHECK-NEXT: [[EXPECTED_ADDR:%.*]] = alloca ptr, align 816// CHECK-NEXT: [[DOTATOMICTMP:%.*]] = alloca [[STRUCT_S]], align 117// CHECK-NEXT: [[ATOMIC_TEMP:%.*]] = alloca { [[STRUCT_S]], [1 x i8] }, align 418// CHECK-NEXT: [[ATOMIC_TEMP1:%.*]] = alloca { [[STRUCT_S]], [1 x i8] }, align 419// CHECK-NEXT: [[CMPXCHG_BOOL:%.*]] = alloca i8, align 120// CHECK-NEXT: [[OLD_TMP:%.*]] = alloca i32, align 421// CHECK-NEXT: [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[DESIRED]], i32 0, i32 022// CHECK-NEXT: store i24 [[DESIRED_COERCE]], ptr [[COERCE_DIVE]], align 123// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 824// CHECK-NEXT: store ptr [[EXPECTED]], ptr [[EXPECTED_ADDR]], align 825// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 826// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[EXPECTED_ADDR]], align 827// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[DOTATOMICTMP]], ptr align 1 [[DESIRED]], i64 3, i1 false)28// CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[ATOMIC_TEMP]], i8 0, i64 4, i1 false)29// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ATOMIC_TEMP]], ptr align 1 [[TMP1]], i64 3, i1 false)30// CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[ATOMIC_TEMP1]], i8 0, i64 4, i1 false)31// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ATOMIC_TEMP1]], ptr align 1 [[DOTATOMICTMP]], i64 3, i1 false)32// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[ATOMIC_TEMP]], align 433// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[ATOMIC_TEMP1]], align 434// CHECK-NEXT: [[TMP4:%.*]] = cmpxchg ptr [[TMP0]], i32 [[TMP2]], i32 [[TMP3]] monotonic monotonic, align 435// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { i32, i1 } [[TMP4]], 036// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { i32, i1 } [[TMP4]], 137// CHECK-NEXT: br i1 [[TMP6]], label %[[CMPXCHG_CONTINUE:.*]], label %[[CMPXCHG_STORE_EXPECTED:.*]]38// CHECK: [[CMPXCHG_STORE_EXPECTED]]:39// CHECK-NEXT: store i32 [[TMP5]], ptr [[OLD_TMP]], align 440// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[TMP1]], ptr align 4 [[OLD_TMP]], i64 3, i1 false)41// CHECK-NEXT: br label %[[CMPXCHG_CONTINUE]]42// CHECK: [[CMPXCHG_CONTINUE]]:43// CHECK-NEXT: [[STOREDV:%.*]] = zext i1 [[TMP6]] to i844// CHECK-NEXT: store i8 [[STOREDV]], ptr [[CMPXCHG_BOOL]], align 145// CHECK-NEXT: [[TMP7:%.*]] = load i8, ptr [[CMPXCHG_BOOL]], align 146// CHECK-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP7]] to i147// CHECK-NEXT: ret i1 [[LOADEDV]]48//49bool test_compare_exchange(_Atomic(S<3>)* a, S<3>* expected, S<3> desired) {50 return __c11_atomic_compare_exchange_strong(a, expected, desired, 0, 0);51}52 53 54// CHECK-LABEL: define dso_local noundef zeroext i1 @_Z21test_compare_exchangePU7_Atomic1SILj4EEPS0_S0_(55// CHECK-SAME: ptr noundef [[A:%.*]], ptr noundef [[EXPECTED:%.*]], i32 [[DESIRED_COERCE:%.*]]) #[[ATTR0]] {56// CHECK-NEXT: [[ENTRY:.*:]]57// CHECK-NEXT: [[DESIRED:%.*]] = alloca [[STRUCT_S_0:%.*]], align 158// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 859// CHECK-NEXT: [[EXPECTED_ADDR:%.*]] = alloca ptr, align 860// CHECK-NEXT: [[DOTATOMICTMP:%.*]] = alloca [[STRUCT_S_0]], align 161// CHECK-NEXT: [[CMPXCHG_BOOL:%.*]] = alloca i8, align 162// CHECK-NEXT: [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[DESIRED]], i32 0, i32 063// CHECK-NEXT: store i32 [[DESIRED_COERCE]], ptr [[COERCE_DIVE]], align 164// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 865// CHECK-NEXT: store ptr [[EXPECTED]], ptr [[EXPECTED_ADDR]], align 866// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 867// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[EXPECTED_ADDR]], align 868// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[DOTATOMICTMP]], ptr align 1 [[DESIRED]], i64 4, i1 false)69// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 170// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTATOMICTMP]], align 171// CHECK-NEXT: [[TMP4:%.*]] = cmpxchg ptr [[TMP0]], i32 [[TMP2]], i32 [[TMP3]] monotonic monotonic, align 472// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { i32, i1 } [[TMP4]], 073// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { i32, i1 } [[TMP4]], 174// CHECK-NEXT: br i1 [[TMP6]], label %[[CMPXCHG_CONTINUE:.*]], label %[[CMPXCHG_STORE_EXPECTED:.*]]75// CHECK: [[CMPXCHG_STORE_EXPECTED]]:76// CHECK-NEXT: store i32 [[TMP5]], ptr [[TMP1]], align 177// CHECK-NEXT: br label %[[CMPXCHG_CONTINUE]]78// CHECK: [[CMPXCHG_CONTINUE]]:79// CHECK-NEXT: [[STOREDV:%.*]] = zext i1 [[TMP6]] to i880// CHECK-NEXT: store i8 [[STOREDV]], ptr [[CMPXCHG_BOOL]], align 181// CHECK-NEXT: [[TMP7:%.*]] = load i8, ptr [[CMPXCHG_BOOL]], align 182// CHECK-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP7]] to i183// CHECK-NEXT: ret i1 [[LOADEDV]]84//85bool test_compare_exchange(_Atomic(S<4>)* a, S<4>* expected, S<4> desired) {86 return __c11_atomic_compare_exchange_strong(a, expected, desired, 0, 0);87}88 89// CHECK-LABEL: define dso_local noundef zeroext i1 @_Z21test_compare_exchangePU7_Atomic1SILj6EEPS0_S0_(90// CHECK-SAME: ptr noundef [[A:%.*]], ptr noundef [[EXPECTED:%.*]], i48 [[DESIRED_COERCE:%.*]]) #[[ATTR0]] {91// CHECK-NEXT: [[ENTRY:.*:]]92// CHECK-NEXT: [[DESIRED:%.*]] = alloca [[STRUCT_S_1:%.*]], align 193// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 894// CHECK-NEXT: [[EXPECTED_ADDR:%.*]] = alloca ptr, align 895// CHECK-NEXT: [[DOTATOMICTMP:%.*]] = alloca [[STRUCT_S_1]], align 196// CHECK-NEXT: [[ATOMIC_TEMP:%.*]] = alloca { [[STRUCT_S_1]], [2 x i8] }, align 897// CHECK-NEXT: [[ATOMIC_TEMP1:%.*]] = alloca { [[STRUCT_S_1]], [2 x i8] }, align 898// CHECK-NEXT: [[CMPXCHG_BOOL:%.*]] = alloca i8, align 199// CHECK-NEXT: [[OLD_TMP:%.*]] = alloca i64, align 8100// CHECK-NEXT: [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw [[STRUCT_S_1]], ptr [[DESIRED]], i32 0, i32 0101// CHECK-NEXT: store i48 [[DESIRED_COERCE]], ptr [[COERCE_DIVE]], align 1102// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8103// CHECK-NEXT: store ptr [[EXPECTED]], ptr [[EXPECTED_ADDR]], align 8104// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8105// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[EXPECTED_ADDR]], align 8106// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[DOTATOMICTMP]], ptr align 1 [[DESIRED]], i64 6, i1 false)107// CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[ATOMIC_TEMP]], i8 0, i64 8, i1 false)108// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[ATOMIC_TEMP]], ptr align 1 [[TMP1]], i64 6, i1 false)109// CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[ATOMIC_TEMP1]], i8 0, i64 8, i1 false)110// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[ATOMIC_TEMP1]], ptr align 1 [[DOTATOMICTMP]], i64 6, i1 false)111// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[ATOMIC_TEMP]], align 8112// CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr [[ATOMIC_TEMP1]], align 8113// CHECK-NEXT: [[TMP4:%.*]] = cmpxchg ptr [[TMP0]], i64 [[TMP2]], i64 [[TMP3]] monotonic monotonic, align 8114// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { i64, i1 } [[TMP4]], 0115// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { i64, i1 } [[TMP4]], 1116// CHECK-NEXT: br i1 [[TMP6]], label %[[CMPXCHG_CONTINUE:.*]], label %[[CMPXCHG_STORE_EXPECTED:.*]]117// CHECK: [[CMPXCHG_STORE_EXPECTED]]:118// CHECK-NEXT: store i64 [[TMP5]], ptr [[OLD_TMP]], align 8119// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[TMP1]], ptr align 8 [[OLD_TMP]], i64 6, i1 false)120// CHECK-NEXT: br label %[[CMPXCHG_CONTINUE]]121// CHECK: [[CMPXCHG_CONTINUE]]:122// CHECK-NEXT: [[STOREDV:%.*]] = zext i1 [[TMP6]] to i8123// CHECK-NEXT: store i8 [[STOREDV]], ptr [[CMPXCHG_BOOL]], align 1124// CHECK-NEXT: [[TMP7:%.*]] = load i8, ptr [[CMPXCHG_BOOL]], align 1125// CHECK-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP7]] to i1126// CHECK-NEXT: ret i1 [[LOADEDV]]127//128bool test_compare_exchange(_Atomic(S<6>)* a, S<6>* expected, S<6> desired) {129 return __c11_atomic_compare_exchange_strong(a, expected, desired, 0, 0);130}131