154 lines · cpp
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 52// RUN: %clang_cc1 -fenable-matrix %s -emit-llvm -triple x86_64-unknown-linux -disable-llvm-passes -o - -std=c++11 | FileCheck %s3 4using i8x3 = _BitInt(8) __attribute__((ext_vector_type(3)));5using i8x3x3 = _BitInt(8) __attribute__((matrix_type(3, 3)));6using i32x3 = _BitInt(32) __attribute__((ext_vector_type(3)));7using i32x3x3 = _BitInt(32) __attribute__((matrix_type(3, 3)));8using i512x3 = _BitInt(512) __attribute__((ext_vector_type(3)));9using i512x3x3 = _BitInt(512) __attribute__((matrix_type(3, 3)));10using i4x3 = _BitInt(4) __attribute__((ext_vector_type(3)));11using i4x3x3 = _BitInt(4) __attribute__((matrix_type(3, 3)));12 13// CHECK-LABEL: define dso_local i32 @_Z2v1Dv3_DB8_(14// CHECK-SAME: i32 [[A_COERCE:%.*]]) #[[ATTR0:[0-9]+]] {15// CHECK-NEXT: [[ENTRY:.*:]]16// CHECK-NEXT: [[RETVAL:%.*]] = alloca <3 x i8>, align 417// CHECK-NEXT: [[A:%.*]] = alloca <3 x i8>, align 418// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <3 x i8>, align 419// CHECK-NEXT: store i32 [[A_COERCE]], ptr [[A]], align 420// CHECK-NEXT: [[LOADVECN:%.*]] = load <4 x i8>, ptr [[A]], align 421// CHECK-NEXT: [[A1:%.*]] = shufflevector <4 x i8> [[LOADVECN]], <4 x i8> poison, <3 x i32> <i32 0, i32 1, i32 2>22// CHECK-NEXT: [[EXTRACTVEC:%.*]] = shufflevector <3 x i8> [[A1]], <3 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>23// CHECK-NEXT: store <4 x i8> [[EXTRACTVEC]], ptr [[A_ADDR]], align 424// CHECK-NEXT: [[LOADVECN2:%.*]] = load <4 x i8>, ptr [[A_ADDR]], align 425// CHECK-NEXT: [[EXTRACTVEC3:%.*]] = shufflevector <4 x i8> [[LOADVECN2]], <4 x i8> poison, <3 x i32> <i32 0, i32 1, i32 2>26// CHECK-NEXT: [[LOADVECN4:%.*]] = load <4 x i8>, ptr [[A_ADDR]], align 427// CHECK-NEXT: [[EXTRACTVEC5:%.*]] = shufflevector <4 x i8> [[LOADVECN4]], <4 x i8> poison, <3 x i32> <i32 0, i32 1, i32 2>28// CHECK-NEXT: [[ADD:%.*]] = add <3 x i8> [[EXTRACTVEC3]], [[EXTRACTVEC5]]29// CHECK-NEXT: store <3 x i8> [[ADD]], ptr [[RETVAL]], align 430// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[RETVAL]], align 431// CHECK-NEXT: ret i32 [[TMP0]]32//33i8x3 v1(i8x3 a) {34 return a + a;35}36 37// CHECK-LABEL: define dso_local noundef <3 x i32> @_Z2v2Dv3_DB32_(38// CHECK-SAME: <3 x i32> noundef [[A:%.*]]) #[[ATTR1:[0-9]+]] {39// CHECK-NEXT: [[ENTRY:.*:]]40// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <3 x i32>, align 1641// CHECK-NEXT: [[EXTRACTVEC:%.*]] = shufflevector <3 x i32> [[A]], <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>42// CHECK-NEXT: store <4 x i32> [[EXTRACTVEC]], ptr [[A_ADDR]], align 1643// CHECK-NEXT: [[LOADVECN:%.*]] = load <4 x i32>, ptr [[A_ADDR]], align 1644// CHECK-NEXT: [[EXTRACTVEC1:%.*]] = shufflevector <4 x i32> [[LOADVECN]], <4 x i32> poison, <3 x i32> <i32 0, i32 1, i32 2>45// CHECK-NEXT: [[LOADVECN2:%.*]] = load <4 x i32>, ptr [[A_ADDR]], align 1646// CHECK-NEXT: [[EXTRACTVEC3:%.*]] = shufflevector <4 x i32> [[LOADVECN2]], <4 x i32> poison, <3 x i32> <i32 0, i32 1, i32 2>47// CHECK-NEXT: [[ADD:%.*]] = add <3 x i32> [[EXTRACTVEC1]], [[EXTRACTVEC3]]48// CHECK-NEXT: ret <3 x i32> [[ADD]]49//50i32x3 v2(i32x3 a) {51 return a + a;52}53 54// CHECK-LABEL: define dso_local noundef <3 x i512> @_Z2v3Dv3_DB512_(55// CHECK-SAME: ptr noundef byval(<3 x i512>) align 256 [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] {56// CHECK-NEXT: [[ENTRY:.*:]]57// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <3 x i512>, align 25658// CHECK-NEXT: [[LOADVECN:%.*]] = load <4 x i512>, ptr [[TMP0]], align 25659// CHECK-NEXT: [[A:%.*]] = shufflevector <4 x i512> [[LOADVECN]], <4 x i512> poison, <3 x i32> <i32 0, i32 1, i32 2>60// CHECK-NEXT: [[EXTRACTVEC:%.*]] = shufflevector <3 x i512> [[A]], <3 x i512> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>61// CHECK-NEXT: store <4 x i512> [[EXTRACTVEC]], ptr [[A_ADDR]], align 25662// CHECK-NEXT: [[LOADVECN1:%.*]] = load <4 x i512>, ptr [[A_ADDR]], align 25663// CHECK-NEXT: [[EXTRACTVEC2:%.*]] = shufflevector <4 x i512> [[LOADVECN1]], <4 x i512> poison, <3 x i32> <i32 0, i32 1, i32 2>64// CHECK-NEXT: [[LOADVECN3:%.*]] = load <4 x i512>, ptr [[A_ADDR]], align 25665// CHECK-NEXT: [[EXTRACTVEC4:%.*]] = shufflevector <4 x i512> [[LOADVECN3]], <4 x i512> poison, <3 x i32> <i32 0, i32 1, i32 2>66// CHECK-NEXT: [[ADD:%.*]] = add <3 x i512> [[EXTRACTVEC2]], [[EXTRACTVEC4]]67// CHECK-NEXT: ret <3 x i512> [[ADD]]68//69i512x3 v3(i512x3 a) {70 return a + a;71}72 73// CHECK-LABEL: define dso_local i32 @_Z2v4Dv3_DB4_(74// CHECK-SAME: i32 [[A_COERCE:%.*]]) #[[ATTR0]] {75// CHECK-NEXT: [[ENTRY:.*:]]76// CHECK-NEXT: [[RETVAL:%.*]] = alloca <3 x i4>, align 477// CHECK-NEXT: [[A:%.*]] = alloca <3 x i4>, align 478// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <3 x i4>, align 479// CHECK-NEXT: [[RETVAL_COERCE:%.*]] = alloca i32, align 480// CHECK-NEXT: store i32 [[A_COERCE]], ptr [[A]], align 481// CHECK-NEXT: [[LOADVECN:%.*]] = load <4 x i4>, ptr [[A]], align 482// CHECK-NEXT: [[A1:%.*]] = shufflevector <4 x i4> [[LOADVECN]], <4 x i4> poison, <3 x i32> <i32 0, i32 1, i32 2>83// CHECK-NEXT: [[EXTRACTVEC:%.*]] = shufflevector <3 x i4> [[A1]], <3 x i4> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>84// CHECK-NEXT: store <4 x i4> [[EXTRACTVEC]], ptr [[A_ADDR]], align 485// CHECK-NEXT: [[LOADVECN2:%.*]] = load <4 x i4>, ptr [[A_ADDR]], align 486// CHECK-NEXT: [[EXTRACTVEC3:%.*]] = shufflevector <4 x i4> [[LOADVECN2]], <4 x i4> poison, <3 x i32> <i32 0, i32 1, i32 2>87// CHECK-NEXT: [[LOADVECN4:%.*]] = load <4 x i4>, ptr [[A_ADDR]], align 488// CHECK-NEXT: [[EXTRACTVEC5:%.*]] = shufflevector <4 x i4> [[LOADVECN4]], <4 x i4> poison, <3 x i32> <i32 0, i32 1, i32 2>89// CHECK-NEXT: [[ADD:%.*]] = add <3 x i4> [[EXTRACTVEC3]], [[EXTRACTVEC5]]90// CHECK-NEXT: store <3 x i4> [[ADD]], ptr [[RETVAL]], align 491// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[RETVAL_COERCE]], ptr align 4 [[RETVAL]], i64 2, i1 false)92// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[RETVAL_COERCE]], align 493// CHECK-NEXT: ret i32 [[TMP0]]94//95i4x3 v4(i4x3 a) {96 return a + a;97}98 99// CHECK-LABEL: define dso_local noundef <9 x i8> @_Z2m1u11matrix_typeILm3ELm3EDB8_E(100// CHECK-SAME: <9 x i8> noundef [[A:%.*]]) #[[ATTR4:[0-9]+]] {101// CHECK-NEXT: [[ENTRY:.*:]]102// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [9 x i8], align 1103// CHECK-NEXT: store <9 x i8> [[A]], ptr [[A_ADDR]], align 1104// CHECK-NEXT: [[TMP0:%.*]] = load <9 x i8>, ptr [[A_ADDR]], align 1105// CHECK-NEXT: [[TMP1:%.*]] = load <9 x i8>, ptr [[A_ADDR]], align 1106// CHECK-NEXT: [[TMP2:%.*]] = add <9 x i8> [[TMP0]], [[TMP1]]107// CHECK-NEXT: ret <9 x i8> [[TMP2]]108//109i8x3x3 m1(i8x3x3 a) {110 return a + a;111}112 113// CHECK-LABEL: define dso_local noundef <9 x i32> @_Z2m2u11matrix_typeILm3ELm3EDB32_E(114// CHECK-SAME: <9 x i32> noundef [[A:%.*]]) #[[ATTR5:[0-9]+]] {115// CHECK-NEXT: [[ENTRY:.*:]]116// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [9 x i32], align 4117// CHECK-NEXT: store <9 x i32> [[A]], ptr [[A_ADDR]], align 4118// CHECK-NEXT: [[TMP0:%.*]] = load <9 x i32>, ptr [[A_ADDR]], align 4119// CHECK-NEXT: [[TMP1:%.*]] = load <9 x i32>, ptr [[A_ADDR]], align 4120// CHECK-NEXT: [[TMP2:%.*]] = add <9 x i32> [[TMP0]], [[TMP1]]121// CHECK-NEXT: ret <9 x i32> [[TMP2]]122//123i32x3x3 m2(i32x3x3 a) {124 return a + a;125}126 127// CHECK-LABEL: define dso_local noundef <9 x i512> @_Z2m3u11matrix_typeILm3ELm3EDB512_E(128// CHECK-SAME: <9 x i512> noundef [[A:%.*]]) #[[ATTR6:[0-9]+]] {129// CHECK-NEXT: [[ENTRY:.*:]]130// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [9 x i512], align 8131// CHECK-NEXT: store <9 x i512> [[A]], ptr [[A_ADDR]], align 8132// CHECK-NEXT: [[TMP0:%.*]] = load <9 x i512>, ptr [[A_ADDR]], align 8133// CHECK-NEXT: [[TMP1:%.*]] = load <9 x i512>, ptr [[A_ADDR]], align 8134// CHECK-NEXT: [[TMP2:%.*]] = add <9 x i512> [[TMP0]], [[TMP1]]135// CHECK-NEXT: ret <9 x i512> [[TMP2]]136//137i512x3x3 m3(i512x3x3 a) {138 return a + a;139}140 141// CHECK-LABEL: define dso_local noundef <9 x i4> @_Z2m4u11matrix_typeILm3ELm3EDB4_E(142// CHECK-SAME: <9 x i4> noundef [[A:%.*]]) #[[ATTR7:[0-9]+]] {143// CHECK-NEXT: [[ENTRY:.*:]]144// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [9 x i4], align 1145// CHECK-NEXT: store <9 x i4> [[A]], ptr [[A_ADDR]], align 1146// CHECK-NEXT: [[TMP0:%.*]] = load <9 x i4>, ptr [[A_ADDR]], align 1147// CHECK-NEXT: [[TMP1:%.*]] = load <9 x i4>, ptr [[A_ADDR]], align 1148// CHECK-NEXT: [[TMP2:%.*]] = add <9 x i4> [[TMP0]], [[TMP1]]149// CHECK-NEXT: ret <9 x i4> [[TMP2]]150//151i4x3x3 m4(i4x3x3 a) {152 return a + a;153}154