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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py2// RUN: %clang_cc1 %s -O0 -triple amdgcn-amd-amdhsa -cl-std=CL1.2 \3// RUN: -emit-llvm -o - | FileCheck %s4 5// CHECK-LABEL: @test_builtin_amdgcn_cvt_off_f32_i4_ui(6// CHECK-NEXT: entry:7// CHECK-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4, addrspace(5)8// CHECK-NEXT: store i32 [[N:%.*]], ptr addrspace(5) [[N_ADDR]], align 49// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr addrspace(5) [[N_ADDR]], align 410// CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.amdgcn.cvt.off.f32.i4(i32 [[TMP0]])11// CHECK-NEXT: ret float [[TMP1]]12//13float test_builtin_amdgcn_cvt_off_f32_i4_ui(unsigned n) {14 return __builtin_amdgcn_cvt_off_f32_i4(n);15}16 17// CHECK-LABEL: @test_builtin_amdgcn_cvt_off_f32_i4_i(18// CHECK-NEXT: entry:19// CHECK-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4, addrspace(5)20// CHECK-NEXT: store i32 [[N:%.*]], ptr addrspace(5) [[N_ADDR]], align 421// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr addrspace(5) [[N_ADDR]], align 422// CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.amdgcn.cvt.off.f32.i4(i32 [[TMP0]])23// CHECK-NEXT: ret float [[TMP1]]24//25float test_builtin_amdgcn_cvt_off_f32_i4_i(int n) {26 return __builtin_amdgcn_cvt_off_f32_i4(n);27}28