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1// REQUIRES: riscv-registered-target2// RUN: %clang --target=riscv32 -mcpu=andes-n45 --print-enabled-extensions | FileCheck %s3 4// CHECK: Extensions enabled for the given RISC-V target5// CHECK-EMPTY:6// CHECK-NEXT: Name Version Description7// CHECK-NEXT: i 2.1 'I' (Base Integer Instruction Set)8// CHECK-NEXT: m 2.0 'M' (Integer Multiplication and Division)9// CHECK-NEXT: a 2.1 'A' (Atomic Instructions)10// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point)11// CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point)12// CHECK-NEXT: c 2.0 'C' (Compressed Instructions)13// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)14// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)15// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication)16// CHECK-NEXT: zaamo 1.0 'Zaamo' (Atomic Memory Operations)17// CHECK-NEXT: zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional)18// CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores)19// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions)20// CHECK-NEXT: zcf 1.0 'Zcf' (Compressed Single-Precision Floating-Point Instructions)21// CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension)22// CHECK-EMPTY:23// CHECK-NEXT: Experimental extensions24// CHECK-EMPTY:25// CHECK-NEXT: ISA String: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_xandesperf5p026