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1// REQUIRES: arm-registered-target2// RUN: %clang --target=arm-linux-gnu --print-supported-extensions | FileCheck --strict-whitespace --implicit-check-not=FEAT_ %s3 4// CHECK: All available -march extensions for ARM5// CHECK-EMPTY:6// CHECK-NEXT: Name Description7// CHECK-NEXT: crc Enable support for CRC instructions8// CHECK-NEXT: crypto Enable support for Cryptography extensions9// CHECK-NEXT: sha2 Enable SHA1 and SHA256 support10// CHECK-NEXT: aes Enable AES support11// CHECK-NEXT: dotprod Enable support for dot product instructions12// CHECK-NEXT: dsp Supports DSP instructions in ARM and/or Thumb213// CHECK-NEXT: mve Support M-Class Vector Extension with integer ops14// CHECK-NEXT: mve.fp Support M-Class Vector Extension with integer and floating ops15// CHECK-NEXT: simd Enable NEON instructions16// CHECK-NEXT: fp16 Enable half-precision floating point17// CHECK-NEXT: ras Enable Reliability, Availability and Serviceability extensions18// CHECK-NEXT: fp16fml Enable full half-precision floating point fml instructions19// CHECK-NEXT: bf16 Enable support for BFloat16 instructions20// CHECK-NEXT: sb Enable v8.5a Speculation Barrier21// CHECK-NEXT: i8mm Enable Matrix Multiply Int8 Extension22// CHECK-NEXT: lob Enable Low Overhead Branch extensions23// CHECK-NEXT: cdecp0 Coprocessor 0 ISA is CDEv124// CHECK-NEXT: cdecp1 Coprocessor 1 ISA is CDEv125// CHECK-NEXT: cdecp2 Coprocessor 2 ISA is CDEv126// CHECK-NEXT: cdecp3 Coprocessor 3 ISA is CDEv127// CHECK-NEXT: cdecp4 Coprocessor 4 ISA is CDEv128// CHECK-NEXT: cdecp5 Coprocessor 5 ISA is CDEv129// CHECK-NEXT: cdecp6 Coprocessor 6 ISA is CDEv130// CHECK-NEXT: cdecp7 Coprocessor 7 ISA is CDEv131// CHECK-NEXT: pacbti Enable Pointer Authentication and Branch Target Identification32