727 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py2// RUN: %clang_cc1 -ffixed-point -triple x86_64-unknown-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,SIGNED3// RUN: %clang_cc1 -ffixed-point -triple x86_64-unknown-linux-gnu -fpadding-on-unsigned-fixed-point -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,UNSIGNED4 5short _Fract shf;6_Accum a;7unsigned _Fract uf;8unsigned long _Accum ula;9 10_Sat short _Fract sshf;11_Sat _Accum sa;12_Sat unsigned _Fract suf;13_Sat unsigned long _Accum sula;14 15int i;16unsigned int u;17signed char c;18 19float fl;20 21 22// CHECK-LABEL: @add_shfa(23// CHECK-NEXT: entry:24// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @a, align 425// CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr @shf, align 126// CHECK-NEXT: [[RESIZE:%.*]] = sext i8 [[TMP1]] to i3227// CHECK-NEXT: [[UPSCALE:%.*]] = shl i32 [[RESIZE]], 828// CHECK-NEXT: [[TMP2:%.*]] = add i32 [[UPSCALE]], [[TMP0]]29// CHECK-NEXT: [[DOWNSCALE:%.*]] = ashr i32 [[TMP2]], 830// CHECK-NEXT: [[RESIZE1:%.*]] = trunc i32 [[DOWNSCALE]] to i831// CHECK-NEXT: store i8 [[RESIZE1]], ptr @shf, align 132// CHECK-NEXT: ret void33//34void add_shfa(void) {35 shf += a;36}37 38// SIGNED-LABEL: @add_auf(39// SIGNED-NEXT: entry:40// SIGNED-NEXT: [[TMP0:%.*]] = load i16, ptr @uf, align 241// SIGNED-NEXT: [[TMP1:%.*]] = load i32, ptr @a, align 442// SIGNED-NEXT: [[RESIZE:%.*]] = sext i32 [[TMP1]] to i3343// SIGNED-NEXT: [[UPSCALE:%.*]] = shl i33 [[RESIZE]], 144// SIGNED-NEXT: [[RESIZE1:%.*]] = zext i16 [[TMP0]] to i3345// SIGNED-NEXT: [[TMP2:%.*]] = add i33 [[UPSCALE]], [[RESIZE1]]46// SIGNED-NEXT: [[DOWNSCALE:%.*]] = ashr i33 [[TMP2]], 147// SIGNED-NEXT: [[RESIZE2:%.*]] = trunc i33 [[DOWNSCALE]] to i3248// SIGNED-NEXT: store i32 [[RESIZE2]], ptr @a, align 449// SIGNED-NEXT: ret void50//51// UNSIGNED-LABEL: @add_auf(52// UNSIGNED-NEXT: entry:53// UNSIGNED-NEXT: [[TMP0:%.*]] = load i16, ptr @uf, align 254// UNSIGNED-NEXT: [[TMP1:%.*]] = load i32, ptr @a, align 455// UNSIGNED-NEXT: [[RESIZE:%.*]] = zext i16 [[TMP0]] to i3256// UNSIGNED-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], [[RESIZE]]57// UNSIGNED-NEXT: store i32 [[TMP2]], ptr @a, align 458// UNSIGNED-NEXT: ret void59//60void add_auf(void) {61 a += uf;62}63 64// CHECK-LABEL: @add_ufula(65// CHECK-NEXT: entry:66// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @ula, align 867// CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr @uf, align 268// CHECK-NEXT: [[RESIZE:%.*]] = zext i16 [[TMP1]] to i6469// CHECK-NEXT: [[UPSCALE:%.*]] = shl i64 [[RESIZE]], 1670// CHECK-NEXT: [[TMP2:%.*]] = add i64 [[UPSCALE]], [[TMP0]]71// CHECK-NEXT: [[DOWNSCALE:%.*]] = lshr i64 [[TMP2]], 1672// CHECK-NEXT: [[RESIZE1:%.*]] = trunc i64 [[DOWNSCALE]] to i1673// CHECK-NEXT: store i16 [[RESIZE1]], ptr @uf, align 274// CHECK-NEXT: ret void75//76void add_ufula(void) {77 uf += ula;78}79 80// SIGNED-LABEL: @add_ulashf(81// SIGNED-NEXT: entry:82// SIGNED-NEXT: [[TMP0:%.*]] = load i8, ptr @shf, align 183// SIGNED-NEXT: [[TMP1:%.*]] = load i64, ptr @ula, align 884// SIGNED-NEXT: [[RESIZE:%.*]] = zext i64 [[TMP1]] to i6585// SIGNED-NEXT: [[RESIZE1:%.*]] = sext i8 [[TMP0]] to i6586// SIGNED-NEXT: [[UPSCALE:%.*]] = shl i65 [[RESIZE1]], 2587// SIGNED-NEXT: [[TMP2:%.*]] = add i65 [[RESIZE]], [[UPSCALE]]88// SIGNED-NEXT: [[DOWNSCALE:%.*]] = ashr i65 [[TMP2]], 189// SIGNED-NEXT: [[RESIZE2:%.*]] = trunc i65 [[DOWNSCALE]] to i6490// SIGNED-NEXT: [[UPSCALE3:%.*]] = shl i64 [[RESIZE2]], 191// SIGNED-NEXT: store i64 [[UPSCALE3]], ptr @ula, align 892// SIGNED-NEXT: ret void93//94// UNSIGNED-LABEL: @add_ulashf(95// UNSIGNED-NEXT: entry:96// UNSIGNED-NEXT: [[TMP0:%.*]] = load i8, ptr @shf, align 197// UNSIGNED-NEXT: [[TMP1:%.*]] = load i64, ptr @ula, align 898// UNSIGNED-NEXT: [[RESIZE:%.*]] = sext i8 [[TMP0]] to i6499// UNSIGNED-NEXT: [[UPSCALE:%.*]] = shl i64 [[RESIZE]], 24100// UNSIGNED-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], [[UPSCALE]]101// UNSIGNED-NEXT: store i64 [[TMP2]], ptr @ula, align 8102// UNSIGNED-NEXT: ret void103//104void add_ulashf(void) {105 ula += shf;106}107 108// SIGNED-LABEL: @add_ufshf(109// SIGNED-NEXT: entry:110// SIGNED-NEXT: [[TMP0:%.*]] = load i8, ptr @shf, align 1111// SIGNED-NEXT: [[TMP1:%.*]] = load i16, ptr @uf, align 2112// SIGNED-NEXT: [[RESIZE:%.*]] = zext i16 [[TMP1]] to i17113// SIGNED-NEXT: [[RESIZE1:%.*]] = sext i8 [[TMP0]] to i17114// SIGNED-NEXT: [[UPSCALE:%.*]] = shl i17 [[RESIZE1]], 9115// SIGNED-NEXT: [[TMP2:%.*]] = add i17 [[RESIZE]], [[UPSCALE]]116// SIGNED-NEXT: [[DOWNSCALE:%.*]] = ashr i17 [[TMP2]], 1117// SIGNED-NEXT: [[RESIZE2:%.*]] = trunc i17 [[DOWNSCALE]] to i16118// SIGNED-NEXT: [[UPSCALE3:%.*]] = shl i16 [[RESIZE2]], 1119// SIGNED-NEXT: store i16 [[UPSCALE3]], ptr @uf, align 2120// SIGNED-NEXT: ret void121//122// UNSIGNED-LABEL: @add_ufshf(123// UNSIGNED-NEXT: entry:124// UNSIGNED-NEXT: [[TMP0:%.*]] = load i8, ptr @shf, align 1125// UNSIGNED-NEXT: [[TMP1:%.*]] = load i16, ptr @uf, align 2126// UNSIGNED-NEXT: [[RESIZE:%.*]] = sext i8 [[TMP0]] to i16127// UNSIGNED-NEXT: [[UPSCALE:%.*]] = shl i16 [[RESIZE]], 8128// UNSIGNED-NEXT: [[TMP2:%.*]] = add i16 [[TMP1]], [[UPSCALE]]129// UNSIGNED-NEXT: store i16 [[TMP2]], ptr @uf, align 2130// UNSIGNED-NEXT: ret void131//132void add_ufshf(void) {133 uf += shf;134}135 136// CHECK-LABEL: @add_ashf(137// CHECK-NEXT: entry:138// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr @shf, align 1139// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @a, align 4140// CHECK-NEXT: [[RESIZE:%.*]] = sext i8 [[TMP0]] to i32141// CHECK-NEXT: [[UPSCALE:%.*]] = shl i32 [[RESIZE]], 8142// CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], [[UPSCALE]]143// CHECK-NEXT: store i32 [[TMP2]], ptr @a, align 4144// CHECK-NEXT: ret void145//146void add_ashf(void) {147 a += shf;148}149 150// CHECK-LABEL: @add_ai(151// CHECK-NEXT: entry:152// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @i, align 4153// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @a, align 4154// CHECK-NEXT: [[RESIZE:%.*]] = sext i32 [[TMP1]] to i47155// CHECK-NEXT: [[RESIZE1:%.*]] = sext i32 [[TMP0]] to i47156// CHECK-NEXT: [[UPSCALE:%.*]] = shl i47 [[RESIZE1]], 15157// CHECK-NEXT: [[TMP2:%.*]] = add i47 [[RESIZE]], [[UPSCALE]]158// CHECK-NEXT: [[RESIZE2:%.*]] = trunc i47 [[TMP2]] to i32159// CHECK-NEXT: store i32 [[RESIZE2]], ptr @a, align 4160// CHECK-NEXT: ret void161//162void add_ai(void) {163 a += i;164}165 166// CHECK-LABEL: @add_au(167// CHECK-NEXT: entry:168// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @u, align 4169// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @a, align 4170// CHECK-NEXT: [[RESIZE:%.*]] = sext i32 [[TMP1]] to i48171// CHECK-NEXT: [[RESIZE1:%.*]] = zext i32 [[TMP0]] to i48172// CHECK-NEXT: [[UPSCALE:%.*]] = shl i48 [[RESIZE1]], 15173// CHECK-NEXT: [[TMP2:%.*]] = add i48 [[RESIZE]], [[UPSCALE]]174// CHECK-NEXT: [[RESIZE2:%.*]] = trunc i48 [[TMP2]] to i32175// CHECK-NEXT: store i32 [[RESIZE2]], ptr @a, align 4176// CHECK-NEXT: ret void177//178void add_au(void) {179 a += u;180}181 182// SIGNED-LABEL: @add_ulai(183// SIGNED-NEXT: entry:184// SIGNED-NEXT: [[TMP0:%.*]] = load i32, ptr @i, align 4185// SIGNED-NEXT: [[TMP1:%.*]] = load i64, ptr @ula, align 8186// SIGNED-NEXT: [[RESIZE:%.*]] = zext i64 [[TMP1]] to i65187// SIGNED-NEXT: [[RESIZE1:%.*]] = sext i32 [[TMP0]] to i65188// SIGNED-NEXT: [[UPSCALE:%.*]] = shl i65 [[RESIZE1]], 32189// SIGNED-NEXT: [[TMP2:%.*]] = add i65 [[RESIZE]], [[UPSCALE]]190// SIGNED-NEXT: [[RESIZE2:%.*]] = trunc i65 [[TMP2]] to i64191// SIGNED-NEXT: store i64 [[RESIZE2]], ptr @ula, align 8192// SIGNED-NEXT: ret void193//194// UNSIGNED-LABEL: @add_ulai(195// UNSIGNED-NEXT: entry:196// UNSIGNED-NEXT: [[TMP0:%.*]] = load i32, ptr @i, align 4197// UNSIGNED-NEXT: [[TMP1:%.*]] = load i64, ptr @ula, align 8198// UNSIGNED-NEXT: [[RESIZE:%.*]] = sext i32 [[TMP0]] to i64199// UNSIGNED-NEXT: [[UPSCALE:%.*]] = shl i64 [[RESIZE]], 31200// UNSIGNED-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], [[UPSCALE]]201// UNSIGNED-NEXT: store i64 [[TMP2]], ptr @ula, align 8202// UNSIGNED-NEXT: ret void203//204void add_ulai(void) {205 ula += i;206}207 208// SIGNED-LABEL: @add_iula(209// SIGNED-NEXT: entry:210// SIGNED-NEXT: [[TMP0:%.*]] = load i64, ptr @ula, align 8211// SIGNED-NEXT: [[TMP1:%.*]] = load i32, ptr @i, align 4212// SIGNED-NEXT: [[RESIZE:%.*]] = sext i32 [[TMP1]] to i65213// SIGNED-NEXT: [[UPSCALE:%.*]] = shl i65 [[RESIZE]], 32214// SIGNED-NEXT: [[RESIZE1:%.*]] = zext i64 [[TMP0]] to i65215// SIGNED-NEXT: [[TMP2:%.*]] = add i65 [[UPSCALE]], [[RESIZE1]]216// SIGNED-NEXT: [[RESIZE2:%.*]] = trunc i65 [[TMP2]] to i64217// SIGNED-NEXT: [[DOWNSCALE:%.*]] = lshr i64 [[RESIZE2]], 32218// SIGNED-NEXT: [[RESIZE3:%.*]] = trunc i64 [[DOWNSCALE]] to i32219// SIGNED-NEXT: store i32 [[RESIZE3]], ptr @i, align 4220// SIGNED-NEXT: ret void221//222// UNSIGNED-LABEL: @add_iula(223// UNSIGNED-NEXT: entry:224// UNSIGNED-NEXT: [[TMP0:%.*]] = load i64, ptr @ula, align 8225// UNSIGNED-NEXT: [[TMP1:%.*]] = load i32, ptr @i, align 4226// UNSIGNED-NEXT: [[RESIZE:%.*]] = sext i32 [[TMP1]] to i64227// UNSIGNED-NEXT: [[UPSCALE:%.*]] = shl i64 [[RESIZE]], 31228// UNSIGNED-NEXT: [[TMP2:%.*]] = add i64 [[UPSCALE]], [[TMP0]]229// UNSIGNED-NEXT: [[DOWNSCALE:%.*]] = lshr i64 [[TMP2]], 31230// UNSIGNED-NEXT: [[RESIZE1:%.*]] = trunc i64 [[DOWNSCALE]] to i32231// UNSIGNED-NEXT: store i32 [[RESIZE1]], ptr @i, align 4232// UNSIGNED-NEXT: ret void233//234void add_iula(void) {235 i += ula;236}237 238// CHECK-LABEL: @add_ca(239// CHECK-NEXT: entry:240// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @a, align 4241// CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr @c, align 1242// CHECK-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32243// CHECK-NEXT: [[RESIZE:%.*]] = sext i32 [[CONV]] to i47244// CHECK-NEXT: [[UPSCALE:%.*]] = shl i47 [[RESIZE]], 15245// CHECK-NEXT: [[RESIZE1:%.*]] = sext i32 [[TMP0]] to i47246// CHECK-NEXT: [[TMP2:%.*]] = add i47 [[UPSCALE]], [[RESIZE1]]247// CHECK-NEXT: [[RESIZE2:%.*]] = trunc i47 [[TMP2]] to i32248// CHECK-NEXT: [[TMP3:%.*]] = icmp slt i32 [[RESIZE2]], 0249// CHECK-NEXT: [[TMP4:%.*]] = add i32 [[RESIZE2]], 32767250// CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP3]], i32 [[TMP4]], i32 [[RESIZE2]]251// CHECK-NEXT: [[DOWNSCALE:%.*]] = ashr i32 [[TMP5]], 15252// CHECK-NEXT: [[RESIZE3:%.*]] = trunc i32 [[DOWNSCALE]] to i8253// CHECK-NEXT: store i8 [[RESIZE3]], ptr @c, align 1254// CHECK-NEXT: ret void255//256void add_ca(void) {257 c += a;258}259 260// CHECK-LABEL: @add_sai(261// CHECK-NEXT: entry:262// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @i, align 4263// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @sa, align 4264// CHECK-NEXT: [[RESIZE:%.*]] = sext i32 [[TMP1]] to i47265// CHECK-NEXT: [[RESIZE1:%.*]] = sext i32 [[TMP0]] to i47266// CHECK-NEXT: [[UPSCALE:%.*]] = shl i47 [[RESIZE1]], 15267// CHECK-NEXT: [[TMP2:%.*]] = call i47 @llvm.sadd.sat.i47(i47 [[RESIZE]], i47 [[UPSCALE]])268// CHECK-NEXT: [[TMP3:%.*]] = icmp sgt i47 [[TMP2]], 2147483647269// CHECK-NEXT: [[SATMAX:%.*]] = select i1 [[TMP3]], i47 2147483647, i47 [[TMP2]]270// CHECK-NEXT: [[TMP4:%.*]] = icmp slt i47 [[SATMAX]], -2147483648271// CHECK-NEXT: [[SATMIN:%.*]] = select i1 [[TMP4]], i47 -2147483648, i47 [[SATMAX]]272// CHECK-NEXT: [[RESIZE2:%.*]] = trunc i47 [[SATMIN]] to i32273// CHECK-NEXT: store i32 [[RESIZE2]], ptr @sa, align 4274// CHECK-NEXT: ret void275//276void add_sai(void) {277 sa += i;278}279 280// CHECK-LABEL: @add_csa(281// CHECK-NEXT: entry:282// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @sa, align 4283// CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr @c, align 1284// CHECK-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32285// CHECK-NEXT: [[RESIZE:%.*]] = sext i32 [[CONV]] to i47286// CHECK-NEXT: [[UPSCALE:%.*]] = shl i47 [[RESIZE]], 15287// CHECK-NEXT: [[RESIZE1:%.*]] = sext i32 [[TMP0]] to i47288// CHECK-NEXT: [[TMP2:%.*]] = call i47 @llvm.sadd.sat.i47(i47 [[UPSCALE]], i47 [[RESIZE1]])289// CHECK-NEXT: [[TMP3:%.*]] = icmp sgt i47 [[TMP2]], 2147483647290// CHECK-NEXT: [[SATMAX:%.*]] = select i1 [[TMP3]], i47 2147483647, i47 [[TMP2]]291// CHECK-NEXT: [[TMP4:%.*]] = icmp slt i47 [[SATMAX]], -2147483648292// CHECK-NEXT: [[SATMIN:%.*]] = select i1 [[TMP4]], i47 -2147483648, i47 [[SATMAX]]293// CHECK-NEXT: [[RESIZE2:%.*]] = trunc i47 [[SATMIN]] to i32294// CHECK-NEXT: [[TMP5:%.*]] = icmp slt i32 [[RESIZE2]], 0295// CHECK-NEXT: [[TMP6:%.*]] = add i32 [[RESIZE2]], 32767296// CHECK-NEXT: [[TMP7:%.*]] = select i1 [[TMP5]], i32 [[TMP6]], i32 [[RESIZE2]]297// CHECK-NEXT: [[DOWNSCALE:%.*]] = ashr i32 [[TMP7]], 15298// CHECK-NEXT: [[RESIZE3:%.*]] = trunc i32 [[DOWNSCALE]] to i8299// CHECK-NEXT: store i8 [[RESIZE3]], ptr @c, align 1300// CHECK-NEXT: ret void301//302void add_csa(void) {303 c += sa;304}305 306// SIGNED-LABEL: @add_sulau(307// SIGNED-NEXT: entry:308// SIGNED-NEXT: [[TMP0:%.*]] = load i32, ptr @u, align 4309// SIGNED-NEXT: [[TMP1:%.*]] = load i64, ptr @sula, align 8310// SIGNED-NEXT: [[RESIZE:%.*]] = zext i32 [[TMP0]] to i64311// SIGNED-NEXT: [[UPSCALE:%.*]] = shl i64 [[RESIZE]], 32312// SIGNED-NEXT: [[TMP2:%.*]] = call i64 @llvm.uadd.sat.i64(i64 [[TMP1]], i64 [[UPSCALE]])313// SIGNED-NEXT: store i64 [[TMP2]], ptr @sula, align 8314// SIGNED-NEXT: ret void315//316// UNSIGNED-LABEL: @add_sulau(317// UNSIGNED-NEXT: entry:318// UNSIGNED-NEXT: [[TMP0:%.*]] = load i32, ptr @u, align 4319// UNSIGNED-NEXT: [[TMP1:%.*]] = load i64, ptr @sula, align 8320// UNSIGNED-NEXT: [[RESIZE:%.*]] = trunc i64 [[TMP1]] to i63321// UNSIGNED-NEXT: [[RESIZE1:%.*]] = zext i32 [[TMP0]] to i63322// UNSIGNED-NEXT: [[UPSCALE:%.*]] = shl i63 [[RESIZE1]], 31323// UNSIGNED-NEXT: [[TMP2:%.*]] = call i63 @llvm.uadd.sat.i63(i63 [[RESIZE]], i63 [[UPSCALE]])324// UNSIGNED-NEXT: [[RESIZE2:%.*]] = zext i63 [[TMP2]] to i64325// UNSIGNED-NEXT: store i64 [[RESIZE2]], ptr @sula, align 8326// UNSIGNED-NEXT: ret void327//328void add_sulau(void) {329 sula += u;330}331 332// SIGNED-LABEL: @add_sshsuf(333// SIGNED-NEXT: entry:334// SIGNED-NEXT: [[TMP0:%.*]] = load i16, ptr @suf, align 2335// SIGNED-NEXT: [[TMP1:%.*]] = load i8, ptr @sshf, align 1336// SIGNED-NEXT: [[RESIZE:%.*]] = sext i8 [[TMP1]] to i17337// SIGNED-NEXT: [[UPSCALE:%.*]] = shl i17 [[RESIZE]], 9338// SIGNED-NEXT: [[RESIZE1:%.*]] = zext i16 [[TMP0]] to i17339// SIGNED-NEXT: [[TMP2:%.*]] = call i17 @llvm.sadd.sat.i17(i17 [[UPSCALE]], i17 [[RESIZE1]])340// SIGNED-NEXT: [[DOWNSCALE:%.*]] = ashr i17 [[TMP2]], 1341// SIGNED-NEXT: [[RESIZE2:%.*]] = trunc i17 [[DOWNSCALE]] to i16342// SIGNED-NEXT: [[DOWNSCALE3:%.*]] = ashr i16 [[RESIZE2]], 8343// SIGNED-NEXT: [[RESIZE4:%.*]] = trunc i16 [[DOWNSCALE3]] to i8344// SIGNED-NEXT: store i8 [[RESIZE4]], ptr @sshf, align 1345// SIGNED-NEXT: ret void346//347// UNSIGNED-LABEL: @add_sshsuf(348// UNSIGNED-NEXT: entry:349// UNSIGNED-NEXT: [[TMP0:%.*]] = load i16, ptr @suf, align 2350// UNSIGNED-NEXT: [[TMP1:%.*]] = load i8, ptr @sshf, align 1351// UNSIGNED-NEXT: [[RESIZE:%.*]] = sext i8 [[TMP1]] to i16352// UNSIGNED-NEXT: [[UPSCALE:%.*]] = shl i16 [[RESIZE]], 8353// UNSIGNED-NEXT: [[TMP2:%.*]] = call i16 @llvm.sadd.sat.i16(i16 [[UPSCALE]], i16 [[TMP0]])354// UNSIGNED-NEXT: [[DOWNSCALE:%.*]] = ashr i16 [[TMP2]], 8355// UNSIGNED-NEXT: [[RESIZE1:%.*]] = trunc i16 [[DOWNSCALE]] to i8356// UNSIGNED-NEXT: store i8 [[RESIZE1]], ptr @sshf, align 1357// UNSIGNED-NEXT: ret void358//359void add_sshsuf(void) {360 sshf += suf;361}362 363// CHECK-LABEL: @add_afl(364// CHECK-NEXT: entry:365// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr @fl, align 4366// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @a, align 4367// CHECK-NEXT: [[TMP2:%.*]] = sitofp i32 [[TMP1]] to float368// CHECK-NEXT: [[TMP3:%.*]] = fmul float [[TMP2]], 0x3F00000000000000369// CHECK-NEXT: [[ADD:%.*]] = fadd float [[TMP3]], [[TMP0]]370// CHECK-NEXT: [[TMP4:%.*]] = fmul float [[ADD]], 3.276800e+04371// CHECK-NEXT: [[TMP5:%.*]] = fptosi float [[TMP4]] to i32372// CHECK-NEXT: store i32 [[TMP5]], ptr @a, align 4373// CHECK-NEXT: ret void374//375void add_afl(void) {376 a += fl;377}378 379// CHECK-LABEL: @add_fla(380// CHECK-NEXT: entry:381// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @a, align 4382// CHECK-NEXT: [[TMP1:%.*]] = sitofp i32 [[TMP0]] to float383// CHECK-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 0x3F00000000000000384// CHECK-NEXT: [[TMP3:%.*]] = load float, ptr @fl, align 4385// CHECK-NEXT: [[ADD:%.*]] = fadd float [[TMP3]], [[TMP2]]386// CHECK-NEXT: store float [[ADD]], ptr @fl, align 4387// CHECK-NEXT: ret void388//389void add_fla(void) {390 fl += a;391}392 393// CHECK-LABEL: @add_safl(394// CHECK-NEXT: entry:395// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr @fl, align 4396// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @sa, align 4397// CHECK-NEXT: [[TMP2:%.*]] = sitofp i32 [[TMP1]] to float398// CHECK-NEXT: [[TMP3:%.*]] = fmul float [[TMP2]], 0x3F00000000000000399// CHECK-NEXT: [[ADD:%.*]] = fadd float [[TMP3]], [[TMP0]]400// CHECK-NEXT: [[TMP4:%.*]] = fmul float [[ADD]], 3.276800e+04401// CHECK-NEXT: [[TMP5:%.*]] = call i32 @llvm.fptosi.sat.i32.f32(float [[TMP4]])402// CHECK-NEXT: store i32 [[TMP5]], ptr @sa, align 4403// CHECK-NEXT: ret void404//405void add_safl(void) {406 sa += fl;407}408 409// CHECK-LABEL: @add_flsa(410// CHECK-NEXT: entry:411// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @sa, align 4412// CHECK-NEXT: [[TMP1:%.*]] = sitofp i32 [[TMP0]] to float413// CHECK-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 0x3F00000000000000414// CHECK-NEXT: [[TMP3:%.*]] = load float, ptr @fl, align 4415// CHECK-NEXT: [[ADD:%.*]] = fadd float [[TMP3]], [[TMP2]]416// CHECK-NEXT: store float [[ADD]], ptr @fl, align 4417// CHECK-NEXT: ret void418//419void add_flsa(void) {420 fl += sa;421}422 423// Subtraction, multiplication and division should work about the same, so424// just make sure we can do them.425 426// SIGNED-LABEL: @sub_auf(427// SIGNED-NEXT: entry:428// SIGNED-NEXT: [[TMP0:%.*]] = load i16, ptr @uf, align 2429// SIGNED-NEXT: [[TMP1:%.*]] = load i32, ptr @a, align 4430// SIGNED-NEXT: [[RESIZE:%.*]] = sext i32 [[TMP1]] to i33431// SIGNED-NEXT: [[UPSCALE:%.*]] = shl i33 [[RESIZE]], 1432// SIGNED-NEXT: [[RESIZE1:%.*]] = zext i16 [[TMP0]] to i33433// SIGNED-NEXT: [[TMP2:%.*]] = sub i33 [[UPSCALE]], [[RESIZE1]]434// SIGNED-NEXT: [[DOWNSCALE:%.*]] = ashr i33 [[TMP2]], 1435// SIGNED-NEXT: [[RESIZE2:%.*]] = trunc i33 [[DOWNSCALE]] to i32436// SIGNED-NEXT: store i32 [[RESIZE2]], ptr @a, align 4437// SIGNED-NEXT: ret void438//439// UNSIGNED-LABEL: @sub_auf(440// UNSIGNED-NEXT: entry:441// UNSIGNED-NEXT: [[TMP0:%.*]] = load i16, ptr @uf, align 2442// UNSIGNED-NEXT: [[TMP1:%.*]] = load i32, ptr @a, align 4443// UNSIGNED-NEXT: [[RESIZE:%.*]] = zext i16 [[TMP0]] to i32444// UNSIGNED-NEXT: [[TMP2:%.*]] = sub i32 [[TMP1]], [[RESIZE]]445// UNSIGNED-NEXT: store i32 [[TMP2]], ptr @a, align 4446// UNSIGNED-NEXT: ret void447//448void sub_auf(void) {449 a -= uf;450}451 452// CHECK-LABEL: @sub_ai(453// CHECK-NEXT: entry:454// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @i, align 4455// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @a, align 4456// CHECK-NEXT: [[RESIZE:%.*]] = sext i32 [[TMP1]] to i47457// CHECK-NEXT: [[RESIZE1:%.*]] = sext i32 [[TMP0]] to i47458// CHECK-NEXT: [[UPSCALE:%.*]] = shl i47 [[RESIZE1]], 15459// CHECK-NEXT: [[TMP2:%.*]] = sub i47 [[RESIZE]], [[UPSCALE]]460// CHECK-NEXT: [[RESIZE2:%.*]] = trunc i47 [[TMP2]] to i32461// CHECK-NEXT: store i32 [[RESIZE2]], ptr @a, align 4462// CHECK-NEXT: ret void463//464void sub_ai(void) {465 a -= i;466}467 468// CHECK-LABEL: @sub_csa(469// CHECK-NEXT: entry:470// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @sa, align 4471// CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr @c, align 1472// CHECK-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32473// CHECK-NEXT: [[RESIZE:%.*]] = sext i32 [[CONV]] to i47474// CHECK-NEXT: [[UPSCALE:%.*]] = shl i47 [[RESIZE]], 15475// CHECK-NEXT: [[RESIZE1:%.*]] = sext i32 [[TMP0]] to i47476// CHECK-NEXT: [[TMP2:%.*]] = call i47 @llvm.ssub.sat.i47(i47 [[UPSCALE]], i47 [[RESIZE1]])477// CHECK-NEXT: [[TMP3:%.*]] = icmp sgt i47 [[TMP2]], 2147483647478// CHECK-NEXT: [[SATMAX:%.*]] = select i1 [[TMP3]], i47 2147483647, i47 [[TMP2]]479// CHECK-NEXT: [[TMP4:%.*]] = icmp slt i47 [[SATMAX]], -2147483648480// CHECK-NEXT: [[SATMIN:%.*]] = select i1 [[TMP4]], i47 -2147483648, i47 [[SATMAX]]481// CHECK-NEXT: [[RESIZE2:%.*]] = trunc i47 [[SATMIN]] to i32482// CHECK-NEXT: [[TMP5:%.*]] = icmp slt i32 [[RESIZE2]], 0483// CHECK-NEXT: [[TMP6:%.*]] = add i32 [[RESIZE2]], 32767484// CHECK-NEXT: [[TMP7:%.*]] = select i1 [[TMP5]], i32 [[TMP6]], i32 [[RESIZE2]]485// CHECK-NEXT: [[DOWNSCALE:%.*]] = ashr i32 [[TMP7]], 15486// CHECK-NEXT: [[RESIZE3:%.*]] = trunc i32 [[DOWNSCALE]] to i8487// CHECK-NEXT: store i8 [[RESIZE3]], ptr @c, align 1488// CHECK-NEXT: ret void489//490void sub_csa(void) {491 c -= sa;492}493 494// CHECK-LABEL: @sub_afl(495// CHECK-NEXT: entry:496// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr @fl, align 4497// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @a, align 4498// CHECK-NEXT: [[TMP2:%.*]] = sitofp i32 [[TMP1]] to float499// CHECK-NEXT: [[TMP3:%.*]] = fmul float [[TMP2]], 0x3F00000000000000500// CHECK-NEXT: [[SUB:%.*]] = fsub float [[TMP3]], [[TMP0]]501// CHECK-NEXT: [[TMP4:%.*]] = fmul float [[SUB]], 3.276800e+04502// CHECK-NEXT: [[TMP5:%.*]] = fptosi float [[TMP4]] to i32503// CHECK-NEXT: store i32 [[TMP5]], ptr @a, align 4504// CHECK-NEXT: ret void505//506void sub_afl(void) {507 a -= fl;508}509 510 511// SIGNED-LABEL: @mul_auf(512// SIGNED-NEXT: entry:513// SIGNED-NEXT: [[TMP0:%.*]] = load i16, ptr @uf, align 2514// SIGNED-NEXT: [[TMP1:%.*]] = load i32, ptr @a, align 4515// SIGNED-NEXT: [[RESIZE:%.*]] = sext i32 [[TMP1]] to i33516// SIGNED-NEXT: [[UPSCALE:%.*]] = shl i33 [[RESIZE]], 1517// SIGNED-NEXT: [[RESIZE1:%.*]] = zext i16 [[TMP0]] to i33518// SIGNED-NEXT: [[TMP2:%.*]] = call i33 @llvm.smul.fix.i33(i33 [[UPSCALE]], i33 [[RESIZE1]], i32 16)519// SIGNED-NEXT: [[DOWNSCALE:%.*]] = ashr i33 [[TMP2]], 1520// SIGNED-NEXT: [[RESIZE2:%.*]] = trunc i33 [[DOWNSCALE]] to i32521// SIGNED-NEXT: store i32 [[RESIZE2]], ptr @a, align 4522// SIGNED-NEXT: ret void523//524// UNSIGNED-LABEL: @mul_auf(525// UNSIGNED-NEXT: entry:526// UNSIGNED-NEXT: [[TMP0:%.*]] = load i16, ptr @uf, align 2527// UNSIGNED-NEXT: [[TMP1:%.*]] = load i32, ptr @a, align 4528// UNSIGNED-NEXT: [[RESIZE:%.*]] = zext i16 [[TMP0]] to i32529// UNSIGNED-NEXT: [[TMP2:%.*]] = call i32 @llvm.smul.fix.i32(i32 [[TMP1]], i32 [[RESIZE]], i32 15)530// UNSIGNED-NEXT: store i32 [[TMP2]], ptr @a, align 4531// UNSIGNED-NEXT: ret void532//533void mul_auf(void) {534 a *= uf;535}536 537// CHECK-LABEL: @mul_ai(538// CHECK-NEXT: entry:539// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @i, align 4540// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @a, align 4541// CHECK-NEXT: [[RESIZE:%.*]] = sext i32 [[TMP1]] to i47542// CHECK-NEXT: [[RESIZE1:%.*]] = sext i32 [[TMP0]] to i47543// CHECK-NEXT: [[UPSCALE:%.*]] = shl i47 [[RESIZE1]], 15544// CHECK-NEXT: [[TMP2:%.*]] = call i47 @llvm.smul.fix.i47(i47 [[RESIZE]], i47 [[UPSCALE]], i32 15)545// CHECK-NEXT: [[RESIZE2:%.*]] = trunc i47 [[TMP2]] to i32546// CHECK-NEXT: store i32 [[RESIZE2]], ptr @a, align 4547// CHECK-NEXT: ret void548//549void mul_ai(void) {550 a *= i;551}552 553// CHECK-LABEL: @mul_csa(554// CHECK-NEXT: entry:555// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @sa, align 4556// CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr @c, align 1557// CHECK-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32558// CHECK-NEXT: [[RESIZE:%.*]] = sext i32 [[CONV]] to i47559// CHECK-NEXT: [[UPSCALE:%.*]] = shl i47 [[RESIZE]], 15560// CHECK-NEXT: [[RESIZE1:%.*]] = sext i32 [[TMP0]] to i47561// CHECK-NEXT: [[TMP2:%.*]] = call i47 @llvm.smul.fix.sat.i47(i47 [[UPSCALE]], i47 [[RESIZE1]], i32 15)562// CHECK-NEXT: [[TMP3:%.*]] = icmp sgt i47 [[TMP2]], 2147483647563// CHECK-NEXT: [[SATMAX:%.*]] = select i1 [[TMP3]], i47 2147483647, i47 [[TMP2]]564// CHECK-NEXT: [[TMP4:%.*]] = icmp slt i47 [[SATMAX]], -2147483648565// CHECK-NEXT: [[SATMIN:%.*]] = select i1 [[TMP4]], i47 -2147483648, i47 [[SATMAX]]566// CHECK-NEXT: [[RESIZE2:%.*]] = trunc i47 [[SATMIN]] to i32567// CHECK-NEXT: [[TMP5:%.*]] = icmp slt i32 [[RESIZE2]], 0568// CHECK-NEXT: [[TMP6:%.*]] = add i32 [[RESIZE2]], 32767569// CHECK-NEXT: [[TMP7:%.*]] = select i1 [[TMP5]], i32 [[TMP6]], i32 [[RESIZE2]]570// CHECK-NEXT: [[DOWNSCALE:%.*]] = ashr i32 [[TMP7]], 15571// CHECK-NEXT: [[RESIZE3:%.*]] = trunc i32 [[DOWNSCALE]] to i8572// CHECK-NEXT: store i8 [[RESIZE3]], ptr @c, align 1573// CHECK-NEXT: ret void574//575void mul_csa(void) {576 c *= sa;577}578 579// CHECK-LABEL: @mul_afl(580// CHECK-NEXT: entry:581// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr @fl, align 4582// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @a, align 4583// CHECK-NEXT: [[TMP2:%.*]] = sitofp i32 [[TMP1]] to float584// CHECK-NEXT: [[TMP3:%.*]] = fmul float [[TMP2]], 0x3F00000000000000585// CHECK-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP0]]586// CHECK-NEXT: [[TMP4:%.*]] = fmul float [[MUL]], 3.276800e+04587// CHECK-NEXT: [[TMP5:%.*]] = fptosi float [[TMP4]] to i32588// CHECK-NEXT: store i32 [[TMP5]], ptr @a, align 4589// CHECK-NEXT: ret void590//591void mul_afl(void) {592 a *= fl;593}594 595 596// SIGNED-LABEL: @div_auf(597// SIGNED-NEXT: entry:598// SIGNED-NEXT: [[TMP0:%.*]] = load i16, ptr @uf, align 2599// SIGNED-NEXT: [[TMP1:%.*]] = load i32, ptr @a, align 4600// SIGNED-NEXT: [[RESIZE:%.*]] = sext i32 [[TMP1]] to i33601// SIGNED-NEXT: [[UPSCALE:%.*]] = shl i33 [[RESIZE]], 1602// SIGNED-NEXT: [[RESIZE1:%.*]] = zext i16 [[TMP0]] to i33603// SIGNED-NEXT: [[TMP2:%.*]] = call i33 @llvm.sdiv.fix.i33(i33 [[UPSCALE]], i33 [[RESIZE1]], i32 16)604// SIGNED-NEXT: [[DOWNSCALE:%.*]] = ashr i33 [[TMP2]], 1605// SIGNED-NEXT: [[RESIZE2:%.*]] = trunc i33 [[DOWNSCALE]] to i32606// SIGNED-NEXT: store i32 [[RESIZE2]], ptr @a, align 4607// SIGNED-NEXT: ret void608//609// UNSIGNED-LABEL: @div_auf(610// UNSIGNED-NEXT: entry:611// UNSIGNED-NEXT: [[TMP0:%.*]] = load i16, ptr @uf, align 2612// UNSIGNED-NEXT: [[TMP1:%.*]] = load i32, ptr @a, align 4613// UNSIGNED-NEXT: [[RESIZE:%.*]] = zext i16 [[TMP0]] to i32614// UNSIGNED-NEXT: [[TMP2:%.*]] = call i32 @llvm.sdiv.fix.i32(i32 [[TMP1]], i32 [[RESIZE]], i32 15)615// UNSIGNED-NEXT: store i32 [[TMP2]], ptr @a, align 4616// UNSIGNED-NEXT: ret void617//618void div_auf(void) {619 a /= uf;620}621 622// CHECK-LABEL: @div_ai(623// CHECK-NEXT: entry:624// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @i, align 4625// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @a, align 4626// CHECK-NEXT: [[RESIZE:%.*]] = sext i32 [[TMP1]] to i47627// CHECK-NEXT: [[RESIZE1:%.*]] = sext i32 [[TMP0]] to i47628// CHECK-NEXT: [[UPSCALE:%.*]] = shl i47 [[RESIZE1]], 15629// CHECK-NEXT: [[TMP2:%.*]] = call i47 @llvm.sdiv.fix.i47(i47 [[RESIZE]], i47 [[UPSCALE]], i32 15)630// CHECK-NEXT: [[RESIZE2:%.*]] = trunc i47 [[TMP2]] to i32631// CHECK-NEXT: store i32 [[RESIZE2]], ptr @a, align 4632// CHECK-NEXT: ret void633//634void div_ai(void) {635 a /= i;636}637 638// CHECK-LABEL: @div_csa(639// CHECK-NEXT: entry:640// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @sa, align 4641// CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr @c, align 1642// CHECK-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32643// CHECK-NEXT: [[RESIZE:%.*]] = sext i32 [[CONV]] to i47644// CHECK-NEXT: [[UPSCALE:%.*]] = shl i47 [[RESIZE]], 15645// CHECK-NEXT: [[RESIZE1:%.*]] = sext i32 [[TMP0]] to i47646// CHECK-NEXT: [[TMP2:%.*]] = call i47 @llvm.sdiv.fix.sat.i47(i47 [[UPSCALE]], i47 [[RESIZE1]], i32 15)647// CHECK-NEXT: [[TMP3:%.*]] = icmp sgt i47 [[TMP2]], 2147483647648// CHECK-NEXT: [[SATMAX:%.*]] = select i1 [[TMP3]], i47 2147483647, i47 [[TMP2]]649// CHECK-NEXT: [[TMP4:%.*]] = icmp slt i47 [[SATMAX]], -2147483648650// CHECK-NEXT: [[SATMIN:%.*]] = select i1 [[TMP4]], i47 -2147483648, i47 [[SATMAX]]651// CHECK-NEXT: [[RESIZE2:%.*]] = trunc i47 [[SATMIN]] to i32652// CHECK-NEXT: [[TMP5:%.*]] = icmp slt i32 [[RESIZE2]], 0653// CHECK-NEXT: [[TMP6:%.*]] = add i32 [[RESIZE2]], 32767654// CHECK-NEXT: [[TMP7:%.*]] = select i1 [[TMP5]], i32 [[TMP6]], i32 [[RESIZE2]]655// CHECK-NEXT: [[DOWNSCALE:%.*]] = ashr i32 [[TMP7]], 15656// CHECK-NEXT: [[RESIZE3:%.*]] = trunc i32 [[DOWNSCALE]] to i8657// CHECK-NEXT: store i8 [[RESIZE3]], ptr @c, align 1658// CHECK-NEXT: ret void659//660void div_csa(void) {661 c /= sa;662}663 664// CHECK-LABEL: @div_afl(665// CHECK-NEXT: entry:666// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr @fl, align 4667// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @a, align 4668// CHECK-NEXT: [[TMP2:%.*]] = sitofp i32 [[TMP1]] to float669// CHECK-NEXT: [[TMP3:%.*]] = fmul float [[TMP2]], 0x3F00000000000000670// CHECK-NEXT: [[DIV:%.*]] = fdiv float [[TMP3]], [[TMP0]]671// CHECK-NEXT: [[TMP4:%.*]] = fmul float [[DIV]], 3.276800e+04672// CHECK-NEXT: [[TMP5:%.*]] = fptosi float [[TMP4]] to i32673// CHECK-NEXT: store i32 [[TMP5]], ptr @a, align 4674// CHECK-NEXT: ret void675//676void div_afl(void) {677 a /= fl;678}679 680 681// CHECK-LABEL: @shft_ai(682// CHECK-NEXT: entry:683// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @i, align 4684// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @a, align 4685// CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[TMP1]], [[TMP0]]686// CHECK-NEXT: store i32 [[TMP2]], ptr @a, align 4687// CHECK-NEXT: ret void688//689void shft_ai(void) {690 a <<= i;691}692 693// SIGNED-LABEL: @shft_sufi(694// SIGNED-NEXT: entry:695// SIGNED-NEXT: [[TMP0:%.*]] = load i32, ptr @i, align 4696// SIGNED-NEXT: [[TMP1:%.*]] = load i16, ptr @suf, align 2697// SIGNED-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP0]] to i16698// SIGNED-NEXT: [[TMP3:%.*]] = call i16 @llvm.ushl.sat.i16(i16 [[TMP1]], i16 [[TMP2]])699// SIGNED-NEXT: store i16 [[TMP3]], ptr @suf, align 2700// SIGNED-NEXT: ret void701//702// UNSIGNED-LABEL: @shft_sufi(703// UNSIGNED-NEXT: entry:704// UNSIGNED-NEXT: [[TMP0:%.*]] = load i32, ptr @i, align 4705// UNSIGNED-NEXT: [[TMP1:%.*]] = load i16, ptr @suf, align 2706// UNSIGNED-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP0]] to i16707// UNSIGNED-NEXT: [[TMP3:%.*]] = call i16 @llvm.sshl.sat.i16(i16 [[TMP1]], i16 [[TMP2]])708// UNSIGNED-NEXT: store i16 [[TMP3]], ptr @suf, align 2709// UNSIGNED-NEXT: ret void710//711void shft_sufi(void) {712 suf <<= i;713}714 715// CHECK-LABEL: @shft_ulai(716// CHECK-NEXT: entry:717// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @i, align 4718// CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @ula, align 8719// CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP0]] to i64720// CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP1]], [[TMP2]]721// CHECK-NEXT: store i64 [[TMP3]], ptr @ula, align 8722// CHECK-NEXT: ret void723//724void shft_ulai(void) {725 ula >>= i;726}727