310 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py2// RUN: %clang_cc1 -ffixed-point -triple arm64-unknown-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,SIGNED3// RUN: %clang_cc1 -ffixed-point -triple arm64-unknown-linux-gnu -emit-llvm %s -o - -fpadding-on-unsigned-fixed-point | FileCheck %s --check-prefixes=CHECK,UNSIGNED4 5short _Fract sf;6long _Fract lf;7 8short _Accum sa;9long _Accum la;10 11unsigned short _Accum usa;12unsigned long _Accum ula;13 14_Sat short _Fract sf_sat;15_Sat long _Fract lf_sat;16 17_Sat short _Accum sa_sat;18_Sat long _Accum la_sat;19 20_Sat unsigned short _Accum usa_sat;21_Sat unsigned long _Accum ula_sat;22 23_Float16 h;24 25 26// CHECK-LABEL: @half_fix1(27// CHECK-NEXT: entry:28// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr @h, align 229// CHECK-NEXT: [[TMP1:%.*]] = fmul half [[TMP0]], 0xH580030// CHECK-NEXT: [[TMP2:%.*]] = fptosi half [[TMP1]] to i831// CHECK-NEXT: store i8 [[TMP2]], ptr @sf, align 132// CHECK-NEXT: ret void33//34void half_fix1(void) {35 sf = h;36}37 38// CHECK-LABEL: @half_fix2(39// CHECK-NEXT: entry:40// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr @h, align 241// CHECK-NEXT: [[TMP1:%.*]] = fpext half [[TMP0]] to float42// CHECK-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 0x41E000000000000043// CHECK-NEXT: [[TMP3:%.*]] = fptosi float [[TMP2]] to i3244// CHECK-NEXT: store i32 [[TMP3]], ptr @lf, align 445// CHECK-NEXT: ret void46//47void half_fix2(void) {48 lf = h;49}50 51// CHECK-LABEL: @half_fix3(52// CHECK-NEXT: entry:53// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr @h, align 254// CHECK-NEXT: [[TMP1:%.*]] = fmul half [[TMP0]], 0xH580055// CHECK-NEXT: [[TMP2:%.*]] = fptosi half [[TMP1]] to i1656// CHECK-NEXT: store i16 [[TMP2]], ptr @sa, align 257// CHECK-NEXT: ret void58//59void half_fix3(void) {60 sa = h;61}62 63// CHECK-LABEL: @half_fix4(64// CHECK-NEXT: entry:65// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr @h, align 266// CHECK-NEXT: [[TMP1:%.*]] = fpext half [[TMP0]] to float67// CHECK-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 0x41E000000000000068// CHECK-NEXT: [[TMP3:%.*]] = fptosi float [[TMP2]] to i6469// CHECK-NEXT: store i64 [[TMP3]], ptr @la, align 870// CHECK-NEXT: ret void71//72void half_fix4(void) {73 la = h;74}75 76// SIGNED-LABEL: @half_fix5(77// SIGNED-NEXT: entry:78// SIGNED-NEXT: [[TMP0:%.*]] = load half, ptr @h, align 279// SIGNED-NEXT: [[TMP1:%.*]] = fpext half [[TMP0]] to float80// SIGNED-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 2.560000e+0281// SIGNED-NEXT: [[TMP3:%.*]] = fptoui float [[TMP2]] to i1682// SIGNED-NEXT: store i16 [[TMP3]], ptr @usa, align 283// SIGNED-NEXT: ret void84//85// UNSIGNED-LABEL: @half_fix5(86// UNSIGNED-NEXT: entry:87// UNSIGNED-NEXT: [[TMP0:%.*]] = load half, ptr @h, align 288// UNSIGNED-NEXT: [[TMP1:%.*]] = fmul half [[TMP0]], 0xH580089// UNSIGNED-NEXT: [[TMP2:%.*]] = fptosi half [[TMP1]] to i1690// UNSIGNED-NEXT: store i16 [[TMP2]], ptr @usa, align 291// UNSIGNED-NEXT: ret void92//93void half_fix5(void) {94 usa = h;95}96 97// SIGNED-LABEL: @half_fix6(98// SIGNED-NEXT: entry:99// SIGNED-NEXT: [[TMP0:%.*]] = load half, ptr @h, align 2100// SIGNED-NEXT: [[TMP1:%.*]] = fpext half [[TMP0]] to float101// SIGNED-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 0x41F0000000000000102// SIGNED-NEXT: [[TMP3:%.*]] = fptoui float [[TMP2]] to i64103// SIGNED-NEXT: store i64 [[TMP3]], ptr @ula, align 8104// SIGNED-NEXT: ret void105//106// UNSIGNED-LABEL: @half_fix6(107// UNSIGNED-NEXT: entry:108// UNSIGNED-NEXT: [[TMP0:%.*]] = load half, ptr @h, align 2109// UNSIGNED-NEXT: [[TMP1:%.*]] = fpext half [[TMP0]] to float110// UNSIGNED-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 0x41E0000000000000111// UNSIGNED-NEXT: [[TMP3:%.*]] = fptosi float [[TMP2]] to i64112// UNSIGNED-NEXT: store i64 [[TMP3]], ptr @ula, align 8113// UNSIGNED-NEXT: ret void114//115void half_fix6(void) {116 ula = h;117}118 119 120// CHECK-LABEL: @half_sat1(121// CHECK-NEXT: entry:122// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr @h, align 2123// CHECK-NEXT: [[TMP1:%.*]] = fmul half [[TMP0]], 0xH5800124// CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.fptosi.sat.i8.f16(half [[TMP1]])125// CHECK-NEXT: store i8 [[TMP2]], ptr @sf_sat, align 1126// CHECK-NEXT: ret void127//128void half_sat1(void) {129 sf_sat = h;130}131 132// CHECK-LABEL: @half_sat2(133// CHECK-NEXT: entry:134// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr @h, align 2135// CHECK-NEXT: [[TMP1:%.*]] = fpext half [[TMP0]] to float136// CHECK-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 0x41E0000000000000137// CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.fptosi.sat.i32.f32(float [[TMP2]])138// CHECK-NEXT: store i32 [[TMP3]], ptr @lf_sat, align 4139// CHECK-NEXT: ret void140//141void half_sat2(void) {142 lf_sat = h;143}144 145// CHECK-LABEL: @half_sat3(146// CHECK-NEXT: entry:147// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr @h, align 2148// CHECK-NEXT: [[TMP1:%.*]] = fmul half [[TMP0]], 0xH5800149// CHECK-NEXT: [[TMP2:%.*]] = call i16 @llvm.fptosi.sat.i16.f16(half [[TMP1]])150// CHECK-NEXT: store i16 [[TMP2]], ptr @sa_sat, align 2151// CHECK-NEXT: ret void152//153void half_sat3(void) {154 sa_sat = h;155}156 157// CHECK-LABEL: @half_sat4(158// CHECK-NEXT: entry:159// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr @h, align 2160// CHECK-NEXT: [[TMP1:%.*]] = fpext half [[TMP0]] to float161// CHECK-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 0x41E0000000000000162// CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.fptosi.sat.i64.f32(float [[TMP2]])163// CHECK-NEXT: store i64 [[TMP3]], ptr @la_sat, align 8164// CHECK-NEXT: ret void165//166void half_sat4(void) {167 la_sat = h;168}169 170// SIGNED-LABEL: @half_sat5(171// SIGNED-NEXT: entry:172// SIGNED-NEXT: [[TMP0:%.*]] = load half, ptr @h, align 2173// SIGNED-NEXT: [[TMP1:%.*]] = fpext half [[TMP0]] to float174// SIGNED-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 2.560000e+02175// SIGNED-NEXT: [[TMP3:%.*]] = call i16 @llvm.fptoui.sat.i16.f32(float [[TMP2]])176// SIGNED-NEXT: store i16 [[TMP3]], ptr @usa_sat, align 2177// SIGNED-NEXT: ret void178//179// UNSIGNED-LABEL: @half_sat5(180// UNSIGNED-NEXT: entry:181// UNSIGNED-NEXT: [[TMP0:%.*]] = load half, ptr @h, align 2182// UNSIGNED-NEXT: [[TMP1:%.*]] = fmul half [[TMP0]], 0xH5800183// UNSIGNED-NEXT: [[TMP2:%.*]] = call i16 @llvm.fptosi.sat.i16.f16(half [[TMP1]])184// UNSIGNED-NEXT: [[TMP3:%.*]] = icmp slt i16 [[TMP2]], 0185// UNSIGNED-NEXT: [[SATMIN:%.*]] = select i1 [[TMP3]], i16 0, i16 [[TMP2]]186// UNSIGNED-NEXT: store i16 [[SATMIN]], ptr @usa_sat, align 2187// UNSIGNED-NEXT: ret void188//189void half_sat5(void) {190 usa_sat = h;191}192 193// SIGNED-LABEL: @half_sat6(194// SIGNED-NEXT: entry:195// SIGNED-NEXT: [[TMP0:%.*]] = load half, ptr @h, align 2196// SIGNED-NEXT: [[TMP1:%.*]] = fpext half [[TMP0]] to float197// SIGNED-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 0x41F0000000000000198// SIGNED-NEXT: [[TMP3:%.*]] = call i64 @llvm.fptoui.sat.i64.f32(float [[TMP2]])199// SIGNED-NEXT: store i64 [[TMP3]], ptr @ula_sat, align 8200// SIGNED-NEXT: ret void201//202// UNSIGNED-LABEL: @half_sat6(203// UNSIGNED-NEXT: entry:204// UNSIGNED-NEXT: [[TMP0:%.*]] = load half, ptr @h, align 2205// UNSIGNED-NEXT: [[TMP1:%.*]] = fpext half [[TMP0]] to float206// UNSIGNED-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 0x41E0000000000000207// UNSIGNED-NEXT: [[TMP3:%.*]] = call i64 @llvm.fptosi.sat.i64.f32(float [[TMP2]])208// UNSIGNED-NEXT: [[TMP4:%.*]] = icmp slt i64 [[TMP3]], 0209// UNSIGNED-NEXT: [[SATMIN:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]210// UNSIGNED-NEXT: store i64 [[SATMIN]], ptr @ula_sat, align 8211// UNSIGNED-NEXT: ret void212//213void half_sat6(void) {214 ula_sat = h;215}216 217 218// CHECK-LABEL: @fix_half1(219// CHECK-NEXT: entry:220// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr @sf, align 1221// CHECK-NEXT: [[TMP1:%.*]] = sitofp i8 [[TMP0]] to half222// CHECK-NEXT: [[TMP2:%.*]] = fmul half [[TMP1]], 0xH2000223// CHECK-NEXT: store half [[TMP2]], ptr @h, align 2224// CHECK-NEXT: ret void225//226void fix_half1(void) {227 h = sf;228}229 230// CHECK-LABEL: @fix_half2(231// CHECK-NEXT: entry:232// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @lf, align 4233// CHECK-NEXT: [[TMP1:%.*]] = sitofp i32 [[TMP0]] to float234// CHECK-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 0x3E00000000000000235// CHECK-NEXT: [[TMP3:%.*]] = fptrunc float [[TMP2]] to half236// CHECK-NEXT: store half [[TMP3]], ptr @h, align 2237// CHECK-NEXT: ret void238//239void fix_half2(void) {240 h = lf;241}242 243// CHECK-LABEL: @fix_half3(244// CHECK-NEXT: entry:245// CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr @sa, align 2246// CHECK-NEXT: [[TMP1:%.*]] = sitofp i16 [[TMP0]] to half247// CHECK-NEXT: [[TMP2:%.*]] = fmul half [[TMP1]], 0xH2000248// CHECK-NEXT: store half [[TMP2]], ptr @h, align 2249// CHECK-NEXT: ret void250//251void fix_half3(void) {252 h = sa;253}254 255// CHECK-LABEL: @fix_half4(256// CHECK-NEXT: entry:257// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @la, align 8258// CHECK-NEXT: [[TMP1:%.*]] = sitofp i64 [[TMP0]] to float259// CHECK-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 0x3E00000000000000260// CHECK-NEXT: [[TMP3:%.*]] = fptrunc float [[TMP2]] to half261// CHECK-NEXT: store half [[TMP3]], ptr @h, align 2262// CHECK-NEXT: ret void263//264void fix_half4(void) {265 h = la;266}267 268// SIGNED-LABEL: @fix_half5(269// SIGNED-NEXT: entry:270// SIGNED-NEXT: [[TMP0:%.*]] = load i16, ptr @usa, align 2271// SIGNED-NEXT: [[TMP1:%.*]] = uitofp i16 [[TMP0]] to float272// SIGNED-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 3.906250e-03273// SIGNED-NEXT: [[TMP3:%.*]] = fptrunc float [[TMP2]] to half274// SIGNED-NEXT: store half [[TMP3]], ptr @h, align 2275// SIGNED-NEXT: ret void276//277// UNSIGNED-LABEL: @fix_half5(278// UNSIGNED-NEXT: entry:279// UNSIGNED-NEXT: [[TMP0:%.*]] = load i16, ptr @usa, align 2280// UNSIGNED-NEXT: [[TMP1:%.*]] = uitofp i16 [[TMP0]] to half281// UNSIGNED-NEXT: [[TMP2:%.*]] = fmul half [[TMP1]], 0xH2000282// UNSIGNED-NEXT: store half [[TMP2]], ptr @h, align 2283// UNSIGNED-NEXT: ret void284//285void fix_half5(void) {286 h = usa;287}288 289// SIGNED-LABEL: @fix_half6(290// SIGNED-NEXT: entry:291// SIGNED-NEXT: [[TMP0:%.*]] = load i64, ptr @ula, align 8292// SIGNED-NEXT: [[TMP1:%.*]] = uitofp i64 [[TMP0]] to float293// SIGNED-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 0x3DF0000000000000294// SIGNED-NEXT: [[TMP3:%.*]] = fptrunc float [[TMP2]] to half295// SIGNED-NEXT: store half [[TMP3]], ptr @h, align 2296// SIGNED-NEXT: ret void297//298// UNSIGNED-LABEL: @fix_half6(299// UNSIGNED-NEXT: entry:300// UNSIGNED-NEXT: [[TMP0:%.*]] = load i64, ptr @ula, align 8301// UNSIGNED-NEXT: [[TMP1:%.*]] = uitofp i64 [[TMP0]] to float302// UNSIGNED-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 0x3E00000000000000303// UNSIGNED-NEXT: [[TMP3:%.*]] = fptrunc float [[TMP2]] to half304// UNSIGNED-NEXT: store half [[TMP3]], ptr @h, align 2305// UNSIGNED-NEXT: ret void306//307void fix_half6(void) {308 h = ula;309}310