945 lines · cpp
1 2// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -target-cpu core2 -fopenmp -fopenmp-version=50 -x c -emit-llvm %s -o - | FileCheck %s3// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -x c -triple x86_64-apple-darwin10 -target-cpu core2 -emit-pch -o %t %s4// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -x c -triple x86_64-apple-darwin10 -target-cpu core2 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix=CHECK --check-prefix=CHECK-50 %s5 6// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -target-cpu core2 -fopenmp-simd -fopenmp-version=50 -x c -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s7// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c -triple x86_64-apple-darwin10 -target-cpu core2 -emit-pch -o %t %s8// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c -triple x86_64-apple-darwin10 -target-cpu core2 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s9 10// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -target-cpu core2 -fopenmp -x c -emit-llvm %s -o - | FileCheck %s11// RUN: %clang_cc1 -fopenmp -x c -triple x86_64-apple-darwin10 -target-cpu core2 -emit-pch -o %t %s12// RUN: %clang_cc1 -fopenmp -x c -triple x86_64-apple-darwin10 -target-cpu core2 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s13 14// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -target-cpu core2 -fopenmp-simd -x c -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s15// RUN: %clang_cc1 -fopenmp-simd -x c -triple x86_64-apple-darwin10 -target-cpu core2 -emit-pch -o %t %s16// RUN: %clang_cc1 -fopenmp-simd -x c -triple x86_64-apple-darwin10 -target-cpu core2 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s17// SIMD-ONLY0-NOT: {{__kmpc|__tgt}}18// expected-no-diagnostics19#ifndef HEADER20#define HEADER21 22_Bool bv, bx;23char cv, cx;24unsigned char ucv, ucx;25short sv, sx;26unsigned short usv, usx;27int iv, ix;28unsigned int uiv, uix;29long lv, lx;30unsigned long ulv, ulx;31long long llv, llx;32unsigned long long ullv, ullx;33float fv, fx;34double dv, dx;35long double ldv, ldx;36_Complex int civ, cix;37_Complex float cfv, cfx;38_Complex double cdv, cdx;39 40typedef int int4 __attribute__((__vector_size__(16)));41int4 int4x;42 43struct BitFields {44 int : 32;45 int a : 31;46} bfx;47 48struct BitFields_packed {49 int : 32;50 int a : 31;51} __attribute__ ((__packed__)) bfx_packed;52 53struct BitFields2 {54 int : 31;55 int a : 1;56} bfx2;57 58struct BitFields2_packed {59 int : 31;60 int a : 1;61} __attribute__ ((__packed__)) bfx2_packed;62 63struct BitFields3 {64 int : 11;65 int a : 14;66} bfx3;67 68struct BitFields3_packed {69 int : 11;70 int a : 14;71} __attribute__ ((__packed__)) bfx3_packed;72 73struct BitFields4 {74 short : 16;75 int a: 1;76 long b : 7;77} bfx4;78 79struct BitFields4_packed {80 short : 16;81 int a: 1;82 long b : 7;83} __attribute__ ((__packed__)) bfx4_packed;84 85typedef float float2 __attribute__((ext_vector_type(2)));86float2 float2x;87 88// Register "0" is currently an invalid register for global register variables.89// Use "esp" instead of "0".90// register int rix __asm__("0");91register int rix __asm__("esp");92 93int main(void) {94// CHECK: [[PREV:%.+]] = atomicrmw add ptr @{{.+}}, i8 1 monotonic, align 195// CHECK: store i8 [[PREV]], ptr @{{.+}},96#pragma omp atomic capture97 bv = bx++;98// CHECK: atomicrmw add ptr @{{.+}}, i8 1 monotonic, align 199// CHECK: add nsw i32 %{{.+}}, 1100// CHECK: store i8 %{{.+}}, ptr @{{.+}},101#pragma omp atomic capture102 cv = ++cx;103// CHECK: [[PREV:%.+]] = atomicrmw sub ptr @{{.+}}, i8 1 monotonic, align 1104// CHECK: store i8 [[PREV]], ptr @{{.+}},105#pragma omp atomic capture106 ucv = ucx--;107// CHECK: atomicrmw sub ptr @{{.+}}, i16 1 monotonic, align 2108// CHECK: sub nsw i32 %{{.+}}, 1109// CHECK: store i16 %{{.+}}, ptr @{{.+}},110#pragma omp atomic capture111 sv = --sx;112// CHECK: [[USV:%.+]] = load i16, ptr @{{.+}},113// CHECK: [[EXPR:%.+]] = zext i16 [[USV]] to i32114// CHECK: [[X:%.+]] = load atomic i16, ptr [[X_ADDR:@.+]] monotonic, align 2115// CHECK: br label %[[CONT:.+]]116// CHECK: [[CONT]]117// CHECK: [[EXPECTED:%.+]] = phi i16 [ [[X]], %{{.+}} ], [ [[OLD_X:%.+]], %[[CONT]] ]118// CHECK: [[CONV:%.+]] = zext i16 [[EXPECTED]] to i32119// CHECK: [[ADD:%.+]] = add nsw i32 [[CONV]], [[EXPR]]120// CHECK: [[DESIRED_CALC:%.+]] = trunc i32 [[ADD]] to i16121// CHECK: store i16 [[DESIRED_CALC]], ptr [[TEMP:%.+]],122// CHECK: [[DESIRED:%.+]] = load i16, ptr [[TEMP]],123// CHECK: [[RES:%.+]] = cmpxchg ptr [[X_ADDR]], i16 [[EXPECTED]], i16 [[DESIRED]] monotonic monotonic, align 2124// CHECK: [[OLD_X]] = extractvalue { i16, i1 } [[RES]], 0125// CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i16, i1 } [[RES]], 1126// CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]]127// CHECK: [[EXIT]]128// CHECK: store i16 [[DESIRED_CALC]], ptr @{{.+}},129#pragma omp atomic capture130 sv = usx += usv;131// CHECK: [[EXPR:%.+]] = load i32, ptr @{{.+}},132// CHECK: [[X:%.+]] = load atomic i32, ptr [[X_ADDR:@.+]] monotonic, align 4133// CHECK: br label %[[CONT:.+]]134// CHECK: [[CONT]]135// CHECK: [[EXPECTED:%.+]] = phi i32 [ [[X]], %{{.+}} ], [ [[OLD_X:%.+]], %[[CONT]] ]136// CHECK: [[DESIRED_CALC:%.+]] = mul nsw i32 [[EXPECTED]], [[EXPR]]137// CHECK: store i32 [[DESIRED_CALC]], ptr [[TEMP:%.+]],138// CHECK: [[DESIRED:%.+]] = load i32, ptr [[TEMP]],139// CHECK: [[RES:%.+]] = cmpxchg ptr [[X_ADDR]], i32 [[EXPECTED]], i32 [[DESIRED]] monotonic monotonic, align 4140// CHECK: [[OLD_X]] = extractvalue { i32, i1 } [[RES]], 0141// CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i32, i1 } [[RES]], 1142// CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]]143// CHECK: [[EXIT]]144// CHECK: store i32 [[DESIRED_CALC]], ptr @{{.+}},145#pragma omp atomic capture146 uiv = ix *= iv;147// CHECK: [[EXPR:%.+]] = load i32, ptr @{{.+}},148// CHECK: [[PREV:%.+]] = atomicrmw sub ptr @{{.+}}, i32 [[EXPR]] monotonic, align 4149// CHECK: store i32 [[PREV]], ptr @{{.+}},150#pragma omp atomic capture151 {iv = uix; uix -= uiv;}152// CHECK: [[EXPR:%.+]] = load i32, ptr @{{.+}},153// CHECK: [[X:%.+]] = load atomic i32, ptr [[X_ADDR:@.+]] monotonic, align 4154// CHECK: br label %[[CONT:.+]]155// CHECK: [[CONT]]156// CHECK: [[EXPECTED:%.+]] = phi i32 [ [[X]], %{{.+}} ], [ [[OLD_X:%.+]], %[[CONT]] ]157// CHECK: [[DESIRED_CALC:%.+]] = shl i32 [[EXPECTED]], [[EXPR]]158// CHECK: store i32 [[DESIRED_CALC]], ptr [[TEMP:%.+]],159// CHECK: [[DESIRED:%.+]] = load i32, ptr [[TEMP]],160// CHECK: [[RES:%.+]] = cmpxchg ptr [[X_ADDR]], i32 [[EXPECTED]], i32 [[DESIRED]] monotonic monotonic, align 4161// CHECK: [[OLD_X]] = extractvalue { i32, i1 } [[RES]], 0162// CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i32, i1 } [[RES]], 1163// CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]]164// CHECK: [[EXIT]]165// CHECK: store i32 [[DESIRED_CALC]], ptr @{{.+}},166#pragma omp atomic capture167 {ix <<= iv; uiv = ix;}168// CHECK: [[EXPR:%.+]] = load i32, ptr @{{.+}},169// CHECK: [[X:%.+]] = load atomic i32, ptr [[X_ADDR:@.+]] monotonic, align 4170// CHECK: br label %[[CONT:.+]]171// CHECK: [[CONT]]172// CHECK: [[EXPECTED:%.+]] = phi i32 [ [[X]], %{{.+}} ], [ [[OLD_X:%.+]], %[[CONT]] ]173// CHECK: [[DESIRED_CALC:%.+]] = lshr i32 [[EXPECTED]], [[EXPR]]174// CHECK: store i32 [[DESIRED_CALC]], ptr [[TEMP:%.+]],175// CHECK: [[DESIRED:%.+]] = load i32, ptr [[TEMP]],176// CHECK: [[RES:%.+]] = cmpxchg ptr [[X_ADDR]], i32 [[EXPECTED]], i32 [[DESIRED]] monotonic monotonic, align 4177// CHECK: [[OLD_X]] = extractvalue { i32, i1 } [[RES]], 0178// CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i32, i1 } [[RES]], 1179// CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]]180// CHECK: [[EXIT]]181// CHECK: store i32 [[DESIRED_CALC]], ptr @{{.+}},182#pragma omp atomic capture183 iv = uix >>= uiv;184// CHECK: [[EXPR:%.+]] = load i64, ptr @{{.+}},185// CHECK: [[X:%.+]] = load atomic i64, ptr [[X_ADDR:@.+]] monotonic, align 8186// CHECK: br label %[[CONT:.+]]187// CHECK: [[CONT]]188// CHECK: [[EXPECTED:%.+]] = phi i64 [ [[X]], %{{.+}} ], [ [[OLD_X:%.+]], %[[CONT]] ]189// CHECK: [[DESIRED:%.+]] = sdiv i64 [[EXPECTED]], [[EXPR]]190// CHECK: store i64 [[DESIRED]], ptr [[TEMP:%.+]],191// CHECK: [[DESIRED:%.+]] = load i64, ptr [[TEMP]],192// CHECK: [[RES:%.+]] = cmpxchg ptr [[X_ADDR]], i64 [[EXPECTED]], i64 [[DESIRED]] monotonic monotonic, align 8193// CHECK: [[OLD_X]] = extractvalue { i64, i1 } [[RES]], 0194// CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i64, i1 } [[RES]], 1195// CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]]196// CHECK: [[EXIT]]197// CHECK: store i64 [[EXPECTED]], ptr @{{.+}},198#pragma omp atomic capture199 {ulv = lx; lx /= lv;}200// CHECK: [[EXPR:%.+]] = load i64, ptr @{{.+}},201// CHECK: [[OLD:%.+]] = atomicrmw and ptr @{{.+}}, i64 [[EXPR]] monotonic, align 8202// CHECK: [[DESIRED:%.+]] = and i64 [[OLD]], [[EXPR]]203// CHECK: store i64 [[DESIRED]], ptr @{{.+}},204#pragma omp atomic capture205 {ulx &= ulv; lv = ulx;}206// CHECK: [[EXPR:%.+]] = load i64, ptr @{{.+}},207// CHECK: [[OLD:%.+]] = atomicrmw xor ptr @{{.+}}, i64 [[EXPR]] monotonic, align 8208// CHECK: [[DESIRED:%.+]] = xor i64 [[OLD]], [[EXPR]]209// CHECK: store i64 [[DESIRED]], ptr @{{.+}},210#pragma omp atomic capture211 ullv = llx ^= llv;212// CHECK: [[EXPR:%.+]] = load i64, ptr @{{.+}},213// CHECK: [[OLD:%.+]] = atomicrmw or ptr @{{.+}}, i64 [[EXPR]] monotonic, align 8214// CHECK: [[DESIRED:%.+]] = or i64 [[OLD]], [[EXPR]]215// CHECK: store i64 [[DESIRED]], ptr @{{.+}},216#pragma omp atomic capture217 llv = ullx |= ullv;218// CHECK: [[EXPR:%.+]] = load float, ptr @{{.+}},219// CHECK: [[OLD:%.+]] = atomicrmw fadd ptr @{{.+}}, float [[EXPR]] monotonic, align 4220// CHECK: [[ADD:%.+]] = fadd float [[OLD]], [[EXPR]]221// CHECK: [[CAST:%.+]] = fpext float [[ADD]] to double222// CHECK: store double [[CAST]], ptr @{{.+}},223#pragma omp atomic capture224 dv = fx = fx + fv;225// CHECK: [[EXPR:%.+]] = load double, ptr @{{.+}},226// CHECK: [[X:%.+]] = load atomic i64, ptr [[X_ADDR:@.+]] monotonic, align 8227// CHECK: br label %[[CONT:.+]]228// CHECK: [[CONT]]229// CHECK: [[EXPECTED:%.+]] = phi i64 [ [[X]], %{{.+}} ], [ [[OLD_X:%.+]], %[[CONT]] ]230// CHECK: [[OLD:%.+]] = bitcast i64 [[EXPECTED]] to double231// CHECK: [[SUB:%.+]] = fsub double [[EXPR]], [[OLD]]232// CHECK: store double [[SUB]], ptr [[TEMP:%.+]],233// CHECK: [[DESIRED:%.+]] = load i64, ptr [[TEMP]],234// CHECK: [[RES:%.+]] = cmpxchg ptr [[X_ADDR]], i64 [[EXPECTED]], i64 [[DESIRED]] monotonic monotonic, align 8235// CHECK: [[OLD_X:%.+]] = extractvalue { i64, i1 } [[RES]], 0236// CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i64, i1 } [[RES]], 1237// CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]]238// CHECK: [[EXIT]]239// CHECK: [[CAST:%.+]] = fptrunc double [[OLD]] to float240// CHECK: store float [[CAST]], ptr @{{.+}},241#pragma omp atomic capture242 {fv = dx; dx = dv - dx;}243// CHECK: [[EXPR:%.+]] = load x86_fp80, ptr @{{.+}},244// CHECK: [[X:%.+]] = load atomic i128, ptr [[X_ADDR:@.+]] monotonic, align 16245// CHECK: br label %[[CONT:.+]]246// CHECK: [[CONT]]247// CHECK: [[EXPECTED:%.+]] = phi i128 [ [[X]], %{{.+}} ], [ [[OLD_X:%.+]], %[[CONT]] ]248// CHECK: store i128 [[EXPECTED]], ptr [[TEMP:%.+]]249// CHECK: store i128 [[EXPECTED]], ptr [[TEMP1:%.+]]250// CHECK: [[OLD:%.+]] = load x86_fp80, ptr [[TEMP1]]251// CHECK: [[MUL:%.+]] = fmul x86_fp80 [[OLD]], [[EXPR]]252// CHECK: store x86_fp80 [[MUL]], ptr [[TEMP]]253// CHECK: [[DESIRED:%.+]] = load i128, ptr [[TEMP]]254// CHECK: [[RES:%.+]] = cmpxchg ptr [[X_ADDR]], i128 [[EXPECTED]], i128 [[DESIRED]] monotonic monotonic, align 16255// CHECK: [[OLD_X:%.+]] = extractvalue { i128, i1 } [[RES]], 0256// CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i128, i1 } [[RES]], 1257// CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]]258// CHECK: [[EXIT]]259// CHECK: [[CAST:%.+]] = fptrunc x86_fp80 [[MUL]] to double260// CHECK: store double [[CAST]], ptr @{{.+}},261#pragma omp atomic capture262 {ldx = ldx * ldv; dv = ldx;}263// CHECK: [[EXPR_RE:%.+]] = load i32, ptr @{{.+}}264// CHECK: [[EXPR_IM:%.+]] = load i32, ptr getelementptr inbounds nuw ({ i32, i32 }, ptr @{{.+}}, i32 0, i32 1)265// CHECK: call void @__atomic_load(i64 noundef 8, ptr noundef [[X_ADDR:@.+]], ptr noundef [[EXPECTED_ADDR:%.+]], i32 noundef 0)266// CHECK: br label %[[CONT:.+]]267// CHECK: [[CONT]]268// CHECK: [[LD_RE_ADDR:%.+]] = getelementptr inbounds nuw { i32, i32 }, ptr [[EXPECTED_ADDR]], i32 0, i32 0269// CHECK: [[LD_RE:%.+]] = load i32, ptr [[LD_RE_ADDR]]270// CHECK: [[LD_IM_ADDR:%.+]] = getelementptr inbounds nuw { i32, i32 }, ptr [[EXPECTED_ADDR]], i32 0, i32 1271// CHECK: [[LD_IM:%.+]] = load i32, ptr [[LD_IM_ADDR]]272// <Skip checks for complex calculations>273// CHECK: [[X_RE_ADDR:%.+]] = getelementptr inbounds nuw { i32, i32 }, ptr [[DESIRED_ADDR:%.+]], i32 0, i32 0274// CHECK: [[X_IM_ADDR:%.+]] = getelementptr inbounds nuw { i32, i32 }, ptr [[DESIRED_ADDR]], i32 0, i32 1275// CHECK: store i32 [[NEW_RE:%.+]], ptr [[X_RE_ADDR]]276// CHECK: store i32 [[NEW_IM:%.+]], ptr [[X_IM_ADDR]]277// CHECK: [[SUCCESS_FAIL:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 noundef 8, ptr noundef [[X_ADDR]], ptr noundef [[EXPECTED_ADDR]], ptr noundef [[DESIRED_ADDR]], i32 noundef 0, i32 noundef 0)278// CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]]279// CHECK: [[EXIT]]280// CHECK: [[RE_CAST:%.+]] = sitofp i32 [[NEW_RE]] to float281// CHECK: [[IM_CAST:%.+]] = sitofp i32 [[NEW_IM]] to float282// CHECK: store float [[RE_CAST]], ptr @{{.+}},283// CHECK: store float [[IM_CAST]], ptr getelementptr inbounds nuw ({ float, float }, ptr @{{.+}}, i32 0, i32 1),284#pragma omp atomic capture285 cfv = cix = civ / cix;286// CHECK: [[EXPR_RE:%.+]] = load float, ptr @{{.+}}287// CHECK: [[EXPR_IM:%.+]] = load float, ptr getelementptr inbounds nuw ({ float, float }, ptr @{{.+}}, i32 0, i32 1)288// CHECK: call void @__atomic_load(i64 noundef 8, ptr noundef [[X_ADDR:@.+]], ptr noundef [[EXPECTED_ADDR:%.+]], i32 noundef 0)289// CHECK: br label %[[CONT:.+]]290// CHECK: [[CONT]]291// CHECK: [[X_RE_ADDR:%.+]] = getelementptr inbounds nuw { float, float }, ptr [[EXPECTED_ADDR]], i32 0, i32 0292// CHECK: [[X_RE_OLD:%.+]] = load float, ptr [[X_RE_ADDR]]293// CHECK: [[X_IM_ADDR:%.+]] = getelementptr inbounds nuw { float, float }, ptr [[EXPECTED_ADDR]], i32 0, i32 1294// CHECK: [[X_IM_OLD:%.+]] = load float, ptr [[X_IM_ADDR]]295// <Skip checks for complex calculations>296// CHECK: [[X_RE_ADDR:%.+]] = getelementptr inbounds nuw { float, float }, ptr [[DESIRED_ADDR:%.+]], i32 0, i32 0297// CHECK: [[X_IM_ADDR:%.+]] = getelementptr inbounds nuw { float, float }, ptr [[DESIRED_ADDR]], i32 0, i32 1298// CHECK: store float [[NEW_RE:%.+]], ptr [[X_RE_ADDR]]299// CHECK: store float [[NEW_IM:%.+]], ptr [[X_IM_ADDR]]300// CHECK: [[SUCCESS_FAIL:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 noundef 8, ptr noundef [[X_ADDR]], ptr noundef [[EXPECTED_ADDR]], ptr noundef [[DESIRED_ADDR]], i32 noundef 0, i32 noundef 0)301// CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]]302// CHECK: [[EXIT]]303// CHECK: [[RE_CAST:%.+]] = fptosi float [[X_RE_OLD]] to i32304// CHECK: [[IM_CAST:%.+]] = fptosi float [[X_IM_OLD]] to i32305// CHECK: store i32 [[RE_CAST]], ptr @{{.+}},306// CHECK: store i32 [[IM_CAST]], ptr getelementptr inbounds nuw ({ i32, i32 }, ptr @{{.+}}, i32 0, i32 1),307#pragma omp atomic capture308 {civ = cfx; cfx = cfv + cfx;}309// CHECK: [[EXPR_RE:%.+]] = load double, ptr @{{.+}}310// CHECK: [[EXPR_IM:%.+]] = load double, ptr getelementptr inbounds nuw ({ double, double }, ptr @{{.+}}, i32 0, i32 1)311// CHECK: call void @__atomic_load(i64 noundef 16, ptr noundef [[X_ADDR:@.+]], ptr noundef [[EXPECTED_ADDR:%.+]], i32 noundef 5)312// CHECK: br label %[[CONT:.+]]313// CHECK: [[CONT]]314// CHECK: [[X_RE_ADDR:%.+]] = getelementptr inbounds nuw { double, double }, ptr [[EXPECTED_ADDR]], i32 0, i32 0315// CHECK: [[X_RE:%.+]] = load double, ptr [[X_RE_ADDR]]316// CHECK: [[X_IM_ADDR:%.+]] = getelementptr inbounds nuw { double, double }, ptr [[EXPECTED_ADDR]], i32 0, i32 1317// CHECK: [[X_IM:%.+]] = load double, ptr [[X_IM_ADDR]]318// <Skip checks for complex calculations>319// CHECK: [[X_RE_ADDR:%.+]] = getelementptr inbounds nuw { double, double }, ptr [[DESIRED_ADDR:%.+]], i32 0, i32 0320// CHECK: [[X_IM_ADDR:%.+]] = getelementptr inbounds nuw { double, double }, ptr [[DESIRED_ADDR]], i32 0, i32 1321// CHECK: store double [[NEW_RE:%.+]], ptr [[X_RE_ADDR]]322// CHECK: store double [[NEW_IM:%.+]], ptr [[X_IM_ADDR]]323// CHECK: [[SUCCESS_FAIL:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 noundef 16, ptr noundef [[X_ADDR]], ptr noundef [[EXPECTED_ADDR]], ptr noundef [[DESIRED_ADDR]], i32 noundef 5, i32 noundef 5)324// CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]]325// CHECK: [[EXIT]]326// CHECK: [[RE_CAST:%.+]] = fptrunc double [[NEW_RE]] to float327// CHECK: [[IM_CAST:%.+]] = fptrunc double [[NEW_IM]] to float328// CHECK: store float [[RE_CAST]], ptr @{{.+}},329// CHECK: store float [[IM_CAST]], ptr getelementptr inbounds nuw ({ float, float }, ptr @{{.+}}, i32 0, i32 1),330// CHECK-50: call{{.*}} @__kmpc_flush(331#pragma omp atomic capture seq_cst332 {cdx = cdx - cdv; cfv = cdx;}333// CHECK: [[BV:%.+]] = load i8, ptr @{{.+}}334// CHECK: [[BOOL:%.+]] = trunc i8 [[BV]] to i1335// CHECK: [[EXPR:%.+]] = zext i1 [[BOOL]] to i64336// CHECK: [[OLD:%.+]] = atomicrmw and ptr @{{.+}}, i64 [[EXPR]] monotonic, align 8337// CHECK: [[DESIRED:%.+]] = and i64 [[OLD]], [[EXPR]]338// CHECK: store i64 [[DESIRED]], ptr @{{.+}},339#pragma omp atomic capture340 ulv = ulx = ulx & bv;341// CHECK: [[CV:%.+]] = load i8, ptr @{{.+}}, align 1342// CHECK: [[EXPR:%.+]] = sext i8 [[CV]] to i32343// CHECK: [[X:%.+]] = load atomic i8, ptr [[BX_ADDR:@.+]] monotonic, align 1344// CHECK: br label %[[CONT:.+]]345// CHECK: [[CONT]]346// CHECK: [[EXPECTED:%.+]] = phi i8 [ [[X]], %{{.+}} ], [ [[OLD_X:%.+]], %[[CONT]] ]347// CHECK: [[OLD_BOOL:%.+]] = trunc i8 [[EXPECTED]] to i1348// CHECK: [[X_RVAL:%.+]] = zext i1 [[OLD_BOOL]] to i32349// CHECK: [[AND:%.+]] = and i32 [[EXPR]], [[X_RVAL]]350// CHECK: [[CAST:%.+]] = icmp ne i32 [[AND]], 0351// CHECK: [[NEW:%.+]] = zext i1 [[CAST]] to i8352// CHECK: store i8 [[NEW]], ptr [[TEMP:%.+]],353// CHECK: [[DESIRED:%.+]] = load i8, ptr [[TEMP]],354// CHECK: [[RES:%.+]] = cmpxchg ptr [[BX_ADDR]], i8 [[EXPECTED]], i8 [[DESIRED]] monotonic monotonic, align 1355// CHECK: [[OLD:%.+]] = extractvalue { i8, i1 } [[RES]], 0356// CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i8, i1 } [[RES]], 1357// CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]]358// CHECK: [[EXIT]]359// CHECK: [[OLD_I8:%.+]] = zext i1 [[OLD_BOOL]] to i8360// CHECK: store i8 [[OLD_I8]], ptr @{{.+}},361#pragma omp atomic capture362 {bv = bx; bx = cv & bx;}363// CHECK: [[UCV:%.+]] = load i8, ptr @{{.+}},364// CHECK: [[EXPR:%.+]] = zext i8 [[UCV]] to i32365// CHECK: [[X:%.+]] = load atomic i8, ptr [[CX_ADDR:@.+]] seq_cst, align 1366// CHECK: br label %[[CONT:.+]]367// CHECK: [[CONT]]368// CHECK: [[EXPECTED:%.+]] = phi i8 [ [[X]], %{{.+}} ], [ [[OLD_X:%.+]], %[[CONT]] ]369// CHECK: [[X_RVAL:%.+]] = sext i8 [[EXPECTED]] to i32370// CHECK: [[ASHR:%.+]] = ashr i32 [[X_RVAL]], [[EXPR]]371// CHECK: [[NEW:%.+]] = trunc i32 [[ASHR]] to i8372// CHECK: store i8 [[NEW]], ptr [[TEMP:%.+]],373// CHECK: [[DESIRED:%.+]] = load i8, ptr [[TEMP]],374// CHECK: [[RES:%.+]] = cmpxchg ptr [[CX_ADDR]], i8 [[EXPECTED]], i8 [[DESIRED]] seq_cst seq_cst, align 1375// CHECK: [[OLD_X:%.+]] = extractvalue { i8, i1 } [[RES]], 0376// CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i8, i1 } [[RES]], 1377// CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]]378// CHECK: [[EXIT]]379// CHECK: store i8 [[NEW]], ptr @{{.+}},380// CHECK-50: call{{.*}} @__kmpc_flush(381#pragma omp atomic capture, seq_cst382 {cx = cx >> ucv; cv = cx;}383// CHECK: [[SV:%.+]] = load i16, ptr @{{.+}},384// CHECK: [[EXPR:%.+]] = sext i16 [[SV]] to i32385// CHECK: [[X:%.+]] = load atomic i64, ptr [[ULX_ADDR:@.+]] monotonic, align 8386// CHECK: br label %[[CONT:.+]]387// CHECK: [[CONT]]388// CHECK: [[EXPECTED:%.+]] = phi i64 [ [[X]], %{{.+}} ], [ [[OLD_X:%.+]], %[[CONT]] ]389// CHECK: [[X_RVAL:%.+]] = trunc i64 [[EXPECTED]] to i32390// CHECK: [[SHL:%.+]] = shl i32 [[EXPR]], [[X_RVAL]]391// CHECK: [[NEW:%.+]] = sext i32 [[SHL]] to i64392// CHECK: store i64 [[NEW]], ptr [[TEMP:%.+]],393// CHECK: [[DESIRED:%.+]] = load i64, ptr [[TEMP]],394// CHECK: [[RES:%.+]] = cmpxchg ptr [[ULX_ADDR]], i64 [[EXPECTED]], i64 [[DESIRED]] monotonic monotonic, align 8395// CHECK: [[OLD_X:%.+]] = extractvalue { i64, i1 } [[RES]], 0396// CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i64, i1 } [[RES]], 1397// CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]]398// CHECK: [[EXIT]]399// CHECK: store i64 [[NEW]], ptr @{{.+}},400#pragma omp atomic capture401 ulv = ulx = sv << ulx;402// CHECK: [[USV:%.+]] = load i16, ptr @{{.+}},403// CHECK: [[EXPR:%.+]] = zext i16 [[USV]] to i64404// CHECK: [[X:%.+]] = load atomic i64, ptr [[LX_ADDR:@.+]] monotonic, align 8405// CHECK: br label %[[CONT:.+]]406// CHECK: [[CONT]]407// CHECK: [[EXPECTED:%.+]] = phi i64 [ [[X]], %{{.+}} ], [ [[OLD_X:%.+]], %[[CONT]] ]408// CHECK: [[DESIRED:%.+]] = srem i64 [[EXPECTED]], [[EXPR]]409// CHECK: store i64 [[DESIRED]], ptr [[TEMP:%.+]],410// CHECK: [[DESIRED:%.+]] = load i64, ptr [[TEMP]],411// CHECK: [[RES:%.+]] = cmpxchg ptr [[LX_ADDR]], i64 [[EXPECTED]], i64 [[DESIRED]] monotonic monotonic, align 8412// CHECK: [[OLD_X:%.+]] = extractvalue { i64, i1 } [[RES]], 0413// CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i64, i1 } [[RES]], 1414// CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]]415// CHECK: [[EXIT]]416// CHECK: store i64 [[EXPECTED]], ptr @{{.+}},417#pragma omp atomic capture418 {lv = lx; lx = lx % usv;}419// CHECK: [[EXPR:%.+]] = load i32, ptr @{{.+}}420// CHECK: [[OLD:%.+]] = atomicrmw or ptr @{{.+}}, i32 [[EXPR]] seq_cst, align 4421// CHECK: [[DESIRED:%.+]] = or i32 [[EXPR]], [[OLD]]422// CHECK: store i32 [[DESIRED]], ptr @{{.+}},423// CHECK-50: call{{.*}} @__kmpc_flush(424#pragma omp atomic seq_cst, capture425 {uix = iv | uix; uiv = uix;}426// CHECK: [[EXPR:%.+]] = load i32, ptr @{{.+}}427// CHECK: [[OLD:%.+]] = atomicrmw and ptr @{{.+}}, i32 [[EXPR]] monotonic, align 4428// CHECK: [[DESIRED:%.+]] = and i32 [[OLD]], [[EXPR]]429// CHECK: store i32 [[DESIRED]], ptr @{{.+}},430#pragma omp atomic capture431 iv = ix = ix & uiv;432// CHECK: [[EXPR:%.+]] = load i64, ptr @{{.+}},433// CHECK: call void @__atomic_load(i64 noundef 8, ptr noundef [[X_ADDR:@.+]], ptr noundef [[EXPECTED_ADDR:%.+]], i32 noundef 0)434// CHECK: br label %[[CONT:.+]]435// CHECK: [[CONT]]436// CHECK: [[X_RE_ADDR:%.+]] = getelementptr inbounds nuw { i32, i32 }, ptr [[EXPECTED_ADDR]], i32 0, i32 0437// CHECK: [[OLD_RE:%.+]] = load i32, ptr [[X_RE_ADDR]]438// CHECK: [[X_IM_ADDR:%.+]] = getelementptr inbounds nuw { i32, i32 }, ptr [[EXPECTED_ADDR]], i32 0, i32 1439// CHECK: [[OLD_IM:%.+]] = load i32, ptr [[X_IM_ADDR]]440// <Skip checks for complex calculations>441// CHECK: [[X_RE_ADDR:%.+]] = getelementptr inbounds nuw { i32, i32 }, ptr [[DESIRED_ADDR:%.+]], i32 0, i32 0442// CHECK: [[X_IM_ADDR:%.+]] = getelementptr inbounds nuw { i32, i32 }, ptr [[DESIRED_ADDR]], i32 0, i32 1443// CHECK: store i32 %{{.+}}, ptr [[X_RE_ADDR]]444// CHECK: store i32 %{{.+}}, ptr [[X_IM_ADDR]]445// CHECK: [[SUCCESS_FAIL:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 noundef 8, ptr noundef [[X_ADDR]], ptr noundef [[EXPECTED_ADDR]], ptr noundef [[DESIRED_ADDR]], i32 noundef 0, i32 noundef 0)446// CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]]447// CHECK: [[EXIT]]448// CHECK: store i32 [[OLD_RE]], ptr @{{.+}},449// CHECK: store i32 [[OLD_IM]], ptr getelementptr inbounds nuw ({ i32, i32 }, ptr @{{.+}}, i32 0, i32 1),450#pragma omp atomic capture451 {civ = cix; cix = lv + cix;}452// CHECK: [[ULV:%.+]] = load i64, ptr @{{.+}},453// CHECK: [[EXPR:%.+]] = uitofp i64 [[ULV]] to float454// CHECK: [[X:%.+]] = load atomic i32, ptr [[X_ADDR:@.+]] monotonic, align 4455// CHECK: br label %[[CONT:.+]]456// CHECK: [[CONT]]457// CHECK: [[EXPECTED:%.+]] = phi i32 [ [[X]], %{{.+}} ], [ [[OLD_X:%.+]], %[[CONT]] ]458// CHECK: [[OLD:%.+]] = bitcast i32 [[EXPECTED]] to float459// CHECK: [[MUL:%.+]] = fmul float [[OLD]], [[EXPR]]460// CHECK: store float [[MUL]], ptr [[TEMP:%.+]],461// CHECK: [[DESIRED:%.+]] = load i32, ptr [[TEMP]],462// CHECK: [[RES:%.+]] = cmpxchg ptr [[X_ADDR]], i32 [[EXPECTED]], i32 [[DESIRED]] monotonic monotonic, align 4463// CHECK: [[OLD_X:%.+]] = extractvalue { i32, i1 } [[RES]], 0464// CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i32, i1 } [[RES]], 1465// CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]]466// CHECK: [[EXIT]]467// CHECK: store float [[MUL]], ptr @{{.+}},468#pragma omp atomic capture469 {fx = fx * ulv; fv = fx;}470// CHECK: [[LLV:%.+]] = load i64, ptr @{{.+}},471// CHECK: [[EXPR:%.+]] = sitofp i64 [[LLV]] to double472// CHECK: [[X:%.+]] = load atomic i64, ptr [[X_ADDR:@.+]] monotonic, align 8473// CHECK: br label %[[CONT:.+]]474// CHECK: [[CONT]]475// CHECK: [[EXPECTED:%.+]] = phi i64 [ [[X]], %{{.+}} ], [ [[OLD_X:%.+]], %[[CONT]] ]476// CHECK: [[OLD:%.+]] = bitcast i64 [[EXPECTED]] to double477// CHECK: [[DIV:%.+]] = fdiv double [[OLD]], [[EXPR]]478// CHECK: store double [[DIV]], ptr [[TEMP:%.+]],479// CHECK: [[DESIRED:%.+]] = load i64, ptr [[TEMP]],480// CHECK: [[RES:%.+]] = cmpxchg ptr [[X_ADDR]], i64 [[EXPECTED]], i64 [[DESIRED]] monotonic monotonic, align 8481// CHECK: [[OLD_X:%.+]] = extractvalue { i64, i1 } [[RES]], 0482// CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i64, i1 } [[RES]], 1483// CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]]484// CHECK: [[EXIT]]485// CHECK: store double [[DIV]], ptr @{{.+}},486#pragma omp atomic capture487 dv = dx /= llv;488// CHECK: [[ULLV:%.+]] = load i64, ptr @{{.+}},489// CHECK: [[EXPR:%.+]] = uitofp i64 [[ULLV]] to x86_fp80490// CHECK: [[X:%.+]] = load atomic i128, ptr [[X_ADDR:@.+]] monotonic, align 16491// CHECK: br label %[[CONT:.+]]492// CHECK: [[CONT]]493// CHECK: [[EXPECTED:%.+]] = phi i128 [ [[X]], %{{.+}} ], [ [[OLD_X:%.+]], %[[CONT]] ]494// CHECK: store i128 [[EXPECTED]], ptr [[TEMP1:%.+]],495// CHECK: store i128 [[EXPECTED]], ptr [[TEMP:%.+]],496// CHECK: [[OLD:%.+]] = load x86_fp80, ptr [[TEMP]],497// CHECK: [[SUB:%.+]] = fsub x86_fp80 [[OLD]], [[EXPR]]498// CHECK: store x86_fp80 [[SUB]], ptr [[TEMP1]]499// CHECK: [[DESIRED:%.+]] = load i128, ptr [[TEMP1]]500// CHECK: [[RES:%.+]] = cmpxchg ptr [[X_ADDR]], i128 [[EXPECTED]], i128 [[DESIRED]] monotonic monotonic, align 16501// CHECK: [[OLD_X:%.+]] = extractvalue { i128, i1 } [[RES]], 0502// CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i128, i1 } [[RES]], 1503// CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]]504// CHECK: [[EXIT]]505// CHECK: store x86_fp80 [[OLD]], ptr @{{.+}},506#pragma omp atomic capture507 {ldv = ldx; ldx -= ullv;}508// CHECK: [[EXPR:%.+]] = load float, ptr @{{.+}},509// CHECK: call void @__atomic_load(i64 noundef 8, ptr noundef [[X_ADDR:@.+]], ptr noundef [[EXPECTED_ADDR:%.+]], i32 noundef 0)510// CHECK: br label %[[CONT:.+]]511// CHECK: [[CONT]]512// CHECK: [[X_RE_ADDR:%.+]] = getelementptr inbounds nuw { i32, i32 }, ptr [[EXPECTED_ADDR]], i32 0, i32 0513// CHECK: [[X_RE:%.+]] = load i32, ptr [[X_RE_ADDR]]514// CHECK: [[X_IM_ADDR:%.+]] = getelementptr inbounds nuw { i32, i32 }, ptr [[EXPECTED_ADDR]], i32 0, i32 1515// CHECK: [[X_IM:%.+]] = load i32, ptr [[X_IM_ADDR]]516// <Skip checks for complex calculations>517// CHECK: [[X_RE_ADDR:%.+]] = getelementptr inbounds nuw { i32, i32 }, ptr [[DESIRED_ADDR:%.+]], i32 0, i32 0518// CHECK: [[X_IM_ADDR:%.+]] = getelementptr inbounds nuw { i32, i32 }, ptr [[DESIRED_ADDR]], i32 0, i32 1519// CHECK: store i32 [[NEW_RE:%.+]], ptr [[X_RE_ADDR]]520// CHECK: store i32 [[NEW_IM:%.+]], ptr [[X_IM_ADDR]]521// CHECK: [[SUCCESS_FAIL:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 noundef 8, ptr noundef [[X_ADDR]], ptr noundef [[EXPECTED_ADDR]], ptr noundef [[DESIRED_ADDR]], i32 noundef 0, i32 noundef 0)522// CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]]523// CHECK: [[EXIT]]524// CHECK: store i32 [[NEW_RE]], ptr @{{.+}},525// CHECK: store i32 [[NEW_IM]], ptr getelementptr inbounds nuw ({ i32, i32 }, ptr @{{.+}}, i32 0, i32 1),526#pragma omp atomic capture527 {cix = fv / cix; civ = cix;}528// CHECK: [[EXPR:%.+]] = load double, ptr @{{.+}},529// CHECK: [[X:%.+]] = load atomic i16, ptr [[X_ADDR:@.+]] monotonic, align 2530// CHECK: br label %[[CONT:.+]]531// CHECK: [[CONT]]532// CHECK: [[EXPECTED:%.+]] = phi i16 [ [[X]], %{{.+}} ], [ [[OLD_X:%.+]], %[[CONT]] ]533// CHECK: [[CONV:%.+]] = sext i16 [[EXPECTED]] to i32534// CHECK: [[X_RVAL:%.+]] = sitofp i32 [[CONV]] to double535// CHECK: [[ADD:%.+]] = fadd double [[X_RVAL]], [[EXPR]]536// CHECK: [[NEW:%.+]] = fptosi double [[ADD]] to i16537// CHECK: store i16 [[NEW]], ptr [[TEMP:%.+]],538// CHECK: [[DESIRED:%.+]] = load i16, ptr [[TEMP]],539// CHECK: [[RES:%.+]] = cmpxchg ptr [[X_ADDR]], i16 [[EXPECTED]], i16 [[DESIRED]] monotonic monotonic, align 2540// CHECK: [[OLD_X]] = extractvalue { i16, i1 } [[RES]], 0541// CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i16, i1 } [[RES]], 1542// CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]]543// CHECK: [[EXIT]]544// CHECK: store i16 [[NEW]], ptr @{{.+}},545#pragma omp atomic capture546 sv = sx = sx + dv;547// CHECK: [[EXPR:%.+]] = load x86_fp80, ptr @{{.+}},548// CHECK: [[XI8:%.+]] = load atomic i8, ptr [[X_ADDR:@.+]] monotonic, align 1549// CHECK: br label %[[CONT:.+]]550// CHECK: [[CONT]]551// CHECK: [[EXPECTED:%.+]] = phi i8 [ [[XI8]], %{{.+}} ], [ [[OLD_X:%.+]], %[[CONT]] ]552// CHECK: [[BOOL_EXPECTED:%.+]] = trunc i8 [[EXPECTED]] to i1553// CHECK: [[CONV:%.+]] = zext i1 [[BOOL_EXPECTED]] to i32554// CHECK: [[X_RVAL:%.+]] = sitofp i32 [[CONV]] to x86_fp80555// CHECK: [[MUL:%.+]] = fmul x86_fp80 [[EXPR]], [[X_RVAL]]556// CHECK: [[BOOL_DESIRED:%.+]] = fcmp une x86_fp80 [[MUL]], 0xK00000000000000000000557// CHECK: [[DESIRED:%.+]] = zext i1 [[BOOL_DESIRED]] to i8558// CHECK: store i8 [[DESIRED]], ptr [[TEMP:%.+]],559// CHECK: [[DESIRED:%.+]] = load i8, ptr [[TEMP]],560// CHECK: [[RES:%.+]] = cmpxchg ptr [[X_ADDR]], i8 [[EXPECTED]], i8 [[DESIRED]] monotonic monotonic, align 1561// CHECK: [[OLD_X:%.+]] = extractvalue { i8, i1 } [[RES]], 0562// CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i8, i1 } [[RES]], 1563// CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]]564// CHECK: [[EXIT]]565// CHECK: [[EXPECTED_I8:%.+]] = zext i1 [[BOOL_EXPECTED]] to i8566// CHECK: store i8 [[EXPECTED_I8]], ptr @{{.+}},567#pragma omp atomic capture568 {bv = bx; bx = ldv * bx;}569// CHECK: [[EXPR_RE:%.+]] = load i32, ptr [[CIV_ADDR:@.+]],570// CHECK: [[EXPR_IM:%.+]] = load i32, ptr getelementptr inbounds nuw ({ i32, i32 }, ptr [[CIV_ADDR]], i32 0, i32 1),571// CHECK: [[XI8:%.+]] = load atomic i8, ptr [[X_ADDR:@.+]] monotonic, align 1572// CHECK: br label %[[CONT:.+]]573// CHECK: [[CONT]]574// CHECK: [[EXPECTED:%.+]] = phi i8 [ [[XI8]], %{{.+}} ], [ [[OLD_X:%.+]], %[[CONT]] ]575// CHECK: [[BOOL_EXPECTED:%.+]] = trunc i8 [[EXPECTED]] to i1576// CHECK: [[X_RVAL:%.+]] = zext i1 [[BOOL_EXPECTED]] to i32577// CHECK: [[SUB_RE:%.+]] = sub i32 [[EXPR_RE:%.+]], [[X_RVAL]]578// CHECK: [[SUB_IM:%.+]] = sub i32 [[EXPR_IM:%.+]], 0579// CHECK: icmp ne i32 [[SUB_RE]], 0580// CHECK: icmp ne i32 [[SUB_IM]], 0581// CHECK: [[BOOL_DESIRED:%.+]] = or i1582// CHECK: [[DESIRED:%.+]] = zext i1 [[BOOL_DESIRED]] to i8583// CHECK: store i8 [[DESIRED]], ptr [[TEMP:%.+]],584// CHECK: [[DESIRED:%.+]] = load i8, ptr [[TEMP]],585// CHECK: [[RES:%.+]] = cmpxchg ptr [[X_ADDR]], i8 [[EXPECTED]], i8 [[DESIRED]] monotonic monotonic, align 1586// CHECK: [[OLD_X:%.+]] = extractvalue { i8, i1 } [[RES]], 0587// CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i8, i1 } [[RES]], 1588// CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]]589// CHECK: [[EXIT]]590// CHECK: [[DESIRED_I8:%.+]] = zext i1 [[BOOL_DESIRED]] to i8591// CHECK: store i8 [[DESIRED_I8]], ptr @{{.+}},592#pragma omp atomic capture593 {bx = civ - bx; bv = bx;}594// CHECK: [[IDX:%.+]] = load i16, ptr @{{.+}}595// CHECK: load i8, ptr596// CHECK: [[VEC_ITEM_VAL:%.+]] = zext i1 %{{.+}} to i32597// CHECK: [[I128VAL:%.+]] = load atomic i128, ptr [[DEST:@.+]] monotonic, align 16598// CHECK: br label %[[CONT:.+]]599// CHECK: [[CONT]]600// CHECK: [[OLD_I128:%.+]] = phi i128 [ [[I128VAL]], %{{.+}} ], [ [[FAILED_OLD_VAL:%.+]], %[[CONT]] ]601// CHECK: store i128 [[OLD_I128]], ptr [[TEMP:%.+]],602// CHECK: [[LD:%.+]] = bitcast i128 [[OLD_I128]] to <4 x i32>603// CHECK: store <4 x i32> [[LD]], ptr [[TEMP1:%.+]],604// CHECK: [[VEC_VAL:%.+]] = load <4 x i32>, ptr [[TEMP1]]605// CHECK: [[ITEM:%.+]] = extractelement <4 x i32> [[VEC_VAL]], i16 [[IDX]]606// CHECK: [[OR:%.+]] = or i32 [[ITEM]], [[VEC_ITEM_VAL]]607// CHECK: [[VEC_VAL:%.+]] = load <4 x i32>, ptr [[TEMP]]608// CHECK: [[NEW_VEC_VAL:%.+]] = insertelement <4 x i32> [[VEC_VAL]], i32 [[OR]], i16 [[IDX]]609// CHECK: store <4 x i32> [[NEW_VEC_VAL]], ptr [[TEMP]]610// CHECK: [[NEW_I128:%.+]] = load i128, ptr [[TEMP]],611// CHECK: [[RES:%.+]] = cmpxchg ptr [[DEST]], i128 [[OLD_I128]], i128 [[NEW_I128]] monotonic monotonic, align 16612// CHECK: [[FAILED_OLD_VAL:%.+]] = extractvalue { i128, i1 } [[RES]], 0613// CHECK: [[FAIL_SUCCESS:%.+]] = extractvalue { i128, i1 } [[RES]], 1614// CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]]615// CHECK: [[EXIT]]616// CHECK: store i32 [[OR]], ptr @{{.+}},617#pragma omp atomic capture618 {int4x[sv] |= bv; iv = int4x[sv];}619// CHECK: [[EXPR:%.+]] = load x86_fp80, ptr @{{.+}}620// CHECK: [[PREV_VALUE:%.+]] = load atomic i32, ptr getelementptr (i8, ptr @{{.+}}, i64 4) monotonic, align 4621// CHECK: br label %[[CONT:.+]]622// CHECK: [[CONT]]623// CHECK: [[OLD_BF_VALUE:%.+]] = phi i32 [ [[PREV_VALUE]], %[[EXIT]] ], [ [[FAILED_OLD_VAL:%.+]], %[[CONT]] ]624// CHECK: store i32 [[OLD_BF_VALUE]], ptr [[TEMP1:%.+]],625// CHECK: store i32 [[OLD_BF_VALUE]], ptr [[TEMP:%.+]],626// CHECK: [[A_LD:%.+]] = load i32, ptr [[TEMP]],627// CHECK: [[A_SHL:%.+]] = shl i32 [[A_LD]], 1628// CHECK: [[A_ASHR:%.+]] = ashr i32 [[A_SHL]], 1629// CHECK: [[X_RVAL:%.+]] = sitofp i32 [[A_ASHR]] to x86_fp80630// CHECK: [[SUB:%.+]] = fsub x86_fp80 [[X_RVAL]], [[EXPR]]631// CHECK: [[CONV:%.+]] = fptosi x86_fp80 [[SUB]] to i32632// CHECK: [[NEW_VAL:%.+]] = load i32, ptr [[TEMP1]],633// CHECK: [[BF_VALUE:%.+]] = and i32 [[CONV]], 2147483647634// CHECK: [[BF_CLEAR:%.+]] = and i32 [[NEW_VAL]], -2147483648635// CHECK: [[BF_SET:%.+]] = or i32 [[BF_CLEAR]], [[BF_VALUE]]636// CHECK: store i32 [[BF_SET]], ptr [[TEMP1]],637// CHECK: [[NEW_BF_VALUE:%.+]] = load i32, ptr [[TEMP1]],638// CHECK: [[RES:%.+]] = cmpxchg ptr getelementptr (i8, ptr @{{.+}}, i64 4), i32 [[OLD_BF_VALUE]], i32 [[NEW_BF_VALUE]] monotonic monotonic, align 4639// CHECK: [[FAILED_OLD_VAL]] = extractvalue { i32, i1 } [[RES]], 0640// CHECK: [[FAIL_SUCCESS:%.+]] = extractvalue { i32, i1 } [[RES]], 1641// CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]]642// CHECK: [[EXIT]]643// CHECK: store i32 [[CONV]], ptr @{{.+}},644#pragma omp atomic capture645 iv = bfx.a = bfx.a - ldv;646// CHECK: [[EXPR:%.+]] = load x86_fp80, ptr @{{.+}}647// CHECK: call void @__atomic_load(i64 noundef 4, ptr noundef getelementptr (i8, ptr @{{.+}}, i64 4), ptr noundef [[LDTEMP:%.+]], i32 noundef 0)648// CHECK: br label %[[CONT:.+]]649// CHECK: [[CONT]]650// CHECK: [[OLD:%.+]] = load i32, ptr [[LDTEMP]],651// CHECK: store i32 [[OLD]], ptr [[TEMP1:%.+]],652// CHECK: [[OLD:%.+]] = load i32, ptr [[LDTEMP]],653// CHECK: store i32 [[OLD]], ptr [[TEMP:%.+]],654// CHECK: [[A_LD:%.+]] = load i32, ptr [[TEMP]],655// CHECK: [[A_SHL:%.+]] = shl i32 [[A_LD]], 1656// CHECK: [[A_ASHR:%.+]] = ashr i32 [[A_SHL]], 1657// CHECK: [[X_RVAL:%.+]] = sitofp i32 [[A_ASHR]] to x86_fp80658// CHECK: [[MUL:%.+]] = fmul x86_fp80 [[X_RVAL]], [[EXPR]]659// CHECK: [[CONV:%.+]] = fptosi x86_fp80 [[MUL]] to i32660// CHECK: [[NEW_VAL:%.+]] = load i32, ptr [[TEMP1]],661// CHECK: [[BF_VALUE:%.+]] = and i32 [[CONV]], 2147483647662// CHECK: [[BF_CLEAR:%.+]] = and i32 [[NEW_VAL]], -2147483648663// CHECK: or i32 [[BF_CLEAR]], [[BF_VALUE]]664// CHECK: store i32 %{{.+}}, ptr [[TEMP1]]665// CHECK: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 noundef 4, ptr noundef getelementptr (i8, ptr @{{.+}}, i64 4), ptr noundef [[LDTEMP]], ptr noundef [[TEMP1]], i32 noundef 0, i32 noundef 0)666// CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]]667// CHECK: [[EXIT]]668// CHECK: store i32 [[A_ASHR]], ptr @{{.+}},669#pragma omp atomic capture670 {iv = bfx_packed.a; bfx_packed.a *= ldv;}671// CHECK: [[EXPR:%.+]] = load x86_fp80, ptr @{{.+}}672// CHECK: [[PREV_VALUE:%.+]] = load atomic i32, ptr @{{.+}} monotonic, align 4673// CHECK: br label %[[CONT:.+]]674// CHECK: [[CONT]]675// CHECK: [[OLD_BF_VALUE:%.+]] = phi i32 [ [[PREV_VALUE]], %[[EXIT]] ], [ [[FAILED_OLD_VAL:%.+]], %[[CONT]] ]676// CHECK: store i32 [[OLD_BF_VALUE]], ptr [[TEMP1:%.+]],677// CHECK: store i32 [[OLD_BF_VALUE]], ptr [[TEMP:%.+]],678// CHECK: [[A_LD:%.+]] = load i32, ptr [[TEMP]],679// CHECK: [[A_ASHR:%.+]] = ashr i32 [[A_LD]], 31680// CHECK: [[X_RVAL:%.+]] = sitofp i32 [[A_ASHR]] to x86_fp80681// CHECK: [[SUB:%.+]] = fsub x86_fp80 [[X_RVAL]], [[EXPR]]682// CHECK: [[CONV:%.+]] = fptosi x86_fp80 [[SUB]] to i32683// CHECK: [[NEW_VAL:%.+]] = load i32, ptr [[TEMP1]],684// CHECK: [[BF_AND:%.+]] = and i32 [[CONV]], 1685// CHECK: [[BF_VALUE:%.+]] = shl i32 [[BF_AND]], 31686// CHECK: [[BF_CLEAR:%.+]] = and i32 [[NEW_VAL]], 2147483647687// CHECK: or i32 [[BF_CLEAR]], [[BF_VALUE]]688// CHECK: store i32 %{{.+}}, ptr [[TEMP1]]689// CHECK: [[NEW_BF_VALUE:%.+]] = load i32, ptr [[TEMP1]]690// CHECK: [[RES:%.+]] = cmpxchg ptr @{{.+}}, i32 [[OLD_BF_VALUE]], i32 [[NEW_BF_VALUE]] monotonic monotonic, align 4691// CHECK: [[FAILED_OLD_VAL]] = extractvalue { i32, i1 } [[RES]], 0692// CHECK: [[FAIL_SUCCESS:%.+]] = extractvalue { i32, i1 } [[RES]], 1693// CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]]694// CHECK: [[EXIT]]695// CHECK: store i32 [[CONV]], ptr @{{.+}},696#pragma omp atomic capture697 {bfx2.a -= ldv; iv = bfx2.a;}698// CHECK: [[EXPR:%.+]] = load x86_fp80, ptr @{{.+}}699// CHECK: [[PREV_VALUE:%.+]] = load atomic i8, ptr getelementptr (i8, ptr @{{.+}}, i64 3) monotonic, align 1700// CHECK: br label %[[CONT:.+]]701// CHECK: [[CONT]]702// CHECK: [[OLD_BF_VALUE:%.+]] = phi i8 [ [[PREV_VALUE]], %[[EXIT]] ], [ [[FAILED_OLD_VAL:%.+]], %[[CONT]] ]703// CHECK: store i8 [[OLD_BF_VALUE]], ptr [[BITCAST_NEW:%.+]],704// CHECK: store i8 [[OLD_BF_VALUE]], ptr [[BITCAST:%.+]],705// CHECK: [[A_LD:%.+]] = load i8, ptr [[BITCAST]],706// CHECK: [[A_ASHR:%.+]] = ashr i8 [[A_LD]], 7707// CHECK: [[CAST:%.+]] = sext i8 [[A_ASHR]] to i32708// CHECK: [[X_RVAL:%.+]] = sitofp i32 [[CAST]] to x86_fp80709// CHECK: [[DIV:%.+]] = fdiv x86_fp80 [[EXPR]], [[X_RVAL]]710// CHECK: [[NEW_VAL:%.+]] = fptosi x86_fp80 [[DIV]] to i32711// CHECK: [[TRUNC:%.+]] = trunc i32 [[NEW_VAL]] to i8712// CHECK: [[BF_LD:%.+]] = load i8, ptr [[BITCAST_NEW]],713// CHECK: [[BF_AND:%.+]] = and i8 [[TRUNC]], 1714// CHECK: [[BF_VALUE:%.+]] = shl i8 [[BF_AND]], 7715// CHECK: [[BF_CLEAR:%.+]] = and i8 %{{.+}}, 127716// CHECK: or i8 [[BF_CLEAR]], [[BF_VALUE]]717// CHECK: store i8 %{{.+}}, ptr [[BITCAST_NEW]]718// CHECK: [[NEW_BF_VALUE:%.+]] = load i8, ptr [[BITCAST_NEW]]719// CHECK: [[RES:%.+]] = cmpxchg ptr getelementptr (i8, ptr @{{.+}}, i64 3), i8 [[OLD_BF_VALUE]], i8 [[NEW_BF_VALUE]] monotonic monotonic, align 1720// CHECK: [[FAILED_OLD_VAL]] = extractvalue { i8, i1 } [[RES]], 0721// CHECK: [[FAIL_SUCCESS:%.+]] = extractvalue { i8, i1 } [[RES]], 1722// CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]]723// CHECK: [[EXIT]]724// CHECK: store i32 [[NEW_VAL]], ptr @{{.+}},725#pragma omp atomic capture726 iv = bfx2_packed.a = ldv / bfx2_packed.a;727// CHECK: [[EXPR:%.+]] = load x86_fp80, ptr @{{.+}}728// CHECK: [[PREV_VALUE:%.+]] = load atomic i32, ptr @{{.+}} monotonic, align 4729// CHECK: br label %[[CONT:.+]]730// CHECK: [[CONT]]731// CHECK: [[OLD_BF_VALUE:%.+]] = phi i32 [ [[PREV_VALUE]], %[[EXIT]] ], [ [[FAILED_OLD_VAL:%.+]], %[[CONT]] ]732// CHECK: store i32 [[OLD_BF_VALUE]], ptr [[TEMP1:%.+]],733// CHECK: store i32 [[OLD_BF_VALUE]], ptr [[TEMP:%.+]],734// CHECK: [[A_LD:%.+]] = load i32, ptr [[TEMP]],735// CHECK: [[A_SHL:%.+]] = shl i32 [[A_LD]], 7736// CHECK: [[A_ASHR:%.+]] = ashr i32 [[A_SHL]], 18737// CHECK: [[X_RVAL:%.+]] = sitofp i32 [[A_ASHR]] to x86_fp80738// CHECK: [[DIV:%.+]] = fdiv x86_fp80 [[X_RVAL]], [[EXPR]]739// CHECK: [[NEW_VAL:%.+]] = fptosi x86_fp80 [[DIV]] to i32740// CHECK: [[BF_LD:%.+]] = load i32, ptr [[TEMP1]],741// CHECK: [[BF_AND:%.+]] = and i32 [[NEW_VAL]], 16383742// CHECK: [[BF_VALUE:%.+]] = shl i32 [[BF_AND]], 11743// CHECK: [[BF_CLEAR:%.+]] = and i32 %{{.+}}, -33552385744// CHECK: or i32 [[BF_CLEAR]], [[BF_VALUE]]745// CHECK: store i32 %{{.+}}, ptr [[TEMP1]]746// CHECK: [[NEW_BF_VALUE:%.+]] = load i32, ptr [[TEMP1]]747// CHECK: [[RES:%.+]] = cmpxchg ptr @{{.+}}, i32 [[OLD_BF_VALUE]], i32 [[NEW_BF_VALUE]] monotonic monotonic, align 4748// CHECK: [[FAILED_OLD_VAL]] = extractvalue { i32, i1 } [[RES]], 0749// CHECK: [[FAIL_SUCCESS:%.+]] = extractvalue { i32, i1 } [[RES]], 1750// CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]]751// CHECK: [[EXIT]]752// CHECK: store i32 [[A_ASHR]], ptr @{{.+}},753#pragma omp atomic capture754 {iv = bfx3.a; bfx3.a /= ldv;}755// CHECK: [[EXPR:%.+]] = load x86_fp80, ptr @{{.+}}756// CHECK: call void @__atomic_load(i64 noundef 3, ptr noundef getelementptr (i8, ptr @{{.+}}, i64 1), ptr noundef [[LDTEMP:%.+]], i32 noundef 0)757// CHECK: br label %[[CONT:.+]]758// CHECK: [[CONT]]759// CHECK: [[OLD:%.+]] = load i24, ptr [[LDTEMP]],760// CHECK: store i24 [[OLD]], ptr [[BITCAST2:%.+]],761// CHECK: [[OLD:%.+]] = load i24, ptr [[LDTEMP]],762// CHECK: store i24 [[OLD]], ptr [[BITCAST1:%.+]],763// CHECK: [[A_LD:%.+]] = load i24, ptr [[BITCAST1]],764// CHECK: [[A_SHL:%.+]] = shl i24 [[A_LD]], 7765// CHECK: [[A_ASHR:%.+]] = ashr i24 [[A_SHL]], 10766// CHECK: [[CAST:%.+]] = sext i24 [[A_ASHR]] to i32767// CHECK: [[X_RVAL:%.+]] = sitofp i32 [[CAST]] to x86_fp80768// CHECK: [[ADD:%.+]] = fadd x86_fp80 [[X_RVAL]], [[EXPR]]769// CHECK: [[NEW_VAL:%.+]] = fptosi x86_fp80 [[ADD]] to i32770// CHECK: [[TRUNC:%.+]] = trunc i32 [[NEW_VAL]] to i24771// CHECK: [[BF_LD:%.+]] = load i24, ptr [[BITCAST2]],772// CHECK: [[BF_AND:%.+]] = and i24 [[TRUNC]], 16383773// CHECK: [[BF_VALUE:%.+]] = shl i24 [[BF_AND]], 3774// CHECK: [[BF_CLEAR:%.+]] = and i24 [[BF_LD]], -131065775// CHECK: or i24 [[BF_CLEAR]], [[BF_VALUE]]776// CHECK: store i24 %{{.+}}, ptr [[BITCAST2]]777// CHECK: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 noundef 3, ptr noundef getelementptr (i8, ptr @{{.+}}, i64 1), ptr noundef [[LDTEMP]], ptr noundef [[BITCAST2]], i32 noundef 0, i32 noundef 0)778// CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]]779// CHECK: [[EXIT]]780// CHECK: store i32 [[NEW_VAL]], ptr @{{.+}},781#pragma omp atomic capture782 {bfx3_packed.a += ldv; iv = bfx3_packed.a;}783// CHECK: [[EXPR:%.+]] = load x86_fp80, ptr @{{.+}}784// CHECK: [[PREV_VALUE:%.+]] = load atomic i64, ptr @{{.+}} monotonic, align 8785// CHECK: br label %[[CONT:.+]]786// CHECK: [[CONT]]787// CHECK: [[OLD_BF_VALUE:%.+]] = phi i64 [ [[PREV_VALUE]], %[[EXIT]] ], [ [[FAILED_OLD_VAL:%.+]], %[[CONT]] ]788// CHECK: store i64 [[OLD_BF_VALUE]], ptr [[TEMP1:%.+]],789// CHECK: store i64 [[OLD_BF_VALUE]], ptr [[TEMP:%.+]],790// CHECK: [[A_LD:%.+]] = load i64, ptr [[TEMP]],791// CHECK: [[A_SHL:%.+]] = shl i64 [[A_LD]], 47792// CHECK: [[A_ASHR:%.+]] = ashr i64 [[A_SHL:%.+]], 63793// CHECK: [[A_CAST:%.+]] = trunc i64 [[A_ASHR:%.+]] to i32794// CHECK: [[X_RVAL:%.+]] = sitofp i32 [[CAST:%.+]] to x86_fp80795// CHECK: [[MUL:%.+]] = fmul x86_fp80 [[X_RVAL]], [[EXPR]]796// CHECK: [[NEW_VAL:%.+]] = fptosi x86_fp80 [[MUL]] to i32797// CHECK: [[ZEXT:%.+]] = zext i32 [[NEW_VAL]] to i64798// CHECK: [[BF_LD:%.+]] = load i64, ptr [[TEMP1]],799// CHECK: [[BF_AND:%.+]] = and i64 [[ZEXT]], 1800// CHECK: [[BF_VALUE:%.+]] = shl i64 [[BF_AND]], 16801// CHECK: [[BF_CLEAR:%.+]] = and i64 [[BF_LD]], -65537802// CHECK: or i64 [[BF_CLEAR]], [[BF_VALUE]]803// CHECK: store i64 %{{.+}}, ptr [[TEMP1]]804// CHECK: [[NEW_BF_VALUE:%.+]] = load i64, ptr [[TEMP1]]805// CHECK: [[RES:%.+]] = cmpxchg ptr @{{.+}}, i64 [[OLD_BF_VALUE]], i64 [[NEW_BF_VALUE]] monotonic monotonic, align 8806// CHECK: [[FAILED_OLD_VAL]] = extractvalue { i64, i1 } [[RES]], 0807// CHECK: [[FAIL_SUCCESS:%.+]] = extractvalue { i64, i1 } [[RES]], 1808// CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]]809// CHECK: [[EXIT]]810// CHECK: store i32 [[NEW_VAL]], ptr @{{.+}},811#pragma omp atomic relaxed capture812 iv = bfx4.a = bfx4.a * ldv;813// CHECK: [[EXPR:%.+]] = load x86_fp80, ptr @{{.+}}814// CHECK: [[PREV_VALUE:%.+]] = load atomic i8, ptr getelementptr inbounds nuw (%struct.BitFields4_packed, ptr @{{.+}}, i32 0, i32 1) monotonic, align 1815// CHECK: br label %[[CONT:.+]]816// CHECK: [[CONT]]817// CHECK: [[OLD_BF_VALUE:%.+]] = phi i8 [ [[PREV_VALUE]], %{{.+}} ], [ [[FAILED_OLD_VAL:%.+]], %[[CONT]] ]818// CHECK: store i8 [[OLD_BF_VALUE]], ptr [[BITCAST1:%.+]],819// CHECK: store i8 [[OLD_BF_VALUE]], ptr [[BITCAST:%.+]],820// CHECK: [[A_LD:%.+]] = load i8, ptr [[BITCAST]],821// CHECK: [[A_SHL:%.+]] = shl i8 [[A_LD]], 7822// CHECK: [[A_ASHR:%.+]] = ashr i8 [[A_SHL:%.+]], 7823// CHECK: [[CAST:%.+]] = sext i8 [[A_ASHR:%.+]] to i32824// CHECK: [[CONV:%.+]] = sitofp i32 [[CAST]] to x86_fp80825// CHECK: [[SUB: %.+]] = fsub x86_fp80 [[CONV]], [[EXPR]]826// CHECK: [[CONV:%.+]] = fptosi x86_fp80 [[SUB:%.+]] to i32827// CHECK: [[NEW_VAL:%.+]] = trunc i32 [[CONV]] to i8828// CHECK: [[BF_LD:%.+]] = load i8, ptr [[BITCAST1]],829// CHECK: [[BF_VALUE:%.+]] = and i8 [[NEW_VAL]], 1830// CHECK: [[BF_CLEAR:%.+]] = and i8 [[BF_LD]], -2831// CHECK: or i8 [[BF_CLEAR]], [[BF_VALUE]]832// CHECK: store i8 %{{.+}}, ptr [[BITCAST1]]833// CHECK: [[NEW_BF_VALUE:%.+]] = load i8, ptr [[BITCAST1]]834// CHECK: [[RES:%.+]] = cmpxchg ptr getelementptr inbounds nuw (%struct.BitFields4_packed, ptr @{{.+}}, i32 0, i32 1), i8 [[OLD_BF_VALUE]], i8 [[NEW_BF_VALUE]] monotonic monotonic, align 1835// CHECK: [[FAILED_OLD_VAL]] = extractvalue { i8, i1 } [[RES]], 0836// CHECK: [[FAIL_SUCCESS:%.+]] = extractvalue { i8, i1 } [[RES]], 1837// CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]]838// CHECK: [[EXIT]]839// CHECK: store i32 [[CAST]], ptr @{{.+}},840#pragma omp atomic capture relaxed841 {iv = bfx4_packed.a; bfx4_packed.a -= ldv;}842// CHECK: [[EXPR:%.+]] = load x86_fp80, ptr @{{.+}}843// CHECK: [[PREV_VALUE:%.+]] = load atomic i64, ptr @{{.+}} monotonic, align 8844// CHECK: br label %[[CONT:.+]]845// CHECK: [[CONT]]846// CHECK: [[OLD_BF_VALUE:%.+]] = phi i64 [ [[PREV_VALUE]], %[[EXIT]] ], [ [[FAILED_OLD_VAL:%.+]], %[[CONT]] ]847// CHECK: store i64 [[OLD_BF_VALUE]], ptr [[TEMP1:%.+]],848// CHECK: store i64 [[OLD_BF_VALUE]], ptr [[TEMP:%.+]],849// CHECK: [[A_LD:%.+]] = load i64, ptr [[TEMP]],850// CHECK: [[A_SHL:%.+]] = shl i64 [[A_LD]], 40851// CHECK: [[A_ASHR:%.+]] = ashr i64 [[A_SHL:%.+]], 57852// CHECK: [[CONV:%.+]] = sitofp i64 [[A_ASHR]] to x86_fp80853// CHECK: [[DIV:%.+]] = fdiv x86_fp80 [[CONV]], [[EXPR]]854// CHECK: [[CONV:%.+]] = fptosi x86_fp80 [[DIV]] to i64855// CHECK: [[BF_LD:%.+]] = load i64, ptr [[TEMP1]],856// CHECK: [[BF_AND:%.+]] = and i64 [[CONV]], 127857// CHECK: [[BF_VALUE:%.+]] = shl i64 [[BF_AND:%.+]], 17858// CHECK: [[BF_CLEAR:%.+]] = and i64 [[BF_LD]], -16646145859// CHECK: [[VAL:%.+]] = or i64 [[BF_CLEAR]], [[BF_VALUE]]860// CHECK: store i64 [[VAL]], ptr [[TEMP1]]861// CHECK: [[NEW_BF_VALUE:%.+]] = load i64, ptr [[TEMP1]]862// CHECK: [[RES:%.+]] = cmpxchg ptr @{{.+}}, i64 [[OLD_BF_VALUE]], i64 [[NEW_BF_VALUE]] release monotonic, align 8863// CHECK: [[FAILED_OLD_VAL]] = extractvalue { i64, i1 } [[RES]], 0864// CHECK: [[FAIL_SUCCESS:%.+]] = extractvalue { i64, i1 } [[RES]], 1865// CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]]866// CHECK: [[EXIT]]867// CHECK: [[NEW_VAL:%.+]] = trunc i64 [[CONV]] to i32868// CHECK: store i32 [[NEW_VAL]], ptr @{{.+}},869// CHECK-50: call{{.*}} @__kmpc_flush(870#pragma omp atomic capture release871 {bfx4.b /= ldv; iv = bfx4.b;}872// CHECK: [[EXPR:%.+]] = load x86_fp80, ptr @{{.+}}873// CHECK: [[PREV_VALUE:%.+]] = load atomic i8, ptr getelementptr inbounds nuw (%struct.BitFields4_packed, ptr @{{.+}}, i32 0, i32 1) acquire, align 1874// CHECK: br label %[[CONT:.+]]875// CHECK: [[CONT]]876// CHECK: [[OLD_BF_VALUE:%.+]] = phi i8 [ [[PREV_VALUE]], %[[EXIT]] ], [ [[FAILED_OLD_VAL:%.+]], %[[CONT]] ]877// CHECK: store i8 [[OLD_BF_VALUE]], ptr [[BITCAST1:%.+]],878// CHECK: store i8 [[OLD_BF_VALUE]], ptr [[BITCAST:%.+]],879// CHECK: [[A_LD:%.+]] = load i8, ptr [[BITCAST]],880// CHECK: [[A_ASHR:%.+]] = ashr i8 [[A_LD]], 1881// CHECK: [[CAST:%.+]] = sext i8 [[A_ASHR]] to i64882// CHECK: [[CONV:%.+]] = sitofp i64 [[CAST]] to x86_fp80883// CHECK: [[ADD:%.+]] = fadd x86_fp80 [[CONV]], [[EXPR]]884// CHECK: [[NEW_VAL:%.+]] = fptosi x86_fp80 [[ADD]] to i64885// CHECK: [[TRUNC:%.+]] = trunc i64 [[NEW_VAL]] to i8886// CHECK: [[BF_LD:%.+]] = load i8, ptr [[BITCAST1]],887// CHECK: [[BF_AND:%.+]] = and i8 [[TRUNC]], 127888// CHECK: [[BF_VALUE:%.+]] = shl i8 [[BF_AND]], 1889// CHECK: [[BF_CLEAR:%.+]] = and i8 [[BF_LD]], 1890// CHECK: or i8 [[BF_CLEAR]], [[BF_VALUE]]891// CHECK: store i8 %{{.+}}, ptr [[BITCAST1]]892// CHECK: [[NEW_BF_VALUE:%.+]] = load i8, ptr [[BITCAST1]]893// CHECK: [[RES:%.+]] = cmpxchg ptr getelementptr inbounds nuw (%struct.BitFields4_packed, ptr @{{.+}}, i32 0, i32 1), i8 [[OLD_BF_VALUE]], i8 [[NEW_BF_VALUE]] acquire acquire, align 1894// CHECK: [[FAILED_OLD_VAL]] = extractvalue { i8, i1 } [[RES]], 0895// CHECK: [[FAIL_SUCCESS:%.+]] = extractvalue { i8, i1 } [[RES]], 1896// CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]]897// CHECK: [[EXIT]]898// CHECK: [[NEW_VAL_I32:%.+]] = trunc i64 [[NEW_VAL]] to i32899// CHECK: store i32 [[NEW_VAL_I32]], ptr @{{.+}},900// CHECK-50: call{{.*}} @__kmpc_flush(901#pragma omp atomic capture acquire902 iv = bfx4_packed.b += ldv;903// CHECK: load i64, ptr904// CHECK: [[EXPR:%.+]] = uitofp i64 %{{.+}} to float905// CHECK: [[I64VAL:%.+]] = load atomic i64, ptr [[DEST:@.+]] acquire, align 8906// CHECK: br label %[[CONT:.+]]907// CHECK: [[CONT]]908// CHECK: [[OLD_I64:%.+]] = phi i64 [ [[I64VAL]], %{{.+}} ], [ [[FAILED_I64_OLD_VAL:%.+]], %[[CONT]] ]909// CHECK: store i64 [[OLD_I64]], ptr [[LDTEMP1:%.+]],910// CHECK: [[OLD_VEC_VAL:%.+]] = bitcast i64 [[OLD_I64]] to <2 x float>911// CHECK: store <2 x float> [[OLD_VEC_VAL]], ptr [[LDTEMP:%.+]],912// CHECK: [[VEC_VAL:%.+]] = load <2 x float>, ptr [[LDTEMP]]913// CHECK: [[X:%.+]] = extractelement <2 x float> [[VEC_VAL]], i64 0914// CHECK: [[VEC_ITEM_VAL:%.+]] = fsub float [[EXPR]], [[X]]915// CHECK: [[VEC_VAL:%.+]] = load <2 x float>, ptr [[LDTEMP1]],916// CHECK: [[NEW_VEC_VAL:%.+]] = insertelement <2 x float> [[VEC_VAL]], float [[VEC_ITEM_VAL]], i64 0917// CHECK: store <2 x float> [[NEW_VEC_VAL]], ptr [[LDTEMP1]]918// CHECK: [[NEW_I64:%.+]] = load i64, ptr [[LDTEMP1]]919// CHECK: [[RES:%.+]] = cmpxchg ptr [[DEST]], i64 [[OLD_I64]], i64 [[NEW_I64]] acq_rel acquire, align 8920// CHECK: [[FAILED_I64_OLD_VAL:%.+]] = extractvalue { i64, i1 } [[RES]], 0921// CHECK: [[FAIL_SUCCESS:%.+]] = extractvalue { i64, i1 } [[RES]], 1922// CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]]923// CHECK: [[EXIT]]924// CHECK: store float [[X]], ptr @{{.+}},925// CHECK-50: call{{.*}} @__kmpc_flush(926#pragma omp atomic capture acq_rel927 {fv = float2x.x; float2x.x = ulv - float2x.x;}928// CHECK: [[EXPR:%.+]] = load double, ptr @{{.+}},929// CHECK: [[OLD_VAL:%.+]] = call i32 @llvm.read_register.i32([[REG:metadata ![0-9]+]])930// CHECK: [[X_RVAL:%.+]] = sitofp i32 [[OLD_VAL]] to double931// CHECK: [[DIV:%.+]] = fdiv double [[EXPR]], [[X_RVAL]]932// CHECK: [[NEW_VAL:%.+]] = fptosi double [[DIV]] to i32933// CHECK: call void @llvm.write_register.i32([[REG]], i32 [[NEW_VAL]])934// CHECK: store i32 [[NEW_VAL]], ptr @{{.+}},935// CHECK-50: call{{.*}} @__kmpc_flush(936#pragma omp atomic capture seq_cst937 {rix = dv / rix; iv = rix;}938// CHECK: [[OLD_VAL:%.+]] = atomicrmw xchg ptr @{{.+}}, i32 5 monotonic, align 4939// CHECK: call void @llvm.write_register.i32([[REG]], i32 [[OLD_VAL]])940#pragma omp atomic capture941 {rix = ix; ix = 5;}942 return 0;943}944#endif945