869 lines · cpp
1// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -target-cpu core2 -fopenmp -x c -emit-llvm %s -o - | FileCheck %s2// RUN: %clang_cc1 -fopenmp -x c -triple x86_64-apple-darwin10 -target-cpu core2 -emit-pch -o %t %s3// RUN: %clang_cc1 -fopenmp -x c -triple x86_64-apple-darwin10 -target-cpu core2 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s4 5// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -target-cpu core2 -fopenmp-simd -x c -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s6// RUN: %clang_cc1 -fopenmp-simd -x c -triple x86_64-apple-darwin10 -target-cpu core2 -emit-pch -o %t %s7// RUN: %clang_cc1 -fopenmp-simd -x c -triple x86_64-apple-darwin10 -target-cpu core2 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s8// SIMD-ONLY0-NOT: {{__kmpc|__tgt}}9// expected-no-diagnostics10#ifndef HEADER11#define HEADER12 13_Bool bv, bx;14char cv, cx;15unsigned char ucv, ucx;16short sv, sx;17unsigned short usv, usx;18int iv, ix;19unsigned int uiv, uix;20long lv, lx;21unsigned long ulv, ulx;22long long llv, llx;23unsigned long long ullv, ullx;24float fv, fx;25double dv, dx;26long double ldv, ldx;27_Complex int civ, cix;28_Complex float cfv, cfx;29_Complex double cdv, cdx;30char *cpx;31 32typedef int int4 __attribute__((__vector_size__(16)));33int4 int4x;34 35struct BitFields {36 int : 32;37 int a : 31;38} bfx;39 40struct BitFields_packed {41 int : 32;42 int a : 31;43} __attribute__ ((__packed__)) bfx_packed;44 45struct BitFields2 {46 int : 31;47 int a : 1;48} bfx2;49 50struct BitFields2_packed {51 int : 31;52 int a : 1;53} __attribute__ ((__packed__)) bfx2_packed;54 55struct BitFields3 {56 int : 11;57 int a : 14;58} bfx3;59 60struct BitFields3_packed {61 int : 11;62 int a : 14;63} __attribute__ ((__packed__)) bfx3_packed;64 65struct BitFields4 {66 short : 16;67 int a: 1;68 long b : 7;69} bfx4;70 71struct BitFields4_packed {72 short : 16;73 int a: 1;74 long b : 7;75} __attribute__ ((__packed__)) bfx4_packed;76 77typedef float float2 __attribute__((ext_vector_type(2)));78float2 float2x;79 80// Register "0" is currently an invalid register for global register variables.81// Use "esp" instead of "0".82// register int rix __asm__("0");83register int rix __asm__("esp");84 85int main(void) {86// CHECK: atomicrmw fadd ptr @{{.+}}, double 1.000000e+00 monotonic, align 887#pragma omp atomic88 ++dv;89// CHECK: atomicrmw add ptr @{{.+}}, i8 1 monotonic, align 190#pragma omp atomic91 bx++;92// CHECK: atomicrmw add ptr @{{.+}}, i8 1 monotonic, align 193#pragma omp atomic update94 ++cx;95// CHECK: atomicrmw sub ptr @{{.+}}, i8 1 monotonic, align 196#pragma omp atomic97 ucx--;98// CHECK: atomicrmw sub ptr @{{.+}}, i16 1 monotonic, align 299#pragma omp atomic update100 --sx;101// CHECK: [[USV:%.+]] = load i16, ptr @{{.+}},102// CHECK: [[EXPR:%.+]] = zext i16 [[USV]] to i32103// CHECK: [[X:%.+]] = load atomic i16, ptr [[X_ADDR:@.+]] monotonic, align 2104// CHECK: br label %[[CONT:.+]]105// CHECK: [[CONT]]106// CHECK: [[EXPECTED:%.+]] = phi i16 [ [[X]], %{{.+}} ], [ [[OLD_X:%.+]], %[[CONT]] ]107// CHECK: [[CONV:%.+]] = zext i16 [[EXPECTED]] to i32108// CHECK: [[ADD:%.+]] = add nsw i32 [[CONV]], [[EXPR]]109// CHECK: [[DESIRED:%.+]] = trunc i32 [[ADD]] to i16110// CHECK: store i16 [[DESIRED]], ptr [[TEMP:%.+]],111// CHECK: [[DESIRED:%.+]] = load i16, ptr [[TEMP]],112// CHECK: [[RES:%.+]] = cmpxchg ptr [[X_ADDR]], i16 [[EXPECTED]], i16 [[DESIRED]] monotonic monotonic, align 2113// CHECK: [[OLD_X]] = extractvalue { i16, i1 } [[RES]], 0114// CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i16, i1 } [[RES]], 1115// CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]]116// CHECK: [[EXIT]]117#pragma omp atomic118 usx += usv;119// CHECK: [[EXPR:%.+]] = load i32, ptr @{{.+}},120// CHECK: [[X:%.+]] = load atomic i32, ptr [[X_ADDR:@.+]] monotonic, align 4121// CHECK: br label %[[CONT:.+]]122// CHECK: [[CONT]]123// CHECK: [[EXPECTED:%.+]] = phi i32 [ [[X]], %{{.+}} ], [ [[OLD_X:%.+]], %[[CONT]] ]124// CHECK: [[DESIRED:%.+]] = mul nsw i32 [[EXPECTED]], [[EXPR]]125// CHECK: store i32 [[DESIRED]], ptr [[TEMP:%.+]],126// CHECK: [[DESIRED:%.+]] = load i32, ptr [[TEMP]],127// CHECK: [[RES:%.+]] = cmpxchg ptr [[X_ADDR]], i32 [[EXPECTED]], i32 [[DESIRED]] monotonic monotonic, align 4128// CHECK: [[OLD_X]] = extractvalue { i32, i1 } [[RES]], 0129// CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i32, i1 } [[RES]], 1130// CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]]131// CHECK: [[EXIT]]132#pragma omp atomic update133 ix *= iv;134// CHECK: [[EXPR:%.+]] = load i32, ptr @{{.+}},135// CHECK: atomicrmw sub ptr @{{.+}}, i32 [[EXPR]] monotonic, align 4136#pragma omp atomic137 uix -= uiv;138// CHECK: [[EXPR:%.+]] = load i32, ptr @{{.+}},139// CHECK: [[X:%.+]] = load atomic i32, ptr [[X_ADDR:@.+]] monotonic, align 4140// CHECK: br label %[[CONT:.+]]141// CHECK: [[CONT]]142// CHECK: [[EXPECTED:%.+]] = phi i32 [ [[X]], %{{.+}} ], [ [[OLD_X:%.+]], %[[CONT]] ]143// CHECK: [[DESIRED:%.+]] = shl i32 [[EXPECTED]], [[EXPR]]144// CHECK: store i32 [[DESIRED]], ptr [[TEMP:%.+]],145// CHECK: [[DESIRED:%.+]] = load i32, ptr [[TEMP]],146// CHECK: [[RES:%.+]] = cmpxchg ptr [[X_ADDR]], i32 [[EXPECTED]], i32 [[DESIRED]] monotonic monotonic, align 4147// CHECK: [[OLD_X]] = extractvalue { i32, i1 } [[RES]], 0148// CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i32, i1 } [[RES]], 1149// CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]]150// CHECK: [[EXIT]]151#pragma omp atomic update152 ix <<= iv;153// CHECK: [[EXPR:%.+]] = load i32, ptr @{{.+}},154// CHECK: [[X:%.+]] = load atomic i32, ptr [[X_ADDR:@.+]] monotonic, align 4155// CHECK: br label %[[CONT:.+]]156// CHECK: [[CONT]]157// CHECK: [[EXPECTED:%.+]] = phi i32 [ [[X]], %{{.+}} ], [ [[OLD_X:%.+]], %[[CONT]] ]158// CHECK: [[DESIRED:%.+]] = lshr i32 [[EXPECTED]], [[EXPR]]159// CHECK: store i32 [[DESIRED]], ptr [[TEMP:%.+]],160// CHECK: [[DESIRED:%.+]] = load i32, ptr [[TEMP]],161// CHECK: [[RES:%.+]] = cmpxchg ptr [[X_ADDR]], i32 [[EXPECTED]], i32 [[DESIRED]] monotonic monotonic, align 4162// CHECK: [[OLD_X]] = extractvalue { i32, i1 } [[RES]], 0163// CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i32, i1 } [[RES]], 1164// CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]]165// CHECK: [[EXIT]]166#pragma omp atomic167 uix >>= uiv;168// CHECK: [[EXPR:%.+]] = load i64, ptr @{{.+}},169// CHECK: [[X:%.+]] = load atomic i64, ptr [[X_ADDR:@.+]] monotonic, align 8170// CHECK: br label %[[CONT:.+]]171// CHECK: [[CONT]]172// CHECK: [[EXPECTED:%.+]] = phi i64 [ [[X]], %{{.+}} ], [ [[OLD_X:%.+]], %[[CONT]] ]173// CHECK: [[DESIRED:%.+]] = sdiv i64 [[EXPECTED]], [[EXPR]]174// CHECK: store i64 [[DESIRED]], ptr [[TEMP:%.+]],175// CHECK: [[DESIRED:%.+]] = load i64, ptr [[TEMP]],176// CHECK: [[RES:%.+]] = cmpxchg ptr [[X_ADDR]], i64 [[EXPECTED]], i64 [[DESIRED]] monotonic monotonic, align 8177// CHECK: [[OLD_X]] = extractvalue { i64, i1 } [[RES]], 0178// CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i64, i1 } [[RES]], 1179// CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]]180// CHECK: [[EXIT]]181#pragma omp atomic update182 lx /= lv;183// CHECK: [[EXPR:%.+]] = load i64, ptr @{{.+}},184// CHECK: atomicrmw and ptr @{{.+}}, i64 [[EXPR]] monotonic, align 8185#pragma omp atomic186 ulx &= ulv;187// CHECK: [[EXPR:%.+]] = load i64, ptr @{{.+}},188// CHECK: atomicrmw xor ptr @{{.+}}, i64 [[EXPR]] monotonic, align 8189#pragma omp atomic update190 llx ^= llv;191// CHECK: [[EXPR:%.+]] = load i64, ptr @{{.+}},192// CHECK: atomicrmw or ptr @{{.+}}, i64 [[EXPR]] monotonic, align 8193#pragma omp atomic194 ullx |= ullv;195// CHECK: [[EXPR:%.+]] = load float, ptr @{{.+}},196// CHECK: atomicrmw fadd ptr @{{.+}}, float [[EXPR]] monotonic, align 4197#pragma omp atomic update198 fx = fx + fv;199// CHECK: [[EXPR:%.+]] = load double, ptr @{{.+}},200// CHECK: [[OLD:%.+]] = load atomic i64, ptr [[X_ADDR:@.+]] monotonic, align 8201// CHECK: br label %[[CONT:.+]]202// CHECK: [[CONT]]203// CHECK: [[EXPECTED:%.+]] = phi i64 [ [[OLD]], %{{.+}} ], [ [[PREV:%.+]], %[[CONT]] ]204// CHECK: [[OLD:%.+]] = bitcast i64 [[EXPECTED]] to double205// CHECK: [[SUB:%.+]] = fsub double [[EXPR]], [[OLD]]206// CHECK: store double [[SUB]], ptr [[TEMP:%.+]],207// CHECK: [[DESIRED:%.+]] = load i64, ptr [[TEMP]],208// CHECK: [[RES:%.+]] = cmpxchg ptr [[X_ADDR]], i64 [[EXPECTED]], i64 [[DESIRED]] monotonic monotonic, align 8209// CHECK: [[PREV:%.+]] = extractvalue { i64, i1 } [[RES]], 0210// CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i64, i1 } [[RES]], 1211// CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]]212// CHECK: [[EXIT]]213#pragma omp atomic214 dx = dv - dx;215// CHECK: [[EXPR:%.+]] = load x86_fp80, ptr @{{.+}},216// CHECK: [[OLD:%.+]] = load atomic i128, ptr [[X_ADDR:@.+]] monotonic, align 16217// CHECK: br label %[[CONT:.+]]218// CHECK: [[CONT]]219// CHECK: [[EXPECTED:%.+]] = phi i128 [ [[OLD]], %{{.+}} ], [ [[PREV:%.+]], %[[CONT]] ]220// CHECK: store i128 [[EXPECTED]], ptr [[TEMP:%.+]],221// CHECK: store i128 [[EXPECTED]], ptr [[TEMP1:%.+]],222// CHECK: [[OLD:%.+]] = load x86_fp80, ptr [[TEMP1]]223// CHECK: [[MUL:%.+]] = fmul x86_fp80 [[OLD]], [[EXPR]]224// CHECK: store x86_fp80 [[MUL]], ptr [[TEMP]]225// CHECK: [[DESIRED:%.+]] = load i128, ptr [[TEMP]]226// CHECK: [[RES:%.+]] = cmpxchg ptr [[X_ADDR]], i128 [[EXPECTED]], i128 [[DESIRED]] monotonic monotonic, align 16227// CHECK: [[PREV:%.+]] = extractvalue { i128, i1 } [[RES]], 0228// CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i128, i1 } [[RES]], 1229// CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]]230// CHECK: [[EXIT]]231#pragma omp atomic update232 ldx = ldx * ldv;233// CHECK: [[EXPR_RE:%.+]] = load i32, ptr @{{.+}}234// CHECK: [[EXPR_IM:%.+]] = load i32, ptr getelementptr inbounds nuw ({ i32, i32 }, ptr @{{.+}}, i32 0, i32 1)235// CHECK: call void @__atomic_load(i64 noundef 8, ptr noundef [[X_ADDR:@.+]], ptr noundef [[EXPECTED_ADDR:%.+]], i32 noundef 0)236// CHECK: br label %[[CONT:.+]]237// CHECK: [[CONT]]238// CHECK: [[X_RE_ADDR:%.+]] = getelementptr inbounds nuw { i32, i32 }, ptr [[EXPECTED_ADDR]], i32 0, i32 0239// CHECK: [[X_RE:%.+]] = load i32, ptr [[X_RE_ADDR]]240// CHECK: [[X_IM_ADDR:%.+]] = getelementptr inbounds nuw { i32, i32 }, ptr [[EXPECTED_ADDR]], i32 0, i32 1241// CHECK: [[X_IM:%.+]] = load i32, ptr [[X_IM_ADDR]]242// <Skip checks for complex calculations>243// CHECK: [[X_RE_ADDR:%.+]] = getelementptr inbounds nuw { i32, i32 }, ptr [[DESIRED_ADDR:%.+]], i32 0, i32 0244// CHECK: [[X_IM_ADDR:%.+]] = getelementptr inbounds nuw { i32, i32 }, ptr [[DESIRED_ADDR]], i32 0, i32 1245// CHECK: store i32 %{{.+}}, ptr [[X_RE_ADDR]]246// CHECK: store i32 %{{.+}}, ptr [[X_IM_ADDR]]247// CHECK: [[SUCCESS_FAIL:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 noundef 8, ptr noundef [[X_ADDR]], ptr noundef [[EXPECTED_ADDR]], ptr noundef [[DESIRED_ADDR]], i32 noundef 0, i32 noundef 0)248// CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]]249// CHECK: [[EXIT]]250#pragma omp atomic251 cix = civ / cix;252// CHECK: [[EXPR_RE:%.+]] = load float, ptr @{{.+}}253// CHECK: [[EXPR_IM:%.+]] = load float, ptr getelementptr inbounds nuw ({ float, float }, ptr @{{.+}}, i32 0, i32 1)254// CHECK: call void @__atomic_load(i64 noundef 8, ptr noundef [[X_ADDR:@.+]], ptr noundef [[EXPECTED_ADDR:%.+]], i32 noundef 0)255// CHECK: br label %[[CONT:.+]]256// CHECK: [[CONT]]257// CHECK: [[X_RE_ADDR:%.+]] = getelementptr inbounds nuw { float, float }, ptr [[EXPECTED_ADDR]], i32 0, i32 0258// CHECK: [[X_RE:%.+]] = load float, ptr [[X_RE_ADDR]]259// CHECK: [[X_IM_ADDR:%.+]] = getelementptr inbounds nuw { float, float }, ptr [[EXPECTED_ADDR]], i32 0, i32 1260// CHECK: [[X_IM:%.+]] = load float, ptr [[X_IM_ADDR]]261// <Skip checks for complex calculations>262// CHECK: [[X_RE_ADDR:%.+]] = getelementptr inbounds nuw { float, float }, ptr [[DESIRED_ADDR:%.+]], i32 0, i32 0263// CHECK: [[X_IM_ADDR:%.+]] = getelementptr inbounds nuw { float, float }, ptr [[DESIRED_ADDR]], i32 0, i32 1264// CHECK: store float %{{.+}}, ptr [[X_RE_ADDR]]265// CHECK: store float %{{.+}}, ptr [[X_IM_ADDR]]266// CHECK: [[SUCCESS_FAIL:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 noundef 8, ptr noundef [[X_ADDR]], ptr noundef [[EXPECTED_ADDR]], ptr noundef [[DESIRED_ADDR]], i32 noundef 0, i32 noundef 0)267// CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]]268// CHECK: [[EXIT]]269#pragma omp atomic update270 cfx = cfv + cfx;271// CHECK: [[EXPR_RE:%.+]] = load double, ptr @{{.+}}272// CHECK: [[EXPR_IM:%.+]] = load double, ptr getelementptr inbounds nuw ({ double, double }, ptr @{{.+}}, i32 0, i32 1)273// CHECK: call void @__atomic_load(i64 noundef 16, ptr noundef [[X_ADDR:@.+]], ptr noundef [[EXPECTED_ADDR:%.+]], i32 noundef 5)274// CHECK: br label %[[CONT:.+]]275// CHECK: [[CONT]]276// CHECK: [[X_RE_ADDR:%.+]] = getelementptr inbounds nuw { double, double }, ptr [[EXPECTED_ADDR]], i32 0, i32 0277// CHECK: [[X_RE:%.+]] = load double, ptr [[X_RE_ADDR]]278// CHECK: [[X_IM_ADDR:%.+]] = getelementptr inbounds nuw { double, double }, ptr [[EXPECTED_ADDR]], i32 0, i32 1279// CHECK: [[X_IM:%.+]] = load double, ptr [[X_IM_ADDR]]280// <Skip checks for complex calculations>281// CHECK: [[X_RE_ADDR:%.+]] = getelementptr inbounds nuw { double, double }, ptr [[DESIRED_ADDR:%.+]], i32 0, i32 0282// CHECK: [[X_IM_ADDR:%.+]] = getelementptr inbounds nuw { double, double }, ptr [[DESIRED_ADDR]], i32 0, i32 1283// CHECK: store double %{{.+}}, ptr [[X_RE_ADDR]]284// CHECK: store double %{{.+}}, ptr [[X_IM_ADDR]]285// CHECK: [[SUCCESS_FAIL:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 noundef 16, ptr noundef [[X_ADDR]], ptr noundef [[EXPECTED_ADDR]], ptr noundef [[DESIRED_ADDR]], i32 noundef 5, i32 noundef 5)286// CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]]287// CHECK: [[EXIT]]288// CHECK: call{{.*}} @__kmpc_flush(289#pragma omp atomic seq_cst290 cdx = cdx - cdv;291// CHECK: [[BV:%.+]] = load i8, ptr @{{.+}}292// CHECK: [[BOOL:%.+]] = trunc i8 [[BV]] to i1293// CHECK: [[EXPR:%.+]] = zext i1 [[BOOL]] to i64294// CHECK: atomicrmw and ptr @{{.+}}, i64 [[EXPR]] monotonic, align 8295#pragma omp atomic update296 ulx = ulx & bv;297// CHECK: [[CV:%.+]] = load i8, ptr @{{.+}}, align 1298// CHECK: [[EXPR:%.+]] = sext i8 [[CV]] to i32299// CHECK: [[BX:%.+]] = load atomic i8, ptr [[BX_ADDR:@.+]] monotonic, align 1300// CHECK: br label %[[CONT:.+]]301// CHECK: [[CONT]]302// CHECK: [[EXPECTED:%.+]] = phi i8 [ [[BX]], %{{.+}} ], [ [[OLD_X:%.+]], %[[CONT]] ]303// CHECK: [[OLD:%.+]] = trunc i8 [[EXPECTED]] to i1304// CHECK: [[X_RVAL:%.+]] = zext i1 [[OLD]] to i32305// CHECK: [[AND:%.+]] = and i32 [[EXPR]], [[X_RVAL]]306// CHECK: [[CAST:%.+]] = icmp ne i32 [[AND]], 0307// CHECK: [[DESIRED:%.+]] = zext i1 [[CAST]] to i8308// CHECK: store i8 [[DESIRED]], ptr [[TEMP:%.+]],309// CHECK: [[DESIRED:%.+]] = load i8, ptr [[TEMP]],310// CHECK: [[RES:%.+]] = cmpxchg ptr [[BX_ADDR]], i8 [[EXPECTED]], i8 [[DESIRED]] monotonic monotonic, align 1311// CHECK: [[OLD_X:%.+]] = extractvalue { i8, i1 } [[RES]], 0312// CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i8, i1 } [[RES]], 1313// CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]]314// CHECK: [[EXIT]]315#pragma omp atomic316 bx = cv & bx;317// CHECK: [[UCV:%.+]] = load i8, ptr @{{.+}},318// CHECK: [[EXPR:%.+]] = zext i8 [[UCV]] to i32319// CHECK: [[X:%.+]] = load atomic i8, ptr [[CX_ADDR:@.+]] seq_cst, align 1320// CHECK: br label %[[CONT:.+]]321// CHECK: [[CONT]]322// CHECK: [[EXPECTED:%.+]] = phi i8 [ [[X]], %{{.+}} ], [ [[OLD_X:%.+]], %[[CONT]] ]323// CHECK: [[X_RVAL:%.+]] = sext i8 [[EXPECTED]] to i32324// CHECK: [[ASHR:%.+]] = ashr i32 [[X_RVAL]], [[EXPR]]325// CHECK: [[DESIRED:%.+]] = trunc i32 [[ASHR]] to i8326// CHECK: store i8 [[DESIRED]], ptr [[TEMP:%.+]],327// CHECK: [[DESIRED:%.+]] = load i8, ptr [[TEMP]],328// CHECK: [[RES:%.+]] = cmpxchg ptr [[CX_ADDR]], i8 [[EXPECTED]], i8 [[DESIRED]] seq_cst seq_cst, align 1329// CHECK: [[OLD_X:%.+]] = extractvalue { i8, i1 } [[RES]], 0330// CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i8, i1 } [[RES]], 1331// CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]]332// CHECK: [[EXIT]]333// CHECK: call{{.*}} @__kmpc_flush(334#pragma omp atomic update, seq_cst335 cx = cx >> ucv;336// CHECK: [[SV:%.+]] = load i16, ptr @{{.+}},337// CHECK: [[EXPR:%.+]] = sext i16 [[SV]] to i32338// CHECK: [[X:%.+]] = load atomic i64, ptr [[ULX_ADDR:@.+]] monotonic, align 8339// CHECK: br label %[[CONT:.+]]340// CHECK: [[CONT]]341// CHECK: [[EXPECTED:%.+]] = phi i64 [ [[X]], %{{.+}} ], [ [[OLD_X:%.+]], %[[CONT]] ]342// CHECK: [[X_RVAL:%.+]] = trunc i64 [[EXPECTED]] to i32343// CHECK: [[SHL:%.+]] = shl i32 [[EXPR]], [[X_RVAL]]344// CHECK: [[DESIRED:%.+]] = sext i32 [[SHL]] to i64345// CHECK: store i64 [[DESIRED]], ptr [[TEMP:%.+]],346// CHECK: [[DESIRED:%.+]] = load i64, ptr [[TEMP]],347// CHECK: [[RES:%.+]] = cmpxchg ptr [[ULX_ADDR]], i64 [[EXPECTED]], i64 [[DESIRED]] monotonic monotonic, align 8348// CHECK: [[OLD_X:%.+]] = extractvalue { i64, i1 } [[RES]], 0349// CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i64, i1 } [[RES]], 1350// CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]]351// CHECK: [[EXIT]]352#pragma omp atomic update353 ulx = sv << ulx;354// CHECK: [[USV:%.+]] = load i16, ptr @{{.+}},355// CHECK: [[EXPR:%.+]] = zext i16 [[USV]] to i64356// CHECK: [[X:%.+]] = load atomic i64, ptr [[LX_ADDR:@.+]] monotonic, align 8357// CHECK: br label %[[CONT:.+]]358// CHECK: [[CONT]]359// CHECK: [[EXPECTED:%.+]] = phi i64 [ [[X]], %{{.+}} ], [ [[OLD_X:%.+]], %[[CONT]] ]360// CHECK: [[DESIRED:%.+]] = srem i64 [[EXPECTED]], [[EXPR]]361// CHECK: store i64 [[DESIRED]], ptr [[TEMP:%.+]],362// CHECK: [[DESIRED:%.+]] = load i64, ptr [[TEMP]],363// CHECK: [[RES:%.+]] = cmpxchg ptr [[LX_ADDR]], i64 [[EXPECTED]], i64 [[DESIRED]] monotonic monotonic, align 8364// CHECK: [[OLD_X:%.+]] = extractvalue { i64, i1 } [[RES]], 0365// CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i64, i1 } [[RES]], 1366// CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]]367// CHECK: [[EXIT]]368#pragma omp atomic369 lx = lx % usv;370// CHECK: [[EXPR:%.+]] = load i32, ptr @{{.+}}371// CHECK: atomicrmw or ptr @{{.+}}, i32 [[EXPR]] seq_cst, align 4372// CHECK: call{{.*}} @__kmpc_flush(373#pragma omp atomic seq_cst, update374 uix = iv | uix;375// CHECK: [[EXPR:%.+]] = load i32, ptr @{{.+}}376// CHECK: atomicrmw and ptr @{{.+}}, i32 [[EXPR]] monotonic, align 4377#pragma omp atomic378 ix = ix & uiv;379// CHECK: [[EXPR:%.+]] = load i64, ptr @{{.+}},380// CHECK: call void @__atomic_load(i64 noundef 8, ptr noundef [[X_ADDR:@.+]], ptr noundef [[EXPECTED_ADDR:%.+]], i32 noundef 0)381// CHECK: br label %[[CONT:.+]]382// CHECK: [[CONT]]383// CHECK: [[X_RE_ADDR:%.+]] = getelementptr inbounds nuw { i32, i32 }, ptr [[EXPECTED_ADDR]], i32 0, i32 0384// CHECK: [[X_RE:%.+]] = load i32, ptr [[X_RE_ADDR]]385// CHECK: [[X_IM_ADDR:%.+]] = getelementptr inbounds nuw { i32, i32 }, ptr [[EXPECTED_ADDR]], i32 0, i32 1386// CHECK: [[X_IM:%.+]] = load i32, ptr [[X_IM_ADDR]]387// <Skip checks for complex calculations>388// CHECK: [[X_RE_ADDR:%.+]] = getelementptr inbounds nuw { i32, i32 }, ptr [[DESIRED_ADDR:%.+]], i32 0, i32 0389// CHECK: [[X_IM_ADDR:%.+]] = getelementptr inbounds nuw { i32, i32 }, ptr [[DESIRED_ADDR]], i32 0, i32 1390// CHECK: store i32 %{{.+}}, ptr [[X_RE_ADDR]]391// CHECK: store i32 %{{.+}}, ptr [[X_IM_ADDR]]392// CHECK: [[SUCCESS_FAIL:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 noundef 8, ptr noundef [[X_ADDR]], ptr noundef [[EXPECTED_ADDR]], ptr noundef [[DESIRED_ADDR]], i32 noundef 0, i32 noundef 0)393// CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]]394// CHECK: [[EXIT]]395#pragma omp atomic update396 cix = lv + cix;397// CHECK: [[ULV:%.+]] = load i64, ptr @{{.+}},398// CHECK: [[EXPR:%.+]] = uitofp i64 [[ULV]] to float399// CHECK: [[OLD:%.+]] = load atomic i32, ptr [[X_ADDR:@.+]] monotonic, align 4400// CHECK: br label %[[CONT:.+]]401// CHECK: [[CONT]]402// CHECK: [[EXPECTED:%.+]] = phi i32 [ [[OLD]], %{{.+}} ], [ [[PREV:%.+]], %[[CONT]] ]403// CHECK: [[OLD:%.+]] = bitcast i32 [[EXPECTED]] to float404// CHECK: [[MUL:%.+]] = fmul float [[OLD]], [[EXPR]]405// CHECK: store float [[MUL]], ptr [[TEMP:%.+]],406// CHECK: [[DESIRED:%.+]] = load i32, ptr [[TEMP]],407// CHECK: [[RES:%.+]] = cmpxchg ptr [[X_ADDR]], i32 [[EXPECTED]], i32 [[DESIRED]] monotonic monotonic, align 4408// CHECK: [[PREV:%.+]] = extractvalue { i32, i1 } [[RES]], 0409// CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i32, i1 } [[RES]], 1410// CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]]411// CHECK: [[EXIT]]412#pragma omp atomic413 fx = fx * ulv;414// CHECK: [[LLV:%.+]] = load i64, ptr @{{.+}},415// CHECK: [[EXPR:%.+]] = sitofp i64 [[LLV]] to double416// CHECK: [[OLD:%.+]] = load atomic i64, ptr [[X_ADDR:@.+]] monotonic, align 8417// CHECK: br label %[[CONT:.+]]418// CHECK: [[CONT]]419// CHECK: [[EXPECTED:%.+]] = phi i64 [ [[OLD]], %{{.+}} ], [ [[PREV:%.+]], %[[CONT]] ]420// CHECK: [[OLD:%.+]] = bitcast i64 [[EXPECTED]] to double421// CHECK: [[DIV:%.+]] = fdiv double [[OLD]], [[EXPR]]422// CHECK: store double [[DIV]], ptr [[TEMP:%.+]],423// CHECK: [[DESIRED:%.+]] = load i64, ptr [[TEMP]],424// CHECK: [[RES:%.+]] = cmpxchg ptr [[X_ADDR]], i64 [[EXPECTED]], i64 [[DESIRED]] monotonic monotonic, align 8425// CHECK: [[PREV:%.+]] = extractvalue { i64, i1 } [[RES]], 0426// CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i64, i1 } [[RES]], 1427// CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]]428// CHECK: [[EXIT]]429#pragma omp atomic update430 dx /= llv;431// CHECK: [[ULLV:%.+]] = load i64, ptr @{{.+}},432// CHECK: [[EXPR:%.+]] = uitofp i64 [[ULLV]] to x86_fp80433// CHECK: [[OLD:%.+]] = load atomic i128, ptr [[X_ADDR:@.+]] monotonic, align 16434// CHECK: br label %[[CONT:.+]]435// CHECK: [[CONT]]436// CHECK: [[EXPECTED:%.+]] = phi i128 [ [[OLD]], %{{.+}} ], [ [[PREV:%.+]], %[[CONT]] ]437// CHECK: store i128 [[EXPECTED]], ptr [[TEMP1:%.+]]438// CHECK: [[OLD:%.+]] = load x86_fp80, ptr [[TEMP:%.+]]439// CHECK: [[SUB:%.+]] = fsub x86_fp80 [[OLD]], [[EXPR]]440// CHECK: store x86_fp80 [[SUB]], ptr [[TEMP1]]441// CHECK: [[DESIRED:%.+]] = load i128, ptr [[TEMP1]]442// CHECK: [[RES:%.+]] = cmpxchg ptr [[X_ADDR]], i128 [[EXPECTED]], i128 [[DESIRED]] monotonic monotonic, align 16443// CHECK: [[PREV:%.+]] = extractvalue { i128, i1 } [[RES]], 0444// CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i128, i1 } [[RES]], 1445// CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]]446// CHECK: [[EXIT]]447#pragma omp atomic448 ldx -= ullv;449// CHECK: [[EXPR:%.+]] = load float, ptr @{{.+}},450// CHECK: call void @__atomic_load(i64 noundef 8, ptr noundef [[X_ADDR:@.+]], ptr noundef [[EXPECTED_ADDR:%.+]], i32 noundef 0)451// CHECK: br label %[[CONT:.+]]452// CHECK: [[CONT]]453// CHECK: [[X_RE_ADDR:%.+]] = getelementptr inbounds nuw { i32, i32 }, ptr [[EXPECTED_ADDR]], i32 0, i32 0454// CHECK: [[X_RE:%.+]] = load i32, ptr [[X_RE_ADDR]]455// CHECK: [[X_IM_ADDR:%.+]] = getelementptr inbounds nuw { i32, i32 }, ptr [[EXPECTED_ADDR]], i32 0, i32 1456// CHECK: [[X_IM:%.+]] = load i32, ptr [[X_IM_ADDR]]457// <Skip checks for complex calculations>458// CHECK: [[X_RE_ADDR:%.+]] = getelementptr inbounds nuw { i32, i32 }, ptr [[DESIRED_ADDR:%.+]], i32 0, i32 0459// CHECK: [[X_IM_ADDR:%.+]] = getelementptr inbounds nuw { i32, i32 }, ptr [[DESIRED_ADDR]], i32 0, i32 1460// CHECK: store i32 %{{.+}}, ptr [[X_RE_ADDR]]461// CHECK: store i32 %{{.+}}, ptr [[X_IM_ADDR]]462// CHECK: [[SUCCESS_FAIL:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 noundef 8, ptr noundef [[X_ADDR]], ptr noundef [[EXPECTED_ADDR]], ptr noundef [[DESIRED_ADDR]], i32 noundef 0, i32 noundef 0)463// CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]]464// CHECK: [[EXIT]]465#pragma omp atomic update466 cix = fv / cix;467// CHECK: [[EXPR:%.+]] = load double, ptr @{{.+}},468// CHECK: [[X:%.+]] = load atomic i16, ptr [[X_ADDR:@.+]] monotonic, align 2469// CHECK: br label %[[CONT:.+]]470// CHECK: [[CONT]]471// CHECK: [[EXPECTED:%.+]] = phi i16 [ [[X]], %{{.+}} ], [ [[OLD_X:%.+]], %[[CONT]] ]472// CHECK: [[CONV:%.+]] = sext i16 [[EXPECTED]] to i32473// CHECK: [[X_RVAL:%.+]] = sitofp i32 [[CONV]] to double474// CHECK: [[ADD:%.+]] = fadd double [[X_RVAL]], [[EXPR]]475// CHECK: [[DESIRED:%.+]] = fptosi double [[ADD]] to i16476// CHECK: store i16 [[DESIRED]], ptr [[TEMP:%.+]]477// CHECK: [[DESIRED:%.+]] = load i16, ptr [[TEMP]]478// CHECK: [[RES:%.+]] = cmpxchg ptr [[X_ADDR]], i16 [[EXPECTED]], i16 [[DESIRED]] monotonic monotonic, align 2479// CHECK: [[OLD_X]] = extractvalue { i16, i1 } [[RES]], 0480// CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i16, i1 } [[RES]], 1481// CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]]482// CHECK: [[EXIT]]483#pragma omp atomic484 sx = sx + dv;485// CHECK: [[EXPR:%.+]] = load x86_fp80, ptr @{{.+}},486// CHECK: [[XI8:%.+]] = load atomic i8, ptr [[X_ADDR:@.+]] monotonic, align 1487// CHECK: br label %[[CONT:.+]]488// CHECK: [[CONT]]489// CHECK: [[EXPECTED:%.+]] = phi i8 [ [[XI8]], %{{.+}} ], [ [[OLD_XI8:%.+]], %[[CONT]] ]490// CHECK: [[BOOL_EXPECTED:%.+]] = trunc i8 [[EXPECTED]] to i1491// CHECK: [[CONV:%.+]] = zext i1 [[BOOL_EXPECTED]] to i32492// CHECK: [[X_RVAL:%.+]] = sitofp i32 [[CONV]] to x86_fp80493// CHECK: [[MUL:%.+]] = fmul x86_fp80 [[EXPR]], [[X_RVAL]]494// CHECK: [[BOOL_DESIRED:%.+]] = fcmp une x86_fp80 [[MUL]], 0xK00000000000000000000495// CHECK: [[DESIRED:%.+]] = zext i1 [[BOOL_DESIRED]] to i8496// CHECK: store i8 [[DESIRED]], ptr [[TEMP:%.+]]497// CHECK: [[DESIRED:%.+]] = load i8, ptr [[TEMP]]498// CHECK: [[RES:%.+]] = cmpxchg ptr [[X_ADDR]], i8 [[EXPECTED]], i8 [[DESIRED]] release monotonic, align 1499// CHECK: [[OLD_XI8:%.+]] = extractvalue { i8, i1 } [[RES]], 0500// CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i8, i1 } [[RES]], 1501// CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]]502// CHECK: [[EXIT]]503// CHECK: call{{.*}} @__kmpc_flush(504#pragma omp atomic update release505 bx = ldv * bx;506// CHECK: [[EXPR_RE:%.+]] = load i32, ptr [[CIV_ADDR:@.+]],507// CHECK: [[EXPR_IM:%.+]] = load i32, ptr getelementptr inbounds nuw ({ i32, i32 }, ptr [[CIV_ADDR]], i32 0, i32 1),508// CHECK: [[XI8:%.+]] = load atomic i8, ptr [[X_ADDR:@.+]] monotonic, align 1509// CHECK: br label %[[CONT:.+]]510// CHECK: [[CONT]]511// CHECK: [[EXPECTED:%.+]] = phi i8 [ [[XI8]], %{{.+}} ], [ [[OLD_XI8:%.+]], %[[CONT]] ]512// CHECK: [[BOOL_EXPECTED:%.+]] = trunc i8 [[EXPECTED]] to i1513// CHECK: [[X_RVAL:%.+]] = zext i1 [[BOOL_EXPECTED]] to i32514// CHECK: [[SUB_RE:%.+]] = sub i32 [[EXPR_RE:%.+]], [[X_RVAL]]515// CHECK: [[SUB_IM:%.+]] = sub i32 [[EXPR_IM:%.+]], 0516// CHECK: icmp ne i32 [[SUB_RE]], 0517// CHECK: icmp ne i32 [[SUB_IM]], 0518// CHECK: [[BOOL_DESIRED:%.+]] = or i1519// CHECK: [[DESIRED:%.+]] = zext i1 [[BOOL_DESIRED]] to i8520// CHECK: store i8 [[DESIRED]], ptr [[TEMP:%.+]]521// CHECK: [[DESIRED:%.+]] = load i8, ptr [[TEMP]]522// CHECK: [[RES:%.+]] = cmpxchg ptr [[X_ADDR]], i8 [[EXPECTED]], i8 [[DESIRED]] monotonic monotonic, align 1523// CHECK: [[OLD_XI8:%.+]] = extractvalue { i8, i1 } [[RES]], 0524// CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i8, i1 } [[RES]], 1525// CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]]526// CHECK: [[EXIT]]527#pragma omp atomic528 bx = civ - bx;529// CHECK: [[IDX:%.+]] = load i16, ptr @{{.+}}530// CHECK: load i8, ptr531// CHECK: [[VEC_ITEM_VAL:%.+]] = zext i1 %{{.+}} to i32532// CHECK: [[I128VAL:%.+]] = load atomic i128, ptr [[DEST:@.+]] monotonic, align 16533// CHECK: br label %[[CONT:.+]]534// CHECK: [[CONT]]535// CHECK: [[OLD_I128:%.+]] = phi i128 [ [[I128VAL]], %{{.+}} ], [ [[FAILED_I128_OLD_VAL:%.+]], %[[CONT]] ]536// CHECK: store i128 [[OLD_I128]], ptr [[TEMP:%.+]],537// CHECK: [[OLD_VEC_VAL:%.+]] = bitcast i128 [[OLD_I128]] to <4 x i32>538// CHECK: store <4 x i32> [[OLD_VEC_VAL]], ptr [[LDTEMP:%.+]],539// CHECK: [[VEC_VAL:%.+]] = load <4 x i32>, ptr [[LDTEMP]]540// CHECK: [[ITEM:%.+]] = extractelement <4 x i32> [[VEC_VAL]], i16 [[IDX]]541// CHECK: [[OR:%.+]] = or i32 [[ITEM]], [[VEC_ITEM_VAL]]542// CHECK: [[VEC_VAL:%.+]] = load <4 x i32>, ptr [[TEMP]]543// CHECK: [[NEW_VEC_VAL:%.+]] = insertelement <4 x i32> [[VEC_VAL]], i32 [[OR]], i16 [[IDX]]544// CHECK: store <4 x i32> [[NEW_VEC_VAL]], ptr [[TEMP]]545// CHECK: [[NEW_I128:%.+]] = load i128, ptr [[TEMP]]546// CHECK: [[RES:%.+]] = cmpxchg ptr [[DEST]], i128 [[OLD_I128]], i128 [[NEW_I128]] monotonic monotonic, align 16547// CHECK: [[FAILED_I128_OLD_VAL:%.+]] = extractvalue { i128, i1 } [[RES]], 0548// CHECK: [[FAIL_SUCCESS:%.+]] = extractvalue { i128, i1 } [[RES]], 1549// CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]]550// CHECK: [[EXIT]]551#pragma omp atomic update552 int4x[sv] |= bv;553// CHECK: [[EXPR:%.+]] = load x86_fp80, ptr @{{.+}}554// CHECK: [[PREV_VALUE:%.+]] = load atomic i32, ptr getelementptr (i8, ptr @{{.+}}, i64 4) monotonic, align 4555// CHECK: br label %[[CONT:.+]]556// CHECK: [[CONT]]557// CHECK: [[OLD_BF_VALUE:%.+]] = phi i32 [ [[PREV_VALUE]], %[[EXIT]] ], [ [[FAILED_OLD_VAL:%.+]], %[[CONT]] ]558// CHECK: store i32 [[OLD_BF_VALUE]], ptr [[TEMP1:%.+]],559// CHECK: store i32 [[OLD_BF_VALUE]], ptr [[TEMP:%.+]],560// CHECK: [[A_LD:%.+]] = load i32, ptr [[TEMP]],561// CHECK: [[A_SHL:%.+]] = shl i32 [[A_LD]], 1562// CHECK: [[A_ASHR:%.+]] = ashr i32 [[A_SHL]], 1563// CHECK: [[X_RVAL:%.+]] = sitofp i32 [[A_ASHR]] to x86_fp80564// CHECK: [[SUB:%.+]] = fsub x86_fp80 [[X_RVAL]], [[EXPR]]565// CHECK: [[CONV:%.+]] = fptosi x86_fp80 [[SUB]] to i32566// CHECK: [[NEW_VAL:%.+]] = load i32, ptr [[TEMP1]],567// CHECK: [[BF_VALUE:%.+]] = and i32 [[CONV]], 2147483647568// CHECK: [[BF_CLEAR:%.+]] = and i32 [[NEW_VAL]], -2147483648569// CHECK: or i32 [[BF_CLEAR]], [[BF_VALUE]]570// CHECK: store i32 %{{.+}}, ptr [[TEMP1]]571// CHECK: [[NEW_BF_VALUE:%.+]] = load i32, ptr [[TEMP1]]572// CHECK: [[RES:%.+]] = cmpxchg ptr getelementptr (i8, ptr @{{.+}}, i64 4), i32 [[OLD_BF_VALUE]], i32 [[NEW_BF_VALUE]] monotonic monotonic, align 4573// CHECK: [[FAILED_OLD_VAL]] = extractvalue { i32, i1 } [[RES]], 0574// CHECK: [[FAIL_SUCCESS:%.+]] = extractvalue { i32, i1 } [[RES]], 1575// CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]]576// CHECK: [[EXIT]]577#pragma omp atomic578 bfx.a = bfx.a - ldv;579// CHECK: [[EXPR:%.+]] = load x86_fp80, ptr @{{.+}}580// CHECK: call void @__atomic_load(i64 noundef 4, ptr noundef getelementptr (i8, ptr @{{.+}}, i64 4), ptr noundef [[LDTEMP:%.+]], i32 noundef 0)581// CHECK: br label %[[CONT:.+]]582// CHECK: [[CONT]]583// CHECK: [[PREV_VALUE:%.+]] = load i32, ptr [[LDTEMP]]584// CHECK: store i32 [[PREV_VALUE]], ptr [[TEMP1:%.+]],585// CHECK: [[PREV_VALUE:%.+]] = load i32, ptr [[LDTEMP]]586// CHECK: store i32 [[PREV_VALUE]], ptr [[TEMP:%.+]],587// CHECK: [[A_LD:%.+]] = load i32, ptr [[TEMP]],588// CHECK: [[A_SHL:%.+]] = shl i32 [[A_LD]], 1589// CHECK: [[A_ASHR:%.+]] = ashr i32 [[A_SHL]], 1590// CHECK: [[X_RVAL:%.+]] = sitofp i32 [[A_ASHR]] to x86_fp80591// CHECK: [[MUL:%.+]] = fmul x86_fp80 [[X_RVAL]], [[EXPR]]592// CHECK: [[CONV:%.+]] = fptosi x86_fp80 [[MUL]] to i32593// CHECK: [[NEW_VAL:%.+]] = load i32, ptr [[TEMP1]],594// CHECK: [[BF_VALUE:%.+]] = and i32 [[CONV]], 2147483647595// CHECK: [[BF_CLEAR:%.+]] = and i32 [[NEW_VAL]], -2147483648596// CHECK: or i32 [[BF_CLEAR]], [[BF_VALUE]]597// CHECK: store i32 %{{.+}}, ptr [[TEMP1]]598// CHECK: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 noundef 4, ptr noundef getelementptr (i8, ptr @{{.+}}, i64 4), ptr noundef [[LDTEMP]], ptr noundef [[TEMP1]], i32 noundef 0, i32 noundef 0)599// CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]]600// CHECK: [[EXIT]]601#pragma omp atomic update602 bfx_packed.a *= ldv;603// CHECK: [[EXPR:%.+]] = load x86_fp80, ptr @{{.+}}604// CHECK: [[PREV_VALUE:%.+]] = load atomic i32, ptr @{{.+}} monotonic, align 4605// CHECK: br label %[[CONT:.+]]606// CHECK: [[CONT]]607// CHECK: [[OLD_BF_VALUE:%.+]] = phi i32 [ [[PREV_VALUE]], %[[EXIT]] ], [ [[FAILED_OLD_VAL:%.+]], %[[CONT]] ]608// CHECK: store i32 [[OLD_BF_VALUE]], ptr [[TEMP1:%.+]],609// CHECK: store i32 [[OLD_BF_VALUE]], ptr [[TEMP:%.+]],610// CHECK: [[A_LD:%.+]] = load i32, ptr [[TEMP]],611// CHECK: [[A_ASHR:%.+]] = ashr i32 [[A_LD]], 31612// CHECK: [[X_RVAL:%.+]] = sitofp i32 [[A_ASHR]] to x86_fp80613// CHECK: [[SUB:%.+]] = fsub x86_fp80 [[X_RVAL]], [[EXPR]]614// CHECK: [[CONV:%.+]] = fptosi x86_fp80 [[SUB]] to i32615// CHECK: [[NEW_VAL:%.+]] = load i32, ptr [[TEMP1]],616// CHECK: [[BF_AND:%.+]] = and i32 [[CONV]], 1617// CHECK: [[BF_VALUE:%.+]] = shl i32 [[BF_AND]], 31618// CHECK: [[BF_CLEAR:%.+]] = and i32 [[NEW_VAL]], 2147483647619// CHECK: or i32 [[BF_CLEAR]], [[BF_VALUE]]620// CHECK: store i32 %{{.+}}, ptr [[TEMP1]]621// CHECK: [[NEW_BF_VALUE:%.+]] = load i32, ptr [[TEMP1]]622// CHECK: [[RES:%.+]] = cmpxchg ptr @{{.+}}, i32 [[OLD_BF_VALUE]], i32 [[NEW_BF_VALUE]] monotonic monotonic, align 4623// CHECK: [[FAILED_OLD_VAL]] = extractvalue { i32, i1 } [[RES]], 0624// CHECK: [[FAIL_SUCCESS:%.+]] = extractvalue { i32, i1 } [[RES]], 1625// CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]]626// CHECK: [[EXIT]]627#pragma omp atomic628 bfx2.a -= ldv;629// CHECK: [[EXPR:%.+]] = load x86_fp80, ptr @{{.+}}630// CHECK: [[PREV_VALUE:%.+]] = load atomic i8, ptr getelementptr (i8, ptr @{{.+}}, i64 3) monotonic, align 1631// CHECK: br label %[[CONT:.+]]632// CHECK: [[CONT]]633// CHECK: [[OLD_BF_VALUE:%.+]] = phi i8 [ [[PREV_VALUE]], %[[EXIT]] ], [ [[FAILED_OLD_VAL:%.+]], %[[CONT]] ]634// CHECK: store i8 [[OLD_BF_VALUE]], ptr [[BITCAST1:%.+]],635// CHECK: store i8 [[OLD_BF_VALUE]], ptr [[BITCAST:%.+]],636// CHECK: [[A_LD:%.+]] = load i8, ptr [[BITCAST]],637// CHECK: [[A_ASHR:%.+]] = ashr i8 [[A_LD]], 7638// CHECK: [[CAST:%.+]] = sext i8 [[A_ASHR]] to i32639// CHECK: [[X_RVAL:%.+]] = sitofp i32 [[CAST]] to x86_fp80640// CHECK: [[DIV:%.+]] = fdiv x86_fp80 [[EXPR]], [[X_RVAL]]641// CHECK: [[NEW_VAL:%.+]] = fptosi x86_fp80 [[DIV]] to i32642// CHECK: [[TRUNC:%.+]] = trunc i32 [[NEW_VAL]] to i8643// CHECK: [[BF_LD:%.+]] = load i8, ptr [[BITCAST1]],644// CHECK: [[BF_AND:%.+]] = and i8 [[TRUNC]], 1645// CHECK: [[BF_VALUE:%.+]] = shl i8 [[BF_AND]], 7646// CHECK: [[BF_CLEAR:%.+]] = and i8 %{{.+}}, 127647// CHECK: or i8 [[BF_CLEAR]], [[BF_VALUE]]648// CHECK: store i8 %{{.+}}, ptr [[BITCAST1]]649// CHECK: [[NEW_BF_VALUE:%.+]] = load i8, ptr [[BITCAST1]]650// CHECK: [[RES:%.+]] = cmpxchg ptr getelementptr (i8, ptr @{{.+}}, i64 3), i8 [[OLD_BF_VALUE]], i8 [[NEW_BF_VALUE]] monotonic monotonic, align 1651// CHECK: [[FAILED_OLD_VAL]] = extractvalue { i8, i1 } [[RES]], 0652// CHECK: [[FAIL_SUCCESS:%.+]] = extractvalue { i8, i1 } [[RES]], 1653// CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]]654// CHECK: [[EXIT]]655#pragma omp atomic update656 bfx2_packed.a = ldv / bfx2_packed.a;657// CHECK: [[EXPR:%.+]] = load x86_fp80, ptr @{{.+}}658// CHECK: [[PREV_VALUE:%.+]] = load atomic i32, ptr @{{.+}} monotonic, align 4659// CHECK: br label %[[CONT:.+]]660// CHECK: [[CONT]]661// CHECK: [[OLD_BF_VALUE:%.+]] = phi i32 [ [[PREV_VALUE]], %[[EXIT]] ], [ [[FAILED_OLD_VAL:%.+]], %[[CONT]] ]662// CHECK: store i32 [[OLD_BF_VALUE]], ptr [[TEMP1:%.+]],663// CHECK: store i32 [[OLD_BF_VALUE]], ptr [[TEMP:%.+]],664// CHECK: [[A_LD:%.+]] = load i32, ptr [[TEMP]],665// CHECK: [[A_SHL:%.+]] = shl i32 [[A_LD]], 7666// CHECK: [[A_ASHR:%.+]] = ashr i32 [[A_SHL]], 18667// CHECK: [[X_RVAL:%.+]] = sitofp i32 [[A_ASHR]] to x86_fp80668// CHECK: [[DIV:%.+]] = fdiv x86_fp80 [[X_RVAL]], [[EXPR]]669// CHECK: [[NEW_VAL:%.+]] = fptosi x86_fp80 [[DIV]] to i32670// CHECK: [[BF_LD:%.+]] = load i32, ptr [[TEMP1]],671// CHECK: [[BF_AND:%.+]] = and i32 [[NEW_VAL]], 16383672// CHECK: [[BF_VALUE:%.+]] = shl i32 [[BF_AND]], 11673// CHECK: [[BF_CLEAR:%.+]] = and i32 %{{.+}}, -33552385674// CHECK: or i32 [[BF_CLEAR]], [[BF_VALUE]]675// CHECK: store i32 %{{.+}}, ptr [[TEMP1]]676// CHECK: [[NEW_BF_VALUE:%.+]] = load i32, ptr [[TEMP1]]677// CHECK: [[RES:%.+]] = cmpxchg ptr @{{.+}}, i32 [[OLD_BF_VALUE]], i32 [[NEW_BF_VALUE]] monotonic monotonic, align 4678// CHECK: [[FAILED_OLD_VAL]] = extractvalue { i32, i1 } [[RES]], 0679// CHECK: [[FAIL_SUCCESS:%.+]] = extractvalue { i32, i1 } [[RES]], 1680// CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]]681// CHECK: [[EXIT]]682#pragma omp atomic683 bfx3.a /= ldv;684// CHECK: [[EXPR:%.+]] = load x86_fp80, ptr @{{.+}}685// CHECK: call void @__atomic_load(i64 noundef 3, ptr noundef getelementptr (i8, ptr @{{.+}}, i64 1), ptr noundef [[BITCAST:%.+]], i32 noundef 0)686// CHECK: br label %[[CONT:.+]]687// CHECK: [[CONT]]688// CHECK: [[PREV_VALUE:%.+]] = load i24, ptr [[LDTEMP:%.+]],689// CHECK: store i24 [[PREV_VALUE]], ptr [[TEMP1:%.+]],690// CHECK: [[PREV_VALUE:%.+]] = load i24, ptr [[LDTEMP]]691// CHECK: store i24 [[PREV_VALUE]], ptr [[TEMP:%.+]],692// CHECK: [[A_LD:%.+]] = load i24, ptr [[TEMP]],693// CHECK: [[A_SHL:%.+]] = shl i24 [[A_LD]], 7694// CHECK: [[A_ASHR:%.+]] = ashr i24 [[A_SHL]], 10695// CHECK: [[CAST:%.+]] = sext i24 [[A_ASHR]] to i32696// CHECK: [[X_RVAL:%.+]] = sitofp i32 [[CAST]] to x86_fp80697// CHECK: [[ADD:%.+]] = fadd x86_fp80 [[X_RVAL]], [[EXPR]]698// CHECK: [[NEW_VAL:%.+]] = fptosi x86_fp80 [[ADD]] to i32699// CHECK: [[TRUNC:%.+]] = trunc i32 [[NEW_VAL]] to i24700// CHECK: [[BF_LD:%.+]] = load i24, ptr [[TEMP1]],701// CHECK: [[BF_AND:%.+]] = and i24 [[TRUNC]], 16383702// CHECK: [[BF_VALUE:%.+]] = shl i24 [[BF_AND]], 3703// CHECK: [[BF_CLEAR:%.+]] = and i24 [[BF_LD]], -131065704// CHECK: or i24 [[BF_CLEAR]], [[BF_VALUE]]705// CHECK: store i24 %{{.+}}, ptr [[TEMP1]]706// CHECK: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 noundef 3, ptr noundef getelementptr (i8, ptr @{{.+}}, i64 1), ptr noundef [[LDTEMP]], ptr noundef [[TEMP1]], i32 noundef 0, i32 noundef 0)707// CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]]708// CHECK: [[EXIT]]709#pragma omp atomic update710 bfx3_packed.a += ldv;711// CHECK: [[EXPR:%.+]] = load x86_fp80, ptr @{{.+}}712// CHECK: [[PREV_VALUE:%.+]] = load atomic i64, ptr @{{.+}} monotonic, align 8713// CHECK: br label %[[CONT:.+]]714// CHECK: [[CONT]]715// CHECK: [[OLD_BF_VALUE:%.+]] = phi i64 [ [[PREV_VALUE]], %[[EXIT]] ], [ [[FAILED_OLD_VAL:%.+]], %[[CONT]] ]716// CHECK: store i64 [[OLD_BF_VALUE]], ptr [[TEMP1:%.+]],717// CHECK: store i64 [[OLD_BF_VALUE]], ptr [[TEMP:%.+]],718// CHECK: [[A_LD:%.+]] = load i64, ptr [[TEMP]],719// CHECK: [[A_SHL:%.+]] = shl i64 [[A_LD]], 47720// CHECK: [[A_ASHR:%.+]] = ashr i64 [[A_SHL:%.+]], 63721// CHECK: [[A_CAST:%.+]] = trunc i64 [[A_ASHR:%.+]] to i32722// CHECK: [[X_RVAL:%.+]] = sitofp i32 [[CAST:%.+]] to x86_fp80723// CHECK: [[MUL:%.+]] = fmul x86_fp80 [[X_RVAL]], [[EXPR]]724// CHECK: [[NEW_VAL:%.+]] = fptosi x86_fp80 [[MUL]] to i32725// CHECK: [[ZEXT:%.+]] = zext i32 [[NEW_VAL]] to i64726// CHECK: [[BF_LD:%.+]] = load i64, ptr [[TEMP1]],727// CHECK: [[BF_AND:%.+]] = and i64 [[ZEXT]], 1728// CHECK: [[BF_VALUE:%.+]] = shl i64 [[BF_AND]], 16729// CHECK: [[BF_CLEAR:%.+]] = and i64 [[BF_LD]], -65537730// CHECK: or i64 [[BF_CLEAR]], [[BF_VALUE]]731// CHECK: store i64 %{{.+}}, ptr [[TEMP1]]732// CHECK: [[NEW_BF_VALUE:%.+]] = load i64, ptr [[TEMP1]]733// CHECK: [[RES:%.+]] = cmpxchg ptr @{{.+}}, i64 [[OLD_BF_VALUE]], i64 [[NEW_BF_VALUE]] monotonic monotonic, align 8734// CHECK: [[FAILED_OLD_VAL]] = extractvalue { i64, i1 } [[RES]], 0735// CHECK: [[FAIL_SUCCESS:%.+]] = extractvalue { i64, i1 } [[RES]], 1736// CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]]737// CHECK: [[EXIT]]738#pragma omp atomic739 bfx4.a = bfx4.a * ldv;740// CHECK: [[EXPR:%.+]] = load x86_fp80, ptr @{{.+}}741// CHECK: [[PREV_VALUE:%.+]] = load atomic i8, ptr getelementptr inbounds nuw (%struct.BitFields4_packed, ptr @{{.+}}, i32 0, i32 1) monotonic, align 1742// CHECK: br label %[[CONT:.+]]743// CHECK: [[CONT]]744// CHECK: [[OLD_BF_VALUE:%.+]] = phi i8 [ [[PREV_VALUE]], %{{.+}} ], [ [[FAILED_OLD_VAL:%.+]], %[[CONT]] ]745// CHECK: store i8 [[OLD_BF_VALUE]], ptr [[BITCAST1:%.+]],746// CHECK: store i8 [[OLD_BF_VALUE]], ptr [[BITCAST:%.+]],747// CHECK: [[A_LD:%.+]] = load i8, ptr [[BITCAST]],748// CHECK: [[A_SHL:%.+]] = shl i8 [[A_LD]], 7749// CHECK: [[A_ASHR:%.+]] = ashr i8 [[A_SHL:%.+]], 7750// CHECK: [[CAST:%.+]] = sext i8 [[A_ASHR:%.+]] to i32751// CHECK: [[CONV:%.+]] = sitofp i32 [[CAST]] to x86_fp80752// CHECK: [[SUB: %.+]] = fsub x86_fp80 [[CONV]], [[EXPR]]753// CHECK: [[CONV:%.+]] = fptosi x86_fp80 [[SUB:%.+]] to i32754// CHECK: [[NEW_VAL:%.+]] = trunc i32 [[CONV]] to i8755// CHECK: [[BF_LD:%.+]] = load i8, ptr [[BITCAST1]],756// CHECK: [[BF_VALUE:%.+]] = and i8 [[NEW_VAL]], 1757// CHECK: [[BF_CLEAR:%.+]] = and i8 [[BF_LD]], -2758// CHECK: or i8 [[BF_CLEAR]], [[BF_VALUE]]759// CHECK: store i8 %{{.+}}, ptr [[BITCAST1]]760// CHECK: [[NEW_BF_VALUE:%.+]] = load i8, ptr [[BITCAST1]]761// CHECK: [[RES:%.+]] = cmpxchg ptr getelementptr inbounds nuw (%struct.BitFields4_packed, ptr @{{.+}}, i32 0, i32 1), i8 [[OLD_BF_VALUE]], i8 [[NEW_BF_VALUE]] monotonic monotonic, align 1762// CHECK: [[FAILED_OLD_VAL]] = extractvalue { i8, i1 } [[RES]], 0763// CHECK: [[FAIL_SUCCESS:%.+]] = extractvalue { i8, i1 } [[RES]], 1764// CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]]765// CHECK: [[EXIT]]766#pragma omp atomic relaxed update767 bfx4_packed.a -= ldv;768// CHECK: [[EXPR:%.+]] = load x86_fp80, ptr @{{.+}}769// CHECK: [[PREV_VALUE:%.+]] = load atomic i64, ptr @{{.+}} monotonic, align 8770// CHECK: br label %[[CONT:.+]]771// CHECK: [[CONT]]772// CHECK: [[OLD_BF_VALUE:%.+]] = phi i64 [ [[PREV_VALUE]], %[[EXIT]] ], [ [[FAILED_OLD_VAL:%.+]], %[[CONT]] ]773// CHECK: store i64 [[OLD_BF_VALUE]], ptr [[TEMP1:%.+]],774// CHECK: store i64 [[OLD_BF_VALUE]], ptr [[TEMP:%.+]],775// CHECK: [[A_LD:%.+]] = load i64, ptr [[TEMP]],776// CHECK: [[A_SHL:%.+]] = shl i64 [[A_LD]], 40777// CHECK: [[A_ASHR:%.+]] = ashr i64 [[A_SHL:%.+]], 57778// CHECK: [[CONV:%.+]] = sitofp i64 [[A_ASHR]] to x86_fp80779// CHECK: [[DIV:%.+]] = fdiv x86_fp80 [[CONV]], [[EXPR]]780// CHECK: [[CONV:%.+]] = fptosi x86_fp80 [[DIV]] to i64781// CHECK: [[BF_LD:%.+]] = load i64, ptr [[TEMP1]],782// CHECK: [[BF_AND:%.+]] = and i64 [[CONV]], 127783// CHECK: [[BF_VALUE:%.+]] = shl i64 [[BF_AND:%.+]], 17784// CHECK: [[BF_CLEAR:%.+]] = and i64 [[BF_LD]], -16646145785// CHECK: [[VAL:%.+]] = or i64 [[BF_CLEAR]], [[BF_VALUE]]786// CHECK: store i64 [[VAL]], ptr [[TEMP1]]787// CHECK: [[NEW_BF_VALUE:%.+]] = load i64, ptr [[TEMP1]]788// CHECK: [[RES:%.+]] = cmpxchg ptr @{{.+}}, i64 [[OLD_BF_VALUE]], i64 [[NEW_BF_VALUE]] monotonic monotonic, align 8789// CHECK: [[FAILED_OLD_VAL]] = extractvalue { i64, i1 } [[RES]], 0790// CHECK: [[FAIL_SUCCESS:%.+]] = extractvalue { i64, i1 } [[RES]], 1791// CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]]792// CHECK: [[EXIT]]793#pragma omp atomic794 bfx4.b /= ldv;795// CHECK: [[EXPR:%.+]] = load x86_fp80, ptr @{{.+}}796// CHECK: [[PREV_VALUE:%.+]] = load atomic i8, ptr getelementptr inbounds nuw (%struct.BitFields4_packed, ptr @{{.+}}, i32 0, i32 1) monotonic, align 1797// CHECK: br label %[[CONT:.+]]798// CHECK: [[CONT]]799// CHECK: [[OLD_BF_VALUE:%.+]] = phi i8 [ [[PREV_VALUE]], %[[EXIT]] ], [ [[FAILED_OLD_VAL:%.+]], %[[CONT]] ]800// CHECK: store i8 [[OLD_BF_VALUE]], ptr [[BITCAST1:%.+]],801// CHECK: store i8 [[OLD_BF_VALUE]], ptr [[BITCAST:%.+]],802// CHECK: [[A_LD:%.+]] = load i8, ptr [[BITCAST]],803// CHECK: [[A_ASHR:%.+]] = ashr i8 [[A_LD]], 1804// CHECK: [[CAST:%.+]] = sext i8 [[A_ASHR]] to i64805// CHECK: [[CONV:%.+]] = sitofp i64 [[CAST]] to x86_fp80806// CHECK: [[ADD:%.+]] = fadd x86_fp80 [[CONV]], [[EXPR]]807// CHECK: [[NEW_VAL:%.+]] = fptosi x86_fp80 [[ADD]] to i64808// CHECK: [[TRUNC:%.+]] = trunc i64 [[NEW_VAL]] to i8809// CHECK: [[BF_LD:%.+]] = load i8, ptr [[BITCAST1]],810// CHECK: [[BF_AND:%.+]] = and i8 [[TRUNC]], 127811// CHECK: [[BF_VALUE:%.+]] = shl i8 [[BF_AND]], 1812// CHECK: [[BF_CLEAR:%.+]] = and i8 [[BF_LD]], 1813// CHECK: or i8 [[BF_CLEAR]], [[BF_VALUE]]814// CHECK: store i8 %{{.+}}, ptr [[BITCAST1]]815// CHECK: [[NEW_BF_VALUE:%.+]] = load i8, ptr [[BITCAST1]]816// CHECK: [[RES:%.+]] = cmpxchg ptr getelementptr inbounds nuw (%struct.BitFields4_packed, ptr @{{.+}}, i32 0, i32 1), i8 [[OLD_BF_VALUE]], i8 [[NEW_BF_VALUE]] monotonic monotonic, align 1817// CHECK: [[FAILED_OLD_VAL]] = extractvalue { i8, i1 } [[RES]], 0818// CHECK: [[FAIL_SUCCESS:%.+]] = extractvalue { i8, i1 } [[RES]], 1819// CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]]820// CHECK: [[EXIT]]821#pragma omp atomic update relaxed822 bfx4_packed.b += ldv;823// CHECK: load i64, ptr824// CHECK: [[EXPR:%.+]] = uitofp i64 %{{.+}} to float825// CHECK: [[I64VAL:%.+]] = load atomic i64, ptr [[DEST:@.+]] monotonic, align 8826// CHECK: br label %[[CONT:.+]]827// CHECK: [[CONT]]828// CHECK: [[OLD_I64:%.+]] = phi i64 [ [[I64VAL]], %{{.+}} ], [ [[FAILED_I64_OLD_VAL:%.+]], %[[CONT]] ]829// CHECK: store i64 [[OLD_I64]], ptr [[TEMP:%.+]],830// CHECK: [[OLD_VEC_VAL:%.+]] = bitcast i64 [[OLD_I64]] to <2 x float>831// CHECK: store <2 x float> [[OLD_VEC_VAL]], ptr [[LDTEMP:%.+]],832// CHECK: [[VEC_VAL:%.+]] = load <2 x float>, ptr [[LDTEMP]]833// CHECK: [[X:%.+]] = extractelement <2 x float> [[VEC_VAL]], i64 0834// CHECK: [[VEC_ITEM_VAL:%.+]] = fsub float [[EXPR]], [[X]]835// CHECK: [[VEC_VAL:%.+]] = load <2 x float>, ptr [[TEMP]],836// CHECK: [[NEW_VEC_VAL:%.+]] = insertelement <2 x float> [[VEC_VAL]], float [[VEC_ITEM_VAL]], i64 0837// CHECK: store <2 x float> [[NEW_VEC_VAL]], ptr [[TEMP]]838// CHECK: [[NEW_I64:%.+]] = load i64, ptr [[TEMP]]839// CHECK: [[RES:%.+]] = cmpxchg ptr [[DEST]], i64 [[OLD_I64]], i64 [[NEW_I64]] monotonic monotonic, align 8840// CHECK: [[FAILED_I64_OLD_VAL:%.+]] = extractvalue { i64, i1 } [[RES]], 0841// CHECK: [[FAIL_SUCCESS:%.+]] = extractvalue { i64, i1 } [[RES]], 1842// CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]]843// CHECK: [[EXIT]]844#pragma omp atomic relaxed845 float2x.x = ulv - float2x.x;846// CHECK: [[EXPR:%.+]] = load double, ptr @{{.+}},847// CHECK: [[OLD_VAL:%.+]] = call i32 @llvm.read_register.i32([[REG:metadata ![0-9]+]])848// CHECK: [[X_RVAL:%.+]] = sitofp i32 [[OLD_VAL]] to double849// CHECK: [[DIV:%.+]] = fdiv double [[EXPR]], [[X_RVAL]]850// CHECK: [[NEW_VAL:%.+]] = fptosi double [[DIV]] to i32851// CHECK: call void @llvm.write_register.i32([[REG]], i32 [[NEW_VAL]])852// CHECK: call{{.*}} @__kmpc_flush(853#pragma omp atomic seq_cst854 rix = dv / rix;855 856// CHECK: [[LD_CPX:%.+]] = load atomic ptr, ptr @cpx monotonic857// CHECK: br label %[[CONT:.+]]858// CHECK: [[CONT]]859// CHECK: [[PHI:%.+]] = phi ptr860// CHECK: [[RES:%.+]] = cmpxchg ptr @cpx,861// CHECK: br i1 %{{.+}}, label %[[EXIT:.+]], label %[[CONT]]862 #pragma omp atomic update863 cpx += 1;864 865 return 0;866}867 868#endif869