86 lines · cpp
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _2// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc3// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple nvptx64-nvidia-cuda -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK14// expected-no-diagnostics5 6int foo(int &a) { return a; }7 8int bar() {9 int a;10 return foo(a);11}12 13 14int maini1() {15 int a;16#pragma omp target parallel map(from:a)17 {18 int b;19 a = foo(b) + bar();20 }21 return a;22}23 24// parallel region25 26 27// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6maini1v_l1628// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR0:[0-9]+]] {29// CHECK1-NEXT: entry:30// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 831// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 832// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x ptr], align 833// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 834// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 835// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 836// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6maini1v_l16_kernel_environment, ptr [[DYN_PTR]])37// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -138// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]39// CHECK1: user_code.entry:40// CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])41// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 042// CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP3]], align 843// CHECK1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6maini1v_l16_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 1)44// CHECK1-NEXT: call void @__kmpc_target_deinit()45// CHECK1-NEXT: ret void46// CHECK1: worker.exit:47// CHECK1-NEXT: ret void48//49//50// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6maini1v_l16_omp_outlined51// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR1:[0-9]+]] {52// CHECK1-NEXT: entry:53// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 854// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 855// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 856// CHECK1-NEXT: [[B:%.*]] = alloca i32, align 457// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 858// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 859// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 860// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 861// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooRi(ptr noundef nonnull align 4 dereferenceable(4) [[B]]) #[[ATTR7:[0-9]+]]62// CHECK1-NEXT: [[CALL1:%.*]] = call noundef i32 @_Z3barv() #[[ATTR7]]63// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]]64// CHECK1-NEXT: store i32 [[ADD]], ptr [[TMP0]], align 465// CHECK1-NEXT: ret void66//67//68// CHECK1-LABEL: define {{[^@]+}}@_Z3fooRi69// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {70// CHECK1-NEXT: entry:71// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 872// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 873// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 874// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 475// CHECK1-NEXT: ret i32 [[TMP1]]76//77//78// CHECK1-LABEL: define {{[^@]+}}@_Z3barv79// CHECK1-SAME: () #[[ATTR2]] {80// CHECK1-NEXT: entry:81// CHECK1-NEXT: [[A:%.*]] = call align 8 ptr @__kmpc_alloc_shared(i64 4)82// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooRi(ptr noundef nonnull align 4 dereferenceable(4) [[A]]) #[[ATTR7]]83// CHECK1-NEXT: call void @__kmpc_free_shared(ptr [[A]], i64 4)84// CHECK1-NEXT: ret i32 [[CALL]]85//86