2576 lines · cpp
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _2// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK13// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s4// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK15// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK36// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s7// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK38 9// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s10// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"11// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"12// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s13// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"14 15// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK816// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s17// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK818// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK1019// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s20// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK1021 22// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"23// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s24// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"25// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"26// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s27// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"28// expected-no-diagnostics29#ifndef HEADER30#define HEADER31 32template <class T>33struct S {34 T f;35 S(T a) : f(a) {}36 S() : f() {}37 operator T() { return T(); }38 ~S() {}39};40 41template <typename T>42T tmain() {43 S<T> test;44 T t_var = T();45 T vec[] = {1, 2};46 S<T> s_arr[] = {1, 2};47 S<T> &var = test;48 #pragma omp target49 #pragma omp teams50 #pragma omp distribute parallel for firstprivate(t_var, vec, s_arr, s_arr, var, var)51 for (int i = 0; i < 2; ++i) {52 vec[i] = t_var;53 s_arr[i] = var;54 }55 return T();56}57 58int main() {59 static int svar;60 volatile double g;61 volatile double &g1 = g;62 63 #ifdef LAMBDA64 [&]() {65 static float sfvar;66 67 #pragma omp target68 #pragma omp teams69 #pragma omp distribute parallel for firstprivate(g, g1, svar, sfvar)70 for (int i = 0; i < 2; ++i) {71 72 // addr alloca's73 74 // private alloca's75 76 // transfer input parameters into addr alloca's77 78 79 // init private alloca's with addr alloca's80 // g81 82 // g183 84 // svar85 86 // sfvar87 88 // pass firstprivate parameters to parallel outlined function89 // g90 91 // g192 93 // svar94 95 // sfvar96 97 98 99 // skip initial params100 101 // addr alloca's102 103 // private alloca's (only for 32-bit)104 105 // transfer input parameters into addr alloca's106 107 // prepare parameters for lambda108 // g109 110 // g1111 112 // svar113 114 // sfvar115 116 g = 1;117 g1 = 1;118 svar = 3;119 sfvar = 4.0;120 121 // pass params to inner lambda122 [&]() {123 g = 2;124 g1 = 2;125 svar = 4;126 sfvar = 8.0;127 128 }();129 }130 }();131 return 0;132 #else133 S<float> test;134 int t_var = 0;135 int vec[] = {1, 2};136 S<float> s_arr[] = {1, 2};137 S<float> &var = test;138 139 #pragma omp target140 #pragma omp teams141 #pragma omp distribute parallel for firstprivate(t_var, vec, s_arr, s_arr, var, var, svar)142 for (int i = 0; i < 2; ++i) {143 vec[i] = t_var;144 s_arr[i] = var;145 }146 return tmain<int>();147 #endif148}149 150 151 152 153// addr alloca's154 155// skip loop alloca's156 157// private alloca's158 159 160// init addr alloca's with input values161 162// init private alloca's with addr alloca's163// t-var164 165// vec166 167// s_arr168 169// var170 171// svar172 173// pass private alloca's to fork174// not dag to distinguish with S_VAR_CAST175 176// call destructors: var..177 178// ..and s_arr179 180 181// By OpenMP specifications, 'firstprivate' applies to both distribute and parallel for.182// However, the support for 'firstprivate' of 'parallel' is only used when 'parallel'183// is found alone. Therefore we only have one 'firstprivate' support for 'parallel for'184// in combination185 186// addr alloca's187 188// skip loop alloca's189 190// private alloca's191 192 193// init addr alloca's with input values194 195// init private alloca's with addr alloca's196// vec197 198// s_arr199 200// var201 202 203// call destructors: var..204 205// ..and s_arr206 207 208// template tmain with S_INT_TY209 210 211 212// addr alloca's213 214// skip loop alloca's215 216// private alloca's217 218 219// init addr alloca's with input values220 221// init private alloca's with addr alloca's222// t-var223 224// vec225 226// s_arr227 228// var229 230// pass private alloca's to fork231// not dag to distinguish with S_VAR_CAST232 233// call destructors: var..234 235// ..and s_arr236 237 238// By OpenMP specifications, 'firstprivate' applies to both distribute and parallel for.239// However, the support for 'firstprivate' of 'parallel' is only used when 'parallel'240// is found alone. Therefore we only have one 'firstprivate' support for 'parallel for'241// in combination242 243// addr alloca's244 245// skip loop alloca's246 247// private alloca's248 249 250// init addr alloca's with input values251 252// init private alloca's with addr alloca's253// vec254 255// s_arr256 257// var258 259 260// call destructors: var..261 262// ..and s_arr263 264 265#endif266// CHECK1-LABEL: define {{[^@]+}}@main267// CHECK1-SAME: () #[[ATTR0:[0-9]+]] {268// CHECK1-NEXT: entry:269// CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4270// CHECK1-NEXT: [[G:%.*]] = alloca double, align 8271// CHECK1-NEXT: [[G1:%.*]] = alloca ptr, align 8272// CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8273// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4274// CHECK1-NEXT: store ptr [[G]], ptr [[G1]], align 8275// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0276// CHECK1-NEXT: store ptr [[G]], ptr [[TMP0]], align 8277// CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1278// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 8279// CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP1]], align 8280// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP]])281// CHECK1-NEXT: ret i32 0282//283//284// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67285// CHECK1-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] {286// CHECK1-NEXT: entry:287// CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8288// CHECK1-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8289// CHECK1-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8290// CHECK1-NEXT: [[SFVAR_ADDR:%.*]] = alloca i64, align 8291// CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8292// CHECK1-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 8293// CHECK1-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 8294// CHECK1-NEXT: store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8295// CHECK1-NEXT: store i64 [[SFVAR]], ptr [[SFVAR_ADDR]], align 8296// CHECK1-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8297// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 8298// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined, ptr [[G_ADDR]], ptr [[TMP0]], ptr [[SVAR_ADDR]], ptr [[SFVAR_ADDR]])299// CHECK1-NEXT: ret void300//301//302// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined303// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[G:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[G1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] {304// CHECK1-NEXT: entry:305// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8306// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8307// CHECK1-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 8308// CHECK1-NEXT: [[G1_ADDR:%.*]] = alloca ptr, align 8309// CHECK1-NEXT: [[SVAR_ADDR:%.*]] = alloca ptr, align 8310// CHECK1-NEXT: [[SFVAR_ADDR:%.*]] = alloca ptr, align 8311// CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8312// CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8313// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4314// CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4315// CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4316// CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4317// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4318// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4319// CHECK1-NEXT: [[G3:%.*]] = alloca double, align 8320// CHECK1-NEXT: [[G14:%.*]] = alloca double, align 8321// CHECK1-NEXT: [[_TMP5:%.*]] = alloca ptr, align 8322// CHECK1-NEXT: [[SVAR6:%.*]] = alloca i32, align 4323// CHECK1-NEXT: [[SFVAR7:%.*]] = alloca float, align 4324// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4325// CHECK1-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8326// CHECK1-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8327// CHECK1-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8328// CHECK1-NEXT: [[SFVAR_CASTED:%.*]] = alloca i64, align 8329// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8330// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8331// CHECK1-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 8332// CHECK1-NEXT: store ptr [[G1]], ptr [[G1_ADDR]], align 8333// CHECK1-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 8334// CHECK1-NEXT: store ptr [[SFVAR]], ptr [[SFVAR_ADDR]], align 8335// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 8336// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 8337// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 8338// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SFVAR_ADDR]], align 8339// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8340// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8341// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8342// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4343// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4344// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4345// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4346// CHECK1-NEXT: [[TMP5:%.*]] = load double, ptr [[TMP0]], align 8347// CHECK1-NEXT: store double [[TMP5]], ptr [[G3]], align 8348// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8349// CHECK1-NEXT: [[TMP7:%.*]] = load double, ptr [[TMP6]], align 8350// CHECK1-NEXT: store double [[TMP7]], ptr [[G14]], align 8351// CHECK1-NEXT: store ptr [[G14]], ptr [[_TMP5]], align 8352// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP2]], align 4353// CHECK1-NEXT: store i32 [[TMP8]], ptr [[SVAR6]], align 4354// CHECK1-NEXT: [[TMP9:%.*]] = load float, ptr [[TMP3]], align 4355// CHECK1-NEXT: store float [[TMP9]], ptr [[SFVAR7]], align 4356// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8357// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4358// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)359// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4360// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1361// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]362// CHECK1: cond.true:363// CHECK1-NEXT: br label [[COND_END:%.*]]364// CHECK1: cond.false:365// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4366// CHECK1-NEXT: br label [[COND_END]]367// CHECK1: cond.end:368// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]369// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4370// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4371// CHECK1-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV]], align 4372// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]373// CHECK1: omp.inner.for.cond:374// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4375// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4376// CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]377// CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]378// CHECK1: omp.inner.for.body:379// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4380// CHECK1-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64381// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4382// CHECK1-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64383// CHECK1-NEXT: [[TMP21:%.*]] = load double, ptr [[G3]], align 8384// CHECK1-NEXT: store double [[TMP21]], ptr [[G_CASTED]], align 8385// CHECK1-NEXT: [[TMP22:%.*]] = load i64, ptr [[G_CASTED]], align 8386// CHECK1-NEXT: [[TMP23:%.*]] = load ptr, ptr [[_TMP5]], align 8387// CHECK1-NEXT: [[TMP24:%.*]] = load volatile double, ptr [[TMP23]], align 8388// CHECK1-NEXT: store double [[TMP24]], ptr [[G1_CASTED]], align 8389// CHECK1-NEXT: [[TMP25:%.*]] = load i64, ptr [[G1_CASTED]], align 8390// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[SVAR6]], align 4391// CHECK1-NEXT: store i32 [[TMP26]], ptr [[SVAR_CASTED]], align 4392// CHECK1-NEXT: [[TMP27:%.*]] = load i64, ptr [[SVAR_CASTED]], align 8393// CHECK1-NEXT: [[TMP28:%.*]] = load float, ptr [[SFVAR7]], align 4394// CHECK1-NEXT: store float [[TMP28]], ptr [[SFVAR_CASTED]], align 4395// CHECK1-NEXT: [[TMP29:%.*]] = load i64, ptr [[SFVAR_CASTED]], align 8396// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined.omp_outlined, i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP22]], i64 [[TMP25]], i64 [[TMP27]], i64 [[TMP29]])397// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]398// CHECK1: omp.inner.for.inc:399// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4400// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4401// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]402// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4403// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]404// CHECK1: omp.inner.for.end:405// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]406// CHECK1: omp.loop.exit:407// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP11]])408// CHECK1-NEXT: ret void409//410//411// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined.omp_outlined412// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]]) #[[ATTR2]] {413// CHECK1-NEXT: entry:414// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8415// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8416// CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8417// CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8418// CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8419// CHECK1-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8420// CHECK1-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8421// CHECK1-NEXT: [[SFVAR_ADDR:%.*]] = alloca i64, align 8422// CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8423// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4424// CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4425// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4426// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4427// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4428// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4429// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4430// CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8431// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8432// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8433// CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8434// CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8435// CHECK1-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 8436// CHECK1-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 8437// CHECK1-NEXT: store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8438// CHECK1-NEXT: store i64 [[SFVAR]], ptr [[SFVAR_ADDR]], align 8439// CHECK1-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8440// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4441// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4442// CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8443// CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32444// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8445// CHECK1-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32446// CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4447// CHECK1-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4448// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4449// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4450// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8451// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4452// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)453// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4454// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1455// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]456// CHECK1: cond.true:457// CHECK1-NEXT: br label [[COND_END:%.*]]458// CHECK1: cond.false:459// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4460// CHECK1-NEXT: br label [[COND_END]]461// CHECK1: cond.end:462// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]463// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4464// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4465// CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4466// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]467// CHECK1: omp.inner.for.cond:468// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4469// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4470// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]471// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]472// CHECK1: omp.inner.for.body:473// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4474// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1475// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]476// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4477// CHECK1-NEXT: store double 1.000000e+00, ptr [[G_ADDR]], align 8478// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP]], align 8479// CHECK1-NEXT: store volatile double 1.000000e+00, ptr [[TMP10]], align 8480// CHECK1-NEXT: store i32 3, ptr [[SVAR_ADDR]], align 4481// CHECK1-NEXT: store float 4.000000e+00, ptr [[SFVAR_ADDR]], align 4482// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0483// CHECK1-NEXT: store ptr [[G_ADDR]], ptr [[TMP11]], align 8484// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1485// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP]], align 8486// CHECK1-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8487// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2488// CHECK1-NEXT: store ptr [[SVAR_ADDR]], ptr [[TMP14]], align 8489// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 3490// CHECK1-NEXT: store ptr [[SFVAR_ADDR]], ptr [[TMP15]], align 8491// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(32) [[REF_TMP]])492// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]493// CHECK1: omp.body.continue:494// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]495// CHECK1: omp.inner.for.inc:496// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4497// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP16]], 1498// CHECK1-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4499// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]500// CHECK1: omp.inner.for.end:501// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]502// CHECK1: omp.loop.exit:503// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]])504// CHECK1-NEXT: ret void505//506//507// CHECK3-LABEL: define {{[^@]+}}@main508// CHECK3-SAME: () #[[ATTR0:[0-9]+]] {509// CHECK3-NEXT: entry:510// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4511// CHECK3-NEXT: [[G:%.*]] = alloca double, align 8512// CHECK3-NEXT: [[G1:%.*]] = alloca ptr, align 4513// CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4514// CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4515// CHECK3-NEXT: store ptr [[G]], ptr [[G1]], align 4516// CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0517// CHECK3-NEXT: store ptr [[G]], ptr [[TMP0]], align 4518// CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1519// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 4520// CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP1]], align 4521// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 4 dereferenceable(8) [[REF_TMP]])522// CHECK3-NEXT: ret i32 0523//524//525// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67526// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[G:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] {527// CHECK3-NEXT: entry:528// CHECK3-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 4529// CHECK3-NEXT: [[G1_ADDR:%.*]] = alloca ptr, align 4530// CHECK3-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4531// CHECK3-NEXT: [[SFVAR_ADDR:%.*]] = alloca i32, align 4532// CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4533// CHECK3-NEXT: [[G2:%.*]] = alloca double, align 8534// CHECK3-NEXT: [[G13:%.*]] = alloca double, align 8535// CHECK3-NEXT: [[_TMP4:%.*]] = alloca ptr, align 4536// CHECK3-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 4537// CHECK3-NEXT: store ptr [[G1]], ptr [[G1_ADDR]], align 4538// CHECK3-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4539// CHECK3-NEXT: store i32 [[SFVAR]], ptr [[SFVAR_ADDR]], align 4540// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4541// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 4542// CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 4543// CHECK3-NEXT: [[TMP2:%.*]] = load double, ptr [[TMP0]], align 8544// CHECK3-NEXT: store double [[TMP2]], ptr [[G2]], align 8545// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4546// CHECK3-NEXT: [[TMP4:%.*]] = load volatile double, ptr [[TMP3]], align 4547// CHECK3-NEXT: store double [[TMP4]], ptr [[G13]], align 8548// CHECK3-NEXT: store ptr [[G13]], ptr [[_TMP4]], align 4549// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP4]], align 4550// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined, ptr [[G2]], ptr [[TMP5]], ptr [[SVAR_ADDR]], ptr [[SFVAR_ADDR]])551// CHECK3-NEXT: ret void552//553//554// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined555// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[G:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] {556// CHECK3-NEXT: entry:557// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4558// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4559// CHECK3-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 4560// CHECK3-NEXT: [[G1_ADDR:%.*]] = alloca ptr, align 4561// CHECK3-NEXT: [[SVAR_ADDR:%.*]] = alloca ptr, align 4562// CHECK3-NEXT: [[SFVAR_ADDR:%.*]] = alloca ptr, align 4563// CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4564// CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4565// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4566// CHECK3-NEXT: [[_TMP2:%.*]] = alloca i32, align 4567// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4568// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4569// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4570// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4571// CHECK3-NEXT: [[G3:%.*]] = alloca double, align 8572// CHECK3-NEXT: [[G14:%.*]] = alloca double, align 8573// CHECK3-NEXT: [[_TMP5:%.*]] = alloca ptr, align 4574// CHECK3-NEXT: [[SVAR6:%.*]] = alloca i32, align 4575// CHECK3-NEXT: [[SFVAR7:%.*]] = alloca float, align 4576// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4577// CHECK3-NEXT: [[G1_CASTED:%.*]] = alloca i32, align 4578// CHECK3-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4579// CHECK3-NEXT: [[SFVAR_CASTED:%.*]] = alloca i32, align 4580// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4581// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4582// CHECK3-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 4583// CHECK3-NEXT: store ptr [[G1]], ptr [[G1_ADDR]], align 4584// CHECK3-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 4585// CHECK3-NEXT: store ptr [[SFVAR]], ptr [[SFVAR_ADDR]], align 4586// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4587// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 4588// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 4589// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SFVAR_ADDR]], align 4590// CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 4591// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4592// CHECK3-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 4593// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4594// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4595// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4596// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4597// CHECK3-NEXT: [[TMP5:%.*]] = load double, ptr [[TMP0]], align 8598// CHECK3-NEXT: store double [[TMP5]], ptr [[G3]], align 8599// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 4600// CHECK3-NEXT: [[TMP7:%.*]] = load double, ptr [[TMP6]], align 4601// CHECK3-NEXT: store double [[TMP7]], ptr [[G14]], align 8602// CHECK3-NEXT: store ptr [[G14]], ptr [[_TMP5]], align 4603// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP2]], align 4604// CHECK3-NEXT: store i32 [[TMP8]], ptr [[SVAR6]], align 4605// CHECK3-NEXT: [[TMP9:%.*]] = load float, ptr [[TMP3]], align 4606// CHECK3-NEXT: store float [[TMP9]], ptr [[SFVAR7]], align 4607// CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4608// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4609// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)610// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4611// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1612// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]613// CHECK3: cond.true:614// CHECK3-NEXT: br label [[COND_END:%.*]]615// CHECK3: cond.false:616// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4617// CHECK3-NEXT: br label [[COND_END]]618// CHECK3: cond.end:619// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]620// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4621// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4622// CHECK3-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV]], align 4623// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]624// CHECK3: omp.inner.for.cond:625// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4626// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4627// CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]628// CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]629// CHECK3: omp.inner.for.body:630// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4631// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4632// CHECK3-NEXT: [[TMP19:%.*]] = load ptr, ptr [[_TMP5]], align 4633// CHECK3-NEXT: [[TMP20:%.*]] = load volatile double, ptr [[TMP19]], align 4634// CHECK3-NEXT: store double [[TMP20]], ptr [[G1_CASTED]], align 4635// CHECK3-NEXT: [[TMP21:%.*]] = load i32, ptr [[G1_CASTED]], align 4636// CHECK3-NEXT: [[TMP22:%.*]] = load i32, ptr [[SVAR6]], align 4637// CHECK3-NEXT: store i32 [[TMP22]], ptr [[SVAR_CASTED]], align 4638// CHECK3-NEXT: [[TMP23:%.*]] = load i32, ptr [[SVAR_CASTED]], align 4639// CHECK3-NEXT: [[TMP24:%.*]] = load float, ptr [[SFVAR7]], align 4640// CHECK3-NEXT: store float [[TMP24]], ptr [[SFVAR_CASTED]], align 4641// CHECK3-NEXT: [[TMP25:%.*]] = load i32, ptr [[SFVAR_CASTED]], align 4642// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined.omp_outlined, i32 [[TMP17]], i32 [[TMP18]], ptr [[G3]], i32 [[TMP21]], i32 [[TMP23]], i32 [[TMP25]])643// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]644// CHECK3: omp.inner.for.inc:645// CHECK3-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4646// CHECK3-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4647// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP26]], [[TMP27]]648// CHECK3-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4649// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]650// CHECK3: omp.inner.for.end:651// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]652// CHECK3: omp.loop.exit:653// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP11]])654// CHECK3-NEXT: ret void655//656//657// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined.omp_outlined658// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[G:%.*]], i32 noundef [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]]) #[[ATTR2]] {659// CHECK3-NEXT: entry:660// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4661// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4662// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4663// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4664// CHECK3-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 4665// CHECK3-NEXT: [[G1_ADDR:%.*]] = alloca i32, align 4666// CHECK3-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4667// CHECK3-NEXT: [[SFVAR_ADDR:%.*]] = alloca i32, align 4668// CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4669// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4670// CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4671// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4672// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4673// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4674// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4675// CHECK3-NEXT: [[G2:%.*]] = alloca double, align 8676// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4677// CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 4678// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4679// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4680// CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4681// CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4682// CHECK3-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 4683// CHECK3-NEXT: store i32 [[G1]], ptr [[G1_ADDR]], align 4684// CHECK3-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4685// CHECK3-NEXT: store i32 [[SFVAR]], ptr [[SFVAR_ADDR]], align 4686// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4687// CHECK3-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 4688// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4689// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4690// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4691// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4692// CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_LB]], align 4693// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTOMP_UB]], align 4694// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4695// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4696// CHECK3-NEXT: [[TMP3:%.*]] = load double, ptr [[TMP0]], align 8697// CHECK3-NEXT: store double [[TMP3]], ptr [[G2]], align 8698// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4699// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4700// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)701// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4702// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1703// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]704// CHECK3: cond.true:705// CHECK3-NEXT: br label [[COND_END:%.*]]706// CHECK3: cond.false:707// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4708// CHECK3-NEXT: br label [[COND_END]]709// CHECK3: cond.end:710// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]711// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4712// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4713// CHECK3-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4714// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]715// CHECK3: omp.inner.for.cond:716// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4717// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4718// CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]719// CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]720// CHECK3: omp.inner.for.body:721// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4722// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1723// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]724// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4725// CHECK3-NEXT: store double 1.000000e+00, ptr [[G2]], align 8726// CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP]], align 4727// CHECK3-NEXT: store volatile double 1.000000e+00, ptr [[TMP12]], align 4728// CHECK3-NEXT: store i32 3, ptr [[SVAR_ADDR]], align 4729// CHECK3-NEXT: store float 4.000000e+00, ptr [[SFVAR_ADDR]], align 4730// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0731// CHECK3-NEXT: store ptr [[G2]], ptr [[TMP13]], align 4732// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1733// CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP]], align 4734// CHECK3-NEXT: store ptr [[TMP15]], ptr [[TMP14]], align 4735// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2736// CHECK3-NEXT: store ptr [[SVAR_ADDR]], ptr [[TMP16]], align 4737// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 3738// CHECK3-NEXT: store ptr [[SFVAR_ADDR]], ptr [[TMP17]], align 4739// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 4 dereferenceable(16) [[REF_TMP]])740// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]741// CHECK3: omp.body.continue:742// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]743// CHECK3: omp.inner.for.inc:744// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4745// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP18]], 1746// CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4747// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]748// CHECK3: omp.inner.for.end:749// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]750// CHECK3: omp.loop.exit:751// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP5]])752// CHECK3-NEXT: ret void753//754//755// CHECK8-LABEL: define {{[^@]+}}@main756// CHECK8-SAME: () #[[ATTR0:[0-9]+]] {757// CHECK8-NEXT: entry:758// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4759// CHECK8-NEXT: [[G:%.*]] = alloca double, align 8760// CHECK8-NEXT: [[G1:%.*]] = alloca ptr, align 8761// CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4762// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4763// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4764// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4765// CHECK8-NEXT: [[VAR:%.*]] = alloca ptr, align 8766// CHECK8-NEXT: [[TMP:%.*]] = alloca ptr, align 8767// CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8768// CHECK8-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8769// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8770// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8771// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8772// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4773// CHECK8-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8774// CHECK8-NEXT: store i32 0, ptr [[RETVAL]], align 4775// CHECK8-NEXT: store ptr [[G]], ptr [[G1]], align 8776// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])777// CHECK8-NEXT: store i32 0, ptr [[T_VAR]], align 4778// CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i64 8, i1 false)779// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], float noundef 1.000000e+00)780// CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i64 1781// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00)782// CHECK8-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8783// CHECK8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8784// CHECK8-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8785// CHECK8-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4786// CHECK8-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4787// CHECK8-NEXT: [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8788// CHECK8-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8789// CHECK8-NEXT: [[TMP4:%.*]] = load i32, ptr @_ZZ4mainE4svar, align 4790// CHECK8-NEXT: store i32 [[TMP4]], ptr [[SVAR_CASTED]], align 4791// CHECK8-NEXT: [[TMP5:%.*]] = load i64, ptr [[SVAR_CASTED]], align 8792// CHECK8-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8793// CHECK8-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 8794// CHECK8-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0795// CHECK8-NEXT: store i64 [[TMP2]], ptr [[TMP8]], align 8796// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0797// CHECK8-NEXT: store i64 [[TMP2]], ptr [[TMP9]], align 8798// CHECK8-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0799// CHECK8-NEXT: store ptr null, ptr [[TMP10]], align 8800// CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1801// CHECK8-NEXT: store ptr [[VEC]], ptr [[TMP11]], align 8802// CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1803// CHECK8-NEXT: store ptr [[VEC]], ptr [[TMP12]], align 8804// CHECK8-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1805// CHECK8-NEXT: store ptr null, ptr [[TMP13]], align 8806// CHECK8-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2807// CHECK8-NEXT: store ptr [[S_ARR]], ptr [[TMP14]], align 8808// CHECK8-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2809// CHECK8-NEXT: store ptr [[S_ARR]], ptr [[TMP15]], align 8810// CHECK8-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2811// CHECK8-NEXT: store ptr null, ptr [[TMP16]], align 8812// CHECK8-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3813// CHECK8-NEXT: store ptr [[TMP6]], ptr [[TMP17]], align 8814// CHECK8-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3815// CHECK8-NEXT: store ptr [[TMP7]], ptr [[TMP18]], align 8816// CHECK8-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3817// CHECK8-NEXT: store ptr null, ptr [[TMP19]], align 8818// CHECK8-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4819// CHECK8-NEXT: store i64 [[TMP5]], ptr [[TMP20]], align 8820// CHECK8-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4821// CHECK8-NEXT: store i64 [[TMP5]], ptr [[TMP21]], align 8822// CHECK8-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4823// CHECK8-NEXT: store ptr null, ptr [[TMP22]], align 8824// CHECK8-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0825// CHECK8-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0826// CHECK8-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0827// CHECK8-NEXT: store i32 3, ptr [[TMP25]], align 4828// CHECK8-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1829// CHECK8-NEXT: store i32 5, ptr [[TMP26]], align 4830// CHECK8-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2831// CHECK8-NEXT: store ptr [[TMP23]], ptr [[TMP27]], align 8832// CHECK8-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3833// CHECK8-NEXT: store ptr [[TMP24]], ptr [[TMP28]], align 8834// CHECK8-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4835// CHECK8-NEXT: store ptr @.offload_sizes, ptr [[TMP29]], align 8836// CHECK8-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5837// CHECK8-NEXT: store ptr @.offload_maptypes, ptr [[TMP30]], align 8838// CHECK8-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6839// CHECK8-NEXT: store ptr null, ptr [[TMP31]], align 8840// CHECK8-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7841// CHECK8-NEXT: store ptr null, ptr [[TMP32]], align 8842// CHECK8-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8843// CHECK8-NEXT: store i64 2, ptr [[TMP33]], align 8844// CHECK8-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9845// CHECK8-NEXT: store i64 0, ptr [[TMP34]], align 8846// CHECK8-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10847// CHECK8-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP35]], align 4848// CHECK8-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11849// CHECK8-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP36]], align 4850// CHECK8-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12851// CHECK8-NEXT: store i32 0, ptr [[TMP37]], align 4852// CHECK8-NEXT: [[TMP38:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139.region_id, ptr [[KERNEL_ARGS]])853// CHECK8-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0854// CHECK8-NEXT: br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]855// CHECK8: omp_offload.failed:856// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139(i64 [[TMP2]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP3]], i64 [[TMP5]]) #[[ATTR4:[0-9]+]]857// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]]858// CHECK8: omp_offload.cont:859// CHECK8-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()860// CHECK8-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4861// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0862// CHECK8-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2863// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]864// CHECK8: arraydestroy.body:865// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP40]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]866// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1867// CHECK8-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]868// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]869// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]870// CHECK8: arraydestroy.done2:871// CHECK8-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]872// CHECK8-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4873// CHECK8-NEXT: ret i32 [[TMP41]]874//875//876// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev877// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {878// CHECK8-NEXT: entry:879// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8880// CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8881// CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8882// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])883// CHECK8-NEXT: ret void884//885//886// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef887// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {888// CHECK8-NEXT: entry:889// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8890// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4891// CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8892// CHECK8-NEXT: store float [[A]], ptr [[A_ADDR]], align 4893// CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8894// CHECK8-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4895// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])896// CHECK8-NEXT: ret void897//898//899// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139900// CHECK8-SAME: (i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] {901// CHECK8-NEXT: entry:902// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8903// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8904// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8905// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8906// CHECK8-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8907// CHECK8-NEXT: [[TMP:%.*]] = alloca ptr, align 8908// CHECK8-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8909// CHECK8-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8910// CHECK8-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8911// CHECK8-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8912// CHECK8-NEXT: store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8913// CHECK8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8914// CHECK8-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8915// CHECK8-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8916// CHECK8-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8917// CHECK8-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8918// CHECK8-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP3]], ptr [[SVAR_ADDR]])919// CHECK8-NEXT: ret void920//921//922// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139.omp_outlined923// CHECK8-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] {924// CHECK8-NEXT: entry:925// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8926// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8927// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 8928// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8929// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8930// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8931// CHECK8-NEXT: [[SVAR_ADDR:%.*]] = alloca ptr, align 8932// CHECK8-NEXT: [[TMP:%.*]] = alloca ptr, align 8933// CHECK8-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8934// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4935// CHECK8-NEXT: [[_TMP2:%.*]] = alloca i32, align 4936// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4937// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4938// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4939// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4940// CHECK8-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4941// CHECK8-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4942// CHECK8-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4943// CHECK8-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4944// CHECK8-NEXT: [[_TMP8:%.*]] = alloca ptr, align 8945// CHECK8-NEXT: [[SVAR9:%.*]] = alloca i32, align 4946// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4947// CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8948// CHECK8-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8949// CHECK8-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8950// CHECK8-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8951// CHECK8-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8952// CHECK8-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8953// CHECK8-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8954// CHECK8-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8955// CHECK8-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 8956// CHECK8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8957// CHECK8-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8958// CHECK8-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8959// CHECK8-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8960// CHECK8-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 8961// CHECK8-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 8962// CHECK8-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8963// CHECK8-NEXT: store ptr [[TMP5]], ptr [[_TMP1]], align 8964// CHECK8-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4965// CHECK8-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4966// CHECK8-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4967// CHECK8-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4968// CHECK8-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP0]], align 4969// CHECK8-NEXT: store i32 [[TMP6]], ptr [[T_VAR3]], align 4970// CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC4]], ptr align 4 [[TMP1]], i64 8, i1 false)971// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0972// CHECK8-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2973// CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP7]]974// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]975// CHECK8: omp.arraycpy.body:976// CHECK8-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]977// CHECK8-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]978// CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i64 4, i1 false)979// CHECK8-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1980// CHECK8-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1981// CHECK8-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP7]]982// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]]983// CHECK8: omp.arraycpy.done6:984// CHECK8-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 8985// CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VAR7]], ptr align 4 [[TMP8]], i64 4, i1 false)986// CHECK8-NEXT: store ptr [[VAR7]], ptr [[_TMP8]], align 8987// CHECK8-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP4]], align 4988// CHECK8-NEXT: store i32 [[TMP9]], ptr [[SVAR9]], align 4989// CHECK8-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8990// CHECK8-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4991// CHECK8-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)992// CHECK8-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4993// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1994// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]995// CHECK8: cond.true:996// CHECK8-NEXT: br label [[COND_END:%.*]]997// CHECK8: cond.false:998// CHECK8-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4999// CHECK8-NEXT: br label [[COND_END]]1000// CHECK8: cond.end:1001// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]1002// CHECK8-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 41003// CHECK8-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 41004// CHECK8-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV]], align 41005// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1006// CHECK8: omp.inner.for.cond:1007// CHECK8-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41008// CHECK8-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 41009// CHECK8-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]1010// CHECK8-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]1011// CHECK8: omp.inner.for.cond.cleanup:1012// CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]]1013// CHECK8: omp.inner.for.body:1014// CHECK8-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 41015// CHECK8-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i641016// CHECK8-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 41017// CHECK8-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i641018// CHECK8-NEXT: [[TMP21:%.*]] = load i32, ptr [[T_VAR3]], align 41019// CHECK8-NEXT: store i32 [[TMP21]], ptr [[T_VAR_CASTED]], align 41020// CHECK8-NEXT: [[TMP22:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 81021// CHECK8-NEXT: [[TMP23:%.*]] = load ptr, ptr [[_TMP8]], align 81022// CHECK8-NEXT: [[TMP24:%.*]] = load i32, ptr [[SVAR9]], align 41023// CHECK8-NEXT: store i32 [[TMP24]], ptr [[SVAR_CASTED]], align 41024// CHECK8-NEXT: [[TMP25:%.*]] = load i64, ptr [[SVAR_CASTED]], align 81025// CHECK8-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 7, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139.omp_outlined.omp_outlined, i64 [[TMP18]], i64 [[TMP20]], ptr [[VEC4]], i64 [[TMP22]], ptr [[S_ARR5]], ptr [[TMP23]], i64 [[TMP25]])1026// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1027// CHECK8: omp.inner.for.inc:1028// CHECK8-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41029// CHECK8-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 41030// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP26]], [[TMP27]]1031// CHECK8-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 41032// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]]1033// CHECK8: omp.inner.for.end:1034// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]]1035// CHECK8: omp.loop.exit:1036// CHECK8-NEXT: [[TMP28:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81037// CHECK8-NEXT: [[TMP29:%.*]] = load i32, ptr [[TMP28]], align 41038// CHECK8-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP29]])1039// CHECK8-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]]1040// CHECK8-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 01041// CHECK8-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i64 21042// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]1043// CHECK8: arraydestroy.body:1044// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP30]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1045// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -11046// CHECK8-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]1047// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]]1048// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]]1049// CHECK8: arraydestroy.done12:1050// CHECK8-NEXT: ret void1051//1052//1053// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139.omp_outlined.omp_outlined1054// CHECK8-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3]] {1055// CHECK8-NEXT: entry:1056// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81057// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81058// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 81059// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 81060// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 81061// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 81062// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 81063// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 81064// CHECK8-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 81065// CHECK8-NEXT: [[TMP:%.*]] = alloca ptr, align 81066// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41067// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 41068// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 41069// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 41070// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41071// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41072// CHECK8-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 41073// CHECK8-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 41074// CHECK8-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 41075// CHECK8-NEXT: [[_TMP7:%.*]] = alloca ptr, align 81076// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 41077// CHECK8-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81078// CHECK8-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81079// CHECK8-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 81080// CHECK8-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 81081// CHECK8-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 81082// CHECK8-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 81083// CHECK8-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 81084// CHECK8-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 81085// CHECK8-NEXT: store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 81086// CHECK8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 81087// CHECK8-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 81088// CHECK8-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 81089// CHECK8-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 81090// CHECK8-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 41091// CHECK8-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 41092// CHECK8-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 81093// CHECK8-NEXT: [[CONV:%.*]] = trunc i64 [[TMP3]] to i321094// CHECK8-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 81095// CHECK8-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP4]] to i321096// CHECK8-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 41097// CHECK8-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 41098// CHECK8-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 41099// CHECK8-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41100// CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC3]], ptr align 4 [[TMP0]], i64 8, i1 false)1101// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 01102// CHECK8-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 21103// CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]]1104// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE5:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]1105// CHECK8: omp.arraycpy.body:1106// CHECK8-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1107// CHECK8-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1108// CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i64 4, i1 false)1109// CHECK8-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 11110// CHECK8-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 11111// CHECK8-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]]1112// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_BODY]]1113// CHECK8: omp.arraycpy.done5:1114// CHECK8-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 81115// CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VAR6]], ptr align 4 [[TMP6]], i64 4, i1 false)1116// CHECK8-NEXT: store ptr [[VAR6]], ptr [[_TMP7]], align 81117// CHECK8-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81118// CHECK8-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 41119// CHECK8-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP8]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1120// CHECK8-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41121// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 11122// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1123// CHECK8: cond.true:1124// CHECK8-NEXT: br label [[COND_END:%.*]]1125// CHECK8: cond.false:1126// CHECK8-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41127// CHECK8-NEXT: br label [[COND_END]]1128// CHECK8: cond.end:1129// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]1130// CHECK8-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 41131// CHECK8-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41132// CHECK8-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 41133// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1134// CHECK8: omp.inner.for.cond:1135// CHECK8-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41136// CHECK8-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41137// CHECK8-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]1138// CHECK8-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]1139// CHECK8: omp.inner.for.cond.cleanup:1140// CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]]1141// CHECK8: omp.inner.for.body:1142// CHECK8-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41143// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 11144// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]1145// CHECK8-NEXT: store i32 [[ADD]], ptr [[I]], align 41146// CHECK8-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 41147// CHECK8-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 41148// CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i641149// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]]1150// CHECK8-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 41151// CHECK8-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 81152// CHECK8-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 41153// CHECK8-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP18]] to i641154// CHECK8-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM9]]1155// CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP17]], i64 4, i1 false)1156// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1157// CHECK8: omp.body.continue:1158// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1159// CHECK8: omp.inner.for.inc:1160// CHECK8-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41161// CHECK8-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP19]], 11162// CHECK8-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 41163// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]]1164// CHECK8: omp.inner.for.end:1165// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]]1166// CHECK8: omp.loop.exit:1167// CHECK8-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81168// CHECK8-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 41169// CHECK8-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]])1170// CHECK8-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]]1171// CHECK8-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 01172// CHECK8-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN12]], i64 21173// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]1174// CHECK8: arraydestroy.body:1175// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1176// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -11177// CHECK8-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]1178// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]]1179// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]]1180// CHECK8: arraydestroy.done13:1181// CHECK8-NEXT: ret void1182//1183//1184// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev1185// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1186// CHECK8-NEXT: entry:1187// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81188// CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81189// CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81190// CHECK8-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]1191// CHECK8-NEXT: ret void1192//1193//1194// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v1195// CHECK8-SAME: () #[[ATTR1]] comdat {1196// CHECK8-NEXT: entry:1197// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 41198// CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 41199// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 41200// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 41201// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 41202// CHECK8-NEXT: [[VAR:%.*]] = alloca ptr, align 81203// CHECK8-NEXT: [[TMP:%.*]] = alloca ptr, align 81204// CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 81205// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 81206// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 81207// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 81208// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 41209// CHECK8-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81210// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])1211// CHECK8-NEXT: store i32 0, ptr [[T_VAR]], align 41212// CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)1213// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef signext 1)1214// CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 11215// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2)1216// CHECK8-NEXT: store ptr [[TEST]], ptr [[VAR]], align 81217// CHECK8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 81218// CHECK8-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 81219// CHECK8-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 41220// CHECK8-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 41221// CHECK8-NEXT: [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 81222// CHECK8-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 81223// CHECK8-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 81224// CHECK8-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 81225// CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01226// CHECK8-NEXT: store i64 [[TMP2]], ptr [[TMP6]], align 81227// CHECK8-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01228// CHECK8-NEXT: store i64 [[TMP2]], ptr [[TMP7]], align 81229// CHECK8-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 01230// CHECK8-NEXT: store ptr null, ptr [[TMP8]], align 81231// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 11232// CHECK8-NEXT: store ptr [[VEC]], ptr [[TMP9]], align 81233// CHECK8-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 11234// CHECK8-NEXT: store ptr [[VEC]], ptr [[TMP10]], align 81235// CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 11236// CHECK8-NEXT: store ptr null, ptr [[TMP11]], align 81237// CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 21238// CHECK8-NEXT: store ptr [[S_ARR]], ptr [[TMP12]], align 81239// CHECK8-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 21240// CHECK8-NEXT: store ptr [[S_ARR]], ptr [[TMP13]], align 81241// CHECK8-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 21242// CHECK8-NEXT: store ptr null, ptr [[TMP14]], align 81243// CHECK8-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 31244// CHECK8-NEXT: store ptr [[TMP4]], ptr [[TMP15]], align 81245// CHECK8-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 31246// CHECK8-NEXT: store ptr [[TMP5]], ptr [[TMP16]], align 81247// CHECK8-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 31248// CHECK8-NEXT: store ptr null, ptr [[TMP17]], align 81249// CHECK8-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01250// CHECK8-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01251// CHECK8-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 01252// CHECK8-NEXT: store i32 3, ptr [[TMP20]], align 41253// CHECK8-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11254// CHECK8-NEXT: store i32 4, ptr [[TMP21]], align 41255// CHECK8-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 21256// CHECK8-NEXT: store ptr [[TMP18]], ptr [[TMP22]], align 81257// CHECK8-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 31258// CHECK8-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 81259// CHECK8-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 41260// CHECK8-NEXT: store ptr @.offload_sizes.1, ptr [[TMP24]], align 81261// CHECK8-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 51262// CHECK8-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP25]], align 81263// CHECK8-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 61264// CHECK8-NEXT: store ptr null, ptr [[TMP26]], align 81265// CHECK8-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 71266// CHECK8-NEXT: store ptr null, ptr [[TMP27]], align 81267// CHECK8-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 81268// CHECK8-NEXT: store i64 2, ptr [[TMP28]], align 81269// CHECK8-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 91270// CHECK8-NEXT: store i64 0, ptr [[TMP29]], align 81271// CHECK8-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 101272// CHECK8-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP30]], align 41273// CHECK8-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 111274// CHECK8-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP31]], align 41275// CHECK8-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 121276// CHECK8-NEXT: store i32 0, ptr [[TMP32]], align 41277// CHECK8-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.region_id, ptr [[KERNEL_ARGS]])1278// CHECK8-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 01279// CHECK8-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]1280// CHECK8: omp_offload.failed:1281// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48(i64 [[TMP2]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP3]]) #[[ATTR4]]1282// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]]1283// CHECK8: omp_offload.cont:1284// CHECK8-NEXT: store i32 0, ptr [[RETVAL]], align 41285// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 01286// CHECK8-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 21287// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]1288// CHECK8: arraydestroy.body:1289// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1290// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -11291// CHECK8-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]1292// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]1293// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]1294// CHECK8: arraydestroy.done2:1295// CHECK8-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]1296// CHECK8-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 41297// CHECK8-NEXT: ret i32 [[TMP36]]1298//1299//1300// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev1301// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1302// CHECK8-NEXT: entry:1303// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81304// CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81305// CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81306// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 01307// CHECK8-NEXT: store float 0.000000e+00, ptr [[F]], align 41308// CHECK8-NEXT: ret void1309//1310//1311// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef1312// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {1313// CHECK8-NEXT: entry:1314// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81315// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 41316// CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81317// CHECK8-NEXT: store float [[A]], ptr [[A_ADDR]], align 41318// CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81319// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 01320// CHECK8-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 41321// CHECK8-NEXT: store float [[TMP0]], ptr [[F]], align 41322// CHECK8-NEXT: ret void1323//1324//1325// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev1326// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1327// CHECK8-NEXT: entry:1328// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81329// CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81330// CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81331// CHECK8-NEXT: ret void1332//1333//1334// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev1335// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1336// CHECK8-NEXT: entry:1337// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81338// CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81339// CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81340// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])1341// CHECK8-NEXT: ret void1342//1343//1344// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei1345// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {1346// CHECK8-NEXT: entry:1347// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81348// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 41349// CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81350// CHECK8-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 41351// CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81352// CHECK8-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41353// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])1354// CHECK8-NEXT: ret void1355//1356//1357// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l481358// CHECK8-SAME: (i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {1359// CHECK8-NEXT: entry:1360// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 81361// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 81362// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 81363// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 81364// CHECK8-NEXT: [[TMP:%.*]] = alloca ptr, align 81365// CHECK8-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 81366// CHECK8-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 81367// CHECK8-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 81368// CHECK8-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 81369// CHECK8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 81370// CHECK8-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 81371// CHECK8-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 81372// CHECK8-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 81373// CHECK8-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 81374// CHECK8-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP3]])1375// CHECK8-NEXT: ret void1376//1377//1378// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.omp_outlined1379// CHECK8-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {1380// CHECK8-NEXT: entry:1381// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81382// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81383// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 81384// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 81385// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 81386// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 81387// CHECK8-NEXT: [[TMP:%.*]] = alloca ptr, align 81388// CHECK8-NEXT: [[_TMP1:%.*]] = alloca ptr, align 81389// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41390// CHECK8-NEXT: [[_TMP2:%.*]] = alloca i32, align 41391// CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 41392// CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 41393// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41394// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41395// CHECK8-NEXT: [[T_VAR3:%.*]] = alloca i32, align 41396// CHECK8-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 41397// CHECK8-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 41398// CHECK8-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 41399// CHECK8-NEXT: [[_TMP8:%.*]] = alloca ptr, align 81400// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 41401// CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 81402// CHECK8-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81403// CHECK8-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81404// CHECK8-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 81405// CHECK8-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 81406// CHECK8-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 81407// CHECK8-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 81408// CHECK8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 81409// CHECK8-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 81410// CHECK8-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 81411// CHECK8-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 81412// CHECK8-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 81413// CHECK8-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 81414// CHECK8-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 81415// CHECK8-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 41416// CHECK8-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 41417// CHECK8-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 41418// CHECK8-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41419// CHECK8-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 41420// CHECK8-NEXT: store i32 [[TMP5]], ptr [[T_VAR3]], align 41421// CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC4]], ptr align 4 [[TMP1]], i64 8, i1 false)1422// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 01423// CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 21424// CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP6]]1425// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]1426// CHECK8: omp.arraycpy.body:1427// CHECK8-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1428// CHECK8-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1429// CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i64 4, i1 false)1430// CHECK8-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 11431// CHECK8-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 11432// CHECK8-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]1433// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]]1434// CHECK8: omp.arraycpy.done6:1435// CHECK8-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP1]], align 81436// CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VAR7]], ptr align 4 [[TMP7]], i64 4, i1 false)1437// CHECK8-NEXT: store ptr [[VAR7]], ptr [[_TMP8]], align 81438// CHECK8-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81439// CHECK8-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 41440// CHECK8-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP9]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1441// CHECK8-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 41442// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 11443// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1444// CHECK8: cond.true:1445// CHECK8-NEXT: br label [[COND_END:%.*]]1446// CHECK8: cond.false:1447// CHECK8-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 41448// CHECK8-NEXT: br label [[COND_END]]1449// CHECK8: cond.end:1450// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]1451// CHECK8-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 41452// CHECK8-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 41453// CHECK8-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 41454// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1455// CHECK8: omp.inner.for.cond:1456// CHECK8-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41457// CHECK8-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 41458// CHECK8-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]1459// CHECK8-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]1460// CHECK8: omp.inner.for.cond.cleanup:1461// CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]]1462// CHECK8: omp.inner.for.body:1463// CHECK8-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 41464// CHECK8-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i641465// CHECK8-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 41466// CHECK8-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i641467// CHECK8-NEXT: [[TMP19:%.*]] = load i32, ptr [[T_VAR3]], align 41468// CHECK8-NEXT: store i32 [[TMP19]], ptr [[T_VAR_CASTED]], align 41469// CHECK8-NEXT: [[TMP20:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 81470// CHECK8-NEXT: [[TMP21:%.*]] = load ptr, ptr [[_TMP8]], align 81471// CHECK8-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.omp_outlined.omp_outlined, i64 [[TMP16]], i64 [[TMP18]], ptr [[VEC4]], i64 [[TMP20]], ptr [[S_ARR5]], ptr [[TMP21]])1472// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1473// CHECK8: omp.inner.for.inc:1474// CHECK8-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41475// CHECK8-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 41476// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]1477// CHECK8-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 41478// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]]1479// CHECK8: omp.inner.for.end:1480// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]]1481// CHECK8: omp.loop.exit:1482// CHECK8-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81483// CHECK8-NEXT: [[TMP25:%.*]] = load i32, ptr [[TMP24]], align 41484// CHECK8-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP25]])1485// CHECK8-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]]1486// CHECK8-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 01487// CHECK8-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i64 21488// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]1489// CHECK8: arraydestroy.body:1490// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP26]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1491// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -11492// CHECK8-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]1493// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]1494// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]1495// CHECK8: arraydestroy.done11:1496// CHECK8-NEXT: ret void1497//1498//1499// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.omp_outlined.omp_outlined1500// CHECK8-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {1501// CHECK8-NEXT: entry:1502// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81503// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81504// CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 81505// CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 81506// CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 81507// CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 81508// CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 81509// CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 81510// CHECK8-NEXT: [[TMP:%.*]] = alloca ptr, align 81511// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41512// CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 41513// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 41514// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 41515// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41516// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41517// CHECK8-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 41518// CHECK8-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 41519// CHECK8-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 41520// CHECK8-NEXT: [[_TMP7:%.*]] = alloca ptr, align 81521// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 41522// CHECK8-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81523// CHECK8-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81524// CHECK8-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 81525// CHECK8-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 81526// CHECK8-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 81527// CHECK8-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 81528// CHECK8-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 81529// CHECK8-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 81530// CHECK8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 81531// CHECK8-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 81532// CHECK8-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 81533// CHECK8-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 81534// CHECK8-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 41535// CHECK8-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 41536// CHECK8-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 81537// CHECK8-NEXT: [[CONV:%.*]] = trunc i64 [[TMP3]] to i321538// CHECK8-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 81539// CHECK8-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP4]] to i321540// CHECK8-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 41541// CHECK8-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 41542// CHECK8-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 41543// CHECK8-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41544// CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC3]], ptr align 4 [[TMP0]], i64 8, i1 false)1545// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 01546// CHECK8-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 21547// CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]]1548// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE5:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]1549// CHECK8: omp.arraycpy.body:1550// CHECK8-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1551// CHECK8-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1552// CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i64 4, i1 false)1553// CHECK8-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 11554// CHECK8-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 11555// CHECK8-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]]1556// CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_BODY]]1557// CHECK8: omp.arraycpy.done5:1558// CHECK8-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 81559// CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VAR6]], ptr align 4 [[TMP6]], i64 4, i1 false)1560// CHECK8-NEXT: store ptr [[VAR6]], ptr [[_TMP7]], align 81561// CHECK8-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81562// CHECK8-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 41563// CHECK8-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP8]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1564// CHECK8-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41565// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 11566// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1567// CHECK8: cond.true:1568// CHECK8-NEXT: br label [[COND_END:%.*]]1569// CHECK8: cond.false:1570// CHECK8-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41571// CHECK8-NEXT: br label [[COND_END]]1572// CHECK8: cond.end:1573// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]1574// CHECK8-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 41575// CHECK8-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41576// CHECK8-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 41577// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1578// CHECK8: omp.inner.for.cond:1579// CHECK8-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41580// CHECK8-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41581// CHECK8-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]1582// CHECK8-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]1583// CHECK8: omp.inner.for.cond.cleanup:1584// CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]]1585// CHECK8: omp.inner.for.body:1586// CHECK8-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41587// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 11588// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]1589// CHECK8-NEXT: store i32 [[ADD]], ptr [[I]], align 41590// CHECK8-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 41591// CHECK8-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 41592// CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i641593// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]]1594// CHECK8-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 41595// CHECK8-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 81596// CHECK8-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 41597// CHECK8-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP18]] to i641598// CHECK8-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM9]]1599// CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP17]], i64 4, i1 false)1600// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1601// CHECK8: omp.body.continue:1602// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1603// CHECK8: omp.inner.for.inc:1604// CHECK8-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41605// CHECK8-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP19]], 11606// CHECK8-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 41607// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]]1608// CHECK8: omp.inner.for.end:1609// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]]1610// CHECK8: omp.loop.exit:1611// CHECK8-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81612// CHECK8-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 41613// CHECK8-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]])1614// CHECK8-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]]1615// CHECK8-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 01616// CHECK8-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 21617// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]1618// CHECK8: arraydestroy.body:1619// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1620// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -11621// CHECK8-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]1622// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]]1623// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]]1624// CHECK8: arraydestroy.done13:1625// CHECK8-NEXT: ret void1626//1627//1628// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev1629// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1630// CHECK8-NEXT: entry:1631// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81632// CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81633// CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81634// CHECK8-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]1635// CHECK8-NEXT: ret void1636//1637//1638// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev1639// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1640// CHECK8-NEXT: entry:1641// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81642// CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81643// CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81644// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 01645// CHECK8-NEXT: store i32 0, ptr [[F]], align 41646// CHECK8-NEXT: ret void1647//1648//1649// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei1650// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {1651// CHECK8-NEXT: entry:1652// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81653// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 41654// CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81655// CHECK8-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 41656// CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81657// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 01658// CHECK8-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41659// CHECK8-NEXT: store i32 [[TMP0]], ptr [[F]], align 41660// CHECK8-NEXT: ret void1661//1662//1663// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev1664// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1665// CHECK8-NEXT: entry:1666// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81667// CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81668// CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81669// CHECK8-NEXT: ret void1670//1671//1672// CHECK10-LABEL: define {{[^@]+}}@main1673// CHECK10-SAME: () #[[ATTR0:[0-9]+]] {1674// CHECK10-NEXT: entry:1675// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 41676// CHECK10-NEXT: [[G:%.*]] = alloca double, align 81677// CHECK10-NEXT: [[G1:%.*]] = alloca ptr, align 41678// CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 41679// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 41680// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 41681// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 41682// CHECK10-NEXT: [[VAR:%.*]] = alloca ptr, align 41683// CHECK10-NEXT: [[TMP:%.*]] = alloca ptr, align 41684// CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 41685// CHECK10-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 41686// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 41687// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 41688// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 41689// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 41690// CHECK10-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81691// CHECK10-NEXT: store i32 0, ptr [[RETVAL]], align 41692// CHECK10-NEXT: store ptr [[G]], ptr [[G1]], align 41693// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])1694// CHECK10-NEXT: store i32 0, ptr [[T_VAR]], align 41695// CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i32 8, i1 false)1696// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], float noundef 1.000000e+00)1697// CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i32 11698// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00)1699// CHECK10-NEXT: store ptr [[TEST]], ptr [[VAR]], align 41700// CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 41701// CHECK10-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 41702// CHECK10-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 41703// CHECK10-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 41704// CHECK10-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 41705// CHECK10-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 41706// CHECK10-NEXT: [[TMP4:%.*]] = load i32, ptr @_ZZ4mainE4svar, align 41707// CHECK10-NEXT: store i32 [[TMP4]], ptr [[SVAR_CASTED]], align 41708// CHECK10-NEXT: [[TMP5:%.*]] = load i32, ptr [[SVAR_CASTED]], align 41709// CHECK10-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 41710// CHECK10-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 41711// CHECK10-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01712// CHECK10-NEXT: store i32 [[TMP2]], ptr [[TMP8]], align 41713// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01714// CHECK10-NEXT: store i32 [[TMP2]], ptr [[TMP9]], align 41715// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 01716// CHECK10-NEXT: store ptr null, ptr [[TMP10]], align 41717// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 11718// CHECK10-NEXT: store ptr [[VEC]], ptr [[TMP11]], align 41719// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 11720// CHECK10-NEXT: store ptr [[VEC]], ptr [[TMP12]], align 41721// CHECK10-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 11722// CHECK10-NEXT: store ptr null, ptr [[TMP13]], align 41723// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 21724// CHECK10-NEXT: store ptr [[S_ARR]], ptr [[TMP14]], align 41725// CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 21726// CHECK10-NEXT: store ptr [[S_ARR]], ptr [[TMP15]], align 41727// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 21728// CHECK10-NEXT: store ptr null, ptr [[TMP16]], align 41729// CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 31730// CHECK10-NEXT: store ptr [[TMP6]], ptr [[TMP17]], align 41731// CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 31732// CHECK10-NEXT: store ptr [[TMP7]], ptr [[TMP18]], align 41733// CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 31734// CHECK10-NEXT: store ptr null, ptr [[TMP19]], align 41735// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 41736// CHECK10-NEXT: store i32 [[TMP5]], ptr [[TMP20]], align 41737// CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 41738// CHECK10-NEXT: store i32 [[TMP5]], ptr [[TMP21]], align 41739// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 41740// CHECK10-NEXT: store ptr null, ptr [[TMP22]], align 41741// CHECK10-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01742// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01743// CHECK10-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 01744// CHECK10-NEXT: store i32 3, ptr [[TMP25]], align 41745// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11746// CHECK10-NEXT: store i32 5, ptr [[TMP26]], align 41747// CHECK10-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 21748// CHECK10-NEXT: store ptr [[TMP23]], ptr [[TMP27]], align 41749// CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 31750// CHECK10-NEXT: store ptr [[TMP24]], ptr [[TMP28]], align 41751// CHECK10-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 41752// CHECK10-NEXT: store ptr @.offload_sizes, ptr [[TMP29]], align 41753// CHECK10-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 51754// CHECK10-NEXT: store ptr @.offload_maptypes, ptr [[TMP30]], align 41755// CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 61756// CHECK10-NEXT: store ptr null, ptr [[TMP31]], align 41757// CHECK10-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 71758// CHECK10-NEXT: store ptr null, ptr [[TMP32]], align 41759// CHECK10-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 81760// CHECK10-NEXT: store i64 2, ptr [[TMP33]], align 81761// CHECK10-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 91762// CHECK10-NEXT: store i64 0, ptr [[TMP34]], align 81763// CHECK10-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 101764// CHECK10-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP35]], align 41765// CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 111766// CHECK10-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP36]], align 41767// CHECK10-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 121768// CHECK10-NEXT: store i32 0, ptr [[TMP37]], align 41769// CHECK10-NEXT: [[TMP38:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139.region_id, ptr [[KERNEL_ARGS]])1770// CHECK10-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 01771// CHECK10-NEXT: br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]1772// CHECK10: omp_offload.failed:1773// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139(i32 [[TMP2]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP3]], i32 [[TMP5]]) #[[ATTR4:[0-9]+]]1774// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]]1775// CHECK10: omp_offload.cont:1776// CHECK10-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()1777// CHECK10-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 41778// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 01779// CHECK10-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 21780// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]1781// CHECK10: arraydestroy.body:1782// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP40]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1783// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -11784// CHECK10-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]1785// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]1786// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]1787// CHECK10: arraydestroy.done2:1788// CHECK10-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]1789// CHECK10-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 41790// CHECK10-NEXT: ret i32 [[TMP41]]1791//1792//1793// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev1794// CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {1795// CHECK10-NEXT: entry:1796// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41797// CHECK10-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41798// CHECK10-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41799// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])1800// CHECK10-NEXT: ret void1801//1802//1803// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef1804// CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1805// CHECK10-NEXT: entry:1806// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41807// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 41808// CHECK10-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41809// CHECK10-NEXT: store float [[A]], ptr [[A_ADDR]], align 41810// CHECK10-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41811// CHECK10-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 41812// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])1813// CHECK10-NEXT: ret void1814//1815//1816// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l1391817// CHECK10-SAME: (i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] {1818// CHECK10-NEXT: entry:1819// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 41820// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 41821// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 41822// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 41823// CHECK10-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 41824// CHECK10-NEXT: [[TMP:%.*]] = alloca ptr, align 41825// CHECK10-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 41826// CHECK10-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 41827// CHECK10-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 41828// CHECK10-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 41829// CHECK10-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 41830// CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 41831// CHECK10-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 41832// CHECK10-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 41833// CHECK10-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 41834// CHECK10-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 41835// CHECK10-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP3]], ptr [[SVAR_ADDR]])1836// CHECK10-NEXT: ret void1837//1838//1839// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139.omp_outlined1840// CHECK10-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] {1841// CHECK10-NEXT: entry:1842// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 41843// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 41844// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 41845// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 41846// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 41847// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 41848// CHECK10-NEXT: [[SVAR_ADDR:%.*]] = alloca ptr, align 41849// CHECK10-NEXT: [[TMP:%.*]] = alloca ptr, align 41850// CHECK10-NEXT: [[_TMP1:%.*]] = alloca ptr, align 41851// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41852// CHECK10-NEXT: [[_TMP2:%.*]] = alloca i32, align 41853// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 41854// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 41855// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41856// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41857// CHECK10-NEXT: [[T_VAR3:%.*]] = alloca i32, align 41858// CHECK10-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 41859// CHECK10-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 41860// CHECK10-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 41861// CHECK10-NEXT: [[_TMP8:%.*]] = alloca ptr, align 41862// CHECK10-NEXT: [[SVAR9:%.*]] = alloca i32, align 41863// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 41864// CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 41865// CHECK10-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 41866// CHECK10-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 41867// CHECK10-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 41868// CHECK10-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 41869// CHECK10-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 41870// CHECK10-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 41871// CHECK10-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 41872// CHECK10-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 41873// CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 41874// CHECK10-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 41875// CHECK10-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 41876// CHECK10-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 41877// CHECK10-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 41878// CHECK10-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 41879// CHECK10-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 41880// CHECK10-NEXT: store ptr [[TMP5]], ptr [[_TMP1]], align 41881// CHECK10-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 41882// CHECK10-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 41883// CHECK10-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 41884// CHECK10-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41885// CHECK10-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP0]], align 41886// CHECK10-NEXT: store i32 [[TMP6]], ptr [[T_VAR3]], align 41887// CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC4]], ptr align 4 [[TMP1]], i32 8, i1 false)1888// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 01889// CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 21890// CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP7]]1891// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]1892// CHECK10: omp.arraycpy.body:1893// CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1894// CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1895// CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 4, i1 false)1896// CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 11897// CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 11898// CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP7]]1899// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]]1900// CHECK10: omp.arraycpy.done6:1901// CHECK10-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 41902// CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VAR7]], ptr align 4 [[TMP8]], i32 4, i1 false)1903// CHECK10-NEXT: store ptr [[VAR7]], ptr [[_TMP8]], align 41904// CHECK10-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP4]], align 41905// CHECK10-NEXT: store i32 [[TMP9]], ptr [[SVAR9]], align 41906// CHECK10-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41907// CHECK10-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 41908// CHECK10-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1909// CHECK10-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 41910// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 11911// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1912// CHECK10: cond.true:1913// CHECK10-NEXT: br label [[COND_END:%.*]]1914// CHECK10: cond.false:1915// CHECK10-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 41916// CHECK10-NEXT: br label [[COND_END]]1917// CHECK10: cond.end:1918// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]1919// CHECK10-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 41920// CHECK10-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 41921// CHECK10-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV]], align 41922// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1923// CHECK10: omp.inner.for.cond:1924// CHECK10-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41925// CHECK10-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 41926// CHECK10-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]1927// CHECK10-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]1928// CHECK10: omp.inner.for.cond.cleanup:1929// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]]1930// CHECK10: omp.inner.for.body:1931// CHECK10-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 41932// CHECK10-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 41933// CHECK10-NEXT: [[TMP19:%.*]] = load i32, ptr [[T_VAR3]], align 41934// CHECK10-NEXT: store i32 [[TMP19]], ptr [[T_VAR_CASTED]], align 41935// CHECK10-NEXT: [[TMP20:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 41936// CHECK10-NEXT: [[TMP21:%.*]] = load ptr, ptr [[_TMP8]], align 41937// CHECK10-NEXT: [[TMP22:%.*]] = load i32, ptr [[SVAR9]], align 41938// CHECK10-NEXT: store i32 [[TMP22]], ptr [[SVAR_CASTED]], align 41939// CHECK10-NEXT: [[TMP23:%.*]] = load i32, ptr [[SVAR_CASTED]], align 41940// CHECK10-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 7, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139.omp_outlined.omp_outlined, i32 [[TMP17]], i32 [[TMP18]], ptr [[VEC4]], i32 [[TMP20]], ptr [[S_ARR5]], ptr [[TMP21]], i32 [[TMP23]])1941// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1942// CHECK10: omp.inner.for.inc:1943// CHECK10-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41944// CHECK10-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 41945// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP24]], [[TMP25]]1946// CHECK10-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 41947// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]]1948// CHECK10: omp.inner.for.end:1949// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]1950// CHECK10: omp.loop.exit:1951// CHECK10-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41952// CHECK10-NEXT: [[TMP27:%.*]] = load i32, ptr [[TMP26]], align 41953// CHECK10-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP27]])1954// CHECK10-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]]1955// CHECK10-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 01956// CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i32 21957// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]1958// CHECK10: arraydestroy.body:1959// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP28]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1960// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -11961// CHECK10-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]1962// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]]1963// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]]1964// CHECK10: arraydestroy.done12:1965// CHECK10-NEXT: ret void1966//1967//1968// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139.omp_outlined.omp_outlined1969// CHECK10-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3]] {1970// CHECK10-NEXT: entry:1971// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 41972// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 41973// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 41974// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 41975// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 41976// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 41977// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 41978// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 41979// CHECK10-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 41980// CHECK10-NEXT: [[TMP:%.*]] = alloca ptr, align 41981// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41982// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 41983// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 41984// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 41985// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41986// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41987// CHECK10-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 41988// CHECK10-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 41989// CHECK10-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 41990// CHECK10-NEXT: [[_TMP6:%.*]] = alloca ptr, align 41991// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 41992// CHECK10-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 41993// CHECK10-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 41994// CHECK10-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 41995// CHECK10-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 41996// CHECK10-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 41997// CHECK10-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 41998// CHECK10-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 41999// CHECK10-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 42000// CHECK10-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 42001// CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 42002// CHECK10-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 42003// CHECK10-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 42004// CHECK10-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 42005// CHECK10-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 42006// CHECK10-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 42007// CHECK10-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 42008// CHECK10-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 42009// CHECK10-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_LB]], align 42010// CHECK10-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 42011// CHECK10-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 42012// CHECK10-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 42013// CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false)2014// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 02015// CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 22016// CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]]2017// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]2018// CHECK10: omp.arraycpy.body:2019// CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]2020// CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]2021// CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 4, i1 false)2022// CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 12023// CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 12024// CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]]2025// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]2026// CHECK10: omp.arraycpy.done4:2027// CHECK10-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 42028// CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VAR5]], ptr align 4 [[TMP6]], i32 4, i1 false)2029// CHECK10-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 42030// CHECK10-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 42031// CHECK10-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 42032// CHECK10-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP8]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)2033// CHECK10-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42034// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 12035// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2036// CHECK10: cond.true:2037// CHECK10-NEXT: br label [[COND_END:%.*]]2038// CHECK10: cond.false:2039// CHECK10-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42040// CHECK10-NEXT: br label [[COND_END]]2041// CHECK10: cond.end:2042// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]2043// CHECK10-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 42044// CHECK10-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42045// CHECK10-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 42046// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]2047// CHECK10: omp.inner.for.cond:2048// CHECK10-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42049// CHECK10-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42050// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]2051// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]2052// CHECK10: omp.inner.for.cond.cleanup:2053// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]]2054// CHECK10: omp.inner.for.body:2055// CHECK10-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42056// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 12057// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]2058// CHECK10-NEXT: store i32 [[ADD]], ptr [[I]], align 42059// CHECK10-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 42060// CHECK10-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 42061// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i32 0, i32 [[TMP16]]2062// CHECK10-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 42063// CHECK10-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP6]], align 42064// CHECK10-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 42065// CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 [[TMP18]]2066// CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP17]], i32 4, i1 false)2067// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]2068// CHECK10: omp.body.continue:2069// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]2070// CHECK10: omp.inner.for.inc:2071// CHECK10-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42072// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP19]], 12073// CHECK10-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 42074// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]]2075// CHECK10: omp.inner.for.end:2076// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]2077// CHECK10: omp.loop.exit:2078// CHECK10-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 42079// CHECK10-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 42080// CHECK10-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]])2081// CHECK10-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]2082// CHECK10-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 02083// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i32 22084// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]2085// CHECK10: arraydestroy.body:2086// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]2087// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -12088// CHECK10-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]2089// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]2090// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]2091// CHECK10: arraydestroy.done11:2092// CHECK10-NEXT: ret void2093//2094//2095// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev2096// CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2097// CHECK10-NEXT: entry:2098// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42099// CHECK10-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42100// CHECK10-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42101// CHECK10-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]2102// CHECK10-NEXT: ret void2103//2104//2105// CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiET_v2106// CHECK10-SAME: () #[[ATTR1]] comdat {2107// CHECK10-NEXT: entry:2108// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 42109// CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 42110// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 42111// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 42112// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 42113// CHECK10-NEXT: [[VAR:%.*]] = alloca ptr, align 42114// CHECK10-NEXT: [[TMP:%.*]] = alloca ptr, align 42115// CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 42116// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 42117// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 42118// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 42119// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 42120// CHECK10-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 82121// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])2122// CHECK10-NEXT: store i32 0, ptr [[T_VAR]], align 42123// CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false)2124// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1)2125// CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 12126// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)2127// CHECK10-NEXT: store ptr [[TEST]], ptr [[VAR]], align 42128// CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 42129// CHECK10-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 42130// CHECK10-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 42131// CHECK10-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 42132// CHECK10-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 42133// CHECK10-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 42134// CHECK10-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 42135// CHECK10-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 42136// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 02137// CHECK10-NEXT: store i32 [[TMP2]], ptr [[TMP6]], align 42138// CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 02139// CHECK10-NEXT: store i32 [[TMP2]], ptr [[TMP7]], align 42140// CHECK10-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 02141// CHECK10-NEXT: store ptr null, ptr [[TMP8]], align 42142// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 12143// CHECK10-NEXT: store ptr [[VEC]], ptr [[TMP9]], align 42144// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 12145// CHECK10-NEXT: store ptr [[VEC]], ptr [[TMP10]], align 42146// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 12147// CHECK10-NEXT: store ptr null, ptr [[TMP11]], align 42148// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 22149// CHECK10-NEXT: store ptr [[S_ARR]], ptr [[TMP12]], align 42150// CHECK10-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 22151// CHECK10-NEXT: store ptr [[S_ARR]], ptr [[TMP13]], align 42152// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 22153// CHECK10-NEXT: store ptr null, ptr [[TMP14]], align 42154// CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 32155// CHECK10-NEXT: store ptr [[TMP4]], ptr [[TMP15]], align 42156// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 32157// CHECK10-NEXT: store ptr [[TMP5]], ptr [[TMP16]], align 42158// CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 32159// CHECK10-NEXT: store ptr null, ptr [[TMP17]], align 42160// CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 02161// CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 02162// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 02163// CHECK10-NEXT: store i32 3, ptr [[TMP20]], align 42164// CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12165// CHECK10-NEXT: store i32 4, ptr [[TMP21]], align 42166// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 22167// CHECK10-NEXT: store ptr [[TMP18]], ptr [[TMP22]], align 42168// CHECK10-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 32169// CHECK10-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 42170// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 42171// CHECK10-NEXT: store ptr @.offload_sizes.1, ptr [[TMP24]], align 42172// CHECK10-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 52173// CHECK10-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP25]], align 42174// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 62175// CHECK10-NEXT: store ptr null, ptr [[TMP26]], align 42176// CHECK10-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 72177// CHECK10-NEXT: store ptr null, ptr [[TMP27]], align 42178// CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 82179// CHECK10-NEXT: store i64 2, ptr [[TMP28]], align 82180// CHECK10-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 92181// CHECK10-NEXT: store i64 0, ptr [[TMP29]], align 82182// CHECK10-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 102183// CHECK10-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP30]], align 42184// CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 112185// CHECK10-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP31]], align 42186// CHECK10-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 122187// CHECK10-NEXT: store i32 0, ptr [[TMP32]], align 42188// CHECK10-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.region_id, ptr [[KERNEL_ARGS]])2189// CHECK10-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 02190// CHECK10-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]2191// CHECK10: omp_offload.failed:2192// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48(i32 [[TMP2]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP3]]) #[[ATTR4]]2193// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]]2194// CHECK10: omp_offload.cont:2195// CHECK10-NEXT: store i32 0, ptr [[RETVAL]], align 42196// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 02197// CHECK10-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 22198// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]2199// CHECK10: arraydestroy.body:2200// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]2201// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -12202// CHECK10-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]2203// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]2204// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]2205// CHECK10: arraydestroy.done2:2206// CHECK10-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]2207// CHECK10-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 42208// CHECK10-NEXT: ret i32 [[TMP36]]2209//2210//2211// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev2212// CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2213// CHECK10-NEXT: entry:2214// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42215// CHECK10-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42216// CHECK10-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42217// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 02218// CHECK10-NEXT: store float 0.000000e+00, ptr [[F]], align 42219// CHECK10-NEXT: ret void2220//2221//2222// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef2223// CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2224// CHECK10-NEXT: entry:2225// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42226// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 42227// CHECK10-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42228// CHECK10-NEXT: store float [[A]], ptr [[A_ADDR]], align 42229// CHECK10-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42230// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 02231// CHECK10-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 42232// CHECK10-NEXT: store float [[TMP0]], ptr [[F]], align 42233// CHECK10-NEXT: ret void2234//2235//2236// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev2237// CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2238// CHECK10-NEXT: entry:2239// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42240// CHECK10-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42241// CHECK10-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42242// CHECK10-NEXT: ret void2243//2244//2245// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev2246// CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2247// CHECK10-NEXT: entry:2248// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42249// CHECK10-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42250// CHECK10-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42251// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])2252// CHECK10-NEXT: ret void2253//2254//2255// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei2256// CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2257// CHECK10-NEXT: entry:2258// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42259// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 42260// CHECK10-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42261// CHECK10-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 42262// CHECK10-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42263// CHECK10-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 42264// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])2265// CHECK10-NEXT: ret void2266//2267//2268// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l482269// CHECK10-SAME: (i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {2270// CHECK10-NEXT: entry:2271// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 42272// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 42273// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 42274// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 42275// CHECK10-NEXT: [[TMP:%.*]] = alloca ptr, align 42276// CHECK10-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 42277// CHECK10-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 42278// CHECK10-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 42279// CHECK10-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 42280// CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 42281// CHECK10-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 42282// CHECK10-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 42283// CHECK10-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 42284// CHECK10-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 42285// CHECK10-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP3]])2286// CHECK10-NEXT: ret void2287//2288//2289// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.omp_outlined2290// CHECK10-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {2291// CHECK10-NEXT: entry:2292// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 42293// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 42294// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 42295// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 42296// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 42297// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 42298// CHECK10-NEXT: [[TMP:%.*]] = alloca ptr, align 42299// CHECK10-NEXT: [[_TMP1:%.*]] = alloca ptr, align 42300// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 42301// CHECK10-NEXT: [[_TMP2:%.*]] = alloca i32, align 42302// CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 42303// CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 42304// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42305// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42306// CHECK10-NEXT: [[T_VAR3:%.*]] = alloca i32, align 42307// CHECK10-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 42308// CHECK10-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 42309// CHECK10-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 42310// CHECK10-NEXT: [[_TMP8:%.*]] = alloca ptr, align 42311// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 42312// CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 42313// CHECK10-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 42314// CHECK10-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 42315// CHECK10-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 42316// CHECK10-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 42317// CHECK10-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 42318// CHECK10-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 42319// CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 42320// CHECK10-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 42321// CHECK10-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 42322// CHECK10-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 42323// CHECK10-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 42324// CHECK10-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 42325// CHECK10-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 42326// CHECK10-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 42327// CHECK10-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 42328// CHECK10-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 42329// CHECK10-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 42330// CHECK10-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 42331// CHECK10-NEXT: store i32 [[TMP5]], ptr [[T_VAR3]], align 42332// CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC4]], ptr align 4 [[TMP1]], i32 8, i1 false)2333// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 02334// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 22335// CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP6]]2336// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]2337// CHECK10: omp.arraycpy.body:2338// CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]2339// CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]2340// CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 4, i1 false)2341// CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 12342// CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 12343// CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]2344// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]]2345// CHECK10: omp.arraycpy.done6:2346// CHECK10-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP1]], align 42347// CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VAR7]], ptr align 4 [[TMP7]], i32 4, i1 false)2348// CHECK10-NEXT: store ptr [[VAR7]], ptr [[_TMP8]], align 42349// CHECK10-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 42350// CHECK10-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 42351// CHECK10-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP9]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)2352// CHECK10-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 42353// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 12354// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2355// CHECK10: cond.true:2356// CHECK10-NEXT: br label [[COND_END:%.*]]2357// CHECK10: cond.false:2358// CHECK10-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 42359// CHECK10-NEXT: br label [[COND_END]]2360// CHECK10: cond.end:2361// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]2362// CHECK10-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 42363// CHECK10-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 42364// CHECK10-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 42365// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]2366// CHECK10: omp.inner.for.cond:2367// CHECK10-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42368// CHECK10-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 42369// CHECK10-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]2370// CHECK10-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]2371// CHECK10: omp.inner.for.cond.cleanup:2372// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]]2373// CHECK10: omp.inner.for.body:2374// CHECK10-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 42375// CHECK10-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 42376// CHECK10-NEXT: [[TMP17:%.*]] = load i32, ptr [[T_VAR3]], align 42377// CHECK10-NEXT: store i32 [[TMP17]], ptr [[T_VAR_CASTED]], align 42378// CHECK10-NEXT: [[TMP18:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 42379// CHECK10-NEXT: [[TMP19:%.*]] = load ptr, ptr [[_TMP8]], align 42380// CHECK10-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.omp_outlined.omp_outlined, i32 [[TMP15]], i32 [[TMP16]], ptr [[VEC4]], i32 [[TMP18]], ptr [[S_ARR5]], ptr [[TMP19]])2381// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]2382// CHECK10: omp.inner.for.inc:2383// CHECK10-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42384// CHECK10-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 42385// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]2386// CHECK10-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 42387// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]]2388// CHECK10: omp.inner.for.end:2389// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]2390// CHECK10: omp.loop.exit:2391// CHECK10-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 42392// CHECK10-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 42393// CHECK10-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP23]])2394// CHECK10-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]]2395// CHECK10-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 02396// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i32 22397// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]2398// CHECK10: arraydestroy.body:2399// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP24]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]2400// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -12401// CHECK10-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]2402// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]2403// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]2404// CHECK10: arraydestroy.done11:2405// CHECK10-NEXT: ret void2406//2407//2408// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.omp_outlined.omp_outlined2409// CHECK10-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {2410// CHECK10-NEXT: entry:2411// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 42412// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 42413// CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 42414// CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 42415// CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 42416// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 42417// CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 42418// CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 42419// CHECK10-NEXT: [[TMP:%.*]] = alloca ptr, align 42420// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 42421// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 42422// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 42423// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 42424// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42425// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42426// CHECK10-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 42427// CHECK10-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 42428// CHECK10-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 42429// CHECK10-NEXT: [[_TMP6:%.*]] = alloca ptr, align 42430// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 42431// CHECK10-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 42432// CHECK10-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 42433// CHECK10-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 42434// CHECK10-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 42435// CHECK10-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 42436// CHECK10-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 42437// CHECK10-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 42438// CHECK10-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 42439// CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 42440// CHECK10-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 42441// CHECK10-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 42442// CHECK10-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 42443// CHECK10-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 42444// CHECK10-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 42445// CHECK10-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 42446// CHECK10-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 42447// CHECK10-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_LB]], align 42448// CHECK10-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 42449// CHECK10-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 42450// CHECK10-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 42451// CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false)2452// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 02453// CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 22454// CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]]2455// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]2456// CHECK10: omp.arraycpy.body:2457// CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]2458// CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]2459// CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 4, i1 false)2460// CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 12461// CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 12462// CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]]2463// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]2464// CHECK10: omp.arraycpy.done4:2465// CHECK10-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 42466// CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VAR5]], ptr align 4 [[TMP6]], i32 4, i1 false)2467// CHECK10-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 42468// CHECK10-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 42469// CHECK10-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 42470// CHECK10-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP8]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)2471// CHECK10-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42472// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 12473// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2474// CHECK10: cond.true:2475// CHECK10-NEXT: br label [[COND_END:%.*]]2476// CHECK10: cond.false:2477// CHECK10-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42478// CHECK10-NEXT: br label [[COND_END]]2479// CHECK10: cond.end:2480// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]2481// CHECK10-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 42482// CHECK10-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42483// CHECK10-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 42484// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]2485// CHECK10: omp.inner.for.cond:2486// CHECK10-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42487// CHECK10-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42488// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]2489// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]2490// CHECK10: omp.inner.for.cond.cleanup:2491// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]]2492// CHECK10: omp.inner.for.body:2493// CHECK10-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42494// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 12495// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]2496// CHECK10-NEXT: store i32 [[ADD]], ptr [[I]], align 42497// CHECK10-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 42498// CHECK10-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 42499// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i32 0, i32 [[TMP16]]2500// CHECK10-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 42501// CHECK10-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP6]], align 42502// CHECK10-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 42503// CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 [[TMP18]]2504// CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP17]], i32 4, i1 false)2505// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]2506// CHECK10: omp.body.continue:2507// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]2508// CHECK10: omp.inner.for.inc:2509// CHECK10-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42510// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP19]], 12511// CHECK10-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 42512// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]]2513// CHECK10: omp.inner.for.end:2514// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]2515// CHECK10: omp.loop.exit:2516// CHECK10-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 42517// CHECK10-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 42518// CHECK10-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]])2519// CHECK10-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]2520// CHECK10-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 02521// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i32 22522// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]2523// CHECK10: arraydestroy.body:2524// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]2525// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -12526// CHECK10-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]2527// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]2528// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]2529// CHECK10: arraydestroy.done11:2530// CHECK10-NEXT: ret void2531//2532//2533// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev2534// CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2535// CHECK10-NEXT: entry:2536// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42537// CHECK10-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42538// CHECK10-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42539// CHECK10-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]2540// CHECK10-NEXT: ret void2541//2542//2543// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev2544// CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2545// CHECK10-NEXT: entry:2546// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42547// CHECK10-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42548// CHECK10-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42549// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 02550// CHECK10-NEXT: store i32 0, ptr [[F]], align 42551// CHECK10-NEXT: ret void2552//2553//2554// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei2555// CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2556// CHECK10-NEXT: entry:2557// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42558// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 42559// CHECK10-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42560// CHECK10-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 42561// CHECK10-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42562// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 02563// CHECK10-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 42564// CHECK10-NEXT: store i32 [[TMP0]], ptr [[F]], align 42565// CHECK10-NEXT: ret void2566//2567//2568// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev2569// CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2570// CHECK10-NEXT: entry:2571// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42572// CHECK10-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42573// CHECK10-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42574// CHECK10-NEXT: ret void2575//2576