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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _2// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK13// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s4// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK15// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK36// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s7// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK38 9// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s10// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK511// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK612// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s13// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK614 15// RUN: %clang_cc1  -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK816// RUN: %clang_cc1  -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s17// RUN: %clang_cc1  -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK818// RUN: %clang_cc1  -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK1019// RUN: %clang_cc1  -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s20// RUN: %clang_cc1  -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK1021 22// RUN: %clang_cc1  -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK1223// RUN: %clang_cc1  -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s24// RUN: %clang_cc1  -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK1225// RUN: %clang_cc1  -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK1426// RUN: %clang_cc1  -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s27// RUN: %clang_cc1  -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK1428// expected-no-diagnostics29#ifndef HEADER30#define HEADER31 32template <class T>33struct S {34  T f;35  S(T a) : f(a) {}36  S() : f() {}37  operator T() { return T(); }38  ~S() {}39};40 41template <typename T>42T tmain() {43  S<T> test;44  T t_var = T();45  T vec[] = {1, 2};46  S<T> s_arr[] = {1, 2};47  S<T> &var = test;48  #pragma omp target49  #pragma omp teams50  #pragma omp distribute parallel for simd firstprivate(t_var, vec, s_arr, s_arr, var, var)51  for (int i = 0; i < 2; ++i) {52    vec[i] = t_var;53    s_arr[i] = var;54  }55  return T();56}57 58int main() {59  static int svar;60  volatile double g;61  volatile double &g1 = g;62 63  #ifdef LAMBDA64  [&]() {65    static float sfvar;66 67    #pragma omp target68    #pragma omp teams69    #pragma omp distribute parallel for simd firstprivate(g, g1, svar, sfvar)70    for (int i = 0; i < 2; ++i) {71 72      // addr alloca's73 74      // private alloca's75 76      // transfer input parameters into addr alloca's77 78      // init private alloca's with addr alloca's79      // g80 81      // g182 83      // svar84 85      // sfvar86 87      // pass firstprivate parameters to parallel outlined function88      // g89 90      // g191 92      // svar93 94      // sfvar95 96 97 98      // skip initial params99 100      // addr alloca's101 102      // private alloca's (only for 32-bit)103 104      // transfer input parameters into addr alloca's105 106      // prepare parameters for lambda107      // g108 109      // g1110 111      // svar112 113      // sfvar114 115      g = 1;116      g1 = 1;117      svar = 3;118      sfvar = 4.0;119 120      // pass params to inner lambda121      [&]() {122	g = 2;123	g1 = 2;124	svar = 4;125	sfvar = 8.0;126 127      }();128    }129  }();130  return 0;131  #else132  S<float> test;133  int t_var = 0;134  int vec[] = {1, 2};135  S<float> s_arr[] = {1, 2};136  S<float> &var = test;137 138  #pragma omp target139  #pragma omp teams140  #pragma omp distribute parallel for simd firstprivate(t_var, vec, s_arr, s_arr, var, var, svar)141  for (int i = 0; i < 2; ++i) {142    vec[i] = t_var;143    s_arr[i] = var;144  }145  return tmain<int>();146  #endif147}148 149 150 151 152// addr alloca's153 154// skip loop alloca's155 156// private alloca's157 158 159// init addr alloca's with input values160 161// init private alloca's with addr alloca's162// t-var163 164// vec165 166// s_arr167 168// var169 170// svar171 172// pass private alloca's to fork173// not dag to distinguish with S_VAR_CAST174 175// call destructors: var..176 177// ..and s_arr178 179 180// By OpenMP specifications, 'firstprivate' applies to both distribute and parallel for.181// However, the support for 'firstprivate' of 'parallel' is only used when 'parallel'182// is found alone. Therefore we only have one 'firstprivate' support for 'parallel for'183// in combination184 185// addr alloca's186 187// skip loop alloca's188 189// private alloca's190 191 192// init addr alloca's with input values193 194// init private alloca's with addr alloca's195// vec196 197// s_arr198 199// var200 201 202// call destructors: var..203 204// ..and s_arr205 206 207// template tmain with S_INT_TY208 209 210 211// addr alloca's212 213// skip loop alloca's214 215// private alloca's216 217 218// init addr alloca's with input values219 220// init private alloca's with addr alloca's221// t-var222 223// vec224 225// s_arr226 227// var228 229// pass private alloca's to fork230// not dag to distinguish with S_VAR_CAST231 232// call destructors: var..233 234// ..and s_arr235 236 237// By OpenMP specifications, 'firstprivate' applies to both distribute and parallel for.238// However, the support for 'firstprivate' of 'parallel' is only used when 'parallel'239// is found alone. Therefore we only have one 'firstprivate' support for 'parallel for'240// in combination241 242// addr alloca's243 244// skip loop alloca's245 246// private alloca's247 248 249// init addr alloca's with input values250 251// init private alloca's with addr alloca's252// vec253 254// s_arr255 256// var257 258 259// call destructors: var..260 261// ..and s_arr262 263 264#endif265// CHECK1-LABEL: define {{[^@]+}}@main266// CHECK1-SAME: () #[[ATTR0:[0-9]+]] {267// CHECK1-NEXT:  entry:268// CHECK1-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4269// CHECK1-NEXT:    [[G:%.*]] = alloca double, align 8270// CHECK1-NEXT:    [[G1:%.*]] = alloca ptr, align 8271// CHECK1-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8272// CHECK1-NEXT:    store i32 0, ptr [[RETVAL]], align 4273// CHECK1-NEXT:    store ptr [[G]], ptr [[G1]], align 8274// CHECK1-NEXT:    [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0275// CHECK1-NEXT:    store ptr [[G]], ptr [[TMP0]], align 8276// CHECK1-NEXT:    [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1277// CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[G1]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]]278// CHECK1-NEXT:    store ptr [[TMP2]], ptr [[TMP1]], align 8279// CHECK1-NEXT:    call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP]])280// CHECK1-NEXT:    ret i32 0281//282//283// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67284// CHECK1-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] {285// CHECK1-NEXT:  entry:286// CHECK1-NEXT:    [[G_ADDR:%.*]] = alloca i64, align 8287// CHECK1-NEXT:    [[G1_ADDR:%.*]] = alloca i64, align 8288// CHECK1-NEXT:    [[SVAR_ADDR:%.*]] = alloca i64, align 8289// CHECK1-NEXT:    [[SFVAR_ADDR:%.*]] = alloca i64, align 8290// CHECK1-NEXT:    [[TMP:%.*]] = alloca ptr, align 8291// CHECK1-NEXT:    store i64 [[G]], ptr [[G_ADDR]], align 8292// CHECK1-NEXT:    store i64 [[G1]], ptr [[G1_ADDR]], align 8293// CHECK1-NEXT:    store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8294// CHECK1-NEXT:    store i64 [[SFVAR]], ptr [[SFVAR_ADDR]], align 8295// CHECK1-NEXT:    store ptr [[G1_ADDR]], ptr [[TMP]], align 8296// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]]297// CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined, ptr [[G_ADDR]], ptr [[TMP0]], ptr [[SVAR_ADDR]], ptr [[SFVAR_ADDR]])298// CHECK1-NEXT:    ret void299//300//301// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined302// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[G:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[G1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] {303// CHECK1-NEXT:  entry:304// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8305// CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8306// CHECK1-NEXT:    [[G_ADDR:%.*]] = alloca ptr, align 8307// CHECK1-NEXT:    [[G1_ADDR:%.*]] = alloca ptr, align 8308// CHECK1-NEXT:    [[SVAR_ADDR:%.*]] = alloca ptr, align 8309// CHECK1-NEXT:    [[SFVAR_ADDR:%.*]] = alloca ptr, align 8310// CHECK1-NEXT:    [[TMP:%.*]] = alloca ptr, align 8311// CHECK1-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8312// CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4313// CHECK1-NEXT:    [[_TMP2:%.*]] = alloca i32, align 4314// CHECK1-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4315// CHECK1-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4316// CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4317// CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4318// CHECK1-NEXT:    [[G3:%.*]] = alloca double, align 8319// CHECK1-NEXT:    [[G14:%.*]] = alloca double, align 8320// CHECK1-NEXT:    [[_TMP5:%.*]] = alloca ptr, align 8321// CHECK1-NEXT:    [[SVAR6:%.*]] = alloca i32, align 4322// CHECK1-NEXT:    [[SFVAR7:%.*]] = alloca float, align 4323// CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4324// CHECK1-NEXT:    [[G_CASTED:%.*]] = alloca i64, align 8325// CHECK1-NEXT:    [[G1_CASTED:%.*]] = alloca i64, align 8326// CHECK1-NEXT:    [[SVAR_CASTED:%.*]] = alloca i64, align 8327// CHECK1-NEXT:    [[SFVAR_CASTED:%.*]] = alloca i64, align 8328// CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8329// CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8330// CHECK1-NEXT:    store ptr [[G]], ptr [[G_ADDR]], align 8331// CHECK1-NEXT:    store ptr [[G1]], ptr [[G1_ADDR]], align 8332// CHECK1-NEXT:    store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 8333// CHECK1-NEXT:    store ptr [[SFVAR]], ptr [[SFVAR_ADDR]], align 8334// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]335// CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]336// CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 8, !nonnull [[META5]], !align [[META7:![0-9]+]]337// CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[SFVAR_ADDR]], align 8, !nonnull [[META5]], !align [[META7]]338// CHECK1-NEXT:    store ptr [[TMP1]], ptr [[TMP]], align 8339// CHECK1-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]]340// CHECK1-NEXT:    store ptr [[TMP4]], ptr [[_TMP1]], align 8341// CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4342// CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_COMB_UB]], align 4343// CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4344// CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4345// CHECK1-NEXT:    [[TMP5:%.*]] = load double, ptr [[TMP0]], align 8346// CHECK1-NEXT:    store double [[TMP5]], ptr [[G3]], align 8347// CHECK1-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META6]]348// CHECK1-NEXT:    [[TMP7:%.*]] = load double, ptr [[TMP6]], align 8349// CHECK1-NEXT:    store double [[TMP7]], ptr [[G14]], align 8350// CHECK1-NEXT:    store ptr [[G14]], ptr [[_TMP5]], align 8351// CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP2]], align 4352// CHECK1-NEXT:    store i32 [[TMP8]], ptr [[SVAR6]], align 4353// CHECK1-NEXT:    [[TMP9:%.*]] = load float, ptr [[TMP3]], align 4354// CHECK1-NEXT:    store float [[TMP9]], ptr [[SFVAR7]], align 4355// CHECK1-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8356// CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4357// CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)358// CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4359// CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1360// CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]361// CHECK1:       cond.true:362// CHECK1-NEXT:    br label [[COND_END:%.*]]363// CHECK1:       cond.false:364// CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4365// CHECK1-NEXT:    br label [[COND_END]]366// CHECK1:       cond.end:367// CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]368// CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4369// CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4370// CHECK1-NEXT:    store i32 [[TMP14]], ptr [[DOTOMP_IV]], align 4371// CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]372// CHECK1:       omp.inner.for.cond:373// CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8:![0-9]+]]374// CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP8]]375// CHECK1-NEXT:    [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]376// CHECK1-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]377// CHECK1:       omp.inner.for.body:378// CHECK1-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP8]]379// CHECK1-NEXT:    [[TMP18:%.*]] = zext i32 [[TMP17]] to i64380// CHECK1-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP8]]381// CHECK1-NEXT:    [[TMP20:%.*]] = zext i32 [[TMP19]] to i64382// CHECK1-NEXT:    [[TMP21:%.*]] = load double, ptr [[G3]], align 8, !llvm.access.group [[ACC_GRP8]]383// CHECK1-NEXT:    store double [[TMP21]], ptr [[G_CASTED]], align 8, !llvm.access.group [[ACC_GRP8]]384// CHECK1-NEXT:    [[TMP22:%.*]] = load i64, ptr [[G_CASTED]], align 8, !llvm.access.group [[ACC_GRP8]]385// CHECK1-NEXT:    [[TMP23:%.*]] = load ptr, ptr [[_TMP5]], align 8, !nonnull [[META5]], !align [[META6]], !llvm.access.group [[ACC_GRP8]]386// CHECK1-NEXT:    [[TMP24:%.*]] = load volatile double, ptr [[TMP23]], align 8, !llvm.access.group [[ACC_GRP8]]387// CHECK1-NEXT:    store double [[TMP24]], ptr [[G1_CASTED]], align 8, !llvm.access.group [[ACC_GRP8]]388// CHECK1-NEXT:    [[TMP25:%.*]] = load i64, ptr [[G1_CASTED]], align 8, !llvm.access.group [[ACC_GRP8]]389// CHECK1-NEXT:    [[TMP26:%.*]] = load i32, ptr [[SVAR6]], align 4, !llvm.access.group [[ACC_GRP8]]390// CHECK1-NEXT:    store i32 [[TMP26]], ptr [[SVAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP8]]391// CHECK1-NEXT:    [[TMP27:%.*]] = load i64, ptr [[SVAR_CASTED]], align 8, !llvm.access.group [[ACC_GRP8]]392// CHECK1-NEXT:    [[TMP28:%.*]] = load float, ptr [[SFVAR7]], align 4, !llvm.access.group [[ACC_GRP8]]393// CHECK1-NEXT:    store float [[TMP28]], ptr [[SFVAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP8]]394// CHECK1-NEXT:    [[TMP29:%.*]] = load i64, ptr [[SFVAR_CASTED]], align 8, !llvm.access.group [[ACC_GRP8]]395// CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined.omp_outlined, i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP22]], i64 [[TMP25]], i64 [[TMP27]], i64 [[TMP29]]), !llvm.access.group [[ACC_GRP8]]396// CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]397// CHECK1:       omp.inner.for.inc:398// CHECK1-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]399// CHECK1-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP8]]400// CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]401// CHECK1-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]402// CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]403// CHECK1:       omp.inner.for.end:404// CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]405// CHECK1:       omp.loop.exit:406// CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP11]])407// CHECK1-NEXT:    [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4408// CHECK1-NEXT:    [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0409// CHECK1-NEXT:    br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]410// CHECK1:       .omp.final.then:411// CHECK1-NEXT:    store i32 2, ptr [[I]], align 4412// CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]413// CHECK1:       .omp.final.done:414// CHECK1-NEXT:    ret void415//416//417// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined.omp_outlined418// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]]) #[[ATTR2]] {419// CHECK1-NEXT:  entry:420// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8421// CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8422// CHECK1-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8423// CHECK1-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8424// CHECK1-NEXT:    [[G_ADDR:%.*]] = alloca i64, align 8425// CHECK1-NEXT:    [[G1_ADDR:%.*]] = alloca i64, align 8426// CHECK1-NEXT:    [[SVAR_ADDR:%.*]] = alloca i64, align 8427// CHECK1-NEXT:    [[SFVAR_ADDR:%.*]] = alloca i64, align 8428// CHECK1-NEXT:    [[TMP:%.*]] = alloca ptr, align 8429// CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4430// CHECK1-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4431// CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4432// CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4433// CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4434// CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4435// CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4436// CHECK1-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8437// CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8438// CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8439// CHECK1-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8440// CHECK1-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8441// CHECK1-NEXT:    store i64 [[G]], ptr [[G_ADDR]], align 8442// CHECK1-NEXT:    store i64 [[G1]], ptr [[G1_ADDR]], align 8443// CHECK1-NEXT:    store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8444// CHECK1-NEXT:    store i64 [[SFVAR]], ptr [[SFVAR_ADDR]], align 8445// CHECK1-NEXT:    store ptr [[G1_ADDR]], ptr [[TMP]], align 8446// CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4447// CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4448// CHECK1-NEXT:    [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8449// CHECK1-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP0]] to i32450// CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8451// CHECK1-NEXT:    [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32452// CHECK1-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4453// CHECK1-NEXT:    store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4454// CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4455// CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4456// CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8457// CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4458// CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)459// CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4460// CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1461// CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]462// CHECK1:       cond.true:463// CHECK1-NEXT:    br label [[COND_END:%.*]]464// CHECK1:       cond.false:465// CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4466// CHECK1-NEXT:    br label [[COND_END]]467// CHECK1:       cond.end:468// CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]469// CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4470// CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4471// CHECK1-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4472// CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]473// CHECK1:       omp.inner.for.cond:474// CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]]475// CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]]476// CHECK1-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]477// CHECK1-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]478// CHECK1:       omp.inner.for.body:479// CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]480// CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1481// CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]482// CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]]483// CHECK1-NEXT:    store double 1.000000e+00, ptr [[G_ADDR]], align 8, !llvm.access.group [[ACC_GRP12]]484// CHECK1-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]], !llvm.access.group [[ACC_GRP12]]485// CHECK1-NEXT:    store volatile double 1.000000e+00, ptr [[TMP10]], align 8, !llvm.access.group [[ACC_GRP12]]486// CHECK1-NEXT:    store i32 3, ptr [[SVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP12]]487// CHECK1-NEXT:    store float 4.000000e+00, ptr [[SFVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP12]]488// CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0489// CHECK1-NEXT:    store ptr [[G_ADDR]], ptr [[TMP11]], align 8, !llvm.access.group [[ACC_GRP12]]490// CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1491// CHECK1-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]], !llvm.access.group [[ACC_GRP12]]492// CHECK1-NEXT:    store ptr [[TMP13]], ptr [[TMP12]], align 8, !llvm.access.group [[ACC_GRP12]]493// CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2494// CHECK1-NEXT:    store ptr [[SVAR_ADDR]], ptr [[TMP14]], align 8, !llvm.access.group [[ACC_GRP12]]495// CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 3496// CHECK1-NEXT:    store ptr [[SFVAR_ADDR]], ptr [[TMP15]], align 8, !llvm.access.group [[ACC_GRP12]]497// CHECK1-NEXT:    call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group [[ACC_GRP12]]498// CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]499// CHECK1:       omp.body.continue:500// CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]501// CHECK1:       omp.inner.for.inc:502// CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]503// CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP16]], 1504// CHECK1-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]505// CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]506// CHECK1:       omp.inner.for.end:507// CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]508// CHECK1:       omp.loop.exit:509// CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]])510// CHECK1-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4511// CHECK1-NEXT:    [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0512// CHECK1-NEXT:    br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]513// CHECK1:       .omp.final.then:514// CHECK1-NEXT:    store i32 2, ptr [[I]], align 4515// CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]516// CHECK1:       .omp.final.done:517// CHECK1-NEXT:    ret void518//519//520// CHECK3-LABEL: define {{[^@]+}}@main521// CHECK3-SAME: () #[[ATTR0:[0-9]+]] {522// CHECK3-NEXT:  entry:523// CHECK3-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4524// CHECK3-NEXT:    [[G:%.*]] = alloca double, align 8525// CHECK3-NEXT:    [[G1:%.*]] = alloca ptr, align 4526// CHECK3-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4527// CHECK3-NEXT:    store i32 0, ptr [[RETVAL]], align 4528// CHECK3-NEXT:    store ptr [[G]], ptr [[G1]], align 4529// CHECK3-NEXT:    [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0530// CHECK3-NEXT:    store ptr [[G]], ptr [[TMP0]], align 4531// CHECK3-NEXT:    [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1532// CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[G1]], align 4, !nonnull [[META6:![0-9]+]], !align [[META7:![0-9]+]]533// CHECK3-NEXT:    store ptr [[TMP2]], ptr [[TMP1]], align 4534// CHECK3-NEXT:    call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 4 dereferenceable(8) [[REF_TMP]])535// CHECK3-NEXT:    ret i32 0536//537//538// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67539// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[G:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] {540// CHECK3-NEXT:  entry:541// CHECK3-NEXT:    [[G_ADDR:%.*]] = alloca ptr, align 4542// CHECK3-NEXT:    [[G1_ADDR:%.*]] = alloca ptr, align 4543// CHECK3-NEXT:    [[SVAR_ADDR:%.*]] = alloca i32, align 4544// CHECK3-NEXT:    [[SFVAR_ADDR:%.*]] = alloca i32, align 4545// CHECK3-NEXT:    [[TMP:%.*]] = alloca ptr, align 4546// CHECK3-NEXT:    [[G2:%.*]] = alloca double, align 8547// CHECK3-NEXT:    [[G13:%.*]] = alloca double, align 8548// CHECK3-NEXT:    [[_TMP4:%.*]] = alloca ptr, align 4549// CHECK3-NEXT:    store ptr [[G]], ptr [[G_ADDR]], align 4550// CHECK3-NEXT:    store ptr [[G1]], ptr [[G1_ADDR]], align 4551// CHECK3-NEXT:    store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4552// CHECK3-NEXT:    store i32 [[SFVAR]], ptr [[SFVAR_ADDR]], align 4553// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4, !nonnull [[META6]], !align [[META7]]554// CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 4, !nonnull [[META6]], !align [[META7]]555// CHECK3-NEXT:    store ptr [[TMP1]], ptr [[TMP]], align 4556// CHECK3-NEXT:    [[TMP2:%.*]] = load double, ptr [[TMP0]], align 8557// CHECK3-NEXT:    store double [[TMP2]], ptr [[G2]], align 8558// CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META6]], !align [[META7]]559// CHECK3-NEXT:    [[TMP4:%.*]] = load volatile double, ptr [[TMP3]], align 4560// CHECK3-NEXT:    store double [[TMP4]], ptr [[G13]], align 8561// CHECK3-NEXT:    store ptr [[G13]], ptr [[_TMP4]], align 4562// CHECK3-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[_TMP4]], align 4, !nonnull [[META6]], !align [[META7]]563// CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined, ptr [[G2]], ptr [[TMP5]], ptr [[SVAR_ADDR]], ptr [[SFVAR_ADDR]])564// CHECK3-NEXT:    ret void565//566//567// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined568// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[G:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] {569// CHECK3-NEXT:  entry:570// CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4571// CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4572// CHECK3-NEXT:    [[G_ADDR:%.*]] = alloca ptr, align 4573// CHECK3-NEXT:    [[G1_ADDR:%.*]] = alloca ptr, align 4574// CHECK3-NEXT:    [[SVAR_ADDR:%.*]] = alloca ptr, align 4575// CHECK3-NEXT:    [[SFVAR_ADDR:%.*]] = alloca ptr, align 4576// CHECK3-NEXT:    [[TMP:%.*]] = alloca ptr, align 4577// CHECK3-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 4578// CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4579// CHECK3-NEXT:    [[_TMP2:%.*]] = alloca i32, align 4580// CHECK3-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4581// CHECK3-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4582// CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4583// CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4584// CHECK3-NEXT:    [[G3:%.*]] = alloca double, align 8585// CHECK3-NEXT:    [[G14:%.*]] = alloca double, align 8586// CHECK3-NEXT:    [[_TMP5:%.*]] = alloca ptr, align 4587// CHECK3-NEXT:    [[SVAR6:%.*]] = alloca i32, align 4588// CHECK3-NEXT:    [[SFVAR7:%.*]] = alloca float, align 4589// CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4590// CHECK3-NEXT:    [[G1_CASTED:%.*]] = alloca i32, align 4591// CHECK3-NEXT:    [[SVAR_CASTED:%.*]] = alloca i32, align 4592// CHECK3-NEXT:    [[SFVAR_CASTED:%.*]] = alloca i32, align 4593// CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4594// CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4595// CHECK3-NEXT:    store ptr [[G]], ptr [[G_ADDR]], align 4596// CHECK3-NEXT:    store ptr [[G1]], ptr [[G1_ADDR]], align 4597// CHECK3-NEXT:    store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 4598// CHECK3-NEXT:    store ptr [[SFVAR]], ptr [[SFVAR_ADDR]], align 4599// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4, !nonnull [[META6]], !align [[META7]]600// CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 4, !nonnull [[META6]], !align [[META7]]601// CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 4, !nonnull [[META6]], !align [[META7]]602// CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[SFVAR_ADDR]], align 4, !nonnull [[META6]], !align [[META7]]603// CHECK3-NEXT:    store ptr [[TMP1]], ptr [[TMP]], align 4604// CHECK3-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META6]], !align [[META7]]605// CHECK3-NEXT:    store ptr [[TMP4]], ptr [[_TMP1]], align 4606// CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4607// CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_COMB_UB]], align 4608// CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4609// CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4610// CHECK3-NEXT:    [[TMP5:%.*]] = load double, ptr [[TMP0]], align 8611// CHECK3-NEXT:    store double [[TMP5]], ptr [[G3]], align 8612// CHECK3-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 4, !nonnull [[META6]], !align [[META7]]613// CHECK3-NEXT:    [[TMP7:%.*]] = load double, ptr [[TMP6]], align 4614// CHECK3-NEXT:    store double [[TMP7]], ptr [[G14]], align 8615// CHECK3-NEXT:    store ptr [[G14]], ptr [[_TMP5]], align 4616// CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP2]], align 4617// CHECK3-NEXT:    store i32 [[TMP8]], ptr [[SVAR6]], align 4618// CHECK3-NEXT:    [[TMP9:%.*]] = load float, ptr [[TMP3]], align 4619// CHECK3-NEXT:    store float [[TMP9]], ptr [[SFVAR7]], align 4620// CHECK3-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4621// CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4622// CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)623// CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4624// CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1625// CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]626// CHECK3:       cond.true:627// CHECK3-NEXT:    br label [[COND_END:%.*]]628// CHECK3:       cond.false:629// CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4630// CHECK3-NEXT:    br label [[COND_END]]631// CHECK3:       cond.end:632// CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]633// CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4634// CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4635// CHECK3-NEXT:    store i32 [[TMP14]], ptr [[DOTOMP_IV]], align 4636// CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]637// CHECK3:       omp.inner.for.cond:638// CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8:![0-9]+]]639// CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP8]]640// CHECK3-NEXT:    [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]641// CHECK3-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]642// CHECK3:       omp.inner.for.body:643// CHECK3-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP8]]644// CHECK3-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP8]]645// CHECK3-NEXT:    [[TMP19:%.*]] = load ptr, ptr [[_TMP5]], align 4, !nonnull [[META6]], !align [[META7]], !llvm.access.group [[ACC_GRP8]]646// CHECK3-NEXT:    [[TMP20:%.*]] = load volatile double, ptr [[TMP19]], align 4, !llvm.access.group [[ACC_GRP8]]647// CHECK3-NEXT:    store double [[TMP20]], ptr [[G1_CASTED]], align 4, !llvm.access.group [[ACC_GRP8]]648// CHECK3-NEXT:    [[TMP21:%.*]] = load i32, ptr [[G1_CASTED]], align 4, !llvm.access.group [[ACC_GRP8]]649// CHECK3-NEXT:    [[TMP22:%.*]] = load i32, ptr [[SVAR6]], align 4, !llvm.access.group [[ACC_GRP8]]650// CHECK3-NEXT:    store i32 [[TMP22]], ptr [[SVAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP8]]651// CHECK3-NEXT:    [[TMP23:%.*]] = load i32, ptr [[SVAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP8]]652// CHECK3-NEXT:    [[TMP24:%.*]] = load float, ptr [[SFVAR7]], align 4, !llvm.access.group [[ACC_GRP8]]653// CHECK3-NEXT:    store float [[TMP24]], ptr [[SFVAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP8]]654// CHECK3-NEXT:    [[TMP25:%.*]] = load i32, ptr [[SFVAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP8]]655// CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined.omp_outlined, i32 [[TMP17]], i32 [[TMP18]], ptr [[G3]], i32 [[TMP21]], i32 [[TMP23]], i32 [[TMP25]]), !llvm.access.group [[ACC_GRP8]]656// CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]657// CHECK3:       omp.inner.for.inc:658// CHECK3-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]659// CHECK3-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP8]]660// CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP26]], [[TMP27]]661// CHECK3-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]662// CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]663// CHECK3:       omp.inner.for.end:664// CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]665// CHECK3:       omp.loop.exit:666// CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP11]])667// CHECK3-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4668// CHECK3-NEXT:    [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0669// CHECK3-NEXT:    br i1 [[TMP29]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]670// CHECK3:       .omp.final.then:671// CHECK3-NEXT:    store i32 2, ptr [[I]], align 4672// CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]673// CHECK3:       .omp.final.done:674// CHECK3-NEXT:    ret void675//676//677// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined.omp_outlined678// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[G:%.*]], i32 noundef [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]]) #[[ATTR2]] {679// CHECK3-NEXT:  entry:680// CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4681// CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4682// CHECK3-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4683// CHECK3-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4684// CHECK3-NEXT:    [[G_ADDR:%.*]] = alloca ptr, align 4685// CHECK3-NEXT:    [[G1_ADDR:%.*]] = alloca i32, align 4686// CHECK3-NEXT:    [[SVAR_ADDR:%.*]] = alloca i32, align 4687// CHECK3-NEXT:    [[SFVAR_ADDR:%.*]] = alloca i32, align 4688// CHECK3-NEXT:    [[TMP:%.*]] = alloca ptr, align 4689// CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4690// CHECK3-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4691// CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4692// CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4693// CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4694// CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4695// CHECK3-NEXT:    [[G2:%.*]] = alloca double, align 8696// CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4697// CHECK3-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 4698// CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4699// CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4700// CHECK3-NEXT:    store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4701// CHECK3-NEXT:    store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4702// CHECK3-NEXT:    store ptr [[G]], ptr [[G_ADDR]], align 4703// CHECK3-NEXT:    store i32 [[G1]], ptr [[G1_ADDR]], align 4704// CHECK3-NEXT:    store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4705// CHECK3-NEXT:    store i32 [[SFVAR]], ptr [[SFVAR_ADDR]], align 4706// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4, !nonnull [[META6]], !align [[META7]]707// CHECK3-NEXT:    store ptr [[G1_ADDR]], ptr [[TMP]], align 4708// CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4709// CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4710// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4711// CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4712// CHECK3-NEXT:    store i32 [[TMP1]], ptr [[DOTOMP_LB]], align 4713// CHECK3-NEXT:    store i32 [[TMP2]], ptr [[DOTOMP_UB]], align 4714// CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4715// CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4716// CHECK3-NEXT:    [[TMP3:%.*]] = load double, ptr [[TMP0]], align 8717// CHECK3-NEXT:    store double [[TMP3]], ptr [[G2]], align 8718// CHECK3-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4719// CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4720// CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)721// CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4722// CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1723// CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]724// CHECK3:       cond.true:725// CHECK3-NEXT:    br label [[COND_END:%.*]]726// CHECK3:       cond.false:727// CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4728// CHECK3-NEXT:    br label [[COND_END]]729// CHECK3:       cond.end:730// CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]731// CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4732// CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4733// CHECK3-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4734// CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]735// CHECK3:       omp.inner.for.cond:736// CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]]737// CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]]738// CHECK3-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]739// CHECK3-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]740// CHECK3:       omp.inner.for.body:741// CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]742// CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1743// CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]744// CHECK3-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]]745// CHECK3-NEXT:    store double 1.000000e+00, ptr [[G2]], align 8, !llvm.access.group [[ACC_GRP12]]746// CHECK3-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META6]], !align [[META7]], !llvm.access.group [[ACC_GRP12]]747// CHECK3-NEXT:    store volatile double 1.000000e+00, ptr [[TMP12]], align 4, !llvm.access.group [[ACC_GRP12]]748// CHECK3-NEXT:    store i32 3, ptr [[SVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP12]]749// CHECK3-NEXT:    store float 4.000000e+00, ptr [[SFVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP12]]750// CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0751// CHECK3-NEXT:    store ptr [[G2]], ptr [[TMP13]], align 4, !llvm.access.group [[ACC_GRP12]]752// CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1753// CHECK3-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META6]], !align [[META7]], !llvm.access.group [[ACC_GRP12]]754// CHECK3-NEXT:    store ptr [[TMP15]], ptr [[TMP14]], align 4, !llvm.access.group [[ACC_GRP12]]755// CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2756// CHECK3-NEXT:    store ptr [[SVAR_ADDR]], ptr [[TMP16]], align 4, !llvm.access.group [[ACC_GRP12]]757// CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 3758// CHECK3-NEXT:    store ptr [[SFVAR_ADDR]], ptr [[TMP17]], align 4, !llvm.access.group [[ACC_GRP12]]759// CHECK3-NEXT:    call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group [[ACC_GRP12]]760// CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]761// CHECK3:       omp.body.continue:762// CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]763// CHECK3:       omp.inner.for.inc:764// CHECK3-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]765// CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP18]], 1766// CHECK3-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]767// CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]768// CHECK3:       omp.inner.for.end:769// CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]770// CHECK3:       omp.loop.exit:771// CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP5]])772// CHECK3-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4773// CHECK3-NEXT:    [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0774// CHECK3-NEXT:    br i1 [[TMP20]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]775// CHECK3:       .omp.final.then:776// CHECK3-NEXT:    store i32 2, ptr [[I]], align 4777// CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]778// CHECK3:       .omp.final.done:779// CHECK3-NEXT:    ret void780//781//782// CHECK5-LABEL: define {{[^@]+}}@main783// CHECK5-SAME: () #[[ATTR0:[0-9]+]] {784// CHECK5-NEXT:  entry:785// CHECK5-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4786// CHECK5-NEXT:    [[G:%.*]] = alloca double, align 8787// CHECK5-NEXT:    [[G1:%.*]] = alloca ptr, align 8788// CHECK5-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8789// CHECK5-NEXT:    store i32 0, ptr [[RETVAL]], align 4790// CHECK5-NEXT:    store ptr [[G]], ptr [[G1]], align 8791// CHECK5-NEXT:    [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0792// CHECK5-NEXT:    store ptr [[G]], ptr [[TMP0]], align 8793// CHECK5-NEXT:    [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1794// CHECK5-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[G1]], align 8, !nonnull [[META2:![0-9]+]], !align [[META3:![0-9]+]]795// CHECK5-NEXT:    store ptr [[TMP2]], ptr [[TMP1]], align 8796// CHECK5-NEXT:    call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP]])797// CHECK5-NEXT:    ret i32 0798//799//800// CHECK6-LABEL: define {{[^@]+}}@main801// CHECK6-SAME: () #[[ATTR0:[0-9]+]] {802// CHECK6-NEXT:  entry:803// CHECK6-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4804// CHECK6-NEXT:    [[G:%.*]] = alloca double, align 8805// CHECK6-NEXT:    [[G1:%.*]] = alloca ptr, align 4806// CHECK6-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4807// CHECK6-NEXT:    store i32 0, ptr [[RETVAL]], align 4808// CHECK6-NEXT:    store ptr [[G]], ptr [[G1]], align 4809// CHECK6-NEXT:    [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0810// CHECK6-NEXT:    store ptr [[G]], ptr [[TMP0]], align 4811// CHECK6-NEXT:    [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1812// CHECK6-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[G1]], align 4, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]]813// CHECK6-NEXT:    store ptr [[TMP2]], ptr [[TMP1]], align 4814// CHECK6-NEXT:    call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 4 dereferenceable(8) [[REF_TMP]])815// CHECK6-NEXT:    ret i32 0816//817//818// CHECK8-LABEL: define {{[^@]+}}@main819// CHECK8-SAME: () #[[ATTR0:[0-9]+]] {820// CHECK8-NEXT:  entry:821// CHECK8-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4822// CHECK8-NEXT:    [[G:%.*]] = alloca double, align 8823// CHECK8-NEXT:    [[G1:%.*]] = alloca ptr, align 8824// CHECK8-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4825// CHECK8-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4826// CHECK8-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4827// CHECK8-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4828// CHECK8-NEXT:    [[VAR:%.*]] = alloca ptr, align 8829// CHECK8-NEXT:    [[TMP:%.*]] = alloca ptr, align 8830// CHECK8-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 8831// CHECK8-NEXT:    [[SVAR_CASTED:%.*]] = alloca i64, align 8832// CHECK8-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8833// CHECK8-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8834// CHECK8-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8835// CHECK8-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4836// CHECK8-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8837// CHECK8-NEXT:    store i32 0, ptr [[RETVAL]], align 4838// CHECK8-NEXT:    store ptr [[G]], ptr [[G1]], align 8839// CHECK8-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])840// CHECK8-NEXT:    store i32 0, ptr [[T_VAR]], align 4841// CHECK8-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i64 8, i1 false)842// CHECK8-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], float noundef 1.000000e+00)843// CHECK8-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i64 1844// CHECK8-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00)845// CHECK8-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 8846// CHECK8-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8, !nonnull [[META7:![0-9]+]], !align [[META8:![0-9]+]]847// CHECK8-NEXT:    store ptr [[TMP0]], ptr [[TMP]], align 8848// CHECK8-NEXT:    [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4849// CHECK8-NEXT:    store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4850// CHECK8-NEXT:    [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8851// CHECK8-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]852// CHECK8-NEXT:    [[TMP4:%.*]] = load i32, ptr @_ZZ4mainE4svar, align 4853// CHECK8-NEXT:    store i32 [[TMP4]], ptr [[SVAR_CASTED]], align 4854// CHECK8-NEXT:    [[TMP5:%.*]] = load i64, ptr [[SVAR_CASTED]], align 8855// CHECK8-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]856// CHECK8-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]857// CHECK8-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0858// CHECK8-NEXT:    store i64 [[TMP2]], ptr [[TMP8]], align 8859// CHECK8-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0860// CHECK8-NEXT:    store i64 [[TMP2]], ptr [[TMP9]], align 8861// CHECK8-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0862// CHECK8-NEXT:    store ptr null, ptr [[TMP10]], align 8863// CHECK8-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1864// CHECK8-NEXT:    store ptr [[VEC]], ptr [[TMP11]], align 8865// CHECK8-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1866// CHECK8-NEXT:    store ptr [[VEC]], ptr [[TMP12]], align 8867// CHECK8-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1868// CHECK8-NEXT:    store ptr null, ptr [[TMP13]], align 8869// CHECK8-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2870// CHECK8-NEXT:    store ptr [[S_ARR]], ptr [[TMP14]], align 8871// CHECK8-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2872// CHECK8-NEXT:    store ptr [[S_ARR]], ptr [[TMP15]], align 8873// CHECK8-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2874// CHECK8-NEXT:    store ptr null, ptr [[TMP16]], align 8875// CHECK8-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3876// CHECK8-NEXT:    store ptr [[TMP6]], ptr [[TMP17]], align 8877// CHECK8-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3878// CHECK8-NEXT:    store ptr [[TMP7]], ptr [[TMP18]], align 8879// CHECK8-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3880// CHECK8-NEXT:    store ptr null, ptr [[TMP19]], align 8881// CHECK8-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4882// CHECK8-NEXT:    store i64 [[TMP5]], ptr [[TMP20]], align 8883// CHECK8-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4884// CHECK8-NEXT:    store i64 [[TMP5]], ptr [[TMP21]], align 8885// CHECK8-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4886// CHECK8-NEXT:    store ptr null, ptr [[TMP22]], align 8887// CHECK8-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0888// CHECK8-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0889// CHECK8-NEXT:    [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0890// CHECK8-NEXT:    store i32 3, ptr [[TMP25]], align 4891// CHECK8-NEXT:    [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1892// CHECK8-NEXT:    store i32 5, ptr [[TMP26]], align 4893// CHECK8-NEXT:    [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2894// CHECK8-NEXT:    store ptr [[TMP23]], ptr [[TMP27]], align 8895// CHECK8-NEXT:    [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3896// CHECK8-NEXT:    store ptr [[TMP24]], ptr [[TMP28]], align 8897// CHECK8-NEXT:    [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4898// CHECK8-NEXT:    store ptr @.offload_sizes, ptr [[TMP29]], align 8899// CHECK8-NEXT:    [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5900// CHECK8-NEXT:    store ptr @.offload_maptypes, ptr [[TMP30]], align 8901// CHECK8-NEXT:    [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6902// CHECK8-NEXT:    store ptr null, ptr [[TMP31]], align 8903// CHECK8-NEXT:    [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7904// CHECK8-NEXT:    store ptr null, ptr [[TMP32]], align 8905// CHECK8-NEXT:    [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8906// CHECK8-NEXT:    store i64 2, ptr [[TMP33]], align 8907// CHECK8-NEXT:    [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9908// CHECK8-NEXT:    store i64 0, ptr [[TMP34]], align 8909// CHECK8-NEXT:    [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10910// CHECK8-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP35]], align 4911// CHECK8-NEXT:    [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11912// CHECK8-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP36]], align 4913// CHECK8-NEXT:    [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12914// CHECK8-NEXT:    store i32 0, ptr [[TMP37]], align 4915// CHECK8-NEXT:    [[TMP38:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l138.region_id, ptr [[KERNEL_ARGS]])916// CHECK8-NEXT:    [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0917// CHECK8-NEXT:    br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]918// CHECK8:       omp_offload.failed:919// CHECK8-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l138(i64 [[TMP2]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP3]], i64 [[TMP5]]) #[[ATTR4:[0-9]+]]920// CHECK8-NEXT:    br label [[OMP_OFFLOAD_CONT]]921// CHECK8:       omp_offload.cont:922// CHECK8-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()923// CHECK8-NEXT:    store i32 [[CALL]], ptr [[RETVAL]], align 4924// CHECK8-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0925// CHECK8-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2926// CHECK8-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]927// CHECK8:       arraydestroy.body:928// CHECK8-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP40]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]929// CHECK8-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1930// CHECK8-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]931// CHECK8-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]932// CHECK8-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]933// CHECK8:       arraydestroy.done2:934// CHECK8-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]935// CHECK8-NEXT:    [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4936// CHECK8-NEXT:    ret i32 [[TMP41]]937//938//939// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev940// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {941// CHECK8-NEXT:  entry:942// CHECK8-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8943// CHECK8-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8944// CHECK8-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8945// CHECK8-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])946// CHECK8-NEXT:    ret void947//948//949// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef950// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {951// CHECK8-NEXT:  entry:952// CHECK8-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8953// CHECK8-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4954// CHECK8-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8955// CHECK8-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4956// CHECK8-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8957// CHECK8-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4958// CHECK8-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])959// CHECK8-NEXT:    ret void960//961//962// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l138963// CHECK8-SAME: (i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] {964// CHECK8-NEXT:  entry:965// CHECK8-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8966// CHECK8-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 8967// CHECK8-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 8968// CHECK8-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 8969// CHECK8-NEXT:    [[SVAR_ADDR:%.*]] = alloca i64, align 8970// CHECK8-NEXT:    [[TMP:%.*]] = alloca ptr, align 8971// CHECK8-NEXT:    store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8972// CHECK8-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 8973// CHECK8-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8974// CHECK8-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 8975// CHECK8-NEXT:    store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8976// CHECK8-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]977// CHECK8-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]978// CHECK8-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]979// CHECK8-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 8980// CHECK8-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]981// CHECK8-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l138.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP3]], ptr [[SVAR_ADDR]])982// CHECK8-NEXT:    ret void983//984//985// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l138.omp_outlined986// CHECK8-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] {987// CHECK8-NEXT:  entry:988// CHECK8-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8989// CHECK8-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8990// CHECK8-NEXT:    [[T_VAR_ADDR:%.*]] = alloca ptr, align 8991// CHECK8-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 8992// CHECK8-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 8993// CHECK8-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 8994// CHECK8-NEXT:    [[SVAR_ADDR:%.*]] = alloca ptr, align 8995// CHECK8-NEXT:    [[TMP:%.*]] = alloca ptr, align 8996// CHECK8-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8997// CHECK8-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4998// CHECK8-NEXT:    [[_TMP2:%.*]] = alloca i32, align 4999// CHECK8-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 41000// CHECK8-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 41001// CHECK8-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41002// CHECK8-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41003// CHECK8-NEXT:    [[T_VAR3:%.*]] = alloca i32, align 41004// CHECK8-NEXT:    [[VEC4:%.*]] = alloca [2 x i32], align 41005// CHECK8-NEXT:    [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 41006// CHECK8-NEXT:    [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 41007// CHECK8-NEXT:    [[_TMP8:%.*]] = alloca ptr, align 81008// CHECK8-NEXT:    [[SVAR9:%.*]] = alloca i32, align 41009// CHECK8-NEXT:    [[I:%.*]] = alloca i32, align 41010// CHECK8-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 81011// CHECK8-NEXT:    [[SVAR_CASTED:%.*]] = alloca i64, align 81012// CHECK8-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81013// CHECK8-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81014// CHECK8-NEXT:    store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 81015// CHECK8-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 81016// CHECK8-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 81017// CHECK8-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 81018// CHECK8-NEXT:    store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 81019// CHECK8-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]1020// CHECK8-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]1021// CHECK8-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]1022// CHECK8-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]1023// CHECK8-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]1024// CHECK8-NEXT:    store ptr [[TMP3]], ptr [[TMP]], align 81025// CHECK8-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]1026// CHECK8-NEXT:    store ptr [[TMP5]], ptr [[_TMP1]], align 81027// CHECK8-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 41028// CHECK8-NEXT:    store i32 1, ptr [[DOTOMP_COMB_UB]], align 41029// CHECK8-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 41030// CHECK8-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 41031// CHECK8-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP0]], align 41032// CHECK8-NEXT:    store i32 [[TMP6]], ptr [[T_VAR3]], align 41033// CHECK8-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC4]], ptr align 4 [[TMP1]], i64 8, i1 false)1034// CHECK8-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 01035// CHECK8-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 21036// CHECK8-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP7]]1037// CHECK8-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]1038// CHECK8:       omp.arraycpy.body:1039// CHECK8-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1040// CHECK8-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1041// CHECK8-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i64 4, i1 false)1042// CHECK8-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 11043// CHECK8-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 11044// CHECK8-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP7]]1045// CHECK8-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]]1046// CHECK8:       omp.arraycpy.done6:1047// CHECK8-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META7]], !align [[META8]]1048// CHECK8-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VAR7]], ptr align 4 [[TMP8]], i64 4, i1 false)1049// CHECK8-NEXT:    store ptr [[VAR7]], ptr [[_TMP8]], align 81050// CHECK8-NEXT:    [[TMP9:%.*]] = load i32, ptr [[TMP4]], align 41051// CHECK8-NEXT:    store i32 [[TMP9]], ptr [[SVAR9]], align 41052// CHECK8-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81053// CHECK8-NEXT:    [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 41054// CHECK8-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1055// CHECK8-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 41056// CHECK8-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 11057// CHECK8-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1058// CHECK8:       cond.true:1059// CHECK8-NEXT:    br label [[COND_END:%.*]]1060// CHECK8:       cond.false:1061// CHECK8-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 41062// CHECK8-NEXT:    br label [[COND_END]]1063// CHECK8:       cond.end:1064// CHECK8-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]1065// CHECK8-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 41066// CHECK8-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 41067// CHECK8-NEXT:    store i32 [[TMP14]], ptr [[DOTOMP_IV]], align 41068// CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]1069// CHECK8:       omp.inner.for.cond:1070// CHECK8-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]]1071// CHECK8-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP9]]1072// CHECK8-NEXT:    [[CMP10:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]1073// CHECK8-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]1074// CHECK8:       omp.inner.for.cond.cleanup:1075// CHECK8-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]1076// CHECK8:       omp.inner.for.body:1077// CHECK8-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP9]]1078// CHECK8-NEXT:    [[TMP18:%.*]] = zext i32 [[TMP17]] to i641079// CHECK8-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP9]]1080// CHECK8-NEXT:    [[TMP20:%.*]] = zext i32 [[TMP19]] to i641081// CHECK8-NEXT:    [[TMP21:%.*]] = load i32, ptr [[T_VAR3]], align 4, !llvm.access.group [[ACC_GRP9]]1082// CHECK8-NEXT:    store i32 [[TMP21]], ptr [[T_VAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP9]]1083// CHECK8-NEXT:    [[TMP22:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8, !llvm.access.group [[ACC_GRP9]]1084// CHECK8-NEXT:    [[TMP23:%.*]] = load ptr, ptr [[_TMP8]], align 8, !nonnull [[META7]], !align [[META8]], !llvm.access.group [[ACC_GRP9]]1085// CHECK8-NEXT:    [[TMP24:%.*]] = load i32, ptr [[SVAR9]], align 4, !llvm.access.group [[ACC_GRP9]]1086// CHECK8-NEXT:    store i32 [[TMP24]], ptr [[SVAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP9]]1087// CHECK8-NEXT:    [[TMP25:%.*]] = load i64, ptr [[SVAR_CASTED]], align 8, !llvm.access.group [[ACC_GRP9]]1088// CHECK8-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 7, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l138.omp_outlined.omp_outlined, i64 [[TMP18]], i64 [[TMP20]], ptr [[VEC4]], i64 [[TMP22]], ptr [[S_ARR5]], ptr [[TMP23]], i64 [[TMP25]]), !llvm.access.group [[ACC_GRP9]]1089// CHECK8-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]1090// CHECK8:       omp.inner.for.inc:1091// CHECK8-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]1092// CHECK8-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP9]]1093// CHECK8-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP26]], [[TMP27]]1094// CHECK8-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]1095// CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]1096// CHECK8:       omp.inner.for.end:1097// CHECK8-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]1098// CHECK8:       omp.loop.exit:1099// CHECK8-NEXT:    [[TMP28:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81100// CHECK8-NEXT:    [[TMP29:%.*]] = load i32, ptr [[TMP28]], align 41101// CHECK8-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP29]])1102// CHECK8-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 41103// CHECK8-NEXT:    [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 01104// CHECK8-NEXT:    br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]1105// CHECK8:       .omp.final.then:1106// CHECK8-NEXT:    store i32 2, ptr [[I]], align 41107// CHECK8-NEXT:    br label [[DOTOMP_FINAL_DONE]]1108// CHECK8:       .omp.final.done:1109// CHECK8-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]]1110// CHECK8-NEXT:    [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 01111// CHECK8-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i64 21112// CHECK8-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]1113// CHECK8:       arraydestroy.body:1114// CHECK8-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP32]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1115// CHECK8-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -11116// CHECK8-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]1117// CHECK8-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]]1118// CHECK8-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]]1119// CHECK8:       arraydestroy.done12:1120// CHECK8-NEXT:    ret void1121//1122//1123// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l138.omp_outlined.omp_outlined1124// CHECK8-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3]] {1125// CHECK8-NEXT:  entry:1126// CHECK8-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81127// CHECK8-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81128// CHECK8-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 81129// CHECK8-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 81130// CHECK8-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 81131// CHECK8-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 81132// CHECK8-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 81133// CHECK8-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 81134// CHECK8-NEXT:    [[SVAR_ADDR:%.*]] = alloca i64, align 81135// CHECK8-NEXT:    [[TMP:%.*]] = alloca ptr, align 81136// CHECK8-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 41137// CHECK8-NEXT:    [[_TMP1:%.*]] = alloca i32, align 41138// CHECK8-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 41139// CHECK8-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 41140// CHECK8-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41141// CHECK8-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41142// CHECK8-NEXT:    [[VEC3:%.*]] = alloca [2 x i32], align 41143// CHECK8-NEXT:    [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 41144// CHECK8-NEXT:    [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 41145// CHECK8-NEXT:    [[_TMP7:%.*]] = alloca ptr, align 81146// CHECK8-NEXT:    [[I:%.*]] = alloca i32, align 41147// CHECK8-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81148// CHECK8-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81149// CHECK8-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 81150// CHECK8-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 81151// CHECK8-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 81152// CHECK8-NEXT:    store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 81153// CHECK8-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 81154// CHECK8-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 81155// CHECK8-NEXT:    store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 81156// CHECK8-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]1157// CHECK8-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]1158// CHECK8-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]1159// CHECK8-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 81160// CHECK8-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 41161// CHECK8-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 41162// CHECK8-NEXT:    [[TMP3:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 81163// CHECK8-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP3]] to i321164// CHECK8-NEXT:    [[TMP4:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 81165// CHECK8-NEXT:    [[CONV2:%.*]] = trunc i64 [[TMP4]] to i321166// CHECK8-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 41167// CHECK8-NEXT:    store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 41168// CHECK8-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 41169// CHECK8-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 41170// CHECK8-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC3]], ptr align 4 [[TMP0]], i64 8, i1 false)1171// CHECK8-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 01172// CHECK8-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 21173// CHECK8-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]]1174// CHECK8-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE5:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]1175// CHECK8:       omp.arraycpy.body:1176// CHECK8-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1177// CHECK8-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1178// CHECK8-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i64 4, i1 false)1179// CHECK8-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 11180// CHECK8-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 11181// CHECK8-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]]1182// CHECK8-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_BODY]]1183// CHECK8:       omp.arraycpy.done5:1184// CHECK8-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]1185// CHECK8-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VAR6]], ptr align 4 [[TMP6]], i64 4, i1 false)1186// CHECK8-NEXT:    store ptr [[VAR6]], ptr [[_TMP7]], align 81187// CHECK8-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81188// CHECK8-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 41189// CHECK8-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP8]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1190// CHECK8-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41191// CHECK8-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 11192// CHECK8-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1193// CHECK8:       cond.true:1194// CHECK8-NEXT:    br label [[COND_END:%.*]]1195// CHECK8:       cond.false:1196// CHECK8-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41197// CHECK8-NEXT:    br label [[COND_END]]1198// CHECK8:       cond.end:1199// CHECK8-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]1200// CHECK8-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 41201// CHECK8-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41202// CHECK8-NEXT:    store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 41203// CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]1204// CHECK8:       omp.inner.for.cond:1205// CHECK8-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13:![0-9]+]]1206// CHECK8-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP13]]1207// CHECK8-NEXT:    [[CMP8:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]1208// CHECK8-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]1209// CHECK8:       omp.inner.for.cond.cleanup:1210// CHECK8-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]1211// CHECK8:       omp.inner.for.body:1212// CHECK8-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]1213// CHECK8-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP14]], 11214// CHECK8-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]1215// CHECK8-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]]1216// CHECK8-NEXT:    [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP13]]1217// CHECK8-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]]1218// CHECK8-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i641219// CHECK8-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]]1220// CHECK8-NEXT:    store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP13]]1221// CHECK8-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 8, !nonnull [[META7]], !align [[META8]], !llvm.access.group [[ACC_GRP13]]1222// CHECK8-NEXT:    [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]]1223// CHECK8-NEXT:    [[IDXPROM9:%.*]] = sext i32 [[TMP18]] to i641224// CHECK8-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM9]]1225// CHECK8-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP17]], i64 4, i1 false), !llvm.access.group [[ACC_GRP13]]1226// CHECK8-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]1227// CHECK8:       omp.body.continue:1228// CHECK8-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]1229// CHECK8:       omp.inner.for.inc:1230// CHECK8-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]1231// CHECK8-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP19]], 11232// CHECK8-NEXT:    store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]1233// CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]1234// CHECK8:       omp.inner.for.end:1235// CHECK8-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]1236// CHECK8:       omp.loop.exit:1237// CHECK8-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81238// CHECK8-NEXT:    [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 41239// CHECK8-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]])1240// CHECK8-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 41241// CHECK8-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 01242// CHECK8-NEXT:    br i1 [[TMP23]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]1243// CHECK8:       .omp.final.then:1244// CHECK8-NEXT:    store i32 2, ptr [[I]], align 41245// CHECK8-NEXT:    br label [[DOTOMP_FINAL_DONE]]1246// CHECK8:       .omp.final.done:1247// CHECK8-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]]1248// CHECK8-NEXT:    [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 01249// CHECK8-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN12]], i64 21250// CHECK8-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]1251// CHECK8:       arraydestroy.body:1252// CHECK8-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP24]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1253// CHECK8-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -11254// CHECK8-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]1255// CHECK8-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]]1256// CHECK8-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]]1257// CHECK8:       arraydestroy.done13:1258// CHECK8-NEXT:    ret void1259//1260//1261// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev1262// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1263// CHECK8-NEXT:  entry:1264// CHECK8-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81265// CHECK8-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81266// CHECK8-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81267// CHECK8-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]1268// CHECK8-NEXT:    ret void1269//1270//1271// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v1272// CHECK8-SAME: () #[[ATTR1]] comdat {1273// CHECK8-NEXT:  entry:1274// CHECK8-NEXT:    [[RETVAL:%.*]] = alloca i32, align 41275// CHECK8-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 41276// CHECK8-NEXT:    [[T_VAR:%.*]] = alloca i32, align 41277// CHECK8-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 41278// CHECK8-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 41279// CHECK8-NEXT:    [[VAR:%.*]] = alloca ptr, align 81280// CHECK8-NEXT:    [[TMP:%.*]] = alloca ptr, align 81281// CHECK8-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 81282// CHECK8-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 81283// CHECK8-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 81284// CHECK8-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 81285// CHECK8-NEXT:    [[_TMP1:%.*]] = alloca i32, align 41286// CHECK8-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81287// CHECK8-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])1288// CHECK8-NEXT:    store i32 0, ptr [[T_VAR]], align 41289// CHECK8-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)1290// CHECK8-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef signext 1)1291// CHECK8-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 11292// CHECK8-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2)1293// CHECK8-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 81294// CHECK8-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8, !nonnull [[META7]], !align [[META8]]1295// CHECK8-NEXT:    store ptr [[TMP0]], ptr [[TMP]], align 81296// CHECK8-NEXT:    [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 41297// CHECK8-NEXT:    store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 41298// CHECK8-NEXT:    [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 81299// CHECK8-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]1300// CHECK8-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]1301// CHECK8-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]1302// CHECK8-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01303// CHECK8-NEXT:    store i64 [[TMP2]], ptr [[TMP6]], align 81304// CHECK8-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01305// CHECK8-NEXT:    store i64 [[TMP2]], ptr [[TMP7]], align 81306// CHECK8-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 01307// CHECK8-NEXT:    store ptr null, ptr [[TMP8]], align 81308// CHECK8-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 11309// CHECK8-NEXT:    store ptr [[VEC]], ptr [[TMP9]], align 81310// CHECK8-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 11311// CHECK8-NEXT:    store ptr [[VEC]], ptr [[TMP10]], align 81312// CHECK8-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 11313// CHECK8-NEXT:    store ptr null, ptr [[TMP11]], align 81314// CHECK8-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 21315// CHECK8-NEXT:    store ptr [[S_ARR]], ptr [[TMP12]], align 81316// CHECK8-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 21317// CHECK8-NEXT:    store ptr [[S_ARR]], ptr [[TMP13]], align 81318// CHECK8-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 21319// CHECK8-NEXT:    store ptr null, ptr [[TMP14]], align 81320// CHECK8-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 31321// CHECK8-NEXT:    store ptr [[TMP4]], ptr [[TMP15]], align 81322// CHECK8-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 31323// CHECK8-NEXT:    store ptr [[TMP5]], ptr [[TMP16]], align 81324// CHECK8-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 31325// CHECK8-NEXT:    store ptr null, ptr [[TMP17]], align 81326// CHECK8-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01327// CHECK8-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01328// CHECK8-NEXT:    [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 01329// CHECK8-NEXT:    store i32 3, ptr [[TMP20]], align 41330// CHECK8-NEXT:    [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11331// CHECK8-NEXT:    store i32 4, ptr [[TMP21]], align 41332// CHECK8-NEXT:    [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 21333// CHECK8-NEXT:    store ptr [[TMP18]], ptr [[TMP22]], align 81334// CHECK8-NEXT:    [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 31335// CHECK8-NEXT:    store ptr [[TMP19]], ptr [[TMP23]], align 81336// CHECK8-NEXT:    [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 41337// CHECK8-NEXT:    store ptr @.offload_sizes.1, ptr [[TMP24]], align 81338// CHECK8-NEXT:    [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 51339// CHECK8-NEXT:    store ptr @.offload_maptypes.2, ptr [[TMP25]], align 81340// CHECK8-NEXT:    [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 61341// CHECK8-NEXT:    store ptr null, ptr [[TMP26]], align 81342// CHECK8-NEXT:    [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 71343// CHECK8-NEXT:    store ptr null, ptr [[TMP27]], align 81344// CHECK8-NEXT:    [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 81345// CHECK8-NEXT:    store i64 2, ptr [[TMP28]], align 81346// CHECK8-NEXT:    [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 91347// CHECK8-NEXT:    store i64 0, ptr [[TMP29]], align 81348// CHECK8-NEXT:    [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 101349// CHECK8-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP30]], align 41350// CHECK8-NEXT:    [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 111351// CHECK8-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP31]], align 41352// CHECK8-NEXT:    [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 121353// CHECK8-NEXT:    store i32 0, ptr [[TMP32]], align 41354// CHECK8-NEXT:    [[TMP33:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.region_id, ptr [[KERNEL_ARGS]])1355// CHECK8-NEXT:    [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 01356// CHECK8-NEXT:    br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]1357// CHECK8:       omp_offload.failed:1358// CHECK8-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48(i64 [[TMP2]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP3]]) #[[ATTR4]]1359// CHECK8-NEXT:    br label [[OMP_OFFLOAD_CONT]]1360// CHECK8:       omp_offload.cont:1361// CHECK8-NEXT:    store i32 0, ptr [[RETVAL]], align 41362// CHECK8-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 01363// CHECK8-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 21364// CHECK8-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]1365// CHECK8:       arraydestroy.body:1366// CHECK8-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1367// CHECK8-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -11368// CHECK8-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]1369// CHECK8-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]1370// CHECK8-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]1371// CHECK8:       arraydestroy.done2:1372// CHECK8-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]1373// CHECK8-NEXT:    [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 41374// CHECK8-NEXT:    ret i32 [[TMP36]]1375//1376//1377// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev1378// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1379// CHECK8-NEXT:  entry:1380// CHECK8-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81381// CHECK8-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81382// CHECK8-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81383// CHECK8-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 01384// CHECK8-NEXT:    store float 0.000000e+00, ptr [[F]], align 41385// CHECK8-NEXT:    ret void1386//1387//1388// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef1389// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {1390// CHECK8-NEXT:  entry:1391// CHECK8-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81392// CHECK8-NEXT:    [[A_ADDR:%.*]] = alloca float, align 41393// CHECK8-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81394// CHECK8-NEXT:    store float [[A]], ptr [[A_ADDR]], align 41395// CHECK8-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81396// CHECK8-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 01397// CHECK8-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 41398// CHECK8-NEXT:    store float [[TMP0]], ptr [[F]], align 41399// CHECK8-NEXT:    ret void1400//1401//1402// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev1403// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1404// CHECK8-NEXT:  entry:1405// CHECK8-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81406// CHECK8-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81407// CHECK8-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81408// CHECK8-NEXT:    ret void1409//1410//1411// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev1412// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1413// CHECK8-NEXT:  entry:1414// CHECK8-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81415// CHECK8-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81416// CHECK8-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81417// CHECK8-NEXT:    call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])1418// CHECK8-NEXT:    ret void1419//1420//1421// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei1422// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {1423// CHECK8-NEXT:  entry:1424// CHECK8-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81425// CHECK8-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 41426// CHECK8-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81427// CHECK8-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 41428// CHECK8-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81429// CHECK8-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41430// CHECK8-NEXT:    call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])1431// CHECK8-NEXT:    ret void1432//1433//1434// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l481435// CHECK8-SAME: (i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {1436// CHECK8-NEXT:  entry:1437// CHECK8-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 81438// CHECK8-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 81439// CHECK8-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 81440// CHECK8-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 81441// CHECK8-NEXT:    [[TMP:%.*]] = alloca ptr, align 81442// CHECK8-NEXT:    store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 81443// CHECK8-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 81444// CHECK8-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 81445// CHECK8-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 81446// CHECK8-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]1447// CHECK8-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]1448// CHECK8-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]1449// CHECK8-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 81450// CHECK8-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]1451// CHECK8-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP3]])1452// CHECK8-NEXT:    ret void1453//1454//1455// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.omp_outlined1456// CHECK8-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {1457// CHECK8-NEXT:  entry:1458// CHECK8-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81459// CHECK8-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81460// CHECK8-NEXT:    [[T_VAR_ADDR:%.*]] = alloca ptr, align 81461// CHECK8-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 81462// CHECK8-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 81463// CHECK8-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 81464// CHECK8-NEXT:    [[TMP:%.*]] = alloca ptr, align 81465// CHECK8-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 81466// CHECK8-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 41467// CHECK8-NEXT:    [[_TMP2:%.*]] = alloca i32, align 41468// CHECK8-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 41469// CHECK8-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 41470// CHECK8-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41471// CHECK8-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41472// CHECK8-NEXT:    [[T_VAR3:%.*]] = alloca i32, align 41473// CHECK8-NEXT:    [[VEC4:%.*]] = alloca [2 x i32], align 41474// CHECK8-NEXT:    [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 41475// CHECK8-NEXT:    [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 41476// CHECK8-NEXT:    [[_TMP8:%.*]] = alloca ptr, align 81477// CHECK8-NEXT:    [[I:%.*]] = alloca i32, align 41478// CHECK8-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 81479// CHECK8-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81480// CHECK8-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81481// CHECK8-NEXT:    store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 81482// CHECK8-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 81483// CHECK8-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 81484// CHECK8-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 81485// CHECK8-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]1486// CHECK8-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]1487// CHECK8-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]1488// CHECK8-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]1489// CHECK8-NEXT:    store ptr [[TMP3]], ptr [[TMP]], align 81490// CHECK8-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]1491// CHECK8-NEXT:    store ptr [[TMP4]], ptr [[_TMP1]], align 81492// CHECK8-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 41493// CHECK8-NEXT:    store i32 1, ptr [[DOTOMP_COMB_UB]], align 41494// CHECK8-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 41495// CHECK8-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 41496// CHECK8-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 41497// CHECK8-NEXT:    store i32 [[TMP5]], ptr [[T_VAR3]], align 41498// CHECK8-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC4]], ptr align 4 [[TMP1]], i64 8, i1 false)1499// CHECK8-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 01500// CHECK8-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 21501// CHECK8-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP6]]1502// CHECK8-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]1503// CHECK8:       omp.arraycpy.body:1504// CHECK8-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1505// CHECK8-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1506// CHECK8-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i64 4, i1 false)1507// CHECK8-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 11508// CHECK8-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 11509// CHECK8-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]1510// CHECK8-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]]1511// CHECK8:       omp.arraycpy.done6:1512// CHECK8-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META7]], !align [[META8]]1513// CHECK8-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VAR7]], ptr align 4 [[TMP7]], i64 4, i1 false)1514// CHECK8-NEXT:    store ptr [[VAR7]], ptr [[_TMP8]], align 81515// CHECK8-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81516// CHECK8-NEXT:    [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 41517// CHECK8-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP9]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1518// CHECK8-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 41519// CHECK8-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 11520// CHECK8-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1521// CHECK8:       cond.true:1522// CHECK8-NEXT:    br label [[COND_END:%.*]]1523// CHECK8:       cond.false:1524// CHECK8-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 41525// CHECK8-NEXT:    br label [[COND_END]]1526// CHECK8:       cond.end:1527// CHECK8-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]1528// CHECK8-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 41529// CHECK8-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 41530// CHECK8-NEXT:    store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 41531// CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]1532// CHECK8:       omp.inner.for.cond:1533// CHECK8-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]]1534// CHECK8-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP18]]1535// CHECK8-NEXT:    [[CMP9:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]1536// CHECK8-NEXT:    br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]1537// CHECK8:       omp.inner.for.cond.cleanup:1538// CHECK8-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]1539// CHECK8:       omp.inner.for.body:1540// CHECK8-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP18]]1541// CHECK8-NEXT:    [[TMP16:%.*]] = zext i32 [[TMP15]] to i641542// CHECK8-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP18]]1543// CHECK8-NEXT:    [[TMP18:%.*]] = zext i32 [[TMP17]] to i641544// CHECK8-NEXT:    [[TMP19:%.*]] = load i32, ptr [[T_VAR3]], align 4, !llvm.access.group [[ACC_GRP18]]1545// CHECK8-NEXT:    store i32 [[TMP19]], ptr [[T_VAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP18]]1546// CHECK8-NEXT:    [[TMP20:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8, !llvm.access.group [[ACC_GRP18]]1547// CHECK8-NEXT:    [[TMP21:%.*]] = load ptr, ptr [[_TMP8]], align 8, !nonnull [[META7]], !align [[META8]], !llvm.access.group [[ACC_GRP18]]1548// CHECK8-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.omp_outlined.omp_outlined, i64 [[TMP16]], i64 [[TMP18]], ptr [[VEC4]], i64 [[TMP20]], ptr [[S_ARR5]], ptr [[TMP21]]), !llvm.access.group [[ACC_GRP18]]1549// CHECK8-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]1550// CHECK8:       omp.inner.for.inc:1551// CHECK8-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]1552// CHECK8-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP18]]1553// CHECK8-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]1554// CHECK8-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]1555// CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]1556// CHECK8:       omp.inner.for.end:1557// CHECK8-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]1558// CHECK8:       omp.loop.exit:1559// CHECK8-NEXT:    [[TMP24:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81560// CHECK8-NEXT:    [[TMP25:%.*]] = load i32, ptr [[TMP24]], align 41561// CHECK8-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP25]])1562// CHECK8-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 41563// CHECK8-NEXT:    [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 01564// CHECK8-NEXT:    br i1 [[TMP27]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]1565// CHECK8:       .omp.final.then:1566// CHECK8-NEXT:    store i32 2, ptr [[I]], align 41567// CHECK8-NEXT:    br label [[DOTOMP_FINAL_DONE]]1568// CHECK8:       .omp.final.done:1569// CHECK8-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]]1570// CHECK8-NEXT:    [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 01571// CHECK8-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i64 21572// CHECK8-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]1573// CHECK8:       arraydestroy.body:1574// CHECK8-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP28]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1575// CHECK8-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -11576// CHECK8-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]1577// CHECK8-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]1578// CHECK8-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]1579// CHECK8:       arraydestroy.done11:1580// CHECK8-NEXT:    ret void1581//1582//1583// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.omp_outlined.omp_outlined1584// CHECK8-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {1585// CHECK8-NEXT:  entry:1586// CHECK8-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81587// CHECK8-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81588// CHECK8-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 81589// CHECK8-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 81590// CHECK8-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 81591// CHECK8-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 81592// CHECK8-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 81593// CHECK8-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 81594// CHECK8-NEXT:    [[TMP:%.*]] = alloca ptr, align 81595// CHECK8-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 41596// CHECK8-NEXT:    [[_TMP1:%.*]] = alloca i32, align 41597// CHECK8-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 41598// CHECK8-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 41599// CHECK8-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41600// CHECK8-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41601// CHECK8-NEXT:    [[VEC3:%.*]] = alloca [2 x i32], align 41602// CHECK8-NEXT:    [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 41603// CHECK8-NEXT:    [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 41604// CHECK8-NEXT:    [[_TMP7:%.*]] = alloca ptr, align 81605// CHECK8-NEXT:    [[I:%.*]] = alloca i32, align 41606// CHECK8-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81607// CHECK8-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81608// CHECK8-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 81609// CHECK8-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 81610// CHECK8-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 81611// CHECK8-NEXT:    store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 81612// CHECK8-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 81613// CHECK8-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 81614// CHECK8-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]1615// CHECK8-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]1616// CHECK8-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]1617// CHECK8-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 81618// CHECK8-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 41619// CHECK8-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 41620// CHECK8-NEXT:    [[TMP3:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 81621// CHECK8-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP3]] to i321622// CHECK8-NEXT:    [[TMP4:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 81623// CHECK8-NEXT:    [[CONV2:%.*]] = trunc i64 [[TMP4]] to i321624// CHECK8-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 41625// CHECK8-NEXT:    store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 41626// CHECK8-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 41627// CHECK8-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 41628// CHECK8-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC3]], ptr align 4 [[TMP0]], i64 8, i1 false)1629// CHECK8-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 01630// CHECK8-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 21631// CHECK8-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]]1632// CHECK8-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE5:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]1633// CHECK8:       omp.arraycpy.body:1634// CHECK8-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1635// CHECK8-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1636// CHECK8-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i64 4, i1 false)1637// CHECK8-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 11638// CHECK8-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 11639// CHECK8-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]]1640// CHECK8-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_BODY]]1641// CHECK8:       omp.arraycpy.done5:1642// CHECK8-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]1643// CHECK8-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VAR6]], ptr align 4 [[TMP6]], i64 4, i1 false)1644// CHECK8-NEXT:    store ptr [[VAR6]], ptr [[_TMP7]], align 81645// CHECK8-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81646// CHECK8-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 41647// CHECK8-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP8]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1648// CHECK8-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41649// CHECK8-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 11650// CHECK8-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1651// CHECK8:       cond.true:1652// CHECK8-NEXT:    br label [[COND_END:%.*]]1653// CHECK8:       cond.false:1654// CHECK8-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41655// CHECK8-NEXT:    br label [[COND_END]]1656// CHECK8:       cond.end:1657// CHECK8-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]1658// CHECK8-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 41659// CHECK8-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41660// CHECK8-NEXT:    store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 41661// CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]1662// CHECK8:       omp.inner.for.cond:1663// CHECK8-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21:![0-9]+]]1664// CHECK8-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP21]]1665// CHECK8-NEXT:    [[CMP8:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]1666// CHECK8-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]1667// CHECK8:       omp.inner.for.cond.cleanup:1668// CHECK8-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]1669// CHECK8:       omp.inner.for.body:1670// CHECK8-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]]1671// CHECK8-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP14]], 11672// CHECK8-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]1673// CHECK8-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]]1674// CHECK8-NEXT:    [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP21]]1675// CHECK8-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]]1676// CHECK8-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i641677// CHECK8-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]]1678// CHECK8-NEXT:    store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP21]]1679// CHECK8-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 8, !nonnull [[META7]], !align [[META8]], !llvm.access.group [[ACC_GRP21]]1680// CHECK8-NEXT:    [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]]1681// CHECK8-NEXT:    [[IDXPROM9:%.*]] = sext i32 [[TMP18]] to i641682// CHECK8-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM9]]1683// CHECK8-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP17]], i64 4, i1 false), !llvm.access.group [[ACC_GRP21]]1684// CHECK8-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]1685// CHECK8:       omp.body.continue:1686// CHECK8-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]1687// CHECK8:       omp.inner.for.inc:1688// CHECK8-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]]1689// CHECK8-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP19]], 11690// CHECK8-NEXT:    store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]]1691// CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]1692// CHECK8:       omp.inner.for.end:1693// CHECK8-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]1694// CHECK8:       omp.loop.exit:1695// CHECK8-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81696// CHECK8-NEXT:    [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 41697// CHECK8-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]])1698// CHECK8-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 41699// CHECK8-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 01700// CHECK8-NEXT:    br i1 [[TMP23]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]1701// CHECK8:       .omp.final.then:1702// CHECK8-NEXT:    store i32 2, ptr [[I]], align 41703// CHECK8-NEXT:    br label [[DOTOMP_FINAL_DONE]]1704// CHECK8:       .omp.final.done:1705// CHECK8-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]]1706// CHECK8-NEXT:    [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 01707// CHECK8-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 21708// CHECK8-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]1709// CHECK8:       arraydestroy.body:1710// CHECK8-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP24]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1711// CHECK8-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -11712// CHECK8-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]1713// CHECK8-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]]1714// CHECK8-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]]1715// CHECK8:       arraydestroy.done13:1716// CHECK8-NEXT:    ret void1717//1718//1719// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev1720// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1721// CHECK8-NEXT:  entry:1722// CHECK8-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81723// CHECK8-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81724// CHECK8-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81725// CHECK8-NEXT:    call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]1726// CHECK8-NEXT:    ret void1727//1728//1729// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev1730// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1731// CHECK8-NEXT:  entry:1732// CHECK8-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81733// CHECK8-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81734// CHECK8-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81735// CHECK8-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 01736// CHECK8-NEXT:    store i32 0, ptr [[F]], align 41737// CHECK8-NEXT:    ret void1738//1739//1740// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei1741// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {1742// CHECK8-NEXT:  entry:1743// CHECK8-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81744// CHECK8-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 41745// CHECK8-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81746// CHECK8-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 41747// CHECK8-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81748// CHECK8-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 01749// CHECK8-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41750// CHECK8-NEXT:    store i32 [[TMP0]], ptr [[F]], align 41751// CHECK8-NEXT:    ret void1752//1753//1754// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev1755// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1756// CHECK8-NEXT:  entry:1757// CHECK8-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81758// CHECK8-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81759// CHECK8-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81760// CHECK8-NEXT:    ret void1761//1762//1763// CHECK10-LABEL: define {{[^@]+}}@main1764// CHECK10-SAME: () #[[ATTR0:[0-9]+]] {1765// CHECK10-NEXT:  entry:1766// CHECK10-NEXT:    [[RETVAL:%.*]] = alloca i32, align 41767// CHECK10-NEXT:    [[G:%.*]] = alloca double, align 81768// CHECK10-NEXT:    [[G1:%.*]] = alloca ptr, align 41769// CHECK10-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 41770// CHECK10-NEXT:    [[T_VAR:%.*]] = alloca i32, align 41771// CHECK10-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 41772// CHECK10-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S], align 41773// CHECK10-NEXT:    [[VAR:%.*]] = alloca ptr, align 41774// CHECK10-NEXT:    [[TMP:%.*]] = alloca ptr, align 41775// CHECK10-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 41776// CHECK10-NEXT:    [[SVAR_CASTED:%.*]] = alloca i32, align 41777// CHECK10-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 41778// CHECK10-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 41779// CHECK10-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 41780// CHECK10-NEXT:    [[_TMP1:%.*]] = alloca i32, align 41781// CHECK10-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81782// CHECK10-NEXT:    store i32 0, ptr [[RETVAL]], align 41783// CHECK10-NEXT:    store ptr [[G]], ptr [[G1]], align 41784// CHECK10-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])1785// CHECK10-NEXT:    store i32 0, ptr [[T_VAR]], align 41786// CHECK10-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i32 8, i1 false)1787// CHECK10-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], float noundef 1.000000e+00)1788// CHECK10-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i32 11789// CHECK10-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00)1790// CHECK10-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 41791// CHECK10-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4, !nonnull [[META8:![0-9]+]], !align [[META9:![0-9]+]]1792// CHECK10-NEXT:    store ptr [[TMP0]], ptr [[TMP]], align 41793// CHECK10-NEXT:    [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 41794// CHECK10-NEXT:    store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 41795// CHECK10-NEXT:    [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 41796// CHECK10-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]1797// CHECK10-NEXT:    [[TMP4:%.*]] = load i32, ptr @_ZZ4mainE4svar, align 41798// CHECK10-NEXT:    store i32 [[TMP4]], ptr [[SVAR_CASTED]], align 41799// CHECK10-NEXT:    [[TMP5:%.*]] = load i32, ptr [[SVAR_CASTED]], align 41800// CHECK10-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]1801// CHECK10-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]1802// CHECK10-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01803// CHECK10-NEXT:    store i32 [[TMP2]], ptr [[TMP8]], align 41804// CHECK10-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01805// CHECK10-NEXT:    store i32 [[TMP2]], ptr [[TMP9]], align 41806// CHECK10-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 01807// CHECK10-NEXT:    store ptr null, ptr [[TMP10]], align 41808// CHECK10-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 11809// CHECK10-NEXT:    store ptr [[VEC]], ptr [[TMP11]], align 41810// CHECK10-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 11811// CHECK10-NEXT:    store ptr [[VEC]], ptr [[TMP12]], align 41812// CHECK10-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 11813// CHECK10-NEXT:    store ptr null, ptr [[TMP13]], align 41814// CHECK10-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 21815// CHECK10-NEXT:    store ptr [[S_ARR]], ptr [[TMP14]], align 41816// CHECK10-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 21817// CHECK10-NEXT:    store ptr [[S_ARR]], ptr [[TMP15]], align 41818// CHECK10-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 21819// CHECK10-NEXT:    store ptr null, ptr [[TMP16]], align 41820// CHECK10-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 31821// CHECK10-NEXT:    store ptr [[TMP6]], ptr [[TMP17]], align 41822// CHECK10-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 31823// CHECK10-NEXT:    store ptr [[TMP7]], ptr [[TMP18]], align 41824// CHECK10-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 31825// CHECK10-NEXT:    store ptr null, ptr [[TMP19]], align 41826// CHECK10-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 41827// CHECK10-NEXT:    store i32 [[TMP5]], ptr [[TMP20]], align 41828// CHECK10-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 41829// CHECK10-NEXT:    store i32 [[TMP5]], ptr [[TMP21]], align 41830// CHECK10-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 41831// CHECK10-NEXT:    store ptr null, ptr [[TMP22]], align 41832// CHECK10-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01833// CHECK10-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01834// CHECK10-NEXT:    [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 01835// CHECK10-NEXT:    store i32 3, ptr [[TMP25]], align 41836// CHECK10-NEXT:    [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11837// CHECK10-NEXT:    store i32 5, ptr [[TMP26]], align 41838// CHECK10-NEXT:    [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 21839// CHECK10-NEXT:    store ptr [[TMP23]], ptr [[TMP27]], align 41840// CHECK10-NEXT:    [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 31841// CHECK10-NEXT:    store ptr [[TMP24]], ptr [[TMP28]], align 41842// CHECK10-NEXT:    [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 41843// CHECK10-NEXT:    store ptr @.offload_sizes, ptr [[TMP29]], align 41844// CHECK10-NEXT:    [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 51845// CHECK10-NEXT:    store ptr @.offload_maptypes, ptr [[TMP30]], align 41846// CHECK10-NEXT:    [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 61847// CHECK10-NEXT:    store ptr null, ptr [[TMP31]], align 41848// CHECK10-NEXT:    [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 71849// CHECK10-NEXT:    store ptr null, ptr [[TMP32]], align 41850// CHECK10-NEXT:    [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 81851// CHECK10-NEXT:    store i64 2, ptr [[TMP33]], align 81852// CHECK10-NEXT:    [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 91853// CHECK10-NEXT:    store i64 0, ptr [[TMP34]], align 81854// CHECK10-NEXT:    [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 101855// CHECK10-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP35]], align 41856// CHECK10-NEXT:    [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 111857// CHECK10-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP36]], align 41858// CHECK10-NEXT:    [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 121859// CHECK10-NEXT:    store i32 0, ptr [[TMP37]], align 41860// CHECK10-NEXT:    [[TMP38:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l138.region_id, ptr [[KERNEL_ARGS]])1861// CHECK10-NEXT:    [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 01862// CHECK10-NEXT:    br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]1863// CHECK10:       omp_offload.failed:1864// CHECK10-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l138(i32 [[TMP2]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP3]], i32 [[TMP5]]) #[[ATTR4:[0-9]+]]1865// CHECK10-NEXT:    br label [[OMP_OFFLOAD_CONT]]1866// CHECK10:       omp_offload.cont:1867// CHECK10-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()1868// CHECK10-NEXT:    store i32 [[CALL]], ptr [[RETVAL]], align 41869// CHECK10-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 01870// CHECK10-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 21871// CHECK10-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]1872// CHECK10:       arraydestroy.body:1873// CHECK10-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP40]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1874// CHECK10-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -11875// CHECK10-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]1876// CHECK10-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]1877// CHECK10-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]1878// CHECK10:       arraydestroy.done2:1879// CHECK10-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]1880// CHECK10-NEXT:    [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 41881// CHECK10-NEXT:    ret i32 [[TMP41]]1882//1883//1884// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev1885// CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {1886// CHECK10-NEXT:  entry:1887// CHECK10-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41888// CHECK10-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41889// CHECK10-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41890// CHECK10-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])1891// CHECK10-NEXT:    ret void1892//1893//1894// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef1895// CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1896// CHECK10-NEXT:  entry:1897// CHECK10-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41898// CHECK10-NEXT:    [[A_ADDR:%.*]] = alloca float, align 41899// CHECK10-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41900// CHECK10-NEXT:    store float [[A]], ptr [[A_ADDR]], align 41901// CHECK10-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41902// CHECK10-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 41903// CHECK10-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])1904// CHECK10-NEXT:    ret void1905//1906//1907// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l1381908// CHECK10-SAME: (i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] {1909// CHECK10-NEXT:  entry:1910// CHECK10-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 41911// CHECK10-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 41912// CHECK10-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 41913// CHECK10-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 41914// CHECK10-NEXT:    [[SVAR_ADDR:%.*]] = alloca i32, align 41915// CHECK10-NEXT:    [[TMP:%.*]] = alloca ptr, align 41916// CHECK10-NEXT:    store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 41917// CHECK10-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 41918// CHECK10-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 41919// CHECK10-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 41920// CHECK10-NEXT:    store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 41921// CHECK10-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1922// CHECK10-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1923// CHECK10-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1924// CHECK10-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 41925// CHECK10-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]1926// CHECK10-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l138.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP3]], ptr [[SVAR_ADDR]])1927// CHECK10-NEXT:    ret void1928//1929//1930// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l138.omp_outlined1931// CHECK10-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] {1932// CHECK10-NEXT:  entry:1933// CHECK10-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 41934// CHECK10-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 41935// CHECK10-NEXT:    [[T_VAR_ADDR:%.*]] = alloca ptr, align 41936// CHECK10-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 41937// CHECK10-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 41938// CHECK10-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 41939// CHECK10-NEXT:    [[SVAR_ADDR:%.*]] = alloca ptr, align 41940// CHECK10-NEXT:    [[TMP:%.*]] = alloca ptr, align 41941// CHECK10-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 41942// CHECK10-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 41943// CHECK10-NEXT:    [[_TMP2:%.*]] = alloca i32, align 41944// CHECK10-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 41945// CHECK10-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 41946// CHECK10-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41947// CHECK10-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41948// CHECK10-NEXT:    [[T_VAR3:%.*]] = alloca i32, align 41949// CHECK10-NEXT:    [[VEC4:%.*]] = alloca [2 x i32], align 41950// CHECK10-NEXT:    [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 41951// CHECK10-NEXT:    [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 41952// CHECK10-NEXT:    [[_TMP8:%.*]] = alloca ptr, align 41953// CHECK10-NEXT:    [[SVAR9:%.*]] = alloca i32, align 41954// CHECK10-NEXT:    [[I:%.*]] = alloca i32, align 41955// CHECK10-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 41956// CHECK10-NEXT:    [[SVAR_CASTED:%.*]] = alloca i32, align 41957// CHECK10-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 41958// CHECK10-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 41959// CHECK10-NEXT:    store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 41960// CHECK10-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 41961// CHECK10-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 41962// CHECK10-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 41963// CHECK10-NEXT:    store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 41964// CHECK10-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1965// CHECK10-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1966// CHECK10-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1967// CHECK10-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1968// CHECK10-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1969// CHECK10-NEXT:    store ptr [[TMP3]], ptr [[TMP]], align 41970// CHECK10-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]1971// CHECK10-NEXT:    store ptr [[TMP5]], ptr [[_TMP1]], align 41972// CHECK10-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 41973// CHECK10-NEXT:    store i32 1, ptr [[DOTOMP_COMB_UB]], align 41974// CHECK10-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 41975// CHECK10-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 41976// CHECK10-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP0]], align 41977// CHECK10-NEXT:    store i32 [[TMP6]], ptr [[T_VAR3]], align 41978// CHECK10-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC4]], ptr align 4 [[TMP1]], i32 8, i1 false)1979// CHECK10-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 01980// CHECK10-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 21981// CHECK10-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP7]]1982// CHECK10-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]1983// CHECK10:       omp.arraycpy.body:1984// CHECK10-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1985// CHECK10-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1986// CHECK10-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 4, i1 false)1987// CHECK10-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 11988// CHECK10-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 11989// CHECK10-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP7]]1990// CHECK10-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]]1991// CHECK10:       omp.arraycpy.done6:1992// CHECK10-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 4, !nonnull [[META8]], !align [[META9]]1993// CHECK10-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VAR7]], ptr align 4 [[TMP8]], i32 4, i1 false)1994// CHECK10-NEXT:    store ptr [[VAR7]], ptr [[_TMP8]], align 41995// CHECK10-NEXT:    [[TMP9:%.*]] = load i32, ptr [[TMP4]], align 41996// CHECK10-NEXT:    store i32 [[TMP9]], ptr [[SVAR9]], align 41997// CHECK10-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41998// CHECK10-NEXT:    [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 41999// CHECK10-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)2000// CHECK10-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 42001// CHECK10-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 12002// CHECK10-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2003// CHECK10:       cond.true:2004// CHECK10-NEXT:    br label [[COND_END:%.*]]2005// CHECK10:       cond.false:2006// CHECK10-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 42007// CHECK10-NEXT:    br label [[COND_END]]2008// CHECK10:       cond.end:2009// CHECK10-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]2010// CHECK10-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 42011// CHECK10-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 42012// CHECK10-NEXT:    store i32 [[TMP14]], ptr [[DOTOMP_IV]], align 42013// CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]2014// CHECK10:       omp.inner.for.cond:2015// CHECK10-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]]2016// CHECK10-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP10]]2017// CHECK10-NEXT:    [[CMP10:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]2018// CHECK10-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]2019// CHECK10:       omp.inner.for.cond.cleanup:2020// CHECK10-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]2021// CHECK10:       omp.inner.for.body:2022// CHECK10-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP10]]2023// CHECK10-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP10]]2024// CHECK10-NEXT:    [[TMP19:%.*]] = load i32, ptr [[T_VAR3]], align 4, !llvm.access.group [[ACC_GRP10]]2025// CHECK10-NEXT:    store i32 [[TMP19]], ptr [[T_VAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP10]]2026// CHECK10-NEXT:    [[TMP20:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP10]]2027// CHECK10-NEXT:    [[TMP21:%.*]] = load ptr, ptr [[_TMP8]], align 4, !nonnull [[META8]], !align [[META9]], !llvm.access.group [[ACC_GRP10]]2028// CHECK10-NEXT:    [[TMP22:%.*]] = load i32, ptr [[SVAR9]], align 4, !llvm.access.group [[ACC_GRP10]]2029// CHECK10-NEXT:    store i32 [[TMP22]], ptr [[SVAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP10]]2030// CHECK10-NEXT:    [[TMP23:%.*]] = load i32, ptr [[SVAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP10]]2031// CHECK10-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 7, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l138.omp_outlined.omp_outlined, i32 [[TMP17]], i32 [[TMP18]], ptr [[VEC4]], i32 [[TMP20]], ptr [[S_ARR5]], ptr [[TMP21]], i32 [[TMP23]]), !llvm.access.group [[ACC_GRP10]]2032// CHECK10-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]2033// CHECK10:       omp.inner.for.inc:2034// CHECK10-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]2035// CHECK10-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP10]]2036// CHECK10-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP24]], [[TMP25]]2037// CHECK10-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]2038// CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]2039// CHECK10:       omp.inner.for.end:2040// CHECK10-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]2041// CHECK10:       omp.loop.exit:2042// CHECK10-NEXT:    [[TMP26:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 42043// CHECK10-NEXT:    [[TMP27:%.*]] = load i32, ptr [[TMP26]], align 42044// CHECK10-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP27]])2045// CHECK10-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 42046// CHECK10-NEXT:    [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 02047// CHECK10-NEXT:    br i1 [[TMP29]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]2048// CHECK10:       .omp.final.then:2049// CHECK10-NEXT:    store i32 2, ptr [[I]], align 42050// CHECK10-NEXT:    br label [[DOTOMP_FINAL_DONE]]2051// CHECK10:       .omp.final.done:2052// CHECK10-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]]2053// CHECK10-NEXT:    [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 02054// CHECK10-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i32 22055// CHECK10-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]2056// CHECK10:       arraydestroy.body:2057// CHECK10-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP30]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]2058// CHECK10-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -12059// CHECK10-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]2060// CHECK10-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]]2061// CHECK10-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]]2062// CHECK10:       arraydestroy.done12:2063// CHECK10-NEXT:    ret void2064//2065//2066// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l138.omp_outlined.omp_outlined2067// CHECK10-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3]] {2068// CHECK10-NEXT:  entry:2069// CHECK10-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 42070// CHECK10-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 42071// CHECK10-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 42072// CHECK10-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 42073// CHECK10-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 42074// CHECK10-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 42075// CHECK10-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 42076// CHECK10-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 42077// CHECK10-NEXT:    [[SVAR_ADDR:%.*]] = alloca i32, align 42078// CHECK10-NEXT:    [[TMP:%.*]] = alloca ptr, align 42079// CHECK10-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 42080// CHECK10-NEXT:    [[_TMP1:%.*]] = alloca i32, align 42081// CHECK10-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 42082// CHECK10-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 42083// CHECK10-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42084// CHECK10-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42085// CHECK10-NEXT:    [[VEC2:%.*]] = alloca [2 x i32], align 42086// CHECK10-NEXT:    [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 42087// CHECK10-NEXT:    [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 42088// CHECK10-NEXT:    [[_TMP6:%.*]] = alloca ptr, align 42089// CHECK10-NEXT:    [[I:%.*]] = alloca i32, align 42090// CHECK10-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 42091// CHECK10-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 42092// CHECK10-NEXT:    store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 42093// CHECK10-NEXT:    store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 42094// CHECK10-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 42095// CHECK10-NEXT:    store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 42096// CHECK10-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 42097// CHECK10-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 42098// CHECK10-NEXT:    store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 42099// CHECK10-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]2100// CHECK10-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]2101// CHECK10-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]2102// CHECK10-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 42103// CHECK10-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 42104// CHECK10-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 42105// CHECK10-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 42106// CHECK10-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 42107// CHECK10-NEXT:    store i32 [[TMP3]], ptr [[DOTOMP_LB]], align 42108// CHECK10-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 42109// CHECK10-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 42110// CHECK10-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 42111// CHECK10-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false)2112// CHECK10-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 02113// CHECK10-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 22114// CHECK10-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]]2115// CHECK10-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]2116// CHECK10:       omp.arraycpy.body:2117// CHECK10-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]2118// CHECK10-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]2119// CHECK10-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 4, i1 false)2120// CHECK10-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 12121// CHECK10-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 12122// CHECK10-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]]2123// CHECK10-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]2124// CHECK10:       omp.arraycpy.done4:2125// CHECK10-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]2126// CHECK10-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VAR5]], ptr align 4 [[TMP6]], i32 4, i1 false)2127// CHECK10-NEXT:    store ptr [[VAR5]], ptr [[_TMP6]], align 42128// CHECK10-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 42129// CHECK10-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 42130// CHECK10-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP8]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)2131// CHECK10-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42132// CHECK10-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 12133// CHECK10-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2134// CHECK10:       cond.true:2135// CHECK10-NEXT:    br label [[COND_END:%.*]]2136// CHECK10:       cond.false:2137// CHECK10-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42138// CHECK10-NEXT:    br label [[COND_END]]2139// CHECK10:       cond.end:2140// CHECK10-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]2141// CHECK10-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 42142// CHECK10-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42143// CHECK10-NEXT:    store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 42144// CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]2145// CHECK10:       omp.inner.for.cond:2146// CHECK10-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14:![0-9]+]]2147// CHECK10-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP14]]2148// CHECK10-NEXT:    [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]2149// CHECK10-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]2150// CHECK10:       omp.inner.for.cond.cleanup:2151// CHECK10-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]2152// CHECK10:       omp.inner.for.body:2153// CHECK10-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]2154// CHECK10-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP14]], 12155// CHECK10-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]2156// CHECK10-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]]2157// CHECK10-NEXT:    [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP14]]2158// CHECK10-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]]2159// CHECK10-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i32 0, i32 [[TMP16]]2160// CHECK10-NEXT:    store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP14]]2161// CHECK10-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[_TMP6]], align 4, !nonnull [[META8]], !align [[META9]], !llvm.access.group [[ACC_GRP14]]2162// CHECK10-NEXT:    [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]]2163// CHECK10-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 [[TMP18]]2164// CHECK10-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP17]], i32 4, i1 false), !llvm.access.group [[ACC_GRP14]]2165// CHECK10-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]2166// CHECK10:       omp.body.continue:2167// CHECK10-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]2168// CHECK10:       omp.inner.for.inc:2169// CHECK10-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]2170// CHECK10-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP19]], 12171// CHECK10-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]2172// CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]2173// CHECK10:       omp.inner.for.end:2174// CHECK10-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]2175// CHECK10:       omp.loop.exit:2176// CHECK10-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 42177// CHECK10-NEXT:    [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 42178// CHECK10-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]])2179// CHECK10-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 42180// CHECK10-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 02181// CHECK10-NEXT:    br i1 [[TMP23]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]2182// CHECK10:       .omp.final.then:2183// CHECK10-NEXT:    store i32 2, ptr [[I]], align 42184// CHECK10-NEXT:    br label [[DOTOMP_FINAL_DONE]]2185// CHECK10:       .omp.final.done:2186// CHECK10-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]2187// CHECK10-NEXT:    [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 02188// CHECK10-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i32 22189// CHECK10-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]2190// CHECK10:       arraydestroy.body:2191// CHECK10-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP24]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]2192// CHECK10-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -12193// CHECK10-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]2194// CHECK10-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]2195// CHECK10-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]2196// CHECK10:       arraydestroy.done11:2197// CHECK10-NEXT:    ret void2198//2199//2200// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev2201// CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2202// CHECK10-NEXT:  entry:2203// CHECK10-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 42204// CHECK10-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 42205// CHECK10-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42206// CHECK10-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]2207// CHECK10-NEXT:    ret void2208//2209//2210// CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiET_v2211// CHECK10-SAME: () #[[ATTR1]] comdat {2212// CHECK10-NEXT:  entry:2213// CHECK10-NEXT:    [[RETVAL:%.*]] = alloca i32, align 42214// CHECK10-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 42215// CHECK10-NEXT:    [[T_VAR:%.*]] = alloca i32, align 42216// CHECK10-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 42217// CHECK10-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 42218// CHECK10-NEXT:    [[VAR:%.*]] = alloca ptr, align 42219// CHECK10-NEXT:    [[TMP:%.*]] = alloca ptr, align 42220// CHECK10-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 42221// CHECK10-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 42222// CHECK10-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 42223// CHECK10-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 42224// CHECK10-NEXT:    [[_TMP1:%.*]] = alloca i32, align 42225// CHECK10-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 82226// CHECK10-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])2227// CHECK10-NEXT:    store i32 0, ptr [[T_VAR]], align 42228// CHECK10-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false)2229// CHECK10-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1)2230// CHECK10-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 12231// CHECK10-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)2232// CHECK10-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 42233// CHECK10-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4, !nonnull [[META8]], !align [[META9]]2234// CHECK10-NEXT:    store ptr [[TMP0]], ptr [[TMP]], align 42235// CHECK10-NEXT:    [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 42236// CHECK10-NEXT:    store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 42237// CHECK10-NEXT:    [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 42238// CHECK10-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]2239// CHECK10-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]2240// CHECK10-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]2241// CHECK10-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 02242// CHECK10-NEXT:    store i32 [[TMP2]], ptr [[TMP6]], align 42243// CHECK10-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 02244// CHECK10-NEXT:    store i32 [[TMP2]], ptr [[TMP7]], align 42245// CHECK10-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 02246// CHECK10-NEXT:    store ptr null, ptr [[TMP8]], align 42247// CHECK10-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 12248// CHECK10-NEXT:    store ptr [[VEC]], ptr [[TMP9]], align 42249// CHECK10-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 12250// CHECK10-NEXT:    store ptr [[VEC]], ptr [[TMP10]], align 42251// CHECK10-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 12252// CHECK10-NEXT:    store ptr null, ptr [[TMP11]], align 42253// CHECK10-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 22254// CHECK10-NEXT:    store ptr [[S_ARR]], ptr [[TMP12]], align 42255// CHECK10-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 22256// CHECK10-NEXT:    store ptr [[S_ARR]], ptr [[TMP13]], align 42257// CHECK10-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 22258// CHECK10-NEXT:    store ptr null, ptr [[TMP14]], align 42259// CHECK10-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 32260// CHECK10-NEXT:    store ptr [[TMP4]], ptr [[TMP15]], align 42261// CHECK10-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 32262// CHECK10-NEXT:    store ptr [[TMP5]], ptr [[TMP16]], align 42263// CHECK10-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 32264// CHECK10-NEXT:    store ptr null, ptr [[TMP17]], align 42265// CHECK10-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 02266// CHECK10-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 02267// CHECK10-NEXT:    [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 02268// CHECK10-NEXT:    store i32 3, ptr [[TMP20]], align 42269// CHECK10-NEXT:    [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12270// CHECK10-NEXT:    store i32 4, ptr [[TMP21]], align 42271// CHECK10-NEXT:    [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 22272// CHECK10-NEXT:    store ptr [[TMP18]], ptr [[TMP22]], align 42273// CHECK10-NEXT:    [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 32274// CHECK10-NEXT:    store ptr [[TMP19]], ptr [[TMP23]], align 42275// CHECK10-NEXT:    [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 42276// CHECK10-NEXT:    store ptr @.offload_sizes.1, ptr [[TMP24]], align 42277// CHECK10-NEXT:    [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 52278// CHECK10-NEXT:    store ptr @.offload_maptypes.2, ptr [[TMP25]], align 42279// CHECK10-NEXT:    [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 62280// CHECK10-NEXT:    store ptr null, ptr [[TMP26]], align 42281// CHECK10-NEXT:    [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 72282// CHECK10-NEXT:    store ptr null, ptr [[TMP27]], align 42283// CHECK10-NEXT:    [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 82284// CHECK10-NEXT:    store i64 2, ptr [[TMP28]], align 82285// CHECK10-NEXT:    [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 92286// CHECK10-NEXT:    store i64 0, ptr [[TMP29]], align 82287// CHECK10-NEXT:    [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 102288// CHECK10-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP30]], align 42289// CHECK10-NEXT:    [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 112290// CHECK10-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP31]], align 42291// CHECK10-NEXT:    [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 122292// CHECK10-NEXT:    store i32 0, ptr [[TMP32]], align 42293// CHECK10-NEXT:    [[TMP33:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.region_id, ptr [[KERNEL_ARGS]])2294// CHECK10-NEXT:    [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 02295// CHECK10-NEXT:    br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]2296// CHECK10:       omp_offload.failed:2297// CHECK10-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48(i32 [[TMP2]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP3]]) #[[ATTR4]]2298// CHECK10-NEXT:    br label [[OMP_OFFLOAD_CONT]]2299// CHECK10:       omp_offload.cont:2300// CHECK10-NEXT:    store i32 0, ptr [[RETVAL]], align 42301// CHECK10-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 02302// CHECK10-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 22303// CHECK10-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]2304// CHECK10:       arraydestroy.body:2305// CHECK10-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]2306// CHECK10-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -12307// CHECK10-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]2308// CHECK10-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]2309// CHECK10-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]2310// CHECK10:       arraydestroy.done2:2311// CHECK10-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]2312// CHECK10-NEXT:    [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 42313// CHECK10-NEXT:    ret i32 [[TMP36]]2314//2315//2316// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev2317// CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2318// CHECK10-NEXT:  entry:2319// CHECK10-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 42320// CHECK10-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 42321// CHECK10-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42322// CHECK10-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 02323// CHECK10-NEXT:    store float 0.000000e+00, ptr [[F]], align 42324// CHECK10-NEXT:    ret void2325//2326//2327// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef2328// CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2329// CHECK10-NEXT:  entry:2330// CHECK10-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 42331// CHECK10-NEXT:    [[A_ADDR:%.*]] = alloca float, align 42332// CHECK10-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 42333// CHECK10-NEXT:    store float [[A]], ptr [[A_ADDR]], align 42334// CHECK10-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42335// CHECK10-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 02336// CHECK10-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 42337// CHECK10-NEXT:    store float [[TMP0]], ptr [[F]], align 42338// CHECK10-NEXT:    ret void2339//2340//2341// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev2342// CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2343// CHECK10-NEXT:  entry:2344// CHECK10-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 42345// CHECK10-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 42346// CHECK10-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42347// CHECK10-NEXT:    ret void2348//2349//2350// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev2351// CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2352// CHECK10-NEXT:  entry:2353// CHECK10-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 42354// CHECK10-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 42355// CHECK10-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42356// CHECK10-NEXT:    call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])2357// CHECK10-NEXT:    ret void2358//2359//2360// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei2361// CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2362// CHECK10-NEXT:  entry:2363// CHECK10-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 42364// CHECK10-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 42365// CHECK10-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 42366// CHECK10-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 42367// CHECK10-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42368// CHECK10-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 42369// CHECK10-NEXT:    call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])2370// CHECK10-NEXT:    ret void2371//2372//2373// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l482374// CHECK10-SAME: (i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {2375// CHECK10-NEXT:  entry:2376// CHECK10-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 42377// CHECK10-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 42378// CHECK10-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 42379// CHECK10-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 42380// CHECK10-NEXT:    [[TMP:%.*]] = alloca ptr, align 42381// CHECK10-NEXT:    store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 42382// CHECK10-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 42383// CHECK10-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 42384// CHECK10-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 42385// CHECK10-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]2386// CHECK10-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]2387// CHECK10-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]2388// CHECK10-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 42389// CHECK10-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]2390// CHECK10-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP3]])2391// CHECK10-NEXT:    ret void2392//2393//2394// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.omp_outlined2395// CHECK10-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {2396// CHECK10-NEXT:  entry:2397// CHECK10-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 42398// CHECK10-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 42399// CHECK10-NEXT:    [[T_VAR_ADDR:%.*]] = alloca ptr, align 42400// CHECK10-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 42401// CHECK10-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 42402// CHECK10-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 42403// CHECK10-NEXT:    [[TMP:%.*]] = alloca ptr, align 42404// CHECK10-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 42405// CHECK10-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 42406// CHECK10-NEXT:    [[_TMP2:%.*]] = alloca i32, align 42407// CHECK10-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 42408// CHECK10-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 42409// CHECK10-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42410// CHECK10-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42411// CHECK10-NEXT:    [[T_VAR3:%.*]] = alloca i32, align 42412// CHECK10-NEXT:    [[VEC4:%.*]] = alloca [2 x i32], align 42413// CHECK10-NEXT:    [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 42414// CHECK10-NEXT:    [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 42415// CHECK10-NEXT:    [[_TMP8:%.*]] = alloca ptr, align 42416// CHECK10-NEXT:    [[I:%.*]] = alloca i32, align 42417// CHECK10-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 42418// CHECK10-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 42419// CHECK10-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 42420// CHECK10-NEXT:    store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 42421// CHECK10-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 42422// CHECK10-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 42423// CHECK10-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 42424// CHECK10-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]2425// CHECK10-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]2426// CHECK10-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]2427// CHECK10-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]2428// CHECK10-NEXT:    store ptr [[TMP3]], ptr [[TMP]], align 42429// CHECK10-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]2430// CHECK10-NEXT:    store ptr [[TMP4]], ptr [[_TMP1]], align 42431// CHECK10-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 42432// CHECK10-NEXT:    store i32 1, ptr [[DOTOMP_COMB_UB]], align 42433// CHECK10-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 42434// CHECK10-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 42435// CHECK10-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 42436// CHECK10-NEXT:    store i32 [[TMP5]], ptr [[T_VAR3]], align 42437// CHECK10-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC4]], ptr align 4 [[TMP1]], i32 8, i1 false)2438// CHECK10-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 02439// CHECK10-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 22440// CHECK10-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP6]]2441// CHECK10-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]2442// CHECK10:       omp.arraycpy.body:2443// CHECK10-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]2444// CHECK10-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]2445// CHECK10-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 4, i1 false)2446// CHECK10-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 12447// CHECK10-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 12448// CHECK10-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]2449// CHECK10-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]]2450// CHECK10:       omp.arraycpy.done6:2451// CHECK10-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[_TMP1]], align 4, !nonnull [[META8]], !align [[META9]]2452// CHECK10-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VAR7]], ptr align 4 [[TMP7]], i32 4, i1 false)2453// CHECK10-NEXT:    store ptr [[VAR7]], ptr [[_TMP8]], align 42454// CHECK10-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 42455// CHECK10-NEXT:    [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 42456// CHECK10-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP9]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)2457// CHECK10-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 42458// CHECK10-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 12459// CHECK10-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2460// CHECK10:       cond.true:2461// CHECK10-NEXT:    br label [[COND_END:%.*]]2462// CHECK10:       cond.false:2463// CHECK10-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 42464// CHECK10-NEXT:    br label [[COND_END]]2465// CHECK10:       cond.end:2466// CHECK10-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]2467// CHECK10-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 42468// CHECK10-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 42469// CHECK10-NEXT:    store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 42470// CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]2471// CHECK10:       omp.inner.for.cond:2472// CHECK10-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19:![0-9]+]]2473// CHECK10-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP19]]2474// CHECK10-NEXT:    [[CMP9:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]2475// CHECK10-NEXT:    br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]2476// CHECK10:       omp.inner.for.cond.cleanup:2477// CHECK10-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]2478// CHECK10:       omp.inner.for.body:2479// CHECK10-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP19]]2480// CHECK10-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP19]]2481// CHECK10-NEXT:    [[TMP17:%.*]] = load i32, ptr [[T_VAR3]], align 4, !llvm.access.group [[ACC_GRP19]]2482// CHECK10-NEXT:    store i32 [[TMP17]], ptr [[T_VAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP19]]2483// CHECK10-NEXT:    [[TMP18:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP19]]2484// CHECK10-NEXT:    [[TMP19:%.*]] = load ptr, ptr [[_TMP8]], align 4, !nonnull [[META8]], !align [[META9]], !llvm.access.group [[ACC_GRP19]]2485// CHECK10-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.omp_outlined.omp_outlined, i32 [[TMP15]], i32 [[TMP16]], ptr [[VEC4]], i32 [[TMP18]], ptr [[S_ARR5]], ptr [[TMP19]]), !llvm.access.group [[ACC_GRP19]]2486// CHECK10-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]2487// CHECK10:       omp.inner.for.inc:2488// CHECK10-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]]2489// CHECK10-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP19]]2490// CHECK10-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]2491// CHECK10-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]]2492// CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]2493// CHECK10:       omp.inner.for.end:2494// CHECK10-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]2495// CHECK10:       omp.loop.exit:2496// CHECK10-NEXT:    [[TMP22:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 42497// CHECK10-NEXT:    [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 42498// CHECK10-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP23]])2499// CHECK10-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 42500// CHECK10-NEXT:    [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 02501// CHECK10-NEXT:    br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]2502// CHECK10:       .omp.final.then:2503// CHECK10-NEXT:    store i32 2, ptr [[I]], align 42504// CHECK10-NEXT:    br label [[DOTOMP_FINAL_DONE]]2505// CHECK10:       .omp.final.done:2506// CHECK10-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]]2507// CHECK10-NEXT:    [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 02508// CHECK10-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i32 22509// CHECK10-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]2510// CHECK10:       arraydestroy.body:2511// CHECK10-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP26]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]2512// CHECK10-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -12513// CHECK10-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]2514// CHECK10-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]2515// CHECK10-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]2516// CHECK10:       arraydestroy.done11:2517// CHECK10-NEXT:    ret void2518//2519//2520// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.omp_outlined.omp_outlined2521// CHECK10-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {2522// CHECK10-NEXT:  entry:2523// CHECK10-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 42524// CHECK10-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 42525// CHECK10-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 42526// CHECK10-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 42527// CHECK10-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 42528// CHECK10-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 42529// CHECK10-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 42530// CHECK10-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 42531// CHECK10-NEXT:    [[TMP:%.*]] = alloca ptr, align 42532// CHECK10-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 42533// CHECK10-NEXT:    [[_TMP1:%.*]] = alloca i32, align 42534// CHECK10-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 42535// CHECK10-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 42536// CHECK10-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42537// CHECK10-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42538// CHECK10-NEXT:    [[VEC2:%.*]] = alloca [2 x i32], align 42539// CHECK10-NEXT:    [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 42540// CHECK10-NEXT:    [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 42541// CHECK10-NEXT:    [[_TMP6:%.*]] = alloca ptr, align 42542// CHECK10-NEXT:    [[I:%.*]] = alloca i32, align 42543// CHECK10-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 42544// CHECK10-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 42545// CHECK10-NEXT:    store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 42546// CHECK10-NEXT:    store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 42547// CHECK10-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 42548// CHECK10-NEXT:    store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 42549// CHECK10-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 42550// CHECK10-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 42551// CHECK10-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]2552// CHECK10-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]2553// CHECK10-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]2554// CHECK10-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 42555// CHECK10-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 42556// CHECK10-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 42557// CHECK10-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 42558// CHECK10-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 42559// CHECK10-NEXT:    store i32 [[TMP3]], ptr [[DOTOMP_LB]], align 42560// CHECK10-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 42561// CHECK10-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 42562// CHECK10-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 42563// CHECK10-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false)2564// CHECK10-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 02565// CHECK10-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 22566// CHECK10-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]]2567// CHECK10-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]2568// CHECK10:       omp.arraycpy.body:2569// CHECK10-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]2570// CHECK10-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]2571// CHECK10-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 4, i1 false)2572// CHECK10-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 12573// CHECK10-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 12574// CHECK10-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]]2575// CHECK10-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]2576// CHECK10:       omp.arraycpy.done4:2577// CHECK10-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]2578// CHECK10-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VAR5]], ptr align 4 [[TMP6]], i32 4, i1 false)2579// CHECK10-NEXT:    store ptr [[VAR5]], ptr [[_TMP6]], align 42580// CHECK10-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 42581// CHECK10-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 42582// CHECK10-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP8]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)2583// CHECK10-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42584// CHECK10-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 12585// CHECK10-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2586// CHECK10:       cond.true:2587// CHECK10-NEXT:    br label [[COND_END:%.*]]2588// CHECK10:       cond.false:2589// CHECK10-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42590// CHECK10-NEXT:    br label [[COND_END]]2591// CHECK10:       cond.end:2592// CHECK10-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]2593// CHECK10-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 42594// CHECK10-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42595// CHECK10-NEXT:    store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 42596// CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]2597// CHECK10:       omp.inner.for.cond:2598// CHECK10-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22:![0-9]+]]2599// CHECK10-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP22]]2600// CHECK10-NEXT:    [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]2601// CHECK10-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]2602// CHECK10:       omp.inner.for.cond.cleanup:2603// CHECK10-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]2604// CHECK10:       omp.inner.for.body:2605// CHECK10-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]2606// CHECK10-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP14]], 12607// CHECK10-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]2608// CHECK10-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]]2609// CHECK10-NEXT:    [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP22]]2610// CHECK10-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]]2611// CHECK10-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i32 0, i32 [[TMP16]]2612// CHECK10-NEXT:    store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]]2613// CHECK10-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[_TMP6]], align 4, !nonnull [[META8]], !align [[META9]], !llvm.access.group [[ACC_GRP22]]2614// CHECK10-NEXT:    [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]]2615// CHECK10-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 [[TMP18]]2616// CHECK10-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP17]], i32 4, i1 false), !llvm.access.group [[ACC_GRP22]]2617// CHECK10-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]2618// CHECK10:       omp.body.continue:2619// CHECK10-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]2620// CHECK10:       omp.inner.for.inc:2621// CHECK10-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]2622// CHECK10-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP19]], 12623// CHECK10-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]2624// CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]2625// CHECK10:       omp.inner.for.end:2626// CHECK10-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]2627// CHECK10:       omp.loop.exit:2628// CHECK10-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 42629// CHECK10-NEXT:    [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 42630// CHECK10-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]])2631// CHECK10-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 42632// CHECK10-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 02633// CHECK10-NEXT:    br i1 [[TMP23]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]2634// CHECK10:       .omp.final.then:2635// CHECK10-NEXT:    store i32 2, ptr [[I]], align 42636// CHECK10-NEXT:    br label [[DOTOMP_FINAL_DONE]]2637// CHECK10:       .omp.final.done:2638// CHECK10-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]2639// CHECK10-NEXT:    [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 02640// CHECK10-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i32 22641// CHECK10-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]2642// CHECK10:       arraydestroy.body:2643// CHECK10-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP24]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]2644// CHECK10-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -12645// CHECK10-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]2646// CHECK10-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]2647// CHECK10-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]2648// CHECK10:       arraydestroy.done11:2649// CHECK10-NEXT:    ret void2650//2651//2652// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev2653// CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2654// CHECK10-NEXT:  entry:2655// CHECK10-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 42656// CHECK10-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 42657// CHECK10-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42658// CHECK10-NEXT:    call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]2659// CHECK10-NEXT:    ret void2660//2661//2662// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev2663// CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2664// CHECK10-NEXT:  entry:2665// CHECK10-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 42666// CHECK10-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 42667// CHECK10-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42668// CHECK10-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 02669// CHECK10-NEXT:    store i32 0, ptr [[F]], align 42670// CHECK10-NEXT:    ret void2671//2672//2673// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei2674// CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2675// CHECK10-NEXT:  entry:2676// CHECK10-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 42677// CHECK10-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 42678// CHECK10-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 42679// CHECK10-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 42680// CHECK10-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42681// CHECK10-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 02682// CHECK10-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 42683// CHECK10-NEXT:    store i32 [[TMP0]], ptr [[F]], align 42684// CHECK10-NEXT:    ret void2685//2686//2687// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev2688// CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2689// CHECK10-NEXT:  entry:2690// CHECK10-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 42691// CHECK10-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 42692// CHECK10-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42693// CHECK10-NEXT:    ret void2694//2695//2696// CHECK12-LABEL: define {{[^@]+}}@main2697// CHECK12-SAME: () #[[ATTR0:[0-9]+]] {2698// CHECK12-NEXT:  entry:2699// CHECK12-NEXT:    [[RETVAL:%.*]] = alloca i32, align 42700// CHECK12-NEXT:    [[G:%.*]] = alloca double, align 82701// CHECK12-NEXT:    [[G1:%.*]] = alloca ptr, align 82702// CHECK12-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 42703// CHECK12-NEXT:    [[T_VAR:%.*]] = alloca i32, align 42704// CHECK12-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 42705// CHECK12-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S], align 42706// CHECK12-NEXT:    [[VAR:%.*]] = alloca ptr, align 82707// CHECK12-NEXT:    [[TMP:%.*]] = alloca ptr, align 82708// CHECK12-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 82709// CHECK12-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 82710// CHECK12-NEXT:    [[_TMP3:%.*]] = alloca i32, align 42711// CHECK12-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 42712// CHECK12-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 42713// CHECK12-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 42714// CHECK12-NEXT:    [[I:%.*]] = alloca i32, align 42715// CHECK12-NEXT:    store i32 0, ptr [[RETVAL]], align 42716// CHECK12-NEXT:    store ptr [[G]], ptr [[G1]], align 82717// CHECK12-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])2718// CHECK12-NEXT:    store i32 0, ptr [[T_VAR]], align 42719// CHECK12-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i64 8, i1 false)2720// CHECK12-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], float noundef 1.000000e+00)2721// CHECK12-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i64 12722// CHECK12-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00)2723// CHECK12-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 82724// CHECK12-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8, !nonnull [[META2:![0-9]+]], !align [[META3:![0-9]+]]2725// CHECK12-NEXT:    store ptr [[TMP0]], ptr [[TMP]], align 82726// CHECK12-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[VAR]], align 8, !nonnull [[META2]], !align [[META3]]2727// CHECK12-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META2]], !align [[META3]]2728// CHECK12-NEXT:    store ptr [[TMP2]], ptr [[_TMP1]], align 82729// CHECK12-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META2]], !align [[META3]]2730// CHECK12-NEXT:    store ptr [[TMP3]], ptr [[_TMP2]], align 82731// CHECK12-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 42732// CHECK12-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 42733// CHECK12-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42734// CHECK12-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 42735// CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]2736// CHECK12:       omp.inner.for.cond:2737// CHECK12-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4:![0-9]+]]2738// CHECK12-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP4]]2739// CHECK12-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]2740// CHECK12-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2741// CHECK12:       omp.inner.for.body:2742// CHECK12-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]2743// CHECK12-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 12744// CHECK12-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]2745// CHECK12-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]]2746// CHECK12-NEXT:    [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP4]]2747// CHECK12-NEXT:    [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]]2748// CHECK12-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i642749// CHECK12-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]]2750// CHECK12-NEXT:    store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP4]]2751// CHECK12-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META2]], !align [[META3]], !llvm.access.group [[ACC_GRP4]]2752// CHECK12-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]]2753// CHECK12-NEXT:    [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i642754// CHECK12-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]]2755// CHECK12-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group [[ACC_GRP4]]2756// CHECK12-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]2757// CHECK12:       omp.body.continue:2758// CHECK12-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]2759// CHECK12:       omp.inner.for.inc:2760// CHECK12-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]2761// CHECK12-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP12]], 12762// CHECK12-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]2763// CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]2764// CHECK12:       omp.inner.for.end:2765// CHECK12-NEXT:    store i32 2, ptr [[I]], align 42766// CHECK12-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()2767// CHECK12-NEXT:    store i32 [[CALL]], ptr [[RETVAL]], align 42768// CHECK12-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 02769// CHECK12-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 22770// CHECK12-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]2771// CHECK12:       arraydestroy.body:2772// CHECK12-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]2773// CHECK12-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -12774// CHECK12-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]]2775// CHECK12-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]2776// CHECK12-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]2777// CHECK12:       arraydestroy.done7:2778// CHECK12-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]]2779// CHECK12-NEXT:    [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 42780// CHECK12-NEXT:    ret i32 [[TMP14]]2781//2782//2783// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev2784// CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {2785// CHECK12-NEXT:  entry:2786// CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82787// CHECK12-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82788// CHECK12-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82789// CHECK12-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])2790// CHECK12-NEXT:    ret void2791//2792//2793// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef2794// CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {2795// CHECK12-NEXT:  entry:2796// CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82797// CHECK12-NEXT:    [[A_ADDR:%.*]] = alloca float, align 42798// CHECK12-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82799// CHECK12-NEXT:    store float [[A]], ptr [[A_ADDR]], align 42800// CHECK12-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82801// CHECK12-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 42802// CHECK12-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])2803// CHECK12-NEXT:    ret void2804//2805//2806// CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiET_v2807// CHECK12-SAME: () #[[ATTR1]] comdat {2808// CHECK12-NEXT:  entry:2809// CHECK12-NEXT:    [[RETVAL:%.*]] = alloca i32, align 42810// CHECK12-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 42811// CHECK12-NEXT:    [[T_VAR:%.*]] = alloca i32, align 42812// CHECK12-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 42813// CHECK12-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 42814// CHECK12-NEXT:    [[VAR:%.*]] = alloca ptr, align 82815// CHECK12-NEXT:    [[TMP:%.*]] = alloca ptr, align 82816// CHECK12-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 82817// CHECK12-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 82818// CHECK12-NEXT:    [[_TMP3:%.*]] = alloca i32, align 42819// CHECK12-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 42820// CHECK12-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 42821// CHECK12-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 42822// CHECK12-NEXT:    [[I:%.*]] = alloca i32, align 42823// CHECK12-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])2824// CHECK12-NEXT:    store i32 0, ptr [[T_VAR]], align 42825// CHECK12-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)2826// CHECK12-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef signext 1)2827// CHECK12-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 12828// CHECK12-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2)2829// CHECK12-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 82830// CHECK12-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8, !nonnull [[META2]], !align [[META3]]2831// CHECK12-NEXT:    store ptr [[TMP0]], ptr [[TMP]], align 82832// CHECK12-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[VAR]], align 8, !nonnull [[META2]], !align [[META3]]2833// CHECK12-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META2]], !align [[META3]]2834// CHECK12-NEXT:    store ptr [[TMP2]], ptr [[_TMP1]], align 82835// CHECK12-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META2]], !align [[META3]]2836// CHECK12-NEXT:    store ptr [[TMP3]], ptr [[_TMP2]], align 82837// CHECK12-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 42838// CHECK12-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 42839// CHECK12-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42840// CHECK12-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 42841// CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]2842// CHECK12:       omp.inner.for.cond:2843// CHECK12-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8:![0-9]+]]2844// CHECK12-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP8]]2845// CHECK12-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]2846// CHECK12-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2847// CHECK12:       omp.inner.for.body:2848// CHECK12-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]2849// CHECK12-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 12850// CHECK12-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]2851// CHECK12-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]]2852// CHECK12-NEXT:    [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP8]]2853// CHECK12-NEXT:    [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]]2854// CHECK12-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i642855// CHECK12-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]]2856// CHECK12-NEXT:    store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP8]]2857// CHECK12-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META2]], !align [[META3]], !llvm.access.group [[ACC_GRP8]]2858// CHECK12-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]]2859// CHECK12-NEXT:    [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i642860// CHECK12-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]]2861// CHECK12-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group [[ACC_GRP8]]2862// CHECK12-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]2863// CHECK12:       omp.body.continue:2864// CHECK12-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]2865// CHECK12:       omp.inner.for.inc:2866// CHECK12-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]2867// CHECK12-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP12]], 12868// CHECK12-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]2869// CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]2870// CHECK12:       omp.inner.for.end:2871// CHECK12-NEXT:    store i32 2, ptr [[I]], align 42872// CHECK12-NEXT:    store i32 0, ptr [[RETVAL]], align 42873// CHECK12-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 02874// CHECK12-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 22875// CHECK12-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]2876// CHECK12:       arraydestroy.body:2877// CHECK12-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]2878// CHECK12-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -12879// CHECK12-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]2880// CHECK12-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]2881// CHECK12-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]2882// CHECK12:       arraydestroy.done7:2883// CHECK12-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]]2884// CHECK12-NEXT:    [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 42885// CHECK12-NEXT:    ret i32 [[TMP14]]2886//2887//2888// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev2889// CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {2890// CHECK12-NEXT:  entry:2891// CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82892// CHECK12-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82893// CHECK12-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82894// CHECK12-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]]2895// CHECK12-NEXT:    ret void2896//2897//2898// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev2899// CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {2900// CHECK12-NEXT:  entry:2901// CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82902// CHECK12-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82903// CHECK12-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82904// CHECK12-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 02905// CHECK12-NEXT:    store float 0.000000e+00, ptr [[F]], align 42906// CHECK12-NEXT:    ret void2907//2908//2909// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev2910// CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {2911// CHECK12-NEXT:  entry:2912// CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82913// CHECK12-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82914// CHECK12-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82915// CHECK12-NEXT:    ret void2916//2917//2918// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef2919// CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {2920// CHECK12-NEXT:  entry:2921// CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82922// CHECK12-NEXT:    [[A_ADDR:%.*]] = alloca float, align 42923// CHECK12-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82924// CHECK12-NEXT:    store float [[A]], ptr [[A_ADDR]], align 42925// CHECK12-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82926// CHECK12-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 02927// CHECK12-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 42928// CHECK12-NEXT:    store float [[TMP0]], ptr [[F]], align 42929// CHECK12-NEXT:    ret void2930//2931//2932// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev2933// CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {2934// CHECK12-NEXT:  entry:2935// CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82936// CHECK12-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82937// CHECK12-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82938// CHECK12-NEXT:    call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])2939// CHECK12-NEXT:    ret void2940//2941//2942// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei2943// CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {2944// CHECK12-NEXT:  entry:2945// CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82946// CHECK12-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 42947// CHECK12-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82948// CHECK12-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 42949// CHECK12-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82950// CHECK12-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 42951// CHECK12-NEXT:    call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])2952// CHECK12-NEXT:    ret void2953//2954//2955// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev2956// CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {2957// CHECK12-NEXT:  entry:2958// CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82959// CHECK12-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82960// CHECK12-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82961// CHECK12-NEXT:    call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]]2962// CHECK12-NEXT:    ret void2963//2964//2965// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev2966// CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {2967// CHECK12-NEXT:  entry:2968// CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82969// CHECK12-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82970// CHECK12-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82971// CHECK12-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 02972// CHECK12-NEXT:    store i32 0, ptr [[F]], align 42973// CHECK12-NEXT:    ret void2974//2975//2976// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei2977// CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {2978// CHECK12-NEXT:  entry:2979// CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82980// CHECK12-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 42981// CHECK12-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82982// CHECK12-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 42983// CHECK12-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82984// CHECK12-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 02985// CHECK12-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 42986// CHECK12-NEXT:    store i32 [[TMP0]], ptr [[F]], align 42987// CHECK12-NEXT:    ret void2988//2989//2990// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev2991// CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {2992// CHECK12-NEXT:  entry:2993// CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82994// CHECK12-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82995// CHECK12-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82996// CHECK12-NEXT:    ret void2997//2998//2999// CHECK14-LABEL: define {{[^@]+}}@main3000// CHECK14-SAME: () #[[ATTR0:[0-9]+]] {3001// CHECK14-NEXT:  entry:3002// CHECK14-NEXT:    [[RETVAL:%.*]] = alloca i32, align 43003// CHECK14-NEXT:    [[G:%.*]] = alloca double, align 83004// CHECK14-NEXT:    [[G1:%.*]] = alloca ptr, align 43005// CHECK14-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 43006// CHECK14-NEXT:    [[T_VAR:%.*]] = alloca i32, align 43007// CHECK14-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 43008// CHECK14-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S], align 43009// CHECK14-NEXT:    [[VAR:%.*]] = alloca ptr, align 43010// CHECK14-NEXT:    [[TMP:%.*]] = alloca ptr, align 43011// CHECK14-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 43012// CHECK14-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 43013// CHECK14-NEXT:    [[_TMP3:%.*]] = alloca i32, align 43014// CHECK14-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 43015// CHECK14-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 43016// CHECK14-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 43017// CHECK14-NEXT:    [[I:%.*]] = alloca i32, align 43018// CHECK14-NEXT:    store i32 0, ptr [[RETVAL]], align 43019// CHECK14-NEXT:    store ptr [[G]], ptr [[G1]], align 43020// CHECK14-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])3021// CHECK14-NEXT:    store i32 0, ptr [[T_VAR]], align 43022// CHECK14-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i32 8, i1 false)3023// CHECK14-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], float noundef 1.000000e+00)3024// CHECK14-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i32 13025// CHECK14-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00)3026// CHECK14-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 43027// CHECK14-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]]3028// CHECK14-NEXT:    store ptr [[TMP0]], ptr [[TMP]], align 43029// CHECK14-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[VAR]], align 4, !nonnull [[META3]], !align [[META4]]3030// CHECK14-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META3]], !align [[META4]]3031// CHECK14-NEXT:    store ptr [[TMP2]], ptr [[_TMP1]], align 43032// CHECK14-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[_TMP1]], align 4, !nonnull [[META3]], !align [[META4]]3033// CHECK14-NEXT:    store ptr [[TMP3]], ptr [[_TMP2]], align 43034// CHECK14-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 43035// CHECK14-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 43036// CHECK14-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 43037// CHECK14-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 43038// CHECK14-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]3039// CHECK14:       omp.inner.for.cond:3040// CHECK14-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]]3041// CHECK14-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP5]]3042// CHECK14-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]3043// CHECK14-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]3044// CHECK14:       omp.inner.for.body:3045// CHECK14-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]3046// CHECK14-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 13047// CHECK14-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]3048// CHECK14-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]]3049// CHECK14-NEXT:    [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP5]]3050// CHECK14-NEXT:    [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]]3051// CHECK14-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]]3052// CHECK14-NEXT:    store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]]3053// CHECK14-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META3]], !align [[META4]], !llvm.access.group [[ACC_GRP5]]3054// CHECK14-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]]3055// CHECK14-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP11]]3056// CHECK14-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group [[ACC_GRP5]]3057// CHECK14-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]3058// CHECK14:       omp.body.continue:3059// CHECK14-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]3060// CHECK14:       omp.inner.for.inc:3061// CHECK14-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]3062// CHECK14-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP12]], 13063// CHECK14-NEXT:    store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]3064// CHECK14-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]3065// CHECK14:       omp.inner.for.end:3066// CHECK14-NEXT:    store i32 2, ptr [[I]], align 43067// CHECK14-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()3068// CHECK14-NEXT:    store i32 [[CALL]], ptr [[RETVAL]], align 43069// CHECK14-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 03070// CHECK14-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 23071// CHECK14-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]3072// CHECK14:       arraydestroy.body:3073// CHECK14-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]3074// CHECK14-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -13075// CHECK14-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]]3076// CHECK14-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]3077// CHECK14-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]3078// CHECK14:       arraydestroy.done6:3079// CHECK14-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]]3080// CHECK14-NEXT:    [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 43081// CHECK14-NEXT:    ret i32 [[TMP14]]3082//3083//3084// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev3085// CHECK14-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {3086// CHECK14-NEXT:  entry:3087// CHECK14-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 43088// CHECK14-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 43089// CHECK14-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 43090// CHECK14-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])3091// CHECK14-NEXT:    ret void3092//3093//3094// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef3095// CHECK14-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {3096// CHECK14-NEXT:  entry:3097// CHECK14-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 43098// CHECK14-NEXT:    [[A_ADDR:%.*]] = alloca float, align 43099// CHECK14-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 43100// CHECK14-NEXT:    store float [[A]], ptr [[A_ADDR]], align 43101// CHECK14-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 43102// CHECK14-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 43103// CHECK14-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])3104// CHECK14-NEXT:    ret void3105//3106//3107// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiET_v3108// CHECK14-SAME: () #[[ATTR1]] comdat {3109// CHECK14-NEXT:  entry:3110// CHECK14-NEXT:    [[RETVAL:%.*]] = alloca i32, align 43111// CHECK14-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 43112// CHECK14-NEXT:    [[T_VAR:%.*]] = alloca i32, align 43113// CHECK14-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 43114// CHECK14-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 43115// CHECK14-NEXT:    [[VAR:%.*]] = alloca ptr, align 43116// CHECK14-NEXT:    [[TMP:%.*]] = alloca ptr, align 43117// CHECK14-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 43118// CHECK14-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 43119// CHECK14-NEXT:    [[_TMP3:%.*]] = alloca i32, align 43120// CHECK14-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 43121// CHECK14-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 43122// CHECK14-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 43123// CHECK14-NEXT:    [[I:%.*]] = alloca i32, align 43124// CHECK14-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])3125// CHECK14-NEXT:    store i32 0, ptr [[T_VAR]], align 43126// CHECK14-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false)3127// CHECK14-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1)3128// CHECK14-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 13129// CHECK14-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)3130// CHECK14-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 43131// CHECK14-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4, !nonnull [[META3]], !align [[META4]]3132// CHECK14-NEXT:    store ptr [[TMP0]], ptr [[TMP]], align 43133// CHECK14-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[VAR]], align 4, !nonnull [[META3]], !align [[META4]]3134// CHECK14-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META3]], !align [[META4]]3135// CHECK14-NEXT:    store ptr [[TMP2]], ptr [[_TMP1]], align 43136// CHECK14-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[_TMP1]], align 4, !nonnull [[META3]], !align [[META4]]3137// CHECK14-NEXT:    store ptr [[TMP3]], ptr [[_TMP2]], align 43138// CHECK14-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 43139// CHECK14-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 43140// CHECK14-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 43141// CHECK14-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 43142// CHECK14-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]3143// CHECK14:       omp.inner.for.cond:3144// CHECK14-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]]3145// CHECK14-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP9]]3146// CHECK14-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]3147// CHECK14-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]3148// CHECK14:       omp.inner.for.body:3149// CHECK14-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]3150// CHECK14-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 13151// CHECK14-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]3152// CHECK14-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]3153// CHECK14-NEXT:    [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP9]]3154// CHECK14-NEXT:    [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]3155// CHECK14-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]]3156// CHECK14-NEXT:    store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]]3157// CHECK14-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META3]], !align [[META4]], !llvm.access.group [[ACC_GRP9]]3158// CHECK14-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]3159// CHECK14-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP11]]3160// CHECK14-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group [[ACC_GRP9]]3161// CHECK14-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]3162// CHECK14:       omp.body.continue:3163// CHECK14-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]3164// CHECK14:       omp.inner.for.inc:3165// CHECK14-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]3166// CHECK14-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP12]], 13167// CHECK14-NEXT:    store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]3168// CHECK14-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]3169// CHECK14:       omp.inner.for.end:3170// CHECK14-NEXT:    store i32 2, ptr [[I]], align 43171// CHECK14-NEXT:    store i32 0, ptr [[RETVAL]], align 43172// CHECK14-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 03173// CHECK14-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 23174// CHECK14-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]3175// CHECK14:       arraydestroy.body:3176// CHECK14-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]3177// CHECK14-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -13178// CHECK14-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]3179// CHECK14-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]3180// CHECK14-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]3181// CHECK14:       arraydestroy.done6:3182// CHECK14-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]]3183// CHECK14-NEXT:    [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 43184// CHECK14-NEXT:    ret i32 [[TMP14]]3185//3186//3187// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev3188// CHECK14-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {3189// CHECK14-NEXT:  entry:3190// CHECK14-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 43191// CHECK14-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 43192// CHECK14-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 43193// CHECK14-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]]3194// CHECK14-NEXT:    ret void3195//3196//3197// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev3198// CHECK14-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {3199// CHECK14-NEXT:  entry:3200// CHECK14-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 43201// CHECK14-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 43202// CHECK14-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 43203// CHECK14-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 03204// CHECK14-NEXT:    store float 0.000000e+00, ptr [[F]], align 43205// CHECK14-NEXT:    ret void3206//3207//3208// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev3209// CHECK14-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {3210// CHECK14-NEXT:  entry:3211// CHECK14-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 43212// CHECK14-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 43213// CHECK14-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 43214// CHECK14-NEXT:    ret void3215//3216//3217// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef3218// CHECK14-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {3219// CHECK14-NEXT:  entry:3220// CHECK14-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 43221// CHECK14-NEXT:    [[A_ADDR:%.*]] = alloca float, align 43222// CHECK14-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 43223// CHECK14-NEXT:    store float [[A]], ptr [[A_ADDR]], align 43224// CHECK14-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 43225// CHECK14-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 03226// CHECK14-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 43227// CHECK14-NEXT:    store float [[TMP0]], ptr [[F]], align 43228// CHECK14-NEXT:    ret void3229//3230//3231// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev3232// CHECK14-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {3233// CHECK14-NEXT:  entry:3234// CHECK14-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 43235// CHECK14-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 43236// CHECK14-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 43237// CHECK14-NEXT:    call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])3238// CHECK14-NEXT:    ret void3239//3240//3241// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei3242// CHECK14-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {3243// CHECK14-NEXT:  entry:3244// CHECK14-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 43245// CHECK14-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 43246// CHECK14-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 43247// CHECK14-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 43248// CHECK14-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 43249// CHECK14-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 43250// CHECK14-NEXT:    call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])3251// CHECK14-NEXT:    ret void3252//3253//3254// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev3255// CHECK14-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {3256// CHECK14-NEXT:  entry:3257// CHECK14-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 43258// CHECK14-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 43259// CHECK14-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 43260// CHECK14-NEXT:    call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]]3261// CHECK14-NEXT:    ret void3262//3263//3264// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev3265// CHECK14-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {3266// CHECK14-NEXT:  entry:3267// CHECK14-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 43268// CHECK14-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 43269// CHECK14-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 43270// CHECK14-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 03271// CHECK14-NEXT:    store i32 0, ptr [[F]], align 43272// CHECK14-NEXT:    ret void3273//3274//3275// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei3276// CHECK14-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {3277// CHECK14-NEXT:  entry:3278// CHECK14-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 43279// CHECK14-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 43280// CHECK14-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 43281// CHECK14-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 43282// CHECK14-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 43283// CHECK14-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 03284// CHECK14-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 43285// CHECK14-NEXT:    store i32 [[TMP0]], ptr [[F]], align 43286// CHECK14-NEXT:    ret void3287//3288//3289// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev3290// CHECK14-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {3291// CHECK14-NEXT:  entry:3292// CHECK14-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 43293// CHECK14-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 43294// CHECK14-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 43295// CHECK14-NEXT:    ret void3296//3297