2476 lines · cpp
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _2// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK13// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s4// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK15// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK36// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s7// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK38 9// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK510// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s11// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK512// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK713// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s14// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK715 16// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK917// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s18// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK919// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK1120// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s21// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK1122 23// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK1324// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s25// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK1326// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK1527// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s28// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK1529// expected-no-diagnostics30#ifndef HEADER31#define HEADER32 33template <class T>34struct S {35 T f;36 S(T a) : f(a) {}37 S() : f() {}38 operator T() { return T(); }39 ~S() {}40};41 42template <typename T>43T tmain() {44 S<T> test;45 T t_var = T();46 T vec[] = {1, 2};47 S<T> s_arr[] = {1, 2};48 S<T> &var = test;49 #pragma omp target50 #pragma omp teams51#pragma omp distribute simd firstprivate(t_var, vec, s_arr, s_arr, var, var)52 for (int i = 0; i < 2; ++i) {53 vec[i] = t_var;54 s_arr[i] = var;55 }56 return T();57}58 59int main() {60 static int svar;61 volatile double g;62 volatile double &g1 = g;63 64 #ifdef LAMBDA65 [&]() {66 static float sfvar;67 68 #pragma omp target69 #pragma omp teams70#pragma omp distribute simd firstprivate(g, g1, svar, sfvar)71 for (int i = 0; i < 2; ++i) {72 // Private alloca's for conversion73 74 // Actual private variables to be used in the body (tmp is used for the reference type)75 76 // Store input parameter addresses into private alloca's for conversion77 78 79 80 g += 1;81 g1 += 1;82 svar += 3;83 sfvar += 4.0;84 85 // call inner lambda (use refs to private alloca's)86 [&]() {87 g += 2;88 g1 += 2;89 svar += 4;90 sfvar += 8.0;91 92 93 94 }();95 }96 }();97 return 0;98 #else99 S<float> test;100 int t_var = 0;101 int vec[] = {1, 2};102 S<float> s_arr[] = {1, 2};103 S<float> &var = test;104 105 #pragma omp target106 #pragma omp teams107 #pragma omp distribute simd firstprivate(t_var, vec, s_arr, s_arr, var, var, svar)108 for (int i = 0; i < 2; ++i) {109 vec[i] = t_var;110 s_arr[i] = var;111 }112 return tmain<int>();113 #endif114}115 116 117 118 119// discard omp loop variables120 121 122 123// init t_var124 125// init vec126 127// init s_arr128 129 130// init var131 132// init svar133 134 135 136// Template137 138 139 140// discard omp loop variables141 142 143 144// init t_var145 146// init vec147 148// init s_arr149 150 151// init var152 153 154 155#endif156// CHECK1-LABEL: define {{[^@]+}}@main157// CHECK1-SAME: () #[[ATTR0:[0-9]+]] {158// CHECK1-NEXT: entry:159// CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4160// CHECK1-NEXT: [[G:%.*]] = alloca double, align 8161// CHECK1-NEXT: [[G1:%.*]] = alloca ptr, align 8162// CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8163// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4164// CHECK1-NEXT: store ptr [[G]], ptr [[G1]], align 8165// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0166// CHECK1-NEXT: store ptr [[G]], ptr [[TMP0]], align 8167// CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1168// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]]169// CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP1]], align 8170// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP]])171// CHECK1-NEXT: ret i32 0172//173//174// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68175// CHECK1-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] {176// CHECK1-NEXT: entry:177// CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8178// CHECK1-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8179// CHECK1-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8180// CHECK1-NEXT: [[SFVAR_ADDR:%.*]] = alloca i64, align 8181// CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8182// CHECK1-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 8183// CHECK1-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 8184// CHECK1-NEXT: store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8185// CHECK1-NEXT: store i64 [[SFVAR]], ptr [[SFVAR_ADDR]], align 8186// CHECK1-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8187// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]]188// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined, ptr [[G_ADDR]], ptr [[TMP0]], ptr [[SVAR_ADDR]], ptr [[SFVAR_ADDR]])189// CHECK1-NEXT: ret void190//191//192// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined193// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[G:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[G1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] {194// CHECK1-NEXT: entry:195// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8196// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8197// CHECK1-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 8198// CHECK1-NEXT: [[G1_ADDR:%.*]] = alloca ptr, align 8199// CHECK1-NEXT: [[SVAR_ADDR:%.*]] = alloca ptr, align 8200// CHECK1-NEXT: [[SFVAR_ADDR:%.*]] = alloca ptr, align 8201// CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8202// CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8203// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4204// CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4205// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4206// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4207// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4208// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4209// CHECK1-NEXT: [[G3:%.*]] = alloca double, align 8210// CHECK1-NEXT: [[G14:%.*]] = alloca double, align 8211// CHECK1-NEXT: [[_TMP5:%.*]] = alloca ptr, align 8212// CHECK1-NEXT: [[SVAR6:%.*]] = alloca i32, align 4213// CHECK1-NEXT: [[SFVAR7:%.*]] = alloca float, align 4214// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4215// CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8216// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8217// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8218// CHECK1-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 8219// CHECK1-NEXT: store ptr [[G1]], ptr [[G1_ADDR]], align 8220// CHECK1-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 8221// CHECK1-NEXT: store ptr [[SFVAR]], ptr [[SFVAR_ADDR]], align 8222// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]223// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]224// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 8, !nonnull [[META5]], !align [[META7:![0-9]+]]225// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SFVAR_ADDR]], align 8, !nonnull [[META5]], !align [[META7]]226// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8227// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]]228// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8229// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4230// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4231// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4232// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4233// CHECK1-NEXT: [[TMP5:%.*]] = load volatile double, ptr [[TMP0]], align 8234// CHECK1-NEXT: store double [[TMP5]], ptr [[G3]], align 8235// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META6]]236// CHECK1-NEXT: [[TMP7:%.*]] = load volatile double, ptr [[TMP6]], align 8237// CHECK1-NEXT: store double [[TMP7]], ptr [[G14]], align 8238// CHECK1-NEXT: store ptr [[G14]], ptr [[_TMP5]], align 8239// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP2]], align 4240// CHECK1-NEXT: store i32 [[TMP8]], ptr [[SVAR6]], align 4241// CHECK1-NEXT: [[TMP9:%.*]] = load float, ptr [[TMP3]], align 4242// CHECK1-NEXT: store float [[TMP9]], ptr [[SFVAR7]], align 4243// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8244// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4245// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)246// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4247// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1248// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]249// CHECK1: cond.true:250// CHECK1-NEXT: br label [[COND_END:%.*]]251// CHECK1: cond.false:252// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4253// CHECK1-NEXT: br label [[COND_END]]254// CHECK1: cond.end:255// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]256// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4257// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4258// CHECK1-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV]], align 4259// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]260// CHECK1: omp.inner.for.cond:261// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8:![0-9]+]]262// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP8]]263// CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]264// CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]265// CHECK1: omp.inner.for.body:266// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]267// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1268// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]269// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]]270// CHECK1-NEXT: [[TMP18:%.*]] = load double, ptr [[G3]], align 8, !llvm.access.group [[ACC_GRP8]]271// CHECK1-NEXT: [[ADD9:%.*]] = fadd double [[TMP18]], 1.000000e+00272// CHECK1-NEXT: store double [[ADD9]], ptr [[G3]], align 8, !llvm.access.group [[ACC_GRP8]]273// CHECK1-NEXT: [[TMP19:%.*]] = load ptr, ptr [[_TMP5]], align 8, !nonnull [[META5]], !align [[META6]], !llvm.access.group [[ACC_GRP8]]274// CHECK1-NEXT: [[TMP20:%.*]] = load volatile double, ptr [[TMP19]], align 8, !llvm.access.group [[ACC_GRP8]]275// CHECK1-NEXT: [[ADD10:%.*]] = fadd double [[TMP20]], 1.000000e+00276// CHECK1-NEXT: store volatile double [[ADD10]], ptr [[TMP19]], align 8, !llvm.access.group [[ACC_GRP8]]277// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[SVAR6]], align 4, !llvm.access.group [[ACC_GRP8]]278// CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 3279// CHECK1-NEXT: store i32 [[ADD11]], ptr [[SVAR6]], align 4, !llvm.access.group [[ACC_GRP8]]280// CHECK1-NEXT: [[TMP22:%.*]] = load float, ptr [[SFVAR7]], align 4, !llvm.access.group [[ACC_GRP8]]281// CHECK1-NEXT: [[CONV:%.*]] = fpext float [[TMP22]] to double282// CHECK1-NEXT: [[ADD12:%.*]] = fadd double [[CONV]], 4.000000e+00283// CHECK1-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float284// CHECK1-NEXT: store float [[CONV13]], ptr [[SFVAR7]], align 4, !llvm.access.group [[ACC_GRP8]]285// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0286// CHECK1-NEXT: store ptr [[G3]], ptr [[TMP23]], align 8, !llvm.access.group [[ACC_GRP8]]287// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1288// CHECK1-NEXT: [[TMP25:%.*]] = load ptr, ptr [[_TMP5]], align 8, !nonnull [[META5]], !align [[META6]], !llvm.access.group [[ACC_GRP8]]289// CHECK1-NEXT: store ptr [[TMP25]], ptr [[TMP24]], align 8, !llvm.access.group [[ACC_GRP8]]290// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2291// CHECK1-NEXT: store ptr [[SVAR6]], ptr [[TMP26]], align 8, !llvm.access.group [[ACC_GRP8]]292// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 3293// CHECK1-NEXT: store ptr [[SFVAR7]], ptr [[TMP27]], align 8, !llvm.access.group [[ACC_GRP8]]294// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group [[ACC_GRP8]]295// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]296// CHECK1: omp.body.continue:297// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]298// CHECK1: omp.inner.for.inc:299// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]300// CHECK1-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP28]], 1301// CHECK1-NEXT: store i32 [[ADD14]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]302// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]303// CHECK1: omp.inner.for.end:304// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]305// CHECK1: omp.loop.exit:306// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP11]])307// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4308// CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0309// CHECK1-NEXT: br i1 [[TMP30]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]310// CHECK1: .omp.final.then:311// CHECK1-NEXT: store i32 2, ptr [[I]], align 4312// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]313// CHECK1: .omp.final.done:314// CHECK1-NEXT: ret void315//316//317// CHECK3-LABEL: define {{[^@]+}}@main318// CHECK3-SAME: () #[[ATTR0:[0-9]+]] {319// CHECK3-NEXT: entry:320// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4321// CHECK3-NEXT: [[G:%.*]] = alloca double, align 8322// CHECK3-NEXT: [[G1:%.*]] = alloca ptr, align 4323// CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4324// CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4325// CHECK3-NEXT: store ptr [[G]], ptr [[G1]], align 4326// CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0327// CHECK3-NEXT: store ptr [[G]], ptr [[TMP0]], align 4328// CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1329// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 4, !nonnull [[META6:![0-9]+]], !align [[META7:![0-9]+]]330// CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP1]], align 4331// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 4 dereferenceable(8) [[REF_TMP]])332// CHECK3-NEXT: ret i32 0333//334//335// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68336// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[G:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] {337// CHECK3-NEXT: entry:338// CHECK3-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 4339// CHECK3-NEXT: [[G1_ADDR:%.*]] = alloca ptr, align 4340// CHECK3-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4341// CHECK3-NEXT: [[SFVAR_ADDR:%.*]] = alloca i32, align 4342// CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4343// CHECK3-NEXT: [[G2:%.*]] = alloca double, align 8344// CHECK3-NEXT: [[G13:%.*]] = alloca double, align 8345// CHECK3-NEXT: [[_TMP4:%.*]] = alloca ptr, align 4346// CHECK3-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 4347// CHECK3-NEXT: store ptr [[G1]], ptr [[G1_ADDR]], align 4348// CHECK3-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4349// CHECK3-NEXT: store i32 [[SFVAR]], ptr [[SFVAR_ADDR]], align 4350// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4, !nonnull [[META6]], !align [[META7]]351// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 4, !nonnull [[META6]], !align [[META7]]352// CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 4353// CHECK3-NEXT: [[TMP2:%.*]] = load double, ptr [[TMP0]], align 8354// CHECK3-NEXT: store double [[TMP2]], ptr [[G2]], align 8355// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META6]], !align [[META7]]356// CHECK3-NEXT: [[TMP4:%.*]] = load volatile double, ptr [[TMP3]], align 4357// CHECK3-NEXT: store double [[TMP4]], ptr [[G13]], align 8358// CHECK3-NEXT: store ptr [[G13]], ptr [[_TMP4]], align 4359// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP4]], align 4, !nonnull [[META6]], !align [[META7]]360// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined, ptr [[G2]], ptr [[TMP5]], ptr [[SVAR_ADDR]], ptr [[SFVAR_ADDR]])361// CHECK3-NEXT: ret void362//363//364// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined365// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[G:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] {366// CHECK3-NEXT: entry:367// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4368// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4369// CHECK3-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 4370// CHECK3-NEXT: [[G1_ADDR:%.*]] = alloca ptr, align 4371// CHECK3-NEXT: [[SVAR_ADDR:%.*]] = alloca ptr, align 4372// CHECK3-NEXT: [[SFVAR_ADDR:%.*]] = alloca ptr, align 4373// CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4374// CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4375// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4376// CHECK3-NEXT: [[_TMP2:%.*]] = alloca i32, align 4377// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4378// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4379// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4380// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4381// CHECK3-NEXT: [[G3:%.*]] = alloca double, align 8382// CHECK3-NEXT: [[G14:%.*]] = alloca double, align 8383// CHECK3-NEXT: [[_TMP5:%.*]] = alloca ptr, align 4384// CHECK3-NEXT: [[SVAR6:%.*]] = alloca i32, align 4385// CHECK3-NEXT: [[SFVAR7:%.*]] = alloca float, align 4386// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4387// CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 4388// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4389// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4390// CHECK3-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 4391// CHECK3-NEXT: store ptr [[G1]], ptr [[G1_ADDR]], align 4392// CHECK3-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 4393// CHECK3-NEXT: store ptr [[SFVAR]], ptr [[SFVAR_ADDR]], align 4394// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4, !nonnull [[META6]], !align [[META7]]395// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 4, !nonnull [[META6]], !align [[META7]]396// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 4, !nonnull [[META6]], !align [[META7]]397// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SFVAR_ADDR]], align 4, !nonnull [[META6]], !align [[META7]]398// CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 4399// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META6]], !align [[META7]]400// CHECK3-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 4401// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4402// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4403// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4404// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4405// CHECK3-NEXT: [[TMP5:%.*]] = load volatile double, ptr [[TMP0]], align 8406// CHECK3-NEXT: store double [[TMP5]], ptr [[G3]], align 8407// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 4, !nonnull [[META6]], !align [[META7]]408// CHECK3-NEXT: [[TMP7:%.*]] = load volatile double, ptr [[TMP6]], align 4409// CHECK3-NEXT: store double [[TMP7]], ptr [[G14]], align 8410// CHECK3-NEXT: store ptr [[G14]], ptr [[_TMP5]], align 4411// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP2]], align 4412// CHECK3-NEXT: store i32 [[TMP8]], ptr [[SVAR6]], align 4413// CHECK3-NEXT: [[TMP9:%.*]] = load float, ptr [[TMP3]], align 4414// CHECK3-NEXT: store float [[TMP9]], ptr [[SFVAR7]], align 4415// CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4416// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4417// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)418// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4419// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1420// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]421// CHECK3: cond.true:422// CHECK3-NEXT: br label [[COND_END:%.*]]423// CHECK3: cond.false:424// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4425// CHECK3-NEXT: br label [[COND_END]]426// CHECK3: cond.end:427// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]428// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4429// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4430// CHECK3-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV]], align 4431// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]432// CHECK3: omp.inner.for.cond:433// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8:![0-9]+]]434// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP8]]435// CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]436// CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]437// CHECK3: omp.inner.for.body:438// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]439// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1440// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]441// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]]442// CHECK3-NEXT: [[TMP18:%.*]] = load double, ptr [[G3]], align 8, !llvm.access.group [[ACC_GRP8]]443// CHECK3-NEXT: [[ADD9:%.*]] = fadd double [[TMP18]], 1.000000e+00444// CHECK3-NEXT: store double [[ADD9]], ptr [[G3]], align 8, !llvm.access.group [[ACC_GRP8]]445// CHECK3-NEXT: [[TMP19:%.*]] = load ptr, ptr [[_TMP5]], align 4, !nonnull [[META6]], !align [[META7]], !llvm.access.group [[ACC_GRP8]]446// CHECK3-NEXT: [[TMP20:%.*]] = load volatile double, ptr [[TMP19]], align 4, !llvm.access.group [[ACC_GRP8]]447// CHECK3-NEXT: [[ADD10:%.*]] = fadd double [[TMP20]], 1.000000e+00448// CHECK3-NEXT: store volatile double [[ADD10]], ptr [[TMP19]], align 4, !llvm.access.group [[ACC_GRP8]]449// CHECK3-NEXT: [[TMP21:%.*]] = load i32, ptr [[SVAR6]], align 4, !llvm.access.group [[ACC_GRP8]]450// CHECK3-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 3451// CHECK3-NEXT: store i32 [[ADD11]], ptr [[SVAR6]], align 4, !llvm.access.group [[ACC_GRP8]]452// CHECK3-NEXT: [[TMP22:%.*]] = load float, ptr [[SFVAR7]], align 4, !llvm.access.group [[ACC_GRP8]]453// CHECK3-NEXT: [[CONV:%.*]] = fpext float [[TMP22]] to double454// CHECK3-NEXT: [[ADD12:%.*]] = fadd double [[CONV]], 4.000000e+00455// CHECK3-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float456// CHECK3-NEXT: store float [[CONV13]], ptr [[SFVAR7]], align 4, !llvm.access.group [[ACC_GRP8]]457// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0458// CHECK3-NEXT: store ptr [[G3]], ptr [[TMP23]], align 4, !llvm.access.group [[ACC_GRP8]]459// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1460// CHECK3-NEXT: [[TMP25:%.*]] = load ptr, ptr [[_TMP5]], align 4, !nonnull [[META6]], !align [[META7]], !llvm.access.group [[ACC_GRP8]]461// CHECK3-NEXT: store ptr [[TMP25]], ptr [[TMP24]], align 4, !llvm.access.group [[ACC_GRP8]]462// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2463// CHECK3-NEXT: store ptr [[SVAR6]], ptr [[TMP26]], align 4, !llvm.access.group [[ACC_GRP8]]464// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 3465// CHECK3-NEXT: store ptr [[SFVAR7]], ptr [[TMP27]], align 4, !llvm.access.group [[ACC_GRP8]]466// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group [[ACC_GRP8]]467// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]468// CHECK3: omp.body.continue:469// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]470// CHECK3: omp.inner.for.inc:471// CHECK3-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]472// CHECK3-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP28]], 1473// CHECK3-NEXT: store i32 [[ADD14]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]474// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]475// CHECK3: omp.inner.for.end:476// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]477// CHECK3: omp.loop.exit:478// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP11]])479// CHECK3-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4480// CHECK3-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0481// CHECK3-NEXT: br i1 [[TMP30]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]482// CHECK3: .omp.final.then:483// CHECK3-NEXT: store i32 2, ptr [[I]], align 4484// CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]485// CHECK3: .omp.final.done:486// CHECK3-NEXT: ret void487//488//489// CHECK5-LABEL: define {{[^@]+}}@main490// CHECK5-SAME: () #[[ATTR0:[0-9]+]] {491// CHECK5-NEXT: entry:492// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4493// CHECK5-NEXT: [[G:%.*]] = alloca double, align 8494// CHECK5-NEXT: [[G1:%.*]] = alloca ptr, align 8495// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8496// CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 4497// CHECK5-NEXT: store ptr [[G]], ptr [[G1]], align 8498// CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0499// CHECK5-NEXT: store ptr [[G]], ptr [[TMP0]], align 8500// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1501// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 8, !nonnull [[META2:![0-9]+]], !align [[META3:![0-9]+]]502// CHECK5-NEXT: store ptr [[TMP2]], ptr [[TMP1]], align 8503// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP]])504// CHECK5-NEXT: ret i32 0505//506//507// CHECK7-LABEL: define {{[^@]+}}@main508// CHECK7-SAME: () #[[ATTR0:[0-9]+]] {509// CHECK7-NEXT: entry:510// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4511// CHECK7-NEXT: [[G:%.*]] = alloca double, align 8512// CHECK7-NEXT: [[G1:%.*]] = alloca ptr, align 4513// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4514// CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 4515// CHECK7-NEXT: store ptr [[G]], ptr [[G1]], align 4516// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0517// CHECK7-NEXT: store ptr [[G]], ptr [[TMP0]], align 4518// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1519// CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 4, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]]520// CHECK7-NEXT: store ptr [[TMP2]], ptr [[TMP1]], align 4521// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 4 dereferenceable(8) [[REF_TMP]])522// CHECK7-NEXT: ret i32 0523//524//525// CHECK9-LABEL: define {{[^@]+}}@main526// CHECK9-SAME: () #[[ATTR0:[0-9]+]] {527// CHECK9-NEXT: entry:528// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4529// CHECK9-NEXT: [[G:%.*]] = alloca double, align 8530// CHECK9-NEXT: [[G1:%.*]] = alloca ptr, align 8531// CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4532// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4533// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4534// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4535// CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 8536// CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8537// CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8538// CHECK9-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8539// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8540// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8541// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8542// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4543// CHECK9-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8544// CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4545// CHECK9-NEXT: store ptr [[G]], ptr [[G1]], align 8546// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])547// CHECK9-NEXT: store i32 0, ptr [[T_VAR]], align 4548// CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i64 8, i1 false)549// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], float noundef 1.000000e+00)550// CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i64 1551// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00)552// CHECK9-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8553// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8, !nonnull [[META7:![0-9]+]], !align [[META8:![0-9]+]]554// CHECK9-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8555// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4556// CHECK9-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4557// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8558// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]559// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr @_ZZ4mainE4svar, align 4560// CHECK9-NEXT: store i32 [[TMP4]], ptr [[SVAR_CASTED]], align 4561// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[SVAR_CASTED]], align 8562// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]563// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]564// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0565// CHECK9-NEXT: store i64 [[TMP2]], ptr [[TMP8]], align 8566// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0567// CHECK9-NEXT: store i64 [[TMP2]], ptr [[TMP9]], align 8568// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0569// CHECK9-NEXT: store ptr null, ptr [[TMP10]], align 8570// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1571// CHECK9-NEXT: store ptr [[VEC]], ptr [[TMP11]], align 8572// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1573// CHECK9-NEXT: store ptr [[VEC]], ptr [[TMP12]], align 8574// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1575// CHECK9-NEXT: store ptr null, ptr [[TMP13]], align 8576// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2577// CHECK9-NEXT: store ptr [[S_ARR]], ptr [[TMP14]], align 8578// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2579// CHECK9-NEXT: store ptr [[S_ARR]], ptr [[TMP15]], align 8580// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2581// CHECK9-NEXT: store ptr null, ptr [[TMP16]], align 8582// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3583// CHECK9-NEXT: store ptr [[TMP6]], ptr [[TMP17]], align 8584// CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3585// CHECK9-NEXT: store ptr [[TMP7]], ptr [[TMP18]], align 8586// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3587// CHECK9-NEXT: store ptr null, ptr [[TMP19]], align 8588// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4589// CHECK9-NEXT: store i64 [[TMP5]], ptr [[TMP20]], align 8590// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4591// CHECK9-NEXT: store i64 [[TMP5]], ptr [[TMP21]], align 8592// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4593// CHECK9-NEXT: store ptr null, ptr [[TMP22]], align 8594// CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0595// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0596// CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0597// CHECK9-NEXT: store i32 3, ptr [[TMP25]], align 4598// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1599// CHECK9-NEXT: store i32 5, ptr [[TMP26]], align 4600// CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2601// CHECK9-NEXT: store ptr [[TMP23]], ptr [[TMP27]], align 8602// CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3603// CHECK9-NEXT: store ptr [[TMP24]], ptr [[TMP28]], align 8604// CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4605// CHECK9-NEXT: store ptr @.offload_sizes, ptr [[TMP29]], align 8606// CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5607// CHECK9-NEXT: store ptr @.offload_maptypes, ptr [[TMP30]], align 8608// CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6609// CHECK9-NEXT: store ptr null, ptr [[TMP31]], align 8610// CHECK9-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7611// CHECK9-NEXT: store ptr null, ptr [[TMP32]], align 8612// CHECK9-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8613// CHECK9-NEXT: store i64 2, ptr [[TMP33]], align 8614// CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9615// CHECK9-NEXT: store i64 0, ptr [[TMP34]], align 8616// CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10617// CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP35]], align 4618// CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11619// CHECK9-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP36]], align 4620// CHECK9-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12621// CHECK9-NEXT: store i32 0, ptr [[TMP37]], align 4622// CHECK9-NEXT: [[TMP38:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105.region_id, ptr [[KERNEL_ARGS]])623// CHECK9-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0624// CHECK9-NEXT: br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]625// CHECK9: omp_offload.failed:626// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105(i64 [[TMP2]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP3]], i64 [[TMP5]]) #[[ATTR4:[0-9]+]]627// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]]628// CHECK9: omp_offload.cont:629// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()630// CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4631// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0632// CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2633// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]634// CHECK9: arraydestroy.body:635// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP40]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]636// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1637// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]638// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]639// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]640// CHECK9: arraydestroy.done2:641// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]642// CHECK9-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4643// CHECK9-NEXT: ret i32 [[TMP41]]644//645//646// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev647// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {648// CHECK9-NEXT: entry:649// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8650// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8651// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8652// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])653// CHECK9-NEXT: ret void654//655//656// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef657// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {658// CHECK9-NEXT: entry:659// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8660// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4661// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8662// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4663// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8664// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4665// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])666// CHECK9-NEXT: ret void667//668//669// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105670// CHECK9-SAME: (i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] {671// CHECK9-NEXT: entry:672// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8673// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8674// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8675// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8676// CHECK9-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8677// CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8678// CHECK9-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8679// CHECK9-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8680// CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8681// CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8682// CHECK9-NEXT: store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8683// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]684// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]685// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]686// CHECK9-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8687// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]688// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP3]], ptr [[SVAR_ADDR]])689// CHECK9-NEXT: ret void690//691//692// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105.omp_outlined693// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] {694// CHECK9-NEXT: entry:695// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8696// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8697// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 8698// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8699// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8700// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8701// CHECK9-NEXT: [[SVAR_ADDR:%.*]] = alloca ptr, align 8702// CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8703// CHECK9-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8704// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4705// CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32, align 4706// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4707// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4708// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4709// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4710// CHECK9-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4711// CHECK9-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4712// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4713// CHECK9-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4714// CHECK9-NEXT: [[_TMP8:%.*]] = alloca ptr, align 8715// CHECK9-NEXT: [[SVAR9:%.*]] = alloca i32, align 4716// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4717// CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8718// CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8719// CHECK9-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8720// CHECK9-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8721// CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8722// CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8723// CHECK9-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 8724// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]725// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]726// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]727// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]728// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]729// CHECK9-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 8730// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]731// CHECK9-NEXT: store ptr [[TMP5]], ptr [[_TMP1]], align 8732// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4733// CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4734// CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4735// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4736// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP0]], align 4737// CHECK9-NEXT: store i32 [[TMP6]], ptr [[T_VAR3]], align 4738// CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC4]], ptr align 4 [[TMP1]], i64 8, i1 false)739// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0740// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2741// CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP7]]742// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]743// CHECK9: omp.arraycpy.body:744// CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]745// CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]746// CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i64 4, i1 false)747// CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1748// CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1749// CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP7]]750// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]]751// CHECK9: omp.arraycpy.done6:752// CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META7]], !align [[META8]]753// CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VAR7]], ptr align 4 [[TMP8]], i64 4, i1 false)754// CHECK9-NEXT: store ptr [[VAR7]], ptr [[_TMP8]], align 8755// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP4]], align 4756// CHECK9-NEXT: store i32 [[TMP9]], ptr [[SVAR9]], align 4757// CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8758// CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4759// CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)760// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4761// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1762// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]763// CHECK9: cond.true:764// CHECK9-NEXT: br label [[COND_END:%.*]]765// CHECK9: cond.false:766// CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4767// CHECK9-NEXT: br label [[COND_END]]768// CHECK9: cond.end:769// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]770// CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4771// CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4772// CHECK9-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV]], align 4773// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]774// CHECK9: omp.inner.for.cond:775// CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]]776// CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP9]]777// CHECK9-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]778// CHECK9-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]779// CHECK9: omp.inner.for.cond.cleanup:780// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]781// CHECK9: omp.inner.for.body:782// CHECK9-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]783// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1784// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]785// CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]786// CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[T_VAR3]], align 4, !llvm.access.group [[ACC_GRP9]]787// CHECK9-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]788// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64789// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]]790// CHECK9-NEXT: store i32 [[TMP18]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]]791// CHECK9-NEXT: [[TMP20:%.*]] = load ptr, ptr [[_TMP8]], align 8, !nonnull [[META7]], !align [[META8]], !llvm.access.group [[ACC_GRP9]]792// CHECK9-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]793// CHECK9-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64794// CHECK9-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM11]]795// CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX12]], ptr align 4 [[TMP20]], i64 4, i1 false), !llvm.access.group [[ACC_GRP9]]796// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]797// CHECK9: omp.body.continue:798// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]799// CHECK9: omp.inner.for.inc:800// CHECK9-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]801// CHECK9-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP22]], 1802// CHECK9-NEXT: store i32 [[ADD13]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]803// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]804// CHECK9: omp.inner.for.end:805// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]806// CHECK9: omp.loop.exit:807// CHECK9-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8808// CHECK9-NEXT: [[TMP24:%.*]] = load i32, ptr [[TMP23]], align 4809// CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP24]])810// CHECK9-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4811// CHECK9-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0812// CHECK9-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]813// CHECK9: .omp.final.then:814// CHECK9-NEXT: store i32 2, ptr [[I]], align 4815// CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]816// CHECK9: .omp.final.done:817// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]]818// CHECK9-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0819// CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN14]], i64 2820// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]821// CHECK9: arraydestroy.body:822// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP27]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]823// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1824// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]825// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]]826// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]]827// CHECK9: arraydestroy.done15:828// CHECK9-NEXT: ret void829//830//831// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev832// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {833// CHECK9-NEXT: entry:834// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8835// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8836// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8837// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]838// CHECK9-NEXT: ret void839//840//841// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v842// CHECK9-SAME: () #[[ATTR1]] comdat {843// CHECK9-NEXT: entry:844// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4845// CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4846// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4847// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4848// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4849// CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 8850// CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8851// CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8852// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8853// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8854// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8855// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4856// CHECK9-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8857// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])858// CHECK9-NEXT: store i32 0, ptr [[T_VAR]], align 4859// CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)860// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef signext 1)861// CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1862// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2)863// CHECK9-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8864// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8, !nonnull [[META7]], !align [[META8]]865// CHECK9-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8866// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4867// CHECK9-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4868// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8869// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]870// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]871// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]872// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0873// CHECK9-NEXT: store i64 [[TMP2]], ptr [[TMP6]], align 8874// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0875// CHECK9-NEXT: store i64 [[TMP2]], ptr [[TMP7]], align 8876// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0877// CHECK9-NEXT: store ptr null, ptr [[TMP8]], align 8878// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1879// CHECK9-NEXT: store ptr [[VEC]], ptr [[TMP9]], align 8880// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1881// CHECK9-NEXT: store ptr [[VEC]], ptr [[TMP10]], align 8882// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1883// CHECK9-NEXT: store ptr null, ptr [[TMP11]], align 8884// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2885// CHECK9-NEXT: store ptr [[S_ARR]], ptr [[TMP12]], align 8886// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2887// CHECK9-NEXT: store ptr [[S_ARR]], ptr [[TMP13]], align 8888// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2889// CHECK9-NEXT: store ptr null, ptr [[TMP14]], align 8890// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3891// CHECK9-NEXT: store ptr [[TMP4]], ptr [[TMP15]], align 8892// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3893// CHECK9-NEXT: store ptr [[TMP5]], ptr [[TMP16]], align 8894// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3895// CHECK9-NEXT: store ptr null, ptr [[TMP17]], align 8896// CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0897// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0898// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0899// CHECK9-NEXT: store i32 3, ptr [[TMP20]], align 4900// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1901// CHECK9-NEXT: store i32 4, ptr [[TMP21]], align 4902// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2903// CHECK9-NEXT: store ptr [[TMP18]], ptr [[TMP22]], align 8904// CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3905// CHECK9-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 8906// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4907// CHECK9-NEXT: store ptr @.offload_sizes.1, ptr [[TMP24]], align 8908// CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5909// CHECK9-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP25]], align 8910// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6911// CHECK9-NEXT: store ptr null, ptr [[TMP26]], align 8912// CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7913// CHECK9-NEXT: store ptr null, ptr [[TMP27]], align 8914// CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8915// CHECK9-NEXT: store i64 2, ptr [[TMP28]], align 8916// CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9917// CHECK9-NEXT: store i64 0, ptr [[TMP29]], align 8918// CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10919// CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP30]], align 4920// CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11921// CHECK9-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP31]], align 4922// CHECK9-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12923// CHECK9-NEXT: store i32 0, ptr [[TMP32]], align 4924// CHECK9-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, ptr [[KERNEL_ARGS]])925// CHECK9-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0926// CHECK9-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]927// CHECK9: omp_offload.failed:928// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i64 [[TMP2]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP3]]) #[[ATTR4]]929// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]]930// CHECK9: omp_offload.cont:931// CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4932// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0933// CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2934// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]935// CHECK9: arraydestroy.body:936// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]937// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1938// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]939// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]940// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]941// CHECK9: arraydestroy.done2:942// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]943// CHECK9-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4944// CHECK9-NEXT: ret i32 [[TMP36]]945//946//947// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev948// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {949// CHECK9-NEXT: entry:950// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8951// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8952// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8953// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0954// CHECK9-NEXT: store float 0.000000e+00, ptr [[F]], align 4955// CHECK9-NEXT: ret void956//957//958// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef959// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {960// CHECK9-NEXT: entry:961// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8962// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4963// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8964// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4965// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8966// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0967// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4968// CHECK9-NEXT: store float [[TMP0]], ptr [[F]], align 4969// CHECK9-NEXT: ret void970//971//972// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev973// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {974// CHECK9-NEXT: entry:975// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8976// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8977// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8978// CHECK9-NEXT: ret void979//980//981// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev982// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {983// CHECK9-NEXT: entry:984// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8985// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8986// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8987// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])988// CHECK9-NEXT: ret void989//990//991// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei992// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {993// CHECK9-NEXT: entry:994// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8995// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4996// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8997// CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4998// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8999// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41000// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])1001// CHECK9-NEXT: ret void1002//1003//1004// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l491005// CHECK9-SAME: (i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {1006// CHECK9-NEXT: entry:1007// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 81008// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 81009// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 81010// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 81011// CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 81012// CHECK9-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 81013// CHECK9-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 81014// CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 81015// CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 81016// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]1017// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]1018// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]1019// CHECK9-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 81020// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]1021// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP3]])1022// CHECK9-NEXT: ret void1023//1024//1025// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.omp_outlined1026// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {1027// CHECK9-NEXT: entry:1028// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81029// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81030// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 81031// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 81032// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 81033// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 81034// CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 81035// CHECK9-NEXT: [[_TMP1:%.*]] = alloca ptr, align 81036// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41037// CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32, align 41038// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 41039// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 41040// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41041// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41042// CHECK9-NEXT: [[T_VAR3:%.*]] = alloca i32, align 41043// CHECK9-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 41044// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 41045// CHECK9-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 41046// CHECK9-NEXT: [[_TMP8:%.*]] = alloca ptr, align 81047// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 41048// CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81049// CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81050// CHECK9-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 81051// CHECK9-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 81052// CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 81053// CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 81054// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]1055// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]1056// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]1057// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]1058// CHECK9-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 81059// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]1060// CHECK9-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 81061// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 41062// CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 41063// CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 41064// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41065// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 41066// CHECK9-NEXT: store i32 [[TMP5]], ptr [[T_VAR3]], align 41067// CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC4]], ptr align 4 [[TMP1]], i64 8, i1 false)1068// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 01069// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 21070// CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP6]]1071// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]1072// CHECK9: omp.arraycpy.body:1073// CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1074// CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1075// CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i64 4, i1 false)1076// CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 11077// CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 11078// CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]1079// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]]1080// CHECK9: omp.arraycpy.done6:1081// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META7]], !align [[META8]]1082// CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VAR7]], ptr align 4 [[TMP7]], i64 4, i1 false)1083// CHECK9-NEXT: store ptr [[VAR7]], ptr [[_TMP8]], align 81084// CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81085// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 41086// CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP9]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1087// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41088// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 11089// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1090// CHECK9: cond.true:1091// CHECK9-NEXT: br label [[COND_END:%.*]]1092// CHECK9: cond.false:1093// CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41094// CHECK9-NEXT: br label [[COND_END]]1095// CHECK9: cond.end:1096// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]1097// CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 41098// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41099// CHECK9-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 41100// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1101// CHECK9: omp.inner.for.cond:1102// CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15:![0-9]+]]1103// CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP15]]1104// CHECK9-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]1105// CHECK9-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]1106// CHECK9: omp.inner.for.cond.cleanup:1107// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]1108// CHECK9: omp.inner.for.body:1109// CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]]1110// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 11111// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]1112// CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP15]]1113// CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[T_VAR3]], align 4, !llvm.access.group [[ACC_GRP15]]1114// CHECK9-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP15]]1115// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i641116// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]]1117// CHECK9-NEXT: store i32 [[TMP16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP15]]1118// CHECK9-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP8]], align 8, !nonnull [[META7]], !align [[META8]], !llvm.access.group [[ACC_GRP15]]1119// CHECK9-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP15]]1120// CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i641121// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM10]]1122// CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP18]], i64 4, i1 false), !llvm.access.group [[ACC_GRP15]]1123// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1124// CHECK9: omp.body.continue:1125// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1126// CHECK9: omp.inner.for.inc:1127// CHECK9-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]]1128// CHECK9-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP20]], 11129// CHECK9-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]]1130// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]1131// CHECK9: omp.inner.for.end:1132// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]1133// CHECK9: omp.loop.exit:1134// CHECK9-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81135// CHECK9-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 41136// CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP22]])1137// CHECK9-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 41138// CHECK9-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 01139// CHECK9-NEXT: br i1 [[TMP24]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]1140// CHECK9: .omp.final.then:1141// CHECK9-NEXT: store i32 2, ptr [[I]], align 41142// CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]1143// CHECK9: .omp.final.done:1144// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]]1145// CHECK9-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 01146// CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN13]], i64 21147// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]1148// CHECK9: arraydestroy.body:1149// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP25]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1150// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -11151// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]1152// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]]1153// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]]1154// CHECK9: arraydestroy.done14:1155// CHECK9-NEXT: ret void1156//1157//1158// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev1159// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1160// CHECK9-NEXT: entry:1161// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81162// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81163// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81164// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]1165// CHECK9-NEXT: ret void1166//1167//1168// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev1169// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1170// CHECK9-NEXT: entry:1171// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81172// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81173// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81174// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 01175// CHECK9-NEXT: store i32 0, ptr [[F]], align 41176// CHECK9-NEXT: ret void1177//1178//1179// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei1180// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {1181// CHECK9-NEXT: entry:1182// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81183// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 41184// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81185// CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 41186// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81187// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 01188// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41189// CHECK9-NEXT: store i32 [[TMP0]], ptr [[F]], align 41190// CHECK9-NEXT: ret void1191//1192//1193// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev1194// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1195// CHECK9-NEXT: entry:1196// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81197// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81198// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81199// CHECK9-NEXT: ret void1200//1201//1202// CHECK11-LABEL: define {{[^@]+}}@main1203// CHECK11-SAME: () #[[ATTR0:[0-9]+]] {1204// CHECK11-NEXT: entry:1205// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 41206// CHECK11-NEXT: [[G:%.*]] = alloca double, align 81207// CHECK11-NEXT: [[G1:%.*]] = alloca ptr, align 41208// CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 41209// CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 41210// CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 41211// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 41212// CHECK11-NEXT: [[VAR:%.*]] = alloca ptr, align 41213// CHECK11-NEXT: [[TMP:%.*]] = alloca ptr, align 41214// CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 41215// CHECK11-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 41216// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 41217// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 41218// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 41219// CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 41220// CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81221// CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 41222// CHECK11-NEXT: store ptr [[G]], ptr [[G1]], align 41223// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])1224// CHECK11-NEXT: store i32 0, ptr [[T_VAR]], align 41225// CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i32 8, i1 false)1226// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], float noundef 1.000000e+00)1227// CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i32 11228// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00)1229// CHECK11-NEXT: store ptr [[TEST]], ptr [[VAR]], align 41230// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4, !nonnull [[META8:![0-9]+]], !align [[META9:![0-9]+]]1231// CHECK11-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 41232// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 41233// CHECK11-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 41234// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 41235// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]1236// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr @_ZZ4mainE4svar, align 41237// CHECK11-NEXT: store i32 [[TMP4]], ptr [[SVAR_CASTED]], align 41238// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[SVAR_CASTED]], align 41239// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]1240// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]1241// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01242// CHECK11-NEXT: store i32 [[TMP2]], ptr [[TMP8]], align 41243// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01244// CHECK11-NEXT: store i32 [[TMP2]], ptr [[TMP9]], align 41245// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 01246// CHECK11-NEXT: store ptr null, ptr [[TMP10]], align 41247// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 11248// CHECK11-NEXT: store ptr [[VEC]], ptr [[TMP11]], align 41249// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 11250// CHECK11-NEXT: store ptr [[VEC]], ptr [[TMP12]], align 41251// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 11252// CHECK11-NEXT: store ptr null, ptr [[TMP13]], align 41253// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 21254// CHECK11-NEXT: store ptr [[S_ARR]], ptr [[TMP14]], align 41255// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 21256// CHECK11-NEXT: store ptr [[S_ARR]], ptr [[TMP15]], align 41257// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 21258// CHECK11-NEXT: store ptr null, ptr [[TMP16]], align 41259// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 31260// CHECK11-NEXT: store ptr [[TMP6]], ptr [[TMP17]], align 41261// CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 31262// CHECK11-NEXT: store ptr [[TMP7]], ptr [[TMP18]], align 41263// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 31264// CHECK11-NEXT: store ptr null, ptr [[TMP19]], align 41265// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 41266// CHECK11-NEXT: store i32 [[TMP5]], ptr [[TMP20]], align 41267// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 41268// CHECK11-NEXT: store i32 [[TMP5]], ptr [[TMP21]], align 41269// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 41270// CHECK11-NEXT: store ptr null, ptr [[TMP22]], align 41271// CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01272// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01273// CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 01274// CHECK11-NEXT: store i32 3, ptr [[TMP25]], align 41275// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11276// CHECK11-NEXT: store i32 5, ptr [[TMP26]], align 41277// CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 21278// CHECK11-NEXT: store ptr [[TMP23]], ptr [[TMP27]], align 41279// CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 31280// CHECK11-NEXT: store ptr [[TMP24]], ptr [[TMP28]], align 41281// CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 41282// CHECK11-NEXT: store ptr @.offload_sizes, ptr [[TMP29]], align 41283// CHECK11-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 51284// CHECK11-NEXT: store ptr @.offload_maptypes, ptr [[TMP30]], align 41285// CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 61286// CHECK11-NEXT: store ptr null, ptr [[TMP31]], align 41287// CHECK11-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 71288// CHECK11-NEXT: store ptr null, ptr [[TMP32]], align 41289// CHECK11-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 81290// CHECK11-NEXT: store i64 2, ptr [[TMP33]], align 81291// CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 91292// CHECK11-NEXT: store i64 0, ptr [[TMP34]], align 81293// CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 101294// CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP35]], align 41295// CHECK11-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 111296// CHECK11-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP36]], align 41297// CHECK11-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 121298// CHECK11-NEXT: store i32 0, ptr [[TMP37]], align 41299// CHECK11-NEXT: [[TMP38:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105.region_id, ptr [[KERNEL_ARGS]])1300// CHECK11-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 01301// CHECK11-NEXT: br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]1302// CHECK11: omp_offload.failed:1303// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105(i32 [[TMP2]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP3]], i32 [[TMP5]]) #[[ATTR4:[0-9]+]]1304// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]]1305// CHECK11: omp_offload.cont:1306// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()1307// CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 41308// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 01309// CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 21310// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]1311// CHECK11: arraydestroy.body:1312// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP40]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1313// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -11314// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]1315// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]1316// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]1317// CHECK11: arraydestroy.done2:1318// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]1319// CHECK11-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 41320// CHECK11-NEXT: ret i32 [[TMP41]]1321//1322//1323// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev1324// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {1325// CHECK11-NEXT: entry:1326// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41327// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41328// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41329// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])1330// CHECK11-NEXT: ret void1331//1332//1333// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef1334// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1335// CHECK11-NEXT: entry:1336// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41337// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 41338// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41339// CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 41340// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41341// CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 41342// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])1343// CHECK11-NEXT: ret void1344//1345//1346// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l1051347// CHECK11-SAME: (i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] {1348// CHECK11-NEXT: entry:1349// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 41350// CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 41351// CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 41352// CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 41353// CHECK11-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 41354// CHECK11-NEXT: [[TMP:%.*]] = alloca ptr, align 41355// CHECK11-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 41356// CHECK11-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 41357// CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 41358// CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 41359// CHECK11-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 41360// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1361// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1362// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1363// CHECK11-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 41364// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]1365// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP3]], ptr [[SVAR_ADDR]])1366// CHECK11-NEXT: ret void1367//1368//1369// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105.omp_outlined1370// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] {1371// CHECK11-NEXT: entry:1372// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 41373// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 41374// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 41375// CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 41376// CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 41377// CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 41378// CHECK11-NEXT: [[SVAR_ADDR:%.*]] = alloca ptr, align 41379// CHECK11-NEXT: [[TMP:%.*]] = alloca ptr, align 41380// CHECK11-NEXT: [[_TMP1:%.*]] = alloca ptr, align 41381// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41382// CHECK11-NEXT: [[_TMP2:%.*]] = alloca i32, align 41383// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 41384// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 41385// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41386// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41387// CHECK11-NEXT: [[T_VAR3:%.*]] = alloca i32, align 41388// CHECK11-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 41389// CHECK11-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 41390// CHECK11-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 41391// CHECK11-NEXT: [[_TMP8:%.*]] = alloca ptr, align 41392// CHECK11-NEXT: [[SVAR9:%.*]] = alloca i32, align 41393// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 41394// CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 41395// CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 41396// CHECK11-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 41397// CHECK11-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 41398// CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 41399// CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 41400// CHECK11-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 41401// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1402// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1403// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1404// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1405// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1406// CHECK11-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 41407// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]1408// CHECK11-NEXT: store ptr [[TMP5]], ptr [[_TMP1]], align 41409// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 41410// CHECK11-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 41411// CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 41412// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41413// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP0]], align 41414// CHECK11-NEXT: store i32 [[TMP6]], ptr [[T_VAR3]], align 41415// CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC4]], ptr align 4 [[TMP1]], i32 8, i1 false)1416// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 01417// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 21418// CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP7]]1419// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]1420// CHECK11: omp.arraycpy.body:1421// CHECK11-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1422// CHECK11-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1423// CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 4, i1 false)1424// CHECK11-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 11425// CHECK11-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 11426// CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP7]]1427// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]]1428// CHECK11: omp.arraycpy.done6:1429// CHECK11-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 4, !nonnull [[META8]], !align [[META9]]1430// CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VAR7]], ptr align 4 [[TMP8]], i32 4, i1 false)1431// CHECK11-NEXT: store ptr [[VAR7]], ptr [[_TMP8]], align 41432// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP4]], align 41433// CHECK11-NEXT: store i32 [[TMP9]], ptr [[SVAR9]], align 41434// CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41435// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 41436// CHECK11-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1437// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41438// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 11439// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1440// CHECK11: cond.true:1441// CHECK11-NEXT: br label [[COND_END:%.*]]1442// CHECK11: cond.false:1443// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41444// CHECK11-NEXT: br label [[COND_END]]1445// CHECK11: cond.end:1446// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]1447// CHECK11-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 41448// CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41449// CHECK11-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV]], align 41450// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1451// CHECK11: omp.inner.for.cond:1452// CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]]1453// CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP10]]1454// CHECK11-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]1455// CHECK11-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]1456// CHECK11: omp.inner.for.cond.cleanup:1457// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]]1458// CHECK11: omp.inner.for.body:1459// CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]1460// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 11461// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]1462// CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]1463// CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[T_VAR3]], align 4, !llvm.access.group [[ACC_GRP10]]1464// CHECK11-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]1465// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i32 0, i32 [[TMP19]]1466// CHECK11-NEXT: store i32 [[TMP18]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]]1467// CHECK11-NEXT: [[TMP20:%.*]] = load ptr, ptr [[_TMP8]], align 4, !nonnull [[META8]], !align [[META9]], !llvm.access.group [[ACC_GRP10]]1468// CHECK11-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]1469// CHECK11-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 [[TMP21]]1470// CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP20]], i32 4, i1 false), !llvm.access.group [[ACC_GRP10]]1471// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1472// CHECK11: omp.body.continue:1473// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1474// CHECK11: omp.inner.for.inc:1475// CHECK11-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]1476// CHECK11-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP22]], 11477// CHECK11-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]1478// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]1479// CHECK11: omp.inner.for.end:1480// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]1481// CHECK11: omp.loop.exit:1482// CHECK11-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41483// CHECK11-NEXT: [[TMP24:%.*]] = load i32, ptr [[TMP23]], align 41484// CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP24]])1485// CHECK11-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 41486// CHECK11-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 01487// CHECK11-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]1488// CHECK11: .omp.final.then:1489// CHECK11-NEXT: store i32 2, ptr [[I]], align 41490// CHECK11-NEXT: br label [[DOTOMP_FINAL_DONE]]1491// CHECK11: .omp.final.done:1492// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]]1493// CHECK11-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 01494// CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN13]], i32 21495// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]1496// CHECK11: arraydestroy.body:1497// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP27]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1498// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -11499// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]1500// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]]1501// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]]1502// CHECK11: arraydestroy.done14:1503// CHECK11-NEXT: ret void1504//1505//1506// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev1507// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1508// CHECK11-NEXT: entry:1509// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41510// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41511// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41512// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]1513// CHECK11-NEXT: ret void1514//1515//1516// CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiET_v1517// CHECK11-SAME: () #[[ATTR1]] comdat {1518// CHECK11-NEXT: entry:1519// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 41520// CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 41521// CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 41522// CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 41523// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 41524// CHECK11-NEXT: [[VAR:%.*]] = alloca ptr, align 41525// CHECK11-NEXT: [[TMP:%.*]] = alloca ptr, align 41526// CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 41527// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 41528// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 41529// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 41530// CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 41531// CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81532// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])1533// CHECK11-NEXT: store i32 0, ptr [[T_VAR]], align 41534// CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false)1535// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1)1536// CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 11537// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)1538// CHECK11-NEXT: store ptr [[TEST]], ptr [[VAR]], align 41539// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4, !nonnull [[META8]], !align [[META9]]1540// CHECK11-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 41541// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 41542// CHECK11-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 41543// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 41544// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]1545// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]1546// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]1547// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01548// CHECK11-NEXT: store i32 [[TMP2]], ptr [[TMP6]], align 41549// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01550// CHECK11-NEXT: store i32 [[TMP2]], ptr [[TMP7]], align 41551// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 01552// CHECK11-NEXT: store ptr null, ptr [[TMP8]], align 41553// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 11554// CHECK11-NEXT: store ptr [[VEC]], ptr [[TMP9]], align 41555// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 11556// CHECK11-NEXT: store ptr [[VEC]], ptr [[TMP10]], align 41557// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 11558// CHECK11-NEXT: store ptr null, ptr [[TMP11]], align 41559// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 21560// CHECK11-NEXT: store ptr [[S_ARR]], ptr [[TMP12]], align 41561// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 21562// CHECK11-NEXT: store ptr [[S_ARR]], ptr [[TMP13]], align 41563// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 21564// CHECK11-NEXT: store ptr null, ptr [[TMP14]], align 41565// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 31566// CHECK11-NEXT: store ptr [[TMP4]], ptr [[TMP15]], align 41567// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 31568// CHECK11-NEXT: store ptr [[TMP5]], ptr [[TMP16]], align 41569// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 31570// CHECK11-NEXT: store ptr null, ptr [[TMP17]], align 41571// CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01572// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01573// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 01574// CHECK11-NEXT: store i32 3, ptr [[TMP20]], align 41575// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11576// CHECK11-NEXT: store i32 4, ptr [[TMP21]], align 41577// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 21578// CHECK11-NEXT: store ptr [[TMP18]], ptr [[TMP22]], align 41579// CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 31580// CHECK11-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 41581// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 41582// CHECK11-NEXT: store ptr @.offload_sizes.1, ptr [[TMP24]], align 41583// CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 51584// CHECK11-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP25]], align 41585// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 61586// CHECK11-NEXT: store ptr null, ptr [[TMP26]], align 41587// CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 71588// CHECK11-NEXT: store ptr null, ptr [[TMP27]], align 41589// CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 81590// CHECK11-NEXT: store i64 2, ptr [[TMP28]], align 81591// CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 91592// CHECK11-NEXT: store i64 0, ptr [[TMP29]], align 81593// CHECK11-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 101594// CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP30]], align 41595// CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 111596// CHECK11-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP31]], align 41597// CHECK11-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 121598// CHECK11-NEXT: store i32 0, ptr [[TMP32]], align 41599// CHECK11-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, ptr [[KERNEL_ARGS]])1600// CHECK11-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 01601// CHECK11-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]1602// CHECK11: omp_offload.failed:1603// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i32 [[TMP2]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP3]]) #[[ATTR4]]1604// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]]1605// CHECK11: omp_offload.cont:1606// CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 41607// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 01608// CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 21609// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]1610// CHECK11: arraydestroy.body:1611// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1612// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -11613// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]1614// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]1615// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]1616// CHECK11: arraydestroy.done2:1617// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]1618// CHECK11-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 41619// CHECK11-NEXT: ret i32 [[TMP36]]1620//1621//1622// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev1623// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1624// CHECK11-NEXT: entry:1625// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41626// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41627// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41628// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 01629// CHECK11-NEXT: store float 0.000000e+00, ptr [[F]], align 41630// CHECK11-NEXT: ret void1631//1632//1633// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef1634// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1635// CHECK11-NEXT: entry:1636// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41637// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 41638// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41639// CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 41640// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41641// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 01642// CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 41643// CHECK11-NEXT: store float [[TMP0]], ptr [[F]], align 41644// CHECK11-NEXT: ret void1645//1646//1647// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev1648// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1649// CHECK11-NEXT: entry:1650// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41651// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41652// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41653// CHECK11-NEXT: ret void1654//1655//1656// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev1657// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1658// CHECK11-NEXT: entry:1659// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41660// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41661// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41662// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])1663// CHECK11-NEXT: ret void1664//1665//1666// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei1667// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1668// CHECK11-NEXT: entry:1669// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41670// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 41671// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41672// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 41673// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41674// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41675// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])1676// CHECK11-NEXT: ret void1677//1678//1679// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l491680// CHECK11-SAME: (i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {1681// CHECK11-NEXT: entry:1682// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 41683// CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 41684// CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 41685// CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 41686// CHECK11-NEXT: [[TMP:%.*]] = alloca ptr, align 41687// CHECK11-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 41688// CHECK11-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 41689// CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 41690// CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 41691// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1692// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1693// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1694// CHECK11-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 41695// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]1696// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP3]])1697// CHECK11-NEXT: ret void1698//1699//1700// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.omp_outlined1701// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {1702// CHECK11-NEXT: entry:1703// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 41704// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 41705// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 41706// CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 41707// CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 41708// CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 41709// CHECK11-NEXT: [[TMP:%.*]] = alloca ptr, align 41710// CHECK11-NEXT: [[_TMP1:%.*]] = alloca ptr, align 41711// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41712// CHECK11-NEXT: [[_TMP2:%.*]] = alloca i32, align 41713// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 41714// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 41715// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41716// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41717// CHECK11-NEXT: [[T_VAR3:%.*]] = alloca i32, align 41718// CHECK11-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 41719// CHECK11-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 41720// CHECK11-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 41721// CHECK11-NEXT: [[_TMP8:%.*]] = alloca ptr, align 41722// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 41723// CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 41724// CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 41725// CHECK11-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 41726// CHECK11-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 41727// CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 41728// CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 41729// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1730// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1731// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1732// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1733// CHECK11-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 41734// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]1735// CHECK11-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 41736// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 41737// CHECK11-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 41738// CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 41739// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41740// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 41741// CHECK11-NEXT: store i32 [[TMP5]], ptr [[T_VAR3]], align 41742// CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC4]], ptr align 4 [[TMP1]], i32 8, i1 false)1743// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 01744// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 21745// CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP6]]1746// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]1747// CHECK11: omp.arraycpy.body:1748// CHECK11-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1749// CHECK11-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1750// CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 4, i1 false)1751// CHECK11-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 11752// CHECK11-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 11753// CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]1754// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]]1755// CHECK11: omp.arraycpy.done6:1756// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP1]], align 4, !nonnull [[META8]], !align [[META9]]1757// CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VAR7]], ptr align 4 [[TMP7]], i32 4, i1 false)1758// CHECK11-NEXT: store ptr [[VAR7]], ptr [[_TMP8]], align 41759// CHECK11-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41760// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 41761// CHECK11-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP9]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1762// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41763// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 11764// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1765// CHECK11: cond.true:1766// CHECK11-NEXT: br label [[COND_END:%.*]]1767// CHECK11: cond.false:1768// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41769// CHECK11-NEXT: br label [[COND_END]]1770// CHECK11: cond.end:1771// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]1772// CHECK11-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 41773// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41774// CHECK11-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 41775// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1776// CHECK11: omp.inner.for.cond:1777// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16:![0-9]+]]1778// CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP16]]1779// CHECK11-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]1780// CHECK11-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]1781// CHECK11: omp.inner.for.cond.cleanup:1782// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]]1783// CHECK11: omp.inner.for.body:1784// CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]]1785// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 11786// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]1787// CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP16]]1788// CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[T_VAR3]], align 4, !llvm.access.group [[ACC_GRP16]]1789// CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP16]]1790// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i32 0, i32 [[TMP17]]1791// CHECK11-NEXT: store i32 [[TMP16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]]1792// CHECK11-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP8]], align 4, !nonnull [[META8]], !align [[META9]], !llvm.access.group [[ACC_GRP16]]1793// CHECK11-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP16]]1794// CHECK11-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 [[TMP19]]1795// CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP18]], i32 4, i1 false), !llvm.access.group [[ACC_GRP16]]1796// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1797// CHECK11: omp.body.continue:1798// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1799// CHECK11: omp.inner.for.inc:1800// CHECK11-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]]1801// CHECK11-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 11802// CHECK11-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]]1803// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]1804// CHECK11: omp.inner.for.end:1805// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]1806// CHECK11: omp.loop.exit:1807// CHECK11-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41808// CHECK11-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 41809// CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP22]])1810// CHECK11-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 41811// CHECK11-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 01812// CHECK11-NEXT: br i1 [[TMP24]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]1813// CHECK11: .omp.final.then:1814// CHECK11-NEXT: store i32 2, ptr [[I]], align 41815// CHECK11-NEXT: br label [[DOTOMP_FINAL_DONE]]1816// CHECK11: .omp.final.done:1817// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]]1818// CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 01819// CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i32 21820// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]1821// CHECK11: arraydestroy.body:1822// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP25]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1823// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -11824// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]1825// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]]1826// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]]1827// CHECK11: arraydestroy.done13:1828// CHECK11-NEXT: ret void1829//1830//1831// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev1832// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1833// CHECK11-NEXT: entry:1834// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41835// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41836// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41837// CHECK11-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]1838// CHECK11-NEXT: ret void1839//1840//1841// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev1842// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1843// CHECK11-NEXT: entry:1844// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41845// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41846// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41847// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 01848// CHECK11-NEXT: store i32 0, ptr [[F]], align 41849// CHECK11-NEXT: ret void1850//1851//1852// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei1853// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1854// CHECK11-NEXT: entry:1855// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41856// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 41857// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41858// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 41859// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41860// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 01861// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41862// CHECK11-NEXT: store i32 [[TMP0]], ptr [[F]], align 41863// CHECK11-NEXT: ret void1864//1865//1866// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev1867// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1868// CHECK11-NEXT: entry:1869// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41870// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41871// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41872// CHECK11-NEXT: ret void1873//1874//1875// CHECK13-LABEL: define {{[^@]+}}@main1876// CHECK13-SAME: () #[[ATTR0:[0-9]+]] {1877// CHECK13-NEXT: entry:1878// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 41879// CHECK13-NEXT: [[G:%.*]] = alloca double, align 81880// CHECK13-NEXT: [[G1:%.*]] = alloca ptr, align 81881// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 41882// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 41883// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 41884// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 41885// CHECK13-NEXT: [[VAR:%.*]] = alloca ptr, align 81886// CHECK13-NEXT: [[TMP:%.*]] = alloca ptr, align 81887// CHECK13-NEXT: [[_TMP1:%.*]] = alloca ptr, align 81888// CHECK13-NEXT: [[_TMP2:%.*]] = alloca ptr, align 81889// CHECK13-NEXT: [[_TMP3:%.*]] = alloca i32, align 41890// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 41891// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 41892// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41893// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 41894// CHECK13-NEXT: store i32 0, ptr [[RETVAL]], align 41895// CHECK13-NEXT: store ptr [[G]], ptr [[G1]], align 81896// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])1897// CHECK13-NEXT: store i32 0, ptr [[T_VAR]], align 41898// CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i64 8, i1 false)1899// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], float noundef 1.000000e+00)1900// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i64 11901// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00)1902// CHECK13-NEXT: store ptr [[TEST]], ptr [[VAR]], align 81903// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8, !nonnull [[META2:![0-9]+]], !align [[META3:![0-9]+]]1904// CHECK13-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 81905// CHECK13-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VAR]], align 8, !nonnull [[META2]], !align [[META3]]1906// CHECK13-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META2]], !align [[META3]]1907// CHECK13-NEXT: store ptr [[TMP2]], ptr [[_TMP1]], align 81908// CHECK13-NEXT: [[TMP3:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META2]], !align [[META3]]1909// CHECK13-NEXT: store ptr [[TMP3]], ptr [[_TMP2]], align 81910// CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 41911// CHECK13-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 41912// CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41913// CHECK13-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 41914// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1915// CHECK13: omp.inner.for.cond:1916// CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4:![0-9]+]]1917// CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP4]]1918// CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]1919// CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1920// CHECK13: omp.inner.for.body:1921// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]1922// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 11923// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]1924// CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]]1925// CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP4]]1926// CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]]1927// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i641928// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]]1929// CHECK13-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP4]]1930// CHECK13-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META2]], !align [[META3]], !llvm.access.group [[ACC_GRP4]]1931// CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]]1932// CHECK13-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i641933// CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]]1934// CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group [[ACC_GRP4]]1935// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1936// CHECK13: omp.body.continue:1937// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1938// CHECK13: omp.inner.for.inc:1939// CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]1940// CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 11941// CHECK13-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]1942// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]1943// CHECK13: omp.inner.for.end:1944// CHECK13-NEXT: store i32 2, ptr [[I]], align 41945// CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()1946// CHECK13-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 41947// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 01948// CHECK13-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 21949// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]1950// CHECK13: arraydestroy.body:1951// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1952// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -11953// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]]1954// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]1955// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]1956// CHECK13: arraydestroy.done7:1957// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]]1958// CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 41959// CHECK13-NEXT: ret i32 [[TMP14]]1960//1961//1962// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev1963// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {1964// CHECK13-NEXT: entry:1965// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81966// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81967// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81968// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])1969// CHECK13-NEXT: ret void1970//1971//1972// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef1973// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {1974// CHECK13-NEXT: entry:1975// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81976// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 41977// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81978// CHECK13-NEXT: store float [[A]], ptr [[A_ADDR]], align 41979// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81980// CHECK13-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 41981// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])1982// CHECK13-NEXT: ret void1983//1984//1985// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiET_v1986// CHECK13-SAME: () #[[ATTR1]] comdat {1987// CHECK13-NEXT: entry:1988// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 41989// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 41990// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 41991// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 41992// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 41993// CHECK13-NEXT: [[VAR:%.*]] = alloca ptr, align 81994// CHECK13-NEXT: [[TMP:%.*]] = alloca ptr, align 81995// CHECK13-NEXT: [[_TMP1:%.*]] = alloca ptr, align 81996// CHECK13-NEXT: [[_TMP2:%.*]] = alloca ptr, align 81997// CHECK13-NEXT: [[_TMP3:%.*]] = alloca i32, align 41998// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 41999// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 42000// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 42001// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 42002// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])2003// CHECK13-NEXT: store i32 0, ptr [[T_VAR]], align 42004// CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)2005// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef signext 1)2006// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 12007// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2)2008// CHECK13-NEXT: store ptr [[TEST]], ptr [[VAR]], align 82009// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8, !nonnull [[META2]], !align [[META3]]2010// CHECK13-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 82011// CHECK13-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VAR]], align 8, !nonnull [[META2]], !align [[META3]]2012// CHECK13-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META2]], !align [[META3]]2013// CHECK13-NEXT: store ptr [[TMP2]], ptr [[_TMP1]], align 82014// CHECK13-NEXT: [[TMP3:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META2]], !align [[META3]]2015// CHECK13-NEXT: store ptr [[TMP3]], ptr [[_TMP2]], align 82016// CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 42017// CHECK13-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 42018// CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42019// CHECK13-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 42020// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]2021// CHECK13: omp.inner.for.cond:2022// CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8:![0-9]+]]2023// CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP8]]2024// CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]2025// CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2026// CHECK13: omp.inner.for.body:2027// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]2028// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 12029// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]2030// CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]]2031// CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP8]]2032// CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]]2033// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i642034// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]]2035// CHECK13-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP8]]2036// CHECK13-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META2]], !align [[META3]], !llvm.access.group [[ACC_GRP8]]2037// CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]]2038// CHECK13-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i642039// CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]]2040// CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group [[ACC_GRP8]]2041// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]2042// CHECK13: omp.body.continue:2043// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]2044// CHECK13: omp.inner.for.inc:2045// CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]2046// CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 12047// CHECK13-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]2048// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]2049// CHECK13: omp.inner.for.end:2050// CHECK13-NEXT: store i32 2, ptr [[I]], align 42051// CHECK13-NEXT: store i32 0, ptr [[RETVAL]], align 42052// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 02053// CHECK13-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 22054// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]2055// CHECK13: arraydestroy.body:2056// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]2057// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -12058// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]2059// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]2060// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]2061// CHECK13: arraydestroy.done7:2062// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]]2063// CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 42064// CHECK13-NEXT: ret i32 [[TMP14]]2065//2066//2067// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev2068// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {2069// CHECK13-NEXT: entry:2070// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82071// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82072// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82073// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]]2074// CHECK13-NEXT: ret void2075//2076//2077// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev2078// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {2079// CHECK13-NEXT: entry:2080// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82081// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82082// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82083// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 02084// CHECK13-NEXT: store float 0.000000e+00, ptr [[F]], align 42085// CHECK13-NEXT: ret void2086//2087//2088// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev2089// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {2090// CHECK13-NEXT: entry:2091// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82092// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82093// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82094// CHECK13-NEXT: ret void2095//2096//2097// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef2098// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {2099// CHECK13-NEXT: entry:2100// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82101// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 42102// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82103// CHECK13-NEXT: store float [[A]], ptr [[A_ADDR]], align 42104// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82105// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 02106// CHECK13-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 42107// CHECK13-NEXT: store float [[TMP0]], ptr [[F]], align 42108// CHECK13-NEXT: ret void2109//2110//2111// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev2112// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {2113// CHECK13-NEXT: entry:2114// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82115// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82116// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82117// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])2118// CHECK13-NEXT: ret void2119//2120//2121// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei2122// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {2123// CHECK13-NEXT: entry:2124// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82125// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 42126// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82127// CHECK13-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 42128// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82129// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 42130// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])2131// CHECK13-NEXT: ret void2132//2133//2134// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev2135// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {2136// CHECK13-NEXT: entry:2137// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82138// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82139// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82140// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]]2141// CHECK13-NEXT: ret void2142//2143//2144// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev2145// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {2146// CHECK13-NEXT: entry:2147// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82148// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82149// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82150// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 02151// CHECK13-NEXT: store i32 0, ptr [[F]], align 42152// CHECK13-NEXT: ret void2153//2154//2155// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei2156// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {2157// CHECK13-NEXT: entry:2158// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82159// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 42160// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82161// CHECK13-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 42162// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82163// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 02164// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 42165// CHECK13-NEXT: store i32 [[TMP0]], ptr [[F]], align 42166// CHECK13-NEXT: ret void2167//2168//2169// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev2170// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {2171// CHECK13-NEXT: entry:2172// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82173// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82174// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82175// CHECK13-NEXT: ret void2176//2177//2178// CHECK15-LABEL: define {{[^@]+}}@main2179// CHECK15-SAME: () #[[ATTR0:[0-9]+]] {2180// CHECK15-NEXT: entry:2181// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 42182// CHECK15-NEXT: [[G:%.*]] = alloca double, align 82183// CHECK15-NEXT: [[G1:%.*]] = alloca ptr, align 42184// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 42185// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 42186// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 42187// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 42188// CHECK15-NEXT: [[VAR:%.*]] = alloca ptr, align 42189// CHECK15-NEXT: [[TMP:%.*]] = alloca ptr, align 42190// CHECK15-NEXT: [[_TMP1:%.*]] = alloca ptr, align 42191// CHECK15-NEXT: [[_TMP2:%.*]] = alloca ptr, align 42192// CHECK15-NEXT: [[_TMP3:%.*]] = alloca i32, align 42193// CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 42194// CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 42195// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 42196// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 42197// CHECK15-NEXT: store i32 0, ptr [[RETVAL]], align 42198// CHECK15-NEXT: store ptr [[G]], ptr [[G1]], align 42199// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])2200// CHECK15-NEXT: store i32 0, ptr [[T_VAR]], align 42201// CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i32 8, i1 false)2202// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], float noundef 1.000000e+00)2203// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i32 12204// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00)2205// CHECK15-NEXT: store ptr [[TEST]], ptr [[VAR]], align 42206// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]]2207// CHECK15-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 42208// CHECK15-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VAR]], align 4, !nonnull [[META3]], !align [[META4]]2209// CHECK15-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META3]], !align [[META4]]2210// CHECK15-NEXT: store ptr [[TMP2]], ptr [[_TMP1]], align 42211// CHECK15-NEXT: [[TMP3:%.*]] = load ptr, ptr [[_TMP1]], align 4, !nonnull [[META3]], !align [[META4]]2212// CHECK15-NEXT: store ptr [[TMP3]], ptr [[_TMP2]], align 42213// CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 42214// CHECK15-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 42215// CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42216// CHECK15-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 42217// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]2218// CHECK15: omp.inner.for.cond:2219// CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]]2220// CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP5]]2221// CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]2222// CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2223// CHECK15: omp.inner.for.body:2224// CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]2225// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 12226// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]2227// CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]]2228// CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP5]]2229// CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]]2230// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]]2231// CHECK15-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]]2232// CHECK15-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META3]], !align [[META4]], !llvm.access.group [[ACC_GRP5]]2233// CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]]2234// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP11]]2235// CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group [[ACC_GRP5]]2236// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]2237// CHECK15: omp.body.continue:2238// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]2239// CHECK15: omp.inner.for.inc:2240// CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]2241// CHECK15-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP12]], 12242// CHECK15-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]2243// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]2244// CHECK15: omp.inner.for.end:2245// CHECK15-NEXT: store i32 2, ptr [[I]], align 42246// CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()2247// CHECK15-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 42248// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 02249// CHECK15-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 22250// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]2251// CHECK15: arraydestroy.body:2252// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]2253// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -12254// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]]2255// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]2256// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]2257// CHECK15: arraydestroy.done6:2258// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]]2259// CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 42260// CHECK15-NEXT: ret i32 [[TMP14]]2261//2262//2263// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev2264// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {2265// CHECK15-NEXT: entry:2266// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42267// CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42268// CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42269// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])2270// CHECK15-NEXT: ret void2271//2272//2273// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef2274// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2275// CHECK15-NEXT: entry:2276// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42277// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 42278// CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42279// CHECK15-NEXT: store float [[A]], ptr [[A_ADDR]], align 42280// CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42281// CHECK15-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 42282// CHECK15-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])2283// CHECK15-NEXT: ret void2284//2285//2286// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiET_v2287// CHECK15-SAME: () #[[ATTR1]] comdat {2288// CHECK15-NEXT: entry:2289// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 42290// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 42291// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 42292// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 42293// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 42294// CHECK15-NEXT: [[VAR:%.*]] = alloca ptr, align 42295// CHECK15-NEXT: [[TMP:%.*]] = alloca ptr, align 42296// CHECK15-NEXT: [[_TMP1:%.*]] = alloca ptr, align 42297// CHECK15-NEXT: [[_TMP2:%.*]] = alloca ptr, align 42298// CHECK15-NEXT: [[_TMP3:%.*]] = alloca i32, align 42299// CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 42300// CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 42301// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 42302// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 42303// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])2304// CHECK15-NEXT: store i32 0, ptr [[T_VAR]], align 42305// CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false)2306// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1)2307// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 12308// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)2309// CHECK15-NEXT: store ptr [[TEST]], ptr [[VAR]], align 42310// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4, !nonnull [[META3]], !align [[META4]]2311// CHECK15-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 42312// CHECK15-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VAR]], align 4, !nonnull [[META3]], !align [[META4]]2313// CHECK15-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META3]], !align [[META4]]2314// CHECK15-NEXT: store ptr [[TMP2]], ptr [[_TMP1]], align 42315// CHECK15-NEXT: [[TMP3:%.*]] = load ptr, ptr [[_TMP1]], align 4, !nonnull [[META3]], !align [[META4]]2316// CHECK15-NEXT: store ptr [[TMP3]], ptr [[_TMP2]], align 42317// CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 42318// CHECK15-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 42319// CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42320// CHECK15-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 42321// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]2322// CHECK15: omp.inner.for.cond:2323// CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]]2324// CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP9]]2325// CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]2326// CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2327// CHECK15: omp.inner.for.body:2328// CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]2329// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 12330// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]2331// CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]2332// CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP9]]2333// CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]2334// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]]2335// CHECK15-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]]2336// CHECK15-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META3]], !align [[META4]], !llvm.access.group [[ACC_GRP9]]2337// CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]2338// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP11]]2339// CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group [[ACC_GRP9]]2340// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]2341// CHECK15: omp.body.continue:2342// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]2343// CHECK15: omp.inner.for.inc:2344// CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]2345// CHECK15-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP12]], 12346// CHECK15-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]2347// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]2348// CHECK15: omp.inner.for.end:2349// CHECK15-NEXT: store i32 2, ptr [[I]], align 42350// CHECK15-NEXT: store i32 0, ptr [[RETVAL]], align 42351// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 02352// CHECK15-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 22353// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]2354// CHECK15: arraydestroy.body:2355// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]2356// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -12357// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]2358// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]2359// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]2360// CHECK15: arraydestroy.done6:2361// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]]2362// CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 42363// CHECK15-NEXT: ret i32 [[TMP14]]2364//2365//2366// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev2367// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2368// CHECK15-NEXT: entry:2369// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42370// CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42371// CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42372// CHECK15-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]]2373// CHECK15-NEXT: ret void2374//2375//2376// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev2377// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2378// CHECK15-NEXT: entry:2379// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42380// CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42381// CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42382// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 02383// CHECK15-NEXT: store float 0.000000e+00, ptr [[F]], align 42384// CHECK15-NEXT: ret void2385//2386//2387// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev2388// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2389// CHECK15-NEXT: entry:2390// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42391// CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42392// CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42393// CHECK15-NEXT: ret void2394//2395//2396// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef2397// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2398// CHECK15-NEXT: entry:2399// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42400// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 42401// CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42402// CHECK15-NEXT: store float [[A]], ptr [[A_ADDR]], align 42403// CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42404// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 02405// CHECK15-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 42406// CHECK15-NEXT: store float [[TMP0]], ptr [[F]], align 42407// CHECK15-NEXT: ret void2408//2409//2410// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev2411// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2412// CHECK15-NEXT: entry:2413// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42414// CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42415// CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42416// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])2417// CHECK15-NEXT: ret void2418//2419//2420// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei2421// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2422// CHECK15-NEXT: entry:2423// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42424// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 42425// CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42426// CHECK15-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 42427// CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42428// CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 42429// CHECK15-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])2430// CHECK15-NEXT: ret void2431//2432//2433// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev2434// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2435// CHECK15-NEXT: entry:2436// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42437// CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42438// CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42439// CHECK15-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]]2440// CHECK15-NEXT: ret void2441//2442//2443// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev2444// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2445// CHECK15-NEXT: entry:2446// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42447// CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42448// CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42449// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 02450// CHECK15-NEXT: store i32 0, ptr [[F]], align 42451// CHECK15-NEXT: ret void2452//2453//2454// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei2455// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2456// CHECK15-NEXT: entry:2457// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42458// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 42459// CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42460// CHECK15-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 42461// CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42462// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 02463// CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 42464// CHECK15-NEXT: store i32 [[TMP0]], ptr [[F]], align 42465// CHECK15-NEXT: ret void2466//2467//2468// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev2469// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2470// CHECK15-NEXT: entry:2471// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42472// CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42473// CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42474// CHECK15-NEXT: ret void2475//2476