989 lines · cpp
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _2// RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s4// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15// RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK36// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s7// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK38 9// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK510// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s11// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK512// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK713// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s14// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK715 16// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK917// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s18// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK919 20// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1121// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s22// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1123 24// expected-no-diagnostics25#ifndef HEADER26#define HEADER27 28template <typename T>29T tmain() {30 T t_var = T();31 T vec[] = {1, 2};32#pragma omp target33#pragma omp teams34#pragma omp distribute simd reduction(+: t_var)35 for (int i = 0; i < 2; ++i) {36 t_var += (T) i;37 }38 return T();39}40 41int main() {42 static int sivar;43#ifdef LAMBDA44 [&]() {45#pragma omp target46#pragma omp teams47#pragma omp distribute simd reduction(+: sivar)48 for (int i = 0; i < 2; ++i) {49 50 // Skip global and bound tid vars51 52 53 sivar += i;54 55 [&]() {56 57 sivar += 4;58 59 }();60 }61 }();62 return 0;63#else64#pragma omp target65#pragma omp teams66#pragma omp distribute simd reduction(+: sivar)67 for (int i = 0; i < 2; ++i) {68 sivar += i;69 }70 return tmain<int>();71#endif72}73 74 75 76// Skip global and bound tid vars77 78 79 80 81// Skip global and bound tid vars82 83 84#endif85// CHECK1-LABEL: define {{[^@]+}}@main86// CHECK1-SAME: () #[[ATTR0:[0-9]+]] {87// CHECK1-NEXT: entry:88// CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 489// CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 890// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 891// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 892// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 893// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 494// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 895// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 496// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 497// CHECK1-NEXT: store i32 [[TMP0]], ptr [[SIVAR_CASTED]], align 498// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 899// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0100// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP2]], align 8101// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0102// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP3]], align 8103// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0104// CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8105// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0106// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0107// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0108// CHECK1-NEXT: store i32 3, ptr [[TMP7]], align 4109// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1110// CHECK1-NEXT: store i32 1, ptr [[TMP8]], align 4111// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2112// CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 8113// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3114// CHECK1-NEXT: store ptr [[TMP6]], ptr [[TMP10]], align 8115// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4116// CHECK1-NEXT: store ptr @.offload_sizes, ptr [[TMP11]], align 8117// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5118// CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP12]], align 8119// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6120// CHECK1-NEXT: store ptr null, ptr [[TMP13]], align 8121// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7122// CHECK1-NEXT: store ptr null, ptr [[TMP14]], align 8123// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8124// CHECK1-NEXT: store i64 2, ptr [[TMP15]], align 8125// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9126// CHECK1-NEXT: store i64 0, ptr [[TMP16]], align 8127// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10128// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4129// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11130// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP18]], align 4131// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12132// CHECK1-NEXT: store i32 0, ptr [[TMP19]], align 4133// CHECK1-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64.region_id, ptr [[KERNEL_ARGS]])134// CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0135// CHECK1-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]136// CHECK1: omp_offload.failed:137// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64(i64 [[TMP1]]) #[[ATTR2:[0-9]+]]138// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]139// CHECK1: omp_offload.cont:140// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()141// CHECK1-NEXT: ret i32 [[CALL]]142//143//144// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64145// CHECK1-SAME: (i64 noundef [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] {146// CHECK1-NEXT: entry:147// CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8148// CHECK1-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8149// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64.omp_outlined, ptr [[SIVAR_ADDR]])150// CHECK1-NEXT: ret void151//152//153// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64.omp_outlined154// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] {155// CHECK1-NEXT: entry:156// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8157// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8158// CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 8159// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4160// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4161// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4162// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4163// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4164// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4165// CHECK1-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4166// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4167// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8168// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8169// CHECK1-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8170// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8171// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4172// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4173// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4174// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4175// CHECK1-NEXT: store i32 0, ptr [[SIVAR1]], align 4176// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8177// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4178// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)179// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4180// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1181// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]182// CHECK1: cond.true:183// CHECK1-NEXT: br label [[COND_END:%.*]]184// CHECK1: cond.false:185// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4186// CHECK1-NEXT: br label [[COND_END]]187// CHECK1: cond.end:188// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]189// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4190// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4191// CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4192// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]193// CHECK1: omp.inner.for.cond:194// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]]195// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP5]]196// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]197// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]198// CHECK1: omp.inner.for.body:199// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]200// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1201// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]202// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]]203// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]]204// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[SIVAR1]], align 4, !llvm.access.group [[ACC_GRP5]]205// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]206// CHECK1-NEXT: store i32 [[ADD3]], ptr [[SIVAR1]], align 4, !llvm.access.group [[ACC_GRP5]]207// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]208// CHECK1: omp.body.continue:209// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]210// CHECK1: omp.inner.for.inc:211// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]212// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1213// CHECK1-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]214// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]215// CHECK1: omp.inner.for.end:216// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]217// CHECK1: omp.loop.exit:218// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])219// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4220// CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0221// CHECK1-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]222// CHECK1: .omp.final.then:223// CHECK1-NEXT: store i32 2, ptr [[I]], align 4224// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]225// CHECK1: .omp.final.done:226// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP0]], align 4227// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[SIVAR1]], align 4228// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]229// CHECK1-NEXT: store i32 [[ADD5]], ptr [[TMP0]], align 4230// CHECK1-NEXT: ret void231//232//233// CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v234// CHECK1-SAME: () #[[ATTR3:[0-9]+]] comdat {235// CHECK1-NEXT: entry:236// CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4237// CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4238// CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8239// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8240// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8241// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8242// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4243// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8244// CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4245// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)246// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 4247// CHECK1-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4248// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8249// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0250// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP2]], align 8251// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0252// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP3]], align 8253// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0254// CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8255// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0256// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0257// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0258// CHECK1-NEXT: store i32 3, ptr [[TMP7]], align 4259// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1260// CHECK1-NEXT: store i32 1, ptr [[TMP8]], align 4261// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2262// CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 8263// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3264// CHECK1-NEXT: store ptr [[TMP6]], ptr [[TMP10]], align 8265// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4266// CHECK1-NEXT: store ptr @.offload_sizes.1, ptr [[TMP11]], align 8267// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5268// CHECK1-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP12]], align 8269// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6270// CHECK1-NEXT: store ptr null, ptr [[TMP13]], align 8271// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7272// CHECK1-NEXT: store ptr null, ptr [[TMP14]], align 8273// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8274// CHECK1-NEXT: store i64 2, ptr [[TMP15]], align 8275// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9276// CHECK1-NEXT: store i64 0, ptr [[TMP16]], align 8277// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10278// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4279// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11280// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP18]], align 4281// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12282// CHECK1-NEXT: store i32 0, ptr [[TMP19]], align 4283// CHECK1-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, ptr [[KERNEL_ARGS]])284// CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0285// CHECK1-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]286// CHECK1: omp_offload.failed:287// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(i64 [[TMP1]]) #[[ATTR2]]288// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]289// CHECK1: omp_offload.cont:290// CHECK1-NEXT: ret i32 0291//292//293// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32294// CHECK1-SAME: (i64 noundef [[T_VAR:%.*]]) #[[ATTR1]] {295// CHECK1-NEXT: entry:296// CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8297// CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8298// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined, ptr [[T_VAR_ADDR]])299// CHECK1-NEXT: ret void300//301//302// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined303// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] {304// CHECK1-NEXT: entry:305// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8306// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8307// CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 8308// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4309// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4310// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4311// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4312// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4313// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4314// CHECK1-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4315// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4316// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8317// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8318// CHECK1-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8319// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8320// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4321// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4322// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4323// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4324// CHECK1-NEXT: store i32 0, ptr [[T_VAR1]], align 4325// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8326// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4327// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)328// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4329// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1330// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]331// CHECK1: cond.true:332// CHECK1-NEXT: br label [[COND_END:%.*]]333// CHECK1: cond.false:334// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4335// CHECK1-NEXT: br label [[COND_END]]336// CHECK1: cond.end:337// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]338// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4339// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4340// CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4341// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]342// CHECK1: omp.inner.for.cond:343// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]]344// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]]345// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]346// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]347// CHECK1: omp.inner.for.body:348// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]349// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1350// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]351// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]]352// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]]353// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP11]]354// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]355// CHECK1-NEXT: store i32 [[ADD3]], ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP11]]356// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]357// CHECK1: omp.body.continue:358// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]359// CHECK1: omp.inner.for.inc:360// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]361// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1362// CHECK1-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]363// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]364// CHECK1: omp.inner.for.end:365// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]366// CHECK1: omp.loop.exit:367// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])368// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4369// CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0370// CHECK1-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]371// CHECK1: .omp.final.then:372// CHECK1-NEXT: store i32 2, ptr [[I]], align 4373// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]374// CHECK1: .omp.final.done:375// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP0]], align 4376// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR1]], align 4377// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]378// CHECK1-NEXT: store i32 [[ADD5]], ptr [[TMP0]], align 4379// CHECK1-NEXT: ret void380//381//382// CHECK3-LABEL: define {{[^@]+}}@main383// CHECK3-SAME: () #[[ATTR0:[0-9]+]] {384// CHECK3-NEXT: entry:385// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4386// CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4387// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4388// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4389// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4390// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4391// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8392// CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4393// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4394// CHECK3-NEXT: store i32 [[TMP0]], ptr [[SIVAR_CASTED]], align 4395// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4396// CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0397// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP2]], align 4398// CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0399// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP3]], align 4400// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0401// CHECK3-NEXT: store ptr null, ptr [[TMP4]], align 4402// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0403// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0404// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0405// CHECK3-NEXT: store i32 3, ptr [[TMP7]], align 4406// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1407// CHECK3-NEXT: store i32 1, ptr [[TMP8]], align 4408// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2409// CHECK3-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 4410// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3411// CHECK3-NEXT: store ptr [[TMP6]], ptr [[TMP10]], align 4412// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4413// CHECK3-NEXT: store ptr @.offload_sizes, ptr [[TMP11]], align 4414// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5415// CHECK3-NEXT: store ptr @.offload_maptypes, ptr [[TMP12]], align 4416// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6417// CHECK3-NEXT: store ptr null, ptr [[TMP13]], align 4418// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7419// CHECK3-NEXT: store ptr null, ptr [[TMP14]], align 4420// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8421// CHECK3-NEXT: store i64 2, ptr [[TMP15]], align 8422// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9423// CHECK3-NEXT: store i64 0, ptr [[TMP16]], align 8424// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10425// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4426// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11427// CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP18]], align 4428// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12429// CHECK3-NEXT: store i32 0, ptr [[TMP19]], align 4430// CHECK3-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64.region_id, ptr [[KERNEL_ARGS]])431// CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0432// CHECK3-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]433// CHECK3: omp_offload.failed:434// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64(i32 [[TMP1]]) #[[ATTR2:[0-9]+]]435// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]436// CHECK3: omp_offload.cont:437// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()438// CHECK3-NEXT: ret i32 [[CALL]]439//440//441// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64442// CHECK3-SAME: (i32 noundef [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] {443// CHECK3-NEXT: entry:444// CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4445// CHECK3-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4446// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64.omp_outlined, ptr [[SIVAR_ADDR]])447// CHECK3-NEXT: ret void448//449//450// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64.omp_outlined451// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] {452// CHECK3-NEXT: entry:453// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4454// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4455// CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 4456// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4457// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4458// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4459// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4460// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4461// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4462// CHECK3-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4463// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4464// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4465// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4466// CHECK3-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 4467// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 4468// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4469// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4470// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4471// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4472// CHECK3-NEXT: store i32 0, ptr [[SIVAR1]], align 4473// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4474// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4475// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)476// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4477// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1478// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]479// CHECK3: cond.true:480// CHECK3-NEXT: br label [[COND_END:%.*]]481// CHECK3: cond.false:482// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4483// CHECK3-NEXT: br label [[COND_END]]484// CHECK3: cond.end:485// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]486// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4487// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4488// CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4489// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]490// CHECK3: omp.inner.for.cond:491// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]]492// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP6]]493// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]494// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]495// CHECK3: omp.inner.for.body:496// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]497// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1498// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]499// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]500// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]501// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[SIVAR1]], align 4, !llvm.access.group [[ACC_GRP6]]502// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]503// CHECK3-NEXT: store i32 [[ADD3]], ptr [[SIVAR1]], align 4, !llvm.access.group [[ACC_GRP6]]504// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]505// CHECK3: omp.body.continue:506// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]507// CHECK3: omp.inner.for.inc:508// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]509// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1510// CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]511// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]512// CHECK3: omp.inner.for.end:513// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]514// CHECK3: omp.loop.exit:515// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])516// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4517// CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0518// CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]519// CHECK3: .omp.final.then:520// CHECK3-NEXT: store i32 2, ptr [[I]], align 4521// CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]522// CHECK3: .omp.final.done:523// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP0]], align 4524// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[SIVAR1]], align 4525// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]526// CHECK3-NEXT: store i32 [[ADD5]], ptr [[TMP0]], align 4527// CHECK3-NEXT: ret void528//529//530// CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v531// CHECK3-SAME: () #[[ATTR3:[0-9]+]] comdat {532// CHECK3-NEXT: entry:533// CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4534// CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4535// CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4536// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4537// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4538// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4539// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4540// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8541// CHECK3-NEXT: store i32 0, ptr [[T_VAR]], align 4542// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false)543// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 4544// CHECK3-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4545// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4546// CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0547// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP2]], align 4548// CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0549// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP3]], align 4550// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0551// CHECK3-NEXT: store ptr null, ptr [[TMP4]], align 4552// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0553// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0554// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0555// CHECK3-NEXT: store i32 3, ptr [[TMP7]], align 4556// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1557// CHECK3-NEXT: store i32 1, ptr [[TMP8]], align 4558// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2559// CHECK3-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 4560// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3561// CHECK3-NEXT: store ptr [[TMP6]], ptr [[TMP10]], align 4562// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4563// CHECK3-NEXT: store ptr @.offload_sizes.1, ptr [[TMP11]], align 4564// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5565// CHECK3-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP12]], align 4566// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6567// CHECK3-NEXT: store ptr null, ptr [[TMP13]], align 4568// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7569// CHECK3-NEXT: store ptr null, ptr [[TMP14]], align 4570// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8571// CHECK3-NEXT: store i64 2, ptr [[TMP15]], align 8572// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9573// CHECK3-NEXT: store i64 0, ptr [[TMP16]], align 8574// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10575// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4576// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11577// CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP18]], align 4578// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12579// CHECK3-NEXT: store i32 0, ptr [[TMP19]], align 4580// CHECK3-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, ptr [[KERNEL_ARGS]])581// CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0582// CHECK3-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]583// CHECK3: omp_offload.failed:584// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(i32 [[TMP1]]) #[[ATTR2]]585// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]586// CHECK3: omp_offload.cont:587// CHECK3-NEXT: ret i32 0588//589//590// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32591// CHECK3-SAME: (i32 noundef [[T_VAR:%.*]]) #[[ATTR1]] {592// CHECK3-NEXT: entry:593// CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4594// CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4595// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined, ptr [[T_VAR_ADDR]])596// CHECK3-NEXT: ret void597//598//599// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined600// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] {601// CHECK3-NEXT: entry:602// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4603// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4604// CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 4605// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4606// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4607// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4608// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4609// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4610// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4611// CHECK3-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4612// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4613// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4614// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4615// CHECK3-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 4616// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4617// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4618// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4619// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4620// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4621// CHECK3-NEXT: store i32 0, ptr [[T_VAR1]], align 4622// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4623// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4624// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)625// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4626// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1627// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]628// CHECK3: cond.true:629// CHECK3-NEXT: br label [[COND_END:%.*]]630// CHECK3: cond.false:631// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4632// CHECK3-NEXT: br label [[COND_END]]633// CHECK3: cond.end:634// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]635// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4636// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4637// CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4638// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]639// CHECK3: omp.inner.for.cond:640// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]]641// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]]642// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]643// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]644// CHECK3: omp.inner.for.body:645// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]646// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1647// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]648// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]]649// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]]650// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP12]]651// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]652// CHECK3-NEXT: store i32 [[ADD3]], ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP12]]653// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]654// CHECK3: omp.body.continue:655// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]656// CHECK3: omp.inner.for.inc:657// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]658// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1659// CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]660// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]661// CHECK3: omp.inner.for.end:662// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]663// CHECK3: omp.loop.exit:664// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])665// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4666// CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0667// CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]668// CHECK3: .omp.final.then:669// CHECK3-NEXT: store i32 2, ptr [[I]], align 4670// CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]671// CHECK3: .omp.final.done:672// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP0]], align 4673// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR1]], align 4674// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]675// CHECK3-NEXT: store i32 [[ADD5]], ptr [[TMP0]], align 4676// CHECK3-NEXT: ret void677//678//679// CHECK5-LABEL: define {{[^@]+}}@main680// CHECK5-SAME: () #[[ATTR0:[0-9]+]] {681// CHECK5-NEXT: entry:682// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4683// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4684// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4685// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4686// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4687// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4688// CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4689// CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 4690// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4691// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4692// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4693// CHECK5-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4694// CHECK5-NEXT: store i32 0, ptr [[SIVAR]], align 4695// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]696// CHECK5: omp.inner.for.cond:697// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]]698// CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]]699// CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]700// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]701// CHECK5: omp.inner.for.body:702// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]703// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1704// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]705// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]706// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]707// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP2]]708// CHECK5-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP5]], [[TMP4]]709// CHECK5-NEXT: store i32 [[ADD1]], ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP2]]710// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]711// CHECK5: omp.body.continue:712// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]713// CHECK5: omp.inner.for.inc:714// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]715// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1716// CHECK5-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]717// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]718// CHECK5: omp.inner.for.end:719// CHECK5-NEXT: store i32 2, ptr [[I]], align 4720// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4721// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[SIVAR]], align 4722// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]]723// CHECK5-NEXT: store i32 [[ADD3]], ptr @_ZZ4mainE5sivar, align 4724// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()725// CHECK5-NEXT: ret i32 [[CALL]]726//727//728// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v729// CHECK5-SAME: () #[[ATTR1:[0-9]+]] comdat {730// CHECK5-NEXT: entry:731// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4732// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4733// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4734// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4735// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4736// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4737// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4738// CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4739// CHECK5-NEXT: store i32 0, ptr [[T_VAR]], align 4740// CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)741// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4742// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4743// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4744// CHECK5-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4745// CHECK5-NEXT: store i32 0, ptr [[T_VAR1]], align 4746// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]747// CHECK5: omp.inner.for.cond:748// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]]749// CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP6]]750// CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]751// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]752// CHECK5: omp.inner.for.body:753// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]754// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1755// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]756// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]757// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]758// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP6]]759// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP5]], [[TMP4]]760// CHECK5-NEXT: store i32 [[ADD2]], ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP6]]761// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]762// CHECK5: omp.body.continue:763// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]764// CHECK5: omp.inner.for.inc:765// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]766// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP6]], 1767// CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]768// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]769// CHECK5: omp.inner.for.end:770// CHECK5-NEXT: store i32 2, ptr [[I]], align 4771// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[T_VAR]], align 4772// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR1]], align 4773// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP7]], [[TMP8]]774// CHECK5-NEXT: store i32 [[ADD4]], ptr [[T_VAR]], align 4775// CHECK5-NEXT: ret i32 0776//777//778// CHECK7-LABEL: define {{[^@]+}}@main779// CHECK7-SAME: () #[[ATTR0:[0-9]+]] {780// CHECK7-NEXT: entry:781// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4782// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4783// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4784// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4785// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4786// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4787// CHECK7-NEXT: [[SIVAR:%.*]] = alloca i32, align 4788// CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 4789// CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4790// CHECK7-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4791// CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4792// CHECK7-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4793// CHECK7-NEXT: store i32 0, ptr [[SIVAR]], align 4794// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]795// CHECK7: omp.inner.for.cond:796// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]]797// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]]798// CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]799// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]800// CHECK7: omp.inner.for.body:801// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]802// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1803// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]804// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]805// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]806// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP3]]807// CHECK7-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP5]], [[TMP4]]808// CHECK7-NEXT: store i32 [[ADD1]], ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP3]]809// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]810// CHECK7: omp.body.continue:811// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]812// CHECK7: omp.inner.for.inc:813// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]814// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1815// CHECK7-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]816// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]817// CHECK7: omp.inner.for.end:818// CHECK7-NEXT: store i32 2, ptr [[I]], align 4819// CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4820// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[SIVAR]], align 4821// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]]822// CHECK7-NEXT: store i32 [[ADD3]], ptr @_ZZ4mainE5sivar, align 4823// CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()824// CHECK7-NEXT: ret i32 [[CALL]]825//826//827// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v828// CHECK7-SAME: () #[[ATTR1:[0-9]+]] comdat {829// CHECK7-NEXT: entry:830// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4831// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4832// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4833// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4834// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4835// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4836// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4837// CHECK7-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4838// CHECK7-NEXT: store i32 0, ptr [[T_VAR]], align 4839// CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false)840// CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4841// CHECK7-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4842// CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4843// CHECK7-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4844// CHECK7-NEXT: store i32 0, ptr [[T_VAR1]], align 4845// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]846// CHECK7: omp.inner.for.cond:847// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]]848// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP7]]849// CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]850// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]851// CHECK7: omp.inner.for.body:852// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]853// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1854// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]855// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]]856// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]]857// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP7]]858// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP5]], [[TMP4]]859// CHECK7-NEXT: store i32 [[ADD2]], ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP7]]860// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]861// CHECK7: omp.body.continue:862// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]863// CHECK7: omp.inner.for.inc:864// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]865// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP6]], 1866// CHECK7-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]867// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]868// CHECK7: omp.inner.for.end:869// CHECK7-NEXT: store i32 2, ptr [[I]], align 4870// CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[T_VAR]], align 4871// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR1]], align 4872// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP7]], [[TMP8]]873// CHECK7-NEXT: store i32 [[ADD4]], ptr [[T_VAR]], align 4874// CHECK7-NEXT: ret i32 0875//876//877// CHECK9-LABEL: define {{[^@]+}}@main878// CHECK9-SAME: () #[[ATTR0:[0-9]+]] {879// CHECK9-NEXT: entry:880// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4881// CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1882// CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4883// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])884// CHECK9-NEXT: ret i32 0885//886//887// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45888// CHECK9-SAME: (i64 noundef [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] {889// CHECK9-NEXT: entry:890// CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8891// CHECK9-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8892// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45.omp_outlined, ptr [[SIVAR_ADDR]])893// CHECK9-NEXT: ret void894//895//896// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45.omp_outlined897// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] {898// CHECK9-NEXT: entry:899// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8900// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8901// CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 8902// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4903// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4904// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4905// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4906// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4907// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4908// CHECK9-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4909// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4910// CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8911// CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8912// CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8913// CHECK9-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8914// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8915// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4916// CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4917// CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4918// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4919// CHECK9-NEXT: store i32 0, ptr [[SIVAR1]], align 4920// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8921// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4922// CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)923// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4924// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1925// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]926// CHECK9: cond.true:927// CHECK9-NEXT: br label [[COND_END:%.*]]928// CHECK9: cond.false:929// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4930// CHECK9-NEXT: br label [[COND_END]]931// CHECK9: cond.end:932// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]933// CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4934// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4935// CHECK9-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4936// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]937// CHECK9: omp.inner.for.cond:938// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4:![0-9]+]]939// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP4]]940// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]941// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]942// CHECK9: omp.inner.for.body:943// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]944// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1945// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]946// CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]]947// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]]948// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[SIVAR1]], align 4, !llvm.access.group [[ACC_GRP4]]949// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]950// CHECK9-NEXT: store i32 [[ADD3]], ptr [[SIVAR1]], align 4, !llvm.access.group [[ACC_GRP4]]951// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0952// CHECK9-NEXT: store ptr [[SIVAR1]], ptr [[TMP11]], align 8, !llvm.access.group [[ACC_GRP4]]953// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(8) [[REF_TMP]]), !llvm.access.group [[ACC_GRP4]]954// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]955// CHECK9: omp.body.continue:956// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]957// CHECK9: omp.inner.for.inc:958// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]959// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1960// CHECK9-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]961// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]962// CHECK9: omp.inner.for.end:963// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]964// CHECK9: omp.loop.exit:965// CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])966// CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4967// CHECK9-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0968// CHECK9-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]969// CHECK9: .omp.final.then:970// CHECK9-NEXT: store i32 2, ptr [[I]], align 4971// CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]972// CHECK9: .omp.final.done:973// CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP0]], align 4974// CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR1]], align 4975// CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]976// CHECK9-NEXT: store i32 [[ADD5]], ptr [[TMP0]], align 4977// CHECK9-NEXT: ret void978//979//980// CHECK11-LABEL: define {{[^@]+}}@main981// CHECK11-SAME: () #[[ATTR0:[0-9]+]] {982// CHECK11-NEXT: entry:983// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4984// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1985// CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4986// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])987// CHECK11-NEXT: ret i32 0988//989