1155 lines · cpp
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _2// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s4// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK36// RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK47 8// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"9// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s10// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"11// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"12// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"13// expected-no-diagnostics14#ifndef HEADER15#define HEADER16 17struct St {18 int a, b;19 St() : a(0), b(0) {}20 St(const St &st) : a(st.a + st.b), b(0) {}21 ~St() {}22};23 24volatile int g = 1212;25volatile int &g1 = g;26 27template <class T>28struct S {29 T f;30 S(T a) : f(a + g) {}31 S() : f(g) {}32 S(const S &s, St t = St()) : f(s.f + t.a) {}33 operator T() { return T(); }34 ~S() {}35};36 37 38template <typename T>39T tmain() {40 S<T> test;41 T t_var = T();42 T vec[] = {1, 2};43 S<T> s_arr[] = {1, 2};44 S<T> &var = test;45#pragma omp parallel46#pragma omp for firstprivate(t_var, vec, s_arr, var)47 for (int i = 0; i < 2; ++i) {48 vec[i] = t_var;49 s_arr[i] = var;50 }51 return T();52}53 54S<float> test;55int t_var = 333;56int vec[] = {1, 2};57S<float> s_arr[] = {1, 2};58S<float> var(3);59 60int main() {61 static int sivar;62#ifdef LAMBDA63 [&]() {64#pragma omp parallel65#pragma omp for firstprivate(g, g1, sivar)66 for (int i = 0; i < 2; ++i) {67 // Skip temp vars for loop68 69 70 71 72 g = 1;73 g1 = 2;74 sivar = 3;75 76 [&]() {77 g = 4;78 g1 = 5;79 sivar = 6;80 81 }();82 }83 }();84 return 0;85#elif defined(BLOCKS)86 ^{87#pragma omp parallel88#pragma omp for firstprivate(g, g1, sivar)89 for (int i = 0; i < 2; ++i) {90 // Skip temp vars for loop91 92 93 94 95 g = 1;96 g1 =1;97 sivar = 2;98 ^{99 g = 2;100 g1 = 2;101 sivar = 4;102 }();103 }104 }();105 return 0;106#else107#pragma omp for firstprivate(t_var, vec, s_arr, var, sivar)108 for (int i = 0; i < 2; ++i) {109 vec[i] = t_var;110 s_arr[i] = var;111 sivar += i;112 }113 return tmain<int>();114#endif115}116 117// Skip temp vars for loop118 119// firstprivate t_var(t_var)120 121// firstprivate vec(vec)122 123// firstprivate s_arr(s_arr)124 125// firstprivate var(var)126 127// firstprivate (sivar)128 129// Synchronization for initialization.130 131 132// ~(firstprivate var), ~(firstprivate s_arr)133 134 135 136// Skip temp vars for loop137 138 139// firstprivate vec(vec)140 141// firstprivate s_arr(s_arr)142 143// firstprivate var(var)144 145// No synchronization for initialization.146 147 148// ~(firstprivate var), ~(firstprivate s_arr)149#endif150 151// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init152// CHECK1-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" {153// CHECK1-NEXT: entry:154// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)155// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]156// CHECK1-NEXT: ret void157//158//159// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev160// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 {161// CHECK1-NEXT: entry:162// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8163// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8164// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8165// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])166// CHECK1-NEXT: ret void167//168//169// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev170// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {171// CHECK1-NEXT: entry:172// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8173// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8174// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8175// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]176// CHECK1-NEXT: ret void177//178//179// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev180// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {181// CHECK1-NEXT: entry:182// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8183// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8184// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8185// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0186// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4187// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float188// CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4189// CHECK1-NEXT: ret void190//191//192// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev193// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {194// CHECK1-NEXT: entry:195// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8196// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8197// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8198// CHECK1-NEXT: ret void199//200//201// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1202// CHECK1-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {203// CHECK1-NEXT: entry:204// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)205// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)206// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]207// CHECK1-NEXT: ret void208//209//210// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef211// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {212// CHECK1-NEXT: entry:213// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8214// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4215// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8216// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4217// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8218// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4219// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])220// CHECK1-NEXT: ret void221//222//223// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor224// CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {225// CHECK1-NEXT: entry:226// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8227// CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8228// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]229// CHECK1: arraydestroy.body:230// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]231// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1232// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]233// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr234// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]235// CHECK1: arraydestroy.done1:236// CHECK1-NEXT: ret void237//238//239// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef240// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {241// CHECK1-NEXT: entry:242// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8243// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4244// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8245// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4246// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8247// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0248// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4249// CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4250// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float251// CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]252// CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4253// CHECK1-NEXT: ret void254//255//256// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2257// CHECK1-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {258// CHECK1-NEXT: entry:259// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)260// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]261// CHECK1-NEXT: ret void262//263//264// CHECK1-LABEL: define {{[^@]+}}@main265// CHECK1-SAME: () #[[ATTR3:[0-9]+]] {266// CHECK1-NEXT: entry:267// CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4268// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4269// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4270// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4271// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4272// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4273// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4274// CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4275// CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4276// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4277// CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4278// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4279// CHECK1-NEXT: [[AGG_TMP2:%.*]] = alloca [[STRUCT_ST]], align 4280// CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4281// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4282// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])283// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4284// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4285// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4286// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4287// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4288// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr @t_var, align 4289// CHECK1-NEXT: store i32 [[TMP1]], ptr [[T_VAR]], align 4290// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @vec, i64 8, i1 false)291// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0292// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2293// CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP2]]294// CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]295// CHECK1: omp.arraycpy.body:296// CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ @s_arr, [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]297// CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]298// CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])299// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]])300// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]301// CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1302// CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1303// CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP2]]304// CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]]305// CHECK1: omp.arraycpy.done1:306// CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP2]])307// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]], ptr noundef nonnull align 4 dereferenceable(4) @var, ptr noundef [[AGG_TMP2]])308// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP2]]) #[[ATTR2]]309// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4310// CHECK1-NEXT: store i32 [[TMP3]], ptr [[SIVAR]], align 4311// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)312// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4313// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1314// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]315// CHECK1: cond.true:316// CHECK1-NEXT: br label [[COND_END:%.*]]317// CHECK1: cond.false:318// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4319// CHECK1-NEXT: br label [[COND_END]]320// CHECK1: cond.end:321// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]322// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4323// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4324// CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4325// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]326// CHECK1: omp.inner.for.cond:327// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4328// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4329// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]330// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]331// CHECK1: omp.inner.for.cond.cleanup:332// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]333// CHECK1: omp.inner.for.body:334// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4335// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1336// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]337// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4338// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4339// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4340// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64341// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]]342// CHECK1-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4343// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4344// CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP12]] to i64345// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]]346// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[VAR]], i64 4, i1 false)347// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4348// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4349// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], [[TMP13]]350// CHECK1-NEXT: store i32 [[ADD6]], ptr [[SIVAR]], align 4351// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]352// CHECK1: omp.body.continue:353// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]354// CHECK1: omp.inner.for.inc:355// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4356// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP15]], 1357// CHECK1-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4358// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]359// CHECK1: omp.inner.for.end:360// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]361// CHECK1: omp.loop.exit:362// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]])363// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]364// CHECK1-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0365// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN8]], i64 2366// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]367// CHECK1: arraydestroy.body:368// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP16]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]369// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1370// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]371// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]]372// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]]373// CHECK1: arraydestroy.done9:374// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP0]])375// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()376// CHECK1-NEXT: ret i32 [[CALL]]377//378//379// CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev380// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {381// CHECK1-NEXT: entry:382// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8383// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8384// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8385// CHECK1-NEXT: call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]])386// CHECK1-NEXT: ret void387//388//389// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St390// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {391// CHECK1-NEXT: entry:392// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8393// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8394// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8395// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8396// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8397// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8398// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8399// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8400// CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]])401// CHECK1-NEXT: ret void402//403//404// CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev405// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {406// CHECK1-NEXT: entry:407// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8408// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8409// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8410// CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]]411// CHECK1-NEXT: ret void412//413//414// CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v415// CHECK1-SAME: () #[[ATTR1]] {416// CHECK1-NEXT: entry:417// CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4418// CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4419// CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4420// CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4421// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4422// CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8423// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])424// CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4425// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)426// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1)427// CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1428// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)429// CHECK1-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8430// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]]431// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_Z5tmainIiET_v.omp_outlined, ptr [[T_VAR]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP0]])432// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4433// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0434// CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2435// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]436// CHECK1: arraydestroy.body:437// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]438// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1439// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]440// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]441// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]442// CHECK1: arraydestroy.done1:443// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]444// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[RETVAL]], align 4445// CHECK1-NEXT: ret i32 [[TMP2]]446//447//448// CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev449// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {450// CHECK1-NEXT: entry:451// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8452// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8453// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8454// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0455// CHECK1-NEXT: store i32 0, ptr [[A]], align 4456// CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1457// CHECK1-NEXT: store i32 0, ptr [[B]], align 4458// CHECK1-NEXT: ret void459//460//461// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St462// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {463// CHECK1-NEXT: entry:464// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8465// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8466// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8467// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8468// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8469// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8470// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8471// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0472// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8, !nonnull [[META3]], !align [[META4]]473// CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0474// CHECK1-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4475// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0476// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4477// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float478// CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]479// CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4480// CHECK1-NEXT: ret void481//482//483// CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev484// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {485// CHECK1-NEXT: entry:486// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8487// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8488// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8489// CHECK1-NEXT: ret void490//491//492// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev493// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {494// CHECK1-NEXT: entry:495// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8496// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8497// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8498// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])499// CHECK1-NEXT: ret void500//501//502// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei503// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {504// CHECK1-NEXT: entry:505// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8506// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4507// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8508// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4509// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8510// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4511// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])512// CHECK1-NEXT: ret void513//514//515// CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v.omp_outlined516// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR6:[0-9]+]] {517// CHECK1-NEXT: entry:518// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8519// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8520// CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 8521// CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8522// CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8523// CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8524// CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8525// CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8526// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4527// CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4528// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4529// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4530// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4531// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4532// CHECK1-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4533// CHECK1-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4534// CHECK1-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4535// CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4536// CHECK1-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4537// CHECK1-NEXT: [[AGG_TMP8:%.*]] = alloca [[STRUCT_ST]], align 4538// CHECK1-NEXT: [[_TMP9:%.*]] = alloca ptr, align 8539// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4540// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8541// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8542// CHECK1-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8543// CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8544// CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8545// CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8546// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]]547// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META3]], !align [[META4]]548// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]]549// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]]550// CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 8551// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META3]], !align [[META4]]552// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8553// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4554// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4555// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4556// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4557// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4558// CHECK1-NEXT: store i32 [[TMP5]], ptr [[T_VAR3]], align 4559// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC4]], ptr align 4 [[TMP1]], i64 8, i1 false)560// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0561// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2562// CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP6]]563// CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]564// CHECK1: omp.arraycpy.body:565// CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]566// CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]567// CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])568// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]])569// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]570// CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1571// CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1572// CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]573// CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]]574// CHECK1: omp.arraycpy.done6:575// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META3]], !align [[META4]]576// CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP8]])577// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP7]], ptr noundef [[AGG_TMP8]])578// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR2]]579// CHECK1-NEXT: store ptr [[VAR7]], ptr [[_TMP9]], align 8580// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8581// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4582// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP9]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)583// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4584// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1585// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]586// CHECK1: cond.true:587// CHECK1-NEXT: br label [[COND_END:%.*]]588// CHECK1: cond.false:589// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4590// CHECK1-NEXT: br label [[COND_END]]591// CHECK1: cond.end:592// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]593// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4594// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4595// CHECK1-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 4596// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]597// CHECK1: omp.inner.for.cond:598// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4599// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4600// CHECK1-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]601// CHECK1-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]602// CHECK1: omp.inner.for.cond.cleanup:603// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]604// CHECK1: omp.inner.for.body:605// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4606// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1607// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]608// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4609// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[T_VAR3]], align 4610// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4611// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64612// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]]613// CHECK1-NEXT: store i32 [[TMP16]], ptr [[ARRAYIDX]], align 4614// CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP9]], align 8, !nonnull [[META3]], !align [[META4]]615// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4616// CHECK1-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP19]] to i64617// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM11]]618// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX12]], ptr align 4 [[TMP18]], i64 4, i1 false)619// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]620// CHECK1: omp.body.continue:621// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]622// CHECK1: omp.inner.for.inc:623// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4624// CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1625// CHECK1-NEXT: store i32 [[ADD13]], ptr [[DOTOMP_IV]], align 4626// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]627// CHECK1: omp.inner.for.end:628// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]629// CHECK1: omp.loop.exit:630// CHECK1-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8631// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4632// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP22]])633// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR2]]634// CHECK1-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0635// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN14]], i64 2636// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]637// CHECK1: arraydestroy.body:638// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP23]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]639// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1640// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]641// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]]642// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]]643// CHECK1: arraydestroy.done15:644// CHECK1-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8645// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[TMP24]], align 4646// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP25]])647// CHECK1-NEXT: ret void648//649//650// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St651// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {652// CHECK1-NEXT: entry:653// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8654// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8655// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8656// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8657// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8658// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8659// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8660// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8661// CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]])662// CHECK1-NEXT: ret void663//664//665// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev666// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {667// CHECK1-NEXT: entry:668// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8669// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8670// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8671// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]672// CHECK1-NEXT: ret void673//674//675// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev676// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {677// CHECK1-NEXT: entry:678// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8679// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8680// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8681// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0682// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4683// CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4684// CHECK1-NEXT: ret void685//686//687// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei688// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {689// CHECK1-NEXT: entry:690// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8691// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4692// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8693// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4694// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8695// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0696// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4697// CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4698// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]699// CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4700// CHECK1-NEXT: ret void701//702//703// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St704// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {705// CHECK1-NEXT: entry:706// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8707// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8708// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8709// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8710// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8711// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8712// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8713// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0714// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8, !nonnull [[META3]], !align [[META4]]715// CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0716// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4717// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0718// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4719// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]720// CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4721// CHECK1-NEXT: ret void722//723//724// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev725// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {726// CHECK1-NEXT: entry:727// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8728// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8729// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8730// CHECK1-NEXT: ret void731//732//733// CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_for_firstprivate_codegen.cpp734// CHECK1-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {735// CHECK1-NEXT: entry:736// CHECK1-NEXT: call void @__cxx_global_var_init()737// CHECK1-NEXT: call void @__cxx_global_var_init.1()738// CHECK1-NEXT: call void @__cxx_global_var_init.2()739// CHECK1-NEXT: ret void740//741//742// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init743// CHECK3-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" {744// CHECK3-NEXT: entry:745// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)746// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]747// CHECK3-NEXT: ret void748//749//750// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev751// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 {752// CHECK3-NEXT: entry:753// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8754// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8755// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8756// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])757// CHECK3-NEXT: ret void758//759//760// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev761// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {762// CHECK3-NEXT: entry:763// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8764// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8765// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8766// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]767// CHECK3-NEXT: ret void768//769//770// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev771// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {772// CHECK3-NEXT: entry:773// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8774// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8775// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8776// CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0777// CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4778// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float779// CHECK3-NEXT: store float [[CONV]], ptr [[F]], align 4780// CHECK3-NEXT: ret void781//782//783// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev784// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {785// CHECK3-NEXT: entry:786// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8787// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8788// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8789// CHECK3-NEXT: ret void790//791//792// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1793// CHECK3-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {794// CHECK3-NEXT: entry:795// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)796// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)797// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]798// CHECK3-NEXT: ret void799//800//801// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef802// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {803// CHECK3-NEXT: entry:804// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8805// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4806// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8807// CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4808// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8809// CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4810// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])811// CHECK3-NEXT: ret void812//813//814// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor815// CHECK3-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {816// CHECK3-NEXT: entry:817// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8818// CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8819// CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]820// CHECK3: arraydestroy.body:821// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]822// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1823// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]824// CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr825// CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]826// CHECK3: arraydestroy.done1:827// CHECK3-NEXT: ret void828//829//830// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef831// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {832// CHECK3-NEXT: entry:833// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8834// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4835// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8836// CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4837// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8838// CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0839// CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4840// CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4841// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float842// CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]843// CHECK3-NEXT: store float [[ADD]], ptr [[F]], align 4844// CHECK3-NEXT: ret void845//846//847// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2848// CHECK3-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {849// CHECK3-NEXT: entry:850// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)851// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]852// CHECK3-NEXT: ret void853//854//855// CHECK3-LABEL: define {{[^@]+}}@main856// CHECK3-SAME: () #[[ATTR3:[0-9]+]] {857// CHECK3-NEXT: entry:858// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4859// CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8860// CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4861// CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0862// CHECK3-NEXT: store ptr @_ZZ4mainE5sivar, ptr [[TMP0]], align 8863// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(8) [[REF_TMP]])864// CHECK3-NEXT: ret i32 0865//866//867// CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_for_firstprivate_codegen.cpp868// CHECK3-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {869// CHECK3-NEXT: entry:870// CHECK3-NEXT: call void @__cxx_global_var_init()871// CHECK3-NEXT: call void @__cxx_global_var_init.1()872// CHECK3-NEXT: call void @__cxx_global_var_init.2()873// CHECK3-NEXT: ret void874//875//876// CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init877// CHECK4-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" {878// CHECK4-NEXT: entry:879// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)880// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]881// CHECK4-NEXT: ret void882//883//884// CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev885// CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 {886// CHECK4-NEXT: entry:887// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8888// CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8889// CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8890// CHECK4-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])891// CHECK4-NEXT: ret void892//893//894// CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev895// CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {896// CHECK4-NEXT: entry:897// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8898// CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8899// CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8900// CHECK4-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]901// CHECK4-NEXT: ret void902//903//904// CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev905// CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {906// CHECK4-NEXT: entry:907// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8908// CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8909// CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8910// CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0911// CHECK4-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4912// CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float913// CHECK4-NEXT: store float [[CONV]], ptr [[F]], align 4914// CHECK4-NEXT: ret void915//916//917// CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev918// CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {919// CHECK4-NEXT: entry:920// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8921// CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8922// CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8923// CHECK4-NEXT: ret void924//925//926// CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1927// CHECK4-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {928// CHECK4-NEXT: entry:929// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)930// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)931// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]932// CHECK4-NEXT: ret void933//934//935// CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef936// CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {937// CHECK4-NEXT: entry:938// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8939// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4940// CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8941// CHECK4-NEXT: store float [[A]], ptr [[A_ADDR]], align 4942// CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8943// CHECK4-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4944// CHECK4-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])945// CHECK4-NEXT: ret void946//947//948// CHECK4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor949// CHECK4-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {950// CHECK4-NEXT: entry:951// CHECK4-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8952// CHECK4-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8953// CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]954// CHECK4: arraydestroy.body:955// CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]956// CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1957// CHECK4-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]958// CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr959// CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]960// CHECK4: arraydestroy.done1:961// CHECK4-NEXT: ret void962//963//964// CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef965// CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {966// CHECK4-NEXT: entry:967// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8968// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4969// CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8970// CHECK4-NEXT: store float [[A]], ptr [[A_ADDR]], align 4971// CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8972// CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0973// CHECK4-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4974// CHECK4-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4975// CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float976// CHECK4-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]977// CHECK4-NEXT: store float [[ADD]], ptr [[F]], align 4978// CHECK4-NEXT: ret void979//980//981// CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2982// CHECK4-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {983// CHECK4-NEXT: entry:984// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)985// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]986// CHECK4-NEXT: ret void987//988//989// CHECK4-LABEL: define {{[^@]+}}@main990// CHECK4-SAME: () #[[ATTR3:[0-9]+]] {991// CHECK4-NEXT: entry:992// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4993// CHECK4-NEXT: [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, i32 }>, align 8994// CHECK4-NEXT: store i32 0, ptr [[RETVAL]], align 4995// CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 0996// CHECK4-NEXT: store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 8997// CHECK4-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 1998// CHECK4-NEXT: store i32 1073741824, ptr [[BLOCK_FLAGS]], align 8999// CHECK4-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 21000// CHECK4-NEXT: store i32 0, ptr [[BLOCK_RESERVED]], align 41001// CHECK4-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 31002// CHECK4-NEXT: store ptr @__main_block_invoke, ptr [[BLOCK_INVOKE]], align 81003// CHECK4-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 41004// CHECK4-NEXT: store ptr @__block_descriptor_tmp.3, ptr [[BLOCK_DESCRIPTOR]], align 81005// CHECK4-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 51006// CHECK4-NEXT: [[TMP0:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 41007// CHECK4-NEXT: store i32 [[TMP0]], ptr [[BLOCK_CAPTURED]], align 81008// CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 31009// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 81010// CHECK4-NEXT: call void [[TMP2]](ptr noundef [[BLOCK]])1011// CHECK4-NEXT: ret i32 01012//1013//1014// CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke1015// CHECK4-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR4:[0-9]+]] {1016// CHECK4-NEXT: entry:1017// CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 81018// CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 81019// CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 81020// CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 81021// CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3:[0-9]+]], i32 1, ptr @__main_block_invoke.omp_outlined, ptr @_ZZ4mainE5sivar)1022// CHECK4-NEXT: ret void1023//1024//1025// CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke.omp_outlined1026// CHECK4-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] {1027// CHECK4-NEXT: entry:1028// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81029// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81030// CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 81031// CHECK4-NEXT: [[TMP:%.*]] = alloca ptr, align 81032// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41033// CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 41034// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 41035// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 41036// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41037// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41038// CHECK4-NEXT: [[G:%.*]] = alloca i32, align 41039// CHECK4-NEXT: [[G1:%.*]] = alloca i32, align 41040// CHECK4-NEXT: [[_TMP2:%.*]] = alloca ptr, align 81041// CHECK4-NEXT: [[SIVAR3:%.*]] = alloca i32, align 41042// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 41043// CHECK4-NEXT: [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, ptr, i32, i32 }>, align 81044// CHECK4-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81045// CHECK4-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81046// CHECK4-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 81047// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]]1048// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr @g1, align 8, !nonnull [[META3]], !align [[META4]]1049// CHECK4-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 81050// CHECK4-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 41051// CHECK4-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 41052// CHECK4-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 41053// CHECK4-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41054// CHECK4-NEXT: [[TMP2:%.*]] = load volatile i32, ptr @g, align 41055// CHECK4-NEXT: store i32 [[TMP2]], ptr [[G]], align 41056// CHECK4-NEXT: [[TMP3:%.*]] = load volatile i32, ptr @g, align 41057// CHECK4-NEXT: store i32 [[TMP3]], ptr [[G1]], align 41058// CHECK4-NEXT: store ptr [[G1]], ptr [[_TMP2]], align 81059// CHECK4-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP0]], align 41060// CHECK4-NEXT: store i32 [[TMP4]], ptr [[SIVAR3]], align 41061// CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81062// CHECK4-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 41063// CHECK4-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1064// CHECK4-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41065// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 11066// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1067// CHECK4: cond.true:1068// CHECK4-NEXT: br label [[COND_END:%.*]]1069// CHECK4: cond.false:1070// CHECK4-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41071// CHECK4-NEXT: br label [[COND_END]]1072// CHECK4: cond.end:1073// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]1074// CHECK4-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 41075// CHECK4-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41076// CHECK4-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 41077// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1078// CHECK4: omp.inner.for.cond:1079// CHECK4-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41080// CHECK4-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41081// CHECK4-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]1082// CHECK4-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1083// CHECK4: omp.inner.for.body:1084// CHECK4-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41085// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 11086// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]1087// CHECK4-NEXT: store i32 [[ADD]], ptr [[I]], align 41088// CHECK4-NEXT: store i32 1, ptr [[G]], align 41089// CHECK4-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META3]], !align [[META4]]1090// CHECK4-NEXT: store volatile i32 1, ptr [[TMP13]], align 41091// CHECK4-NEXT: store i32 2, ptr [[SIVAR3]], align 41092// CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 01093// CHECK4-NEXT: store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 81094// CHECK4-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 11095// CHECK4-NEXT: store i32 1073741824, ptr [[BLOCK_FLAGS]], align 81096// CHECK4-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 21097// CHECK4-NEXT: store i32 0, ptr [[BLOCK_RESERVED]], align 41098// CHECK4-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 31099// CHECK4-NEXT: store ptr @var_block_invoke, ptr [[BLOCK_INVOKE]], align 81100// CHECK4-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 41101// CHECK4-NEXT: store ptr @__block_descriptor_tmp, ptr [[BLOCK_DESCRIPTOR]], align 81102// CHECK4-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 61103// CHECK4-NEXT: [[TMP14:%.*]] = load volatile i32, ptr [[G]], align 41104// CHECK4-NEXT: store volatile i32 [[TMP14]], ptr [[BLOCK_CAPTURED]], align 81105// CHECK4-NEXT: [[BLOCK_CAPTURED5:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 51106// CHECK4-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META3]], !align [[META4]]1107// CHECK4-NEXT: store ptr [[TMP15]], ptr [[BLOCK_CAPTURED5]], align 81108// CHECK4-NEXT: [[BLOCK_CAPTURED6:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 71109// CHECK4-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR3]], align 41110// CHECK4-NEXT: store i32 [[TMP16]], ptr [[BLOCK_CAPTURED6]], align 41111// CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 31112// CHECK4-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 81113// CHECK4-NEXT: call void [[TMP18]](ptr noundef [[BLOCK]])1114// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1115// CHECK4: omp.body.continue:1116// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1117// CHECK4: omp.inner.for.inc:1118// CHECK4-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41119// CHECK4-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 11120// CHECK4-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 41121// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]]1122// CHECK4: omp.inner.for.end:1123// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]1124// CHECK4: omp.loop.exit:1125// CHECK4-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP6]])1126// CHECK4-NEXT: call void @__kmpc_barrier(ptr @[[GLOB2:[0-9]+]], i32 [[TMP6]])1127// CHECK4-NEXT: ret void1128//1129//1130// CHECK4-LABEL: define {{[^@]+}}@var_block_invoke1131// CHECK4-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR4]] {1132// CHECK4-NEXT: entry:1133// CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 81134// CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 81135// CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 81136// CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 81137// CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, i32, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 61138// CHECK4-NEXT: store i32 2, ptr [[BLOCK_CAPTURE_ADDR]], align 81139// CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, i32, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 51140// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR1]], align 8, !nonnull [[META3]], !align [[META4]]1141// CHECK4-NEXT: store i32 2, ptr [[TMP0]], align 41142// CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, i32, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 71143// CHECK4-NEXT: store i32 4, ptr [[BLOCK_CAPTURE_ADDR2]], align 41144// CHECK4-NEXT: ret void1145//1146//1147// CHECK4-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_for_firstprivate_codegen.cpp1148// CHECK4-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {1149// CHECK4-NEXT: entry:1150// CHECK4-NEXT: call void @__cxx_global_var_init()1151// CHECK4-NEXT: call void @__cxx_global_var_init.1()1152// CHECK4-NEXT: call void @__cxx_global_var_init.2()1153// CHECK4-NEXT: ret void1154//1155