740 lines · cpp
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _2// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s4// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK36// RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK47 8// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"9// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s10// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"11// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"12// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"13// expected-no-diagnostics14#ifndef HEADER15#define HEADER16 17template <class T>18struct S {19 T f;20 S(T a) : f(a) {}21 S() : f() {}22 operator T() { return T(); }23 ~S() {}24};25 26volatile double g;27volatile double &g1 = g;28 29template <typename T>30T tmain() {31 S<T> test;32 T t_var = T();33 T vec[] = {1, 2};34 S<T> s_arr[] = {1, 2};35 S<T> &var = test;36#pragma omp parallel37#pragma omp for private(t_var, vec, s_arr, s_arr, var, var)38 for (int i = 0; i < 2; ++i) {39 vec[i] = t_var;40 s_arr[i] = var;41 }42 return T();43}44 45int main() {46 static int svar;47#ifdef LAMBDA48 [&]() {49 static float sfvar;50#pragma omp parallel51#pragma omp for private(g, g1, svar, sfvar)52 for (int i = 0; i < 2; ++i) {53 g = 1;54 g1 = 1;55 svar = 3;56 sfvar = 4.0;57 [&]() {58 g = 2;59 g1 = 2;60 svar = 4;61 sfvar = 8.0;62 }();63 }64 }();65 return 0;66#elif defined(BLOCKS)67 ^{68 static float sfvar;69#pragma omp parallel70#pragma omp for private(g, g1, svar, sfvar)71 for (int i = 0; i < 2; ++i) {72 g = 1;73 g1 = 1;74 svar = 2;75 sfvar = 3.0;76 ^{77 g = 2;78 g1 = 2;79 svar = 4;80 sfvar = 9.0;81 }();82 }83 }();84 return 0;85#else86 S<float> test;87 int t_var = 0;88 int vec[] = {1, 2};89 S<float> s_arr[] = {1, 2};90 S<float> &var = test;91#pragma omp parallel92#pragma omp for private(t_var, vec, s_arr, s_arr, var, var, svar)93 for (int i = 0; i < 2; ++i) {94 vec[i] = t_var;95 s_arr[i] = var;96 }97 int i;98#pragma omp parallel99#pragma omp for private(i)100 for (i = 0; i < 2; ++i) {101 ;102 }103 return tmain<int>();104#endif105}106 107 108#endif109 110// CHECK1-LABEL: define {{[^@]+}}@main111// CHECK1-SAME: () #[[ATTR0:[0-9]+]] {112// CHECK1-NEXT: entry:113// CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4114// CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4115// CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4116// CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4117// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4118// CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8119// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4120// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4121// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])122// CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4123// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i64 8, i1 false)124// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], float noundef 1.000000e+00)125// CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i64 1126// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00)127// CHECK1-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8128// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3:[0-9]+]], i32 0, ptr @main.omp_outlined)129// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 0, ptr @main.omp_outlined.1)130// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()131// CHECK1-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4132// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0133// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2134// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]135// CHECK1: arraydestroy.body:136// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP0]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]137// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1138// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]]139// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]140// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]141// CHECK1: arraydestroy.done1:142// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]143// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4144// CHECK1-NEXT: ret i32 [[TMP1]]145//146//147// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev148// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {149// CHECK1-NEXT: entry:150// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8151// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8152// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8153// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])154// CHECK1-NEXT: ret void155//156//157// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef158// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {159// CHECK1-NEXT: entry:160// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8161// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4162// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8163// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4164// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8165// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4166// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])167// CHECK1-NEXT: ret void168//169//170// CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined171// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {172// CHECK1-NEXT: entry:173// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8174// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8175// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4176// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4177// CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8178// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4179// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4180// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4181// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4182// CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4183// CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4184// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4185// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4186// CHECK1-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8187// CHECK1-NEXT: [[SVAR:%.*]] = alloca i32, align 4188// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4189// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8190// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8191// CHECK1-NEXT: store ptr undef, ptr [[_TMP1]], align 8192// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4193// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4194// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4195// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4196// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0197// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2198// CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]199// CHECK1: arrayctor.loop:200// CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]201// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])202// CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1203// CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]204// CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]205// CHECK1: arrayctor.cont:206// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])207// CHECK1-NEXT: store ptr [[VAR]], ptr [[_TMP2]], align 8208// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8209// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4210// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)211// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4212// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1213// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]214// CHECK1: cond.true:215// CHECK1-NEXT: br label [[COND_END:%.*]]216// CHECK1: cond.false:217// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4218// CHECK1-NEXT: br label [[COND_END]]219// CHECK1: cond.end:220// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]221// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4222// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4223// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4224// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]225// CHECK1: omp.inner.for.cond:226// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4227// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4228// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]229// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]230// CHECK1: omp.inner.for.cond.cleanup:231// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]232// CHECK1: omp.inner.for.body:233// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4234// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1235// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]236// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4237// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4238// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4239// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64240// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]]241// CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4242// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8243// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4244// CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64245// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]]246// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false)247// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]248// CHECK1: omp.body.continue:249// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]250// CHECK1: omp.inner.for.inc:251// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4252// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1253// CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4254// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]255// CHECK1: omp.inner.for.end:256// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]257// CHECK1: omp.loop.exit:258// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8259// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4260// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]])261// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]]262// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0263// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 2264// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]265// CHECK1: arraydestroy.body:266// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]267// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1268// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]269// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]270// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]271// CHECK1: arraydestroy.done8:272// CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8273// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4274// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB2:[0-9]+]], i32 [[TMP17]])275// CHECK1-NEXT: ret void276//277//278// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev279// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {280// CHECK1-NEXT: entry:281// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8282// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8283// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8284// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]285// CHECK1-NEXT: ret void286//287//288// CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.1289// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {290// CHECK1-NEXT: entry:291// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8292// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8293// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4294// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4295// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4296// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4297// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4298// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4299// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4300// CHECK1-NEXT: [[I1:%.*]] = alloca i32, align 4301// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8302// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8303// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4304// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4305// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4306// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4307// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8308// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4309// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)310// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4311// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1312// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]313// CHECK1: cond.true:314// CHECK1-NEXT: br label [[COND_END:%.*]]315// CHECK1: cond.false:316// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4317// CHECK1-NEXT: br label [[COND_END]]318// CHECK1: cond.end:319// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]320// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4321// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4322// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4323// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]324// CHECK1: omp.inner.for.cond:325// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4326// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4327// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]328// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]329// CHECK1: omp.inner.for.body:330// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4331// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1332// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]333// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4334// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]335// CHECK1: omp.body.continue:336// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]337// CHECK1: omp.inner.for.inc:338// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4339// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1340// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4341// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]342// CHECK1: omp.inner.for.end:343// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]344// CHECK1: omp.loop.exit:345// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])346// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB2]], i32 [[TMP1]])347// CHECK1-NEXT: ret void348//349//350// CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v351// CHECK1-SAME: () #[[ATTR1]] comdat {352// CHECK1-NEXT: entry:353// CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4354// CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4355// CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4356// CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4357// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4358// CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8359// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])360// CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4361// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)362// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1)363// CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1364// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)365// CHECK1-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8366// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 0, ptr @_Z5tmainIiET_v.omp_outlined)367// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4368// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0369// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2370// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]371// CHECK1: arraydestroy.body:372// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP0]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]373// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1374// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]375// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]376// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]377// CHECK1: arraydestroy.done1:378// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]379// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4380// CHECK1-NEXT: ret i32 [[TMP1]]381//382//383// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev384// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {385// CHECK1-NEXT: entry:386// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8387// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8388// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8389// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0390// CHECK1-NEXT: store float 0.000000e+00, ptr [[F]], align 4391// CHECK1-NEXT: ret void392//393//394// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef395// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {396// CHECK1-NEXT: entry:397// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8398// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4399// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8400// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4401// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8402// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0403// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4404// CHECK1-NEXT: store float [[TMP0]], ptr [[F]], align 4405// CHECK1-NEXT: ret void406//407//408// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev409// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {410// CHECK1-NEXT: entry:411// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8412// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8413// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8414// CHECK1-NEXT: ret void415//416//417// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev418// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {419// CHECK1-NEXT: entry:420// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8421// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8422// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8423// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])424// CHECK1-NEXT: ret void425//426//427// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei428// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {429// CHECK1-NEXT: entry:430// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8431// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4432// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8433// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4434// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8435// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4436// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])437// CHECK1-NEXT: ret void438//439//440// CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v.omp_outlined441// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {442// CHECK1-NEXT: entry:443// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8444// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8445// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4446// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4447// CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8448// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4449// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4450// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4451// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4452// CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4453// CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4454// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4455// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4456// CHECK1-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8457// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4458// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8459// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8460// CHECK1-NEXT: store ptr undef, ptr [[_TMP1]], align 8461// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4462// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4463// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4464// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4465// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0466// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2467// CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]468// CHECK1: arrayctor.loop:469// CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]470// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])471// CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1472// CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]473// CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]474// CHECK1: arrayctor.cont:475// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])476// CHECK1-NEXT: store ptr [[VAR]], ptr [[_TMP2]], align 8477// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8478// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4479// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)480// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4481// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1482// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]483// CHECK1: cond.true:484// CHECK1-NEXT: br label [[COND_END:%.*]]485// CHECK1: cond.false:486// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4487// CHECK1-NEXT: br label [[COND_END]]488// CHECK1: cond.end:489// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]490// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4491// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4492// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4493// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]494// CHECK1: omp.inner.for.cond:495// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4496// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4497// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]498// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]499// CHECK1: omp.inner.for.cond.cleanup:500// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]501// CHECK1: omp.inner.for.body:502// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4503// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1504// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]505// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4506// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4507// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4508// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64509// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]]510// CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4511// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8512// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4513// CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64514// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]]515// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false)516// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]517// CHECK1: omp.body.continue:518// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]519// CHECK1: omp.inner.for.inc:520// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4521// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1522// CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4523// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]524// CHECK1: omp.inner.for.end:525// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]526// CHECK1: omp.loop.exit:527// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8528// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4529// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]])530// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]]531// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0532// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i64 2533// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]534// CHECK1: arraydestroy.body:535// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]536// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1537// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]538// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]539// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]540// CHECK1: arraydestroy.done8:541// CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8542// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4543// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB2]], i32 [[TMP17]])544// CHECK1-NEXT: ret void545//546//547// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev548// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {549// CHECK1-NEXT: entry:550// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8551// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8552// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8553// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]554// CHECK1-NEXT: ret void555//556//557// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev558// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {559// CHECK1-NEXT: entry:560// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8561// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8562// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8563// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0564// CHECK1-NEXT: store i32 0, ptr [[F]], align 4565// CHECK1-NEXT: ret void566//567//568// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei569// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {570// CHECK1-NEXT: entry:571// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8572// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4573// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8574// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4575// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8576// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0577// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4578// CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4579// CHECK1-NEXT: ret void580//581//582// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev583// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {584// CHECK1-NEXT: entry:585// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8586// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8587// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8588// CHECK1-NEXT: ret void589//590//591// CHECK3-LABEL: define {{[^@]+}}@main592// CHECK3-SAME: () #[[ATTR0:[0-9]+]] {593// CHECK3-NEXT: entry:594// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4595// CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1596// CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4597// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])598// CHECK3-NEXT: ret i32 0599//600//601// CHECK4-LABEL: define {{[^@]+}}@main602// CHECK4-SAME: () #[[ATTR1:[0-9]+]] {603// CHECK4-NEXT: entry:604// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4605// CHECK4-NEXT: store i32 0, ptr [[RETVAL]], align 4606// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr getelementptr inbounds nuw ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr @__block_literal_global, i32 0, i32 3), align 8607// CHECK4-NEXT: call void [[TMP0]](ptr noundef @__block_literal_global)608// CHECK4-NEXT: ret i32 0609//610//611// CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke612// CHECK4-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] {613// CHECK4-NEXT: entry:614// CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8615// CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8616// CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8617// CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8618// CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3:[0-9]+]], i32 0, ptr @__main_block_invoke.omp_outlined)619// CHECK4-NEXT: ret void620//621//622// CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke.omp_outlined623// CHECK4-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {624// CHECK4-NEXT: entry:625// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8626// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8627// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4628// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4629// CHECK4-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8630// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4631// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4632// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4633// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4634// CHECK4-NEXT: [[G:%.*]] = alloca double, align 8635// CHECK4-NEXT: [[G1:%.*]] = alloca double, align 8636// CHECK4-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8637// CHECK4-NEXT: [[SVAR:%.*]] = alloca i32, align 4638// CHECK4-NEXT: [[SFVAR:%.*]] = alloca float, align 4639// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4640// CHECK4-NEXT: [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, double, ptr, i32, float }>, align 8641// CHECK4-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8642// CHECK4-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8643// CHECK4-NEXT: store ptr undef, ptr [[_TMP1]], align 8644// CHECK4-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4645// CHECK4-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4646// CHECK4-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4647// CHECK4-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4648// CHECK4-NEXT: store ptr [[G1]], ptr [[_TMP2]], align 8649// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8650// CHECK4-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4651// CHECK4-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)652// CHECK4-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4653// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1654// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]655// CHECK4: cond.true:656// CHECK4-NEXT: br label [[COND_END:%.*]]657// CHECK4: cond.false:658// CHECK4-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4659// CHECK4-NEXT: br label [[COND_END]]660// CHECK4: cond.end:661// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]662// CHECK4-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4663// CHECK4-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4664// CHECK4-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4665// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]666// CHECK4: omp.inner.for.cond:667// CHECK4-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4668// CHECK4-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4669// CHECK4-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]670// CHECK4-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]671// CHECK4: omp.inner.for.body:672// CHECK4-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4673// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1674// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]675// CHECK4-NEXT: store i32 [[ADD]], ptr [[I]], align 4676// CHECK4-NEXT: store double 1.000000e+00, ptr [[G]], align 8677// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8678// CHECK4-NEXT: store volatile double 1.000000e+00, ptr [[TMP8]], align 8679// CHECK4-NEXT: store i32 2, ptr [[SVAR]], align 4680// CHECK4-NEXT: store float 3.000000e+00, ptr [[SFVAR]], align 4681// CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, ptr, i32, float }>, ptr [[BLOCK]], i32 0, i32 0682// CHECK4-NEXT: store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 8683// CHECK4-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, ptr, i32, float }>, ptr [[BLOCK]], i32 0, i32 1684// CHECK4-NEXT: store i32 1073741824, ptr [[BLOCK_FLAGS]], align 8685// CHECK4-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, ptr, i32, float }>, ptr [[BLOCK]], i32 0, i32 2686// CHECK4-NEXT: store i32 0, ptr [[BLOCK_RESERVED]], align 4687// CHECK4-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, ptr, i32, float }>, ptr [[BLOCK]], i32 0, i32 3688// CHECK4-NEXT: store ptr @g1_block_invoke_2, ptr [[BLOCK_INVOKE]], align 8689// CHECK4-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, ptr, i32, float }>, ptr [[BLOCK]], i32 0, i32 4690// CHECK4-NEXT: store ptr @__block_descriptor_tmp.1, ptr [[BLOCK_DESCRIPTOR]], align 8691// CHECK4-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, ptr, i32, float }>, ptr [[BLOCK]], i32 0, i32 5692// CHECK4-NEXT: [[TMP9:%.*]] = load volatile double, ptr [[G]], align 8693// CHECK4-NEXT: store volatile double [[TMP9]], ptr [[BLOCK_CAPTURED]], align 8694// CHECK4-NEXT: [[BLOCK_CAPTURED4:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, ptr, i32, float }>, ptr [[BLOCK]], i32 0, i32 6695// CHECK4-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8696// CHECK4-NEXT: store ptr [[TMP10]], ptr [[BLOCK_CAPTURED4]], align 8697// CHECK4-NEXT: [[BLOCK_CAPTURED5:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, ptr, i32, float }>, ptr [[BLOCK]], i32 0, i32 7698// CHECK4-NEXT: [[TMP11:%.*]] = load i32, ptr [[SVAR]], align 4699// CHECK4-NEXT: store i32 [[TMP11]], ptr [[BLOCK_CAPTURED5]], align 8700// CHECK4-NEXT: [[BLOCK_CAPTURED6:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, ptr, i32, float }>, ptr [[BLOCK]], i32 0, i32 8701// CHECK4-NEXT: [[TMP12:%.*]] = load float, ptr [[SFVAR]], align 4702// CHECK4-NEXT: store float [[TMP12]], ptr [[BLOCK_CAPTURED6]], align 4703// CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3704// CHECK4-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 8705// CHECK4-NEXT: call void [[TMP14]](ptr noundef [[BLOCK]])706// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]707// CHECK4: omp.body.continue:708// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]709// CHECK4: omp.inner.for.inc:710// CHECK4-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4711// CHECK4-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP15]], 1712// CHECK4-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4713// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]]714// CHECK4: omp.inner.for.end:715// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]716// CHECK4: omp.loop.exit:717// CHECK4-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])718// CHECK4-NEXT: call void @__kmpc_barrier(ptr @[[GLOB2:[0-9]+]], i32 [[TMP1]])719// CHECK4-NEXT: ret void720//721//722// CHECK4-LABEL: define {{[^@]+}}@g1_block_invoke_2723// CHECK4-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] {724// CHECK4-NEXT: entry:725// CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8726// CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8727// CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8728// CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8729// CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, ptr, i32, float }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 5730// CHECK4-NEXT: store double 2.000000e+00, ptr [[BLOCK_CAPTURE_ADDR]], align 8731// CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, ptr, i32, float }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 6732// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR1]], align 8733// CHECK4-NEXT: store double 2.000000e+00, ptr [[TMP0]], align 8734// CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, ptr, i32, float }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 7735// CHECK4-NEXT: store i32 4, ptr [[BLOCK_CAPTURE_ADDR2]], align 8736// CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR3:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, ptr, i32, float }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 8737// CHECK4-NEXT: store float 9.000000e+00, ptr [[BLOCK_CAPTURE_ADDR3]], align 4738// CHECK4-NEXT: ret void739//740