5325 lines · cpp
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _2 3// expected-no-diagnostics4 5// Check code generation6// RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -std=c++20 -fclang-abi-compat=latest -fopenmp -fopenmp-version=60 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 8// Check same results after serialization round-trip9// FIXME: They should be exactly the same but currently differ in function order10// RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -std=c++20 -fclang-abi-compat=latest -fopenmp -fopenmp-version=60 -emit-pch -o %t %s11// RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -std=c++20 -fclang-abi-compat=latest -fopenmp -fopenmp-version=60 -include-pch %t -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK212 13#ifndef HEADER14#define HEADER15 16// placeholder for loop body code.17extern "C" void body(...) {}18 19 20extern "C" void foo1(int start, int end, int step) {21 int i;22#pragma omp interchange permutation(1)23 for (i = start; i < end; i += step)24 body(i);25}26 27 28extern "C" void foo2(int start1, int start2, int end1, int end2, int step1, int step2) {29#pragma omp interchange30 for (int i = start1; i < end1; i += step1)31 for (int j = start2; j < end2; j += step2)32 body(i, j);33}34 35 36extern "C" void foo3() {37#pragma omp for38#pragma omp interchange39 for (int i = 7; i < 17; i += 3)40 for (int j = 7; j < 17; j += 3)41 body(i, j);42}43 44 45extern "C" void foo4() {46#pragma omp for collapse(2)47 for (int k = 7; k < 17; k += 3)48#pragma omp interchange49 for (int i = 7; i < 17; i += 3)50 for (int j = 7; j < 17; j += 3)51 body(i, j);52}53 54 55extern "C" void foo5() {56#pragma omp for collapse(3)57 for (int i = 7; i < 17; i += 3)58#pragma omp interchange permutation(1)59 for (int j = 7; j < 17; j += 3)60 for (int k = 7; k < 17; k += 3)61 body(i, j, k);62}63 64 65extern "C" void foo6() {66#pragma omp for collapse(4)67 for (int i = 7; i < 17; i += 3)68#pragma omp interchange69 for (int j = 7; j < 17; j += 3)70 for (int k = 7; k < 17; k += 3)71 for (int l = 7; l < 17; l += 3)72 body(i, j, k, l);73}74 75 76extern "C" void foo7() {77#pragma omp interchange permutation(2,3,4,1)78 for (int i = 7; i < 17; i += 3)79 for (int j = 7; j < 17; j += 3)80 for (int k = 7; k < 17; k += 3)81 for (int l = 7; l < 17; l += 3)82 body(i, j, k, l);83}84 85 86template<int TILESIZE>87void foo8(int start, int end, int step) {88 #pragma omp for collapse(4)89 for (int i = start; i < end; i += step)90 #pragma omp interchange permutation(1)91 for (int j = start; j < end; j += step)92 #pragma omp tile sizes(TILESIZE)93 for (int k = start; k < end; k += step)94 body(i, j, k);95}96 97// Also test instantiating the template.98extern "C" void tfoo8() {99 foo8<32>(0, 42, 1);100 foo8<64>(0, 42, 3);101}102 103 104extern "C" void foo9() {105 double arr[128];106 #pragma omp interchange107 for (double c = 42; auto && v : arr)108 for (int i = 0; i < 42; i += 2)109 body(c, v, i);110}111 112 113extern "C" void foo10() {114 double A[128], B[16];115 #pragma omp for collapse(4)116 for (int i = 0; i < 128; ++i)117 #pragma omp interchange118 for (double c = 42; auto aa : A)119 for (double d = 42; auto &bb : B)120 for (int j = 0; j < 128; ++j)121 body(i, c, aa, d, bb, j);122}123 124#endif /* HEADER */125 126// CHECK1-LABEL: define {{[^@]+}}@body127// CHECK1-SAME: (...) #[[ATTR0:[0-9]+]] {128// CHECK1-NEXT: entry:129// CHECK1-NEXT: ret void130//131//132// CHECK1-LABEL: define {{[^@]+}}@foo1133// CHECK1-SAME: (i32 noundef [[START:%.*]], i32 noundef [[END:%.*]], i32 noundef [[STEP:%.*]]) #[[ATTR0]] {134// CHECK1-NEXT: entry:135// CHECK1-NEXT: [[START_ADDR:%.*]] = alloca i32, align 4136// CHECK1-NEXT: [[END_ADDR:%.*]] = alloca i32, align 4137// CHECK1-NEXT: [[STEP_ADDR:%.*]] = alloca i32, align 4138// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4139// CHECK1-NEXT: store i32 [[START]], ptr [[START_ADDR]], align 4140// CHECK1-NEXT: store i32 [[END]], ptr [[END_ADDR]], align 4141// CHECK1-NEXT: store i32 [[STEP]], ptr [[STEP_ADDR]], align 4142// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[START_ADDR]], align 4143// CHECK1-NEXT: store i32 [[TMP0]], ptr [[I]], align 4144// CHECK1-NEXT: br label [[FOR_COND:%.*]]145// CHECK1: for.cond:146// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[I]], align 4147// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[END_ADDR]], align 4148// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]]149// CHECK1-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]150// CHECK1: for.body:151// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[I]], align 4152// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP3]])153// CHECK1-NEXT: br label [[FOR_INC:%.*]]154// CHECK1: for.inc:155// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[STEP_ADDR]], align 4156// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4157// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], [[TMP4]]158// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4159// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]160// CHECK1: for.end:161// CHECK1-NEXT: ret void162//163//164// CHECK1-LABEL: define {{[^@]+}}@foo2165// CHECK1-SAME: (i32 noundef [[START1:%.*]], i32 noundef [[START2:%.*]], i32 noundef [[END1:%.*]], i32 noundef [[END2:%.*]], i32 noundef [[STEP1:%.*]], i32 noundef [[STEP2:%.*]]) #[[ATTR0]] {166// CHECK1-NEXT: entry:167// CHECK1-NEXT: [[START1_ADDR:%.*]] = alloca i32, align 4168// CHECK1-NEXT: [[START2_ADDR:%.*]] = alloca i32, align 4169// CHECK1-NEXT: [[END1_ADDR:%.*]] = alloca i32, align 4170// CHECK1-NEXT: [[END2_ADDR:%.*]] = alloca i32, align 4171// CHECK1-NEXT: [[STEP1_ADDR:%.*]] = alloca i32, align 4172// CHECK1-NEXT: [[STEP2_ADDR:%.*]] = alloca i32, align 4173// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4174// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4175// CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4176// CHECK1-NEXT: [[DOTNEW_STEP:%.*]] = alloca i32, align 4177// CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4178// CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4179// CHECK1-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4180// CHECK1-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i32, align 4181// CHECK1-NEXT: [[DOTNEW_STEP7:%.*]] = alloca i32, align 4182// CHECK1-NEXT: [[DOTCAPTURE_EXPR_8:%.*]] = alloca i32, align 4183// CHECK1-NEXT: [[DOTPERMUTED_0_IV_J:%.*]] = alloca i32, align 4184// CHECK1-NEXT: [[DOTPERMUTED_1_IV_I:%.*]] = alloca i32, align 4185// CHECK1-NEXT: store i32 [[START1]], ptr [[START1_ADDR]], align 4186// CHECK1-NEXT: store i32 [[START2]], ptr [[START2_ADDR]], align 4187// CHECK1-NEXT: store i32 [[END1]], ptr [[END1_ADDR]], align 4188// CHECK1-NEXT: store i32 [[END2]], ptr [[END2_ADDR]], align 4189// CHECK1-NEXT: store i32 [[STEP1]], ptr [[STEP1_ADDR]], align 4190// CHECK1-NEXT: store i32 [[STEP2]], ptr [[STEP2_ADDR]], align 4191// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[START1_ADDR]], align 4192// CHECK1-NEXT: store i32 [[TMP0]], ptr [[I]], align 4193// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[START1_ADDR]], align 4194// CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4195// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[END1_ADDR]], align 4196// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_1]], align 4197// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[STEP1_ADDR]], align 4198// CHECK1-NEXT: store i32 [[TMP3]], ptr [[DOTNEW_STEP]], align 4199// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4200// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4201// CHECK1-NEXT: [[SUB:%.*]] = sub i32 [[TMP4]], [[TMP5]]202// CHECK1-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1203// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4204// CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], [[TMP6]]205// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4206// CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], [[TMP7]]207// CHECK1-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1208// CHECK1-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4209// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[START2_ADDR]], align 4210// CHECK1-NEXT: store i32 [[TMP8]], ptr [[J]], align 4211// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[START2_ADDR]], align 4212// CHECK1-NEXT: store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR_5]], align 4213// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[END2_ADDR]], align 4214// CHECK1-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR_6]], align 4215// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[STEP2_ADDR]], align 4216// CHECK1-NEXT: store i32 [[TMP11]], ptr [[DOTNEW_STEP7]], align 4217// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4218// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4219// CHECK1-NEXT: [[SUB9:%.*]] = sub i32 [[TMP12]], [[TMP13]]220// CHECK1-NEXT: [[SUB10:%.*]] = sub i32 [[SUB9]], 1221// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4222// CHECK1-NEXT: [[ADD11:%.*]] = add i32 [[SUB10]], [[TMP14]]223// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4224// CHECK1-NEXT: [[DIV12:%.*]] = udiv i32 [[ADD11]], [[TMP15]]225// CHECK1-NEXT: [[SUB13:%.*]] = sub i32 [[DIV12]], 1226// CHECK1-NEXT: store i32 [[SUB13]], ptr [[DOTCAPTURE_EXPR_8]], align 4227// CHECK1-NEXT: store i32 0, ptr [[DOTPERMUTED_0_IV_J]], align 4228// CHECK1-NEXT: br label [[FOR_COND:%.*]]229// CHECK1: for.cond:230// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4231// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_8]], align 4232// CHECK1-NEXT: [[ADD14:%.*]] = add i32 [[TMP17]], 1233// CHECK1-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP16]], [[ADD14]]234// CHECK1-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END24:%.*]]235// CHECK1: for.body:236// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4237// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4238// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4239// CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], [[TMP20]]240// CHECK1-NEXT: [[ADD15:%.*]] = add i32 [[TMP18]], [[MUL]]241// CHECK1-NEXT: store i32 [[ADD15]], ptr [[J]], align 4242// CHECK1-NEXT: store i32 0, ptr [[DOTPERMUTED_1_IV_I]], align 4243// CHECK1-NEXT: br label [[FOR_COND16:%.*]]244// CHECK1: for.cond16:245// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4246// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4247// CHECK1-NEXT: [[ADD17:%.*]] = add i32 [[TMP22]], 1248// CHECK1-NEXT: [[CMP18:%.*]] = icmp ult i32 [[TMP21]], [[ADD17]]249// CHECK1-NEXT: br i1 [[CMP18]], label [[FOR_BODY19:%.*]], label [[FOR_END:%.*]]250// CHECK1: for.body19:251// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4252// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4253// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4254// CHECK1-NEXT: [[MUL20:%.*]] = mul i32 [[TMP24]], [[TMP25]]255// CHECK1-NEXT: [[ADD21:%.*]] = add i32 [[TMP23]], [[MUL20]]256// CHECK1-NEXT: store i32 [[ADD21]], ptr [[I]], align 4257// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[I]], align 4258// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[J]], align 4259// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP26]], i32 noundef [[TMP27]])260// CHECK1-NEXT: br label [[FOR_INC:%.*]]261// CHECK1: for.inc:262// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4263// CHECK1-NEXT: [[INC:%.*]] = add i32 [[TMP28]], 1264// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTPERMUTED_1_IV_I]], align 4265// CHECK1-NEXT: br label [[FOR_COND16]], !llvm.loop [[LOOP5:![0-9]+]]266// CHECK1: for.end:267// CHECK1-NEXT: br label [[FOR_INC22:%.*]]268// CHECK1: for.inc22:269// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4270// CHECK1-NEXT: [[INC23:%.*]] = add i32 [[TMP29]], 1271// CHECK1-NEXT: store i32 [[INC23]], ptr [[DOTPERMUTED_0_IV_J]], align 4272// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]273// CHECK1: for.end24:274// CHECK1-NEXT: ret void275//276//277// CHECK1-LABEL: define {{[^@]+}}@foo3278// CHECK1-SAME: () #[[ATTR0]] {279// CHECK1-NEXT: entry:280// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4281// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4282// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4283// CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4284// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4285// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4286// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4287// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4288// CHECK1-NEXT: [[DOTPERMUTED_0_IV_J:%.*]] = alloca i32, align 4289// CHECK1-NEXT: [[DOTPERMUTED_1_IV_I:%.*]] = alloca i32, align 4290// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])291// CHECK1-NEXT: store i32 7, ptr [[I]], align 4292// CHECK1-NEXT: store i32 7, ptr [[J]], align 4293// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4294// CHECK1-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 4295// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4296// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4297// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)298// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4299// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 3300// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]301// CHECK1: cond.true:302// CHECK1-NEXT: br label [[COND_END:%.*]]303// CHECK1: cond.false:304// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4305// CHECK1-NEXT: br label [[COND_END]]306// CHECK1: cond.end:307// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ]308// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4309// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4310// CHECK1-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4311// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]312// CHECK1: omp.inner.for.cond:313// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4314// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4315// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]316// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]317// CHECK1: omp.inner.for.body:318// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4319// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1320// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]321// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTPERMUTED_0_IV_J]], align 4322// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4323// CHECK1-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP7]], 3324// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 7, [[MUL2]]325// CHECK1-NEXT: store i32 [[ADD3]], ptr [[J]], align 4326// CHECK1-NEXT: store i32 0, ptr [[DOTPERMUTED_1_IV_I]], align 4327// CHECK1-NEXT: br label [[FOR_COND:%.*]]328// CHECK1: for.cond:329// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4330// CHECK1-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP8]], 4331// CHECK1-NEXT: br i1 [[CMP4]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]332// CHECK1: for.body:333// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4334// CHECK1-NEXT: [[MUL5:%.*]] = mul nsw i32 [[TMP9]], 3335// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 7, [[MUL5]]336// CHECK1-NEXT: store i32 [[ADD6]], ptr [[I]], align 4337// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4338// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[J]], align 4339// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP10]], i32 noundef [[TMP11]])340// CHECK1-NEXT: br label [[FOR_INC:%.*]]341// CHECK1: for.inc:342// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4343// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1344// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTPERMUTED_1_IV_I]], align 4345// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]346// CHECK1: for.end:347// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]348// CHECK1: omp.body.continue:349// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]350// CHECK1: omp.inner.for.inc:351// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4352// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP13]], 1353// CHECK1-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4354// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]355// CHECK1: omp.inner.for.end:356// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]357// CHECK1: omp.loop.exit:358// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]])359// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP0]])360// CHECK1-NEXT: ret void361//362//363// CHECK1-LABEL: define {{[^@]+}}@foo4364// CHECK1-SAME: () #[[ATTR0]] {365// CHECK1-NEXT: entry:366// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4367// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4368// CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4369// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4370// CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4371// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4372// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4373// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4374// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4375// CHECK1-NEXT: [[K:%.*]] = alloca i32, align 4376// CHECK1-NEXT: [[DOTPERMUTED_0_IV_J:%.*]] = alloca i32, align 4377// CHECK1-NEXT: [[DOTPERMUTED_1_IV_I:%.*]] = alloca i32, align 4378// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])379// CHECK1-NEXT: store i32 7, ptr [[I]], align 4380// CHECK1-NEXT: store i32 7, ptr [[J]], align 4381// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4382// CHECK1-NEXT: store i32 15, ptr [[DOTOMP_UB]], align 4383// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4384// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4385// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)386// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4387// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 15388// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]389// CHECK1: cond.true:390// CHECK1-NEXT: br label [[COND_END:%.*]]391// CHECK1: cond.false:392// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4393// CHECK1-NEXT: br label [[COND_END]]394// CHECK1: cond.end:395// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 15, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ]396// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4397// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4398// CHECK1-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4399// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]400// CHECK1: omp.inner.for.cond:401// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4402// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4403// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]404// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]405// CHECK1: omp.inner.for.body:406// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4407// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP6]], 4408// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 3409// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 7, [[MUL]]410// CHECK1-NEXT: store i32 [[ADD]], ptr [[K]], align 4411// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4412// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4413// CHECK1-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP8]], 4414// CHECK1-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 4415// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], [[MUL4]]416// CHECK1-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1417// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]418// CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTPERMUTED_0_IV_J]], align 4419// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4420// CHECK1-NEXT: [[MUL7:%.*]] = mul nsw i32 [[TMP9]], 3421// CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 7, [[MUL7]]422// CHECK1-NEXT: store i32 [[ADD8]], ptr [[J]], align 4423// CHECK1-NEXT: store i32 0, ptr [[DOTPERMUTED_1_IV_I]], align 4424// CHECK1-NEXT: br label [[FOR_COND:%.*]]425// CHECK1: for.cond:426// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4427// CHECK1-NEXT: [[CMP9:%.*]] = icmp slt i32 [[TMP10]], 4428// CHECK1-NEXT: br i1 [[CMP9]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]429// CHECK1: for.body:430// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4431// CHECK1-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP11]], 3432// CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 7, [[MUL10]]433// CHECK1-NEXT: store i32 [[ADD11]], ptr [[I]], align 4434// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4435// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[J]], align 4436// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP12]], i32 noundef [[TMP13]])437// CHECK1-NEXT: br label [[FOR_INC:%.*]]438// CHECK1: for.inc:439// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4440// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1441// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTPERMUTED_1_IV_I]], align 4442// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]443// CHECK1: for.end:444// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]445// CHECK1: omp.body.continue:446// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]447// CHECK1: omp.inner.for.inc:448// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4449// CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP15]], 1450// CHECK1-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4451// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]452// CHECK1: omp.inner.for.end:453// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]454// CHECK1: omp.loop.exit:455// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]])456// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]])457// CHECK1-NEXT: ret void458//459//460// CHECK1-LABEL: define {{[^@]+}}@foo5461// CHECK1-SAME: () #[[ATTR0]] {462// CHECK1-NEXT: entry:463// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4464// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4465// CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4466// CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4467// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4468// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4469// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4470// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4471// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4472// CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4473// CHECK1-NEXT: [[K:%.*]] = alloca i32, align 4474// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])475// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4476// CHECK1-NEXT: store i32 63, ptr [[DOTOMP_UB]], align 4477// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4478// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4479// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)480// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4481// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 63482// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]483// CHECK1: cond.true:484// CHECK1-NEXT: br label [[COND_END:%.*]]485// CHECK1: cond.false:486// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4487// CHECK1-NEXT: br label [[COND_END]]488// CHECK1: cond.end:489// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 63, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ]490// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4491// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4492// CHECK1-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4493// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]494// CHECK1: omp.inner.for.cond:495// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4496// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4497// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]498// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]499// CHECK1: omp.inner.for.body:500// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4501// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP6]], 16502// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 3503// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 7, [[MUL]]504// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4505// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4506// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4507// CHECK1-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP8]], 16508// CHECK1-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 16509// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], [[MUL5]]510// CHECK1-NEXT: [[DIV6:%.*]] = sdiv i32 [[SUB]], 4511// CHECK1-NEXT: [[MUL7:%.*]] = mul nsw i32 [[DIV6]], 3512// CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 7, [[MUL7]]513// CHECK1-NEXT: store i32 [[ADD8]], ptr [[J]], align 4514// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4515// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4516// CHECK1-NEXT: [[DIV9:%.*]] = sdiv i32 [[TMP10]], 16517// CHECK1-NEXT: [[MUL10:%.*]] = mul nsw i32 [[DIV9]], 16518// CHECK1-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP9]], [[MUL10]]519// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4520// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4521// CHECK1-NEXT: [[DIV12:%.*]] = sdiv i32 [[TMP12]], 16522// CHECK1-NEXT: [[MUL13:%.*]] = mul nsw i32 [[DIV12]], 16523// CHECK1-NEXT: [[SUB14:%.*]] = sub nsw i32 [[TMP11]], [[MUL13]]524// CHECK1-NEXT: [[DIV15:%.*]] = sdiv i32 [[SUB14]], 4525// CHECK1-NEXT: [[MUL16:%.*]] = mul nsw i32 [[DIV15]], 4526// CHECK1-NEXT: [[SUB17:%.*]] = sub nsw i32 [[SUB11]], [[MUL16]]527// CHECK1-NEXT: [[MUL18:%.*]] = mul nsw i32 [[SUB17]], 3528// CHECK1-NEXT: [[ADD19:%.*]] = add nsw i32 7, [[MUL18]]529// CHECK1-NEXT: store i32 [[ADD19]], ptr [[K]], align 4530// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4531// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[J]], align 4532// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[K]], align 4533// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP13]], i32 noundef [[TMP14]], i32 noundef [[TMP15]])534// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]535// CHECK1: omp.body.continue:536// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]537// CHECK1: omp.inner.for.inc:538// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4539// CHECK1-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP16]], 1540// CHECK1-NEXT: store i32 [[ADD20]], ptr [[DOTOMP_IV]], align 4541// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]542// CHECK1: omp.inner.for.end:543// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]544// CHECK1: omp.loop.exit:545// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]])546// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]])547// CHECK1-NEXT: ret void548//549//550// CHECK1-LABEL: define {{[^@]+}}@foo6551// CHECK1-SAME: () #[[ATTR0]] {552// CHECK1-NEXT: entry:553// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4554// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4555// CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4556// CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4557// CHECK1-NEXT: [[_TMP3:%.*]] = alloca i32, align 4558// CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4559// CHECK1-NEXT: [[K:%.*]] = alloca i32, align 4560// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4561// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4562// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4563// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4564// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4565// CHECK1-NEXT: [[DOTPERMUTED_0_IV_K:%.*]] = alloca i32, align 4566// CHECK1-NEXT: [[DOTPERMUTED_1_IV_J:%.*]] = alloca i32, align 4567// CHECK1-NEXT: [[L:%.*]] = alloca i32, align 4568// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])569// CHECK1-NEXT: store i32 7, ptr [[J]], align 4570// CHECK1-NEXT: store i32 7, ptr [[K]], align 4571// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4572// CHECK1-NEXT: store i32 255, ptr [[DOTOMP_UB]], align 4573// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4574// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4575// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)576// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4577// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 255578// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]579// CHECK1: cond.true:580// CHECK1-NEXT: br label [[COND_END:%.*]]581// CHECK1: cond.false:582// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4583// CHECK1-NEXT: br label [[COND_END]]584// CHECK1: cond.end:585// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 255, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ]586// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4587// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4588// CHECK1-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4589// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]590// CHECK1: omp.inner.for.cond:591// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4592// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4593// CHECK1-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]594// CHECK1-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]595// CHECK1: omp.inner.for.body:596// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4597// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP6]], 64598// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 3599// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 7, [[MUL]]600// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4601// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4602// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4603// CHECK1-NEXT: [[DIV5:%.*]] = sdiv i32 [[TMP8]], 64604// CHECK1-NEXT: [[MUL6:%.*]] = mul nsw i32 [[DIV5]], 64605// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], [[MUL6]]606// CHECK1-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB]], 16607// CHECK1-NEXT: [[MUL8:%.*]] = mul nsw i32 [[DIV7]], 1608// CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 0, [[MUL8]]609// CHECK1-NEXT: store i32 [[ADD9]], ptr [[DOTPERMUTED_0_IV_K]], align 4610// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4611// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4612// CHECK1-NEXT: [[DIV10:%.*]] = sdiv i32 [[TMP10]], 64613// CHECK1-NEXT: [[MUL11:%.*]] = mul nsw i32 [[DIV10]], 64614// CHECK1-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP9]], [[MUL11]]615// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4616// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4617// CHECK1-NEXT: [[DIV13:%.*]] = sdiv i32 [[TMP12]], 64618// CHECK1-NEXT: [[MUL14:%.*]] = mul nsw i32 [[DIV13]], 64619// CHECK1-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP11]], [[MUL14]]620// CHECK1-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 16621// CHECK1-NEXT: [[MUL17:%.*]] = mul nsw i32 [[DIV16]], 16622// CHECK1-NEXT: [[SUB18:%.*]] = sub nsw i32 [[SUB12]], [[MUL17]]623// CHECK1-NEXT: [[DIV19:%.*]] = sdiv i32 [[SUB18]], 4624// CHECK1-NEXT: [[MUL20:%.*]] = mul nsw i32 [[DIV19]], 1625// CHECK1-NEXT: [[ADD21:%.*]] = add nsw i32 0, [[MUL20]]626// CHECK1-NEXT: store i32 [[ADD21]], ptr [[DOTPERMUTED_1_IV_J]], align 4627// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4628// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4629// CHECK1-NEXT: [[DIV22:%.*]] = sdiv i32 [[TMP14]], 64630// CHECK1-NEXT: [[MUL23:%.*]] = mul nsw i32 [[DIV22]], 64631// CHECK1-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP13]], [[MUL23]]632// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4633// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4634// CHECK1-NEXT: [[DIV25:%.*]] = sdiv i32 [[TMP16]], 64635// CHECK1-NEXT: [[MUL26:%.*]] = mul nsw i32 [[DIV25]], 64636// CHECK1-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP15]], [[MUL26]]637// CHECK1-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 16638// CHECK1-NEXT: [[MUL29:%.*]] = mul nsw i32 [[DIV28]], 16639// CHECK1-NEXT: [[SUB30:%.*]] = sub nsw i32 [[SUB24]], [[MUL29]]640// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4641// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4642// CHECK1-NEXT: [[DIV31:%.*]] = sdiv i32 [[TMP18]], 64643// CHECK1-NEXT: [[MUL32:%.*]] = mul nsw i32 [[DIV31]], 64644// CHECK1-NEXT: [[SUB33:%.*]] = sub nsw i32 [[TMP17]], [[MUL32]]645// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4646// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4647// CHECK1-NEXT: [[DIV34:%.*]] = sdiv i32 [[TMP20]], 64648// CHECK1-NEXT: [[MUL35:%.*]] = mul nsw i32 [[DIV34]], 64649// CHECK1-NEXT: [[SUB36:%.*]] = sub nsw i32 [[TMP19]], [[MUL35]]650// CHECK1-NEXT: [[DIV37:%.*]] = sdiv i32 [[SUB36]], 16651// CHECK1-NEXT: [[MUL38:%.*]] = mul nsw i32 [[DIV37]], 16652// CHECK1-NEXT: [[SUB39:%.*]] = sub nsw i32 [[SUB33]], [[MUL38]]653// CHECK1-NEXT: [[DIV40:%.*]] = sdiv i32 [[SUB39]], 4654// CHECK1-NEXT: [[MUL41:%.*]] = mul nsw i32 [[DIV40]], 4655// CHECK1-NEXT: [[SUB42:%.*]] = sub nsw i32 [[SUB30]], [[MUL41]]656// CHECK1-NEXT: [[MUL43:%.*]] = mul nsw i32 [[SUB42]], 3657// CHECK1-NEXT: [[ADD44:%.*]] = add nsw i32 7, [[MUL43]]658// CHECK1-NEXT: store i32 [[ADD44]], ptr [[L]], align 4659// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_K]], align 4660// CHECK1-NEXT: [[MUL45:%.*]] = mul nsw i32 [[TMP21]], 3661// CHECK1-NEXT: [[ADD46:%.*]] = add nsw i32 7, [[MUL45]]662// CHECK1-NEXT: store i32 [[ADD46]], ptr [[K]], align 4663// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_J]], align 4664// CHECK1-NEXT: [[MUL47:%.*]] = mul nsw i32 [[TMP22]], 3665// CHECK1-NEXT: [[ADD48:%.*]] = add nsw i32 7, [[MUL47]]666// CHECK1-NEXT: store i32 [[ADD48]], ptr [[J]], align 4667// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[I]], align 4668// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[J]], align 4669// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[K]], align 4670// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[L]], align 4671// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP23]], i32 noundef [[TMP24]], i32 noundef [[TMP25]], i32 noundef [[TMP26]])672// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]673// CHECK1: omp.body.continue:674// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]675// CHECK1: omp.inner.for.inc:676// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4677// CHECK1-NEXT: [[ADD49:%.*]] = add nsw i32 [[TMP27]], 1678// CHECK1-NEXT: store i32 [[ADD49]], ptr [[DOTOMP_IV]], align 4679// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]680// CHECK1: omp.inner.for.end:681// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]682// CHECK1: omp.loop.exit:683// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]])684// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]])685// CHECK1-NEXT: ret void686//687//688// CHECK1-LABEL: define {{[^@]+}}@foo7689// CHECK1-SAME: () #[[ATTR0]] {690// CHECK1-NEXT: entry:691// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4692// CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4693// CHECK1-NEXT: [[K:%.*]] = alloca i32, align 4694// CHECK1-NEXT: [[L:%.*]] = alloca i32, align 4695// CHECK1-NEXT: [[DOTPERMUTED_0_IV_J:%.*]] = alloca i32, align 4696// CHECK1-NEXT: [[DOTPERMUTED_1_IV_K:%.*]] = alloca i32, align 4697// CHECK1-NEXT: [[DOTPERMUTED_2_IV_L:%.*]] = alloca i32, align 4698// CHECK1-NEXT: [[DOTPERMUTED_3_IV_I:%.*]] = alloca i32, align 4699// CHECK1-NEXT: store i32 7, ptr [[I]], align 4700// CHECK1-NEXT: store i32 7, ptr [[J]], align 4701// CHECK1-NEXT: store i32 7, ptr [[K]], align 4702// CHECK1-NEXT: store i32 7, ptr [[L]], align 4703// CHECK1-NEXT: store i32 0, ptr [[DOTPERMUTED_0_IV_J]], align 4704// CHECK1-NEXT: br label [[FOR_COND:%.*]]705// CHECK1: for.cond:706// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4707// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 4708// CHECK1-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END24:%.*]]709// CHECK1: for.body:710// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4711// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 3712// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 7, [[MUL]]713// CHECK1-NEXT: store i32 [[ADD]], ptr [[J]], align 4714// CHECK1-NEXT: store i32 0, ptr [[DOTPERMUTED_1_IV_K]], align 4715// CHECK1-NEXT: br label [[FOR_COND1:%.*]]716// CHECK1: for.cond1:717// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_K]], align 4718// CHECK1-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP2]], 4719// CHECK1-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END21:%.*]]720// CHECK1: for.body3:721// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_K]], align 4722// CHECK1-NEXT: [[MUL4:%.*]] = mul nsw i32 [[TMP3]], 3723// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 7, [[MUL4]]724// CHECK1-NEXT: store i32 [[ADD5]], ptr [[K]], align 4725// CHECK1-NEXT: store i32 0, ptr [[DOTPERMUTED_2_IV_L]], align 4726// CHECK1-NEXT: br label [[FOR_COND6:%.*]]727// CHECK1: for.cond6:728// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTPERMUTED_2_IV_L]], align 4729// CHECK1-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP4]], 4730// CHECK1-NEXT: br i1 [[CMP7]], label [[FOR_BODY8:%.*]], label [[FOR_END18:%.*]]731// CHECK1: for.body8:732// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTPERMUTED_2_IV_L]], align 4733// CHECK1-NEXT: [[MUL9:%.*]] = mul nsw i32 [[TMP5]], 3734// CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 7, [[MUL9]]735// CHECK1-NEXT: store i32 [[ADD10]], ptr [[L]], align 4736// CHECK1-NEXT: store i32 0, ptr [[DOTPERMUTED_3_IV_I]], align 4737// CHECK1-NEXT: br label [[FOR_COND11:%.*]]738// CHECK1: for.cond11:739// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTPERMUTED_3_IV_I]], align 4740// CHECK1-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP6]], 4741// CHECK1-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END:%.*]]742// CHECK1: for.body13:743// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTPERMUTED_3_IV_I]], align 4744// CHECK1-NEXT: [[MUL14:%.*]] = mul nsw i32 [[TMP7]], 3745// CHECK1-NEXT: [[ADD15:%.*]] = add nsw i32 7, [[MUL14]]746// CHECK1-NEXT: store i32 [[ADD15]], ptr [[I]], align 4747// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[I]], align 4748// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[J]], align 4749// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[K]], align 4750// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[L]], align 4751// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP8]], i32 noundef [[TMP9]], i32 noundef [[TMP10]], i32 noundef [[TMP11]])752// CHECK1-NEXT: br label [[FOR_INC:%.*]]753// CHECK1: for.inc:754// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTPERMUTED_3_IV_I]], align 4755// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1756// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTPERMUTED_3_IV_I]], align 4757// CHECK1-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP9:![0-9]+]]758// CHECK1: for.end:759// CHECK1-NEXT: br label [[FOR_INC16:%.*]]760// CHECK1: for.inc16:761// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTPERMUTED_2_IV_L]], align 4762// CHECK1-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP13]], 1763// CHECK1-NEXT: store i32 [[INC17]], ptr [[DOTPERMUTED_2_IV_L]], align 4764// CHECK1-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP10:![0-9]+]]765// CHECK1: for.end18:766// CHECK1-NEXT: br label [[FOR_INC19:%.*]]767// CHECK1: for.inc19:768// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_K]], align 4769// CHECK1-NEXT: [[INC20:%.*]] = add nsw i32 [[TMP14]], 1770// CHECK1-NEXT: store i32 [[INC20]], ptr [[DOTPERMUTED_1_IV_K]], align 4771// CHECK1-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP11:![0-9]+]]772// CHECK1: for.end21:773// CHECK1-NEXT: br label [[FOR_INC22:%.*]]774// CHECK1: for.inc22:775// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4776// CHECK1-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP15]], 1777// CHECK1-NEXT: store i32 [[INC23]], ptr [[DOTPERMUTED_0_IV_J]], align 4778// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]779// CHECK1: for.end24:780// CHECK1-NEXT: ret void781//782//783// CHECK1-LABEL: define {{[^@]+}}@tfoo8784// CHECK1-SAME: () #[[ATTR0]] {785// CHECK1-NEXT: entry:786// CHECK1-NEXT: call void @_Z4foo8ILi32EEviii(i32 noundef 0, i32 noundef 42, i32 noundef 1)787// CHECK1-NEXT: call void @_Z4foo8ILi64EEviii(i32 noundef 0, i32 noundef 42, i32 noundef 3)788// CHECK1-NEXT: ret void789//790//791// CHECK1-LABEL: define {{[^@]+}}@_Z4foo8ILi32EEviii792// CHECK1-SAME: (i32 noundef [[START:%.*]], i32 noundef [[END:%.*]], i32 noundef [[STEP:%.*]]) #[[ATTR0]] comdat {793// CHECK1-NEXT: entry:794// CHECK1-NEXT: [[START_ADDR:%.*]] = alloca i32, align 4795// CHECK1-NEXT: [[END_ADDR:%.*]] = alloca i32, align 4796// CHECK1-NEXT: [[STEP_ADDR:%.*]] = alloca i32, align 4797// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8798// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4799// CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4800// CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4801// CHECK1-NEXT: [[_TMP3:%.*]] = alloca i32, align 4802// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4803// CHECK1-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4804// CHECK1-NEXT: [[DOTNEW_STEP:%.*]] = alloca i32, align 4805// CHECK1-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4806// CHECK1-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i32, align 4807// CHECK1-NEXT: [[DOTNEW_STEP7:%.*]] = alloca i32, align 4808// CHECK1-NEXT: [[K:%.*]] = alloca i32, align 4809// CHECK1-NEXT: [[DOTCAPTURE_EXPR_8:%.*]] = alloca i32, align 4810// CHECK1-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4811// CHECK1-NEXT: [[DOTNEW_STEP10:%.*]] = alloca i32, align 4812// CHECK1-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 4813// CHECK1-NEXT: [[DOTCAPTURE_EXPR_14:%.*]] = alloca i32, align 4814// CHECK1-NEXT: [[DOTCAPTURE_EXPR_16:%.*]] = alloca i32, align 4815// CHECK1-NEXT: [[DOTCAPTURE_EXPR_17:%.*]] = alloca i32, align 4816// CHECK1-NEXT: [[DOTCAPTURE_EXPR_22:%.*]] = alloca i64, align 8817// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4818// CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4819// CHECK1-NEXT: [[DOTFLOOR_0_IV_K:%.*]] = alloca i32, align 4820// CHECK1-NEXT: [[DOTTILE_0_IV_K:%.*]] = alloca i32, align 4821// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8822// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8823// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8824// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4825// CHECK1-NEXT: [[I49:%.*]] = alloca i32, align 4826// CHECK1-NEXT: [[J50:%.*]] = alloca i32, align 4827// CHECK1-NEXT: [[DOTFLOOR_0_IV_K51:%.*]] = alloca i32, align 4828// CHECK1-NEXT: [[DOTTILE_0_IV_K52:%.*]] = alloca i32, align 4829// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])830// CHECK1-NEXT: store i32 [[START]], ptr [[START_ADDR]], align 4831// CHECK1-NEXT: store i32 [[END]], ptr [[END_ADDR]], align 4832// CHECK1-NEXT: store i32 [[STEP]], ptr [[STEP_ADDR]], align 4833// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[START_ADDR]], align 4834// CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4835// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[END_ADDR]], align 4836// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_4]], align 4837// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[STEP_ADDR]], align 4838// CHECK1-NEXT: store i32 [[TMP3]], ptr [[DOTNEW_STEP]], align 4839// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[START_ADDR]], align 4840// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_5]], align 4841// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[END_ADDR]], align 4842// CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_6]], align 4843// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[STEP_ADDR]], align 4844// CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTNEW_STEP7]], align 4845// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[START_ADDR]], align 4846// CHECK1-NEXT: store i32 [[TMP7]], ptr [[K]], align 4847// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[START_ADDR]], align 4848// CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTCAPTURE_EXPR_8]], align 4849// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[END_ADDR]], align 4850// CHECK1-NEXT: store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR_9]], align 4851// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[STEP_ADDR]], align 4852// CHECK1-NEXT: store i32 [[TMP10]], ptr [[DOTNEW_STEP10]], align 4853// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_9]], align 4854// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_8]], align 4855// CHECK1-NEXT: [[SUB:%.*]] = sub i32 [[TMP11]], [[TMP12]]856// CHECK1-NEXT: [[SUB12:%.*]] = sub i32 [[SUB]], 1857// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 4858// CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB12]], [[TMP13]]859// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 4860// CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], [[TMP14]]861// CHECK1-NEXT: [[SUB13:%.*]] = sub i32 [[DIV]], 1862// CHECK1-NEXT: store i32 [[SUB13]], ptr [[DOTCAPTURE_EXPR_11]], align 4863// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4864// CHECK1-NEXT: [[ADD15:%.*]] = add i32 [[TMP15]], 1865// CHECK1-NEXT: store i32 [[ADD15]], ptr [[DOTCAPTURE_EXPR_14]], align 4866// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[_TMP2]], align 4867// CHECK1-NEXT: store i32 [[TMP16]], ptr [[DOTCAPTURE_EXPR_16]], align 4868// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4869// CHECK1-NEXT: [[ADD18:%.*]] = add i32 [[TMP17]], 1870// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[_TMP2]], align 4871// CHECK1-NEXT: [[ADD19:%.*]] = add i32 [[TMP18]], 32872// CHECK1-NEXT: [[CMP:%.*]] = icmp ult i32 [[ADD18]], [[ADD19]]873// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]874// CHECK1: cond.true:875// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4876// CHECK1-NEXT: [[ADD20:%.*]] = add i32 [[TMP19]], 1877// CHECK1-NEXT: br label [[COND_END:%.*]]878// CHECK1: cond.false:879// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[_TMP2]], align 4880// CHECK1-NEXT: [[ADD21:%.*]] = add i32 [[TMP20]], 32881// CHECK1-NEXT: br label [[COND_END]]882// CHECK1: cond.end:883// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[ADD20]], [[COND_TRUE]] ], [ [[ADD21]], [[COND_FALSE]] ]884// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTCAPTURE_EXPR_17]], align 4885// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4886// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4887// CHECK1-NEXT: [[SUB23:%.*]] = sub i32 [[TMP21]], [[TMP22]]888// CHECK1-NEXT: [[SUB24:%.*]] = sub i32 [[SUB23]], 1889// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4890// CHECK1-NEXT: [[ADD25:%.*]] = add i32 [[SUB24]], [[TMP23]]891// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4892// CHECK1-NEXT: [[DIV26:%.*]] = udiv i32 [[ADD25]], [[TMP24]]893// CHECK1-NEXT: [[CONV:%.*]] = zext i32 [[DIV26]] to i64894// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4895// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4896// CHECK1-NEXT: [[SUB27:%.*]] = sub i32 [[TMP25]], [[TMP26]]897// CHECK1-NEXT: [[SUB28:%.*]] = sub i32 [[SUB27]], 1898// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4899// CHECK1-NEXT: [[ADD29:%.*]] = add i32 [[SUB28]], [[TMP27]]900// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4901// CHECK1-NEXT: [[DIV30:%.*]] = udiv i32 [[ADD29]], [[TMP28]]902// CHECK1-NEXT: [[CONV31:%.*]] = zext i32 [[DIV30]] to i64903// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV31]]904// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4905// CHECK1-NEXT: [[SUB32:%.*]] = sub i32 [[TMP29]], -31906// CHECK1-NEXT: [[DIV33:%.*]] = udiv i32 [[SUB32]], 32907// CHECK1-NEXT: [[CONV34:%.*]] = zext i32 [[DIV33]] to i64908// CHECK1-NEXT: [[MUL35:%.*]] = mul nsw i64 [[MUL]], [[CONV34]]909// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4910// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4911// CHECK1-NEXT: [[SUB36:%.*]] = sub i32 [[TMP30]], [[TMP31]]912// CHECK1-NEXT: [[SUB37:%.*]] = sub i32 [[SUB36]], 1913// CHECK1-NEXT: [[ADD38:%.*]] = add i32 [[SUB37]], 1914// CHECK1-NEXT: [[DIV39:%.*]] = udiv i32 [[ADD38]], 1915// CHECK1-NEXT: [[CONV40:%.*]] = zext i32 [[DIV39]] to i64916// CHECK1-NEXT: [[MUL41:%.*]] = mul nsw i64 [[MUL35]], [[CONV40]]917// CHECK1-NEXT: [[SUB42:%.*]] = sub nsw i64 [[MUL41]], 1918// CHECK1-NEXT: store i64 [[SUB42]], ptr [[DOTCAPTURE_EXPR_22]], align 8919// CHECK1-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4920// CHECK1-NEXT: store i32 [[TMP32]], ptr [[I]], align 4921// CHECK1-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4922// CHECK1-NEXT: store i32 [[TMP33]], ptr [[J]], align 4923// CHECK1-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV_K]], align 4924// CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4925// CHECK1-NEXT: store i32 [[TMP34]], ptr [[DOTTILE_0_IV_K]], align 4926// CHECK1-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4927// CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4928// CHECK1-NEXT: [[CMP43:%.*]] = icmp slt i32 [[TMP35]], [[TMP36]]929// CHECK1-NEXT: br i1 [[CMP43]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]930// CHECK1: land.lhs.true:931// CHECK1-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4932// CHECK1-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4933// CHECK1-NEXT: [[CMP44:%.*]] = icmp slt i32 [[TMP37]], [[TMP38]]934// CHECK1-NEXT: br i1 [[CMP44]], label [[LAND_LHS_TRUE45:%.*]], label [[OMP_PRECOND_END]]935// CHECK1: land.lhs.true45:936// CHECK1-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4937// CHECK1-NEXT: [[CMP46:%.*]] = icmp ult i32 0, [[TMP39]]938// CHECK1-NEXT: br i1 [[CMP46]], label [[LAND_LHS_TRUE47:%.*]], label [[OMP_PRECOND_END]]939// CHECK1: land.lhs.true47:940// CHECK1-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4941// CHECK1-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4942// CHECK1-NEXT: [[CMP48:%.*]] = icmp ult i32 [[TMP40]], [[TMP41]]943// CHECK1-NEXT: br i1 [[CMP48]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]944// CHECK1: omp.precond.then:945// CHECK1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8946// CHECK1-NEXT: [[TMP42:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8947// CHECK1-NEXT: store i64 [[TMP42]], ptr [[DOTOMP_UB]], align 8948// CHECK1-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8949// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4950// CHECK1-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)951// CHECK1-NEXT: [[TMP43:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8952// CHECK1-NEXT: [[TMP44:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8953// CHECK1-NEXT: [[CMP53:%.*]] = icmp sgt i64 [[TMP43]], [[TMP44]]954// CHECK1-NEXT: br i1 [[CMP53]], label [[COND_TRUE54:%.*]], label [[COND_FALSE55:%.*]]955// CHECK1: cond.true54:956// CHECK1-NEXT: [[TMP45:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8957// CHECK1-NEXT: br label [[COND_END56:%.*]]958// CHECK1: cond.false55:959// CHECK1-NEXT: [[TMP46:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8960// CHECK1-NEXT: br label [[COND_END56]]961// CHECK1: cond.end56:962// CHECK1-NEXT: [[COND57:%.*]] = phi i64 [ [[TMP45]], [[COND_TRUE54]] ], [ [[TMP46]], [[COND_FALSE55]] ]963// CHECK1-NEXT: store i64 [[COND57]], ptr [[DOTOMP_UB]], align 8964// CHECK1-NEXT: [[TMP47:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8965// CHECK1-NEXT: store i64 [[TMP47]], ptr [[DOTOMP_IV]], align 8966// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]967// CHECK1: omp.inner.for.cond:968// CHECK1-NEXT: [[TMP48:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8969// CHECK1-NEXT: [[TMP49:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8970// CHECK1-NEXT: [[CMP58:%.*]] = icmp sle i64 [[TMP48]], [[TMP49]]971// CHECK1-NEXT: br i1 [[CMP58]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]972// CHECK1: omp.inner.for.body:973// CHECK1-NEXT: [[TMP50:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4974// CHECK1-NEXT: [[CONV59:%.*]] = sext i32 [[TMP50]] to i64975// CHECK1-NEXT: [[TMP51:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8976// CHECK1-NEXT: [[TMP52:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4977// CHECK1-NEXT: [[TMP53:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4978// CHECK1-NEXT: [[SUB60:%.*]] = sub i32 [[TMP52]], [[TMP53]]979// CHECK1-NEXT: [[SUB61:%.*]] = sub i32 [[SUB60]], 1980// CHECK1-NEXT: [[TMP54:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4981// CHECK1-NEXT: [[ADD62:%.*]] = add i32 [[SUB61]], [[TMP54]]982// CHECK1-NEXT: [[TMP55:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4983// CHECK1-NEXT: [[DIV63:%.*]] = udiv i32 [[ADD62]], [[TMP55]]984// CHECK1-NEXT: [[MUL64:%.*]] = mul i32 1, [[DIV63]]985// CHECK1-NEXT: [[TMP56:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4986// CHECK1-NEXT: [[SUB65:%.*]] = sub i32 [[TMP56]], -31987// CHECK1-NEXT: [[DIV66:%.*]] = udiv i32 [[SUB65]], 32988// CHECK1-NEXT: [[MUL67:%.*]] = mul i32 [[MUL64]], [[DIV66]]989// CHECK1-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4990// CHECK1-NEXT: [[TMP58:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4991// CHECK1-NEXT: [[SUB68:%.*]] = sub i32 [[TMP57]], [[TMP58]]992// CHECK1-NEXT: [[SUB69:%.*]] = sub i32 [[SUB68]], 1993// CHECK1-NEXT: [[ADD70:%.*]] = add i32 [[SUB69]], 1994// CHECK1-NEXT: [[DIV71:%.*]] = udiv i32 [[ADD70]], 1995// CHECK1-NEXT: [[MUL72:%.*]] = mul i32 [[MUL67]], [[DIV71]]996// CHECK1-NEXT: [[CONV73:%.*]] = zext i32 [[MUL72]] to i64997// CHECK1-NEXT: [[DIV74:%.*]] = sdiv i64 [[TMP51]], [[CONV73]]998// CHECK1-NEXT: [[TMP59:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4999// CHECK1-NEXT: [[CONV75:%.*]] = sext i32 [[TMP59]] to i641000// CHECK1-NEXT: [[MUL76:%.*]] = mul nsw i64 [[DIV74]], [[CONV75]]1001// CHECK1-NEXT: [[ADD77:%.*]] = add nsw i64 [[CONV59]], [[MUL76]]1002// CHECK1-NEXT: [[CONV78:%.*]] = trunc i64 [[ADD77]] to i321003// CHECK1-NEXT: store i32 [[CONV78]], ptr [[I49]], align 41004// CHECK1-NEXT: [[TMP60:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 41005// CHECK1-NEXT: [[CONV79:%.*]] = sext i32 [[TMP60]] to i641006// CHECK1-NEXT: [[TMP61:%.*]] = load i64, ptr [[DOTOMP_IV]], align 81007// CHECK1-NEXT: [[TMP62:%.*]] = load i64, ptr [[DOTOMP_IV]], align 81008// CHECK1-NEXT: [[TMP63:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 41009// CHECK1-NEXT: [[TMP64:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 41010// CHECK1-NEXT: [[SUB80:%.*]] = sub i32 [[TMP63]], [[TMP64]]1011// CHECK1-NEXT: [[SUB81:%.*]] = sub i32 [[SUB80]], 11012// CHECK1-NEXT: [[TMP65:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41013// CHECK1-NEXT: [[ADD82:%.*]] = add i32 [[SUB81]], [[TMP65]]1014// CHECK1-NEXT: [[TMP66:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41015// CHECK1-NEXT: [[DIV83:%.*]] = udiv i32 [[ADD82]], [[TMP66]]1016// CHECK1-NEXT: [[MUL84:%.*]] = mul i32 1, [[DIV83]]1017// CHECK1-NEXT: [[TMP67:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 41018// CHECK1-NEXT: [[SUB85:%.*]] = sub i32 [[TMP67]], -311019// CHECK1-NEXT: [[DIV86:%.*]] = udiv i32 [[SUB85]], 321020// CHECK1-NEXT: [[MUL87:%.*]] = mul i32 [[MUL84]], [[DIV86]]1021// CHECK1-NEXT: [[TMP68:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 41022// CHECK1-NEXT: [[TMP69:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 41023// CHECK1-NEXT: [[SUB88:%.*]] = sub i32 [[TMP68]], [[TMP69]]1024// CHECK1-NEXT: [[SUB89:%.*]] = sub i32 [[SUB88]], 11025// CHECK1-NEXT: [[ADD90:%.*]] = add i32 [[SUB89]], 11026// CHECK1-NEXT: [[DIV91:%.*]] = udiv i32 [[ADD90]], 11027// CHECK1-NEXT: [[MUL92:%.*]] = mul i32 [[MUL87]], [[DIV91]]1028// CHECK1-NEXT: [[CONV93:%.*]] = zext i32 [[MUL92]] to i641029// CHECK1-NEXT: [[DIV94:%.*]] = sdiv i64 [[TMP62]], [[CONV93]]1030// CHECK1-NEXT: [[TMP70:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 41031// CHECK1-NEXT: [[TMP71:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 41032// CHECK1-NEXT: [[SUB95:%.*]] = sub i32 [[TMP70]], [[TMP71]]1033// CHECK1-NEXT: [[SUB96:%.*]] = sub i32 [[SUB95]], 11034// CHECK1-NEXT: [[TMP72:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41035// CHECK1-NEXT: [[ADD97:%.*]] = add i32 [[SUB96]], [[TMP72]]1036// CHECK1-NEXT: [[TMP73:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41037// CHECK1-NEXT: [[DIV98:%.*]] = udiv i32 [[ADD97]], [[TMP73]]1038// CHECK1-NEXT: [[MUL99:%.*]] = mul i32 1, [[DIV98]]1039// CHECK1-NEXT: [[TMP74:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 41040// CHECK1-NEXT: [[SUB100:%.*]] = sub i32 [[TMP74]], -311041// CHECK1-NEXT: [[DIV101:%.*]] = udiv i32 [[SUB100]], 321042// CHECK1-NEXT: [[MUL102:%.*]] = mul i32 [[MUL99]], [[DIV101]]1043// CHECK1-NEXT: [[TMP75:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 41044// CHECK1-NEXT: [[TMP76:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 41045// CHECK1-NEXT: [[SUB103:%.*]] = sub i32 [[TMP75]], [[TMP76]]1046// CHECK1-NEXT: [[SUB104:%.*]] = sub i32 [[SUB103]], 11047// CHECK1-NEXT: [[ADD105:%.*]] = add i32 [[SUB104]], 11048// CHECK1-NEXT: [[DIV106:%.*]] = udiv i32 [[ADD105]], 11049// CHECK1-NEXT: [[MUL107:%.*]] = mul i32 [[MUL102]], [[DIV106]]1050// CHECK1-NEXT: [[CONV108:%.*]] = zext i32 [[MUL107]] to i641051// CHECK1-NEXT: [[MUL109:%.*]] = mul nsw i64 [[DIV94]], [[CONV108]]1052// CHECK1-NEXT: [[SUB110:%.*]] = sub nsw i64 [[TMP61]], [[MUL109]]1053// CHECK1-NEXT: [[TMP77:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 41054// CHECK1-NEXT: [[SUB111:%.*]] = sub i32 [[TMP77]], -311055// CHECK1-NEXT: [[DIV112:%.*]] = udiv i32 [[SUB111]], 321056// CHECK1-NEXT: [[MUL113:%.*]] = mul i32 1, [[DIV112]]1057// CHECK1-NEXT: [[TMP78:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 41058// CHECK1-NEXT: [[TMP79:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 41059// CHECK1-NEXT: [[SUB114:%.*]] = sub i32 [[TMP78]], [[TMP79]]1060// CHECK1-NEXT: [[SUB115:%.*]] = sub i32 [[SUB114]], 11061// CHECK1-NEXT: [[ADD116:%.*]] = add i32 [[SUB115]], 11062// CHECK1-NEXT: [[DIV117:%.*]] = udiv i32 [[ADD116]], 11063// CHECK1-NEXT: [[MUL118:%.*]] = mul i32 [[MUL113]], [[DIV117]]1064// CHECK1-NEXT: [[CONV119:%.*]] = zext i32 [[MUL118]] to i641065// CHECK1-NEXT: [[DIV120:%.*]] = sdiv i64 [[SUB110]], [[CONV119]]1066// CHECK1-NEXT: [[TMP80:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41067// CHECK1-NEXT: [[CONV121:%.*]] = sext i32 [[TMP80]] to i641068// CHECK1-NEXT: [[MUL122:%.*]] = mul nsw i64 [[DIV120]], [[CONV121]]1069// CHECK1-NEXT: [[ADD123:%.*]] = add nsw i64 [[CONV79]], [[MUL122]]1070// CHECK1-NEXT: [[CONV124:%.*]] = trunc i64 [[ADD123]] to i321071// CHECK1-NEXT: store i32 [[CONV124]], ptr [[J50]], align 41072// CHECK1-NEXT: [[TMP81:%.*]] = load i64, ptr [[DOTOMP_IV]], align 81073// CHECK1-NEXT: [[TMP82:%.*]] = load i64, ptr [[DOTOMP_IV]], align 81074// CHECK1-NEXT: [[TMP83:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 41075// CHECK1-NEXT: [[TMP84:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 41076// CHECK1-NEXT: [[SUB125:%.*]] = sub i32 [[TMP83]], [[TMP84]]1077// CHECK1-NEXT: [[SUB126:%.*]] = sub i32 [[SUB125]], 11078// CHECK1-NEXT: [[TMP85:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41079// CHECK1-NEXT: [[ADD127:%.*]] = add i32 [[SUB126]], [[TMP85]]1080// CHECK1-NEXT: [[TMP86:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41081// CHECK1-NEXT: [[DIV128:%.*]] = udiv i32 [[ADD127]], [[TMP86]]1082// CHECK1-NEXT: [[MUL129:%.*]] = mul i32 1, [[DIV128]]1083// CHECK1-NEXT: [[TMP87:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 41084// CHECK1-NEXT: [[SUB130:%.*]] = sub i32 [[TMP87]], -311085// CHECK1-NEXT: [[DIV131:%.*]] = udiv i32 [[SUB130]], 321086// CHECK1-NEXT: [[MUL132:%.*]] = mul i32 [[MUL129]], [[DIV131]]1087// CHECK1-NEXT: [[TMP88:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 41088// CHECK1-NEXT: [[TMP89:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 41089// CHECK1-NEXT: [[SUB133:%.*]] = sub i32 [[TMP88]], [[TMP89]]1090// CHECK1-NEXT: [[SUB134:%.*]] = sub i32 [[SUB133]], 11091// CHECK1-NEXT: [[ADD135:%.*]] = add i32 [[SUB134]], 11092// CHECK1-NEXT: [[DIV136:%.*]] = udiv i32 [[ADD135]], 11093// CHECK1-NEXT: [[MUL137:%.*]] = mul i32 [[MUL132]], [[DIV136]]1094// CHECK1-NEXT: [[CONV138:%.*]] = zext i32 [[MUL137]] to i641095// CHECK1-NEXT: [[DIV139:%.*]] = sdiv i64 [[TMP82]], [[CONV138]]1096// CHECK1-NEXT: [[TMP90:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 41097// CHECK1-NEXT: [[TMP91:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 41098// CHECK1-NEXT: [[SUB140:%.*]] = sub i32 [[TMP90]], [[TMP91]]1099// CHECK1-NEXT: [[SUB141:%.*]] = sub i32 [[SUB140]], 11100// CHECK1-NEXT: [[TMP92:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41101// CHECK1-NEXT: [[ADD142:%.*]] = add i32 [[SUB141]], [[TMP92]]1102// CHECK1-NEXT: [[TMP93:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41103// CHECK1-NEXT: [[DIV143:%.*]] = udiv i32 [[ADD142]], [[TMP93]]1104// CHECK1-NEXT: [[MUL144:%.*]] = mul i32 1, [[DIV143]]1105// CHECK1-NEXT: [[TMP94:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 41106// CHECK1-NEXT: [[SUB145:%.*]] = sub i32 [[TMP94]], -311107// CHECK1-NEXT: [[DIV146:%.*]] = udiv i32 [[SUB145]], 321108// CHECK1-NEXT: [[MUL147:%.*]] = mul i32 [[MUL144]], [[DIV146]]1109// CHECK1-NEXT: [[TMP95:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 41110// CHECK1-NEXT: [[TMP96:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 41111// CHECK1-NEXT: [[SUB148:%.*]] = sub i32 [[TMP95]], [[TMP96]]1112// CHECK1-NEXT: [[SUB149:%.*]] = sub i32 [[SUB148]], 11113// CHECK1-NEXT: [[ADD150:%.*]] = add i32 [[SUB149]], 11114// CHECK1-NEXT: [[DIV151:%.*]] = udiv i32 [[ADD150]], 11115// CHECK1-NEXT: [[MUL152:%.*]] = mul i32 [[MUL147]], [[DIV151]]1116// CHECK1-NEXT: [[CONV153:%.*]] = zext i32 [[MUL152]] to i641117// CHECK1-NEXT: [[MUL154:%.*]] = mul nsw i64 [[DIV139]], [[CONV153]]1118// CHECK1-NEXT: [[SUB155:%.*]] = sub nsw i64 [[TMP81]], [[MUL154]]1119// CHECK1-NEXT: [[TMP97:%.*]] = load i64, ptr [[DOTOMP_IV]], align 81120// CHECK1-NEXT: [[TMP98:%.*]] = load i64, ptr [[DOTOMP_IV]], align 81121// CHECK1-NEXT: [[TMP99:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 41122// CHECK1-NEXT: [[TMP100:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 41123// CHECK1-NEXT: [[SUB156:%.*]] = sub i32 [[TMP99]], [[TMP100]]1124// CHECK1-NEXT: [[SUB157:%.*]] = sub i32 [[SUB156]], 11125// CHECK1-NEXT: [[TMP101:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41126// CHECK1-NEXT: [[ADD158:%.*]] = add i32 [[SUB157]], [[TMP101]]1127// CHECK1-NEXT: [[TMP102:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41128// CHECK1-NEXT: [[DIV159:%.*]] = udiv i32 [[ADD158]], [[TMP102]]1129// CHECK1-NEXT: [[MUL160:%.*]] = mul i32 1, [[DIV159]]1130// CHECK1-NEXT: [[TMP103:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 41131// CHECK1-NEXT: [[SUB161:%.*]] = sub i32 [[TMP103]], -311132// CHECK1-NEXT: [[DIV162:%.*]] = udiv i32 [[SUB161]], 321133// CHECK1-NEXT: [[MUL163:%.*]] = mul i32 [[MUL160]], [[DIV162]]1134// CHECK1-NEXT: [[TMP104:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 41135// CHECK1-NEXT: [[TMP105:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 41136// CHECK1-NEXT: [[SUB164:%.*]] = sub i32 [[TMP104]], [[TMP105]]1137// CHECK1-NEXT: [[SUB165:%.*]] = sub i32 [[SUB164]], 11138// CHECK1-NEXT: [[ADD166:%.*]] = add i32 [[SUB165]], 11139// CHECK1-NEXT: [[DIV167:%.*]] = udiv i32 [[ADD166]], 11140// CHECK1-NEXT: [[MUL168:%.*]] = mul i32 [[MUL163]], [[DIV167]]1141// CHECK1-NEXT: [[CONV169:%.*]] = zext i32 [[MUL168]] to i641142// CHECK1-NEXT: [[DIV170:%.*]] = sdiv i64 [[TMP98]], [[CONV169]]1143// CHECK1-NEXT: [[TMP106:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 41144// CHECK1-NEXT: [[TMP107:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 41145// CHECK1-NEXT: [[SUB171:%.*]] = sub i32 [[TMP106]], [[TMP107]]1146// CHECK1-NEXT: [[SUB172:%.*]] = sub i32 [[SUB171]], 11147// CHECK1-NEXT: [[TMP108:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41148// CHECK1-NEXT: [[ADD173:%.*]] = add i32 [[SUB172]], [[TMP108]]1149// CHECK1-NEXT: [[TMP109:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41150// CHECK1-NEXT: [[DIV174:%.*]] = udiv i32 [[ADD173]], [[TMP109]]1151// CHECK1-NEXT: [[MUL175:%.*]] = mul i32 1, [[DIV174]]1152// CHECK1-NEXT: [[TMP110:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 41153// CHECK1-NEXT: [[SUB176:%.*]] = sub i32 [[TMP110]], -311154// CHECK1-NEXT: [[DIV177:%.*]] = udiv i32 [[SUB176]], 321155// CHECK1-NEXT: [[MUL178:%.*]] = mul i32 [[MUL175]], [[DIV177]]1156// CHECK1-NEXT: [[TMP111:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 41157// CHECK1-NEXT: [[TMP112:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 41158// CHECK1-NEXT: [[SUB179:%.*]] = sub i32 [[TMP111]], [[TMP112]]1159// CHECK1-NEXT: [[SUB180:%.*]] = sub i32 [[SUB179]], 11160// CHECK1-NEXT: [[ADD181:%.*]] = add i32 [[SUB180]], 11161// CHECK1-NEXT: [[DIV182:%.*]] = udiv i32 [[ADD181]], 11162// CHECK1-NEXT: [[MUL183:%.*]] = mul i32 [[MUL178]], [[DIV182]]1163// CHECK1-NEXT: [[CONV184:%.*]] = zext i32 [[MUL183]] to i641164// CHECK1-NEXT: [[MUL185:%.*]] = mul nsw i64 [[DIV170]], [[CONV184]]1165// CHECK1-NEXT: [[SUB186:%.*]] = sub nsw i64 [[TMP97]], [[MUL185]]1166// CHECK1-NEXT: [[TMP113:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 41167// CHECK1-NEXT: [[SUB187:%.*]] = sub i32 [[TMP113]], -311168// CHECK1-NEXT: [[DIV188:%.*]] = udiv i32 [[SUB187]], 321169// CHECK1-NEXT: [[MUL189:%.*]] = mul i32 1, [[DIV188]]1170// CHECK1-NEXT: [[TMP114:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 41171// CHECK1-NEXT: [[TMP115:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 41172// CHECK1-NEXT: [[SUB190:%.*]] = sub i32 [[TMP114]], [[TMP115]]1173// CHECK1-NEXT: [[SUB191:%.*]] = sub i32 [[SUB190]], 11174// CHECK1-NEXT: [[ADD192:%.*]] = add i32 [[SUB191]], 11175// CHECK1-NEXT: [[DIV193:%.*]] = udiv i32 [[ADD192]], 11176// CHECK1-NEXT: [[MUL194:%.*]] = mul i32 [[MUL189]], [[DIV193]]1177// CHECK1-NEXT: [[CONV195:%.*]] = zext i32 [[MUL194]] to i641178// CHECK1-NEXT: [[DIV196:%.*]] = sdiv i64 [[SUB186]], [[CONV195]]1179// CHECK1-NEXT: [[TMP116:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 41180// CHECK1-NEXT: [[SUB197:%.*]] = sub i32 [[TMP116]], -311181// CHECK1-NEXT: [[DIV198:%.*]] = udiv i32 [[SUB197]], 321182// CHECK1-NEXT: [[MUL199:%.*]] = mul i32 1, [[DIV198]]1183// CHECK1-NEXT: [[TMP117:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 41184// CHECK1-NEXT: [[TMP118:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 41185// CHECK1-NEXT: [[SUB200:%.*]] = sub i32 [[TMP117]], [[TMP118]]1186// CHECK1-NEXT: [[SUB201:%.*]] = sub i32 [[SUB200]], 11187// CHECK1-NEXT: [[ADD202:%.*]] = add i32 [[SUB201]], 11188// CHECK1-NEXT: [[DIV203:%.*]] = udiv i32 [[ADD202]], 11189// CHECK1-NEXT: [[MUL204:%.*]] = mul i32 [[MUL199]], [[DIV203]]1190// CHECK1-NEXT: [[CONV205:%.*]] = zext i32 [[MUL204]] to i641191// CHECK1-NEXT: [[MUL206:%.*]] = mul nsw i64 [[DIV196]], [[CONV205]]1192// CHECK1-NEXT: [[SUB207:%.*]] = sub nsw i64 [[SUB155]], [[MUL206]]1193// CHECK1-NEXT: [[TMP119:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 41194// CHECK1-NEXT: [[TMP120:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 41195// CHECK1-NEXT: [[SUB208:%.*]] = sub i32 [[TMP119]], [[TMP120]]1196// CHECK1-NEXT: [[SUB209:%.*]] = sub i32 [[SUB208]], 11197// CHECK1-NEXT: [[ADD210:%.*]] = add i32 [[SUB209]], 11198// CHECK1-NEXT: [[DIV211:%.*]] = udiv i32 [[ADD210]], 11199// CHECK1-NEXT: [[MUL212:%.*]] = mul i32 1, [[DIV211]]1200// CHECK1-NEXT: [[CONV213:%.*]] = zext i32 [[MUL212]] to i641201// CHECK1-NEXT: [[DIV214:%.*]] = sdiv i64 [[SUB207]], [[CONV213]]1202// CHECK1-NEXT: [[MUL215:%.*]] = mul nsw i64 [[DIV214]], 321203// CHECK1-NEXT: [[ADD216:%.*]] = add nsw i64 0, [[MUL215]]1204// CHECK1-NEXT: [[CONV217:%.*]] = trunc i64 [[ADD216]] to i321205// CHECK1-NEXT: store i32 [[CONV217]], ptr [[DOTFLOOR_0_IV_K51]], align 41206// CHECK1-NEXT: [[TMP121:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 41207// CHECK1-NEXT: [[CONV218:%.*]] = zext i32 [[TMP121]] to i641208// CHECK1-NEXT: [[TMP122:%.*]] = load i64, ptr [[DOTOMP_IV]], align 81209// CHECK1-NEXT: [[TMP123:%.*]] = load i64, ptr [[DOTOMP_IV]], align 81210// CHECK1-NEXT: [[TMP124:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 41211// CHECK1-NEXT: [[TMP125:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 41212// CHECK1-NEXT: [[SUB219:%.*]] = sub i32 [[TMP124]], [[TMP125]]1213// CHECK1-NEXT: [[SUB220:%.*]] = sub i32 [[SUB219]], 11214// CHECK1-NEXT: [[TMP126:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41215// CHECK1-NEXT: [[ADD221:%.*]] = add i32 [[SUB220]], [[TMP126]]1216// CHECK1-NEXT: [[TMP127:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41217// CHECK1-NEXT: [[DIV222:%.*]] = udiv i32 [[ADD221]], [[TMP127]]1218// CHECK1-NEXT: [[MUL223:%.*]] = mul i32 1, [[DIV222]]1219// CHECK1-NEXT: [[TMP128:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 41220// CHECK1-NEXT: [[SUB224:%.*]] = sub i32 [[TMP128]], -311221// CHECK1-NEXT: [[DIV225:%.*]] = udiv i32 [[SUB224]], 321222// CHECK1-NEXT: [[MUL226:%.*]] = mul i32 [[MUL223]], [[DIV225]]1223// CHECK1-NEXT: [[TMP129:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 41224// CHECK1-NEXT: [[TMP130:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 41225// CHECK1-NEXT: [[SUB227:%.*]] = sub i32 [[TMP129]], [[TMP130]]1226// CHECK1-NEXT: [[SUB228:%.*]] = sub i32 [[SUB227]], 11227// CHECK1-NEXT: [[ADD229:%.*]] = add i32 [[SUB228]], 11228// CHECK1-NEXT: [[DIV230:%.*]] = udiv i32 [[ADD229]], 11229// CHECK1-NEXT: [[MUL231:%.*]] = mul i32 [[MUL226]], [[DIV230]]1230// CHECK1-NEXT: [[CONV232:%.*]] = zext i32 [[MUL231]] to i641231// CHECK1-NEXT: [[DIV233:%.*]] = sdiv i64 [[TMP123]], [[CONV232]]1232// CHECK1-NEXT: [[TMP131:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 41233// CHECK1-NEXT: [[TMP132:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 41234// CHECK1-NEXT: [[SUB234:%.*]] = sub i32 [[TMP131]], [[TMP132]]1235// CHECK1-NEXT: [[SUB235:%.*]] = sub i32 [[SUB234]], 11236// CHECK1-NEXT: [[TMP133:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41237// CHECK1-NEXT: [[ADD236:%.*]] = add i32 [[SUB235]], [[TMP133]]1238// CHECK1-NEXT: [[TMP134:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41239// CHECK1-NEXT: [[DIV237:%.*]] = udiv i32 [[ADD236]], [[TMP134]]1240// CHECK1-NEXT: [[MUL238:%.*]] = mul i32 1, [[DIV237]]1241// CHECK1-NEXT: [[TMP135:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 41242// CHECK1-NEXT: [[SUB239:%.*]] = sub i32 [[TMP135]], -311243// CHECK1-NEXT: [[DIV240:%.*]] = udiv i32 [[SUB239]], 321244// CHECK1-NEXT: [[MUL241:%.*]] = mul i32 [[MUL238]], [[DIV240]]1245// CHECK1-NEXT: [[TMP136:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 41246// CHECK1-NEXT: [[TMP137:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 41247// CHECK1-NEXT: [[SUB242:%.*]] = sub i32 [[TMP136]], [[TMP137]]1248// CHECK1-NEXT: [[SUB243:%.*]] = sub i32 [[SUB242]], 11249// CHECK1-NEXT: [[ADD244:%.*]] = add i32 [[SUB243]], 11250// CHECK1-NEXT: [[DIV245:%.*]] = udiv i32 [[ADD244]], 11251// CHECK1-NEXT: [[MUL246:%.*]] = mul i32 [[MUL241]], [[DIV245]]1252// CHECK1-NEXT: [[CONV247:%.*]] = zext i32 [[MUL246]] to i641253// CHECK1-NEXT: [[MUL248:%.*]] = mul nsw i64 [[DIV233]], [[CONV247]]1254// CHECK1-NEXT: [[SUB249:%.*]] = sub nsw i64 [[TMP122]], [[MUL248]]1255// CHECK1-NEXT: [[TMP138:%.*]] = load i64, ptr [[DOTOMP_IV]], align 81256// CHECK1-NEXT: [[TMP139:%.*]] = load i64, ptr [[DOTOMP_IV]], align 81257// CHECK1-NEXT: [[TMP140:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 41258// CHECK1-NEXT: [[TMP141:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 41259// CHECK1-NEXT: [[SUB250:%.*]] = sub i32 [[TMP140]], [[TMP141]]1260// CHECK1-NEXT: [[SUB251:%.*]] = sub i32 [[SUB250]], 11261// CHECK1-NEXT: [[TMP142:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41262// CHECK1-NEXT: [[ADD252:%.*]] = add i32 [[SUB251]], [[TMP142]]1263// CHECK1-NEXT: [[TMP143:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41264// CHECK1-NEXT: [[DIV253:%.*]] = udiv i32 [[ADD252]], [[TMP143]]1265// CHECK1-NEXT: [[MUL254:%.*]] = mul i32 1, [[DIV253]]1266// CHECK1-NEXT: [[TMP144:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 41267// CHECK1-NEXT: [[SUB255:%.*]] = sub i32 [[TMP144]], -311268// CHECK1-NEXT: [[DIV256:%.*]] = udiv i32 [[SUB255]], 321269// CHECK1-NEXT: [[MUL257:%.*]] = mul i32 [[MUL254]], [[DIV256]]1270// CHECK1-NEXT: [[TMP145:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 41271// CHECK1-NEXT: [[TMP146:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 41272// CHECK1-NEXT: [[SUB258:%.*]] = sub i32 [[TMP145]], [[TMP146]]1273// CHECK1-NEXT: [[SUB259:%.*]] = sub i32 [[SUB258]], 11274// CHECK1-NEXT: [[ADD260:%.*]] = add i32 [[SUB259]], 11275// CHECK1-NEXT: [[DIV261:%.*]] = udiv i32 [[ADD260]], 11276// CHECK1-NEXT: [[MUL262:%.*]] = mul i32 [[MUL257]], [[DIV261]]1277// CHECK1-NEXT: [[CONV263:%.*]] = zext i32 [[MUL262]] to i641278// CHECK1-NEXT: [[DIV264:%.*]] = sdiv i64 [[TMP139]], [[CONV263]]1279// CHECK1-NEXT: [[TMP147:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 41280// CHECK1-NEXT: [[TMP148:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 41281// CHECK1-NEXT: [[SUB265:%.*]] = sub i32 [[TMP147]], [[TMP148]]1282// CHECK1-NEXT: [[SUB266:%.*]] = sub i32 [[SUB265]], 11283// CHECK1-NEXT: [[TMP149:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41284// CHECK1-NEXT: [[ADD267:%.*]] = add i32 [[SUB266]], [[TMP149]]1285// CHECK1-NEXT: [[TMP150:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41286// CHECK1-NEXT: [[DIV268:%.*]] = udiv i32 [[ADD267]], [[TMP150]]1287// CHECK1-NEXT: [[MUL269:%.*]] = mul i32 1, [[DIV268]]1288// CHECK1-NEXT: [[TMP151:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 41289// CHECK1-NEXT: [[SUB270:%.*]] = sub i32 [[TMP151]], -311290// CHECK1-NEXT: [[DIV271:%.*]] = udiv i32 [[SUB270]], 321291// CHECK1-NEXT: [[MUL272:%.*]] = mul i32 [[MUL269]], [[DIV271]]1292// CHECK1-NEXT: [[TMP152:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 41293// CHECK1-NEXT: [[TMP153:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 41294// CHECK1-NEXT: [[SUB273:%.*]] = sub i32 [[TMP152]], [[TMP153]]1295// CHECK1-NEXT: [[SUB274:%.*]] = sub i32 [[SUB273]], 11296// CHECK1-NEXT: [[ADD275:%.*]] = add i32 [[SUB274]], 11297// CHECK1-NEXT: [[DIV276:%.*]] = udiv i32 [[ADD275]], 11298// CHECK1-NEXT: [[MUL277:%.*]] = mul i32 [[MUL272]], [[DIV276]]1299// CHECK1-NEXT: [[CONV278:%.*]] = zext i32 [[MUL277]] to i641300// CHECK1-NEXT: [[MUL279:%.*]] = mul nsw i64 [[DIV264]], [[CONV278]]1301// CHECK1-NEXT: [[SUB280:%.*]] = sub nsw i64 [[TMP138]], [[MUL279]]1302// CHECK1-NEXT: [[TMP154:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 41303// CHECK1-NEXT: [[SUB281:%.*]] = sub i32 [[TMP154]], -311304// CHECK1-NEXT: [[DIV282:%.*]] = udiv i32 [[SUB281]], 321305// CHECK1-NEXT: [[MUL283:%.*]] = mul i32 1, [[DIV282]]1306// CHECK1-NEXT: [[TMP155:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 41307// CHECK1-NEXT: [[TMP156:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 41308// CHECK1-NEXT: [[SUB284:%.*]] = sub i32 [[TMP155]], [[TMP156]]1309// CHECK1-NEXT: [[SUB285:%.*]] = sub i32 [[SUB284]], 11310// CHECK1-NEXT: [[ADD286:%.*]] = add i32 [[SUB285]], 11311// CHECK1-NEXT: [[DIV287:%.*]] = udiv i32 [[ADD286]], 11312// CHECK1-NEXT: [[MUL288:%.*]] = mul i32 [[MUL283]], [[DIV287]]1313// CHECK1-NEXT: [[CONV289:%.*]] = zext i32 [[MUL288]] to i641314// CHECK1-NEXT: [[DIV290:%.*]] = sdiv i64 [[SUB280]], [[CONV289]]1315// CHECK1-NEXT: [[TMP157:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 41316// CHECK1-NEXT: [[SUB291:%.*]] = sub i32 [[TMP157]], -311317// CHECK1-NEXT: [[DIV292:%.*]] = udiv i32 [[SUB291]], 321318// CHECK1-NEXT: [[MUL293:%.*]] = mul i32 1, [[DIV292]]1319// CHECK1-NEXT: [[TMP158:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 41320// CHECK1-NEXT: [[TMP159:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 41321// CHECK1-NEXT: [[SUB294:%.*]] = sub i32 [[TMP158]], [[TMP159]]1322// CHECK1-NEXT: [[SUB295:%.*]] = sub i32 [[SUB294]], 11323// CHECK1-NEXT: [[ADD296:%.*]] = add i32 [[SUB295]], 11324// CHECK1-NEXT: [[DIV297:%.*]] = udiv i32 [[ADD296]], 11325// CHECK1-NEXT: [[MUL298:%.*]] = mul i32 [[MUL293]], [[DIV297]]1326// CHECK1-NEXT: [[CONV299:%.*]] = zext i32 [[MUL298]] to i641327// CHECK1-NEXT: [[MUL300:%.*]] = mul nsw i64 [[DIV290]], [[CONV299]]1328// CHECK1-NEXT: [[SUB301:%.*]] = sub nsw i64 [[SUB249]], [[MUL300]]1329// CHECK1-NEXT: [[TMP160:%.*]] = load i64, ptr [[DOTOMP_IV]], align 81330// CHECK1-NEXT: [[TMP161:%.*]] = load i64, ptr [[DOTOMP_IV]], align 81331// CHECK1-NEXT: [[TMP162:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 41332// CHECK1-NEXT: [[TMP163:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 41333// CHECK1-NEXT: [[SUB302:%.*]] = sub i32 [[TMP162]], [[TMP163]]1334// CHECK1-NEXT: [[SUB303:%.*]] = sub i32 [[SUB302]], 11335// CHECK1-NEXT: [[TMP164:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41336// CHECK1-NEXT: [[ADD304:%.*]] = add i32 [[SUB303]], [[TMP164]]1337// CHECK1-NEXT: [[TMP165:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41338// CHECK1-NEXT: [[DIV305:%.*]] = udiv i32 [[ADD304]], [[TMP165]]1339// CHECK1-NEXT: [[MUL306:%.*]] = mul i32 1, [[DIV305]]1340// CHECK1-NEXT: [[TMP166:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 41341// CHECK1-NEXT: [[SUB307:%.*]] = sub i32 [[TMP166]], -311342// CHECK1-NEXT: [[DIV308:%.*]] = udiv i32 [[SUB307]], 321343// CHECK1-NEXT: [[MUL309:%.*]] = mul i32 [[MUL306]], [[DIV308]]1344// CHECK1-NEXT: [[TMP167:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 41345// CHECK1-NEXT: [[TMP168:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 41346// CHECK1-NEXT: [[SUB310:%.*]] = sub i32 [[TMP167]], [[TMP168]]1347// CHECK1-NEXT: [[SUB311:%.*]] = sub i32 [[SUB310]], 11348// CHECK1-NEXT: [[ADD312:%.*]] = add i32 [[SUB311]], 11349// CHECK1-NEXT: [[DIV313:%.*]] = udiv i32 [[ADD312]], 11350// CHECK1-NEXT: [[MUL314:%.*]] = mul i32 [[MUL309]], [[DIV313]]1351// CHECK1-NEXT: [[CONV315:%.*]] = zext i32 [[MUL314]] to i641352// CHECK1-NEXT: [[DIV316:%.*]] = sdiv i64 [[TMP161]], [[CONV315]]1353// CHECK1-NEXT: [[TMP169:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 41354// CHECK1-NEXT: [[TMP170:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 41355// CHECK1-NEXT: [[SUB317:%.*]] = sub i32 [[TMP169]], [[TMP170]]1356// CHECK1-NEXT: [[SUB318:%.*]] = sub i32 [[SUB317]], 11357// CHECK1-NEXT: [[TMP171:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41358// CHECK1-NEXT: [[ADD319:%.*]] = add i32 [[SUB318]], [[TMP171]]1359// CHECK1-NEXT: [[TMP172:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41360// CHECK1-NEXT: [[DIV320:%.*]] = udiv i32 [[ADD319]], [[TMP172]]1361// CHECK1-NEXT: [[MUL321:%.*]] = mul i32 1, [[DIV320]]1362// CHECK1-NEXT: [[TMP173:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 41363// CHECK1-NEXT: [[SUB322:%.*]] = sub i32 [[TMP173]], -311364// CHECK1-NEXT: [[DIV323:%.*]] = udiv i32 [[SUB322]], 321365// CHECK1-NEXT: [[MUL324:%.*]] = mul i32 [[MUL321]], [[DIV323]]1366// CHECK1-NEXT: [[TMP174:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 41367// CHECK1-NEXT: [[TMP175:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 41368// CHECK1-NEXT: [[SUB325:%.*]] = sub i32 [[TMP174]], [[TMP175]]1369// CHECK1-NEXT: [[SUB326:%.*]] = sub i32 [[SUB325]], 11370// CHECK1-NEXT: [[ADD327:%.*]] = add i32 [[SUB326]], 11371// CHECK1-NEXT: [[DIV328:%.*]] = udiv i32 [[ADD327]], 11372// CHECK1-NEXT: [[MUL329:%.*]] = mul i32 [[MUL324]], [[DIV328]]1373// CHECK1-NEXT: [[CONV330:%.*]] = zext i32 [[MUL329]] to i641374// CHECK1-NEXT: [[MUL331:%.*]] = mul nsw i64 [[DIV316]], [[CONV330]]1375// CHECK1-NEXT: [[SUB332:%.*]] = sub nsw i64 [[TMP160]], [[MUL331]]1376// CHECK1-NEXT: [[TMP176:%.*]] = load i64, ptr [[DOTOMP_IV]], align 81377// CHECK1-NEXT: [[TMP177:%.*]] = load i64, ptr [[DOTOMP_IV]], align 81378// CHECK1-NEXT: [[TMP178:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 41379// CHECK1-NEXT: [[TMP179:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 41380// CHECK1-NEXT: [[SUB333:%.*]] = sub i32 [[TMP178]], [[TMP179]]1381// CHECK1-NEXT: [[SUB334:%.*]] = sub i32 [[SUB333]], 11382// CHECK1-NEXT: [[TMP180:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41383// CHECK1-NEXT: [[ADD335:%.*]] = add i32 [[SUB334]], [[TMP180]]1384// CHECK1-NEXT: [[TMP181:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41385// CHECK1-NEXT: [[DIV336:%.*]] = udiv i32 [[ADD335]], [[TMP181]]1386// CHECK1-NEXT: [[MUL337:%.*]] = mul i32 1, [[DIV336]]1387// CHECK1-NEXT: [[TMP182:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 41388// CHECK1-NEXT: [[SUB338:%.*]] = sub i32 [[TMP182]], -311389// CHECK1-NEXT: [[DIV339:%.*]] = udiv i32 [[SUB338]], 321390// CHECK1-NEXT: [[MUL340:%.*]] = mul i32 [[MUL337]], [[DIV339]]1391// CHECK1-NEXT: [[TMP183:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 41392// CHECK1-NEXT: [[TMP184:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 41393// CHECK1-NEXT: [[SUB341:%.*]] = sub i32 [[TMP183]], [[TMP184]]1394// CHECK1-NEXT: [[SUB342:%.*]] = sub i32 [[SUB341]], 11395// CHECK1-NEXT: [[ADD343:%.*]] = add i32 [[SUB342]], 11396// CHECK1-NEXT: [[DIV344:%.*]] = udiv i32 [[ADD343]], 11397// CHECK1-NEXT: [[MUL345:%.*]] = mul i32 [[MUL340]], [[DIV344]]1398// CHECK1-NEXT: [[CONV346:%.*]] = zext i32 [[MUL345]] to i641399// CHECK1-NEXT: [[DIV347:%.*]] = sdiv i64 [[TMP177]], [[CONV346]]1400// CHECK1-NEXT: [[TMP185:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 41401// CHECK1-NEXT: [[TMP186:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 41402// CHECK1-NEXT: [[SUB348:%.*]] = sub i32 [[TMP185]], [[TMP186]]1403// CHECK1-NEXT: [[SUB349:%.*]] = sub i32 [[SUB348]], 11404// CHECK1-NEXT: [[TMP187:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41405// CHECK1-NEXT: [[ADD350:%.*]] = add i32 [[SUB349]], [[TMP187]]1406// CHECK1-NEXT: [[TMP188:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41407// CHECK1-NEXT: [[DIV351:%.*]] = udiv i32 [[ADD350]], [[TMP188]]1408// CHECK1-NEXT: [[MUL352:%.*]] = mul i32 1, [[DIV351]]1409// CHECK1-NEXT: [[TMP189:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 41410// CHECK1-NEXT: [[SUB353:%.*]] = sub i32 [[TMP189]], -311411// CHECK1-NEXT: [[DIV354:%.*]] = udiv i32 [[SUB353]], 321412// CHECK1-NEXT: [[MUL355:%.*]] = mul i32 [[MUL352]], [[DIV354]]1413// CHECK1-NEXT: [[TMP190:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 41414// CHECK1-NEXT: [[TMP191:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 41415// CHECK1-NEXT: [[SUB356:%.*]] = sub i32 [[TMP190]], [[TMP191]]1416// CHECK1-NEXT: [[SUB357:%.*]] = sub i32 [[SUB356]], 11417// CHECK1-NEXT: [[ADD358:%.*]] = add i32 [[SUB357]], 11418// CHECK1-NEXT: [[DIV359:%.*]] = udiv i32 [[ADD358]], 11419// CHECK1-NEXT: [[MUL360:%.*]] = mul i32 [[MUL355]], [[DIV359]]1420// CHECK1-NEXT: [[CONV361:%.*]] = zext i32 [[MUL360]] to i641421// CHECK1-NEXT: [[MUL362:%.*]] = mul nsw i64 [[DIV347]], [[CONV361]]1422// CHECK1-NEXT: [[SUB363:%.*]] = sub nsw i64 [[TMP176]], [[MUL362]]1423// CHECK1-NEXT: [[TMP192:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 41424// CHECK1-NEXT: [[SUB364:%.*]] = sub i32 [[TMP192]], -311425// CHECK1-NEXT: [[DIV365:%.*]] = udiv i32 [[SUB364]], 321426// CHECK1-NEXT: [[MUL366:%.*]] = mul i32 1, [[DIV365]]1427// CHECK1-NEXT: [[TMP193:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 41428// CHECK1-NEXT: [[TMP194:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 41429// CHECK1-NEXT: [[SUB367:%.*]] = sub i32 [[TMP193]], [[TMP194]]1430// CHECK1-NEXT: [[SUB368:%.*]] = sub i32 [[SUB367]], 11431// CHECK1-NEXT: [[ADD369:%.*]] = add i32 [[SUB368]], 11432// CHECK1-NEXT: [[DIV370:%.*]] = udiv i32 [[ADD369]], 11433// CHECK1-NEXT: [[MUL371:%.*]] = mul i32 [[MUL366]], [[DIV370]]1434// CHECK1-NEXT: [[CONV372:%.*]] = zext i32 [[MUL371]] to i641435// CHECK1-NEXT: [[DIV373:%.*]] = sdiv i64 [[SUB363]], [[CONV372]]1436// CHECK1-NEXT: [[TMP195:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 41437// CHECK1-NEXT: [[SUB374:%.*]] = sub i32 [[TMP195]], -311438// CHECK1-NEXT: [[DIV375:%.*]] = udiv i32 [[SUB374]], 321439// CHECK1-NEXT: [[MUL376:%.*]] = mul i32 1, [[DIV375]]1440// CHECK1-NEXT: [[TMP196:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 41441// CHECK1-NEXT: [[TMP197:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 41442// CHECK1-NEXT: [[SUB377:%.*]] = sub i32 [[TMP196]], [[TMP197]]1443// CHECK1-NEXT: [[SUB378:%.*]] = sub i32 [[SUB377]], 11444// CHECK1-NEXT: [[ADD379:%.*]] = add i32 [[SUB378]], 11445// CHECK1-NEXT: [[DIV380:%.*]] = udiv i32 [[ADD379]], 11446// CHECK1-NEXT: [[MUL381:%.*]] = mul i32 [[MUL376]], [[DIV380]]1447// CHECK1-NEXT: [[CONV382:%.*]] = zext i32 [[MUL381]] to i641448// CHECK1-NEXT: [[MUL383:%.*]] = mul nsw i64 [[DIV373]], [[CONV382]]1449// CHECK1-NEXT: [[SUB384:%.*]] = sub nsw i64 [[SUB332]], [[MUL383]]1450// CHECK1-NEXT: [[TMP198:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 41451// CHECK1-NEXT: [[TMP199:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 41452// CHECK1-NEXT: [[SUB385:%.*]] = sub i32 [[TMP198]], [[TMP199]]1453// CHECK1-NEXT: [[SUB386:%.*]] = sub i32 [[SUB385]], 11454// CHECK1-NEXT: [[ADD387:%.*]] = add i32 [[SUB386]], 11455// CHECK1-NEXT: [[DIV388:%.*]] = udiv i32 [[ADD387]], 11456// CHECK1-NEXT: [[MUL389:%.*]] = mul i32 1, [[DIV388]]1457// CHECK1-NEXT: [[CONV390:%.*]] = zext i32 [[MUL389]] to i641458// CHECK1-NEXT: [[DIV391:%.*]] = sdiv i64 [[SUB384]], [[CONV390]]1459// CHECK1-NEXT: [[TMP200:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 41460// CHECK1-NEXT: [[TMP201:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 41461// CHECK1-NEXT: [[SUB392:%.*]] = sub i32 [[TMP200]], [[TMP201]]1462// CHECK1-NEXT: [[SUB393:%.*]] = sub i32 [[SUB392]], 11463// CHECK1-NEXT: [[ADD394:%.*]] = add i32 [[SUB393]], 11464// CHECK1-NEXT: [[DIV395:%.*]] = udiv i32 [[ADD394]], 11465// CHECK1-NEXT: [[MUL396:%.*]] = mul i32 1, [[DIV395]]1466// CHECK1-NEXT: [[CONV397:%.*]] = zext i32 [[MUL396]] to i641467// CHECK1-NEXT: [[MUL398:%.*]] = mul nsw i64 [[DIV391]], [[CONV397]]1468// CHECK1-NEXT: [[SUB399:%.*]] = sub nsw i64 [[SUB301]], [[MUL398]]1469// CHECK1-NEXT: [[MUL400:%.*]] = mul nsw i64 [[SUB399]], 11470// CHECK1-NEXT: [[ADD401:%.*]] = add nsw i64 [[CONV218]], [[MUL400]]1471// CHECK1-NEXT: [[CONV402:%.*]] = trunc i64 [[ADD401]] to i321472// CHECK1-NEXT: store i32 [[CONV402]], ptr [[DOTTILE_0_IV_K52]], align 41473// CHECK1-NEXT: [[TMP202:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_8]], align 41474// CHECK1-NEXT: [[TMP203:%.*]] = load i32, ptr [[DOTTILE_0_IV_K52]], align 41475// CHECK1-NEXT: [[TMP204:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 41476// CHECK1-NEXT: [[MUL403:%.*]] = mul i32 [[TMP203]], [[TMP204]]1477// CHECK1-NEXT: [[ADD404:%.*]] = add i32 [[TMP202]], [[MUL403]]1478// CHECK1-NEXT: store i32 [[ADD404]], ptr [[K]], align 41479// CHECK1-NEXT: [[TMP205:%.*]] = load i32, ptr [[I49]], align 41480// CHECK1-NEXT: [[TMP206:%.*]] = load i32, ptr [[J50]], align 41481// CHECK1-NEXT: [[TMP207:%.*]] = load i32, ptr [[K]], align 41482// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP205]], i32 noundef [[TMP206]], i32 noundef [[TMP207]])1483// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1484// CHECK1: omp.body.continue:1485// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1486// CHECK1: omp.inner.for.inc:1487// CHECK1-NEXT: [[TMP208:%.*]] = load i64, ptr [[DOTOMP_IV]], align 81488// CHECK1-NEXT: [[ADD405:%.*]] = add nsw i64 [[TMP208]], 11489// CHECK1-NEXT: store i64 [[ADD405]], ptr [[DOTOMP_IV]], align 81490// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]1491// CHECK1: omp.inner.for.end:1492// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]1493// CHECK1: omp.loop.exit:1494// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]])1495// CHECK1-NEXT: br label [[OMP_PRECOND_END]]1496// CHECK1: omp.precond.end:1497// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]])1498// CHECK1-NEXT: ret void1499//1500//1501// CHECK1-LABEL: define {{[^@]+}}@_Z4foo8ILi64EEviii1502// CHECK1-SAME: (i32 noundef [[START:%.*]], i32 noundef [[END:%.*]], i32 noundef [[STEP:%.*]]) #[[ATTR0]] comdat {1503// CHECK1-NEXT: entry:1504// CHECK1-NEXT: [[START_ADDR:%.*]] = alloca i32, align 41505// CHECK1-NEXT: [[END_ADDR:%.*]] = alloca i32, align 41506// CHECK1-NEXT: [[STEP_ADDR:%.*]] = alloca i32, align 41507// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 81508// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 41509// CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 41510// CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 41511// CHECK1-NEXT: [[_TMP3:%.*]] = alloca i32, align 41512// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 41513// CHECK1-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 41514// CHECK1-NEXT: [[DOTNEW_STEP:%.*]] = alloca i32, align 41515// CHECK1-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 41516// CHECK1-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i32, align 41517// CHECK1-NEXT: [[DOTNEW_STEP7:%.*]] = alloca i32, align 41518// CHECK1-NEXT: [[K:%.*]] = alloca i32, align 41519// CHECK1-NEXT: [[DOTCAPTURE_EXPR_8:%.*]] = alloca i32, align 41520// CHECK1-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 41521// CHECK1-NEXT: [[DOTNEW_STEP10:%.*]] = alloca i32, align 41522// CHECK1-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 41523// CHECK1-NEXT: [[DOTCAPTURE_EXPR_14:%.*]] = alloca i32, align 41524// CHECK1-NEXT: [[DOTCAPTURE_EXPR_16:%.*]] = alloca i32, align 41525// CHECK1-NEXT: [[DOTCAPTURE_EXPR_17:%.*]] = alloca i32, align 41526// CHECK1-NEXT: [[DOTCAPTURE_EXPR_22:%.*]] = alloca i64, align 81527// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 41528// CHECK1-NEXT: [[J:%.*]] = alloca i32, align 41529// CHECK1-NEXT: [[DOTFLOOR_0_IV_K:%.*]] = alloca i32, align 41530// CHECK1-NEXT: [[DOTTILE_0_IV_K:%.*]] = alloca i32, align 41531// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 81532// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 81533// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 81534// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41535// CHECK1-NEXT: [[I49:%.*]] = alloca i32, align 41536// CHECK1-NEXT: [[J50:%.*]] = alloca i32, align 41537// CHECK1-NEXT: [[DOTFLOOR_0_IV_K51:%.*]] = alloca i32, align 41538// CHECK1-NEXT: [[DOTTILE_0_IV_K52:%.*]] = alloca i32, align 41539// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])1540// CHECK1-NEXT: store i32 [[START]], ptr [[START_ADDR]], align 41541// CHECK1-NEXT: store i32 [[END]], ptr [[END_ADDR]], align 41542// CHECK1-NEXT: store i32 [[STEP]], ptr [[STEP_ADDR]], align 41543// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[START_ADDR]], align 41544// CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 41545// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[END_ADDR]], align 41546// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_4]], align 41547// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[STEP_ADDR]], align 41548// CHECK1-NEXT: store i32 [[TMP3]], ptr [[DOTNEW_STEP]], align 41549// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[START_ADDR]], align 41550// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_5]], align 41551// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[END_ADDR]], align 41552// CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_6]], align 41553// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[STEP_ADDR]], align 41554// CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTNEW_STEP7]], align 41555// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[START_ADDR]], align 41556// CHECK1-NEXT: store i32 [[TMP7]], ptr [[K]], align 41557// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[START_ADDR]], align 41558// CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTCAPTURE_EXPR_8]], align 41559// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[END_ADDR]], align 41560// CHECK1-NEXT: store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR_9]], align 41561// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[STEP_ADDR]], align 41562// CHECK1-NEXT: store i32 [[TMP10]], ptr [[DOTNEW_STEP10]], align 41563// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_9]], align 41564// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_8]], align 41565// CHECK1-NEXT: [[SUB:%.*]] = sub i32 [[TMP11]], [[TMP12]]1566// CHECK1-NEXT: [[SUB12:%.*]] = sub i32 [[SUB]], 11567// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 41568// CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB12]], [[TMP13]]1569// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 41570// CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], [[TMP14]]1571// CHECK1-NEXT: [[SUB13:%.*]] = sub i32 [[DIV]], 11572// CHECK1-NEXT: store i32 [[SUB13]], ptr [[DOTCAPTURE_EXPR_11]], align 41573// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 41574// CHECK1-NEXT: [[ADD15:%.*]] = add i32 [[TMP15]], 11575// CHECK1-NEXT: store i32 [[ADD15]], ptr [[DOTCAPTURE_EXPR_14]], align 41576// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[_TMP2]], align 41577// CHECK1-NEXT: store i32 [[TMP16]], ptr [[DOTCAPTURE_EXPR_16]], align 41578// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 41579// CHECK1-NEXT: [[ADD18:%.*]] = add i32 [[TMP17]], 11580// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[_TMP2]], align 41581// CHECK1-NEXT: [[ADD19:%.*]] = add i32 [[TMP18]], 641582// CHECK1-NEXT: [[CMP:%.*]] = icmp ult i32 [[ADD18]], [[ADD19]]1583// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1584// CHECK1: cond.true:1585// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 41586// CHECK1-NEXT: [[ADD20:%.*]] = add i32 [[TMP19]], 11587// CHECK1-NEXT: br label [[COND_END:%.*]]1588// CHECK1: cond.false:1589// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[_TMP2]], align 41590// CHECK1-NEXT: [[ADD21:%.*]] = add i32 [[TMP20]], 641591// CHECK1-NEXT: br label [[COND_END]]1592// CHECK1: cond.end:1593// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[ADD20]], [[COND_TRUE]] ], [ [[ADD21]], [[COND_FALSE]] ]1594// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTCAPTURE_EXPR_17]], align 41595// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 41596// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41597// CHECK1-NEXT: [[SUB23:%.*]] = sub i32 [[TMP21]], [[TMP22]]1598// CHECK1-NEXT: [[SUB24:%.*]] = sub i32 [[SUB23]], 11599// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 41600// CHECK1-NEXT: [[ADD25:%.*]] = add i32 [[SUB24]], [[TMP23]]1601// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 41602// CHECK1-NEXT: [[DIV26:%.*]] = udiv i32 [[ADD25]], [[TMP24]]1603// CHECK1-NEXT: [[CONV:%.*]] = zext i32 [[DIV26]] to i641604// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 41605// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 41606// CHECK1-NEXT: [[SUB27:%.*]] = sub i32 [[TMP25]], [[TMP26]]1607// CHECK1-NEXT: [[SUB28:%.*]] = sub i32 [[SUB27]], 11608// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41609// CHECK1-NEXT: [[ADD29:%.*]] = add i32 [[SUB28]], [[TMP27]]1610// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41611// CHECK1-NEXT: [[DIV30:%.*]] = udiv i32 [[ADD29]], [[TMP28]]1612// CHECK1-NEXT: [[CONV31:%.*]] = zext i32 [[DIV30]] to i641613// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV31]]1614// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 41615// CHECK1-NEXT: [[SUB32:%.*]] = sub i32 [[TMP29]], -631616// CHECK1-NEXT: [[DIV33:%.*]] = udiv i32 [[SUB32]], 641617// CHECK1-NEXT: [[CONV34:%.*]] = zext i32 [[DIV33]] to i641618// CHECK1-NEXT: [[MUL35:%.*]] = mul nsw i64 [[MUL]], [[CONV34]]1619// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 41620// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 41621// CHECK1-NEXT: [[SUB36:%.*]] = sub i32 [[TMP30]], [[TMP31]]1622// CHECK1-NEXT: [[SUB37:%.*]] = sub i32 [[SUB36]], 11623// CHECK1-NEXT: [[ADD38:%.*]] = add i32 [[SUB37]], 11624// CHECK1-NEXT: [[DIV39:%.*]] = udiv i32 [[ADD38]], 11625// CHECK1-NEXT: [[CONV40:%.*]] = zext i32 [[DIV39]] to i641626// CHECK1-NEXT: [[MUL41:%.*]] = mul nsw i64 [[MUL35]], [[CONV40]]1627// CHECK1-NEXT: [[SUB42:%.*]] = sub nsw i64 [[MUL41]], 11628// CHECK1-NEXT: store i64 [[SUB42]], ptr [[DOTCAPTURE_EXPR_22]], align 81629// CHECK1-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41630// CHECK1-NEXT: store i32 [[TMP32]], ptr [[I]], align 41631// CHECK1-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 41632// CHECK1-NEXT: store i32 [[TMP33]], ptr [[J]], align 41633// CHECK1-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV_K]], align 41634// CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 41635// CHECK1-NEXT: store i32 [[TMP34]], ptr [[DOTTILE_0_IV_K]], align 41636// CHECK1-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41637// CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 41638// CHECK1-NEXT: [[CMP43:%.*]] = icmp slt i32 [[TMP35]], [[TMP36]]1639// CHECK1-NEXT: br i1 [[CMP43]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]1640// CHECK1: land.lhs.true:1641// CHECK1-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 41642// CHECK1-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 41643// CHECK1-NEXT: [[CMP44:%.*]] = icmp slt i32 [[TMP37]], [[TMP38]]1644// CHECK1-NEXT: br i1 [[CMP44]], label [[LAND_LHS_TRUE45:%.*]], label [[OMP_PRECOND_END]]1645// CHECK1: land.lhs.true45:1646// CHECK1-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 41647// CHECK1-NEXT: [[CMP46:%.*]] = icmp ult i32 0, [[TMP39]]1648// CHECK1-NEXT: br i1 [[CMP46]], label [[LAND_LHS_TRUE47:%.*]], label [[OMP_PRECOND_END]]1649// CHECK1: land.lhs.true47:1650// CHECK1-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 41651// CHECK1-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 41652// CHECK1-NEXT: [[CMP48:%.*]] = icmp ult i32 [[TMP40]], [[TMP41]]1653// CHECK1-NEXT: br i1 [[CMP48]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]1654// CHECK1: omp.precond.then:1655// CHECK1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 81656// CHECK1-NEXT: [[TMP42:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 81657// CHECK1-NEXT: store i64 [[TMP42]], ptr [[DOTOMP_UB]], align 81658// CHECK1-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 81659// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41660// CHECK1-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)1661// CHECK1-NEXT: [[TMP43:%.*]] = load i64, ptr [[DOTOMP_UB]], align 81662// CHECK1-NEXT: [[TMP44:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 81663// CHECK1-NEXT: [[CMP53:%.*]] = icmp sgt i64 [[TMP43]], [[TMP44]]1664// CHECK1-NEXT: br i1 [[CMP53]], label [[COND_TRUE54:%.*]], label [[COND_FALSE55:%.*]]1665// CHECK1: cond.true54:1666// CHECK1-NEXT: [[TMP45:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 81667// CHECK1-NEXT: br label [[COND_END56:%.*]]1668// CHECK1: cond.false55:1669// CHECK1-NEXT: [[TMP46:%.*]] = load i64, ptr [[DOTOMP_UB]], align 81670// CHECK1-NEXT: br label [[COND_END56]]1671// CHECK1: cond.end56:1672// CHECK1-NEXT: [[COND57:%.*]] = phi i64 [ [[TMP45]], [[COND_TRUE54]] ], [ [[TMP46]], [[COND_FALSE55]] ]1673// CHECK1-NEXT: store i64 [[COND57]], ptr [[DOTOMP_UB]], align 81674// CHECK1-NEXT: [[TMP47:%.*]] = load i64, ptr [[DOTOMP_LB]], align 81675// CHECK1-NEXT: store i64 [[TMP47]], ptr [[DOTOMP_IV]], align 81676// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1677// CHECK1: omp.inner.for.cond:1678// CHECK1-NEXT: [[TMP48:%.*]] = load i64, ptr [[DOTOMP_IV]], align 81679// CHECK1-NEXT: [[TMP49:%.*]] = load i64, ptr [[DOTOMP_UB]], align 81680// CHECK1-NEXT: [[CMP58:%.*]] = icmp sle i64 [[TMP48]], [[TMP49]]1681// CHECK1-NEXT: br i1 [[CMP58]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1682// CHECK1: omp.inner.for.body:1683// CHECK1-NEXT: [[TMP50:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41684// CHECK1-NEXT: [[CONV59:%.*]] = sext i32 [[TMP50]] to i641685// CHECK1-NEXT: [[TMP51:%.*]] = load i64, ptr [[DOTOMP_IV]], align 81686// CHECK1-NEXT: [[TMP52:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 41687// CHECK1-NEXT: [[TMP53:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 41688// CHECK1-NEXT: [[SUB60:%.*]] = sub i32 [[TMP52]], [[TMP53]]1689// CHECK1-NEXT: [[SUB61:%.*]] = sub i32 [[SUB60]], 11690// CHECK1-NEXT: [[TMP54:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41691// CHECK1-NEXT: [[ADD62:%.*]] = add i32 [[SUB61]], [[TMP54]]1692// CHECK1-NEXT: [[TMP55:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41693// CHECK1-NEXT: [[DIV63:%.*]] = udiv i32 [[ADD62]], [[TMP55]]1694// CHECK1-NEXT: [[MUL64:%.*]] = mul i32 1, [[DIV63]]1695// CHECK1-NEXT: [[TMP56:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 41696// CHECK1-NEXT: [[SUB65:%.*]] = sub i32 [[TMP56]], -631697// CHECK1-NEXT: [[DIV66:%.*]] = udiv i32 [[SUB65]], 641698// CHECK1-NEXT: [[MUL67:%.*]] = mul i32 [[MUL64]], [[DIV66]]1699// CHECK1-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 41700// CHECK1-NEXT: [[TMP58:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 41701// CHECK1-NEXT: [[SUB68:%.*]] = sub i32 [[TMP57]], [[TMP58]]1702// CHECK1-NEXT: [[SUB69:%.*]] = sub i32 [[SUB68]], 11703// CHECK1-NEXT: [[ADD70:%.*]] = add i32 [[SUB69]], 11704// CHECK1-NEXT: [[DIV71:%.*]] = udiv i32 [[ADD70]], 11705// CHECK1-NEXT: [[MUL72:%.*]] = mul i32 [[MUL67]], [[DIV71]]1706// CHECK1-NEXT: [[CONV73:%.*]] = zext i32 [[MUL72]] to i641707// CHECK1-NEXT: [[DIV74:%.*]] = sdiv i64 [[TMP51]], [[CONV73]]1708// CHECK1-NEXT: [[TMP59:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 41709// CHECK1-NEXT: [[CONV75:%.*]] = sext i32 [[TMP59]] to i641710// CHECK1-NEXT: [[MUL76:%.*]] = mul nsw i64 [[DIV74]], [[CONV75]]1711// CHECK1-NEXT: [[ADD77:%.*]] = add nsw i64 [[CONV59]], [[MUL76]]1712// CHECK1-NEXT: [[CONV78:%.*]] = trunc i64 [[ADD77]] to i321713// CHECK1-NEXT: store i32 [[CONV78]], ptr [[I49]], align 41714// CHECK1-NEXT: [[TMP60:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 41715// CHECK1-NEXT: [[CONV79:%.*]] = sext i32 [[TMP60]] to i641716// CHECK1-NEXT: [[TMP61:%.*]] = load i64, ptr [[DOTOMP_IV]], align 81717// CHECK1-NEXT: [[TMP62:%.*]] = load i64, ptr [[DOTOMP_IV]], align 81718// CHECK1-NEXT: [[TMP63:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 41719// CHECK1-NEXT: [[TMP64:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 41720// CHECK1-NEXT: [[SUB80:%.*]] = sub i32 [[TMP63]], [[TMP64]]1721// CHECK1-NEXT: [[SUB81:%.*]] = sub i32 [[SUB80]], 11722// CHECK1-NEXT: [[TMP65:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41723// CHECK1-NEXT: [[ADD82:%.*]] = add i32 [[SUB81]], [[TMP65]]1724// CHECK1-NEXT: [[TMP66:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41725// CHECK1-NEXT: [[DIV83:%.*]] = udiv i32 [[ADD82]], [[TMP66]]1726// CHECK1-NEXT: [[MUL84:%.*]] = mul i32 1, [[DIV83]]1727// CHECK1-NEXT: [[TMP67:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 41728// CHECK1-NEXT: [[SUB85:%.*]] = sub i32 [[TMP67]], -631729// CHECK1-NEXT: [[DIV86:%.*]] = udiv i32 [[SUB85]], 641730// CHECK1-NEXT: [[MUL87:%.*]] = mul i32 [[MUL84]], [[DIV86]]1731// CHECK1-NEXT: [[TMP68:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 41732// CHECK1-NEXT: [[TMP69:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 41733// CHECK1-NEXT: [[SUB88:%.*]] = sub i32 [[TMP68]], [[TMP69]]1734// CHECK1-NEXT: [[SUB89:%.*]] = sub i32 [[SUB88]], 11735// CHECK1-NEXT: [[ADD90:%.*]] = add i32 [[SUB89]], 11736// CHECK1-NEXT: [[DIV91:%.*]] = udiv i32 [[ADD90]], 11737// CHECK1-NEXT: [[MUL92:%.*]] = mul i32 [[MUL87]], [[DIV91]]1738// CHECK1-NEXT: [[CONV93:%.*]] = zext i32 [[MUL92]] to i641739// CHECK1-NEXT: [[DIV94:%.*]] = sdiv i64 [[TMP62]], [[CONV93]]1740// CHECK1-NEXT: [[TMP70:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 41741// CHECK1-NEXT: [[TMP71:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 41742// CHECK1-NEXT: [[SUB95:%.*]] = sub i32 [[TMP70]], [[TMP71]]1743// CHECK1-NEXT: [[SUB96:%.*]] = sub i32 [[SUB95]], 11744// CHECK1-NEXT: [[TMP72:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41745// CHECK1-NEXT: [[ADD97:%.*]] = add i32 [[SUB96]], [[TMP72]]1746// CHECK1-NEXT: [[TMP73:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41747// CHECK1-NEXT: [[DIV98:%.*]] = udiv i32 [[ADD97]], [[TMP73]]1748// CHECK1-NEXT: [[MUL99:%.*]] = mul i32 1, [[DIV98]]1749// CHECK1-NEXT: [[TMP74:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 41750// CHECK1-NEXT: [[SUB100:%.*]] = sub i32 [[TMP74]], -631751// CHECK1-NEXT: [[DIV101:%.*]] = udiv i32 [[SUB100]], 641752// CHECK1-NEXT: [[MUL102:%.*]] = mul i32 [[MUL99]], [[DIV101]]1753// CHECK1-NEXT: [[TMP75:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 41754// CHECK1-NEXT: [[TMP76:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 41755// CHECK1-NEXT: [[SUB103:%.*]] = sub i32 [[TMP75]], [[TMP76]]1756// CHECK1-NEXT: [[SUB104:%.*]] = sub i32 [[SUB103]], 11757// CHECK1-NEXT: [[ADD105:%.*]] = add i32 [[SUB104]], 11758// CHECK1-NEXT: [[DIV106:%.*]] = udiv i32 [[ADD105]], 11759// CHECK1-NEXT: [[MUL107:%.*]] = mul i32 [[MUL102]], [[DIV106]]1760// CHECK1-NEXT: [[CONV108:%.*]] = zext i32 [[MUL107]] to i641761// CHECK1-NEXT: [[MUL109:%.*]] = mul nsw i64 [[DIV94]], [[CONV108]]1762// CHECK1-NEXT: [[SUB110:%.*]] = sub nsw i64 [[TMP61]], [[MUL109]]1763// CHECK1-NEXT: [[TMP77:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 41764// CHECK1-NEXT: [[SUB111:%.*]] = sub i32 [[TMP77]], -631765// CHECK1-NEXT: [[DIV112:%.*]] = udiv i32 [[SUB111]], 641766// CHECK1-NEXT: [[MUL113:%.*]] = mul i32 1, [[DIV112]]1767// CHECK1-NEXT: [[TMP78:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 41768// CHECK1-NEXT: [[TMP79:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 41769// CHECK1-NEXT: [[SUB114:%.*]] = sub i32 [[TMP78]], [[TMP79]]1770// CHECK1-NEXT: [[SUB115:%.*]] = sub i32 [[SUB114]], 11771// CHECK1-NEXT: [[ADD116:%.*]] = add i32 [[SUB115]], 11772// CHECK1-NEXT: [[DIV117:%.*]] = udiv i32 [[ADD116]], 11773// CHECK1-NEXT: [[MUL118:%.*]] = mul i32 [[MUL113]], [[DIV117]]1774// CHECK1-NEXT: [[CONV119:%.*]] = zext i32 [[MUL118]] to i641775// CHECK1-NEXT: [[DIV120:%.*]] = sdiv i64 [[SUB110]], [[CONV119]]1776// CHECK1-NEXT: [[TMP80:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41777// CHECK1-NEXT: [[CONV121:%.*]] = sext i32 [[TMP80]] to i641778// CHECK1-NEXT: [[MUL122:%.*]] = mul nsw i64 [[DIV120]], [[CONV121]]1779// CHECK1-NEXT: [[ADD123:%.*]] = add nsw i64 [[CONV79]], [[MUL122]]1780// CHECK1-NEXT: [[CONV124:%.*]] = trunc i64 [[ADD123]] to i321781// CHECK1-NEXT: store i32 [[CONV124]], ptr [[J50]], align 41782// CHECK1-NEXT: [[TMP81:%.*]] = load i64, ptr [[DOTOMP_IV]], align 81783// CHECK1-NEXT: [[TMP82:%.*]] = load i64, ptr [[DOTOMP_IV]], align 81784// CHECK1-NEXT: [[TMP83:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 41785// CHECK1-NEXT: [[TMP84:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 41786// CHECK1-NEXT: [[SUB125:%.*]] = sub i32 [[TMP83]], [[TMP84]]1787// CHECK1-NEXT: [[SUB126:%.*]] = sub i32 [[SUB125]], 11788// CHECK1-NEXT: [[TMP85:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41789// CHECK1-NEXT: [[ADD127:%.*]] = add i32 [[SUB126]], [[TMP85]]1790// CHECK1-NEXT: [[TMP86:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41791// CHECK1-NEXT: [[DIV128:%.*]] = udiv i32 [[ADD127]], [[TMP86]]1792// CHECK1-NEXT: [[MUL129:%.*]] = mul i32 1, [[DIV128]]1793// CHECK1-NEXT: [[TMP87:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 41794// CHECK1-NEXT: [[SUB130:%.*]] = sub i32 [[TMP87]], -631795// CHECK1-NEXT: [[DIV131:%.*]] = udiv i32 [[SUB130]], 641796// CHECK1-NEXT: [[MUL132:%.*]] = mul i32 [[MUL129]], [[DIV131]]1797// CHECK1-NEXT: [[TMP88:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 41798// CHECK1-NEXT: [[TMP89:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 41799// CHECK1-NEXT: [[SUB133:%.*]] = sub i32 [[TMP88]], [[TMP89]]1800// CHECK1-NEXT: [[SUB134:%.*]] = sub i32 [[SUB133]], 11801// CHECK1-NEXT: [[ADD135:%.*]] = add i32 [[SUB134]], 11802// CHECK1-NEXT: [[DIV136:%.*]] = udiv i32 [[ADD135]], 11803// CHECK1-NEXT: [[MUL137:%.*]] = mul i32 [[MUL132]], [[DIV136]]1804// CHECK1-NEXT: [[CONV138:%.*]] = zext i32 [[MUL137]] to i641805// CHECK1-NEXT: [[DIV139:%.*]] = sdiv i64 [[TMP82]], [[CONV138]]1806// CHECK1-NEXT: [[TMP90:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 41807// CHECK1-NEXT: [[TMP91:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 41808// CHECK1-NEXT: [[SUB140:%.*]] = sub i32 [[TMP90]], [[TMP91]]1809// CHECK1-NEXT: [[SUB141:%.*]] = sub i32 [[SUB140]], 11810// CHECK1-NEXT: [[TMP92:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41811// CHECK1-NEXT: [[ADD142:%.*]] = add i32 [[SUB141]], [[TMP92]]1812// CHECK1-NEXT: [[TMP93:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41813// CHECK1-NEXT: [[DIV143:%.*]] = udiv i32 [[ADD142]], [[TMP93]]1814// CHECK1-NEXT: [[MUL144:%.*]] = mul i32 1, [[DIV143]]1815// CHECK1-NEXT: [[TMP94:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 41816// CHECK1-NEXT: [[SUB145:%.*]] = sub i32 [[TMP94]], -631817// CHECK1-NEXT: [[DIV146:%.*]] = udiv i32 [[SUB145]], 641818// CHECK1-NEXT: [[MUL147:%.*]] = mul i32 [[MUL144]], [[DIV146]]1819// CHECK1-NEXT: [[TMP95:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 41820// CHECK1-NEXT: [[TMP96:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 41821// CHECK1-NEXT: [[SUB148:%.*]] = sub i32 [[TMP95]], [[TMP96]]1822// CHECK1-NEXT: [[SUB149:%.*]] = sub i32 [[SUB148]], 11823// CHECK1-NEXT: [[ADD150:%.*]] = add i32 [[SUB149]], 11824// CHECK1-NEXT: [[DIV151:%.*]] = udiv i32 [[ADD150]], 11825// CHECK1-NEXT: [[MUL152:%.*]] = mul i32 [[MUL147]], [[DIV151]]1826// CHECK1-NEXT: [[CONV153:%.*]] = zext i32 [[MUL152]] to i641827// CHECK1-NEXT: [[MUL154:%.*]] = mul nsw i64 [[DIV139]], [[CONV153]]1828// CHECK1-NEXT: [[SUB155:%.*]] = sub nsw i64 [[TMP81]], [[MUL154]]1829// CHECK1-NEXT: [[TMP97:%.*]] = load i64, ptr [[DOTOMP_IV]], align 81830// CHECK1-NEXT: [[TMP98:%.*]] = load i64, ptr [[DOTOMP_IV]], align 81831// CHECK1-NEXT: [[TMP99:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 41832// CHECK1-NEXT: [[TMP100:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 41833// CHECK1-NEXT: [[SUB156:%.*]] = sub i32 [[TMP99]], [[TMP100]]1834// CHECK1-NEXT: [[SUB157:%.*]] = sub i32 [[SUB156]], 11835// CHECK1-NEXT: [[TMP101:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41836// CHECK1-NEXT: [[ADD158:%.*]] = add i32 [[SUB157]], [[TMP101]]1837// CHECK1-NEXT: [[TMP102:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41838// CHECK1-NEXT: [[DIV159:%.*]] = udiv i32 [[ADD158]], [[TMP102]]1839// CHECK1-NEXT: [[MUL160:%.*]] = mul i32 1, [[DIV159]]1840// CHECK1-NEXT: [[TMP103:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 41841// CHECK1-NEXT: [[SUB161:%.*]] = sub i32 [[TMP103]], -631842// CHECK1-NEXT: [[DIV162:%.*]] = udiv i32 [[SUB161]], 641843// CHECK1-NEXT: [[MUL163:%.*]] = mul i32 [[MUL160]], [[DIV162]]1844// CHECK1-NEXT: [[TMP104:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 41845// CHECK1-NEXT: [[TMP105:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 41846// CHECK1-NEXT: [[SUB164:%.*]] = sub i32 [[TMP104]], [[TMP105]]1847// CHECK1-NEXT: [[SUB165:%.*]] = sub i32 [[SUB164]], 11848// CHECK1-NEXT: [[ADD166:%.*]] = add i32 [[SUB165]], 11849// CHECK1-NEXT: [[DIV167:%.*]] = udiv i32 [[ADD166]], 11850// CHECK1-NEXT: [[MUL168:%.*]] = mul i32 [[MUL163]], [[DIV167]]1851// CHECK1-NEXT: [[CONV169:%.*]] = zext i32 [[MUL168]] to i641852// CHECK1-NEXT: [[DIV170:%.*]] = sdiv i64 [[TMP98]], [[CONV169]]1853// CHECK1-NEXT: [[TMP106:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 41854// CHECK1-NEXT: [[TMP107:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 41855// CHECK1-NEXT: [[SUB171:%.*]] = sub i32 [[TMP106]], [[TMP107]]1856// CHECK1-NEXT: [[SUB172:%.*]] = sub i32 [[SUB171]], 11857// CHECK1-NEXT: [[TMP108:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41858// CHECK1-NEXT: [[ADD173:%.*]] = add i32 [[SUB172]], [[TMP108]]1859// CHECK1-NEXT: [[TMP109:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41860// CHECK1-NEXT: [[DIV174:%.*]] = udiv i32 [[ADD173]], [[TMP109]]1861// CHECK1-NEXT: [[MUL175:%.*]] = mul i32 1, [[DIV174]]1862// CHECK1-NEXT: [[TMP110:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 41863// CHECK1-NEXT: [[SUB176:%.*]] = sub i32 [[TMP110]], -631864// CHECK1-NEXT: [[DIV177:%.*]] = udiv i32 [[SUB176]], 641865// CHECK1-NEXT: [[MUL178:%.*]] = mul i32 [[MUL175]], [[DIV177]]1866// CHECK1-NEXT: [[TMP111:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 41867// CHECK1-NEXT: [[TMP112:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 41868// CHECK1-NEXT: [[SUB179:%.*]] = sub i32 [[TMP111]], [[TMP112]]1869// CHECK1-NEXT: [[SUB180:%.*]] = sub i32 [[SUB179]], 11870// CHECK1-NEXT: [[ADD181:%.*]] = add i32 [[SUB180]], 11871// CHECK1-NEXT: [[DIV182:%.*]] = udiv i32 [[ADD181]], 11872// CHECK1-NEXT: [[MUL183:%.*]] = mul i32 [[MUL178]], [[DIV182]]1873// CHECK1-NEXT: [[CONV184:%.*]] = zext i32 [[MUL183]] to i641874// CHECK1-NEXT: [[MUL185:%.*]] = mul nsw i64 [[DIV170]], [[CONV184]]1875// CHECK1-NEXT: [[SUB186:%.*]] = sub nsw i64 [[TMP97]], [[MUL185]]1876// CHECK1-NEXT: [[TMP113:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 41877// CHECK1-NEXT: [[SUB187:%.*]] = sub i32 [[TMP113]], -631878// CHECK1-NEXT: [[DIV188:%.*]] = udiv i32 [[SUB187]], 641879// CHECK1-NEXT: [[MUL189:%.*]] = mul i32 1, [[DIV188]]1880// CHECK1-NEXT: [[TMP114:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 41881// CHECK1-NEXT: [[TMP115:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 41882// CHECK1-NEXT: [[SUB190:%.*]] = sub i32 [[TMP114]], [[TMP115]]1883// CHECK1-NEXT: [[SUB191:%.*]] = sub i32 [[SUB190]], 11884// CHECK1-NEXT: [[ADD192:%.*]] = add i32 [[SUB191]], 11885// CHECK1-NEXT: [[DIV193:%.*]] = udiv i32 [[ADD192]], 11886// CHECK1-NEXT: [[MUL194:%.*]] = mul i32 [[MUL189]], [[DIV193]]1887// CHECK1-NEXT: [[CONV195:%.*]] = zext i32 [[MUL194]] to i641888// CHECK1-NEXT: [[DIV196:%.*]] = sdiv i64 [[SUB186]], [[CONV195]]1889// CHECK1-NEXT: [[TMP116:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 41890// CHECK1-NEXT: [[SUB197:%.*]] = sub i32 [[TMP116]], -631891// CHECK1-NEXT: [[DIV198:%.*]] = udiv i32 [[SUB197]], 641892// CHECK1-NEXT: [[MUL199:%.*]] = mul i32 1, [[DIV198]]1893// CHECK1-NEXT: [[TMP117:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 41894// CHECK1-NEXT: [[TMP118:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 41895// CHECK1-NEXT: [[SUB200:%.*]] = sub i32 [[TMP117]], [[TMP118]]1896// CHECK1-NEXT: [[SUB201:%.*]] = sub i32 [[SUB200]], 11897// CHECK1-NEXT: [[ADD202:%.*]] = add i32 [[SUB201]], 11898// CHECK1-NEXT: [[DIV203:%.*]] = udiv i32 [[ADD202]], 11899// CHECK1-NEXT: [[MUL204:%.*]] = mul i32 [[MUL199]], [[DIV203]]1900// CHECK1-NEXT: [[CONV205:%.*]] = zext i32 [[MUL204]] to i641901// CHECK1-NEXT: [[MUL206:%.*]] = mul nsw i64 [[DIV196]], [[CONV205]]1902// CHECK1-NEXT: [[SUB207:%.*]] = sub nsw i64 [[SUB155]], [[MUL206]]1903// CHECK1-NEXT: [[TMP119:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 41904// CHECK1-NEXT: [[TMP120:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 41905// CHECK1-NEXT: [[SUB208:%.*]] = sub i32 [[TMP119]], [[TMP120]]1906// CHECK1-NEXT: [[SUB209:%.*]] = sub i32 [[SUB208]], 11907// CHECK1-NEXT: [[ADD210:%.*]] = add i32 [[SUB209]], 11908// CHECK1-NEXT: [[DIV211:%.*]] = udiv i32 [[ADD210]], 11909// CHECK1-NEXT: [[MUL212:%.*]] = mul i32 1, [[DIV211]]1910// CHECK1-NEXT: [[CONV213:%.*]] = zext i32 [[MUL212]] to i641911// CHECK1-NEXT: [[DIV214:%.*]] = sdiv i64 [[SUB207]], [[CONV213]]1912// CHECK1-NEXT: [[MUL215:%.*]] = mul nsw i64 [[DIV214]], 641913// CHECK1-NEXT: [[ADD216:%.*]] = add nsw i64 0, [[MUL215]]1914// CHECK1-NEXT: [[CONV217:%.*]] = trunc i64 [[ADD216]] to i321915// CHECK1-NEXT: store i32 [[CONV217]], ptr [[DOTFLOOR_0_IV_K51]], align 41916// CHECK1-NEXT: [[TMP121:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 41917// CHECK1-NEXT: [[CONV218:%.*]] = zext i32 [[TMP121]] to i641918// CHECK1-NEXT: [[TMP122:%.*]] = load i64, ptr [[DOTOMP_IV]], align 81919// CHECK1-NEXT: [[TMP123:%.*]] = load i64, ptr [[DOTOMP_IV]], align 81920// CHECK1-NEXT: [[TMP124:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 41921// CHECK1-NEXT: [[TMP125:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 41922// CHECK1-NEXT: [[SUB219:%.*]] = sub i32 [[TMP124]], [[TMP125]]1923// CHECK1-NEXT: [[SUB220:%.*]] = sub i32 [[SUB219]], 11924// CHECK1-NEXT: [[TMP126:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41925// CHECK1-NEXT: [[ADD221:%.*]] = add i32 [[SUB220]], [[TMP126]]1926// CHECK1-NEXT: [[TMP127:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41927// CHECK1-NEXT: [[DIV222:%.*]] = udiv i32 [[ADD221]], [[TMP127]]1928// CHECK1-NEXT: [[MUL223:%.*]] = mul i32 1, [[DIV222]]1929// CHECK1-NEXT: [[TMP128:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 41930// CHECK1-NEXT: [[SUB224:%.*]] = sub i32 [[TMP128]], -631931// CHECK1-NEXT: [[DIV225:%.*]] = udiv i32 [[SUB224]], 641932// CHECK1-NEXT: [[MUL226:%.*]] = mul i32 [[MUL223]], [[DIV225]]1933// CHECK1-NEXT: [[TMP129:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 41934// CHECK1-NEXT: [[TMP130:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 41935// CHECK1-NEXT: [[SUB227:%.*]] = sub i32 [[TMP129]], [[TMP130]]1936// CHECK1-NEXT: [[SUB228:%.*]] = sub i32 [[SUB227]], 11937// CHECK1-NEXT: [[ADD229:%.*]] = add i32 [[SUB228]], 11938// CHECK1-NEXT: [[DIV230:%.*]] = udiv i32 [[ADD229]], 11939// CHECK1-NEXT: [[MUL231:%.*]] = mul i32 [[MUL226]], [[DIV230]]1940// CHECK1-NEXT: [[CONV232:%.*]] = zext i32 [[MUL231]] to i641941// CHECK1-NEXT: [[DIV233:%.*]] = sdiv i64 [[TMP123]], [[CONV232]]1942// CHECK1-NEXT: [[TMP131:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 41943// CHECK1-NEXT: [[TMP132:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 41944// CHECK1-NEXT: [[SUB234:%.*]] = sub i32 [[TMP131]], [[TMP132]]1945// CHECK1-NEXT: [[SUB235:%.*]] = sub i32 [[SUB234]], 11946// CHECK1-NEXT: [[TMP133:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41947// CHECK1-NEXT: [[ADD236:%.*]] = add i32 [[SUB235]], [[TMP133]]1948// CHECK1-NEXT: [[TMP134:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41949// CHECK1-NEXT: [[DIV237:%.*]] = udiv i32 [[ADD236]], [[TMP134]]1950// CHECK1-NEXT: [[MUL238:%.*]] = mul i32 1, [[DIV237]]1951// CHECK1-NEXT: [[TMP135:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 41952// CHECK1-NEXT: [[SUB239:%.*]] = sub i32 [[TMP135]], -631953// CHECK1-NEXT: [[DIV240:%.*]] = udiv i32 [[SUB239]], 641954// CHECK1-NEXT: [[MUL241:%.*]] = mul i32 [[MUL238]], [[DIV240]]1955// CHECK1-NEXT: [[TMP136:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 41956// CHECK1-NEXT: [[TMP137:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 41957// CHECK1-NEXT: [[SUB242:%.*]] = sub i32 [[TMP136]], [[TMP137]]1958// CHECK1-NEXT: [[SUB243:%.*]] = sub i32 [[SUB242]], 11959// CHECK1-NEXT: [[ADD244:%.*]] = add i32 [[SUB243]], 11960// CHECK1-NEXT: [[DIV245:%.*]] = udiv i32 [[ADD244]], 11961// CHECK1-NEXT: [[MUL246:%.*]] = mul i32 [[MUL241]], [[DIV245]]1962// CHECK1-NEXT: [[CONV247:%.*]] = zext i32 [[MUL246]] to i641963// CHECK1-NEXT: [[MUL248:%.*]] = mul nsw i64 [[DIV233]], [[CONV247]]1964// CHECK1-NEXT: [[SUB249:%.*]] = sub nsw i64 [[TMP122]], [[MUL248]]1965// CHECK1-NEXT: [[TMP138:%.*]] = load i64, ptr [[DOTOMP_IV]], align 81966// CHECK1-NEXT: [[TMP139:%.*]] = load i64, ptr [[DOTOMP_IV]], align 81967// CHECK1-NEXT: [[TMP140:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 41968// CHECK1-NEXT: [[TMP141:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 41969// CHECK1-NEXT: [[SUB250:%.*]] = sub i32 [[TMP140]], [[TMP141]]1970// CHECK1-NEXT: [[SUB251:%.*]] = sub i32 [[SUB250]], 11971// CHECK1-NEXT: [[TMP142:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41972// CHECK1-NEXT: [[ADD252:%.*]] = add i32 [[SUB251]], [[TMP142]]1973// CHECK1-NEXT: [[TMP143:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41974// CHECK1-NEXT: [[DIV253:%.*]] = udiv i32 [[ADD252]], [[TMP143]]1975// CHECK1-NEXT: [[MUL254:%.*]] = mul i32 1, [[DIV253]]1976// CHECK1-NEXT: [[TMP144:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 41977// CHECK1-NEXT: [[SUB255:%.*]] = sub i32 [[TMP144]], -631978// CHECK1-NEXT: [[DIV256:%.*]] = udiv i32 [[SUB255]], 641979// CHECK1-NEXT: [[MUL257:%.*]] = mul i32 [[MUL254]], [[DIV256]]1980// CHECK1-NEXT: [[TMP145:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 41981// CHECK1-NEXT: [[TMP146:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 41982// CHECK1-NEXT: [[SUB258:%.*]] = sub i32 [[TMP145]], [[TMP146]]1983// CHECK1-NEXT: [[SUB259:%.*]] = sub i32 [[SUB258]], 11984// CHECK1-NEXT: [[ADD260:%.*]] = add i32 [[SUB259]], 11985// CHECK1-NEXT: [[DIV261:%.*]] = udiv i32 [[ADD260]], 11986// CHECK1-NEXT: [[MUL262:%.*]] = mul i32 [[MUL257]], [[DIV261]]1987// CHECK1-NEXT: [[CONV263:%.*]] = zext i32 [[MUL262]] to i641988// CHECK1-NEXT: [[DIV264:%.*]] = sdiv i64 [[TMP139]], [[CONV263]]1989// CHECK1-NEXT: [[TMP147:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 41990// CHECK1-NEXT: [[TMP148:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 41991// CHECK1-NEXT: [[SUB265:%.*]] = sub i32 [[TMP147]], [[TMP148]]1992// CHECK1-NEXT: [[SUB266:%.*]] = sub i32 [[SUB265]], 11993// CHECK1-NEXT: [[TMP149:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41994// CHECK1-NEXT: [[ADD267:%.*]] = add i32 [[SUB266]], [[TMP149]]1995// CHECK1-NEXT: [[TMP150:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 41996// CHECK1-NEXT: [[DIV268:%.*]] = udiv i32 [[ADD267]], [[TMP150]]1997// CHECK1-NEXT: [[MUL269:%.*]] = mul i32 1, [[DIV268]]1998// CHECK1-NEXT: [[TMP151:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 41999// CHECK1-NEXT: [[SUB270:%.*]] = sub i32 [[TMP151]], -632000// CHECK1-NEXT: [[DIV271:%.*]] = udiv i32 [[SUB270]], 642001// CHECK1-NEXT: [[MUL272:%.*]] = mul i32 [[MUL269]], [[DIV271]]2002// CHECK1-NEXT: [[TMP152:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 42003// CHECK1-NEXT: [[TMP153:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 42004// CHECK1-NEXT: [[SUB273:%.*]] = sub i32 [[TMP152]], [[TMP153]]2005// CHECK1-NEXT: [[SUB274:%.*]] = sub i32 [[SUB273]], 12006// CHECK1-NEXT: [[ADD275:%.*]] = add i32 [[SUB274]], 12007// CHECK1-NEXT: [[DIV276:%.*]] = udiv i32 [[ADD275]], 12008// CHECK1-NEXT: [[MUL277:%.*]] = mul i32 [[MUL272]], [[DIV276]]2009// CHECK1-NEXT: [[CONV278:%.*]] = zext i32 [[MUL277]] to i642010// CHECK1-NEXT: [[MUL279:%.*]] = mul nsw i64 [[DIV264]], [[CONV278]]2011// CHECK1-NEXT: [[SUB280:%.*]] = sub nsw i64 [[TMP138]], [[MUL279]]2012// CHECK1-NEXT: [[TMP154:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 42013// CHECK1-NEXT: [[SUB281:%.*]] = sub i32 [[TMP154]], -632014// CHECK1-NEXT: [[DIV282:%.*]] = udiv i32 [[SUB281]], 642015// CHECK1-NEXT: [[MUL283:%.*]] = mul i32 1, [[DIV282]]2016// CHECK1-NEXT: [[TMP155:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 42017// CHECK1-NEXT: [[TMP156:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 42018// CHECK1-NEXT: [[SUB284:%.*]] = sub i32 [[TMP155]], [[TMP156]]2019// CHECK1-NEXT: [[SUB285:%.*]] = sub i32 [[SUB284]], 12020// CHECK1-NEXT: [[ADD286:%.*]] = add i32 [[SUB285]], 12021// CHECK1-NEXT: [[DIV287:%.*]] = udiv i32 [[ADD286]], 12022// CHECK1-NEXT: [[MUL288:%.*]] = mul i32 [[MUL283]], [[DIV287]]2023// CHECK1-NEXT: [[CONV289:%.*]] = zext i32 [[MUL288]] to i642024// CHECK1-NEXT: [[DIV290:%.*]] = sdiv i64 [[SUB280]], [[CONV289]]2025// CHECK1-NEXT: [[TMP157:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 42026// CHECK1-NEXT: [[SUB291:%.*]] = sub i32 [[TMP157]], -632027// CHECK1-NEXT: [[DIV292:%.*]] = udiv i32 [[SUB291]], 642028// CHECK1-NEXT: [[MUL293:%.*]] = mul i32 1, [[DIV292]]2029// CHECK1-NEXT: [[TMP158:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 42030// CHECK1-NEXT: [[TMP159:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 42031// CHECK1-NEXT: [[SUB294:%.*]] = sub i32 [[TMP158]], [[TMP159]]2032// CHECK1-NEXT: [[SUB295:%.*]] = sub i32 [[SUB294]], 12033// CHECK1-NEXT: [[ADD296:%.*]] = add i32 [[SUB295]], 12034// CHECK1-NEXT: [[DIV297:%.*]] = udiv i32 [[ADD296]], 12035// CHECK1-NEXT: [[MUL298:%.*]] = mul i32 [[MUL293]], [[DIV297]]2036// CHECK1-NEXT: [[CONV299:%.*]] = zext i32 [[MUL298]] to i642037// CHECK1-NEXT: [[MUL300:%.*]] = mul nsw i64 [[DIV290]], [[CONV299]]2038// CHECK1-NEXT: [[SUB301:%.*]] = sub nsw i64 [[SUB249]], [[MUL300]]2039// CHECK1-NEXT: [[TMP160:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82040// CHECK1-NEXT: [[TMP161:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82041// CHECK1-NEXT: [[TMP162:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 42042// CHECK1-NEXT: [[TMP163:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 42043// CHECK1-NEXT: [[SUB302:%.*]] = sub i32 [[TMP162]], [[TMP163]]2044// CHECK1-NEXT: [[SUB303:%.*]] = sub i32 [[SUB302]], 12045// CHECK1-NEXT: [[TMP164:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 42046// CHECK1-NEXT: [[ADD304:%.*]] = add i32 [[SUB303]], [[TMP164]]2047// CHECK1-NEXT: [[TMP165:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 42048// CHECK1-NEXT: [[DIV305:%.*]] = udiv i32 [[ADD304]], [[TMP165]]2049// CHECK1-NEXT: [[MUL306:%.*]] = mul i32 1, [[DIV305]]2050// CHECK1-NEXT: [[TMP166:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 42051// CHECK1-NEXT: [[SUB307:%.*]] = sub i32 [[TMP166]], -632052// CHECK1-NEXT: [[DIV308:%.*]] = udiv i32 [[SUB307]], 642053// CHECK1-NEXT: [[MUL309:%.*]] = mul i32 [[MUL306]], [[DIV308]]2054// CHECK1-NEXT: [[TMP167:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 42055// CHECK1-NEXT: [[TMP168:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 42056// CHECK1-NEXT: [[SUB310:%.*]] = sub i32 [[TMP167]], [[TMP168]]2057// CHECK1-NEXT: [[SUB311:%.*]] = sub i32 [[SUB310]], 12058// CHECK1-NEXT: [[ADD312:%.*]] = add i32 [[SUB311]], 12059// CHECK1-NEXT: [[DIV313:%.*]] = udiv i32 [[ADD312]], 12060// CHECK1-NEXT: [[MUL314:%.*]] = mul i32 [[MUL309]], [[DIV313]]2061// CHECK1-NEXT: [[CONV315:%.*]] = zext i32 [[MUL314]] to i642062// CHECK1-NEXT: [[DIV316:%.*]] = sdiv i64 [[TMP161]], [[CONV315]]2063// CHECK1-NEXT: [[TMP169:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 42064// CHECK1-NEXT: [[TMP170:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 42065// CHECK1-NEXT: [[SUB317:%.*]] = sub i32 [[TMP169]], [[TMP170]]2066// CHECK1-NEXT: [[SUB318:%.*]] = sub i32 [[SUB317]], 12067// CHECK1-NEXT: [[TMP171:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 42068// CHECK1-NEXT: [[ADD319:%.*]] = add i32 [[SUB318]], [[TMP171]]2069// CHECK1-NEXT: [[TMP172:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 42070// CHECK1-NEXT: [[DIV320:%.*]] = udiv i32 [[ADD319]], [[TMP172]]2071// CHECK1-NEXT: [[MUL321:%.*]] = mul i32 1, [[DIV320]]2072// CHECK1-NEXT: [[TMP173:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 42073// CHECK1-NEXT: [[SUB322:%.*]] = sub i32 [[TMP173]], -632074// CHECK1-NEXT: [[DIV323:%.*]] = udiv i32 [[SUB322]], 642075// CHECK1-NEXT: [[MUL324:%.*]] = mul i32 [[MUL321]], [[DIV323]]2076// CHECK1-NEXT: [[TMP174:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 42077// CHECK1-NEXT: [[TMP175:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 42078// CHECK1-NEXT: [[SUB325:%.*]] = sub i32 [[TMP174]], [[TMP175]]2079// CHECK1-NEXT: [[SUB326:%.*]] = sub i32 [[SUB325]], 12080// CHECK1-NEXT: [[ADD327:%.*]] = add i32 [[SUB326]], 12081// CHECK1-NEXT: [[DIV328:%.*]] = udiv i32 [[ADD327]], 12082// CHECK1-NEXT: [[MUL329:%.*]] = mul i32 [[MUL324]], [[DIV328]]2083// CHECK1-NEXT: [[CONV330:%.*]] = zext i32 [[MUL329]] to i642084// CHECK1-NEXT: [[MUL331:%.*]] = mul nsw i64 [[DIV316]], [[CONV330]]2085// CHECK1-NEXT: [[SUB332:%.*]] = sub nsw i64 [[TMP160]], [[MUL331]]2086// CHECK1-NEXT: [[TMP176:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82087// CHECK1-NEXT: [[TMP177:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82088// CHECK1-NEXT: [[TMP178:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 42089// CHECK1-NEXT: [[TMP179:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 42090// CHECK1-NEXT: [[SUB333:%.*]] = sub i32 [[TMP178]], [[TMP179]]2091// CHECK1-NEXT: [[SUB334:%.*]] = sub i32 [[SUB333]], 12092// CHECK1-NEXT: [[TMP180:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 42093// CHECK1-NEXT: [[ADD335:%.*]] = add i32 [[SUB334]], [[TMP180]]2094// CHECK1-NEXT: [[TMP181:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 42095// CHECK1-NEXT: [[DIV336:%.*]] = udiv i32 [[ADD335]], [[TMP181]]2096// CHECK1-NEXT: [[MUL337:%.*]] = mul i32 1, [[DIV336]]2097// CHECK1-NEXT: [[TMP182:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 42098// CHECK1-NEXT: [[SUB338:%.*]] = sub i32 [[TMP182]], -632099// CHECK1-NEXT: [[DIV339:%.*]] = udiv i32 [[SUB338]], 642100// CHECK1-NEXT: [[MUL340:%.*]] = mul i32 [[MUL337]], [[DIV339]]2101// CHECK1-NEXT: [[TMP183:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 42102// CHECK1-NEXT: [[TMP184:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 42103// CHECK1-NEXT: [[SUB341:%.*]] = sub i32 [[TMP183]], [[TMP184]]2104// CHECK1-NEXT: [[SUB342:%.*]] = sub i32 [[SUB341]], 12105// CHECK1-NEXT: [[ADD343:%.*]] = add i32 [[SUB342]], 12106// CHECK1-NEXT: [[DIV344:%.*]] = udiv i32 [[ADD343]], 12107// CHECK1-NEXT: [[MUL345:%.*]] = mul i32 [[MUL340]], [[DIV344]]2108// CHECK1-NEXT: [[CONV346:%.*]] = zext i32 [[MUL345]] to i642109// CHECK1-NEXT: [[DIV347:%.*]] = sdiv i64 [[TMP177]], [[CONV346]]2110// CHECK1-NEXT: [[TMP185:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 42111// CHECK1-NEXT: [[TMP186:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 42112// CHECK1-NEXT: [[SUB348:%.*]] = sub i32 [[TMP185]], [[TMP186]]2113// CHECK1-NEXT: [[SUB349:%.*]] = sub i32 [[SUB348]], 12114// CHECK1-NEXT: [[TMP187:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 42115// CHECK1-NEXT: [[ADD350:%.*]] = add i32 [[SUB349]], [[TMP187]]2116// CHECK1-NEXT: [[TMP188:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 42117// CHECK1-NEXT: [[DIV351:%.*]] = udiv i32 [[ADD350]], [[TMP188]]2118// CHECK1-NEXT: [[MUL352:%.*]] = mul i32 1, [[DIV351]]2119// CHECK1-NEXT: [[TMP189:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 42120// CHECK1-NEXT: [[SUB353:%.*]] = sub i32 [[TMP189]], -632121// CHECK1-NEXT: [[DIV354:%.*]] = udiv i32 [[SUB353]], 642122// CHECK1-NEXT: [[MUL355:%.*]] = mul i32 [[MUL352]], [[DIV354]]2123// CHECK1-NEXT: [[TMP190:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 42124// CHECK1-NEXT: [[TMP191:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 42125// CHECK1-NEXT: [[SUB356:%.*]] = sub i32 [[TMP190]], [[TMP191]]2126// CHECK1-NEXT: [[SUB357:%.*]] = sub i32 [[SUB356]], 12127// CHECK1-NEXT: [[ADD358:%.*]] = add i32 [[SUB357]], 12128// CHECK1-NEXT: [[DIV359:%.*]] = udiv i32 [[ADD358]], 12129// CHECK1-NEXT: [[MUL360:%.*]] = mul i32 [[MUL355]], [[DIV359]]2130// CHECK1-NEXT: [[CONV361:%.*]] = zext i32 [[MUL360]] to i642131// CHECK1-NEXT: [[MUL362:%.*]] = mul nsw i64 [[DIV347]], [[CONV361]]2132// CHECK1-NEXT: [[SUB363:%.*]] = sub nsw i64 [[TMP176]], [[MUL362]]2133// CHECK1-NEXT: [[TMP192:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 42134// CHECK1-NEXT: [[SUB364:%.*]] = sub i32 [[TMP192]], -632135// CHECK1-NEXT: [[DIV365:%.*]] = udiv i32 [[SUB364]], 642136// CHECK1-NEXT: [[MUL366:%.*]] = mul i32 1, [[DIV365]]2137// CHECK1-NEXT: [[TMP193:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 42138// CHECK1-NEXT: [[TMP194:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 42139// CHECK1-NEXT: [[SUB367:%.*]] = sub i32 [[TMP193]], [[TMP194]]2140// CHECK1-NEXT: [[SUB368:%.*]] = sub i32 [[SUB367]], 12141// CHECK1-NEXT: [[ADD369:%.*]] = add i32 [[SUB368]], 12142// CHECK1-NEXT: [[DIV370:%.*]] = udiv i32 [[ADD369]], 12143// CHECK1-NEXT: [[MUL371:%.*]] = mul i32 [[MUL366]], [[DIV370]]2144// CHECK1-NEXT: [[CONV372:%.*]] = zext i32 [[MUL371]] to i642145// CHECK1-NEXT: [[DIV373:%.*]] = sdiv i64 [[SUB363]], [[CONV372]]2146// CHECK1-NEXT: [[TMP195:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 42147// CHECK1-NEXT: [[SUB374:%.*]] = sub i32 [[TMP195]], -632148// CHECK1-NEXT: [[DIV375:%.*]] = udiv i32 [[SUB374]], 642149// CHECK1-NEXT: [[MUL376:%.*]] = mul i32 1, [[DIV375]]2150// CHECK1-NEXT: [[TMP196:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 42151// CHECK1-NEXT: [[TMP197:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 42152// CHECK1-NEXT: [[SUB377:%.*]] = sub i32 [[TMP196]], [[TMP197]]2153// CHECK1-NEXT: [[SUB378:%.*]] = sub i32 [[SUB377]], 12154// CHECK1-NEXT: [[ADD379:%.*]] = add i32 [[SUB378]], 12155// CHECK1-NEXT: [[DIV380:%.*]] = udiv i32 [[ADD379]], 12156// CHECK1-NEXT: [[MUL381:%.*]] = mul i32 [[MUL376]], [[DIV380]]2157// CHECK1-NEXT: [[CONV382:%.*]] = zext i32 [[MUL381]] to i642158// CHECK1-NEXT: [[MUL383:%.*]] = mul nsw i64 [[DIV373]], [[CONV382]]2159// CHECK1-NEXT: [[SUB384:%.*]] = sub nsw i64 [[SUB332]], [[MUL383]]2160// CHECK1-NEXT: [[TMP198:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 42161// CHECK1-NEXT: [[TMP199:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 42162// CHECK1-NEXT: [[SUB385:%.*]] = sub i32 [[TMP198]], [[TMP199]]2163// CHECK1-NEXT: [[SUB386:%.*]] = sub i32 [[SUB385]], 12164// CHECK1-NEXT: [[ADD387:%.*]] = add i32 [[SUB386]], 12165// CHECK1-NEXT: [[DIV388:%.*]] = udiv i32 [[ADD387]], 12166// CHECK1-NEXT: [[MUL389:%.*]] = mul i32 1, [[DIV388]]2167// CHECK1-NEXT: [[CONV390:%.*]] = zext i32 [[MUL389]] to i642168// CHECK1-NEXT: [[DIV391:%.*]] = sdiv i64 [[SUB384]], [[CONV390]]2169// CHECK1-NEXT: [[TMP200:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 42170// CHECK1-NEXT: [[TMP201:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 42171// CHECK1-NEXT: [[SUB392:%.*]] = sub i32 [[TMP200]], [[TMP201]]2172// CHECK1-NEXT: [[SUB393:%.*]] = sub i32 [[SUB392]], 12173// CHECK1-NEXT: [[ADD394:%.*]] = add i32 [[SUB393]], 12174// CHECK1-NEXT: [[DIV395:%.*]] = udiv i32 [[ADD394]], 12175// CHECK1-NEXT: [[MUL396:%.*]] = mul i32 1, [[DIV395]]2176// CHECK1-NEXT: [[CONV397:%.*]] = zext i32 [[MUL396]] to i642177// CHECK1-NEXT: [[MUL398:%.*]] = mul nsw i64 [[DIV391]], [[CONV397]]2178// CHECK1-NEXT: [[SUB399:%.*]] = sub nsw i64 [[SUB301]], [[MUL398]]2179// CHECK1-NEXT: [[MUL400:%.*]] = mul nsw i64 [[SUB399]], 12180// CHECK1-NEXT: [[ADD401:%.*]] = add nsw i64 [[CONV218]], [[MUL400]]2181// CHECK1-NEXT: [[CONV402:%.*]] = trunc i64 [[ADD401]] to i322182// CHECK1-NEXT: store i32 [[CONV402]], ptr [[DOTTILE_0_IV_K52]], align 42183// CHECK1-NEXT: [[TMP202:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_8]], align 42184// CHECK1-NEXT: [[TMP203:%.*]] = load i32, ptr [[DOTTILE_0_IV_K52]], align 42185// CHECK1-NEXT: [[TMP204:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 42186// CHECK1-NEXT: [[MUL403:%.*]] = mul i32 [[TMP203]], [[TMP204]]2187// CHECK1-NEXT: [[ADD404:%.*]] = add i32 [[TMP202]], [[MUL403]]2188// CHECK1-NEXT: store i32 [[ADD404]], ptr [[K]], align 42189// CHECK1-NEXT: [[TMP205:%.*]] = load i32, ptr [[I49]], align 42190// CHECK1-NEXT: [[TMP206:%.*]] = load i32, ptr [[J50]], align 42191// CHECK1-NEXT: [[TMP207:%.*]] = load i32, ptr [[K]], align 42192// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP205]], i32 noundef [[TMP206]], i32 noundef [[TMP207]])2193// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]2194// CHECK1: omp.body.continue:2195// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]2196// CHECK1: omp.inner.for.inc:2197// CHECK1-NEXT: [[TMP208:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82198// CHECK1-NEXT: [[ADD405:%.*]] = add nsw i64 [[TMP208]], 12199// CHECK1-NEXT: store i64 [[ADD405]], ptr [[DOTOMP_IV]], align 82200// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]2201// CHECK1: omp.inner.for.end:2202// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]2203// CHECK1: omp.loop.exit:2204// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]])2205// CHECK1-NEXT: br label [[OMP_PRECOND_END]]2206// CHECK1: omp.precond.end:2207// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]])2208// CHECK1-NEXT: ret void2209//2210//2211// CHECK1-LABEL: define {{[^@]+}}@foo92212// CHECK1-SAME: () #[[ATTR0]] {2213// CHECK1-NEXT: entry:2214// CHECK1-NEXT: [[ARR:%.*]] = alloca [128 x double], align 162215// CHECK1-NEXT: [[C:%.*]] = alloca double, align 82216// CHECK1-NEXT: [[__RANGE2:%.*]] = alloca ptr, align 82217// CHECK1-NEXT: [[__END2:%.*]] = alloca ptr, align 82218// CHECK1-NEXT: [[__BEGIN2:%.*]] = alloca ptr, align 82219// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca ptr, align 82220// CHECK1-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca ptr, align 82221// CHECK1-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i64, align 82222// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 42223// CHECK1-NEXT: [[DOTPERMUTED_0_IV_I:%.*]] = alloca i32, align 42224// CHECK1-NEXT: [[DOTPERMUTED_1_IV___BEGIN2:%.*]] = alloca i64, align 82225// CHECK1-NEXT: [[V:%.*]] = alloca ptr, align 82226// CHECK1-NEXT: store double 4.200000e+01, ptr [[C]], align 82227// CHECK1-NEXT: store ptr [[ARR]], ptr [[__RANGE2]], align 82228// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__RANGE2]], align 82229// CHECK1-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP0]], i64 0, i64 02230// CHECK1-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY]], i64 1282231// CHECK1-NEXT: store ptr [[ADD_PTR]], ptr [[__END2]], align 82232// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE2]], align 82233// CHECK1-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP1]], i64 0, i64 02234// CHECK1-NEXT: store ptr [[ARRAYDECAY1]], ptr [[__BEGIN2]], align 82235// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE2]], align 82236// CHECK1-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP2]], i64 0, i64 02237// CHECK1-NEXT: store ptr [[ARRAYDECAY2]], ptr [[DOTCAPTURE_EXPR_]], align 82238// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[__END2]], align 82239// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTCAPTURE_EXPR_3]], align 82240// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_3]], align 82241// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 82242// CHECK1-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint ptr [[TMP4]] to i642243// CHECK1-NEXT: [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint ptr [[TMP5]] to i642244// CHECK1-NEXT: [[SUB_PTR_SUB:%.*]] = sub i64 [[SUB_PTR_LHS_CAST]], [[SUB_PTR_RHS_CAST]]2245// CHECK1-NEXT: [[SUB_PTR_DIV:%.*]] = sdiv exact i64 [[SUB_PTR_SUB]], 82246// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i64 [[SUB_PTR_DIV]], 12247// CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 [[SUB]], 12248// CHECK1-NEXT: [[DIV:%.*]] = sdiv i64 [[ADD]], 12249// CHECK1-NEXT: [[SUB5:%.*]] = sub nsw i64 [[DIV]], 12250// CHECK1-NEXT: store i64 [[SUB5]], ptr [[DOTCAPTURE_EXPR_4]], align 82251// CHECK1-NEXT: store i32 0, ptr [[I]], align 42252// CHECK1-NEXT: store i32 0, ptr [[DOTPERMUTED_0_IV_I]], align 42253// CHECK1-NEXT: br label [[FOR_COND:%.*]]2254// CHECK1: for.cond:2255// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_I]], align 42256// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], 212257// CHECK1-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END15:%.*]]2258// CHECK1: for.body:2259// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_I]], align 42260// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 22261// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL]]2262// CHECK1-NEXT: store i32 [[ADD6]], ptr [[I]], align 42263// CHECK1-NEXT: store i64 0, ptr [[DOTPERMUTED_1_IV___BEGIN2]], align 82264// CHECK1-NEXT: br label [[FOR_COND7:%.*]]2265// CHECK1: for.cond7:2266// CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTPERMUTED_1_IV___BEGIN2]], align 82267// CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_4]], align 82268// CHECK1-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP9]], 12269// CHECK1-NEXT: [[CMP9:%.*]] = icmp slt i64 [[TMP8]], [[ADD8]]2270// CHECK1-NEXT: br i1 [[CMP9]], label [[FOR_BODY10:%.*]], label [[FOR_END:%.*]]2271// CHECK1: for.body10:2272// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 82273// CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTPERMUTED_1_IV___BEGIN2]], align 82274// CHECK1-NEXT: [[MUL11:%.*]] = mul nsw i64 [[TMP11]], 12275// CHECK1-NEXT: [[ADD_PTR12:%.*]] = getelementptr inbounds double, ptr [[TMP10]], i64 [[MUL11]]2276// CHECK1-NEXT: store ptr [[ADD_PTR12]], ptr [[__BEGIN2]], align 82277// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[__BEGIN2]], align 82278// CHECK1-NEXT: store ptr [[TMP12]], ptr [[V]], align 82279// CHECK1-NEXT: [[TMP13:%.*]] = load double, ptr [[C]], align 82280// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[V]], align 82281// CHECK1-NEXT: [[TMP15:%.*]] = load double, ptr [[TMP14]], align 82282// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 42283// CHECK1-NEXT: call void (...) @body(double noundef [[TMP13]], double noundef [[TMP15]], i32 noundef [[TMP16]])2284// CHECK1-NEXT: br label [[FOR_INC:%.*]]2285// CHECK1: for.inc:2286// CHECK1-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTPERMUTED_1_IV___BEGIN2]], align 82287// CHECK1-NEXT: [[INC:%.*]] = add nsw i64 [[TMP17]], 12288// CHECK1-NEXT: store i64 [[INC]], ptr [[DOTPERMUTED_1_IV___BEGIN2]], align 82289// CHECK1-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP13:![0-9]+]]2290// CHECK1: for.end:2291// CHECK1-NEXT: br label [[FOR_INC13:%.*]]2292// CHECK1: for.inc13:2293// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_I]], align 42294// CHECK1-NEXT: [[INC14:%.*]] = add nsw i32 [[TMP18]], 12295// CHECK1-NEXT: store i32 [[INC14]], ptr [[DOTPERMUTED_0_IV_I]], align 42296// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]2297// CHECK1: for.end15:2298// CHECK1-NEXT: ret void2299//2300//2301// CHECK1-LABEL: define {{[^@]+}}@foo102302// CHECK1-SAME: () #[[ATTR0]] {2303// CHECK1-NEXT: entry:2304// CHECK1-NEXT: [[A:%.*]] = alloca [128 x double], align 162305// CHECK1-NEXT: [[B:%.*]] = alloca [16 x double], align 162306// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 82307// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 42308// CHECK1-NEXT: [[_TMP1:%.*]] = alloca i64, align 82309// CHECK1-NEXT: [[_TMP2:%.*]] = alloca i64, align 82310// CHECK1-NEXT: [[_TMP3:%.*]] = alloca i32, align 42311// CHECK1-NEXT: [[C:%.*]] = alloca double, align 82312// CHECK1-NEXT: [[__RANGE3:%.*]] = alloca ptr, align 82313// CHECK1-NEXT: [[__END3:%.*]] = alloca ptr, align 82314// CHECK1-NEXT: [[__BEGIN3:%.*]] = alloca ptr, align 82315// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca ptr, align 82316// CHECK1-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca ptr, align 82317// CHECK1-NEXT: [[DOTCAPTURE_EXPR_7:%.*]] = alloca i64, align 82318// CHECK1-NEXT: [[D:%.*]] = alloca double, align 82319// CHECK1-NEXT: [[__RANGE4:%.*]] = alloca ptr, align 82320// CHECK1-NEXT: [[__END4:%.*]] = alloca ptr, align 82321// CHECK1-NEXT: [[__BEGIN4:%.*]] = alloca ptr, align 82322// CHECK1-NEXT: [[DOTCAPTURE_EXPR_12:%.*]] = alloca ptr, align 82323// CHECK1-NEXT: [[DOTCAPTURE_EXPR_14:%.*]] = alloca ptr, align 82324// CHECK1-NEXT: [[DOTCAPTURE_EXPR_15:%.*]] = alloca i64, align 82325// CHECK1-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i64, align 82326// CHECK1-NEXT: [[DOTCAPTURE_EXPR_26:%.*]] = alloca i64, align 82327// CHECK1-NEXT: [[DOTCAPTURE_EXPR_28:%.*]] = alloca i64, align 82328// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 42329// CHECK1-NEXT: [[DOTPERMUTED_0_IV___BEGIN4:%.*]] = alloca i64, align 82330// CHECK1-NEXT: [[DOTPERMUTED_1_IV___BEGIN3:%.*]] = alloca i64, align 82331// CHECK1-NEXT: [[J:%.*]] = alloca i32, align 42332// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 82333// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 82334// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 82335// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42336// CHECK1-NEXT: [[I37:%.*]] = alloca i32, align 42337// CHECK1-NEXT: [[DOTPERMUTED_0_IV___BEGIN438:%.*]] = alloca i64, align 82338// CHECK1-NEXT: [[DOTPERMUTED_1_IV___BEGIN339:%.*]] = alloca i64, align 82339// CHECK1-NEXT: [[J40:%.*]] = alloca i32, align 42340// CHECK1-NEXT: [[BB:%.*]] = alloca ptr, align 82341// CHECK1-NEXT: [[AA:%.*]] = alloca double, align 82342// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])2343// CHECK1-NEXT: store double 4.200000e+01, ptr [[C]], align 82344// CHECK1-NEXT: store ptr [[A]], ptr [[__RANGE3]], align 82345// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE3]], align 82346// CHECK1-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP1]], i64 0, i64 02347// CHECK1-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY]], i64 1282348// CHECK1-NEXT: store ptr [[ADD_PTR]], ptr [[__END3]], align 82349// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE3]], align 82350// CHECK1-NEXT: [[ARRAYDECAY4:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP2]], i64 0, i64 02351// CHECK1-NEXT: store ptr [[ARRAYDECAY4]], ptr [[__BEGIN3]], align 82352// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[__RANGE3]], align 82353// CHECK1-NEXT: [[ARRAYDECAY5:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP3]], i64 0, i64 02354// CHECK1-NEXT: store ptr [[ARRAYDECAY5]], ptr [[DOTCAPTURE_EXPR_]], align 82355// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[__END3]], align 82356// CHECK1-NEXT: store ptr [[TMP4]], ptr [[DOTCAPTURE_EXPR_6]], align 82357// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_6]], align 82358// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 82359// CHECK1-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint ptr [[TMP5]] to i642360// CHECK1-NEXT: [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint ptr [[TMP6]] to i642361// CHECK1-NEXT: [[SUB_PTR_SUB:%.*]] = sub i64 [[SUB_PTR_LHS_CAST]], [[SUB_PTR_RHS_CAST]]2362// CHECK1-NEXT: [[SUB_PTR_DIV:%.*]] = sdiv exact i64 [[SUB_PTR_SUB]], 82363// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i64 [[SUB_PTR_DIV]], 12364// CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 [[SUB]], 12365// CHECK1-NEXT: [[DIV:%.*]] = sdiv i64 [[ADD]], 12366// CHECK1-NEXT: [[SUB8:%.*]] = sub nsw i64 [[DIV]], 12367// CHECK1-NEXT: store i64 [[SUB8]], ptr [[DOTCAPTURE_EXPR_7]], align 82368// CHECK1-NEXT: store double 4.200000e+01, ptr [[D]], align 82369// CHECK1-NEXT: store ptr [[B]], ptr [[__RANGE4]], align 82370// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[__RANGE4]], align 82371// CHECK1-NEXT: [[ARRAYDECAY9:%.*]] = getelementptr inbounds [16 x double], ptr [[TMP7]], i64 0, i64 02372// CHECK1-NEXT: [[ADD_PTR10:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY9]], i64 162373// CHECK1-NEXT: store ptr [[ADD_PTR10]], ptr [[__END4]], align 82374// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__RANGE4]], align 82375// CHECK1-NEXT: [[ARRAYDECAY11:%.*]] = getelementptr inbounds [16 x double], ptr [[TMP8]], i64 0, i64 02376// CHECK1-NEXT: store ptr [[ARRAYDECAY11]], ptr [[__BEGIN4]], align 82377// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__RANGE4]], align 82378// CHECK1-NEXT: [[ARRAYDECAY13:%.*]] = getelementptr inbounds [16 x double], ptr [[TMP9]], i64 0, i64 02379// CHECK1-NEXT: store ptr [[ARRAYDECAY13]], ptr [[DOTCAPTURE_EXPR_12]], align 82380// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[__END4]], align 82381// CHECK1-NEXT: store ptr [[TMP10]], ptr [[DOTCAPTURE_EXPR_14]], align 82382// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_14]], align 82383// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_12]], align 82384// CHECK1-NEXT: [[SUB_PTR_LHS_CAST16:%.*]] = ptrtoint ptr [[TMP11]] to i642385// CHECK1-NEXT: [[SUB_PTR_RHS_CAST17:%.*]] = ptrtoint ptr [[TMP12]] to i642386// CHECK1-NEXT: [[SUB_PTR_SUB18:%.*]] = sub i64 [[SUB_PTR_LHS_CAST16]], [[SUB_PTR_RHS_CAST17]]2387// CHECK1-NEXT: [[SUB_PTR_DIV19:%.*]] = sdiv exact i64 [[SUB_PTR_SUB18]], 82388// CHECK1-NEXT: [[SUB20:%.*]] = sub nsw i64 [[SUB_PTR_DIV19]], 12389// CHECK1-NEXT: [[ADD21:%.*]] = add nsw i64 [[SUB20]], 12390// CHECK1-NEXT: [[DIV22:%.*]] = sdiv i64 [[ADD21]], 12391// CHECK1-NEXT: [[SUB23:%.*]] = sub nsw i64 [[DIV22]], 12392// CHECK1-NEXT: store i64 [[SUB23]], ptr [[DOTCAPTURE_EXPR_15]], align 82393// CHECK1-NEXT: [[TMP13:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_15]], align 82394// CHECK1-NEXT: [[ADD25:%.*]] = add nsw i64 [[TMP13]], 12395// CHECK1-NEXT: store i64 [[ADD25]], ptr [[DOTCAPTURE_EXPR_24]], align 82396// CHECK1-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_7]], align 82397// CHECK1-NEXT: [[ADD27:%.*]] = add nsw i64 [[TMP14]], 12398// CHECK1-NEXT: store i64 [[ADD27]], ptr [[DOTCAPTURE_EXPR_26]], align 82399// CHECK1-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 82400// CHECK1-NEXT: [[SUB29:%.*]] = sub nsw i64 [[TMP15]], 02401// CHECK1-NEXT: [[DIV30:%.*]] = sdiv i64 [[SUB29]], 12402// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 128, [[DIV30]]2403// CHECK1-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 82404// CHECK1-NEXT: [[SUB31:%.*]] = sub nsw i64 [[TMP16]], 02405// CHECK1-NEXT: [[DIV32:%.*]] = sdiv i64 [[SUB31]], 12406// CHECK1-NEXT: [[MUL33:%.*]] = mul nsw i64 [[MUL]], [[DIV32]]2407// CHECK1-NEXT: [[MUL34:%.*]] = mul nsw i64 [[MUL33]], 1282408// CHECK1-NEXT: [[SUB35:%.*]] = sub nsw i64 [[MUL34]], 12409// CHECK1-NEXT: store i64 [[SUB35]], ptr [[DOTCAPTURE_EXPR_28]], align 82410// CHECK1-NEXT: store i32 0, ptr [[I]], align 42411// CHECK1-NEXT: store i64 0, ptr [[DOTPERMUTED_0_IV___BEGIN4]], align 82412// CHECK1-NEXT: store i64 0, ptr [[DOTPERMUTED_1_IV___BEGIN3]], align 82413// CHECK1-NEXT: store i32 0, ptr [[J]], align 42414// CHECK1-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 82415// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i64 0, [[TMP17]]2416// CHECK1-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]2417// CHECK1: land.lhs.true:2418// CHECK1-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 82419// CHECK1-NEXT: [[CMP36:%.*]] = icmp slt i64 0, [[TMP18]]2420// CHECK1-NEXT: br i1 [[CMP36]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]2421// CHECK1: omp.precond.then:2422// CHECK1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 82423// CHECK1-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_28]], align 82424// CHECK1-NEXT: store i64 [[TMP19]], ptr [[DOTOMP_UB]], align 82425// CHECK1-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 82426// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 42427// CHECK1-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)2428// CHECK1-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_UB]], align 82429// CHECK1-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_28]], align 82430// CHECK1-NEXT: [[CMP41:%.*]] = icmp sgt i64 [[TMP20]], [[TMP21]]2431// CHECK1-NEXT: br i1 [[CMP41]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2432// CHECK1: cond.true:2433// CHECK1-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_28]], align 82434// CHECK1-NEXT: br label [[COND_END:%.*]]2435// CHECK1: cond.false:2436// CHECK1-NEXT: [[TMP23:%.*]] = load i64, ptr [[DOTOMP_UB]], align 82437// CHECK1-NEXT: br label [[COND_END]]2438// CHECK1: cond.end:2439// CHECK1-NEXT: [[COND:%.*]] = phi i64 [ [[TMP22]], [[COND_TRUE]] ], [ [[TMP23]], [[COND_FALSE]] ]2440// CHECK1-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 82441// CHECK1-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_LB]], align 82442// CHECK1-NEXT: store i64 [[TMP24]], ptr [[DOTOMP_IV]], align 82443// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]2444// CHECK1: omp.inner.for.cond:2445// CHECK1-NEXT: [[TMP25:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82446// CHECK1-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTOMP_UB]], align 82447// CHECK1-NEXT: [[CMP42:%.*]] = icmp sle i64 [[TMP25]], [[TMP26]]2448// CHECK1-NEXT: br i1 [[CMP42]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2449// CHECK1: omp.inner.for.body:2450// CHECK1-NEXT: [[TMP27:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82451// CHECK1-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 82452// CHECK1-NEXT: [[SUB43:%.*]] = sub nsw i64 [[TMP28]], 02453// CHECK1-NEXT: [[DIV44:%.*]] = sdiv i64 [[SUB43]], 12454// CHECK1-NEXT: [[MUL45:%.*]] = mul nsw i64 1, [[DIV44]]2455// CHECK1-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 82456// CHECK1-NEXT: [[SUB46:%.*]] = sub nsw i64 [[TMP29]], 02457// CHECK1-NEXT: [[DIV47:%.*]] = sdiv i64 [[SUB46]], 12458// CHECK1-NEXT: [[MUL48:%.*]] = mul nsw i64 [[MUL45]], [[DIV47]]2459// CHECK1-NEXT: [[MUL49:%.*]] = mul nsw i64 [[MUL48]], 1282460// CHECK1-NEXT: [[DIV50:%.*]] = sdiv i64 [[TMP27]], [[MUL49]]2461// CHECK1-NEXT: [[MUL51:%.*]] = mul nsw i64 [[DIV50]], 12462// CHECK1-NEXT: [[ADD52:%.*]] = add nsw i64 0, [[MUL51]]2463// CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[ADD52]] to i322464// CHECK1-NEXT: store i32 [[CONV]], ptr [[I37]], align 42465// CHECK1-NEXT: [[TMP30:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82466// CHECK1-NEXT: [[TMP31:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82467// CHECK1-NEXT: [[TMP32:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 82468// CHECK1-NEXT: [[SUB53:%.*]] = sub nsw i64 [[TMP32]], 02469// CHECK1-NEXT: [[DIV54:%.*]] = sdiv i64 [[SUB53]], 12470// CHECK1-NEXT: [[MUL55:%.*]] = mul nsw i64 1, [[DIV54]]2471// CHECK1-NEXT: [[TMP33:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 82472// CHECK1-NEXT: [[SUB56:%.*]] = sub nsw i64 [[TMP33]], 02473// CHECK1-NEXT: [[DIV57:%.*]] = sdiv i64 [[SUB56]], 12474// CHECK1-NEXT: [[MUL58:%.*]] = mul nsw i64 [[MUL55]], [[DIV57]]2475// CHECK1-NEXT: [[MUL59:%.*]] = mul nsw i64 [[MUL58]], 1282476// CHECK1-NEXT: [[DIV60:%.*]] = sdiv i64 [[TMP31]], [[MUL59]]2477// CHECK1-NEXT: [[TMP34:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 82478// CHECK1-NEXT: [[SUB61:%.*]] = sub nsw i64 [[TMP34]], 02479// CHECK1-NEXT: [[DIV62:%.*]] = sdiv i64 [[SUB61]], 12480// CHECK1-NEXT: [[MUL63:%.*]] = mul nsw i64 1, [[DIV62]]2481// CHECK1-NEXT: [[TMP35:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 82482// CHECK1-NEXT: [[SUB64:%.*]] = sub nsw i64 [[TMP35]], 02483// CHECK1-NEXT: [[DIV65:%.*]] = sdiv i64 [[SUB64]], 12484// CHECK1-NEXT: [[MUL66:%.*]] = mul nsw i64 [[MUL63]], [[DIV65]]2485// CHECK1-NEXT: [[MUL67:%.*]] = mul nsw i64 [[MUL66]], 1282486// CHECK1-NEXT: [[MUL68:%.*]] = mul nsw i64 [[DIV60]], [[MUL67]]2487// CHECK1-NEXT: [[SUB69:%.*]] = sub nsw i64 [[TMP30]], [[MUL68]]2488// CHECK1-NEXT: [[TMP36:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 82489// CHECK1-NEXT: [[SUB70:%.*]] = sub nsw i64 [[TMP36]], 02490// CHECK1-NEXT: [[DIV71:%.*]] = sdiv i64 [[SUB70]], 12491// CHECK1-NEXT: [[MUL72:%.*]] = mul nsw i64 1, [[DIV71]]2492// CHECK1-NEXT: [[MUL73:%.*]] = mul nsw i64 [[MUL72]], 1282493// CHECK1-NEXT: [[DIV74:%.*]] = sdiv i64 [[SUB69]], [[MUL73]]2494// CHECK1-NEXT: [[MUL75:%.*]] = mul nsw i64 [[DIV74]], 12495// CHECK1-NEXT: [[ADD76:%.*]] = add nsw i64 0, [[MUL75]]2496// CHECK1-NEXT: store i64 [[ADD76]], ptr [[DOTPERMUTED_0_IV___BEGIN438]], align 82497// CHECK1-NEXT: [[TMP37:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82498// CHECK1-NEXT: [[TMP38:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82499// CHECK1-NEXT: [[TMP39:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 82500// CHECK1-NEXT: [[SUB77:%.*]] = sub nsw i64 [[TMP39]], 02501// CHECK1-NEXT: [[DIV78:%.*]] = sdiv i64 [[SUB77]], 12502// CHECK1-NEXT: [[MUL79:%.*]] = mul nsw i64 1, [[DIV78]]2503// CHECK1-NEXT: [[TMP40:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 82504// CHECK1-NEXT: [[SUB80:%.*]] = sub nsw i64 [[TMP40]], 02505// CHECK1-NEXT: [[DIV81:%.*]] = sdiv i64 [[SUB80]], 12506// CHECK1-NEXT: [[MUL82:%.*]] = mul nsw i64 [[MUL79]], [[DIV81]]2507// CHECK1-NEXT: [[MUL83:%.*]] = mul nsw i64 [[MUL82]], 1282508// CHECK1-NEXT: [[DIV84:%.*]] = sdiv i64 [[TMP38]], [[MUL83]]2509// CHECK1-NEXT: [[TMP41:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 82510// CHECK1-NEXT: [[SUB85:%.*]] = sub nsw i64 [[TMP41]], 02511// CHECK1-NEXT: [[DIV86:%.*]] = sdiv i64 [[SUB85]], 12512// CHECK1-NEXT: [[MUL87:%.*]] = mul nsw i64 1, [[DIV86]]2513// CHECK1-NEXT: [[TMP42:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 82514// CHECK1-NEXT: [[SUB88:%.*]] = sub nsw i64 [[TMP42]], 02515// CHECK1-NEXT: [[DIV89:%.*]] = sdiv i64 [[SUB88]], 12516// CHECK1-NEXT: [[MUL90:%.*]] = mul nsw i64 [[MUL87]], [[DIV89]]2517// CHECK1-NEXT: [[MUL91:%.*]] = mul nsw i64 [[MUL90]], 1282518// CHECK1-NEXT: [[MUL92:%.*]] = mul nsw i64 [[DIV84]], [[MUL91]]2519// CHECK1-NEXT: [[SUB93:%.*]] = sub nsw i64 [[TMP37]], [[MUL92]]2520// CHECK1-NEXT: [[TMP43:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82521// CHECK1-NEXT: [[TMP44:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82522// CHECK1-NEXT: [[TMP45:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 82523// CHECK1-NEXT: [[SUB94:%.*]] = sub nsw i64 [[TMP45]], 02524// CHECK1-NEXT: [[DIV95:%.*]] = sdiv i64 [[SUB94]], 12525// CHECK1-NEXT: [[MUL96:%.*]] = mul nsw i64 1, [[DIV95]]2526// CHECK1-NEXT: [[TMP46:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 82527// CHECK1-NEXT: [[SUB97:%.*]] = sub nsw i64 [[TMP46]], 02528// CHECK1-NEXT: [[DIV98:%.*]] = sdiv i64 [[SUB97]], 12529// CHECK1-NEXT: [[MUL99:%.*]] = mul nsw i64 [[MUL96]], [[DIV98]]2530// CHECK1-NEXT: [[MUL100:%.*]] = mul nsw i64 [[MUL99]], 1282531// CHECK1-NEXT: [[DIV101:%.*]] = sdiv i64 [[TMP44]], [[MUL100]]2532// CHECK1-NEXT: [[TMP47:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 82533// CHECK1-NEXT: [[SUB102:%.*]] = sub nsw i64 [[TMP47]], 02534// CHECK1-NEXT: [[DIV103:%.*]] = sdiv i64 [[SUB102]], 12535// CHECK1-NEXT: [[MUL104:%.*]] = mul nsw i64 1, [[DIV103]]2536// CHECK1-NEXT: [[TMP48:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 82537// CHECK1-NEXT: [[SUB105:%.*]] = sub nsw i64 [[TMP48]], 02538// CHECK1-NEXT: [[DIV106:%.*]] = sdiv i64 [[SUB105]], 12539// CHECK1-NEXT: [[MUL107:%.*]] = mul nsw i64 [[MUL104]], [[DIV106]]2540// CHECK1-NEXT: [[MUL108:%.*]] = mul nsw i64 [[MUL107]], 1282541// CHECK1-NEXT: [[MUL109:%.*]] = mul nsw i64 [[DIV101]], [[MUL108]]2542// CHECK1-NEXT: [[SUB110:%.*]] = sub nsw i64 [[TMP43]], [[MUL109]]2543// CHECK1-NEXT: [[TMP49:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 82544// CHECK1-NEXT: [[SUB111:%.*]] = sub nsw i64 [[TMP49]], 02545// CHECK1-NEXT: [[DIV112:%.*]] = sdiv i64 [[SUB111]], 12546// CHECK1-NEXT: [[MUL113:%.*]] = mul nsw i64 1, [[DIV112]]2547// CHECK1-NEXT: [[MUL114:%.*]] = mul nsw i64 [[MUL113]], 1282548// CHECK1-NEXT: [[DIV115:%.*]] = sdiv i64 [[SUB110]], [[MUL114]]2549// CHECK1-NEXT: [[TMP50:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 82550// CHECK1-NEXT: [[SUB116:%.*]] = sub nsw i64 [[TMP50]], 02551// CHECK1-NEXT: [[DIV117:%.*]] = sdiv i64 [[SUB116]], 12552// CHECK1-NEXT: [[MUL118:%.*]] = mul nsw i64 1, [[DIV117]]2553// CHECK1-NEXT: [[MUL119:%.*]] = mul nsw i64 [[MUL118]], 1282554// CHECK1-NEXT: [[MUL120:%.*]] = mul nsw i64 [[DIV115]], [[MUL119]]2555// CHECK1-NEXT: [[SUB121:%.*]] = sub nsw i64 [[SUB93]], [[MUL120]]2556// CHECK1-NEXT: [[DIV122:%.*]] = sdiv i64 [[SUB121]], 1282557// CHECK1-NEXT: [[MUL123:%.*]] = mul nsw i64 [[DIV122]], 12558// CHECK1-NEXT: [[ADD124:%.*]] = add nsw i64 0, [[MUL123]]2559// CHECK1-NEXT: store i64 [[ADD124]], ptr [[DOTPERMUTED_1_IV___BEGIN339]], align 82560// CHECK1-NEXT: [[TMP51:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82561// CHECK1-NEXT: [[TMP52:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82562// CHECK1-NEXT: [[TMP53:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 82563// CHECK1-NEXT: [[SUB125:%.*]] = sub nsw i64 [[TMP53]], 02564// CHECK1-NEXT: [[DIV126:%.*]] = sdiv i64 [[SUB125]], 12565// CHECK1-NEXT: [[MUL127:%.*]] = mul nsw i64 1, [[DIV126]]2566// CHECK1-NEXT: [[TMP54:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 82567// CHECK1-NEXT: [[SUB128:%.*]] = sub nsw i64 [[TMP54]], 02568// CHECK1-NEXT: [[DIV129:%.*]] = sdiv i64 [[SUB128]], 12569// CHECK1-NEXT: [[MUL130:%.*]] = mul nsw i64 [[MUL127]], [[DIV129]]2570// CHECK1-NEXT: [[MUL131:%.*]] = mul nsw i64 [[MUL130]], 1282571// CHECK1-NEXT: [[DIV132:%.*]] = sdiv i64 [[TMP52]], [[MUL131]]2572// CHECK1-NEXT: [[TMP55:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 82573// CHECK1-NEXT: [[SUB133:%.*]] = sub nsw i64 [[TMP55]], 02574// CHECK1-NEXT: [[DIV134:%.*]] = sdiv i64 [[SUB133]], 12575// CHECK1-NEXT: [[MUL135:%.*]] = mul nsw i64 1, [[DIV134]]2576// CHECK1-NEXT: [[TMP56:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 82577// CHECK1-NEXT: [[SUB136:%.*]] = sub nsw i64 [[TMP56]], 02578// CHECK1-NEXT: [[DIV137:%.*]] = sdiv i64 [[SUB136]], 12579// CHECK1-NEXT: [[MUL138:%.*]] = mul nsw i64 [[MUL135]], [[DIV137]]2580// CHECK1-NEXT: [[MUL139:%.*]] = mul nsw i64 [[MUL138]], 1282581// CHECK1-NEXT: [[MUL140:%.*]] = mul nsw i64 [[DIV132]], [[MUL139]]2582// CHECK1-NEXT: [[SUB141:%.*]] = sub nsw i64 [[TMP51]], [[MUL140]]2583// CHECK1-NEXT: [[TMP57:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82584// CHECK1-NEXT: [[TMP58:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82585// CHECK1-NEXT: [[TMP59:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 82586// CHECK1-NEXT: [[SUB142:%.*]] = sub nsw i64 [[TMP59]], 02587// CHECK1-NEXT: [[DIV143:%.*]] = sdiv i64 [[SUB142]], 12588// CHECK1-NEXT: [[MUL144:%.*]] = mul nsw i64 1, [[DIV143]]2589// CHECK1-NEXT: [[TMP60:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 82590// CHECK1-NEXT: [[SUB145:%.*]] = sub nsw i64 [[TMP60]], 02591// CHECK1-NEXT: [[DIV146:%.*]] = sdiv i64 [[SUB145]], 12592// CHECK1-NEXT: [[MUL147:%.*]] = mul nsw i64 [[MUL144]], [[DIV146]]2593// CHECK1-NEXT: [[MUL148:%.*]] = mul nsw i64 [[MUL147]], 1282594// CHECK1-NEXT: [[DIV149:%.*]] = sdiv i64 [[TMP58]], [[MUL148]]2595// CHECK1-NEXT: [[TMP61:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 82596// CHECK1-NEXT: [[SUB150:%.*]] = sub nsw i64 [[TMP61]], 02597// CHECK1-NEXT: [[DIV151:%.*]] = sdiv i64 [[SUB150]], 12598// CHECK1-NEXT: [[MUL152:%.*]] = mul nsw i64 1, [[DIV151]]2599// CHECK1-NEXT: [[TMP62:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 82600// CHECK1-NEXT: [[SUB153:%.*]] = sub nsw i64 [[TMP62]], 02601// CHECK1-NEXT: [[DIV154:%.*]] = sdiv i64 [[SUB153]], 12602// CHECK1-NEXT: [[MUL155:%.*]] = mul nsw i64 [[MUL152]], [[DIV154]]2603// CHECK1-NEXT: [[MUL156:%.*]] = mul nsw i64 [[MUL155]], 1282604// CHECK1-NEXT: [[MUL157:%.*]] = mul nsw i64 [[DIV149]], [[MUL156]]2605// CHECK1-NEXT: [[SUB158:%.*]] = sub nsw i64 [[TMP57]], [[MUL157]]2606// CHECK1-NEXT: [[TMP63:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 82607// CHECK1-NEXT: [[SUB159:%.*]] = sub nsw i64 [[TMP63]], 02608// CHECK1-NEXT: [[DIV160:%.*]] = sdiv i64 [[SUB159]], 12609// CHECK1-NEXT: [[MUL161:%.*]] = mul nsw i64 1, [[DIV160]]2610// CHECK1-NEXT: [[MUL162:%.*]] = mul nsw i64 [[MUL161]], 1282611// CHECK1-NEXT: [[DIV163:%.*]] = sdiv i64 [[SUB158]], [[MUL162]]2612// CHECK1-NEXT: [[TMP64:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 82613// CHECK1-NEXT: [[SUB164:%.*]] = sub nsw i64 [[TMP64]], 02614// CHECK1-NEXT: [[DIV165:%.*]] = sdiv i64 [[SUB164]], 12615// CHECK1-NEXT: [[MUL166:%.*]] = mul nsw i64 1, [[DIV165]]2616// CHECK1-NEXT: [[MUL167:%.*]] = mul nsw i64 [[MUL166]], 1282617// CHECK1-NEXT: [[MUL168:%.*]] = mul nsw i64 [[DIV163]], [[MUL167]]2618// CHECK1-NEXT: [[SUB169:%.*]] = sub nsw i64 [[SUB141]], [[MUL168]]2619// CHECK1-NEXT: [[TMP65:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82620// CHECK1-NEXT: [[TMP66:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82621// CHECK1-NEXT: [[TMP67:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 82622// CHECK1-NEXT: [[SUB170:%.*]] = sub nsw i64 [[TMP67]], 02623// CHECK1-NEXT: [[DIV171:%.*]] = sdiv i64 [[SUB170]], 12624// CHECK1-NEXT: [[MUL172:%.*]] = mul nsw i64 1, [[DIV171]]2625// CHECK1-NEXT: [[TMP68:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 82626// CHECK1-NEXT: [[SUB173:%.*]] = sub nsw i64 [[TMP68]], 02627// CHECK1-NEXT: [[DIV174:%.*]] = sdiv i64 [[SUB173]], 12628// CHECK1-NEXT: [[MUL175:%.*]] = mul nsw i64 [[MUL172]], [[DIV174]]2629// CHECK1-NEXT: [[MUL176:%.*]] = mul nsw i64 [[MUL175]], 1282630// CHECK1-NEXT: [[DIV177:%.*]] = sdiv i64 [[TMP66]], [[MUL176]]2631// CHECK1-NEXT: [[TMP69:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 82632// CHECK1-NEXT: [[SUB178:%.*]] = sub nsw i64 [[TMP69]], 02633// CHECK1-NEXT: [[DIV179:%.*]] = sdiv i64 [[SUB178]], 12634// CHECK1-NEXT: [[MUL180:%.*]] = mul nsw i64 1, [[DIV179]]2635// CHECK1-NEXT: [[TMP70:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 82636// CHECK1-NEXT: [[SUB181:%.*]] = sub nsw i64 [[TMP70]], 02637// CHECK1-NEXT: [[DIV182:%.*]] = sdiv i64 [[SUB181]], 12638// CHECK1-NEXT: [[MUL183:%.*]] = mul nsw i64 [[MUL180]], [[DIV182]]2639// CHECK1-NEXT: [[MUL184:%.*]] = mul nsw i64 [[MUL183]], 1282640// CHECK1-NEXT: [[MUL185:%.*]] = mul nsw i64 [[DIV177]], [[MUL184]]2641// CHECK1-NEXT: [[SUB186:%.*]] = sub nsw i64 [[TMP65]], [[MUL185]]2642// CHECK1-NEXT: [[TMP71:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82643// CHECK1-NEXT: [[TMP72:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82644// CHECK1-NEXT: [[TMP73:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 82645// CHECK1-NEXT: [[SUB187:%.*]] = sub nsw i64 [[TMP73]], 02646// CHECK1-NEXT: [[DIV188:%.*]] = sdiv i64 [[SUB187]], 12647// CHECK1-NEXT: [[MUL189:%.*]] = mul nsw i64 1, [[DIV188]]2648// CHECK1-NEXT: [[TMP74:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 82649// CHECK1-NEXT: [[SUB190:%.*]] = sub nsw i64 [[TMP74]], 02650// CHECK1-NEXT: [[DIV191:%.*]] = sdiv i64 [[SUB190]], 12651// CHECK1-NEXT: [[MUL192:%.*]] = mul nsw i64 [[MUL189]], [[DIV191]]2652// CHECK1-NEXT: [[MUL193:%.*]] = mul nsw i64 [[MUL192]], 1282653// CHECK1-NEXT: [[DIV194:%.*]] = sdiv i64 [[TMP72]], [[MUL193]]2654// CHECK1-NEXT: [[TMP75:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 82655// CHECK1-NEXT: [[SUB195:%.*]] = sub nsw i64 [[TMP75]], 02656// CHECK1-NEXT: [[DIV196:%.*]] = sdiv i64 [[SUB195]], 12657// CHECK1-NEXT: [[MUL197:%.*]] = mul nsw i64 1, [[DIV196]]2658// CHECK1-NEXT: [[TMP76:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 82659// CHECK1-NEXT: [[SUB198:%.*]] = sub nsw i64 [[TMP76]], 02660// CHECK1-NEXT: [[DIV199:%.*]] = sdiv i64 [[SUB198]], 12661// CHECK1-NEXT: [[MUL200:%.*]] = mul nsw i64 [[MUL197]], [[DIV199]]2662// CHECK1-NEXT: [[MUL201:%.*]] = mul nsw i64 [[MUL200]], 1282663// CHECK1-NEXT: [[MUL202:%.*]] = mul nsw i64 [[DIV194]], [[MUL201]]2664// CHECK1-NEXT: [[SUB203:%.*]] = sub nsw i64 [[TMP71]], [[MUL202]]2665// CHECK1-NEXT: [[TMP77:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 82666// CHECK1-NEXT: [[SUB204:%.*]] = sub nsw i64 [[TMP77]], 02667// CHECK1-NEXT: [[DIV205:%.*]] = sdiv i64 [[SUB204]], 12668// CHECK1-NEXT: [[MUL206:%.*]] = mul nsw i64 1, [[DIV205]]2669// CHECK1-NEXT: [[MUL207:%.*]] = mul nsw i64 [[MUL206]], 1282670// CHECK1-NEXT: [[DIV208:%.*]] = sdiv i64 [[SUB203]], [[MUL207]]2671// CHECK1-NEXT: [[TMP78:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 82672// CHECK1-NEXT: [[SUB209:%.*]] = sub nsw i64 [[TMP78]], 02673// CHECK1-NEXT: [[DIV210:%.*]] = sdiv i64 [[SUB209]], 12674// CHECK1-NEXT: [[MUL211:%.*]] = mul nsw i64 1, [[DIV210]]2675// CHECK1-NEXT: [[MUL212:%.*]] = mul nsw i64 [[MUL211]], 1282676// CHECK1-NEXT: [[MUL213:%.*]] = mul nsw i64 [[DIV208]], [[MUL212]]2677// CHECK1-NEXT: [[SUB214:%.*]] = sub nsw i64 [[SUB186]], [[MUL213]]2678// CHECK1-NEXT: [[DIV215:%.*]] = sdiv i64 [[SUB214]], 1282679// CHECK1-NEXT: [[MUL216:%.*]] = mul nsw i64 [[DIV215]], 1282680// CHECK1-NEXT: [[SUB217:%.*]] = sub nsw i64 [[SUB169]], [[MUL216]]2681// CHECK1-NEXT: [[MUL218:%.*]] = mul nsw i64 [[SUB217]], 12682// CHECK1-NEXT: [[ADD219:%.*]] = add nsw i64 0, [[MUL218]]2683// CHECK1-NEXT: [[CONV220:%.*]] = trunc i64 [[ADD219]] to i322684// CHECK1-NEXT: store i32 [[CONV220]], ptr [[J40]], align 42685// CHECK1-NEXT: [[TMP79:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_12]], align 82686// CHECK1-NEXT: [[TMP80:%.*]] = load i64, ptr [[DOTPERMUTED_0_IV___BEGIN438]], align 82687// CHECK1-NEXT: [[MUL221:%.*]] = mul nsw i64 [[TMP80]], 12688// CHECK1-NEXT: [[ADD_PTR222:%.*]] = getelementptr inbounds double, ptr [[TMP79]], i64 [[MUL221]]2689// CHECK1-NEXT: store ptr [[ADD_PTR222]], ptr [[__BEGIN4]], align 82690// CHECK1-NEXT: [[TMP81:%.*]] = load ptr, ptr [[__BEGIN4]], align 82691// CHECK1-NEXT: store ptr [[TMP81]], ptr [[BB]], align 82692// CHECK1-NEXT: [[TMP82:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 82693// CHECK1-NEXT: [[TMP83:%.*]] = load i64, ptr [[DOTPERMUTED_1_IV___BEGIN339]], align 82694// CHECK1-NEXT: [[MUL223:%.*]] = mul nsw i64 [[TMP83]], 12695// CHECK1-NEXT: [[ADD_PTR224:%.*]] = getelementptr inbounds double, ptr [[TMP82]], i64 [[MUL223]]2696// CHECK1-NEXT: store ptr [[ADD_PTR224]], ptr [[__BEGIN3]], align 82697// CHECK1-NEXT: [[TMP84:%.*]] = load ptr, ptr [[__BEGIN3]], align 82698// CHECK1-NEXT: [[TMP85:%.*]] = load double, ptr [[TMP84]], align 82699// CHECK1-NEXT: store double [[TMP85]], ptr [[AA]], align 82700// CHECK1-NEXT: [[TMP86:%.*]] = load i32, ptr [[I37]], align 42701// CHECK1-NEXT: [[TMP87:%.*]] = load double, ptr [[C]], align 82702// CHECK1-NEXT: [[TMP88:%.*]] = load double, ptr [[AA]], align 82703// CHECK1-NEXT: [[TMP89:%.*]] = load double, ptr [[D]], align 82704// CHECK1-NEXT: [[TMP90:%.*]] = load ptr, ptr [[BB]], align 82705// CHECK1-NEXT: [[TMP91:%.*]] = load double, ptr [[TMP90]], align 82706// CHECK1-NEXT: [[TMP92:%.*]] = load i32, ptr [[J40]], align 42707// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP86]], double noundef [[TMP87]], double noundef [[TMP88]], double noundef [[TMP89]], double noundef [[TMP91]], i32 noundef [[TMP92]])2708// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]2709// CHECK1: omp.body.continue:2710// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]2711// CHECK1: omp.inner.for.inc:2712// CHECK1-NEXT: [[TMP93:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82713// CHECK1-NEXT: [[ADD225:%.*]] = add nsw i64 [[TMP93]], 12714// CHECK1-NEXT: store i64 [[ADD225]], ptr [[DOTOMP_IV]], align 82715// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]2716// CHECK1: omp.inner.for.end:2717// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]2718// CHECK1: omp.loop.exit:2719// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]])2720// CHECK1-NEXT: br label [[OMP_PRECOND_END]]2721// CHECK1: omp.precond.end:2722// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]])2723// CHECK1-NEXT: ret void2724//2725//2726// CHECK2-LABEL: define {{[^@]+}}@body2727// CHECK2-SAME: (...) #[[ATTR0:[0-9]+]] {2728// CHECK2-NEXT: entry:2729// CHECK2-NEXT: ret void2730//2731//2732// CHECK2-LABEL: define {{[^@]+}}@foo12733// CHECK2-SAME: (i32 noundef [[START:%.*]], i32 noundef [[END:%.*]], i32 noundef [[STEP:%.*]]) #[[ATTR0]] {2734// CHECK2-NEXT: entry:2735// CHECK2-NEXT: [[START_ADDR:%.*]] = alloca i32, align 42736// CHECK2-NEXT: [[END_ADDR:%.*]] = alloca i32, align 42737// CHECK2-NEXT: [[STEP_ADDR:%.*]] = alloca i32, align 42738// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 42739// CHECK2-NEXT: store i32 [[START]], ptr [[START_ADDR]], align 42740// CHECK2-NEXT: store i32 [[END]], ptr [[END_ADDR]], align 42741// CHECK2-NEXT: store i32 [[STEP]], ptr [[STEP_ADDR]], align 42742// CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[START_ADDR]], align 42743// CHECK2-NEXT: store i32 [[TMP0]], ptr [[I]], align 42744// CHECK2-NEXT: br label [[FOR_COND:%.*]]2745// CHECK2: for.cond:2746// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[I]], align 42747// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[END_ADDR]], align 42748// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]]2749// CHECK2-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]2750// CHECK2: for.body:2751// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[I]], align 42752// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP3]])2753// CHECK2-NEXT: br label [[FOR_INC:%.*]]2754// CHECK2: for.inc:2755// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[STEP_ADDR]], align 42756// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 42757// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], [[TMP4]]2758// CHECK2-NEXT: store i32 [[ADD]], ptr [[I]], align 42759// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]2760// CHECK2: for.end:2761// CHECK2-NEXT: ret void2762//2763//2764// CHECK2-LABEL: define {{[^@]+}}@foo102765// CHECK2-SAME: () #[[ATTR0]] {2766// CHECK2-NEXT: entry:2767// CHECK2-NEXT: [[A:%.*]] = alloca [128 x double], align 162768// CHECK2-NEXT: [[B:%.*]] = alloca [16 x double], align 162769// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 82770// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 42771// CHECK2-NEXT: [[_TMP1:%.*]] = alloca i64, align 82772// CHECK2-NEXT: [[_TMP2:%.*]] = alloca i64, align 82773// CHECK2-NEXT: [[_TMP3:%.*]] = alloca i32, align 42774// CHECK2-NEXT: [[C:%.*]] = alloca double, align 82775// CHECK2-NEXT: [[__RANGE3:%.*]] = alloca ptr, align 82776// CHECK2-NEXT: [[__END3:%.*]] = alloca ptr, align 82777// CHECK2-NEXT: [[__BEGIN3:%.*]] = alloca ptr, align 82778// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca ptr, align 82779// CHECK2-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca ptr, align 82780// CHECK2-NEXT: [[DOTCAPTURE_EXPR_7:%.*]] = alloca i64, align 82781// CHECK2-NEXT: [[D:%.*]] = alloca double, align 82782// CHECK2-NEXT: [[__RANGE4:%.*]] = alloca ptr, align 82783// CHECK2-NEXT: [[__END4:%.*]] = alloca ptr, align 82784// CHECK2-NEXT: [[__BEGIN4:%.*]] = alloca ptr, align 82785// CHECK2-NEXT: [[DOTCAPTURE_EXPR_12:%.*]] = alloca ptr, align 82786// CHECK2-NEXT: [[DOTCAPTURE_EXPR_14:%.*]] = alloca ptr, align 82787// CHECK2-NEXT: [[DOTCAPTURE_EXPR_15:%.*]] = alloca i64, align 82788// CHECK2-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i64, align 82789// CHECK2-NEXT: [[DOTCAPTURE_EXPR_26:%.*]] = alloca i64, align 82790// CHECK2-NEXT: [[DOTCAPTURE_EXPR_28:%.*]] = alloca i64, align 82791// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 42792// CHECK2-NEXT: [[DOTPERMUTED_0_IV___BEGIN4:%.*]] = alloca i64, align 82793// CHECK2-NEXT: [[DOTPERMUTED_1_IV___BEGIN3:%.*]] = alloca i64, align 82794// CHECK2-NEXT: [[J:%.*]] = alloca i32, align 42795// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 82796// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 82797// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 82798// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42799// CHECK2-NEXT: [[I37:%.*]] = alloca i32, align 42800// CHECK2-NEXT: [[DOTPERMUTED_0_IV___BEGIN438:%.*]] = alloca i64, align 82801// CHECK2-NEXT: [[DOTPERMUTED_1_IV___BEGIN339:%.*]] = alloca i64, align 82802// CHECK2-NEXT: [[J40:%.*]] = alloca i32, align 42803// CHECK2-NEXT: [[BB:%.*]] = alloca ptr, align 82804// CHECK2-NEXT: [[AA:%.*]] = alloca double, align 82805// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])2806// CHECK2-NEXT: store double 4.200000e+01, ptr [[C]], align 82807// CHECK2-NEXT: store ptr [[A]], ptr [[__RANGE3]], align 82808// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE3]], align 82809// CHECK2-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP1]], i64 0, i64 02810// CHECK2-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY]], i64 1282811// CHECK2-NEXT: store ptr [[ADD_PTR]], ptr [[__END3]], align 82812// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE3]], align 82813// CHECK2-NEXT: [[ARRAYDECAY4:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP2]], i64 0, i64 02814// CHECK2-NEXT: store ptr [[ARRAYDECAY4]], ptr [[__BEGIN3]], align 82815// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[__RANGE3]], align 82816// CHECK2-NEXT: [[ARRAYDECAY5:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP3]], i64 0, i64 02817// CHECK2-NEXT: store ptr [[ARRAYDECAY5]], ptr [[DOTCAPTURE_EXPR_]], align 82818// CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[__END3]], align 82819// CHECK2-NEXT: store ptr [[TMP4]], ptr [[DOTCAPTURE_EXPR_6]], align 82820// CHECK2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_6]], align 82821// CHECK2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 82822// CHECK2-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint ptr [[TMP5]] to i642823// CHECK2-NEXT: [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint ptr [[TMP6]] to i642824// CHECK2-NEXT: [[SUB_PTR_SUB:%.*]] = sub i64 [[SUB_PTR_LHS_CAST]], [[SUB_PTR_RHS_CAST]]2825// CHECK2-NEXT: [[SUB_PTR_DIV:%.*]] = sdiv exact i64 [[SUB_PTR_SUB]], 82826// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i64 [[SUB_PTR_DIV]], 12827// CHECK2-NEXT: [[ADD:%.*]] = add nsw i64 [[SUB]], 12828// CHECK2-NEXT: [[DIV:%.*]] = sdiv i64 [[ADD]], 12829// CHECK2-NEXT: [[SUB8:%.*]] = sub nsw i64 [[DIV]], 12830// CHECK2-NEXT: store i64 [[SUB8]], ptr [[DOTCAPTURE_EXPR_7]], align 82831// CHECK2-NEXT: store double 4.200000e+01, ptr [[D]], align 82832// CHECK2-NEXT: store ptr [[B]], ptr [[__RANGE4]], align 82833// CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[__RANGE4]], align 82834// CHECK2-NEXT: [[ARRAYDECAY9:%.*]] = getelementptr inbounds [16 x double], ptr [[TMP7]], i64 0, i64 02835// CHECK2-NEXT: [[ADD_PTR10:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY9]], i64 162836// CHECK2-NEXT: store ptr [[ADD_PTR10]], ptr [[__END4]], align 82837// CHECK2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__RANGE4]], align 82838// CHECK2-NEXT: [[ARRAYDECAY11:%.*]] = getelementptr inbounds [16 x double], ptr [[TMP8]], i64 0, i64 02839// CHECK2-NEXT: store ptr [[ARRAYDECAY11]], ptr [[__BEGIN4]], align 82840// CHECK2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__RANGE4]], align 82841// CHECK2-NEXT: [[ARRAYDECAY13:%.*]] = getelementptr inbounds [16 x double], ptr [[TMP9]], i64 0, i64 02842// CHECK2-NEXT: store ptr [[ARRAYDECAY13]], ptr [[DOTCAPTURE_EXPR_12]], align 82843// CHECK2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[__END4]], align 82844// CHECK2-NEXT: store ptr [[TMP10]], ptr [[DOTCAPTURE_EXPR_14]], align 82845// CHECK2-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_14]], align 82846// CHECK2-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_12]], align 82847// CHECK2-NEXT: [[SUB_PTR_LHS_CAST16:%.*]] = ptrtoint ptr [[TMP11]] to i642848// CHECK2-NEXT: [[SUB_PTR_RHS_CAST17:%.*]] = ptrtoint ptr [[TMP12]] to i642849// CHECK2-NEXT: [[SUB_PTR_SUB18:%.*]] = sub i64 [[SUB_PTR_LHS_CAST16]], [[SUB_PTR_RHS_CAST17]]2850// CHECK2-NEXT: [[SUB_PTR_DIV19:%.*]] = sdiv exact i64 [[SUB_PTR_SUB18]], 82851// CHECK2-NEXT: [[SUB20:%.*]] = sub nsw i64 [[SUB_PTR_DIV19]], 12852// CHECK2-NEXT: [[ADD21:%.*]] = add nsw i64 [[SUB20]], 12853// CHECK2-NEXT: [[DIV22:%.*]] = sdiv i64 [[ADD21]], 12854// CHECK2-NEXT: [[SUB23:%.*]] = sub nsw i64 [[DIV22]], 12855// CHECK2-NEXT: store i64 [[SUB23]], ptr [[DOTCAPTURE_EXPR_15]], align 82856// CHECK2-NEXT: [[TMP13:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_15]], align 82857// CHECK2-NEXT: [[ADD25:%.*]] = add nsw i64 [[TMP13]], 12858// CHECK2-NEXT: store i64 [[ADD25]], ptr [[DOTCAPTURE_EXPR_24]], align 82859// CHECK2-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_7]], align 82860// CHECK2-NEXT: [[ADD27:%.*]] = add nsw i64 [[TMP14]], 12861// CHECK2-NEXT: store i64 [[ADD27]], ptr [[DOTCAPTURE_EXPR_26]], align 82862// CHECK2-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 82863// CHECK2-NEXT: [[SUB29:%.*]] = sub nsw i64 [[TMP15]], 02864// CHECK2-NEXT: [[DIV30:%.*]] = sdiv i64 [[SUB29]], 12865// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i64 128, [[DIV30]]2866// CHECK2-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 82867// CHECK2-NEXT: [[SUB31:%.*]] = sub nsw i64 [[TMP16]], 02868// CHECK2-NEXT: [[DIV32:%.*]] = sdiv i64 [[SUB31]], 12869// CHECK2-NEXT: [[MUL33:%.*]] = mul nsw i64 [[MUL]], [[DIV32]]2870// CHECK2-NEXT: [[MUL34:%.*]] = mul nsw i64 [[MUL33]], 1282871// CHECK2-NEXT: [[SUB35:%.*]] = sub nsw i64 [[MUL34]], 12872// CHECK2-NEXT: store i64 [[SUB35]], ptr [[DOTCAPTURE_EXPR_28]], align 82873// CHECK2-NEXT: store i32 0, ptr [[I]], align 42874// CHECK2-NEXT: store i64 0, ptr [[DOTPERMUTED_0_IV___BEGIN4]], align 82875// CHECK2-NEXT: store i64 0, ptr [[DOTPERMUTED_1_IV___BEGIN3]], align 82876// CHECK2-NEXT: store i32 0, ptr [[J]], align 42877// CHECK2-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 82878// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i64 0, [[TMP17]]2879// CHECK2-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]2880// CHECK2: land.lhs.true:2881// CHECK2-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 82882// CHECK2-NEXT: [[CMP36:%.*]] = icmp slt i64 0, [[TMP18]]2883// CHECK2-NEXT: br i1 [[CMP36]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]2884// CHECK2: omp.precond.then:2885// CHECK2-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 82886// CHECK2-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_28]], align 82887// CHECK2-NEXT: store i64 [[TMP19]], ptr [[DOTOMP_UB]], align 82888// CHECK2-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 82889// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 42890// CHECK2-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1:[0-9]+]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)2891// CHECK2-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_UB]], align 82892// CHECK2-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_28]], align 82893// CHECK2-NEXT: [[CMP41:%.*]] = icmp sgt i64 [[TMP20]], [[TMP21]]2894// CHECK2-NEXT: br i1 [[CMP41]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2895// CHECK2: cond.true:2896// CHECK2-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_28]], align 82897// CHECK2-NEXT: br label [[COND_END:%.*]]2898// CHECK2: cond.false:2899// CHECK2-NEXT: [[TMP23:%.*]] = load i64, ptr [[DOTOMP_UB]], align 82900// CHECK2-NEXT: br label [[COND_END]]2901// CHECK2: cond.end:2902// CHECK2-NEXT: [[COND:%.*]] = phi i64 [ [[TMP22]], [[COND_TRUE]] ], [ [[TMP23]], [[COND_FALSE]] ]2903// CHECK2-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 82904// CHECK2-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_LB]], align 82905// CHECK2-NEXT: store i64 [[TMP24]], ptr [[DOTOMP_IV]], align 82906// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]2907// CHECK2: omp.inner.for.cond:2908// CHECK2-NEXT: [[TMP25:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82909// CHECK2-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTOMP_UB]], align 82910// CHECK2-NEXT: [[CMP42:%.*]] = icmp sle i64 [[TMP25]], [[TMP26]]2911// CHECK2-NEXT: br i1 [[CMP42]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2912// CHECK2: omp.inner.for.body:2913// CHECK2-NEXT: [[TMP27:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82914// CHECK2-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 82915// CHECK2-NEXT: [[SUB43:%.*]] = sub nsw i64 [[TMP28]], 02916// CHECK2-NEXT: [[DIV44:%.*]] = sdiv i64 [[SUB43]], 12917// CHECK2-NEXT: [[MUL45:%.*]] = mul nsw i64 1, [[DIV44]]2918// CHECK2-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 82919// CHECK2-NEXT: [[SUB46:%.*]] = sub nsw i64 [[TMP29]], 02920// CHECK2-NEXT: [[DIV47:%.*]] = sdiv i64 [[SUB46]], 12921// CHECK2-NEXT: [[MUL48:%.*]] = mul nsw i64 [[MUL45]], [[DIV47]]2922// CHECK2-NEXT: [[MUL49:%.*]] = mul nsw i64 [[MUL48]], 1282923// CHECK2-NEXT: [[DIV50:%.*]] = sdiv i64 [[TMP27]], [[MUL49]]2924// CHECK2-NEXT: [[MUL51:%.*]] = mul nsw i64 [[DIV50]], 12925// CHECK2-NEXT: [[ADD52:%.*]] = add nsw i64 0, [[MUL51]]2926// CHECK2-NEXT: [[CONV:%.*]] = trunc i64 [[ADD52]] to i322927// CHECK2-NEXT: store i32 [[CONV]], ptr [[I37]], align 42928// CHECK2-NEXT: [[TMP30:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82929// CHECK2-NEXT: [[TMP31:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82930// CHECK2-NEXT: [[TMP32:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 82931// CHECK2-NEXT: [[SUB53:%.*]] = sub nsw i64 [[TMP32]], 02932// CHECK2-NEXT: [[DIV54:%.*]] = sdiv i64 [[SUB53]], 12933// CHECK2-NEXT: [[MUL55:%.*]] = mul nsw i64 1, [[DIV54]]2934// CHECK2-NEXT: [[TMP33:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 82935// CHECK2-NEXT: [[SUB56:%.*]] = sub nsw i64 [[TMP33]], 02936// CHECK2-NEXT: [[DIV57:%.*]] = sdiv i64 [[SUB56]], 12937// CHECK2-NEXT: [[MUL58:%.*]] = mul nsw i64 [[MUL55]], [[DIV57]]2938// CHECK2-NEXT: [[MUL59:%.*]] = mul nsw i64 [[MUL58]], 1282939// CHECK2-NEXT: [[DIV60:%.*]] = sdiv i64 [[TMP31]], [[MUL59]]2940// CHECK2-NEXT: [[TMP34:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 82941// CHECK2-NEXT: [[SUB61:%.*]] = sub nsw i64 [[TMP34]], 02942// CHECK2-NEXT: [[DIV62:%.*]] = sdiv i64 [[SUB61]], 12943// CHECK2-NEXT: [[MUL63:%.*]] = mul nsw i64 1, [[DIV62]]2944// CHECK2-NEXT: [[TMP35:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 82945// CHECK2-NEXT: [[SUB64:%.*]] = sub nsw i64 [[TMP35]], 02946// CHECK2-NEXT: [[DIV65:%.*]] = sdiv i64 [[SUB64]], 12947// CHECK2-NEXT: [[MUL66:%.*]] = mul nsw i64 [[MUL63]], [[DIV65]]2948// CHECK2-NEXT: [[MUL67:%.*]] = mul nsw i64 [[MUL66]], 1282949// CHECK2-NEXT: [[MUL68:%.*]] = mul nsw i64 [[DIV60]], [[MUL67]]2950// CHECK2-NEXT: [[SUB69:%.*]] = sub nsw i64 [[TMP30]], [[MUL68]]2951// CHECK2-NEXT: [[TMP36:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 82952// CHECK2-NEXT: [[SUB70:%.*]] = sub nsw i64 [[TMP36]], 02953// CHECK2-NEXT: [[DIV71:%.*]] = sdiv i64 [[SUB70]], 12954// CHECK2-NEXT: [[MUL72:%.*]] = mul nsw i64 1, [[DIV71]]2955// CHECK2-NEXT: [[MUL73:%.*]] = mul nsw i64 [[MUL72]], 1282956// CHECK2-NEXT: [[DIV74:%.*]] = sdiv i64 [[SUB69]], [[MUL73]]2957// CHECK2-NEXT: [[MUL75:%.*]] = mul nsw i64 [[DIV74]], 12958// CHECK2-NEXT: [[ADD76:%.*]] = add nsw i64 0, [[MUL75]]2959// CHECK2-NEXT: store i64 [[ADD76]], ptr [[DOTPERMUTED_0_IV___BEGIN438]], align 82960// CHECK2-NEXT: [[TMP37:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82961// CHECK2-NEXT: [[TMP38:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82962// CHECK2-NEXT: [[TMP39:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 82963// CHECK2-NEXT: [[SUB77:%.*]] = sub nsw i64 [[TMP39]], 02964// CHECK2-NEXT: [[DIV78:%.*]] = sdiv i64 [[SUB77]], 12965// CHECK2-NEXT: [[MUL79:%.*]] = mul nsw i64 1, [[DIV78]]2966// CHECK2-NEXT: [[TMP40:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 82967// CHECK2-NEXT: [[SUB80:%.*]] = sub nsw i64 [[TMP40]], 02968// CHECK2-NEXT: [[DIV81:%.*]] = sdiv i64 [[SUB80]], 12969// CHECK2-NEXT: [[MUL82:%.*]] = mul nsw i64 [[MUL79]], [[DIV81]]2970// CHECK2-NEXT: [[MUL83:%.*]] = mul nsw i64 [[MUL82]], 1282971// CHECK2-NEXT: [[DIV84:%.*]] = sdiv i64 [[TMP38]], [[MUL83]]2972// CHECK2-NEXT: [[TMP41:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 82973// CHECK2-NEXT: [[SUB85:%.*]] = sub nsw i64 [[TMP41]], 02974// CHECK2-NEXT: [[DIV86:%.*]] = sdiv i64 [[SUB85]], 12975// CHECK2-NEXT: [[MUL87:%.*]] = mul nsw i64 1, [[DIV86]]2976// CHECK2-NEXT: [[TMP42:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 82977// CHECK2-NEXT: [[SUB88:%.*]] = sub nsw i64 [[TMP42]], 02978// CHECK2-NEXT: [[DIV89:%.*]] = sdiv i64 [[SUB88]], 12979// CHECK2-NEXT: [[MUL90:%.*]] = mul nsw i64 [[MUL87]], [[DIV89]]2980// CHECK2-NEXT: [[MUL91:%.*]] = mul nsw i64 [[MUL90]], 1282981// CHECK2-NEXT: [[MUL92:%.*]] = mul nsw i64 [[DIV84]], [[MUL91]]2982// CHECK2-NEXT: [[SUB93:%.*]] = sub nsw i64 [[TMP37]], [[MUL92]]2983// CHECK2-NEXT: [[TMP43:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82984// CHECK2-NEXT: [[TMP44:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82985// CHECK2-NEXT: [[TMP45:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 82986// CHECK2-NEXT: [[SUB94:%.*]] = sub nsw i64 [[TMP45]], 02987// CHECK2-NEXT: [[DIV95:%.*]] = sdiv i64 [[SUB94]], 12988// CHECK2-NEXT: [[MUL96:%.*]] = mul nsw i64 1, [[DIV95]]2989// CHECK2-NEXT: [[TMP46:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 82990// CHECK2-NEXT: [[SUB97:%.*]] = sub nsw i64 [[TMP46]], 02991// CHECK2-NEXT: [[DIV98:%.*]] = sdiv i64 [[SUB97]], 12992// CHECK2-NEXT: [[MUL99:%.*]] = mul nsw i64 [[MUL96]], [[DIV98]]2993// CHECK2-NEXT: [[MUL100:%.*]] = mul nsw i64 [[MUL99]], 1282994// CHECK2-NEXT: [[DIV101:%.*]] = sdiv i64 [[TMP44]], [[MUL100]]2995// CHECK2-NEXT: [[TMP47:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 82996// CHECK2-NEXT: [[SUB102:%.*]] = sub nsw i64 [[TMP47]], 02997// CHECK2-NEXT: [[DIV103:%.*]] = sdiv i64 [[SUB102]], 12998// CHECK2-NEXT: [[MUL104:%.*]] = mul nsw i64 1, [[DIV103]]2999// CHECK2-NEXT: [[TMP48:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 83000// CHECK2-NEXT: [[SUB105:%.*]] = sub nsw i64 [[TMP48]], 03001// CHECK2-NEXT: [[DIV106:%.*]] = sdiv i64 [[SUB105]], 13002// CHECK2-NEXT: [[MUL107:%.*]] = mul nsw i64 [[MUL104]], [[DIV106]]3003// CHECK2-NEXT: [[MUL108:%.*]] = mul nsw i64 [[MUL107]], 1283004// CHECK2-NEXT: [[MUL109:%.*]] = mul nsw i64 [[DIV101]], [[MUL108]]3005// CHECK2-NEXT: [[SUB110:%.*]] = sub nsw i64 [[TMP43]], [[MUL109]]3006// CHECK2-NEXT: [[TMP49:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 83007// CHECK2-NEXT: [[SUB111:%.*]] = sub nsw i64 [[TMP49]], 03008// CHECK2-NEXT: [[DIV112:%.*]] = sdiv i64 [[SUB111]], 13009// CHECK2-NEXT: [[MUL113:%.*]] = mul nsw i64 1, [[DIV112]]3010// CHECK2-NEXT: [[MUL114:%.*]] = mul nsw i64 [[MUL113]], 1283011// CHECK2-NEXT: [[DIV115:%.*]] = sdiv i64 [[SUB110]], [[MUL114]]3012// CHECK2-NEXT: [[TMP50:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 83013// CHECK2-NEXT: [[SUB116:%.*]] = sub nsw i64 [[TMP50]], 03014// CHECK2-NEXT: [[DIV117:%.*]] = sdiv i64 [[SUB116]], 13015// CHECK2-NEXT: [[MUL118:%.*]] = mul nsw i64 1, [[DIV117]]3016// CHECK2-NEXT: [[MUL119:%.*]] = mul nsw i64 [[MUL118]], 1283017// CHECK2-NEXT: [[MUL120:%.*]] = mul nsw i64 [[DIV115]], [[MUL119]]3018// CHECK2-NEXT: [[SUB121:%.*]] = sub nsw i64 [[SUB93]], [[MUL120]]3019// CHECK2-NEXT: [[DIV122:%.*]] = sdiv i64 [[SUB121]], 1283020// CHECK2-NEXT: [[MUL123:%.*]] = mul nsw i64 [[DIV122]], 13021// CHECK2-NEXT: [[ADD124:%.*]] = add nsw i64 0, [[MUL123]]3022// CHECK2-NEXT: store i64 [[ADD124]], ptr [[DOTPERMUTED_1_IV___BEGIN339]], align 83023// CHECK2-NEXT: [[TMP51:%.*]] = load i64, ptr [[DOTOMP_IV]], align 83024// CHECK2-NEXT: [[TMP52:%.*]] = load i64, ptr [[DOTOMP_IV]], align 83025// CHECK2-NEXT: [[TMP53:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 83026// CHECK2-NEXT: [[SUB125:%.*]] = sub nsw i64 [[TMP53]], 03027// CHECK2-NEXT: [[DIV126:%.*]] = sdiv i64 [[SUB125]], 13028// CHECK2-NEXT: [[MUL127:%.*]] = mul nsw i64 1, [[DIV126]]3029// CHECK2-NEXT: [[TMP54:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 83030// CHECK2-NEXT: [[SUB128:%.*]] = sub nsw i64 [[TMP54]], 03031// CHECK2-NEXT: [[DIV129:%.*]] = sdiv i64 [[SUB128]], 13032// CHECK2-NEXT: [[MUL130:%.*]] = mul nsw i64 [[MUL127]], [[DIV129]]3033// CHECK2-NEXT: [[MUL131:%.*]] = mul nsw i64 [[MUL130]], 1283034// CHECK2-NEXT: [[DIV132:%.*]] = sdiv i64 [[TMP52]], [[MUL131]]3035// CHECK2-NEXT: [[TMP55:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 83036// CHECK2-NEXT: [[SUB133:%.*]] = sub nsw i64 [[TMP55]], 03037// CHECK2-NEXT: [[DIV134:%.*]] = sdiv i64 [[SUB133]], 13038// CHECK2-NEXT: [[MUL135:%.*]] = mul nsw i64 1, [[DIV134]]3039// CHECK2-NEXT: [[TMP56:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 83040// CHECK2-NEXT: [[SUB136:%.*]] = sub nsw i64 [[TMP56]], 03041// CHECK2-NEXT: [[DIV137:%.*]] = sdiv i64 [[SUB136]], 13042// CHECK2-NEXT: [[MUL138:%.*]] = mul nsw i64 [[MUL135]], [[DIV137]]3043// CHECK2-NEXT: [[MUL139:%.*]] = mul nsw i64 [[MUL138]], 1283044// CHECK2-NEXT: [[MUL140:%.*]] = mul nsw i64 [[DIV132]], [[MUL139]]3045// CHECK2-NEXT: [[SUB141:%.*]] = sub nsw i64 [[TMP51]], [[MUL140]]3046// CHECK2-NEXT: [[TMP57:%.*]] = load i64, ptr [[DOTOMP_IV]], align 83047// CHECK2-NEXT: [[TMP58:%.*]] = load i64, ptr [[DOTOMP_IV]], align 83048// CHECK2-NEXT: [[TMP59:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 83049// CHECK2-NEXT: [[SUB142:%.*]] = sub nsw i64 [[TMP59]], 03050// CHECK2-NEXT: [[DIV143:%.*]] = sdiv i64 [[SUB142]], 13051// CHECK2-NEXT: [[MUL144:%.*]] = mul nsw i64 1, [[DIV143]]3052// CHECK2-NEXT: [[TMP60:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 83053// CHECK2-NEXT: [[SUB145:%.*]] = sub nsw i64 [[TMP60]], 03054// CHECK2-NEXT: [[DIV146:%.*]] = sdiv i64 [[SUB145]], 13055// CHECK2-NEXT: [[MUL147:%.*]] = mul nsw i64 [[MUL144]], [[DIV146]]3056// CHECK2-NEXT: [[MUL148:%.*]] = mul nsw i64 [[MUL147]], 1283057// CHECK2-NEXT: [[DIV149:%.*]] = sdiv i64 [[TMP58]], [[MUL148]]3058// CHECK2-NEXT: [[TMP61:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 83059// CHECK2-NEXT: [[SUB150:%.*]] = sub nsw i64 [[TMP61]], 03060// CHECK2-NEXT: [[DIV151:%.*]] = sdiv i64 [[SUB150]], 13061// CHECK2-NEXT: [[MUL152:%.*]] = mul nsw i64 1, [[DIV151]]3062// CHECK2-NEXT: [[TMP62:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 83063// CHECK2-NEXT: [[SUB153:%.*]] = sub nsw i64 [[TMP62]], 03064// CHECK2-NEXT: [[DIV154:%.*]] = sdiv i64 [[SUB153]], 13065// CHECK2-NEXT: [[MUL155:%.*]] = mul nsw i64 [[MUL152]], [[DIV154]]3066// CHECK2-NEXT: [[MUL156:%.*]] = mul nsw i64 [[MUL155]], 1283067// CHECK2-NEXT: [[MUL157:%.*]] = mul nsw i64 [[DIV149]], [[MUL156]]3068// CHECK2-NEXT: [[SUB158:%.*]] = sub nsw i64 [[TMP57]], [[MUL157]]3069// CHECK2-NEXT: [[TMP63:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 83070// CHECK2-NEXT: [[SUB159:%.*]] = sub nsw i64 [[TMP63]], 03071// CHECK2-NEXT: [[DIV160:%.*]] = sdiv i64 [[SUB159]], 13072// CHECK2-NEXT: [[MUL161:%.*]] = mul nsw i64 1, [[DIV160]]3073// CHECK2-NEXT: [[MUL162:%.*]] = mul nsw i64 [[MUL161]], 1283074// CHECK2-NEXT: [[DIV163:%.*]] = sdiv i64 [[SUB158]], [[MUL162]]3075// CHECK2-NEXT: [[TMP64:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 83076// CHECK2-NEXT: [[SUB164:%.*]] = sub nsw i64 [[TMP64]], 03077// CHECK2-NEXT: [[DIV165:%.*]] = sdiv i64 [[SUB164]], 13078// CHECK2-NEXT: [[MUL166:%.*]] = mul nsw i64 1, [[DIV165]]3079// CHECK2-NEXT: [[MUL167:%.*]] = mul nsw i64 [[MUL166]], 1283080// CHECK2-NEXT: [[MUL168:%.*]] = mul nsw i64 [[DIV163]], [[MUL167]]3081// CHECK2-NEXT: [[SUB169:%.*]] = sub nsw i64 [[SUB141]], [[MUL168]]3082// CHECK2-NEXT: [[TMP65:%.*]] = load i64, ptr [[DOTOMP_IV]], align 83083// CHECK2-NEXT: [[TMP66:%.*]] = load i64, ptr [[DOTOMP_IV]], align 83084// CHECK2-NEXT: [[TMP67:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 83085// CHECK2-NEXT: [[SUB170:%.*]] = sub nsw i64 [[TMP67]], 03086// CHECK2-NEXT: [[DIV171:%.*]] = sdiv i64 [[SUB170]], 13087// CHECK2-NEXT: [[MUL172:%.*]] = mul nsw i64 1, [[DIV171]]3088// CHECK2-NEXT: [[TMP68:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 83089// CHECK2-NEXT: [[SUB173:%.*]] = sub nsw i64 [[TMP68]], 03090// CHECK2-NEXT: [[DIV174:%.*]] = sdiv i64 [[SUB173]], 13091// CHECK2-NEXT: [[MUL175:%.*]] = mul nsw i64 [[MUL172]], [[DIV174]]3092// CHECK2-NEXT: [[MUL176:%.*]] = mul nsw i64 [[MUL175]], 1283093// CHECK2-NEXT: [[DIV177:%.*]] = sdiv i64 [[TMP66]], [[MUL176]]3094// CHECK2-NEXT: [[TMP69:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 83095// CHECK2-NEXT: [[SUB178:%.*]] = sub nsw i64 [[TMP69]], 03096// CHECK2-NEXT: [[DIV179:%.*]] = sdiv i64 [[SUB178]], 13097// CHECK2-NEXT: [[MUL180:%.*]] = mul nsw i64 1, [[DIV179]]3098// CHECK2-NEXT: [[TMP70:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 83099// CHECK2-NEXT: [[SUB181:%.*]] = sub nsw i64 [[TMP70]], 03100// CHECK2-NEXT: [[DIV182:%.*]] = sdiv i64 [[SUB181]], 13101// CHECK2-NEXT: [[MUL183:%.*]] = mul nsw i64 [[MUL180]], [[DIV182]]3102// CHECK2-NEXT: [[MUL184:%.*]] = mul nsw i64 [[MUL183]], 1283103// CHECK2-NEXT: [[MUL185:%.*]] = mul nsw i64 [[DIV177]], [[MUL184]]3104// CHECK2-NEXT: [[SUB186:%.*]] = sub nsw i64 [[TMP65]], [[MUL185]]3105// CHECK2-NEXT: [[TMP71:%.*]] = load i64, ptr [[DOTOMP_IV]], align 83106// CHECK2-NEXT: [[TMP72:%.*]] = load i64, ptr [[DOTOMP_IV]], align 83107// CHECK2-NEXT: [[TMP73:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 83108// CHECK2-NEXT: [[SUB187:%.*]] = sub nsw i64 [[TMP73]], 03109// CHECK2-NEXT: [[DIV188:%.*]] = sdiv i64 [[SUB187]], 13110// CHECK2-NEXT: [[MUL189:%.*]] = mul nsw i64 1, [[DIV188]]3111// CHECK2-NEXT: [[TMP74:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 83112// CHECK2-NEXT: [[SUB190:%.*]] = sub nsw i64 [[TMP74]], 03113// CHECK2-NEXT: [[DIV191:%.*]] = sdiv i64 [[SUB190]], 13114// CHECK2-NEXT: [[MUL192:%.*]] = mul nsw i64 [[MUL189]], [[DIV191]]3115// CHECK2-NEXT: [[MUL193:%.*]] = mul nsw i64 [[MUL192]], 1283116// CHECK2-NEXT: [[DIV194:%.*]] = sdiv i64 [[TMP72]], [[MUL193]]3117// CHECK2-NEXT: [[TMP75:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 83118// CHECK2-NEXT: [[SUB195:%.*]] = sub nsw i64 [[TMP75]], 03119// CHECK2-NEXT: [[DIV196:%.*]] = sdiv i64 [[SUB195]], 13120// CHECK2-NEXT: [[MUL197:%.*]] = mul nsw i64 1, [[DIV196]]3121// CHECK2-NEXT: [[TMP76:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 83122// CHECK2-NEXT: [[SUB198:%.*]] = sub nsw i64 [[TMP76]], 03123// CHECK2-NEXT: [[DIV199:%.*]] = sdiv i64 [[SUB198]], 13124// CHECK2-NEXT: [[MUL200:%.*]] = mul nsw i64 [[MUL197]], [[DIV199]]3125// CHECK2-NEXT: [[MUL201:%.*]] = mul nsw i64 [[MUL200]], 1283126// CHECK2-NEXT: [[MUL202:%.*]] = mul nsw i64 [[DIV194]], [[MUL201]]3127// CHECK2-NEXT: [[SUB203:%.*]] = sub nsw i64 [[TMP71]], [[MUL202]]3128// CHECK2-NEXT: [[TMP77:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 83129// CHECK2-NEXT: [[SUB204:%.*]] = sub nsw i64 [[TMP77]], 03130// CHECK2-NEXT: [[DIV205:%.*]] = sdiv i64 [[SUB204]], 13131// CHECK2-NEXT: [[MUL206:%.*]] = mul nsw i64 1, [[DIV205]]3132// CHECK2-NEXT: [[MUL207:%.*]] = mul nsw i64 [[MUL206]], 1283133// CHECK2-NEXT: [[DIV208:%.*]] = sdiv i64 [[SUB203]], [[MUL207]]3134// CHECK2-NEXT: [[TMP78:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 83135// CHECK2-NEXT: [[SUB209:%.*]] = sub nsw i64 [[TMP78]], 03136// CHECK2-NEXT: [[DIV210:%.*]] = sdiv i64 [[SUB209]], 13137// CHECK2-NEXT: [[MUL211:%.*]] = mul nsw i64 1, [[DIV210]]3138// CHECK2-NEXT: [[MUL212:%.*]] = mul nsw i64 [[MUL211]], 1283139// CHECK2-NEXT: [[MUL213:%.*]] = mul nsw i64 [[DIV208]], [[MUL212]]3140// CHECK2-NEXT: [[SUB214:%.*]] = sub nsw i64 [[SUB186]], [[MUL213]]3141// CHECK2-NEXT: [[DIV215:%.*]] = sdiv i64 [[SUB214]], 1283142// CHECK2-NEXT: [[MUL216:%.*]] = mul nsw i64 [[DIV215]], 1283143// CHECK2-NEXT: [[SUB217:%.*]] = sub nsw i64 [[SUB169]], [[MUL216]]3144// CHECK2-NEXT: [[MUL218:%.*]] = mul nsw i64 [[SUB217]], 13145// CHECK2-NEXT: [[ADD219:%.*]] = add nsw i64 0, [[MUL218]]3146// CHECK2-NEXT: [[CONV220:%.*]] = trunc i64 [[ADD219]] to i323147// CHECK2-NEXT: store i32 [[CONV220]], ptr [[J40]], align 43148// CHECK2-NEXT: [[TMP79:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_12]], align 83149// CHECK2-NEXT: [[TMP80:%.*]] = load i64, ptr [[DOTPERMUTED_0_IV___BEGIN438]], align 83150// CHECK2-NEXT: [[MUL221:%.*]] = mul nsw i64 [[TMP80]], 13151// CHECK2-NEXT: [[ADD_PTR222:%.*]] = getelementptr inbounds double, ptr [[TMP79]], i64 [[MUL221]]3152// CHECK2-NEXT: store ptr [[ADD_PTR222]], ptr [[__BEGIN4]], align 83153// CHECK2-NEXT: [[TMP81:%.*]] = load ptr, ptr [[__BEGIN4]], align 83154// CHECK2-NEXT: store ptr [[TMP81]], ptr [[BB]], align 83155// CHECK2-NEXT: [[TMP82:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 83156// CHECK2-NEXT: [[TMP83:%.*]] = load i64, ptr [[DOTPERMUTED_1_IV___BEGIN339]], align 83157// CHECK2-NEXT: [[MUL223:%.*]] = mul nsw i64 [[TMP83]], 13158// CHECK2-NEXT: [[ADD_PTR224:%.*]] = getelementptr inbounds double, ptr [[TMP82]], i64 [[MUL223]]3159// CHECK2-NEXT: store ptr [[ADD_PTR224]], ptr [[__BEGIN3]], align 83160// CHECK2-NEXT: [[TMP84:%.*]] = load ptr, ptr [[__BEGIN3]], align 83161// CHECK2-NEXT: [[TMP85:%.*]] = load double, ptr [[TMP84]], align 83162// CHECK2-NEXT: store double [[TMP85]], ptr [[AA]], align 83163// CHECK2-NEXT: [[TMP86:%.*]] = load i32, ptr [[I37]], align 43164// CHECK2-NEXT: [[TMP87:%.*]] = load double, ptr [[C]], align 83165// CHECK2-NEXT: [[TMP88:%.*]] = load double, ptr [[AA]], align 83166// CHECK2-NEXT: [[TMP89:%.*]] = load double, ptr [[D]], align 83167// CHECK2-NEXT: [[TMP90:%.*]] = load ptr, ptr [[BB]], align 83168// CHECK2-NEXT: [[TMP91:%.*]] = load double, ptr [[TMP90]], align 83169// CHECK2-NEXT: [[TMP92:%.*]] = load i32, ptr [[J40]], align 43170// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP86]], double noundef [[TMP87]], double noundef [[TMP88]], double noundef [[TMP89]], double noundef [[TMP91]], i32 noundef [[TMP92]])3171// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]3172// CHECK2: omp.body.continue:3173// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]3174// CHECK2: omp.inner.for.inc:3175// CHECK2-NEXT: [[TMP93:%.*]] = load i64, ptr [[DOTOMP_IV]], align 83176// CHECK2-NEXT: [[ADD225:%.*]] = add nsw i64 [[TMP93]], 13177// CHECK2-NEXT: store i64 [[ADD225]], ptr [[DOTOMP_IV]], align 83178// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]3179// CHECK2: omp.inner.for.end:3180// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]3181// CHECK2: omp.loop.exit:3182// CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]])3183// CHECK2-NEXT: br label [[OMP_PRECOND_END]]3184// CHECK2: omp.precond.end:3185// CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP0]])3186// CHECK2-NEXT: ret void3187//3188//3189// CHECK2-LABEL: define {{[^@]+}}@foo23190// CHECK2-SAME: (i32 noundef [[START1:%.*]], i32 noundef [[START2:%.*]], i32 noundef [[END1:%.*]], i32 noundef [[END2:%.*]], i32 noundef [[STEP1:%.*]], i32 noundef [[STEP2:%.*]]) #[[ATTR0]] {3191// CHECK2-NEXT: entry:3192// CHECK2-NEXT: [[START1_ADDR:%.*]] = alloca i32, align 43193// CHECK2-NEXT: [[START2_ADDR:%.*]] = alloca i32, align 43194// CHECK2-NEXT: [[END1_ADDR:%.*]] = alloca i32, align 43195// CHECK2-NEXT: [[END2_ADDR:%.*]] = alloca i32, align 43196// CHECK2-NEXT: [[STEP1_ADDR:%.*]] = alloca i32, align 43197// CHECK2-NEXT: [[STEP2_ADDR:%.*]] = alloca i32, align 43198// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 43199// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 43200// CHECK2-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 43201// CHECK2-NEXT: [[DOTNEW_STEP:%.*]] = alloca i32, align 43202// CHECK2-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 43203// CHECK2-NEXT: [[J:%.*]] = alloca i32, align 43204// CHECK2-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 43205// CHECK2-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i32, align 43206// CHECK2-NEXT: [[DOTNEW_STEP7:%.*]] = alloca i32, align 43207// CHECK2-NEXT: [[DOTCAPTURE_EXPR_8:%.*]] = alloca i32, align 43208// CHECK2-NEXT: [[DOTPERMUTED_0_IV_J:%.*]] = alloca i32, align 43209// CHECK2-NEXT: [[DOTPERMUTED_1_IV_I:%.*]] = alloca i32, align 43210// CHECK2-NEXT: store i32 [[START1]], ptr [[START1_ADDR]], align 43211// CHECK2-NEXT: store i32 [[START2]], ptr [[START2_ADDR]], align 43212// CHECK2-NEXT: store i32 [[END1]], ptr [[END1_ADDR]], align 43213// CHECK2-NEXT: store i32 [[END2]], ptr [[END2_ADDR]], align 43214// CHECK2-NEXT: store i32 [[STEP1]], ptr [[STEP1_ADDR]], align 43215// CHECK2-NEXT: store i32 [[STEP2]], ptr [[STEP2_ADDR]], align 43216// CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[START1_ADDR]], align 43217// CHECK2-NEXT: store i32 [[TMP0]], ptr [[I]], align 43218// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[START1_ADDR]], align 43219// CHECK2-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 43220// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[END1_ADDR]], align 43221// CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_1]], align 43222// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[STEP1_ADDR]], align 43223// CHECK2-NEXT: store i32 [[TMP3]], ptr [[DOTNEW_STEP]], align 43224// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 43225// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 43226// CHECK2-NEXT: [[SUB:%.*]] = sub i32 [[TMP4]], [[TMP5]]3227// CHECK2-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 13228// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 43229// CHECK2-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], [[TMP6]]3230// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 43231// CHECK2-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], [[TMP7]]3232// CHECK2-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 13233// CHECK2-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 43234// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[START2_ADDR]], align 43235// CHECK2-NEXT: store i32 [[TMP8]], ptr [[J]], align 43236// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[START2_ADDR]], align 43237// CHECK2-NEXT: store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR_5]], align 43238// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[END2_ADDR]], align 43239// CHECK2-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR_6]], align 43240// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[STEP2_ADDR]], align 43241// CHECK2-NEXT: store i32 [[TMP11]], ptr [[DOTNEW_STEP7]], align 43242// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 43243// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 43244// CHECK2-NEXT: [[SUB9:%.*]] = sub i32 [[TMP12]], [[TMP13]]3245// CHECK2-NEXT: [[SUB10:%.*]] = sub i32 [[SUB9]], 13246// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 43247// CHECK2-NEXT: [[ADD11:%.*]] = add i32 [[SUB10]], [[TMP14]]3248// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 43249// CHECK2-NEXT: [[DIV12:%.*]] = udiv i32 [[ADD11]], [[TMP15]]3250// CHECK2-NEXT: [[SUB13:%.*]] = sub i32 [[DIV12]], 13251// CHECK2-NEXT: store i32 [[SUB13]], ptr [[DOTCAPTURE_EXPR_8]], align 43252// CHECK2-NEXT: store i32 0, ptr [[DOTPERMUTED_0_IV_J]], align 43253// CHECK2-NEXT: br label [[FOR_COND:%.*]]3254// CHECK2: for.cond:3255// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 43256// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_8]], align 43257// CHECK2-NEXT: [[ADD14:%.*]] = add i32 [[TMP17]], 13258// CHECK2-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP16]], [[ADD14]]3259// CHECK2-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END24:%.*]]3260// CHECK2: for.body:3261// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 43262// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 43263// CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 43264// CHECK2-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], [[TMP20]]3265// CHECK2-NEXT: [[ADD15:%.*]] = add i32 [[TMP18]], [[MUL]]3266// CHECK2-NEXT: store i32 [[ADD15]], ptr [[J]], align 43267// CHECK2-NEXT: store i32 0, ptr [[DOTPERMUTED_1_IV_I]], align 43268// CHECK2-NEXT: br label [[FOR_COND16:%.*]]3269// CHECK2: for.cond16:3270// CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 43271// CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 43272// CHECK2-NEXT: [[ADD17:%.*]] = add i32 [[TMP22]], 13273// CHECK2-NEXT: [[CMP18:%.*]] = icmp ult i32 [[TMP21]], [[ADD17]]3274// CHECK2-NEXT: br i1 [[CMP18]], label [[FOR_BODY19:%.*]], label [[FOR_END:%.*]]3275// CHECK2: for.body19:3276// CHECK2-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 43277// CHECK2-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 43278// CHECK2-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 43279// CHECK2-NEXT: [[MUL20:%.*]] = mul i32 [[TMP24]], [[TMP25]]3280// CHECK2-NEXT: [[ADD21:%.*]] = add i32 [[TMP23]], [[MUL20]]3281// CHECK2-NEXT: store i32 [[ADD21]], ptr [[I]], align 43282// CHECK2-NEXT: [[TMP26:%.*]] = load i32, ptr [[I]], align 43283// CHECK2-NEXT: [[TMP27:%.*]] = load i32, ptr [[J]], align 43284// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP26]], i32 noundef [[TMP27]])3285// CHECK2-NEXT: br label [[FOR_INC:%.*]]3286// CHECK2: for.inc:3287// CHECK2-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 43288// CHECK2-NEXT: [[INC:%.*]] = add i32 [[TMP28]], 13289// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTPERMUTED_1_IV_I]], align 43290// CHECK2-NEXT: br label [[FOR_COND16]], !llvm.loop [[LOOP5:![0-9]+]]3291// CHECK2: for.end:3292// CHECK2-NEXT: br label [[FOR_INC22:%.*]]3293// CHECK2: for.inc22:3294// CHECK2-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 43295// CHECK2-NEXT: [[INC23:%.*]] = add i32 [[TMP29]], 13296// CHECK2-NEXT: store i32 [[INC23]], ptr [[DOTPERMUTED_0_IV_J]], align 43297// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]3298// CHECK2: for.end24:3299// CHECK2-NEXT: ret void3300//3301//3302// CHECK2-LABEL: define {{[^@]+}}@foo33303// CHECK2-SAME: () #[[ATTR0]] {3304// CHECK2-NEXT: entry:3305// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 43306// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 43307// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 43308// CHECK2-NEXT: [[J:%.*]] = alloca i32, align 43309// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 43310// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 43311// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 43312// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 43313// CHECK2-NEXT: [[DOTPERMUTED_0_IV_J:%.*]] = alloca i32, align 43314// CHECK2-NEXT: [[DOTPERMUTED_1_IV_I:%.*]] = alloca i32, align 43315// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])3316// CHECK2-NEXT: store i32 7, ptr [[I]], align 43317// CHECK2-NEXT: store i32 7, ptr [[J]], align 43318// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 43319// CHECK2-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 43320// CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 43321// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 43322// CHECK2-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)3323// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43324// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 33325// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]3326// CHECK2: cond.true:3327// CHECK2-NEXT: br label [[COND_END:%.*]]3328// CHECK2: cond.false:3329// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43330// CHECK2-NEXT: br label [[COND_END]]3331// CHECK2: cond.end:3332// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ]3333// CHECK2-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 43334// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 43335// CHECK2-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 43336// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]3337// CHECK2: omp.inner.for.cond:3338// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43339// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43340// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]3341// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]3342// CHECK2: omp.inner.for.body:3343// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43344// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 13345// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]3346// CHECK2-NEXT: store i32 [[ADD]], ptr [[DOTPERMUTED_0_IV_J]], align 43347// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 43348// CHECK2-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP7]], 33349// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 7, [[MUL2]]3350// CHECK2-NEXT: store i32 [[ADD3]], ptr [[J]], align 43351// CHECK2-NEXT: store i32 0, ptr [[DOTPERMUTED_1_IV_I]], align 43352// CHECK2-NEXT: br label [[FOR_COND:%.*]]3353// CHECK2: for.cond:3354// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 43355// CHECK2-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP8]], 43356// CHECK2-NEXT: br i1 [[CMP4]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]3357// CHECK2: for.body:3358// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 43359// CHECK2-NEXT: [[MUL5:%.*]] = mul nsw i32 [[TMP9]], 33360// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 7, [[MUL5]]3361// CHECK2-NEXT: store i32 [[ADD6]], ptr [[I]], align 43362// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 43363// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[J]], align 43364// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP10]], i32 noundef [[TMP11]])3365// CHECK2-NEXT: br label [[FOR_INC:%.*]]3366// CHECK2: for.inc:3367// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 43368// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 13369// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTPERMUTED_1_IV_I]], align 43370// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]3371// CHECK2: for.end:3372// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]3373// CHECK2: omp.body.continue:3374// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]3375// CHECK2: omp.inner.for.inc:3376// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43377// CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP13]], 13378// CHECK2-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 43379// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]3380// CHECK2: omp.inner.for.end:3381// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]3382// CHECK2: omp.loop.exit:3383// CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]])3384// CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]])3385// CHECK2-NEXT: ret void3386//3387//3388// CHECK2-LABEL: define {{[^@]+}}@foo43389// CHECK2-SAME: () #[[ATTR0]] {3390// CHECK2-NEXT: entry:3391// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 43392// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 43393// CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 43394// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 43395// CHECK2-NEXT: [[J:%.*]] = alloca i32, align 43396// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 43397// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 43398// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 43399// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 43400// CHECK2-NEXT: [[K:%.*]] = alloca i32, align 43401// CHECK2-NEXT: [[DOTPERMUTED_0_IV_J:%.*]] = alloca i32, align 43402// CHECK2-NEXT: [[DOTPERMUTED_1_IV_I:%.*]] = alloca i32, align 43403// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])3404// CHECK2-NEXT: store i32 7, ptr [[I]], align 43405// CHECK2-NEXT: store i32 7, ptr [[J]], align 43406// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 43407// CHECK2-NEXT: store i32 15, ptr [[DOTOMP_UB]], align 43408// CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 43409// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 43410// CHECK2-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)3411// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43412// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 153413// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]3414// CHECK2: cond.true:3415// CHECK2-NEXT: br label [[COND_END:%.*]]3416// CHECK2: cond.false:3417// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43418// CHECK2-NEXT: br label [[COND_END]]3419// CHECK2: cond.end:3420// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 15, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ]3421// CHECK2-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 43422// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 43423// CHECK2-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 43424// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]3425// CHECK2: omp.inner.for.cond:3426// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43427// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43428// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]3429// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]3430// CHECK2: omp.inner.for.body:3431// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43432// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP6]], 43433// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 33434// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 7, [[MUL]]3435// CHECK2-NEXT: store i32 [[ADD]], ptr [[K]], align 43436// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43437// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43438// CHECK2-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP8]], 43439// CHECK2-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 43440// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], [[MUL4]]3441// CHECK2-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 13442// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]3443// CHECK2-NEXT: store i32 [[ADD6]], ptr [[DOTPERMUTED_0_IV_J]], align 43444// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 43445// CHECK2-NEXT: [[MUL7:%.*]] = mul nsw i32 [[TMP9]], 33446// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 7, [[MUL7]]3447// CHECK2-NEXT: store i32 [[ADD8]], ptr [[J]], align 43448// CHECK2-NEXT: store i32 0, ptr [[DOTPERMUTED_1_IV_I]], align 43449// CHECK2-NEXT: br label [[FOR_COND:%.*]]3450// CHECK2: for.cond:3451// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 43452// CHECK2-NEXT: [[CMP9:%.*]] = icmp slt i32 [[TMP10]], 43453// CHECK2-NEXT: br i1 [[CMP9]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]3454// CHECK2: for.body:3455// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 43456// CHECK2-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP11]], 33457// CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 7, [[MUL10]]3458// CHECK2-NEXT: store i32 [[ADD11]], ptr [[I]], align 43459// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 43460// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[J]], align 43461// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP12]], i32 noundef [[TMP13]])3462// CHECK2-NEXT: br label [[FOR_INC:%.*]]3463// CHECK2: for.inc:3464// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 43465// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 13466// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTPERMUTED_1_IV_I]], align 43467// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]3468// CHECK2: for.end:3469// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]3470// CHECK2: omp.body.continue:3471// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]3472// CHECK2: omp.inner.for.inc:3473// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43474// CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP15]], 13475// CHECK2-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 43476// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]3477// CHECK2: omp.inner.for.end:3478// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]3479// CHECK2: omp.loop.exit:3480// CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]])3481// CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]])3482// CHECK2-NEXT: ret void3483//3484//3485// CHECK2-LABEL: define {{[^@]+}}@foo53486// CHECK2-SAME: () #[[ATTR0]] {3487// CHECK2-NEXT: entry:3488// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 43489// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 43490// CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 43491// CHECK2-NEXT: [[_TMP2:%.*]] = alloca i32, align 43492// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 43493// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 43494// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 43495// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 43496// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 43497// CHECK2-NEXT: [[J:%.*]] = alloca i32, align 43498// CHECK2-NEXT: [[K:%.*]] = alloca i32, align 43499// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])3500// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 43501// CHECK2-NEXT: store i32 63, ptr [[DOTOMP_UB]], align 43502// CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 43503// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 43504// CHECK2-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)3505// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43506// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 633507// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]3508// CHECK2: cond.true:3509// CHECK2-NEXT: br label [[COND_END:%.*]]3510// CHECK2: cond.false:3511// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43512// CHECK2-NEXT: br label [[COND_END]]3513// CHECK2: cond.end:3514// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 63, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ]3515// CHECK2-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 43516// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 43517// CHECK2-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 43518// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]3519// CHECK2: omp.inner.for.cond:3520// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43521// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43522// CHECK2-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]3523// CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]3524// CHECK2: omp.inner.for.body:3525// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43526// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP6]], 163527// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 33528// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 7, [[MUL]]3529// CHECK2-NEXT: store i32 [[ADD]], ptr [[I]], align 43530// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43531// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43532// CHECK2-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP8]], 163533// CHECK2-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 163534// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], [[MUL5]]3535// CHECK2-NEXT: [[DIV6:%.*]] = sdiv i32 [[SUB]], 43536// CHECK2-NEXT: [[MUL7:%.*]] = mul nsw i32 [[DIV6]], 33537// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 7, [[MUL7]]3538// CHECK2-NEXT: store i32 [[ADD8]], ptr [[J]], align 43539// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43540// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43541// CHECK2-NEXT: [[DIV9:%.*]] = sdiv i32 [[TMP10]], 163542// CHECK2-NEXT: [[MUL10:%.*]] = mul nsw i32 [[DIV9]], 163543// CHECK2-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP9]], [[MUL10]]3544// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43545// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43546// CHECK2-NEXT: [[DIV12:%.*]] = sdiv i32 [[TMP12]], 163547// CHECK2-NEXT: [[MUL13:%.*]] = mul nsw i32 [[DIV12]], 163548// CHECK2-NEXT: [[SUB14:%.*]] = sub nsw i32 [[TMP11]], [[MUL13]]3549// CHECK2-NEXT: [[DIV15:%.*]] = sdiv i32 [[SUB14]], 43550// CHECK2-NEXT: [[MUL16:%.*]] = mul nsw i32 [[DIV15]], 43551// CHECK2-NEXT: [[SUB17:%.*]] = sub nsw i32 [[SUB11]], [[MUL16]]3552// CHECK2-NEXT: [[MUL18:%.*]] = mul nsw i32 [[SUB17]], 33553// CHECK2-NEXT: [[ADD19:%.*]] = add nsw i32 7, [[MUL18]]3554// CHECK2-NEXT: store i32 [[ADD19]], ptr [[K]], align 43555// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 43556// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[J]], align 43557// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[K]], align 43558// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP13]], i32 noundef [[TMP14]], i32 noundef [[TMP15]])3559// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]3560// CHECK2: omp.body.continue:3561// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]3562// CHECK2: omp.inner.for.inc:3563// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43564// CHECK2-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP16]], 13565// CHECK2-NEXT: store i32 [[ADD20]], ptr [[DOTOMP_IV]], align 43566// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]3567// CHECK2: omp.inner.for.end:3568// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]3569// CHECK2: omp.loop.exit:3570// CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]])3571// CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]])3572// CHECK2-NEXT: ret void3573//3574//3575// CHECK2-LABEL: define {{[^@]+}}@foo63576// CHECK2-SAME: () #[[ATTR0]] {3577// CHECK2-NEXT: entry:3578// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 43579// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 43580// CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 43581// CHECK2-NEXT: [[_TMP2:%.*]] = alloca i32, align 43582// CHECK2-NEXT: [[_TMP3:%.*]] = alloca i32, align 43583// CHECK2-NEXT: [[J:%.*]] = alloca i32, align 43584// CHECK2-NEXT: [[K:%.*]] = alloca i32, align 43585// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 43586// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 43587// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 43588// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 43589// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 43590// CHECK2-NEXT: [[DOTPERMUTED_0_IV_K:%.*]] = alloca i32, align 43591// CHECK2-NEXT: [[DOTPERMUTED_1_IV_J:%.*]] = alloca i32, align 43592// CHECK2-NEXT: [[L:%.*]] = alloca i32, align 43593// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])3594// CHECK2-NEXT: store i32 7, ptr [[J]], align 43595// CHECK2-NEXT: store i32 7, ptr [[K]], align 43596// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 43597// CHECK2-NEXT: store i32 255, ptr [[DOTOMP_UB]], align 43598// CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 43599// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 43600// CHECK2-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)3601// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43602// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 2553603// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]3604// CHECK2: cond.true:3605// CHECK2-NEXT: br label [[COND_END:%.*]]3606// CHECK2: cond.false:3607// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43608// CHECK2-NEXT: br label [[COND_END]]3609// CHECK2: cond.end:3610// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 255, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ]3611// CHECK2-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 43612// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 43613// CHECK2-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 43614// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]3615// CHECK2: omp.inner.for.cond:3616// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43617// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43618// CHECK2-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]3619// CHECK2-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]3620// CHECK2: omp.inner.for.body:3621// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43622// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP6]], 643623// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 33624// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 7, [[MUL]]3625// CHECK2-NEXT: store i32 [[ADD]], ptr [[I]], align 43626// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43627// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43628// CHECK2-NEXT: [[DIV5:%.*]] = sdiv i32 [[TMP8]], 643629// CHECK2-NEXT: [[MUL6:%.*]] = mul nsw i32 [[DIV5]], 643630// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], [[MUL6]]3631// CHECK2-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB]], 163632// CHECK2-NEXT: [[MUL8:%.*]] = mul nsw i32 [[DIV7]], 13633// CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 0, [[MUL8]]3634// CHECK2-NEXT: store i32 [[ADD9]], ptr [[DOTPERMUTED_0_IV_K]], align 43635// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43636// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43637// CHECK2-NEXT: [[DIV10:%.*]] = sdiv i32 [[TMP10]], 643638// CHECK2-NEXT: [[MUL11:%.*]] = mul nsw i32 [[DIV10]], 643639// CHECK2-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP9]], [[MUL11]]3640// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43641// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43642// CHECK2-NEXT: [[DIV13:%.*]] = sdiv i32 [[TMP12]], 643643// CHECK2-NEXT: [[MUL14:%.*]] = mul nsw i32 [[DIV13]], 643644// CHECK2-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP11]], [[MUL14]]3645// CHECK2-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 163646// CHECK2-NEXT: [[MUL17:%.*]] = mul nsw i32 [[DIV16]], 163647// CHECK2-NEXT: [[SUB18:%.*]] = sub nsw i32 [[SUB12]], [[MUL17]]3648// CHECK2-NEXT: [[DIV19:%.*]] = sdiv i32 [[SUB18]], 43649// CHECK2-NEXT: [[MUL20:%.*]] = mul nsw i32 [[DIV19]], 13650// CHECK2-NEXT: [[ADD21:%.*]] = add nsw i32 0, [[MUL20]]3651// CHECK2-NEXT: store i32 [[ADD21]], ptr [[DOTPERMUTED_1_IV_J]], align 43652// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43653// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43654// CHECK2-NEXT: [[DIV22:%.*]] = sdiv i32 [[TMP14]], 643655// CHECK2-NEXT: [[MUL23:%.*]] = mul nsw i32 [[DIV22]], 643656// CHECK2-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP13]], [[MUL23]]3657// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43658// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43659// CHECK2-NEXT: [[DIV25:%.*]] = sdiv i32 [[TMP16]], 643660// CHECK2-NEXT: [[MUL26:%.*]] = mul nsw i32 [[DIV25]], 643661// CHECK2-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP15]], [[MUL26]]3662// CHECK2-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 163663// CHECK2-NEXT: [[MUL29:%.*]] = mul nsw i32 [[DIV28]], 163664// CHECK2-NEXT: [[SUB30:%.*]] = sub nsw i32 [[SUB24]], [[MUL29]]3665// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43666// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43667// CHECK2-NEXT: [[DIV31:%.*]] = sdiv i32 [[TMP18]], 643668// CHECK2-NEXT: [[MUL32:%.*]] = mul nsw i32 [[DIV31]], 643669// CHECK2-NEXT: [[SUB33:%.*]] = sub nsw i32 [[TMP17]], [[MUL32]]3670// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43671// CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43672// CHECK2-NEXT: [[DIV34:%.*]] = sdiv i32 [[TMP20]], 643673// CHECK2-NEXT: [[MUL35:%.*]] = mul nsw i32 [[DIV34]], 643674// CHECK2-NEXT: [[SUB36:%.*]] = sub nsw i32 [[TMP19]], [[MUL35]]3675// CHECK2-NEXT: [[DIV37:%.*]] = sdiv i32 [[SUB36]], 163676// CHECK2-NEXT: [[MUL38:%.*]] = mul nsw i32 [[DIV37]], 163677// CHECK2-NEXT: [[SUB39:%.*]] = sub nsw i32 [[SUB33]], [[MUL38]]3678// CHECK2-NEXT: [[DIV40:%.*]] = sdiv i32 [[SUB39]], 43679// CHECK2-NEXT: [[MUL41:%.*]] = mul nsw i32 [[DIV40]], 43680// CHECK2-NEXT: [[SUB42:%.*]] = sub nsw i32 [[SUB30]], [[MUL41]]3681// CHECK2-NEXT: [[MUL43:%.*]] = mul nsw i32 [[SUB42]], 33682// CHECK2-NEXT: [[ADD44:%.*]] = add nsw i32 7, [[MUL43]]3683// CHECK2-NEXT: store i32 [[ADD44]], ptr [[L]], align 43684// CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_K]], align 43685// CHECK2-NEXT: [[MUL45:%.*]] = mul nsw i32 [[TMP21]], 33686// CHECK2-NEXT: [[ADD46:%.*]] = add nsw i32 7, [[MUL45]]3687// CHECK2-NEXT: store i32 [[ADD46]], ptr [[K]], align 43688// CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_J]], align 43689// CHECK2-NEXT: [[MUL47:%.*]] = mul nsw i32 [[TMP22]], 33690// CHECK2-NEXT: [[ADD48:%.*]] = add nsw i32 7, [[MUL47]]3691// CHECK2-NEXT: store i32 [[ADD48]], ptr [[J]], align 43692// CHECK2-NEXT: [[TMP23:%.*]] = load i32, ptr [[I]], align 43693// CHECK2-NEXT: [[TMP24:%.*]] = load i32, ptr [[J]], align 43694// CHECK2-NEXT: [[TMP25:%.*]] = load i32, ptr [[K]], align 43695// CHECK2-NEXT: [[TMP26:%.*]] = load i32, ptr [[L]], align 43696// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP23]], i32 noundef [[TMP24]], i32 noundef [[TMP25]], i32 noundef [[TMP26]])3697// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]3698// CHECK2: omp.body.continue:3699// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]3700// CHECK2: omp.inner.for.inc:3701// CHECK2-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43702// CHECK2-NEXT: [[ADD49:%.*]] = add nsw i32 [[TMP27]], 13703// CHECK2-NEXT: store i32 [[ADD49]], ptr [[DOTOMP_IV]], align 43704// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]3705// CHECK2: omp.inner.for.end:3706// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]3707// CHECK2: omp.loop.exit:3708// CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]])3709// CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]])3710// CHECK2-NEXT: ret void3711//3712//3713// CHECK2-LABEL: define {{[^@]+}}@foo73714// CHECK2-SAME: () #[[ATTR0]] {3715// CHECK2-NEXT: entry:3716// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 43717// CHECK2-NEXT: [[J:%.*]] = alloca i32, align 43718// CHECK2-NEXT: [[K:%.*]] = alloca i32, align 43719// CHECK2-NEXT: [[L:%.*]] = alloca i32, align 43720// CHECK2-NEXT: [[DOTPERMUTED_0_IV_J:%.*]] = alloca i32, align 43721// CHECK2-NEXT: [[DOTPERMUTED_1_IV_K:%.*]] = alloca i32, align 43722// CHECK2-NEXT: [[DOTPERMUTED_2_IV_L:%.*]] = alloca i32, align 43723// CHECK2-NEXT: [[DOTPERMUTED_3_IV_I:%.*]] = alloca i32, align 43724// CHECK2-NEXT: store i32 7, ptr [[I]], align 43725// CHECK2-NEXT: store i32 7, ptr [[J]], align 43726// CHECK2-NEXT: store i32 7, ptr [[K]], align 43727// CHECK2-NEXT: store i32 7, ptr [[L]], align 43728// CHECK2-NEXT: store i32 0, ptr [[DOTPERMUTED_0_IV_J]], align 43729// CHECK2-NEXT: br label [[FOR_COND:%.*]]3730// CHECK2: for.cond:3731// CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 43732// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 43733// CHECK2-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END24:%.*]]3734// CHECK2: for.body:3735// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 43736// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 33737// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 7, [[MUL]]3738// CHECK2-NEXT: store i32 [[ADD]], ptr [[J]], align 43739// CHECK2-NEXT: store i32 0, ptr [[DOTPERMUTED_1_IV_K]], align 43740// CHECK2-NEXT: br label [[FOR_COND1:%.*]]3741// CHECK2: for.cond1:3742// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_K]], align 43743// CHECK2-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP2]], 43744// CHECK2-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END21:%.*]]3745// CHECK2: for.body3:3746// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_K]], align 43747// CHECK2-NEXT: [[MUL4:%.*]] = mul nsw i32 [[TMP3]], 33748// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 7, [[MUL4]]3749// CHECK2-NEXT: store i32 [[ADD5]], ptr [[K]], align 43750// CHECK2-NEXT: store i32 0, ptr [[DOTPERMUTED_2_IV_L]], align 43751// CHECK2-NEXT: br label [[FOR_COND6:%.*]]3752// CHECK2: for.cond6:3753// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTPERMUTED_2_IV_L]], align 43754// CHECK2-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP4]], 43755// CHECK2-NEXT: br i1 [[CMP7]], label [[FOR_BODY8:%.*]], label [[FOR_END18:%.*]]3756// CHECK2: for.body8:3757// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTPERMUTED_2_IV_L]], align 43758// CHECK2-NEXT: [[MUL9:%.*]] = mul nsw i32 [[TMP5]], 33759// CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 7, [[MUL9]]3760// CHECK2-NEXT: store i32 [[ADD10]], ptr [[L]], align 43761// CHECK2-NEXT: store i32 0, ptr [[DOTPERMUTED_3_IV_I]], align 43762// CHECK2-NEXT: br label [[FOR_COND11:%.*]]3763// CHECK2: for.cond11:3764// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTPERMUTED_3_IV_I]], align 43765// CHECK2-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP6]], 43766// CHECK2-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END:%.*]]3767// CHECK2: for.body13:3768// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTPERMUTED_3_IV_I]], align 43769// CHECK2-NEXT: [[MUL14:%.*]] = mul nsw i32 [[TMP7]], 33770// CHECK2-NEXT: [[ADD15:%.*]] = add nsw i32 7, [[MUL14]]3771// CHECK2-NEXT: store i32 [[ADD15]], ptr [[I]], align 43772// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[I]], align 43773// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[J]], align 43774// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[K]], align 43775// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[L]], align 43776// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP8]], i32 noundef [[TMP9]], i32 noundef [[TMP10]], i32 noundef [[TMP11]])3777// CHECK2-NEXT: br label [[FOR_INC:%.*]]3778// CHECK2: for.inc:3779// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTPERMUTED_3_IV_I]], align 43780// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 13781// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTPERMUTED_3_IV_I]], align 43782// CHECK2-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP9:![0-9]+]]3783// CHECK2: for.end:3784// CHECK2-NEXT: br label [[FOR_INC16:%.*]]3785// CHECK2: for.inc16:3786// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTPERMUTED_2_IV_L]], align 43787// CHECK2-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP13]], 13788// CHECK2-NEXT: store i32 [[INC17]], ptr [[DOTPERMUTED_2_IV_L]], align 43789// CHECK2-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP10:![0-9]+]]3790// CHECK2: for.end18:3791// CHECK2-NEXT: br label [[FOR_INC19:%.*]]3792// CHECK2: for.inc19:3793// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_K]], align 43794// CHECK2-NEXT: [[INC20:%.*]] = add nsw i32 [[TMP14]], 13795// CHECK2-NEXT: store i32 [[INC20]], ptr [[DOTPERMUTED_1_IV_K]], align 43796// CHECK2-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP11:![0-9]+]]3797// CHECK2: for.end21:3798// CHECK2-NEXT: br label [[FOR_INC22:%.*]]3799// CHECK2: for.inc22:3800// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 43801// CHECK2-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP15]], 13802// CHECK2-NEXT: store i32 [[INC23]], ptr [[DOTPERMUTED_0_IV_J]], align 43803// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]3804// CHECK2: for.end24:3805// CHECK2-NEXT: ret void3806//3807//3808// CHECK2-LABEL: define {{[^@]+}}@foo93809// CHECK2-SAME: () #[[ATTR0]] {3810// CHECK2-NEXT: entry:3811// CHECK2-NEXT: [[ARR:%.*]] = alloca [128 x double], align 163812// CHECK2-NEXT: [[C:%.*]] = alloca double, align 83813// CHECK2-NEXT: [[__RANGE2:%.*]] = alloca ptr, align 83814// CHECK2-NEXT: [[__END2:%.*]] = alloca ptr, align 83815// CHECK2-NEXT: [[__BEGIN2:%.*]] = alloca ptr, align 83816// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca ptr, align 83817// CHECK2-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca ptr, align 83818// CHECK2-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i64, align 83819// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 43820// CHECK2-NEXT: [[DOTPERMUTED_0_IV_I:%.*]] = alloca i32, align 43821// CHECK2-NEXT: [[DOTPERMUTED_1_IV___BEGIN2:%.*]] = alloca i64, align 83822// CHECK2-NEXT: [[V:%.*]] = alloca ptr, align 83823// CHECK2-NEXT: store double 4.200000e+01, ptr [[C]], align 83824// CHECK2-NEXT: store ptr [[ARR]], ptr [[__RANGE2]], align 83825// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__RANGE2]], align 83826// CHECK2-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP0]], i64 0, i64 03827// CHECK2-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY]], i64 1283828// CHECK2-NEXT: store ptr [[ADD_PTR]], ptr [[__END2]], align 83829// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE2]], align 83830// CHECK2-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP1]], i64 0, i64 03831// CHECK2-NEXT: store ptr [[ARRAYDECAY1]], ptr [[__BEGIN2]], align 83832// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE2]], align 83833// CHECK2-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP2]], i64 0, i64 03834// CHECK2-NEXT: store ptr [[ARRAYDECAY2]], ptr [[DOTCAPTURE_EXPR_]], align 83835// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[__END2]], align 83836// CHECK2-NEXT: store ptr [[TMP3]], ptr [[DOTCAPTURE_EXPR_3]], align 83837// CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_3]], align 83838// CHECK2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 83839// CHECK2-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint ptr [[TMP4]] to i643840// CHECK2-NEXT: [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint ptr [[TMP5]] to i643841// CHECK2-NEXT: [[SUB_PTR_SUB:%.*]] = sub i64 [[SUB_PTR_LHS_CAST]], [[SUB_PTR_RHS_CAST]]3842// CHECK2-NEXT: [[SUB_PTR_DIV:%.*]] = sdiv exact i64 [[SUB_PTR_SUB]], 83843// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i64 [[SUB_PTR_DIV]], 13844// CHECK2-NEXT: [[ADD:%.*]] = add nsw i64 [[SUB]], 13845// CHECK2-NEXT: [[DIV:%.*]] = sdiv i64 [[ADD]], 13846// CHECK2-NEXT: [[SUB5:%.*]] = sub nsw i64 [[DIV]], 13847// CHECK2-NEXT: store i64 [[SUB5]], ptr [[DOTCAPTURE_EXPR_4]], align 83848// CHECK2-NEXT: store i32 0, ptr [[I]], align 43849// CHECK2-NEXT: store i32 0, ptr [[DOTPERMUTED_0_IV_I]], align 43850// CHECK2-NEXT: br label [[FOR_COND:%.*]]3851// CHECK2: for.cond:3852// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_I]], align 43853// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], 213854// CHECK2-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END15:%.*]]3855// CHECK2: for.body:3856// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_I]], align 43857// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 23858// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL]]3859// CHECK2-NEXT: store i32 [[ADD6]], ptr [[I]], align 43860// CHECK2-NEXT: store i64 0, ptr [[DOTPERMUTED_1_IV___BEGIN2]], align 83861// CHECK2-NEXT: br label [[FOR_COND7:%.*]]3862// CHECK2: for.cond7:3863// CHECK2-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTPERMUTED_1_IV___BEGIN2]], align 83864// CHECK2-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_4]], align 83865// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP9]], 13866// CHECK2-NEXT: [[CMP9:%.*]] = icmp slt i64 [[TMP8]], [[ADD8]]3867// CHECK2-NEXT: br i1 [[CMP9]], label [[FOR_BODY10:%.*]], label [[FOR_END:%.*]]3868// CHECK2: for.body10:3869// CHECK2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 83870// CHECK2-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTPERMUTED_1_IV___BEGIN2]], align 83871// CHECK2-NEXT: [[MUL11:%.*]] = mul nsw i64 [[TMP11]], 13872// CHECK2-NEXT: [[ADD_PTR12:%.*]] = getelementptr inbounds double, ptr [[TMP10]], i64 [[MUL11]]3873// CHECK2-NEXT: store ptr [[ADD_PTR12]], ptr [[__BEGIN2]], align 83874// CHECK2-NEXT: [[TMP12:%.*]] = load ptr, ptr [[__BEGIN2]], align 83875// CHECK2-NEXT: store ptr [[TMP12]], ptr [[V]], align 83876// CHECK2-NEXT: [[TMP13:%.*]] = load double, ptr [[C]], align 83877// CHECK2-NEXT: [[TMP14:%.*]] = load ptr, ptr [[V]], align 83878// CHECK2-NEXT: [[TMP15:%.*]] = load double, ptr [[TMP14]], align 83879// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 43880// CHECK2-NEXT: call void (...) @body(double noundef [[TMP13]], double noundef [[TMP15]], i32 noundef [[TMP16]])3881// CHECK2-NEXT: br label [[FOR_INC:%.*]]3882// CHECK2: for.inc:3883// CHECK2-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTPERMUTED_1_IV___BEGIN2]], align 83884// CHECK2-NEXT: [[INC:%.*]] = add nsw i64 [[TMP17]], 13885// CHECK2-NEXT: store i64 [[INC]], ptr [[DOTPERMUTED_1_IV___BEGIN2]], align 83886// CHECK2-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP13:![0-9]+]]3887// CHECK2: for.end:3888// CHECK2-NEXT: br label [[FOR_INC13:%.*]]3889// CHECK2: for.inc13:3890// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_I]], align 43891// CHECK2-NEXT: [[INC14:%.*]] = add nsw i32 [[TMP18]], 13892// CHECK2-NEXT: store i32 [[INC14]], ptr [[DOTPERMUTED_0_IV_I]], align 43893// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]3894// CHECK2: for.end15:3895// CHECK2-NEXT: ret void3896//3897//3898// CHECK2-LABEL: define {{[^@]+}}@tfoo83899// CHECK2-SAME: () #[[ATTR0]] {3900// CHECK2-NEXT: entry:3901// CHECK2-NEXT: call void @_Z4foo8ILi32EEviii(i32 noundef 0, i32 noundef 42, i32 noundef 1)3902// CHECK2-NEXT: call void @_Z4foo8ILi64EEviii(i32 noundef 0, i32 noundef 42, i32 noundef 3)3903// CHECK2-NEXT: ret void3904//3905//3906// CHECK2-LABEL: define {{[^@]+}}@_Z4foo8ILi32EEviii3907// CHECK2-SAME: (i32 noundef [[START:%.*]], i32 noundef [[END:%.*]], i32 noundef [[STEP:%.*]]) #[[ATTR0]] comdat {3908// CHECK2-NEXT: entry:3909// CHECK2-NEXT: [[START_ADDR:%.*]] = alloca i32, align 43910// CHECK2-NEXT: [[END_ADDR:%.*]] = alloca i32, align 43911// CHECK2-NEXT: [[STEP_ADDR:%.*]] = alloca i32, align 43912// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 83913// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 43914// CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 43915// CHECK2-NEXT: [[_TMP2:%.*]] = alloca i32, align 43916// CHECK2-NEXT: [[_TMP3:%.*]] = alloca i32, align 43917// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 43918// CHECK2-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 43919// CHECK2-NEXT: [[DOTNEW_STEP:%.*]] = alloca i32, align 43920// CHECK2-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 43921// CHECK2-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i32, align 43922// CHECK2-NEXT: [[DOTNEW_STEP7:%.*]] = alloca i32, align 43923// CHECK2-NEXT: [[K:%.*]] = alloca i32, align 43924// CHECK2-NEXT: [[DOTCAPTURE_EXPR_8:%.*]] = alloca i32, align 43925// CHECK2-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 43926// CHECK2-NEXT: [[DOTNEW_STEP10:%.*]] = alloca i32, align 43927// CHECK2-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 43928// CHECK2-NEXT: [[DOTCAPTURE_EXPR_14:%.*]] = alloca i32, align 43929// CHECK2-NEXT: [[DOTCAPTURE_EXPR_16:%.*]] = alloca i32, align 43930// CHECK2-NEXT: [[DOTCAPTURE_EXPR_17:%.*]] = alloca i32, align 43931// CHECK2-NEXT: [[DOTCAPTURE_EXPR_22:%.*]] = alloca i64, align 83932// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 43933// CHECK2-NEXT: [[J:%.*]] = alloca i32, align 43934// CHECK2-NEXT: [[DOTFLOOR_0_IV_K:%.*]] = alloca i32, align 43935// CHECK2-NEXT: [[DOTTILE_0_IV_K:%.*]] = alloca i32, align 43936// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 83937// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 83938// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 83939// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 43940// CHECK2-NEXT: [[I49:%.*]] = alloca i32, align 43941// CHECK2-NEXT: [[J50:%.*]] = alloca i32, align 43942// CHECK2-NEXT: [[DOTFLOOR_0_IV_K51:%.*]] = alloca i32, align 43943// CHECK2-NEXT: [[DOTTILE_0_IV_K52:%.*]] = alloca i32, align 43944// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])3945// CHECK2-NEXT: store i32 [[START]], ptr [[START_ADDR]], align 43946// CHECK2-NEXT: store i32 [[END]], ptr [[END_ADDR]], align 43947// CHECK2-NEXT: store i32 [[STEP]], ptr [[STEP_ADDR]], align 43948// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[START_ADDR]], align 43949// CHECK2-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 43950// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[END_ADDR]], align 43951// CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_4]], align 43952// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[STEP_ADDR]], align 43953// CHECK2-NEXT: store i32 [[TMP3]], ptr [[DOTNEW_STEP]], align 43954// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[START_ADDR]], align 43955// CHECK2-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_5]], align 43956// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[END_ADDR]], align 43957// CHECK2-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_6]], align 43958// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[STEP_ADDR]], align 43959// CHECK2-NEXT: store i32 [[TMP6]], ptr [[DOTNEW_STEP7]], align 43960// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[START_ADDR]], align 43961// CHECK2-NEXT: store i32 [[TMP7]], ptr [[K]], align 43962// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[START_ADDR]], align 43963// CHECK2-NEXT: store i32 [[TMP8]], ptr [[DOTCAPTURE_EXPR_8]], align 43964// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[END_ADDR]], align 43965// CHECK2-NEXT: store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR_9]], align 43966// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[STEP_ADDR]], align 43967// CHECK2-NEXT: store i32 [[TMP10]], ptr [[DOTNEW_STEP10]], align 43968// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_9]], align 43969// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_8]], align 43970// CHECK2-NEXT: [[SUB:%.*]] = sub i32 [[TMP11]], [[TMP12]]3971// CHECK2-NEXT: [[SUB12:%.*]] = sub i32 [[SUB]], 13972// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 43973// CHECK2-NEXT: [[ADD:%.*]] = add i32 [[SUB12]], [[TMP13]]3974// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 43975// CHECK2-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], [[TMP14]]3976// CHECK2-NEXT: [[SUB13:%.*]] = sub i32 [[DIV]], 13977// CHECK2-NEXT: store i32 [[SUB13]], ptr [[DOTCAPTURE_EXPR_11]], align 43978// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 43979// CHECK2-NEXT: [[ADD15:%.*]] = add i32 [[TMP15]], 13980// CHECK2-NEXT: store i32 [[ADD15]], ptr [[DOTCAPTURE_EXPR_14]], align 43981// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[_TMP2]], align 43982// CHECK2-NEXT: store i32 [[TMP16]], ptr [[DOTCAPTURE_EXPR_16]], align 43983// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 43984// CHECK2-NEXT: [[ADD18:%.*]] = add i32 [[TMP17]], 13985// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[_TMP2]], align 43986// CHECK2-NEXT: [[ADD19:%.*]] = add i32 [[TMP18]], 323987// CHECK2-NEXT: [[CMP:%.*]] = icmp ult i32 [[ADD18]], [[ADD19]]3988// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]3989// CHECK2: cond.true:3990// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 43991// CHECK2-NEXT: [[ADD20:%.*]] = add i32 [[TMP19]], 13992// CHECK2-NEXT: br label [[COND_END:%.*]]3993// CHECK2: cond.false:3994// CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[_TMP2]], align 43995// CHECK2-NEXT: [[ADD21:%.*]] = add i32 [[TMP20]], 323996// CHECK2-NEXT: br label [[COND_END]]3997// CHECK2: cond.end:3998// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ [[ADD20]], [[COND_TRUE]] ], [ [[ADD21]], [[COND_FALSE]] ]3999// CHECK2-NEXT: store i32 [[COND]], ptr [[DOTCAPTURE_EXPR_17]], align 44000// CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 44001// CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 44002// CHECK2-NEXT: [[SUB23:%.*]] = sub i32 [[TMP21]], [[TMP22]]4003// CHECK2-NEXT: [[SUB24:%.*]] = sub i32 [[SUB23]], 14004// CHECK2-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 44005// CHECK2-NEXT: [[ADD25:%.*]] = add i32 [[SUB24]], [[TMP23]]4006// CHECK2-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 44007// CHECK2-NEXT: [[DIV26:%.*]] = udiv i32 [[ADD25]], [[TMP24]]4008// CHECK2-NEXT: [[CONV:%.*]] = zext i32 [[DIV26]] to i644009// CHECK2-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 44010// CHECK2-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 44011// CHECK2-NEXT: [[SUB27:%.*]] = sub i32 [[TMP25]], [[TMP26]]4012// CHECK2-NEXT: [[SUB28:%.*]] = sub i32 [[SUB27]], 14013// CHECK2-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44014// CHECK2-NEXT: [[ADD29:%.*]] = add i32 [[SUB28]], [[TMP27]]4015// CHECK2-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44016// CHECK2-NEXT: [[DIV30:%.*]] = udiv i32 [[ADD29]], [[TMP28]]4017// CHECK2-NEXT: [[CONV31:%.*]] = zext i32 [[DIV30]] to i644018// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV31]]4019// CHECK2-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 44020// CHECK2-NEXT: [[SUB32:%.*]] = sub i32 [[TMP29]], -314021// CHECK2-NEXT: [[DIV33:%.*]] = udiv i32 [[SUB32]], 324022// CHECK2-NEXT: [[CONV34:%.*]] = zext i32 [[DIV33]] to i644023// CHECK2-NEXT: [[MUL35:%.*]] = mul nsw i64 [[MUL]], [[CONV34]]4024// CHECK2-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 44025// CHECK2-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 44026// CHECK2-NEXT: [[SUB36:%.*]] = sub i32 [[TMP30]], [[TMP31]]4027// CHECK2-NEXT: [[SUB37:%.*]] = sub i32 [[SUB36]], 14028// CHECK2-NEXT: [[ADD38:%.*]] = add i32 [[SUB37]], 14029// CHECK2-NEXT: [[DIV39:%.*]] = udiv i32 [[ADD38]], 14030// CHECK2-NEXT: [[CONV40:%.*]] = zext i32 [[DIV39]] to i644031// CHECK2-NEXT: [[MUL41:%.*]] = mul nsw i64 [[MUL35]], [[CONV40]]4032// CHECK2-NEXT: [[SUB42:%.*]] = sub nsw i64 [[MUL41]], 14033// CHECK2-NEXT: store i64 [[SUB42]], ptr [[DOTCAPTURE_EXPR_22]], align 84034// CHECK2-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 44035// CHECK2-NEXT: store i32 [[TMP32]], ptr [[I]], align 44036// CHECK2-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 44037// CHECK2-NEXT: store i32 [[TMP33]], ptr [[J]], align 44038// CHECK2-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV_K]], align 44039// CHECK2-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 44040// CHECK2-NEXT: store i32 [[TMP34]], ptr [[DOTTILE_0_IV_K]], align 44041// CHECK2-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 44042// CHECK2-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 44043// CHECK2-NEXT: [[CMP43:%.*]] = icmp slt i32 [[TMP35]], [[TMP36]]4044// CHECK2-NEXT: br i1 [[CMP43]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]4045// CHECK2: land.lhs.true:4046// CHECK2-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 44047// CHECK2-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 44048// CHECK2-NEXT: [[CMP44:%.*]] = icmp slt i32 [[TMP37]], [[TMP38]]4049// CHECK2-NEXT: br i1 [[CMP44]], label [[LAND_LHS_TRUE45:%.*]], label [[OMP_PRECOND_END]]4050// CHECK2: land.lhs.true45:4051// CHECK2-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 44052// CHECK2-NEXT: [[CMP46:%.*]] = icmp ult i32 0, [[TMP39]]4053// CHECK2-NEXT: br i1 [[CMP46]], label [[LAND_LHS_TRUE47:%.*]], label [[OMP_PRECOND_END]]4054// CHECK2: land.lhs.true47:4055// CHECK2-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 44056// CHECK2-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 44057// CHECK2-NEXT: [[CMP48:%.*]] = icmp ult i32 [[TMP40]], [[TMP41]]4058// CHECK2-NEXT: br i1 [[CMP48]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]4059// CHECK2: omp.precond.then:4060// CHECK2-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 84061// CHECK2-NEXT: [[TMP42:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 84062// CHECK2-NEXT: store i64 [[TMP42]], ptr [[DOTOMP_UB]], align 84063// CHECK2-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 84064// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 44065// CHECK2-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)4066// CHECK2-NEXT: [[TMP43:%.*]] = load i64, ptr [[DOTOMP_UB]], align 84067// CHECK2-NEXT: [[TMP44:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 84068// CHECK2-NEXT: [[CMP53:%.*]] = icmp sgt i64 [[TMP43]], [[TMP44]]4069// CHECK2-NEXT: br i1 [[CMP53]], label [[COND_TRUE54:%.*]], label [[COND_FALSE55:%.*]]4070// CHECK2: cond.true54:4071// CHECK2-NEXT: [[TMP45:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 84072// CHECK2-NEXT: br label [[COND_END56:%.*]]4073// CHECK2: cond.false55:4074// CHECK2-NEXT: [[TMP46:%.*]] = load i64, ptr [[DOTOMP_UB]], align 84075// CHECK2-NEXT: br label [[COND_END56]]4076// CHECK2: cond.end56:4077// CHECK2-NEXT: [[COND57:%.*]] = phi i64 [ [[TMP45]], [[COND_TRUE54]] ], [ [[TMP46]], [[COND_FALSE55]] ]4078// CHECK2-NEXT: store i64 [[COND57]], ptr [[DOTOMP_UB]], align 84079// CHECK2-NEXT: [[TMP47:%.*]] = load i64, ptr [[DOTOMP_LB]], align 84080// CHECK2-NEXT: store i64 [[TMP47]], ptr [[DOTOMP_IV]], align 84081// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]4082// CHECK2: omp.inner.for.cond:4083// CHECK2-NEXT: [[TMP48:%.*]] = load i64, ptr [[DOTOMP_IV]], align 84084// CHECK2-NEXT: [[TMP49:%.*]] = load i64, ptr [[DOTOMP_UB]], align 84085// CHECK2-NEXT: [[CMP58:%.*]] = icmp sle i64 [[TMP48]], [[TMP49]]4086// CHECK2-NEXT: br i1 [[CMP58]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]4087// CHECK2: omp.inner.for.body:4088// CHECK2-NEXT: [[TMP50:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 44089// CHECK2-NEXT: [[CONV59:%.*]] = sext i32 [[TMP50]] to i644090// CHECK2-NEXT: [[TMP51:%.*]] = load i64, ptr [[DOTOMP_IV]], align 84091// CHECK2-NEXT: [[TMP52:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 44092// CHECK2-NEXT: [[TMP53:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 44093// CHECK2-NEXT: [[SUB60:%.*]] = sub i32 [[TMP52]], [[TMP53]]4094// CHECK2-NEXT: [[SUB61:%.*]] = sub i32 [[SUB60]], 14095// CHECK2-NEXT: [[TMP54:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44096// CHECK2-NEXT: [[ADD62:%.*]] = add i32 [[SUB61]], [[TMP54]]4097// CHECK2-NEXT: [[TMP55:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44098// CHECK2-NEXT: [[DIV63:%.*]] = udiv i32 [[ADD62]], [[TMP55]]4099// CHECK2-NEXT: [[MUL64:%.*]] = mul i32 1, [[DIV63]]4100// CHECK2-NEXT: [[TMP56:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 44101// CHECK2-NEXT: [[SUB65:%.*]] = sub i32 [[TMP56]], -314102// CHECK2-NEXT: [[DIV66:%.*]] = udiv i32 [[SUB65]], 324103// CHECK2-NEXT: [[MUL67:%.*]] = mul i32 [[MUL64]], [[DIV66]]4104// CHECK2-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 44105// CHECK2-NEXT: [[TMP58:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 44106// CHECK2-NEXT: [[SUB68:%.*]] = sub i32 [[TMP57]], [[TMP58]]4107// CHECK2-NEXT: [[SUB69:%.*]] = sub i32 [[SUB68]], 14108// CHECK2-NEXT: [[ADD70:%.*]] = add i32 [[SUB69]], 14109// CHECK2-NEXT: [[DIV71:%.*]] = udiv i32 [[ADD70]], 14110// CHECK2-NEXT: [[MUL72:%.*]] = mul i32 [[MUL67]], [[DIV71]]4111// CHECK2-NEXT: [[CONV73:%.*]] = zext i32 [[MUL72]] to i644112// CHECK2-NEXT: [[DIV74:%.*]] = sdiv i64 [[TMP51]], [[CONV73]]4113// CHECK2-NEXT: [[TMP59:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 44114// CHECK2-NEXT: [[CONV75:%.*]] = sext i32 [[TMP59]] to i644115// CHECK2-NEXT: [[MUL76:%.*]] = mul nsw i64 [[DIV74]], [[CONV75]]4116// CHECK2-NEXT: [[ADD77:%.*]] = add nsw i64 [[CONV59]], [[MUL76]]4117// CHECK2-NEXT: [[CONV78:%.*]] = trunc i64 [[ADD77]] to i324118// CHECK2-NEXT: store i32 [[CONV78]], ptr [[I49]], align 44119// CHECK2-NEXT: [[TMP60:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 44120// CHECK2-NEXT: [[CONV79:%.*]] = sext i32 [[TMP60]] to i644121// CHECK2-NEXT: [[TMP61:%.*]] = load i64, ptr [[DOTOMP_IV]], align 84122// CHECK2-NEXT: [[TMP62:%.*]] = load i64, ptr [[DOTOMP_IV]], align 84123// CHECK2-NEXT: [[TMP63:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 44124// CHECK2-NEXT: [[TMP64:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 44125// CHECK2-NEXT: [[SUB80:%.*]] = sub i32 [[TMP63]], [[TMP64]]4126// CHECK2-NEXT: [[SUB81:%.*]] = sub i32 [[SUB80]], 14127// CHECK2-NEXT: [[TMP65:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44128// CHECK2-NEXT: [[ADD82:%.*]] = add i32 [[SUB81]], [[TMP65]]4129// CHECK2-NEXT: [[TMP66:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44130// CHECK2-NEXT: [[DIV83:%.*]] = udiv i32 [[ADD82]], [[TMP66]]4131// CHECK2-NEXT: [[MUL84:%.*]] = mul i32 1, [[DIV83]]4132// CHECK2-NEXT: [[TMP67:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 44133// CHECK2-NEXT: [[SUB85:%.*]] = sub i32 [[TMP67]], -314134// CHECK2-NEXT: [[DIV86:%.*]] = udiv i32 [[SUB85]], 324135// CHECK2-NEXT: [[MUL87:%.*]] = mul i32 [[MUL84]], [[DIV86]]4136// CHECK2-NEXT: [[TMP68:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 44137// CHECK2-NEXT: [[TMP69:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 44138// CHECK2-NEXT: [[SUB88:%.*]] = sub i32 [[TMP68]], [[TMP69]]4139// CHECK2-NEXT: [[SUB89:%.*]] = sub i32 [[SUB88]], 14140// CHECK2-NEXT: [[ADD90:%.*]] = add i32 [[SUB89]], 14141// CHECK2-NEXT: [[DIV91:%.*]] = udiv i32 [[ADD90]], 14142// CHECK2-NEXT: [[MUL92:%.*]] = mul i32 [[MUL87]], [[DIV91]]4143// CHECK2-NEXT: [[CONV93:%.*]] = zext i32 [[MUL92]] to i644144// CHECK2-NEXT: [[DIV94:%.*]] = sdiv i64 [[TMP62]], [[CONV93]]4145// CHECK2-NEXT: [[TMP70:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 44146// CHECK2-NEXT: [[TMP71:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 44147// CHECK2-NEXT: [[SUB95:%.*]] = sub i32 [[TMP70]], [[TMP71]]4148// CHECK2-NEXT: [[SUB96:%.*]] = sub i32 [[SUB95]], 14149// CHECK2-NEXT: [[TMP72:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44150// CHECK2-NEXT: [[ADD97:%.*]] = add i32 [[SUB96]], [[TMP72]]4151// CHECK2-NEXT: [[TMP73:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44152// CHECK2-NEXT: [[DIV98:%.*]] = udiv i32 [[ADD97]], [[TMP73]]4153// CHECK2-NEXT: [[MUL99:%.*]] = mul i32 1, [[DIV98]]4154// CHECK2-NEXT: [[TMP74:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 44155// CHECK2-NEXT: [[SUB100:%.*]] = sub i32 [[TMP74]], -314156// CHECK2-NEXT: [[DIV101:%.*]] = udiv i32 [[SUB100]], 324157// CHECK2-NEXT: [[MUL102:%.*]] = mul i32 [[MUL99]], [[DIV101]]4158// CHECK2-NEXT: [[TMP75:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 44159// CHECK2-NEXT: [[TMP76:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 44160// CHECK2-NEXT: [[SUB103:%.*]] = sub i32 [[TMP75]], [[TMP76]]4161// CHECK2-NEXT: [[SUB104:%.*]] = sub i32 [[SUB103]], 14162// CHECK2-NEXT: [[ADD105:%.*]] = add i32 [[SUB104]], 14163// CHECK2-NEXT: [[DIV106:%.*]] = udiv i32 [[ADD105]], 14164// CHECK2-NEXT: [[MUL107:%.*]] = mul i32 [[MUL102]], [[DIV106]]4165// CHECK2-NEXT: [[CONV108:%.*]] = zext i32 [[MUL107]] to i644166// CHECK2-NEXT: [[MUL109:%.*]] = mul nsw i64 [[DIV94]], [[CONV108]]4167// CHECK2-NEXT: [[SUB110:%.*]] = sub nsw i64 [[TMP61]], [[MUL109]]4168// CHECK2-NEXT: [[TMP77:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 44169// CHECK2-NEXT: [[SUB111:%.*]] = sub i32 [[TMP77]], -314170// CHECK2-NEXT: [[DIV112:%.*]] = udiv i32 [[SUB111]], 324171// CHECK2-NEXT: [[MUL113:%.*]] = mul i32 1, [[DIV112]]4172// CHECK2-NEXT: [[TMP78:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 44173// CHECK2-NEXT: [[TMP79:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 44174// CHECK2-NEXT: [[SUB114:%.*]] = sub i32 [[TMP78]], [[TMP79]]4175// CHECK2-NEXT: [[SUB115:%.*]] = sub i32 [[SUB114]], 14176// CHECK2-NEXT: [[ADD116:%.*]] = add i32 [[SUB115]], 14177// CHECK2-NEXT: [[DIV117:%.*]] = udiv i32 [[ADD116]], 14178// CHECK2-NEXT: [[MUL118:%.*]] = mul i32 [[MUL113]], [[DIV117]]4179// CHECK2-NEXT: [[CONV119:%.*]] = zext i32 [[MUL118]] to i644180// CHECK2-NEXT: [[DIV120:%.*]] = sdiv i64 [[SUB110]], [[CONV119]]4181// CHECK2-NEXT: [[TMP80:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44182// CHECK2-NEXT: [[CONV121:%.*]] = sext i32 [[TMP80]] to i644183// CHECK2-NEXT: [[MUL122:%.*]] = mul nsw i64 [[DIV120]], [[CONV121]]4184// CHECK2-NEXT: [[ADD123:%.*]] = add nsw i64 [[CONV79]], [[MUL122]]4185// CHECK2-NEXT: [[CONV124:%.*]] = trunc i64 [[ADD123]] to i324186// CHECK2-NEXT: store i32 [[CONV124]], ptr [[J50]], align 44187// CHECK2-NEXT: [[TMP81:%.*]] = load i64, ptr [[DOTOMP_IV]], align 84188// CHECK2-NEXT: [[TMP82:%.*]] = load i64, ptr [[DOTOMP_IV]], align 84189// CHECK2-NEXT: [[TMP83:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 44190// CHECK2-NEXT: [[TMP84:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 44191// CHECK2-NEXT: [[SUB125:%.*]] = sub i32 [[TMP83]], [[TMP84]]4192// CHECK2-NEXT: [[SUB126:%.*]] = sub i32 [[SUB125]], 14193// CHECK2-NEXT: [[TMP85:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44194// CHECK2-NEXT: [[ADD127:%.*]] = add i32 [[SUB126]], [[TMP85]]4195// CHECK2-NEXT: [[TMP86:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44196// CHECK2-NEXT: [[DIV128:%.*]] = udiv i32 [[ADD127]], [[TMP86]]4197// CHECK2-NEXT: [[MUL129:%.*]] = mul i32 1, [[DIV128]]4198// CHECK2-NEXT: [[TMP87:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 44199// CHECK2-NEXT: [[SUB130:%.*]] = sub i32 [[TMP87]], -314200// CHECK2-NEXT: [[DIV131:%.*]] = udiv i32 [[SUB130]], 324201// CHECK2-NEXT: [[MUL132:%.*]] = mul i32 [[MUL129]], [[DIV131]]4202// CHECK2-NEXT: [[TMP88:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 44203// CHECK2-NEXT: [[TMP89:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 44204// CHECK2-NEXT: [[SUB133:%.*]] = sub i32 [[TMP88]], [[TMP89]]4205// CHECK2-NEXT: [[SUB134:%.*]] = sub i32 [[SUB133]], 14206// CHECK2-NEXT: [[ADD135:%.*]] = add i32 [[SUB134]], 14207// CHECK2-NEXT: [[DIV136:%.*]] = udiv i32 [[ADD135]], 14208// CHECK2-NEXT: [[MUL137:%.*]] = mul i32 [[MUL132]], [[DIV136]]4209// CHECK2-NEXT: [[CONV138:%.*]] = zext i32 [[MUL137]] to i644210// CHECK2-NEXT: [[DIV139:%.*]] = sdiv i64 [[TMP82]], [[CONV138]]4211// CHECK2-NEXT: [[TMP90:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 44212// CHECK2-NEXT: [[TMP91:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 44213// CHECK2-NEXT: [[SUB140:%.*]] = sub i32 [[TMP90]], [[TMP91]]4214// CHECK2-NEXT: [[SUB141:%.*]] = sub i32 [[SUB140]], 14215// CHECK2-NEXT: [[TMP92:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44216// CHECK2-NEXT: [[ADD142:%.*]] = add i32 [[SUB141]], [[TMP92]]4217// CHECK2-NEXT: [[TMP93:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44218// CHECK2-NEXT: [[DIV143:%.*]] = udiv i32 [[ADD142]], [[TMP93]]4219// CHECK2-NEXT: [[MUL144:%.*]] = mul i32 1, [[DIV143]]4220// CHECK2-NEXT: [[TMP94:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 44221// CHECK2-NEXT: [[SUB145:%.*]] = sub i32 [[TMP94]], -314222// CHECK2-NEXT: [[DIV146:%.*]] = udiv i32 [[SUB145]], 324223// CHECK2-NEXT: [[MUL147:%.*]] = mul i32 [[MUL144]], [[DIV146]]4224// CHECK2-NEXT: [[TMP95:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 44225// CHECK2-NEXT: [[TMP96:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 44226// CHECK2-NEXT: [[SUB148:%.*]] = sub i32 [[TMP95]], [[TMP96]]4227// CHECK2-NEXT: [[SUB149:%.*]] = sub i32 [[SUB148]], 14228// CHECK2-NEXT: [[ADD150:%.*]] = add i32 [[SUB149]], 14229// CHECK2-NEXT: [[DIV151:%.*]] = udiv i32 [[ADD150]], 14230// CHECK2-NEXT: [[MUL152:%.*]] = mul i32 [[MUL147]], [[DIV151]]4231// CHECK2-NEXT: [[CONV153:%.*]] = zext i32 [[MUL152]] to i644232// CHECK2-NEXT: [[MUL154:%.*]] = mul nsw i64 [[DIV139]], [[CONV153]]4233// CHECK2-NEXT: [[SUB155:%.*]] = sub nsw i64 [[TMP81]], [[MUL154]]4234// CHECK2-NEXT: [[TMP97:%.*]] = load i64, ptr [[DOTOMP_IV]], align 84235// CHECK2-NEXT: [[TMP98:%.*]] = load i64, ptr [[DOTOMP_IV]], align 84236// CHECK2-NEXT: [[TMP99:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 44237// CHECK2-NEXT: [[TMP100:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 44238// CHECK2-NEXT: [[SUB156:%.*]] = sub i32 [[TMP99]], [[TMP100]]4239// CHECK2-NEXT: [[SUB157:%.*]] = sub i32 [[SUB156]], 14240// CHECK2-NEXT: [[TMP101:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44241// CHECK2-NEXT: [[ADD158:%.*]] = add i32 [[SUB157]], [[TMP101]]4242// CHECK2-NEXT: [[TMP102:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44243// CHECK2-NEXT: [[DIV159:%.*]] = udiv i32 [[ADD158]], [[TMP102]]4244// CHECK2-NEXT: [[MUL160:%.*]] = mul i32 1, [[DIV159]]4245// CHECK2-NEXT: [[TMP103:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 44246// CHECK2-NEXT: [[SUB161:%.*]] = sub i32 [[TMP103]], -314247// CHECK2-NEXT: [[DIV162:%.*]] = udiv i32 [[SUB161]], 324248// CHECK2-NEXT: [[MUL163:%.*]] = mul i32 [[MUL160]], [[DIV162]]4249// CHECK2-NEXT: [[TMP104:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 44250// CHECK2-NEXT: [[TMP105:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 44251// CHECK2-NEXT: [[SUB164:%.*]] = sub i32 [[TMP104]], [[TMP105]]4252// CHECK2-NEXT: [[SUB165:%.*]] = sub i32 [[SUB164]], 14253// CHECK2-NEXT: [[ADD166:%.*]] = add i32 [[SUB165]], 14254// CHECK2-NEXT: [[DIV167:%.*]] = udiv i32 [[ADD166]], 14255// CHECK2-NEXT: [[MUL168:%.*]] = mul i32 [[MUL163]], [[DIV167]]4256// CHECK2-NEXT: [[CONV169:%.*]] = zext i32 [[MUL168]] to i644257// CHECK2-NEXT: [[DIV170:%.*]] = sdiv i64 [[TMP98]], [[CONV169]]4258// CHECK2-NEXT: [[TMP106:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 44259// CHECK2-NEXT: [[TMP107:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 44260// CHECK2-NEXT: [[SUB171:%.*]] = sub i32 [[TMP106]], [[TMP107]]4261// CHECK2-NEXT: [[SUB172:%.*]] = sub i32 [[SUB171]], 14262// CHECK2-NEXT: [[TMP108:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44263// CHECK2-NEXT: [[ADD173:%.*]] = add i32 [[SUB172]], [[TMP108]]4264// CHECK2-NEXT: [[TMP109:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44265// CHECK2-NEXT: [[DIV174:%.*]] = udiv i32 [[ADD173]], [[TMP109]]4266// CHECK2-NEXT: [[MUL175:%.*]] = mul i32 1, [[DIV174]]4267// CHECK2-NEXT: [[TMP110:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 44268// CHECK2-NEXT: [[SUB176:%.*]] = sub i32 [[TMP110]], -314269// CHECK2-NEXT: [[DIV177:%.*]] = udiv i32 [[SUB176]], 324270// CHECK2-NEXT: [[MUL178:%.*]] = mul i32 [[MUL175]], [[DIV177]]4271// CHECK2-NEXT: [[TMP111:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 44272// CHECK2-NEXT: [[TMP112:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 44273// CHECK2-NEXT: [[SUB179:%.*]] = sub i32 [[TMP111]], [[TMP112]]4274// CHECK2-NEXT: [[SUB180:%.*]] = sub i32 [[SUB179]], 14275// CHECK2-NEXT: [[ADD181:%.*]] = add i32 [[SUB180]], 14276// CHECK2-NEXT: [[DIV182:%.*]] = udiv i32 [[ADD181]], 14277// CHECK2-NEXT: [[MUL183:%.*]] = mul i32 [[MUL178]], [[DIV182]]4278// CHECK2-NEXT: [[CONV184:%.*]] = zext i32 [[MUL183]] to i644279// CHECK2-NEXT: [[MUL185:%.*]] = mul nsw i64 [[DIV170]], [[CONV184]]4280// CHECK2-NEXT: [[SUB186:%.*]] = sub nsw i64 [[TMP97]], [[MUL185]]4281// CHECK2-NEXT: [[TMP113:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 44282// CHECK2-NEXT: [[SUB187:%.*]] = sub i32 [[TMP113]], -314283// CHECK2-NEXT: [[DIV188:%.*]] = udiv i32 [[SUB187]], 324284// CHECK2-NEXT: [[MUL189:%.*]] = mul i32 1, [[DIV188]]4285// CHECK2-NEXT: [[TMP114:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 44286// CHECK2-NEXT: [[TMP115:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 44287// CHECK2-NEXT: [[SUB190:%.*]] = sub i32 [[TMP114]], [[TMP115]]4288// CHECK2-NEXT: [[SUB191:%.*]] = sub i32 [[SUB190]], 14289// CHECK2-NEXT: [[ADD192:%.*]] = add i32 [[SUB191]], 14290// CHECK2-NEXT: [[DIV193:%.*]] = udiv i32 [[ADD192]], 14291// CHECK2-NEXT: [[MUL194:%.*]] = mul i32 [[MUL189]], [[DIV193]]4292// CHECK2-NEXT: [[CONV195:%.*]] = zext i32 [[MUL194]] to i644293// CHECK2-NEXT: [[DIV196:%.*]] = sdiv i64 [[SUB186]], [[CONV195]]4294// CHECK2-NEXT: [[TMP116:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 44295// CHECK2-NEXT: [[SUB197:%.*]] = sub i32 [[TMP116]], -314296// CHECK2-NEXT: [[DIV198:%.*]] = udiv i32 [[SUB197]], 324297// CHECK2-NEXT: [[MUL199:%.*]] = mul i32 1, [[DIV198]]4298// CHECK2-NEXT: [[TMP117:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 44299// CHECK2-NEXT: [[TMP118:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 44300// CHECK2-NEXT: [[SUB200:%.*]] = sub i32 [[TMP117]], [[TMP118]]4301// CHECK2-NEXT: [[SUB201:%.*]] = sub i32 [[SUB200]], 14302// CHECK2-NEXT: [[ADD202:%.*]] = add i32 [[SUB201]], 14303// CHECK2-NEXT: [[DIV203:%.*]] = udiv i32 [[ADD202]], 14304// CHECK2-NEXT: [[MUL204:%.*]] = mul i32 [[MUL199]], [[DIV203]]4305// CHECK2-NEXT: [[CONV205:%.*]] = zext i32 [[MUL204]] to i644306// CHECK2-NEXT: [[MUL206:%.*]] = mul nsw i64 [[DIV196]], [[CONV205]]4307// CHECK2-NEXT: [[SUB207:%.*]] = sub nsw i64 [[SUB155]], [[MUL206]]4308// CHECK2-NEXT: [[TMP119:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 44309// CHECK2-NEXT: [[TMP120:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 44310// CHECK2-NEXT: [[SUB208:%.*]] = sub i32 [[TMP119]], [[TMP120]]4311// CHECK2-NEXT: [[SUB209:%.*]] = sub i32 [[SUB208]], 14312// CHECK2-NEXT: [[ADD210:%.*]] = add i32 [[SUB209]], 14313// CHECK2-NEXT: [[DIV211:%.*]] = udiv i32 [[ADD210]], 14314// CHECK2-NEXT: [[MUL212:%.*]] = mul i32 1, [[DIV211]]4315// CHECK2-NEXT: [[CONV213:%.*]] = zext i32 [[MUL212]] to i644316// CHECK2-NEXT: [[DIV214:%.*]] = sdiv i64 [[SUB207]], [[CONV213]]4317// CHECK2-NEXT: [[MUL215:%.*]] = mul nsw i64 [[DIV214]], 324318// CHECK2-NEXT: [[ADD216:%.*]] = add nsw i64 0, [[MUL215]]4319// CHECK2-NEXT: [[CONV217:%.*]] = trunc i64 [[ADD216]] to i324320// CHECK2-NEXT: store i32 [[CONV217]], ptr [[DOTFLOOR_0_IV_K51]], align 44321// CHECK2-NEXT: [[TMP121:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 44322// CHECK2-NEXT: [[CONV218:%.*]] = zext i32 [[TMP121]] to i644323// CHECK2-NEXT: [[TMP122:%.*]] = load i64, ptr [[DOTOMP_IV]], align 84324// CHECK2-NEXT: [[TMP123:%.*]] = load i64, ptr [[DOTOMP_IV]], align 84325// CHECK2-NEXT: [[TMP124:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 44326// CHECK2-NEXT: [[TMP125:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 44327// CHECK2-NEXT: [[SUB219:%.*]] = sub i32 [[TMP124]], [[TMP125]]4328// CHECK2-NEXT: [[SUB220:%.*]] = sub i32 [[SUB219]], 14329// CHECK2-NEXT: [[TMP126:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44330// CHECK2-NEXT: [[ADD221:%.*]] = add i32 [[SUB220]], [[TMP126]]4331// CHECK2-NEXT: [[TMP127:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44332// CHECK2-NEXT: [[DIV222:%.*]] = udiv i32 [[ADD221]], [[TMP127]]4333// CHECK2-NEXT: [[MUL223:%.*]] = mul i32 1, [[DIV222]]4334// CHECK2-NEXT: [[TMP128:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 44335// CHECK2-NEXT: [[SUB224:%.*]] = sub i32 [[TMP128]], -314336// CHECK2-NEXT: [[DIV225:%.*]] = udiv i32 [[SUB224]], 324337// CHECK2-NEXT: [[MUL226:%.*]] = mul i32 [[MUL223]], [[DIV225]]4338// CHECK2-NEXT: [[TMP129:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 44339// CHECK2-NEXT: [[TMP130:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 44340// CHECK2-NEXT: [[SUB227:%.*]] = sub i32 [[TMP129]], [[TMP130]]4341// CHECK2-NEXT: [[SUB228:%.*]] = sub i32 [[SUB227]], 14342// CHECK2-NEXT: [[ADD229:%.*]] = add i32 [[SUB228]], 14343// CHECK2-NEXT: [[DIV230:%.*]] = udiv i32 [[ADD229]], 14344// CHECK2-NEXT: [[MUL231:%.*]] = mul i32 [[MUL226]], [[DIV230]]4345// CHECK2-NEXT: [[CONV232:%.*]] = zext i32 [[MUL231]] to i644346// CHECK2-NEXT: [[DIV233:%.*]] = sdiv i64 [[TMP123]], [[CONV232]]4347// CHECK2-NEXT: [[TMP131:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 44348// CHECK2-NEXT: [[TMP132:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 44349// CHECK2-NEXT: [[SUB234:%.*]] = sub i32 [[TMP131]], [[TMP132]]4350// CHECK2-NEXT: [[SUB235:%.*]] = sub i32 [[SUB234]], 14351// CHECK2-NEXT: [[TMP133:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44352// CHECK2-NEXT: [[ADD236:%.*]] = add i32 [[SUB235]], [[TMP133]]4353// CHECK2-NEXT: [[TMP134:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44354// CHECK2-NEXT: [[DIV237:%.*]] = udiv i32 [[ADD236]], [[TMP134]]4355// CHECK2-NEXT: [[MUL238:%.*]] = mul i32 1, [[DIV237]]4356// CHECK2-NEXT: [[TMP135:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 44357// CHECK2-NEXT: [[SUB239:%.*]] = sub i32 [[TMP135]], -314358// CHECK2-NEXT: [[DIV240:%.*]] = udiv i32 [[SUB239]], 324359// CHECK2-NEXT: [[MUL241:%.*]] = mul i32 [[MUL238]], [[DIV240]]4360// CHECK2-NEXT: [[TMP136:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 44361// CHECK2-NEXT: [[TMP137:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 44362// CHECK2-NEXT: [[SUB242:%.*]] = sub i32 [[TMP136]], [[TMP137]]4363// CHECK2-NEXT: [[SUB243:%.*]] = sub i32 [[SUB242]], 14364// CHECK2-NEXT: [[ADD244:%.*]] = add i32 [[SUB243]], 14365// CHECK2-NEXT: [[DIV245:%.*]] = udiv i32 [[ADD244]], 14366// CHECK2-NEXT: [[MUL246:%.*]] = mul i32 [[MUL241]], [[DIV245]]4367// CHECK2-NEXT: [[CONV247:%.*]] = zext i32 [[MUL246]] to i644368// CHECK2-NEXT: [[MUL248:%.*]] = mul nsw i64 [[DIV233]], [[CONV247]]4369// CHECK2-NEXT: [[SUB249:%.*]] = sub nsw i64 [[TMP122]], [[MUL248]]4370// CHECK2-NEXT: [[TMP138:%.*]] = load i64, ptr [[DOTOMP_IV]], align 84371// CHECK2-NEXT: [[TMP139:%.*]] = load i64, ptr [[DOTOMP_IV]], align 84372// CHECK2-NEXT: [[TMP140:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 44373// CHECK2-NEXT: [[TMP141:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 44374// CHECK2-NEXT: [[SUB250:%.*]] = sub i32 [[TMP140]], [[TMP141]]4375// CHECK2-NEXT: [[SUB251:%.*]] = sub i32 [[SUB250]], 14376// CHECK2-NEXT: [[TMP142:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44377// CHECK2-NEXT: [[ADD252:%.*]] = add i32 [[SUB251]], [[TMP142]]4378// CHECK2-NEXT: [[TMP143:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44379// CHECK2-NEXT: [[DIV253:%.*]] = udiv i32 [[ADD252]], [[TMP143]]4380// CHECK2-NEXT: [[MUL254:%.*]] = mul i32 1, [[DIV253]]4381// CHECK2-NEXT: [[TMP144:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 44382// CHECK2-NEXT: [[SUB255:%.*]] = sub i32 [[TMP144]], -314383// CHECK2-NEXT: [[DIV256:%.*]] = udiv i32 [[SUB255]], 324384// CHECK2-NEXT: [[MUL257:%.*]] = mul i32 [[MUL254]], [[DIV256]]4385// CHECK2-NEXT: [[TMP145:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 44386// CHECK2-NEXT: [[TMP146:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 44387// CHECK2-NEXT: [[SUB258:%.*]] = sub i32 [[TMP145]], [[TMP146]]4388// CHECK2-NEXT: [[SUB259:%.*]] = sub i32 [[SUB258]], 14389// CHECK2-NEXT: [[ADD260:%.*]] = add i32 [[SUB259]], 14390// CHECK2-NEXT: [[DIV261:%.*]] = udiv i32 [[ADD260]], 14391// CHECK2-NEXT: [[MUL262:%.*]] = mul i32 [[MUL257]], [[DIV261]]4392// CHECK2-NEXT: [[CONV263:%.*]] = zext i32 [[MUL262]] to i644393// CHECK2-NEXT: [[DIV264:%.*]] = sdiv i64 [[TMP139]], [[CONV263]]4394// CHECK2-NEXT: [[TMP147:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 44395// CHECK2-NEXT: [[TMP148:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 44396// CHECK2-NEXT: [[SUB265:%.*]] = sub i32 [[TMP147]], [[TMP148]]4397// CHECK2-NEXT: [[SUB266:%.*]] = sub i32 [[SUB265]], 14398// CHECK2-NEXT: [[TMP149:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44399// CHECK2-NEXT: [[ADD267:%.*]] = add i32 [[SUB266]], [[TMP149]]4400// CHECK2-NEXT: [[TMP150:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44401// CHECK2-NEXT: [[DIV268:%.*]] = udiv i32 [[ADD267]], [[TMP150]]4402// CHECK2-NEXT: [[MUL269:%.*]] = mul i32 1, [[DIV268]]4403// CHECK2-NEXT: [[TMP151:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 44404// CHECK2-NEXT: [[SUB270:%.*]] = sub i32 [[TMP151]], -314405// CHECK2-NEXT: [[DIV271:%.*]] = udiv i32 [[SUB270]], 324406// CHECK2-NEXT: [[MUL272:%.*]] = mul i32 [[MUL269]], [[DIV271]]4407// CHECK2-NEXT: [[TMP152:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 44408// CHECK2-NEXT: [[TMP153:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 44409// CHECK2-NEXT: [[SUB273:%.*]] = sub i32 [[TMP152]], [[TMP153]]4410// CHECK2-NEXT: [[SUB274:%.*]] = sub i32 [[SUB273]], 14411// CHECK2-NEXT: [[ADD275:%.*]] = add i32 [[SUB274]], 14412// CHECK2-NEXT: [[DIV276:%.*]] = udiv i32 [[ADD275]], 14413// CHECK2-NEXT: [[MUL277:%.*]] = mul i32 [[MUL272]], [[DIV276]]4414// CHECK2-NEXT: [[CONV278:%.*]] = zext i32 [[MUL277]] to i644415// CHECK2-NEXT: [[MUL279:%.*]] = mul nsw i64 [[DIV264]], [[CONV278]]4416// CHECK2-NEXT: [[SUB280:%.*]] = sub nsw i64 [[TMP138]], [[MUL279]]4417// CHECK2-NEXT: [[TMP154:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 44418// CHECK2-NEXT: [[SUB281:%.*]] = sub i32 [[TMP154]], -314419// CHECK2-NEXT: [[DIV282:%.*]] = udiv i32 [[SUB281]], 324420// CHECK2-NEXT: [[MUL283:%.*]] = mul i32 1, [[DIV282]]4421// CHECK2-NEXT: [[TMP155:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 44422// CHECK2-NEXT: [[TMP156:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 44423// CHECK2-NEXT: [[SUB284:%.*]] = sub i32 [[TMP155]], [[TMP156]]4424// CHECK2-NEXT: [[SUB285:%.*]] = sub i32 [[SUB284]], 14425// CHECK2-NEXT: [[ADD286:%.*]] = add i32 [[SUB285]], 14426// CHECK2-NEXT: [[DIV287:%.*]] = udiv i32 [[ADD286]], 14427// CHECK2-NEXT: [[MUL288:%.*]] = mul i32 [[MUL283]], [[DIV287]]4428// CHECK2-NEXT: [[CONV289:%.*]] = zext i32 [[MUL288]] to i644429// CHECK2-NEXT: [[DIV290:%.*]] = sdiv i64 [[SUB280]], [[CONV289]]4430// CHECK2-NEXT: [[TMP157:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 44431// CHECK2-NEXT: [[SUB291:%.*]] = sub i32 [[TMP157]], -314432// CHECK2-NEXT: [[DIV292:%.*]] = udiv i32 [[SUB291]], 324433// CHECK2-NEXT: [[MUL293:%.*]] = mul i32 1, [[DIV292]]4434// CHECK2-NEXT: [[TMP158:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 44435// CHECK2-NEXT: [[TMP159:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 44436// CHECK2-NEXT: [[SUB294:%.*]] = sub i32 [[TMP158]], [[TMP159]]4437// CHECK2-NEXT: [[SUB295:%.*]] = sub i32 [[SUB294]], 14438// CHECK2-NEXT: [[ADD296:%.*]] = add i32 [[SUB295]], 14439// CHECK2-NEXT: [[DIV297:%.*]] = udiv i32 [[ADD296]], 14440// CHECK2-NEXT: [[MUL298:%.*]] = mul i32 [[MUL293]], [[DIV297]]4441// CHECK2-NEXT: [[CONV299:%.*]] = zext i32 [[MUL298]] to i644442// CHECK2-NEXT: [[MUL300:%.*]] = mul nsw i64 [[DIV290]], [[CONV299]]4443// CHECK2-NEXT: [[SUB301:%.*]] = sub nsw i64 [[SUB249]], [[MUL300]]4444// CHECK2-NEXT: [[TMP160:%.*]] = load i64, ptr [[DOTOMP_IV]], align 84445// CHECK2-NEXT: [[TMP161:%.*]] = load i64, ptr [[DOTOMP_IV]], align 84446// CHECK2-NEXT: [[TMP162:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 44447// CHECK2-NEXT: [[TMP163:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 44448// CHECK2-NEXT: [[SUB302:%.*]] = sub i32 [[TMP162]], [[TMP163]]4449// CHECK2-NEXT: [[SUB303:%.*]] = sub i32 [[SUB302]], 14450// CHECK2-NEXT: [[TMP164:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44451// CHECK2-NEXT: [[ADD304:%.*]] = add i32 [[SUB303]], [[TMP164]]4452// CHECK2-NEXT: [[TMP165:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44453// CHECK2-NEXT: [[DIV305:%.*]] = udiv i32 [[ADD304]], [[TMP165]]4454// CHECK2-NEXT: [[MUL306:%.*]] = mul i32 1, [[DIV305]]4455// CHECK2-NEXT: [[TMP166:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 44456// CHECK2-NEXT: [[SUB307:%.*]] = sub i32 [[TMP166]], -314457// CHECK2-NEXT: [[DIV308:%.*]] = udiv i32 [[SUB307]], 324458// CHECK2-NEXT: [[MUL309:%.*]] = mul i32 [[MUL306]], [[DIV308]]4459// CHECK2-NEXT: [[TMP167:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 44460// CHECK2-NEXT: [[TMP168:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 44461// CHECK2-NEXT: [[SUB310:%.*]] = sub i32 [[TMP167]], [[TMP168]]4462// CHECK2-NEXT: [[SUB311:%.*]] = sub i32 [[SUB310]], 14463// CHECK2-NEXT: [[ADD312:%.*]] = add i32 [[SUB311]], 14464// CHECK2-NEXT: [[DIV313:%.*]] = udiv i32 [[ADD312]], 14465// CHECK2-NEXT: [[MUL314:%.*]] = mul i32 [[MUL309]], [[DIV313]]4466// CHECK2-NEXT: [[CONV315:%.*]] = zext i32 [[MUL314]] to i644467// CHECK2-NEXT: [[DIV316:%.*]] = sdiv i64 [[TMP161]], [[CONV315]]4468// CHECK2-NEXT: [[TMP169:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 44469// CHECK2-NEXT: [[TMP170:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 44470// CHECK2-NEXT: [[SUB317:%.*]] = sub i32 [[TMP169]], [[TMP170]]4471// CHECK2-NEXT: [[SUB318:%.*]] = sub i32 [[SUB317]], 14472// CHECK2-NEXT: [[TMP171:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44473// CHECK2-NEXT: [[ADD319:%.*]] = add i32 [[SUB318]], [[TMP171]]4474// CHECK2-NEXT: [[TMP172:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44475// CHECK2-NEXT: [[DIV320:%.*]] = udiv i32 [[ADD319]], [[TMP172]]4476// CHECK2-NEXT: [[MUL321:%.*]] = mul i32 1, [[DIV320]]4477// CHECK2-NEXT: [[TMP173:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 44478// CHECK2-NEXT: [[SUB322:%.*]] = sub i32 [[TMP173]], -314479// CHECK2-NEXT: [[DIV323:%.*]] = udiv i32 [[SUB322]], 324480// CHECK2-NEXT: [[MUL324:%.*]] = mul i32 [[MUL321]], [[DIV323]]4481// CHECK2-NEXT: [[TMP174:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 44482// CHECK2-NEXT: [[TMP175:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 44483// CHECK2-NEXT: [[SUB325:%.*]] = sub i32 [[TMP174]], [[TMP175]]4484// CHECK2-NEXT: [[SUB326:%.*]] = sub i32 [[SUB325]], 14485// CHECK2-NEXT: [[ADD327:%.*]] = add i32 [[SUB326]], 14486// CHECK2-NEXT: [[DIV328:%.*]] = udiv i32 [[ADD327]], 14487// CHECK2-NEXT: [[MUL329:%.*]] = mul i32 [[MUL324]], [[DIV328]]4488// CHECK2-NEXT: [[CONV330:%.*]] = zext i32 [[MUL329]] to i644489// CHECK2-NEXT: [[MUL331:%.*]] = mul nsw i64 [[DIV316]], [[CONV330]]4490// CHECK2-NEXT: [[SUB332:%.*]] = sub nsw i64 [[TMP160]], [[MUL331]]4491// CHECK2-NEXT: [[TMP176:%.*]] = load i64, ptr [[DOTOMP_IV]], align 84492// CHECK2-NEXT: [[TMP177:%.*]] = load i64, ptr [[DOTOMP_IV]], align 84493// CHECK2-NEXT: [[TMP178:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 44494// CHECK2-NEXT: [[TMP179:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 44495// CHECK2-NEXT: [[SUB333:%.*]] = sub i32 [[TMP178]], [[TMP179]]4496// CHECK2-NEXT: [[SUB334:%.*]] = sub i32 [[SUB333]], 14497// CHECK2-NEXT: [[TMP180:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44498// CHECK2-NEXT: [[ADD335:%.*]] = add i32 [[SUB334]], [[TMP180]]4499// CHECK2-NEXT: [[TMP181:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44500// CHECK2-NEXT: [[DIV336:%.*]] = udiv i32 [[ADD335]], [[TMP181]]4501// CHECK2-NEXT: [[MUL337:%.*]] = mul i32 1, [[DIV336]]4502// CHECK2-NEXT: [[TMP182:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 44503// CHECK2-NEXT: [[SUB338:%.*]] = sub i32 [[TMP182]], -314504// CHECK2-NEXT: [[DIV339:%.*]] = udiv i32 [[SUB338]], 324505// CHECK2-NEXT: [[MUL340:%.*]] = mul i32 [[MUL337]], [[DIV339]]4506// CHECK2-NEXT: [[TMP183:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 44507// CHECK2-NEXT: [[TMP184:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 44508// CHECK2-NEXT: [[SUB341:%.*]] = sub i32 [[TMP183]], [[TMP184]]4509// CHECK2-NEXT: [[SUB342:%.*]] = sub i32 [[SUB341]], 14510// CHECK2-NEXT: [[ADD343:%.*]] = add i32 [[SUB342]], 14511// CHECK2-NEXT: [[DIV344:%.*]] = udiv i32 [[ADD343]], 14512// CHECK2-NEXT: [[MUL345:%.*]] = mul i32 [[MUL340]], [[DIV344]]4513// CHECK2-NEXT: [[CONV346:%.*]] = zext i32 [[MUL345]] to i644514// CHECK2-NEXT: [[DIV347:%.*]] = sdiv i64 [[TMP177]], [[CONV346]]4515// CHECK2-NEXT: [[TMP185:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 44516// CHECK2-NEXT: [[TMP186:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 44517// CHECK2-NEXT: [[SUB348:%.*]] = sub i32 [[TMP185]], [[TMP186]]4518// CHECK2-NEXT: [[SUB349:%.*]] = sub i32 [[SUB348]], 14519// CHECK2-NEXT: [[TMP187:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44520// CHECK2-NEXT: [[ADD350:%.*]] = add i32 [[SUB349]], [[TMP187]]4521// CHECK2-NEXT: [[TMP188:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44522// CHECK2-NEXT: [[DIV351:%.*]] = udiv i32 [[ADD350]], [[TMP188]]4523// CHECK2-NEXT: [[MUL352:%.*]] = mul i32 1, [[DIV351]]4524// CHECK2-NEXT: [[TMP189:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 44525// CHECK2-NEXT: [[SUB353:%.*]] = sub i32 [[TMP189]], -314526// CHECK2-NEXT: [[DIV354:%.*]] = udiv i32 [[SUB353]], 324527// CHECK2-NEXT: [[MUL355:%.*]] = mul i32 [[MUL352]], [[DIV354]]4528// CHECK2-NEXT: [[TMP190:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 44529// CHECK2-NEXT: [[TMP191:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 44530// CHECK2-NEXT: [[SUB356:%.*]] = sub i32 [[TMP190]], [[TMP191]]4531// CHECK2-NEXT: [[SUB357:%.*]] = sub i32 [[SUB356]], 14532// CHECK2-NEXT: [[ADD358:%.*]] = add i32 [[SUB357]], 14533// CHECK2-NEXT: [[DIV359:%.*]] = udiv i32 [[ADD358]], 14534// CHECK2-NEXT: [[MUL360:%.*]] = mul i32 [[MUL355]], [[DIV359]]4535// CHECK2-NEXT: [[CONV361:%.*]] = zext i32 [[MUL360]] to i644536// CHECK2-NEXT: [[MUL362:%.*]] = mul nsw i64 [[DIV347]], [[CONV361]]4537// CHECK2-NEXT: [[SUB363:%.*]] = sub nsw i64 [[TMP176]], [[MUL362]]4538// CHECK2-NEXT: [[TMP192:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 44539// CHECK2-NEXT: [[SUB364:%.*]] = sub i32 [[TMP192]], -314540// CHECK2-NEXT: [[DIV365:%.*]] = udiv i32 [[SUB364]], 324541// CHECK2-NEXT: [[MUL366:%.*]] = mul i32 1, [[DIV365]]4542// CHECK2-NEXT: [[TMP193:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 44543// CHECK2-NEXT: [[TMP194:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 44544// CHECK2-NEXT: [[SUB367:%.*]] = sub i32 [[TMP193]], [[TMP194]]4545// CHECK2-NEXT: [[SUB368:%.*]] = sub i32 [[SUB367]], 14546// CHECK2-NEXT: [[ADD369:%.*]] = add i32 [[SUB368]], 14547// CHECK2-NEXT: [[DIV370:%.*]] = udiv i32 [[ADD369]], 14548// CHECK2-NEXT: [[MUL371:%.*]] = mul i32 [[MUL366]], [[DIV370]]4549// CHECK2-NEXT: [[CONV372:%.*]] = zext i32 [[MUL371]] to i644550// CHECK2-NEXT: [[DIV373:%.*]] = sdiv i64 [[SUB363]], [[CONV372]]4551// CHECK2-NEXT: [[TMP195:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 44552// CHECK2-NEXT: [[SUB374:%.*]] = sub i32 [[TMP195]], -314553// CHECK2-NEXT: [[DIV375:%.*]] = udiv i32 [[SUB374]], 324554// CHECK2-NEXT: [[MUL376:%.*]] = mul i32 1, [[DIV375]]4555// CHECK2-NEXT: [[TMP196:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 44556// CHECK2-NEXT: [[TMP197:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 44557// CHECK2-NEXT: [[SUB377:%.*]] = sub i32 [[TMP196]], [[TMP197]]4558// CHECK2-NEXT: [[SUB378:%.*]] = sub i32 [[SUB377]], 14559// CHECK2-NEXT: [[ADD379:%.*]] = add i32 [[SUB378]], 14560// CHECK2-NEXT: [[DIV380:%.*]] = udiv i32 [[ADD379]], 14561// CHECK2-NEXT: [[MUL381:%.*]] = mul i32 [[MUL376]], [[DIV380]]4562// CHECK2-NEXT: [[CONV382:%.*]] = zext i32 [[MUL381]] to i644563// CHECK2-NEXT: [[MUL383:%.*]] = mul nsw i64 [[DIV373]], [[CONV382]]4564// CHECK2-NEXT: [[SUB384:%.*]] = sub nsw i64 [[SUB332]], [[MUL383]]4565// CHECK2-NEXT: [[TMP198:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 44566// CHECK2-NEXT: [[TMP199:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 44567// CHECK2-NEXT: [[SUB385:%.*]] = sub i32 [[TMP198]], [[TMP199]]4568// CHECK2-NEXT: [[SUB386:%.*]] = sub i32 [[SUB385]], 14569// CHECK2-NEXT: [[ADD387:%.*]] = add i32 [[SUB386]], 14570// CHECK2-NEXT: [[DIV388:%.*]] = udiv i32 [[ADD387]], 14571// CHECK2-NEXT: [[MUL389:%.*]] = mul i32 1, [[DIV388]]4572// CHECK2-NEXT: [[CONV390:%.*]] = zext i32 [[MUL389]] to i644573// CHECK2-NEXT: [[DIV391:%.*]] = sdiv i64 [[SUB384]], [[CONV390]]4574// CHECK2-NEXT: [[TMP200:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 44575// CHECK2-NEXT: [[TMP201:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 44576// CHECK2-NEXT: [[SUB392:%.*]] = sub i32 [[TMP200]], [[TMP201]]4577// CHECK2-NEXT: [[SUB393:%.*]] = sub i32 [[SUB392]], 14578// CHECK2-NEXT: [[ADD394:%.*]] = add i32 [[SUB393]], 14579// CHECK2-NEXT: [[DIV395:%.*]] = udiv i32 [[ADD394]], 14580// CHECK2-NEXT: [[MUL396:%.*]] = mul i32 1, [[DIV395]]4581// CHECK2-NEXT: [[CONV397:%.*]] = zext i32 [[MUL396]] to i644582// CHECK2-NEXT: [[MUL398:%.*]] = mul nsw i64 [[DIV391]], [[CONV397]]4583// CHECK2-NEXT: [[SUB399:%.*]] = sub nsw i64 [[SUB301]], [[MUL398]]4584// CHECK2-NEXT: [[MUL400:%.*]] = mul nsw i64 [[SUB399]], 14585// CHECK2-NEXT: [[ADD401:%.*]] = add nsw i64 [[CONV218]], [[MUL400]]4586// CHECK2-NEXT: [[CONV402:%.*]] = trunc i64 [[ADD401]] to i324587// CHECK2-NEXT: store i32 [[CONV402]], ptr [[DOTTILE_0_IV_K52]], align 44588// CHECK2-NEXT: [[TMP202:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_8]], align 44589// CHECK2-NEXT: [[TMP203:%.*]] = load i32, ptr [[DOTTILE_0_IV_K52]], align 44590// CHECK2-NEXT: [[TMP204:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 44591// CHECK2-NEXT: [[MUL403:%.*]] = mul i32 [[TMP203]], [[TMP204]]4592// CHECK2-NEXT: [[ADD404:%.*]] = add i32 [[TMP202]], [[MUL403]]4593// CHECK2-NEXT: store i32 [[ADD404]], ptr [[K]], align 44594// CHECK2-NEXT: [[TMP205:%.*]] = load i32, ptr [[I49]], align 44595// CHECK2-NEXT: [[TMP206:%.*]] = load i32, ptr [[J50]], align 44596// CHECK2-NEXT: [[TMP207:%.*]] = load i32, ptr [[K]], align 44597// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP205]], i32 noundef [[TMP206]], i32 noundef [[TMP207]])4598// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]4599// CHECK2: omp.body.continue:4600// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]4601// CHECK2: omp.inner.for.inc:4602// CHECK2-NEXT: [[TMP208:%.*]] = load i64, ptr [[DOTOMP_IV]], align 84603// CHECK2-NEXT: [[ADD405:%.*]] = add nsw i64 [[TMP208]], 14604// CHECK2-NEXT: store i64 [[ADD405]], ptr [[DOTOMP_IV]], align 84605// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]4606// CHECK2: omp.inner.for.end:4607// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]4608// CHECK2: omp.loop.exit:4609// CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]])4610// CHECK2-NEXT: br label [[OMP_PRECOND_END]]4611// CHECK2: omp.precond.end:4612// CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]])4613// CHECK2-NEXT: ret void4614//4615//4616// CHECK2-LABEL: define {{[^@]+}}@_Z4foo8ILi64EEviii4617// CHECK2-SAME: (i32 noundef [[START:%.*]], i32 noundef [[END:%.*]], i32 noundef [[STEP:%.*]]) #[[ATTR0]] comdat {4618// CHECK2-NEXT: entry:4619// CHECK2-NEXT: [[START_ADDR:%.*]] = alloca i32, align 44620// CHECK2-NEXT: [[END_ADDR:%.*]] = alloca i32, align 44621// CHECK2-NEXT: [[STEP_ADDR:%.*]] = alloca i32, align 44622// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 84623// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 44624// CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 44625// CHECK2-NEXT: [[_TMP2:%.*]] = alloca i32, align 44626// CHECK2-NEXT: [[_TMP3:%.*]] = alloca i32, align 44627// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 44628// CHECK2-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 44629// CHECK2-NEXT: [[DOTNEW_STEP:%.*]] = alloca i32, align 44630// CHECK2-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 44631// CHECK2-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i32, align 44632// CHECK2-NEXT: [[DOTNEW_STEP7:%.*]] = alloca i32, align 44633// CHECK2-NEXT: [[K:%.*]] = alloca i32, align 44634// CHECK2-NEXT: [[DOTCAPTURE_EXPR_8:%.*]] = alloca i32, align 44635// CHECK2-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 44636// CHECK2-NEXT: [[DOTNEW_STEP10:%.*]] = alloca i32, align 44637// CHECK2-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 44638// CHECK2-NEXT: [[DOTCAPTURE_EXPR_14:%.*]] = alloca i32, align 44639// CHECK2-NEXT: [[DOTCAPTURE_EXPR_16:%.*]] = alloca i32, align 44640// CHECK2-NEXT: [[DOTCAPTURE_EXPR_17:%.*]] = alloca i32, align 44641// CHECK2-NEXT: [[DOTCAPTURE_EXPR_22:%.*]] = alloca i64, align 84642// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 44643// CHECK2-NEXT: [[J:%.*]] = alloca i32, align 44644// CHECK2-NEXT: [[DOTFLOOR_0_IV_K:%.*]] = alloca i32, align 44645// CHECK2-NEXT: [[DOTTILE_0_IV_K:%.*]] = alloca i32, align 44646// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 84647// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 84648// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 84649// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 44650// CHECK2-NEXT: [[I49:%.*]] = alloca i32, align 44651// CHECK2-NEXT: [[J50:%.*]] = alloca i32, align 44652// CHECK2-NEXT: [[DOTFLOOR_0_IV_K51:%.*]] = alloca i32, align 44653// CHECK2-NEXT: [[DOTTILE_0_IV_K52:%.*]] = alloca i32, align 44654// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])4655// CHECK2-NEXT: store i32 [[START]], ptr [[START_ADDR]], align 44656// CHECK2-NEXT: store i32 [[END]], ptr [[END_ADDR]], align 44657// CHECK2-NEXT: store i32 [[STEP]], ptr [[STEP_ADDR]], align 44658// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[START_ADDR]], align 44659// CHECK2-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 44660// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[END_ADDR]], align 44661// CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_4]], align 44662// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[STEP_ADDR]], align 44663// CHECK2-NEXT: store i32 [[TMP3]], ptr [[DOTNEW_STEP]], align 44664// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[START_ADDR]], align 44665// CHECK2-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_5]], align 44666// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[END_ADDR]], align 44667// CHECK2-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_6]], align 44668// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[STEP_ADDR]], align 44669// CHECK2-NEXT: store i32 [[TMP6]], ptr [[DOTNEW_STEP7]], align 44670// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[START_ADDR]], align 44671// CHECK2-NEXT: store i32 [[TMP7]], ptr [[K]], align 44672// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[START_ADDR]], align 44673// CHECK2-NEXT: store i32 [[TMP8]], ptr [[DOTCAPTURE_EXPR_8]], align 44674// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[END_ADDR]], align 44675// CHECK2-NEXT: store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR_9]], align 44676// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[STEP_ADDR]], align 44677// CHECK2-NEXT: store i32 [[TMP10]], ptr [[DOTNEW_STEP10]], align 44678// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_9]], align 44679// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_8]], align 44680// CHECK2-NEXT: [[SUB:%.*]] = sub i32 [[TMP11]], [[TMP12]]4681// CHECK2-NEXT: [[SUB12:%.*]] = sub i32 [[SUB]], 14682// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 44683// CHECK2-NEXT: [[ADD:%.*]] = add i32 [[SUB12]], [[TMP13]]4684// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 44685// CHECK2-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], [[TMP14]]4686// CHECK2-NEXT: [[SUB13:%.*]] = sub i32 [[DIV]], 14687// CHECK2-NEXT: store i32 [[SUB13]], ptr [[DOTCAPTURE_EXPR_11]], align 44688// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 44689// CHECK2-NEXT: [[ADD15:%.*]] = add i32 [[TMP15]], 14690// CHECK2-NEXT: store i32 [[ADD15]], ptr [[DOTCAPTURE_EXPR_14]], align 44691// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[_TMP2]], align 44692// CHECK2-NEXT: store i32 [[TMP16]], ptr [[DOTCAPTURE_EXPR_16]], align 44693// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 44694// CHECK2-NEXT: [[ADD18:%.*]] = add i32 [[TMP17]], 14695// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[_TMP2]], align 44696// CHECK2-NEXT: [[ADD19:%.*]] = add i32 [[TMP18]], 644697// CHECK2-NEXT: [[CMP:%.*]] = icmp ult i32 [[ADD18]], [[ADD19]]4698// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]4699// CHECK2: cond.true:4700// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 44701// CHECK2-NEXT: [[ADD20:%.*]] = add i32 [[TMP19]], 14702// CHECK2-NEXT: br label [[COND_END:%.*]]4703// CHECK2: cond.false:4704// CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[_TMP2]], align 44705// CHECK2-NEXT: [[ADD21:%.*]] = add i32 [[TMP20]], 644706// CHECK2-NEXT: br label [[COND_END]]4707// CHECK2: cond.end:4708// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ [[ADD20]], [[COND_TRUE]] ], [ [[ADD21]], [[COND_FALSE]] ]4709// CHECK2-NEXT: store i32 [[COND]], ptr [[DOTCAPTURE_EXPR_17]], align 44710// CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 44711// CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 44712// CHECK2-NEXT: [[SUB23:%.*]] = sub i32 [[TMP21]], [[TMP22]]4713// CHECK2-NEXT: [[SUB24:%.*]] = sub i32 [[SUB23]], 14714// CHECK2-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 44715// CHECK2-NEXT: [[ADD25:%.*]] = add i32 [[SUB24]], [[TMP23]]4716// CHECK2-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 44717// CHECK2-NEXT: [[DIV26:%.*]] = udiv i32 [[ADD25]], [[TMP24]]4718// CHECK2-NEXT: [[CONV:%.*]] = zext i32 [[DIV26]] to i644719// CHECK2-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 44720// CHECK2-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 44721// CHECK2-NEXT: [[SUB27:%.*]] = sub i32 [[TMP25]], [[TMP26]]4722// CHECK2-NEXT: [[SUB28:%.*]] = sub i32 [[SUB27]], 14723// CHECK2-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44724// CHECK2-NEXT: [[ADD29:%.*]] = add i32 [[SUB28]], [[TMP27]]4725// CHECK2-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44726// CHECK2-NEXT: [[DIV30:%.*]] = udiv i32 [[ADD29]], [[TMP28]]4727// CHECK2-NEXT: [[CONV31:%.*]] = zext i32 [[DIV30]] to i644728// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV31]]4729// CHECK2-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 44730// CHECK2-NEXT: [[SUB32:%.*]] = sub i32 [[TMP29]], -634731// CHECK2-NEXT: [[DIV33:%.*]] = udiv i32 [[SUB32]], 644732// CHECK2-NEXT: [[CONV34:%.*]] = zext i32 [[DIV33]] to i644733// CHECK2-NEXT: [[MUL35:%.*]] = mul nsw i64 [[MUL]], [[CONV34]]4734// CHECK2-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 44735// CHECK2-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 44736// CHECK2-NEXT: [[SUB36:%.*]] = sub i32 [[TMP30]], [[TMP31]]4737// CHECK2-NEXT: [[SUB37:%.*]] = sub i32 [[SUB36]], 14738// CHECK2-NEXT: [[ADD38:%.*]] = add i32 [[SUB37]], 14739// CHECK2-NEXT: [[DIV39:%.*]] = udiv i32 [[ADD38]], 14740// CHECK2-NEXT: [[CONV40:%.*]] = zext i32 [[DIV39]] to i644741// CHECK2-NEXT: [[MUL41:%.*]] = mul nsw i64 [[MUL35]], [[CONV40]]4742// CHECK2-NEXT: [[SUB42:%.*]] = sub nsw i64 [[MUL41]], 14743// CHECK2-NEXT: store i64 [[SUB42]], ptr [[DOTCAPTURE_EXPR_22]], align 84744// CHECK2-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 44745// CHECK2-NEXT: store i32 [[TMP32]], ptr [[I]], align 44746// CHECK2-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 44747// CHECK2-NEXT: store i32 [[TMP33]], ptr [[J]], align 44748// CHECK2-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV_K]], align 44749// CHECK2-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 44750// CHECK2-NEXT: store i32 [[TMP34]], ptr [[DOTTILE_0_IV_K]], align 44751// CHECK2-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 44752// CHECK2-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 44753// CHECK2-NEXT: [[CMP43:%.*]] = icmp slt i32 [[TMP35]], [[TMP36]]4754// CHECK2-NEXT: br i1 [[CMP43]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]4755// CHECK2: land.lhs.true:4756// CHECK2-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 44757// CHECK2-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 44758// CHECK2-NEXT: [[CMP44:%.*]] = icmp slt i32 [[TMP37]], [[TMP38]]4759// CHECK2-NEXT: br i1 [[CMP44]], label [[LAND_LHS_TRUE45:%.*]], label [[OMP_PRECOND_END]]4760// CHECK2: land.lhs.true45:4761// CHECK2-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 44762// CHECK2-NEXT: [[CMP46:%.*]] = icmp ult i32 0, [[TMP39]]4763// CHECK2-NEXT: br i1 [[CMP46]], label [[LAND_LHS_TRUE47:%.*]], label [[OMP_PRECOND_END]]4764// CHECK2: land.lhs.true47:4765// CHECK2-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 44766// CHECK2-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 44767// CHECK2-NEXT: [[CMP48:%.*]] = icmp ult i32 [[TMP40]], [[TMP41]]4768// CHECK2-NEXT: br i1 [[CMP48]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]4769// CHECK2: omp.precond.then:4770// CHECK2-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 84771// CHECK2-NEXT: [[TMP42:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 84772// CHECK2-NEXT: store i64 [[TMP42]], ptr [[DOTOMP_UB]], align 84773// CHECK2-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 84774// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 44775// CHECK2-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)4776// CHECK2-NEXT: [[TMP43:%.*]] = load i64, ptr [[DOTOMP_UB]], align 84777// CHECK2-NEXT: [[TMP44:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 84778// CHECK2-NEXT: [[CMP53:%.*]] = icmp sgt i64 [[TMP43]], [[TMP44]]4779// CHECK2-NEXT: br i1 [[CMP53]], label [[COND_TRUE54:%.*]], label [[COND_FALSE55:%.*]]4780// CHECK2: cond.true54:4781// CHECK2-NEXT: [[TMP45:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 84782// CHECK2-NEXT: br label [[COND_END56:%.*]]4783// CHECK2: cond.false55:4784// CHECK2-NEXT: [[TMP46:%.*]] = load i64, ptr [[DOTOMP_UB]], align 84785// CHECK2-NEXT: br label [[COND_END56]]4786// CHECK2: cond.end56:4787// CHECK2-NEXT: [[COND57:%.*]] = phi i64 [ [[TMP45]], [[COND_TRUE54]] ], [ [[TMP46]], [[COND_FALSE55]] ]4788// CHECK2-NEXT: store i64 [[COND57]], ptr [[DOTOMP_UB]], align 84789// CHECK2-NEXT: [[TMP47:%.*]] = load i64, ptr [[DOTOMP_LB]], align 84790// CHECK2-NEXT: store i64 [[TMP47]], ptr [[DOTOMP_IV]], align 84791// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]4792// CHECK2: omp.inner.for.cond:4793// CHECK2-NEXT: [[TMP48:%.*]] = load i64, ptr [[DOTOMP_IV]], align 84794// CHECK2-NEXT: [[TMP49:%.*]] = load i64, ptr [[DOTOMP_UB]], align 84795// CHECK2-NEXT: [[CMP58:%.*]] = icmp sle i64 [[TMP48]], [[TMP49]]4796// CHECK2-NEXT: br i1 [[CMP58]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]4797// CHECK2: omp.inner.for.body:4798// CHECK2-NEXT: [[TMP50:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 44799// CHECK2-NEXT: [[CONV59:%.*]] = sext i32 [[TMP50]] to i644800// CHECK2-NEXT: [[TMP51:%.*]] = load i64, ptr [[DOTOMP_IV]], align 84801// CHECK2-NEXT: [[TMP52:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 44802// CHECK2-NEXT: [[TMP53:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 44803// CHECK2-NEXT: [[SUB60:%.*]] = sub i32 [[TMP52]], [[TMP53]]4804// CHECK2-NEXT: [[SUB61:%.*]] = sub i32 [[SUB60]], 14805// CHECK2-NEXT: [[TMP54:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44806// CHECK2-NEXT: [[ADD62:%.*]] = add i32 [[SUB61]], [[TMP54]]4807// CHECK2-NEXT: [[TMP55:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44808// CHECK2-NEXT: [[DIV63:%.*]] = udiv i32 [[ADD62]], [[TMP55]]4809// CHECK2-NEXT: [[MUL64:%.*]] = mul i32 1, [[DIV63]]4810// CHECK2-NEXT: [[TMP56:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 44811// CHECK2-NEXT: [[SUB65:%.*]] = sub i32 [[TMP56]], -634812// CHECK2-NEXT: [[DIV66:%.*]] = udiv i32 [[SUB65]], 644813// CHECK2-NEXT: [[MUL67:%.*]] = mul i32 [[MUL64]], [[DIV66]]4814// CHECK2-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 44815// CHECK2-NEXT: [[TMP58:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 44816// CHECK2-NEXT: [[SUB68:%.*]] = sub i32 [[TMP57]], [[TMP58]]4817// CHECK2-NEXT: [[SUB69:%.*]] = sub i32 [[SUB68]], 14818// CHECK2-NEXT: [[ADD70:%.*]] = add i32 [[SUB69]], 14819// CHECK2-NEXT: [[DIV71:%.*]] = udiv i32 [[ADD70]], 14820// CHECK2-NEXT: [[MUL72:%.*]] = mul i32 [[MUL67]], [[DIV71]]4821// CHECK2-NEXT: [[CONV73:%.*]] = zext i32 [[MUL72]] to i644822// CHECK2-NEXT: [[DIV74:%.*]] = sdiv i64 [[TMP51]], [[CONV73]]4823// CHECK2-NEXT: [[TMP59:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 44824// CHECK2-NEXT: [[CONV75:%.*]] = sext i32 [[TMP59]] to i644825// CHECK2-NEXT: [[MUL76:%.*]] = mul nsw i64 [[DIV74]], [[CONV75]]4826// CHECK2-NEXT: [[ADD77:%.*]] = add nsw i64 [[CONV59]], [[MUL76]]4827// CHECK2-NEXT: [[CONV78:%.*]] = trunc i64 [[ADD77]] to i324828// CHECK2-NEXT: store i32 [[CONV78]], ptr [[I49]], align 44829// CHECK2-NEXT: [[TMP60:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 44830// CHECK2-NEXT: [[CONV79:%.*]] = sext i32 [[TMP60]] to i644831// CHECK2-NEXT: [[TMP61:%.*]] = load i64, ptr [[DOTOMP_IV]], align 84832// CHECK2-NEXT: [[TMP62:%.*]] = load i64, ptr [[DOTOMP_IV]], align 84833// CHECK2-NEXT: [[TMP63:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 44834// CHECK2-NEXT: [[TMP64:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 44835// CHECK2-NEXT: [[SUB80:%.*]] = sub i32 [[TMP63]], [[TMP64]]4836// CHECK2-NEXT: [[SUB81:%.*]] = sub i32 [[SUB80]], 14837// CHECK2-NEXT: [[TMP65:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44838// CHECK2-NEXT: [[ADD82:%.*]] = add i32 [[SUB81]], [[TMP65]]4839// CHECK2-NEXT: [[TMP66:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44840// CHECK2-NEXT: [[DIV83:%.*]] = udiv i32 [[ADD82]], [[TMP66]]4841// CHECK2-NEXT: [[MUL84:%.*]] = mul i32 1, [[DIV83]]4842// CHECK2-NEXT: [[TMP67:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 44843// CHECK2-NEXT: [[SUB85:%.*]] = sub i32 [[TMP67]], -634844// CHECK2-NEXT: [[DIV86:%.*]] = udiv i32 [[SUB85]], 644845// CHECK2-NEXT: [[MUL87:%.*]] = mul i32 [[MUL84]], [[DIV86]]4846// CHECK2-NEXT: [[TMP68:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 44847// CHECK2-NEXT: [[TMP69:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 44848// CHECK2-NEXT: [[SUB88:%.*]] = sub i32 [[TMP68]], [[TMP69]]4849// CHECK2-NEXT: [[SUB89:%.*]] = sub i32 [[SUB88]], 14850// CHECK2-NEXT: [[ADD90:%.*]] = add i32 [[SUB89]], 14851// CHECK2-NEXT: [[DIV91:%.*]] = udiv i32 [[ADD90]], 14852// CHECK2-NEXT: [[MUL92:%.*]] = mul i32 [[MUL87]], [[DIV91]]4853// CHECK2-NEXT: [[CONV93:%.*]] = zext i32 [[MUL92]] to i644854// CHECK2-NEXT: [[DIV94:%.*]] = sdiv i64 [[TMP62]], [[CONV93]]4855// CHECK2-NEXT: [[TMP70:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 44856// CHECK2-NEXT: [[TMP71:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 44857// CHECK2-NEXT: [[SUB95:%.*]] = sub i32 [[TMP70]], [[TMP71]]4858// CHECK2-NEXT: [[SUB96:%.*]] = sub i32 [[SUB95]], 14859// CHECK2-NEXT: [[TMP72:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44860// CHECK2-NEXT: [[ADD97:%.*]] = add i32 [[SUB96]], [[TMP72]]4861// CHECK2-NEXT: [[TMP73:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44862// CHECK2-NEXT: [[DIV98:%.*]] = udiv i32 [[ADD97]], [[TMP73]]4863// CHECK2-NEXT: [[MUL99:%.*]] = mul i32 1, [[DIV98]]4864// CHECK2-NEXT: [[TMP74:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 44865// CHECK2-NEXT: [[SUB100:%.*]] = sub i32 [[TMP74]], -634866// CHECK2-NEXT: [[DIV101:%.*]] = udiv i32 [[SUB100]], 644867// CHECK2-NEXT: [[MUL102:%.*]] = mul i32 [[MUL99]], [[DIV101]]4868// CHECK2-NEXT: [[TMP75:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 44869// CHECK2-NEXT: [[TMP76:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 44870// CHECK2-NEXT: [[SUB103:%.*]] = sub i32 [[TMP75]], [[TMP76]]4871// CHECK2-NEXT: [[SUB104:%.*]] = sub i32 [[SUB103]], 14872// CHECK2-NEXT: [[ADD105:%.*]] = add i32 [[SUB104]], 14873// CHECK2-NEXT: [[DIV106:%.*]] = udiv i32 [[ADD105]], 14874// CHECK2-NEXT: [[MUL107:%.*]] = mul i32 [[MUL102]], [[DIV106]]4875// CHECK2-NEXT: [[CONV108:%.*]] = zext i32 [[MUL107]] to i644876// CHECK2-NEXT: [[MUL109:%.*]] = mul nsw i64 [[DIV94]], [[CONV108]]4877// CHECK2-NEXT: [[SUB110:%.*]] = sub nsw i64 [[TMP61]], [[MUL109]]4878// CHECK2-NEXT: [[TMP77:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 44879// CHECK2-NEXT: [[SUB111:%.*]] = sub i32 [[TMP77]], -634880// CHECK2-NEXT: [[DIV112:%.*]] = udiv i32 [[SUB111]], 644881// CHECK2-NEXT: [[MUL113:%.*]] = mul i32 1, [[DIV112]]4882// CHECK2-NEXT: [[TMP78:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 44883// CHECK2-NEXT: [[TMP79:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 44884// CHECK2-NEXT: [[SUB114:%.*]] = sub i32 [[TMP78]], [[TMP79]]4885// CHECK2-NEXT: [[SUB115:%.*]] = sub i32 [[SUB114]], 14886// CHECK2-NEXT: [[ADD116:%.*]] = add i32 [[SUB115]], 14887// CHECK2-NEXT: [[DIV117:%.*]] = udiv i32 [[ADD116]], 14888// CHECK2-NEXT: [[MUL118:%.*]] = mul i32 [[MUL113]], [[DIV117]]4889// CHECK2-NEXT: [[CONV119:%.*]] = zext i32 [[MUL118]] to i644890// CHECK2-NEXT: [[DIV120:%.*]] = sdiv i64 [[SUB110]], [[CONV119]]4891// CHECK2-NEXT: [[TMP80:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44892// CHECK2-NEXT: [[CONV121:%.*]] = sext i32 [[TMP80]] to i644893// CHECK2-NEXT: [[MUL122:%.*]] = mul nsw i64 [[DIV120]], [[CONV121]]4894// CHECK2-NEXT: [[ADD123:%.*]] = add nsw i64 [[CONV79]], [[MUL122]]4895// CHECK2-NEXT: [[CONV124:%.*]] = trunc i64 [[ADD123]] to i324896// CHECK2-NEXT: store i32 [[CONV124]], ptr [[J50]], align 44897// CHECK2-NEXT: [[TMP81:%.*]] = load i64, ptr [[DOTOMP_IV]], align 84898// CHECK2-NEXT: [[TMP82:%.*]] = load i64, ptr [[DOTOMP_IV]], align 84899// CHECK2-NEXT: [[TMP83:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 44900// CHECK2-NEXT: [[TMP84:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 44901// CHECK2-NEXT: [[SUB125:%.*]] = sub i32 [[TMP83]], [[TMP84]]4902// CHECK2-NEXT: [[SUB126:%.*]] = sub i32 [[SUB125]], 14903// CHECK2-NEXT: [[TMP85:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44904// CHECK2-NEXT: [[ADD127:%.*]] = add i32 [[SUB126]], [[TMP85]]4905// CHECK2-NEXT: [[TMP86:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44906// CHECK2-NEXT: [[DIV128:%.*]] = udiv i32 [[ADD127]], [[TMP86]]4907// CHECK2-NEXT: [[MUL129:%.*]] = mul i32 1, [[DIV128]]4908// CHECK2-NEXT: [[TMP87:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 44909// CHECK2-NEXT: [[SUB130:%.*]] = sub i32 [[TMP87]], -634910// CHECK2-NEXT: [[DIV131:%.*]] = udiv i32 [[SUB130]], 644911// CHECK2-NEXT: [[MUL132:%.*]] = mul i32 [[MUL129]], [[DIV131]]4912// CHECK2-NEXT: [[TMP88:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 44913// CHECK2-NEXT: [[TMP89:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 44914// CHECK2-NEXT: [[SUB133:%.*]] = sub i32 [[TMP88]], [[TMP89]]4915// CHECK2-NEXT: [[SUB134:%.*]] = sub i32 [[SUB133]], 14916// CHECK2-NEXT: [[ADD135:%.*]] = add i32 [[SUB134]], 14917// CHECK2-NEXT: [[DIV136:%.*]] = udiv i32 [[ADD135]], 14918// CHECK2-NEXT: [[MUL137:%.*]] = mul i32 [[MUL132]], [[DIV136]]4919// CHECK2-NEXT: [[CONV138:%.*]] = zext i32 [[MUL137]] to i644920// CHECK2-NEXT: [[DIV139:%.*]] = sdiv i64 [[TMP82]], [[CONV138]]4921// CHECK2-NEXT: [[TMP90:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 44922// CHECK2-NEXT: [[TMP91:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 44923// CHECK2-NEXT: [[SUB140:%.*]] = sub i32 [[TMP90]], [[TMP91]]4924// CHECK2-NEXT: [[SUB141:%.*]] = sub i32 [[SUB140]], 14925// CHECK2-NEXT: [[TMP92:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44926// CHECK2-NEXT: [[ADD142:%.*]] = add i32 [[SUB141]], [[TMP92]]4927// CHECK2-NEXT: [[TMP93:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44928// CHECK2-NEXT: [[DIV143:%.*]] = udiv i32 [[ADD142]], [[TMP93]]4929// CHECK2-NEXT: [[MUL144:%.*]] = mul i32 1, [[DIV143]]4930// CHECK2-NEXT: [[TMP94:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 44931// CHECK2-NEXT: [[SUB145:%.*]] = sub i32 [[TMP94]], -634932// CHECK2-NEXT: [[DIV146:%.*]] = udiv i32 [[SUB145]], 644933// CHECK2-NEXT: [[MUL147:%.*]] = mul i32 [[MUL144]], [[DIV146]]4934// CHECK2-NEXT: [[TMP95:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 44935// CHECK2-NEXT: [[TMP96:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 44936// CHECK2-NEXT: [[SUB148:%.*]] = sub i32 [[TMP95]], [[TMP96]]4937// CHECK2-NEXT: [[SUB149:%.*]] = sub i32 [[SUB148]], 14938// CHECK2-NEXT: [[ADD150:%.*]] = add i32 [[SUB149]], 14939// CHECK2-NEXT: [[DIV151:%.*]] = udiv i32 [[ADD150]], 14940// CHECK2-NEXT: [[MUL152:%.*]] = mul i32 [[MUL147]], [[DIV151]]4941// CHECK2-NEXT: [[CONV153:%.*]] = zext i32 [[MUL152]] to i644942// CHECK2-NEXT: [[MUL154:%.*]] = mul nsw i64 [[DIV139]], [[CONV153]]4943// CHECK2-NEXT: [[SUB155:%.*]] = sub nsw i64 [[TMP81]], [[MUL154]]4944// CHECK2-NEXT: [[TMP97:%.*]] = load i64, ptr [[DOTOMP_IV]], align 84945// CHECK2-NEXT: [[TMP98:%.*]] = load i64, ptr [[DOTOMP_IV]], align 84946// CHECK2-NEXT: [[TMP99:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 44947// CHECK2-NEXT: [[TMP100:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 44948// CHECK2-NEXT: [[SUB156:%.*]] = sub i32 [[TMP99]], [[TMP100]]4949// CHECK2-NEXT: [[SUB157:%.*]] = sub i32 [[SUB156]], 14950// CHECK2-NEXT: [[TMP101:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44951// CHECK2-NEXT: [[ADD158:%.*]] = add i32 [[SUB157]], [[TMP101]]4952// CHECK2-NEXT: [[TMP102:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44953// CHECK2-NEXT: [[DIV159:%.*]] = udiv i32 [[ADD158]], [[TMP102]]4954// CHECK2-NEXT: [[MUL160:%.*]] = mul i32 1, [[DIV159]]4955// CHECK2-NEXT: [[TMP103:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 44956// CHECK2-NEXT: [[SUB161:%.*]] = sub i32 [[TMP103]], -634957// CHECK2-NEXT: [[DIV162:%.*]] = udiv i32 [[SUB161]], 644958// CHECK2-NEXT: [[MUL163:%.*]] = mul i32 [[MUL160]], [[DIV162]]4959// CHECK2-NEXT: [[TMP104:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 44960// CHECK2-NEXT: [[TMP105:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 44961// CHECK2-NEXT: [[SUB164:%.*]] = sub i32 [[TMP104]], [[TMP105]]4962// CHECK2-NEXT: [[SUB165:%.*]] = sub i32 [[SUB164]], 14963// CHECK2-NEXT: [[ADD166:%.*]] = add i32 [[SUB165]], 14964// CHECK2-NEXT: [[DIV167:%.*]] = udiv i32 [[ADD166]], 14965// CHECK2-NEXT: [[MUL168:%.*]] = mul i32 [[MUL163]], [[DIV167]]4966// CHECK2-NEXT: [[CONV169:%.*]] = zext i32 [[MUL168]] to i644967// CHECK2-NEXT: [[DIV170:%.*]] = sdiv i64 [[TMP98]], [[CONV169]]4968// CHECK2-NEXT: [[TMP106:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 44969// CHECK2-NEXT: [[TMP107:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 44970// CHECK2-NEXT: [[SUB171:%.*]] = sub i32 [[TMP106]], [[TMP107]]4971// CHECK2-NEXT: [[SUB172:%.*]] = sub i32 [[SUB171]], 14972// CHECK2-NEXT: [[TMP108:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44973// CHECK2-NEXT: [[ADD173:%.*]] = add i32 [[SUB172]], [[TMP108]]4974// CHECK2-NEXT: [[TMP109:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 44975// CHECK2-NEXT: [[DIV174:%.*]] = udiv i32 [[ADD173]], [[TMP109]]4976// CHECK2-NEXT: [[MUL175:%.*]] = mul i32 1, [[DIV174]]4977// CHECK2-NEXT: [[TMP110:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 44978// CHECK2-NEXT: [[SUB176:%.*]] = sub i32 [[TMP110]], -634979// CHECK2-NEXT: [[DIV177:%.*]] = udiv i32 [[SUB176]], 644980// CHECK2-NEXT: [[MUL178:%.*]] = mul i32 [[MUL175]], [[DIV177]]4981// CHECK2-NEXT: [[TMP111:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 44982// CHECK2-NEXT: [[TMP112:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 44983// CHECK2-NEXT: [[SUB179:%.*]] = sub i32 [[TMP111]], [[TMP112]]4984// CHECK2-NEXT: [[SUB180:%.*]] = sub i32 [[SUB179]], 14985// CHECK2-NEXT: [[ADD181:%.*]] = add i32 [[SUB180]], 14986// CHECK2-NEXT: [[DIV182:%.*]] = udiv i32 [[ADD181]], 14987// CHECK2-NEXT: [[MUL183:%.*]] = mul i32 [[MUL178]], [[DIV182]]4988// CHECK2-NEXT: [[CONV184:%.*]] = zext i32 [[MUL183]] to i644989// CHECK2-NEXT: [[MUL185:%.*]] = mul nsw i64 [[DIV170]], [[CONV184]]4990// CHECK2-NEXT: [[SUB186:%.*]] = sub nsw i64 [[TMP97]], [[MUL185]]4991// CHECK2-NEXT: [[TMP113:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 44992// CHECK2-NEXT: [[SUB187:%.*]] = sub i32 [[TMP113]], -634993// CHECK2-NEXT: [[DIV188:%.*]] = udiv i32 [[SUB187]], 644994// CHECK2-NEXT: [[MUL189:%.*]] = mul i32 1, [[DIV188]]4995// CHECK2-NEXT: [[TMP114:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 44996// CHECK2-NEXT: [[TMP115:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 44997// CHECK2-NEXT: [[SUB190:%.*]] = sub i32 [[TMP114]], [[TMP115]]4998// CHECK2-NEXT: [[SUB191:%.*]] = sub i32 [[SUB190]], 14999// CHECK2-NEXT: [[ADD192:%.*]] = add i32 [[SUB191]], 15000// CHECK2-NEXT: [[DIV193:%.*]] = udiv i32 [[ADD192]], 15001// CHECK2-NEXT: [[MUL194:%.*]] = mul i32 [[MUL189]], [[DIV193]]5002// CHECK2-NEXT: [[CONV195:%.*]] = zext i32 [[MUL194]] to i645003// CHECK2-NEXT: [[DIV196:%.*]] = sdiv i64 [[SUB186]], [[CONV195]]5004// CHECK2-NEXT: [[TMP116:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 45005// CHECK2-NEXT: [[SUB197:%.*]] = sub i32 [[TMP116]], -635006// CHECK2-NEXT: [[DIV198:%.*]] = udiv i32 [[SUB197]], 645007// CHECK2-NEXT: [[MUL199:%.*]] = mul i32 1, [[DIV198]]5008// CHECK2-NEXT: [[TMP117:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 45009// CHECK2-NEXT: [[TMP118:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 45010// CHECK2-NEXT: [[SUB200:%.*]] = sub i32 [[TMP117]], [[TMP118]]5011// CHECK2-NEXT: [[SUB201:%.*]] = sub i32 [[SUB200]], 15012// CHECK2-NEXT: [[ADD202:%.*]] = add i32 [[SUB201]], 15013// CHECK2-NEXT: [[DIV203:%.*]] = udiv i32 [[ADD202]], 15014// CHECK2-NEXT: [[MUL204:%.*]] = mul i32 [[MUL199]], [[DIV203]]5015// CHECK2-NEXT: [[CONV205:%.*]] = zext i32 [[MUL204]] to i645016// CHECK2-NEXT: [[MUL206:%.*]] = mul nsw i64 [[DIV196]], [[CONV205]]5017// CHECK2-NEXT: [[SUB207:%.*]] = sub nsw i64 [[SUB155]], [[MUL206]]5018// CHECK2-NEXT: [[TMP119:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 45019// CHECK2-NEXT: [[TMP120:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 45020// CHECK2-NEXT: [[SUB208:%.*]] = sub i32 [[TMP119]], [[TMP120]]5021// CHECK2-NEXT: [[SUB209:%.*]] = sub i32 [[SUB208]], 15022// CHECK2-NEXT: [[ADD210:%.*]] = add i32 [[SUB209]], 15023// CHECK2-NEXT: [[DIV211:%.*]] = udiv i32 [[ADD210]], 15024// CHECK2-NEXT: [[MUL212:%.*]] = mul i32 1, [[DIV211]]5025// CHECK2-NEXT: [[CONV213:%.*]] = zext i32 [[MUL212]] to i645026// CHECK2-NEXT: [[DIV214:%.*]] = sdiv i64 [[SUB207]], [[CONV213]]5027// CHECK2-NEXT: [[MUL215:%.*]] = mul nsw i64 [[DIV214]], 645028// CHECK2-NEXT: [[ADD216:%.*]] = add nsw i64 0, [[MUL215]]5029// CHECK2-NEXT: [[CONV217:%.*]] = trunc i64 [[ADD216]] to i325030// CHECK2-NEXT: store i32 [[CONV217]], ptr [[DOTFLOOR_0_IV_K51]], align 45031// CHECK2-NEXT: [[TMP121:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 45032// CHECK2-NEXT: [[CONV218:%.*]] = zext i32 [[TMP121]] to i645033// CHECK2-NEXT: [[TMP122:%.*]] = load i64, ptr [[DOTOMP_IV]], align 85034// CHECK2-NEXT: [[TMP123:%.*]] = load i64, ptr [[DOTOMP_IV]], align 85035// CHECK2-NEXT: [[TMP124:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 45036// CHECK2-NEXT: [[TMP125:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 45037// CHECK2-NEXT: [[SUB219:%.*]] = sub i32 [[TMP124]], [[TMP125]]5038// CHECK2-NEXT: [[SUB220:%.*]] = sub i32 [[SUB219]], 15039// CHECK2-NEXT: [[TMP126:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 45040// CHECK2-NEXT: [[ADD221:%.*]] = add i32 [[SUB220]], [[TMP126]]5041// CHECK2-NEXT: [[TMP127:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 45042// CHECK2-NEXT: [[DIV222:%.*]] = udiv i32 [[ADD221]], [[TMP127]]5043// CHECK2-NEXT: [[MUL223:%.*]] = mul i32 1, [[DIV222]]5044// CHECK2-NEXT: [[TMP128:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 45045// CHECK2-NEXT: [[SUB224:%.*]] = sub i32 [[TMP128]], -635046// CHECK2-NEXT: [[DIV225:%.*]] = udiv i32 [[SUB224]], 645047// CHECK2-NEXT: [[MUL226:%.*]] = mul i32 [[MUL223]], [[DIV225]]5048// CHECK2-NEXT: [[TMP129:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 45049// CHECK2-NEXT: [[TMP130:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 45050// CHECK2-NEXT: [[SUB227:%.*]] = sub i32 [[TMP129]], [[TMP130]]5051// CHECK2-NEXT: [[SUB228:%.*]] = sub i32 [[SUB227]], 15052// CHECK2-NEXT: [[ADD229:%.*]] = add i32 [[SUB228]], 15053// CHECK2-NEXT: [[DIV230:%.*]] = udiv i32 [[ADD229]], 15054// CHECK2-NEXT: [[MUL231:%.*]] = mul i32 [[MUL226]], [[DIV230]]5055// CHECK2-NEXT: [[CONV232:%.*]] = zext i32 [[MUL231]] to i645056// CHECK2-NEXT: [[DIV233:%.*]] = sdiv i64 [[TMP123]], [[CONV232]]5057// CHECK2-NEXT: [[TMP131:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 45058// CHECK2-NEXT: [[TMP132:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 45059// CHECK2-NEXT: [[SUB234:%.*]] = sub i32 [[TMP131]], [[TMP132]]5060// CHECK2-NEXT: [[SUB235:%.*]] = sub i32 [[SUB234]], 15061// CHECK2-NEXT: [[TMP133:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 45062// CHECK2-NEXT: [[ADD236:%.*]] = add i32 [[SUB235]], [[TMP133]]5063// CHECK2-NEXT: [[TMP134:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 45064// CHECK2-NEXT: [[DIV237:%.*]] = udiv i32 [[ADD236]], [[TMP134]]5065// CHECK2-NEXT: [[MUL238:%.*]] = mul i32 1, [[DIV237]]5066// CHECK2-NEXT: [[TMP135:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 45067// CHECK2-NEXT: [[SUB239:%.*]] = sub i32 [[TMP135]], -635068// CHECK2-NEXT: [[DIV240:%.*]] = udiv i32 [[SUB239]], 645069// CHECK2-NEXT: [[MUL241:%.*]] = mul i32 [[MUL238]], [[DIV240]]5070// CHECK2-NEXT: [[TMP136:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 45071// CHECK2-NEXT: [[TMP137:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 45072// CHECK2-NEXT: [[SUB242:%.*]] = sub i32 [[TMP136]], [[TMP137]]5073// CHECK2-NEXT: [[SUB243:%.*]] = sub i32 [[SUB242]], 15074// CHECK2-NEXT: [[ADD244:%.*]] = add i32 [[SUB243]], 15075// CHECK2-NEXT: [[DIV245:%.*]] = udiv i32 [[ADD244]], 15076// CHECK2-NEXT: [[MUL246:%.*]] = mul i32 [[MUL241]], [[DIV245]]5077// CHECK2-NEXT: [[CONV247:%.*]] = zext i32 [[MUL246]] to i645078// CHECK2-NEXT: [[MUL248:%.*]] = mul nsw i64 [[DIV233]], [[CONV247]]5079// CHECK2-NEXT: [[SUB249:%.*]] = sub nsw i64 [[TMP122]], [[MUL248]]5080// CHECK2-NEXT: [[TMP138:%.*]] = load i64, ptr [[DOTOMP_IV]], align 85081// CHECK2-NEXT: [[TMP139:%.*]] = load i64, ptr [[DOTOMP_IV]], align 85082// CHECK2-NEXT: [[TMP140:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 45083// CHECK2-NEXT: [[TMP141:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 45084// CHECK2-NEXT: [[SUB250:%.*]] = sub i32 [[TMP140]], [[TMP141]]5085// CHECK2-NEXT: [[SUB251:%.*]] = sub i32 [[SUB250]], 15086// CHECK2-NEXT: [[TMP142:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 45087// CHECK2-NEXT: [[ADD252:%.*]] = add i32 [[SUB251]], [[TMP142]]5088// CHECK2-NEXT: [[TMP143:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 45089// CHECK2-NEXT: [[DIV253:%.*]] = udiv i32 [[ADD252]], [[TMP143]]5090// CHECK2-NEXT: [[MUL254:%.*]] = mul i32 1, [[DIV253]]5091// CHECK2-NEXT: [[TMP144:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 45092// CHECK2-NEXT: [[SUB255:%.*]] = sub i32 [[TMP144]], -635093// CHECK2-NEXT: [[DIV256:%.*]] = udiv i32 [[SUB255]], 645094// CHECK2-NEXT: [[MUL257:%.*]] = mul i32 [[MUL254]], [[DIV256]]5095// CHECK2-NEXT: [[TMP145:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 45096// CHECK2-NEXT: [[TMP146:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 45097// CHECK2-NEXT: [[SUB258:%.*]] = sub i32 [[TMP145]], [[TMP146]]5098// CHECK2-NEXT: [[SUB259:%.*]] = sub i32 [[SUB258]], 15099// CHECK2-NEXT: [[ADD260:%.*]] = add i32 [[SUB259]], 15100// CHECK2-NEXT: [[DIV261:%.*]] = udiv i32 [[ADD260]], 15101// CHECK2-NEXT: [[MUL262:%.*]] = mul i32 [[MUL257]], [[DIV261]]5102// CHECK2-NEXT: [[CONV263:%.*]] = zext i32 [[MUL262]] to i645103// CHECK2-NEXT: [[DIV264:%.*]] = sdiv i64 [[TMP139]], [[CONV263]]5104// CHECK2-NEXT: [[TMP147:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 45105// CHECK2-NEXT: [[TMP148:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 45106// CHECK2-NEXT: [[SUB265:%.*]] = sub i32 [[TMP147]], [[TMP148]]5107// CHECK2-NEXT: [[SUB266:%.*]] = sub i32 [[SUB265]], 15108// CHECK2-NEXT: [[TMP149:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 45109// CHECK2-NEXT: [[ADD267:%.*]] = add i32 [[SUB266]], [[TMP149]]5110// CHECK2-NEXT: [[TMP150:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 45111// CHECK2-NEXT: [[DIV268:%.*]] = udiv i32 [[ADD267]], [[TMP150]]5112// CHECK2-NEXT: [[MUL269:%.*]] = mul i32 1, [[DIV268]]5113// CHECK2-NEXT: [[TMP151:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 45114// CHECK2-NEXT: [[SUB270:%.*]] = sub i32 [[TMP151]], -635115// CHECK2-NEXT: [[DIV271:%.*]] = udiv i32 [[SUB270]], 645116// CHECK2-NEXT: [[MUL272:%.*]] = mul i32 [[MUL269]], [[DIV271]]5117// CHECK2-NEXT: [[TMP152:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 45118// CHECK2-NEXT: [[TMP153:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 45119// CHECK2-NEXT: [[SUB273:%.*]] = sub i32 [[TMP152]], [[TMP153]]5120// CHECK2-NEXT: [[SUB274:%.*]] = sub i32 [[SUB273]], 15121// CHECK2-NEXT: [[ADD275:%.*]] = add i32 [[SUB274]], 15122// CHECK2-NEXT: [[DIV276:%.*]] = udiv i32 [[ADD275]], 15123// CHECK2-NEXT: [[MUL277:%.*]] = mul i32 [[MUL272]], [[DIV276]]5124// CHECK2-NEXT: [[CONV278:%.*]] = zext i32 [[MUL277]] to i645125// CHECK2-NEXT: [[MUL279:%.*]] = mul nsw i64 [[DIV264]], [[CONV278]]5126// CHECK2-NEXT: [[SUB280:%.*]] = sub nsw i64 [[TMP138]], [[MUL279]]5127// CHECK2-NEXT: [[TMP154:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 45128// CHECK2-NEXT: [[SUB281:%.*]] = sub i32 [[TMP154]], -635129// CHECK2-NEXT: [[DIV282:%.*]] = udiv i32 [[SUB281]], 645130// CHECK2-NEXT: [[MUL283:%.*]] = mul i32 1, [[DIV282]]5131// CHECK2-NEXT: [[TMP155:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 45132// CHECK2-NEXT: [[TMP156:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 45133// CHECK2-NEXT: [[SUB284:%.*]] = sub i32 [[TMP155]], [[TMP156]]5134// CHECK2-NEXT: [[SUB285:%.*]] = sub i32 [[SUB284]], 15135// CHECK2-NEXT: [[ADD286:%.*]] = add i32 [[SUB285]], 15136// CHECK2-NEXT: [[DIV287:%.*]] = udiv i32 [[ADD286]], 15137// CHECK2-NEXT: [[MUL288:%.*]] = mul i32 [[MUL283]], [[DIV287]]5138// CHECK2-NEXT: [[CONV289:%.*]] = zext i32 [[MUL288]] to i645139// CHECK2-NEXT: [[DIV290:%.*]] = sdiv i64 [[SUB280]], [[CONV289]]5140// CHECK2-NEXT: [[TMP157:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 45141// CHECK2-NEXT: [[SUB291:%.*]] = sub i32 [[TMP157]], -635142// CHECK2-NEXT: [[DIV292:%.*]] = udiv i32 [[SUB291]], 645143// CHECK2-NEXT: [[MUL293:%.*]] = mul i32 1, [[DIV292]]5144// CHECK2-NEXT: [[TMP158:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 45145// CHECK2-NEXT: [[TMP159:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 45146// CHECK2-NEXT: [[SUB294:%.*]] = sub i32 [[TMP158]], [[TMP159]]5147// CHECK2-NEXT: [[SUB295:%.*]] = sub i32 [[SUB294]], 15148// CHECK2-NEXT: [[ADD296:%.*]] = add i32 [[SUB295]], 15149// CHECK2-NEXT: [[DIV297:%.*]] = udiv i32 [[ADD296]], 15150// CHECK2-NEXT: [[MUL298:%.*]] = mul i32 [[MUL293]], [[DIV297]]5151// CHECK2-NEXT: [[CONV299:%.*]] = zext i32 [[MUL298]] to i645152// CHECK2-NEXT: [[MUL300:%.*]] = mul nsw i64 [[DIV290]], [[CONV299]]5153// CHECK2-NEXT: [[SUB301:%.*]] = sub nsw i64 [[SUB249]], [[MUL300]]5154// CHECK2-NEXT: [[TMP160:%.*]] = load i64, ptr [[DOTOMP_IV]], align 85155// CHECK2-NEXT: [[TMP161:%.*]] = load i64, ptr [[DOTOMP_IV]], align 85156// CHECK2-NEXT: [[TMP162:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 45157// CHECK2-NEXT: [[TMP163:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 45158// CHECK2-NEXT: [[SUB302:%.*]] = sub i32 [[TMP162]], [[TMP163]]5159// CHECK2-NEXT: [[SUB303:%.*]] = sub i32 [[SUB302]], 15160// CHECK2-NEXT: [[TMP164:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 45161// CHECK2-NEXT: [[ADD304:%.*]] = add i32 [[SUB303]], [[TMP164]]5162// CHECK2-NEXT: [[TMP165:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 45163// CHECK2-NEXT: [[DIV305:%.*]] = udiv i32 [[ADD304]], [[TMP165]]5164// CHECK2-NEXT: [[MUL306:%.*]] = mul i32 1, [[DIV305]]5165// CHECK2-NEXT: [[TMP166:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 45166// CHECK2-NEXT: [[SUB307:%.*]] = sub i32 [[TMP166]], -635167// CHECK2-NEXT: [[DIV308:%.*]] = udiv i32 [[SUB307]], 645168// CHECK2-NEXT: [[MUL309:%.*]] = mul i32 [[MUL306]], [[DIV308]]5169// CHECK2-NEXT: [[TMP167:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 45170// CHECK2-NEXT: [[TMP168:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 45171// CHECK2-NEXT: [[SUB310:%.*]] = sub i32 [[TMP167]], [[TMP168]]5172// CHECK2-NEXT: [[SUB311:%.*]] = sub i32 [[SUB310]], 15173// CHECK2-NEXT: [[ADD312:%.*]] = add i32 [[SUB311]], 15174// CHECK2-NEXT: [[DIV313:%.*]] = udiv i32 [[ADD312]], 15175// CHECK2-NEXT: [[MUL314:%.*]] = mul i32 [[MUL309]], [[DIV313]]5176// CHECK2-NEXT: [[CONV315:%.*]] = zext i32 [[MUL314]] to i645177// CHECK2-NEXT: [[DIV316:%.*]] = sdiv i64 [[TMP161]], [[CONV315]]5178// CHECK2-NEXT: [[TMP169:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 45179// CHECK2-NEXT: [[TMP170:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 45180// CHECK2-NEXT: [[SUB317:%.*]] = sub i32 [[TMP169]], [[TMP170]]5181// CHECK2-NEXT: [[SUB318:%.*]] = sub i32 [[SUB317]], 15182// CHECK2-NEXT: [[TMP171:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 45183// CHECK2-NEXT: [[ADD319:%.*]] = add i32 [[SUB318]], [[TMP171]]5184// CHECK2-NEXT: [[TMP172:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 45185// CHECK2-NEXT: [[DIV320:%.*]] = udiv i32 [[ADD319]], [[TMP172]]5186// CHECK2-NEXT: [[MUL321:%.*]] = mul i32 1, [[DIV320]]5187// CHECK2-NEXT: [[TMP173:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 45188// CHECK2-NEXT: [[SUB322:%.*]] = sub i32 [[TMP173]], -635189// CHECK2-NEXT: [[DIV323:%.*]] = udiv i32 [[SUB322]], 645190// CHECK2-NEXT: [[MUL324:%.*]] = mul i32 [[MUL321]], [[DIV323]]5191// CHECK2-NEXT: [[TMP174:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 45192// CHECK2-NEXT: [[TMP175:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 45193// CHECK2-NEXT: [[SUB325:%.*]] = sub i32 [[TMP174]], [[TMP175]]5194// CHECK2-NEXT: [[SUB326:%.*]] = sub i32 [[SUB325]], 15195// CHECK2-NEXT: [[ADD327:%.*]] = add i32 [[SUB326]], 15196// CHECK2-NEXT: [[DIV328:%.*]] = udiv i32 [[ADD327]], 15197// CHECK2-NEXT: [[MUL329:%.*]] = mul i32 [[MUL324]], [[DIV328]]5198// CHECK2-NEXT: [[CONV330:%.*]] = zext i32 [[MUL329]] to i645199// CHECK2-NEXT: [[MUL331:%.*]] = mul nsw i64 [[DIV316]], [[CONV330]]5200// CHECK2-NEXT: [[SUB332:%.*]] = sub nsw i64 [[TMP160]], [[MUL331]]5201// CHECK2-NEXT: [[TMP176:%.*]] = load i64, ptr [[DOTOMP_IV]], align 85202// CHECK2-NEXT: [[TMP177:%.*]] = load i64, ptr [[DOTOMP_IV]], align 85203// CHECK2-NEXT: [[TMP178:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 45204// CHECK2-NEXT: [[TMP179:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 45205// CHECK2-NEXT: [[SUB333:%.*]] = sub i32 [[TMP178]], [[TMP179]]5206// CHECK2-NEXT: [[SUB334:%.*]] = sub i32 [[SUB333]], 15207// CHECK2-NEXT: [[TMP180:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 45208// CHECK2-NEXT: [[ADD335:%.*]] = add i32 [[SUB334]], [[TMP180]]5209// CHECK2-NEXT: [[TMP181:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 45210// CHECK2-NEXT: [[DIV336:%.*]] = udiv i32 [[ADD335]], [[TMP181]]5211// CHECK2-NEXT: [[MUL337:%.*]] = mul i32 1, [[DIV336]]5212// CHECK2-NEXT: [[TMP182:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 45213// CHECK2-NEXT: [[SUB338:%.*]] = sub i32 [[TMP182]], -635214// CHECK2-NEXT: [[DIV339:%.*]] = udiv i32 [[SUB338]], 645215// CHECK2-NEXT: [[MUL340:%.*]] = mul i32 [[MUL337]], [[DIV339]]5216// CHECK2-NEXT: [[TMP183:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 45217// CHECK2-NEXT: [[TMP184:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 45218// CHECK2-NEXT: [[SUB341:%.*]] = sub i32 [[TMP183]], [[TMP184]]5219// CHECK2-NEXT: [[SUB342:%.*]] = sub i32 [[SUB341]], 15220// CHECK2-NEXT: [[ADD343:%.*]] = add i32 [[SUB342]], 15221// CHECK2-NEXT: [[DIV344:%.*]] = udiv i32 [[ADD343]], 15222// CHECK2-NEXT: [[MUL345:%.*]] = mul i32 [[MUL340]], [[DIV344]]5223// CHECK2-NEXT: [[CONV346:%.*]] = zext i32 [[MUL345]] to i645224// CHECK2-NEXT: [[DIV347:%.*]] = sdiv i64 [[TMP177]], [[CONV346]]5225// CHECK2-NEXT: [[TMP185:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 45226// CHECK2-NEXT: [[TMP186:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 45227// CHECK2-NEXT: [[SUB348:%.*]] = sub i32 [[TMP185]], [[TMP186]]5228// CHECK2-NEXT: [[SUB349:%.*]] = sub i32 [[SUB348]], 15229// CHECK2-NEXT: [[TMP187:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 45230// CHECK2-NEXT: [[ADD350:%.*]] = add i32 [[SUB349]], [[TMP187]]5231// CHECK2-NEXT: [[TMP188:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 45232// CHECK2-NEXT: [[DIV351:%.*]] = udiv i32 [[ADD350]], [[TMP188]]5233// CHECK2-NEXT: [[MUL352:%.*]] = mul i32 1, [[DIV351]]5234// CHECK2-NEXT: [[TMP189:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 45235// CHECK2-NEXT: [[SUB353:%.*]] = sub i32 [[TMP189]], -635236// CHECK2-NEXT: [[DIV354:%.*]] = udiv i32 [[SUB353]], 645237// CHECK2-NEXT: [[MUL355:%.*]] = mul i32 [[MUL352]], [[DIV354]]5238// CHECK2-NEXT: [[TMP190:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 45239// CHECK2-NEXT: [[TMP191:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 45240// CHECK2-NEXT: [[SUB356:%.*]] = sub i32 [[TMP190]], [[TMP191]]5241// CHECK2-NEXT: [[SUB357:%.*]] = sub i32 [[SUB356]], 15242// CHECK2-NEXT: [[ADD358:%.*]] = add i32 [[SUB357]], 15243// CHECK2-NEXT: [[DIV359:%.*]] = udiv i32 [[ADD358]], 15244// CHECK2-NEXT: [[MUL360:%.*]] = mul i32 [[MUL355]], [[DIV359]]5245// CHECK2-NEXT: [[CONV361:%.*]] = zext i32 [[MUL360]] to i645246// CHECK2-NEXT: [[MUL362:%.*]] = mul nsw i64 [[DIV347]], [[CONV361]]5247// CHECK2-NEXT: [[SUB363:%.*]] = sub nsw i64 [[TMP176]], [[MUL362]]5248// CHECK2-NEXT: [[TMP192:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 45249// CHECK2-NEXT: [[SUB364:%.*]] = sub i32 [[TMP192]], -635250// CHECK2-NEXT: [[DIV365:%.*]] = udiv i32 [[SUB364]], 645251// CHECK2-NEXT: [[MUL366:%.*]] = mul i32 1, [[DIV365]]5252// CHECK2-NEXT: [[TMP193:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 45253// CHECK2-NEXT: [[TMP194:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 45254// CHECK2-NEXT: [[SUB367:%.*]] = sub i32 [[TMP193]], [[TMP194]]5255// CHECK2-NEXT: [[SUB368:%.*]] = sub i32 [[SUB367]], 15256// CHECK2-NEXT: [[ADD369:%.*]] = add i32 [[SUB368]], 15257// CHECK2-NEXT: [[DIV370:%.*]] = udiv i32 [[ADD369]], 15258// CHECK2-NEXT: [[MUL371:%.*]] = mul i32 [[MUL366]], [[DIV370]]5259// CHECK2-NEXT: [[CONV372:%.*]] = zext i32 [[MUL371]] to i645260// CHECK2-NEXT: [[DIV373:%.*]] = sdiv i64 [[SUB363]], [[CONV372]]5261// CHECK2-NEXT: [[TMP195:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 45262// CHECK2-NEXT: [[SUB374:%.*]] = sub i32 [[TMP195]], -635263// CHECK2-NEXT: [[DIV375:%.*]] = udiv i32 [[SUB374]], 645264// CHECK2-NEXT: [[MUL376:%.*]] = mul i32 1, [[DIV375]]5265// CHECK2-NEXT: [[TMP196:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 45266// CHECK2-NEXT: [[TMP197:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 45267// CHECK2-NEXT: [[SUB377:%.*]] = sub i32 [[TMP196]], [[TMP197]]5268// CHECK2-NEXT: [[SUB378:%.*]] = sub i32 [[SUB377]], 15269// CHECK2-NEXT: [[ADD379:%.*]] = add i32 [[SUB378]], 15270// CHECK2-NEXT: [[DIV380:%.*]] = udiv i32 [[ADD379]], 15271// CHECK2-NEXT: [[MUL381:%.*]] = mul i32 [[MUL376]], [[DIV380]]5272// CHECK2-NEXT: [[CONV382:%.*]] = zext i32 [[MUL381]] to i645273// CHECK2-NEXT: [[MUL383:%.*]] = mul nsw i64 [[DIV373]], [[CONV382]]5274// CHECK2-NEXT: [[SUB384:%.*]] = sub nsw i64 [[SUB332]], [[MUL383]]5275// CHECK2-NEXT: [[TMP198:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 45276// CHECK2-NEXT: [[TMP199:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 45277// CHECK2-NEXT: [[SUB385:%.*]] = sub i32 [[TMP198]], [[TMP199]]5278// CHECK2-NEXT: [[SUB386:%.*]] = sub i32 [[SUB385]], 15279// CHECK2-NEXT: [[ADD387:%.*]] = add i32 [[SUB386]], 15280// CHECK2-NEXT: [[DIV388:%.*]] = udiv i32 [[ADD387]], 15281// CHECK2-NEXT: [[MUL389:%.*]] = mul i32 1, [[DIV388]]5282// CHECK2-NEXT: [[CONV390:%.*]] = zext i32 [[MUL389]] to i645283// CHECK2-NEXT: [[DIV391:%.*]] = sdiv i64 [[SUB384]], [[CONV390]]5284// CHECK2-NEXT: [[TMP200:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 45285// CHECK2-NEXT: [[TMP201:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 45286// CHECK2-NEXT: [[SUB392:%.*]] = sub i32 [[TMP200]], [[TMP201]]5287// CHECK2-NEXT: [[SUB393:%.*]] = sub i32 [[SUB392]], 15288// CHECK2-NEXT: [[ADD394:%.*]] = add i32 [[SUB393]], 15289// CHECK2-NEXT: [[DIV395:%.*]] = udiv i32 [[ADD394]], 15290// CHECK2-NEXT: [[MUL396:%.*]] = mul i32 1, [[DIV395]]5291// CHECK2-NEXT: [[CONV397:%.*]] = zext i32 [[MUL396]] to i645292// CHECK2-NEXT: [[MUL398:%.*]] = mul nsw i64 [[DIV391]], [[CONV397]]5293// CHECK2-NEXT: [[SUB399:%.*]] = sub nsw i64 [[SUB301]], [[MUL398]]5294// CHECK2-NEXT: [[MUL400:%.*]] = mul nsw i64 [[SUB399]], 15295// CHECK2-NEXT: [[ADD401:%.*]] = add nsw i64 [[CONV218]], [[MUL400]]5296// CHECK2-NEXT: [[CONV402:%.*]] = trunc i64 [[ADD401]] to i325297// CHECK2-NEXT: store i32 [[CONV402]], ptr [[DOTTILE_0_IV_K52]], align 45298// CHECK2-NEXT: [[TMP202:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_8]], align 45299// CHECK2-NEXT: [[TMP203:%.*]] = load i32, ptr [[DOTTILE_0_IV_K52]], align 45300// CHECK2-NEXT: [[TMP204:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 45301// CHECK2-NEXT: [[MUL403:%.*]] = mul i32 [[TMP203]], [[TMP204]]5302// CHECK2-NEXT: [[ADD404:%.*]] = add i32 [[TMP202]], [[MUL403]]5303// CHECK2-NEXT: store i32 [[ADD404]], ptr [[K]], align 45304// CHECK2-NEXT: [[TMP205:%.*]] = load i32, ptr [[I49]], align 45305// CHECK2-NEXT: [[TMP206:%.*]] = load i32, ptr [[J50]], align 45306// CHECK2-NEXT: [[TMP207:%.*]] = load i32, ptr [[K]], align 45307// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP205]], i32 noundef [[TMP206]], i32 noundef [[TMP207]])5308// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]5309// CHECK2: omp.body.continue:5310// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]5311// CHECK2: omp.inner.for.inc:5312// CHECK2-NEXT: [[TMP208:%.*]] = load i64, ptr [[DOTOMP_IV]], align 85313// CHECK2-NEXT: [[ADD405:%.*]] = add nsw i64 [[TMP208]], 15314// CHECK2-NEXT: store i64 [[ADD405]], ptr [[DOTOMP_IV]], align 85315// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]5316// CHECK2: omp.inner.for.end:5317// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]5318// CHECK2: omp.loop.exit:5319// CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]])5320// CHECK2-NEXT: br label [[OMP_PRECOND_END]]5321// CHECK2: omp.precond.end:5322// CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]])5323// CHECK2-NEXT: ret void5324 5325