159 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_ size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _2// RUN: %clang_cc1 -fopenmp-enable-irbuilder -verify -fopenmp -fopenmp-version=45 -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s3// expected-no-diagnostics4 5#ifndef HEADER6#define HEADER7 8extern "C" void workshareloop_unsigned(float *a, float *b, float *c, float *d) {9#pragma omp for10 for (unsigned i = 33; i < 32000000; i += 7) {11 a[i] = b[i] * c[i] * d[i];12 }13}14 15#endif // HEADER16// CHECK-LABEL: define {{[^@]+}}@workshareloop_unsigned17// CHECK-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] {18// CHECK-NEXT: entry:19// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 820// CHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 821// CHECK-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 822// CHECK-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 823// CHECK-NEXT: [[I:%.*]] = alloca i32, align 424// CHECK-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 825// CHECK-NEXT: [[AGG_CAPTURED1:%.*]] = alloca [[STRUCT_ANON_0:%.*]], align 426// CHECK-NEXT: [[DOTCOUNT_ADDR:%.*]] = alloca i32, align 427// CHECK-NEXT: [[P_LASTITER:%.*]] = alloca i32, align 428// CHECK-NEXT: [[P_LOWERBOUND:%.*]] = alloca i32, align 429// CHECK-NEXT: [[P_UPPERBOUND:%.*]] = alloca i32, align 430// CHECK-NEXT: [[P_STRIDE:%.*]] = alloca i32, align 431// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 832// CHECK-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 833// CHECK-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 834// CHECK-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 835// CHECK-NEXT: store i32 33, ptr [[I]], align 436// CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 037// CHECK-NEXT: store ptr [[I]], ptr [[TMP0]], align 838// CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_0]], ptr [[AGG_CAPTURED1]], i32 0, i32 039// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[I]], align 440// CHECK-NEXT: store i32 [[TMP2]], ptr [[TMP1]], align 441// CHECK-NEXT: call void @__captured_stmt(ptr [[DOTCOUNT_ADDR]], ptr [[AGG_CAPTURED]])42// CHECK-NEXT: [[DOTCOUNT:%.*]] = load i32, ptr [[DOTCOUNT_ADDR]], align 443// CHECK-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]44// CHECK: omp_loop.preheader:45// CHECK-NEXT: store i32 0, ptr [[P_LOWERBOUND]], align 446// CHECK-NEXT: [[TMP3:%.*]] = sub i32 [[DOTCOUNT]], 147// CHECK-NEXT: store i32 [[TMP3]], ptr [[P_UPPERBOUND]], align 448// CHECK-NEXT: store i32 1, ptr [[P_STRIDE]], align 449// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])50// CHECK-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 34, ptr [[P_LASTITER]], ptr [[P_LOWERBOUND]], ptr [[P_UPPERBOUND]], ptr [[P_STRIDE]], i32 1, i32 0)51// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[P_LOWERBOUND]], align 452// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[P_UPPERBOUND]], align 453// CHECK-NEXT: [[TMP6:%.*]] = sub i32 [[TMP5]], [[TMP4]]54// CHECK-NEXT: [[TMP7:%.*]] = add i32 [[TMP6]], 155// CHECK-NEXT: br label [[OMP_LOOP_HEADER:%.*]]56// CHECK: omp_loop.header:57// CHECK-NEXT: [[OMP_LOOP_IV:%.*]] = phi i32 [ 0, [[OMP_LOOP_PREHEADER]] ], [ [[OMP_LOOP_NEXT:%.*]], [[OMP_LOOP_INC:%.*]] ]58// CHECK-NEXT: br label [[OMP_LOOP_COND:%.*]]59// CHECK: omp_loop.cond:60// CHECK-NEXT: [[OMP_LOOP_CMP:%.*]] = icmp ult i32 [[OMP_LOOP_IV]], [[TMP7]]61// CHECK-NEXT: br i1 [[OMP_LOOP_CMP]], label [[OMP_LOOP_BODY:%.*]], label [[OMP_LOOP_EXIT:%.*]]62// CHECK: omp_loop.body:63// CHECK-NEXT: [[TMP8:%.*]] = add i32 [[OMP_LOOP_IV]], [[TMP4]]64// CHECK-NEXT: call void @__captured_stmt.1(ptr [[I]], i32 [[TMP8]], ptr [[AGG_CAPTURED1]])65// CHECK-NEXT: [[TMP9:%.*]] = load ptr, ptr [[B_ADDR]], align 866// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 467// CHECK-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP10]] to i6468// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP9]], i64 [[IDXPROM]]69// CHECK-NEXT: [[TMP11:%.*]] = load float, ptr [[ARRAYIDX]], align 470// CHECK-NEXT: [[TMP12:%.*]] = load ptr, ptr [[C_ADDR]], align 871// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 472// CHECK-NEXT: [[IDXPROM2:%.*]] = zext i32 [[TMP13]] to i6473// CHECK-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds nuw float, ptr [[TMP12]], i64 [[IDXPROM2]]74// CHECK-NEXT: [[TMP14:%.*]] = load float, ptr [[ARRAYIDX3]], align 475// CHECK-NEXT: [[MUL:%.*]] = fmul float [[TMP11]], [[TMP14]]76// CHECK-NEXT: [[TMP15:%.*]] = load ptr, ptr [[D_ADDR]], align 877// CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 478// CHECK-NEXT: [[IDXPROM4:%.*]] = zext i32 [[TMP16]] to i6479// CHECK-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds nuw float, ptr [[TMP15]], i64 [[IDXPROM4]]80// CHECK-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX5]], align 481// CHECK-NEXT: [[MUL6:%.*]] = fmul float [[MUL]], [[TMP17]]82// CHECK-NEXT: [[TMP18:%.*]] = load ptr, ptr [[A_ADDR]], align 883// CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 484// CHECK-NEXT: [[IDXPROM7:%.*]] = zext i32 [[TMP19]] to i6485// CHECK-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds nuw float, ptr [[TMP18]], i64 [[IDXPROM7]]86// CHECK-NEXT: store float [[MUL6]], ptr [[ARRAYIDX8]], align 487// CHECK-NEXT: br label [[OMP_LOOP_INC]]88// CHECK: omp_loop.inc:89// CHECK-NEXT: [[OMP_LOOP_NEXT]] = add nuw i32 [[OMP_LOOP_IV]], 190// CHECK-NEXT: br label [[OMP_LOOP_HEADER]]91// CHECK: omp_loop.exit:92// CHECK-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]])93// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM9:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])94// CHECK-NEXT: call void @__kmpc_barrier(ptr @[[GLOB2:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM9]])95// CHECK-NEXT: br label [[OMP_LOOP_AFTER:%.*]]96// CHECK: omp_loop.after:97// CHECK-NEXT: ret void98//99//100// CHECK-LABEL: define {{[^@]+}}@__captured_stmt101// CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[DISTANCE:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR1:[0-9]+]] {102// CHECK-NEXT: entry:103// CHECK-NEXT: [[DISTANCE_ADDR:%.*]] = alloca ptr, align 8104// CHECK-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8105// CHECK-NEXT: [[DOTSTART:%.*]] = alloca i32, align 4106// CHECK-NEXT: [[DOTSTOP:%.*]] = alloca i32, align 4107// CHECK-NEXT: [[DOTSTEP:%.*]] = alloca i32, align 4108// CHECK-NEXT: store ptr [[DISTANCE]], ptr [[DISTANCE_ADDR]], align 8109// CHECK-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8110// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8111// CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP0]], i32 0, i32 0112// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8113// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4114// CHECK-NEXT: store i32 [[TMP3]], ptr [[DOTSTART]], align 4115// CHECK-NEXT: store i32 32000000, ptr [[DOTSTOP]], align 4116// CHECK-NEXT: store i32 7, ptr [[DOTSTEP]], align 4117// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTSTART]], align 4118// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTSTOP]], align 4119// CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP4]], [[TMP5]]120// CHECK-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]121// CHECK: cond.true:122// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTSTOP]], align 4123// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTSTART]], align 4124// CHECK-NEXT: [[SUB:%.*]] = sub i32 [[TMP6]], [[TMP7]]125// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTSTEP]], align 4126// CHECK-NEXT: [[SUB1:%.*]] = sub i32 [[TMP8]], 1127// CHECK-NEXT: [[ADD:%.*]] = add i32 [[SUB]], [[SUB1]]128// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTSTEP]], align 4129// CHECK-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], [[TMP9]]130// CHECK-NEXT: br label [[COND_END:%.*]]131// CHECK: cond.false:132// CHECK-NEXT: br label [[COND_END]]133// CHECK: cond.end:134// CHECK-NEXT: [[COND:%.*]] = phi i32 [ [[DIV]], [[COND_TRUE]] ], [ 0, [[COND_FALSE]] ]135// CHECK-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DISTANCE_ADDR]], align 8136// CHECK-NEXT: store i32 [[COND]], ptr [[TMP10]], align 4137// CHECK-NEXT: ret void138//139//140// CHECK-LABEL: define {{[^@]+}}@__captured_stmt.1141// CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[LOOPVAR:%.*]], i32 noundef [[LOGICAL:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR1]] {142// CHECK-NEXT: entry:143// CHECK-NEXT: [[LOOPVAR_ADDR:%.*]] = alloca ptr, align 8144// CHECK-NEXT: [[LOGICAL_ADDR:%.*]] = alloca i32, align 4145// CHECK-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8146// CHECK-NEXT: store ptr [[LOOPVAR]], ptr [[LOOPVAR_ADDR]], align 8147// CHECK-NEXT: store i32 [[LOGICAL]], ptr [[LOGICAL_ADDR]], align 4148// CHECK-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8149// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8150// CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0151// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4152// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[LOGICAL_ADDR]], align 4153// CHECK-NEXT: [[MUL:%.*]] = mul i32 7, [[TMP3]]154// CHECK-NEXT: [[ADD:%.*]] = add i32 [[TMP2]], [[MUL]]155// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[LOOPVAR_ADDR]], align 8156// CHECK-NEXT: store i32 [[ADD]], ptr [[TMP4]], align 4157// CHECK-NEXT: ret void158//159