231 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_ size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _2// RUN: %clang_cc1 -fopenmp-enable-irbuilder -verify -fopenmp -x c -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s3// expected-no-diagnostics4 5// REQUIRES: x86-registered-target6 7#ifndef HEADER8#define HEADER9 10double sind(double);11 12 13void unroll_partial_heuristic_runtime_for(int n, float *a, float *b, float *c, float *d, float *e, float offset) {14#pragma omp for15#pragma omp unroll partial16 for (int i = 0; i < n; i++) {17 a[i] += sind(b[i]) * c[i] * d[i] * e[i] + offset;18 }19}20 21#endif // HEADER22 23 24 25 26 27// CHECK-LABEL: define {{[^@]+}}@unroll_partial_heuristic_runtime_for28// CHECK-SAME: (i32 noundef [[N:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]], ptr noundef [[E:%.*]], float noundef [[OFFSET:%.*]]) #[[ATTR0:[0-9]+]] {29// CHECK-NEXT: entry:30// CHECK-NEXT: [[N_ADDR:%.*]] = alloca i32, align 431// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 832// CHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 833// CHECK-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 834// CHECK-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 835// CHECK-NEXT: [[E_ADDR:%.*]] = alloca ptr, align 836// CHECK-NEXT: [[OFFSET_ADDR:%.*]] = alloca float, align 437// CHECK-NEXT: [[I:%.*]] = alloca i32, align 438// CHECK-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 839// CHECK-NEXT: [[AGG_CAPTURED1:%.*]] = alloca [[STRUCT_ANON_0:%.*]], align 440// CHECK-NEXT: [[DOTCOUNT_ADDR:%.*]] = alloca i32, align 441// CHECK-NEXT: [[P_LASTITER:%.*]] = alloca i32, align 442// CHECK-NEXT: [[P_LOWERBOUND:%.*]] = alloca i32, align 443// CHECK-NEXT: [[P_UPPERBOUND:%.*]] = alloca i32, align 444// CHECK-NEXT: [[P_STRIDE:%.*]] = alloca i32, align 445// CHECK-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 446// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 847// CHECK-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 848// CHECK-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 849// CHECK-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 850// CHECK-NEXT: store ptr [[E]], ptr [[E_ADDR]], align 851// CHECK-NEXT: store float [[OFFSET]], ptr [[OFFSET_ADDR]], align 452// CHECK-NEXT: store i32 0, ptr [[I]], align 453// CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 054// CHECK-NEXT: store ptr [[I]], ptr [[TMP0]], align 855// CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 156// CHECK-NEXT: store ptr [[N_ADDR]], ptr [[TMP1]], align 857// CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_0]], ptr [[AGG_CAPTURED1]], i32 0, i32 058// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[I]], align 459// CHECK-NEXT: store i32 [[TMP3]], ptr [[TMP2]], align 460// CHECK-NEXT: call void @__captured_stmt(ptr [[DOTCOUNT_ADDR]], ptr [[AGG_CAPTURED]])61// CHECK-NEXT: [[DOTCOUNT:%.*]] = load i32, ptr [[DOTCOUNT_ADDR]], align 462// CHECK-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]63// CHECK: omp_loop.preheader:64// CHECK-NEXT: [[TMP4:%.*]] = udiv i32 [[DOTCOUNT]], 465// CHECK-NEXT: [[TMP5:%.*]] = urem i32 [[DOTCOUNT]], 466// CHECK-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 067// CHECK-NEXT: [[TMP7:%.*]] = zext i1 [[TMP6]] to i3268// CHECK-NEXT: [[OMP_FLOOR0_TRIPCOUNT:%.*]] = add nuw i32 [[TMP4]], [[TMP7]]69// CHECK-NEXT: br label [[OMP_FLOOR0_PREHEADER:%.*]]70// CHECK: omp_floor0.preheader:71// CHECK-NEXT: store i32 0, ptr [[P_LOWERBOUND]], align 472// CHECK-NEXT: [[TMP8:%.*]] = sub i32 [[OMP_FLOOR0_TRIPCOUNT]], 173// CHECK-NEXT: store i32 [[TMP8]], ptr [[P_UPPERBOUND]], align 474// CHECK-NEXT: store i32 1, ptr [[P_STRIDE]], align 475// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])76// CHECK-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 34, ptr [[P_LASTITER]], ptr [[P_LOWERBOUND]], ptr [[P_UPPERBOUND]], ptr [[P_STRIDE]], i32 1, i32 0)77// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[P_LOWERBOUND]], align 478// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[P_UPPERBOUND]], align 479// CHECK-NEXT: [[TMP11:%.*]] = sub i32 [[TMP10]], [[TMP9]]80// CHECK-NEXT: [[TMP12:%.*]] = add i32 [[TMP11]], 181// CHECK-NEXT: br label [[OMP_FLOOR0_HEADER:%.*]]82// CHECK: omp_floor0.header:83// CHECK-NEXT: [[OMP_FLOOR0_IV:%.*]] = phi i32 [ 0, [[OMP_FLOOR0_PREHEADER]] ], [ [[OMP_FLOOR0_NEXT:%.*]], [[OMP_FLOOR0_INC:%.*]] ]84// CHECK-NEXT: br label [[OMP_FLOOR0_COND:%.*]]85// CHECK: omp_floor0.cond:86// CHECK-NEXT: [[OMP_FLOOR0_CMP:%.*]] = icmp ult i32 [[OMP_FLOOR0_IV]], [[TMP12]]87// CHECK-NEXT: br i1 [[OMP_FLOOR0_CMP]], label [[OMP_FLOOR0_BODY:%.*]], label [[OMP_FLOOR0_EXIT:%.*]]88// CHECK: omp_floor0.body:89// CHECK-NEXT: [[TMP13:%.*]] = add i32 [[OMP_FLOOR0_IV]], [[TMP9]]90// CHECK-NEXT: [[TMP14:%.*]] = icmp eq i32 [[TMP13]], [[TMP4]]91// CHECK-NEXT: [[TMP15:%.*]] = select i1 [[TMP14]], i32 [[TMP5]], i32 492// CHECK-NEXT: br label [[OMP_TILE0_PREHEADER:%.*]]93// CHECK: omp_tile0.preheader:94// CHECK-NEXT: br label [[OMP_TILE0_HEADER:%.*]]95// CHECK: omp_tile0.header:96// CHECK-NEXT: [[OMP_TILE0_IV:%.*]] = phi i32 [ 0, [[OMP_TILE0_PREHEADER]] ], [ [[OMP_TILE0_NEXT:%.*]], [[OMP_TILE0_INC:%.*]] ]97// CHECK-NEXT: br label [[OMP_TILE0_COND:%.*]]98// CHECK: omp_tile0.cond:99// CHECK-NEXT: [[OMP_TILE0_CMP:%.*]] = icmp ult i32 [[OMP_TILE0_IV]], [[TMP15]]100// CHECK-NEXT: br i1 [[OMP_TILE0_CMP]], label [[OMP_TILE0_BODY:%.*]], label [[OMP_TILE0_EXIT:%.*]]101// CHECK: omp_tile0.body:102// CHECK-NEXT: [[TMP16:%.*]] = mul nuw i32 4, [[TMP13]]103// CHECK-NEXT: [[TMP17:%.*]] = add nuw i32 [[TMP16]], [[OMP_TILE0_IV]]104// CHECK-NEXT: br label [[OMP_LOOP_BODY:%.*]]105// CHECK: omp_loop.body:106// CHECK-NEXT: call void @__captured_stmt.1(ptr [[I]], i32 [[TMP17]], ptr [[AGG_CAPTURED1]])107// CHECK-NEXT: [[TMP18:%.*]] = load ptr, ptr [[B_ADDR]], align 8108// CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4109// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64110// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[IDXPROM]]111// CHECK-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4112// CHECK-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double113// CHECK-NEXT: [[CALL:%.*]] = call double @sind(double noundef [[CONV]])114// CHECK-NEXT: [[TMP21:%.*]] = load ptr, ptr [[C_ADDR]], align 8115// CHECK-NEXT: [[TMP22:%.*]] = load i32, ptr [[I]], align 4116// CHECK-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP22]] to i64117// CHECK-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i64 [[IDXPROM2]]118// CHECK-NEXT: [[TMP23:%.*]] = load float, ptr [[ARRAYIDX3]], align 4119// CHECK-NEXT: [[CONV4:%.*]] = fpext float [[TMP23]] to double120// CHECK-NEXT: [[MUL:%.*]] = fmul double [[CALL]], [[CONV4]]121// CHECK-NEXT: [[TMP24:%.*]] = load ptr, ptr [[D_ADDR]], align 8122// CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[I]], align 4123// CHECK-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP25]] to i64124// CHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP24]], i64 [[IDXPROM5]]125// CHECK-NEXT: [[TMP26:%.*]] = load float, ptr [[ARRAYIDX6]], align 4126// CHECK-NEXT: [[CONV7:%.*]] = fpext float [[TMP26]] to double127// CHECK-NEXT: [[MUL8:%.*]] = fmul double [[MUL]], [[CONV7]]128// CHECK-NEXT: [[TMP27:%.*]] = load ptr, ptr [[E_ADDR]], align 8129// CHECK-NEXT: [[TMP28:%.*]] = load i32, ptr [[I]], align 4130// CHECK-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP28]] to i64131// CHECK-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP27]], i64 [[IDXPROM9]]132// CHECK-NEXT: [[TMP29:%.*]] = load float, ptr [[ARRAYIDX10]], align 4133// CHECK-NEXT: [[CONV11:%.*]] = fpext float [[TMP29]] to double134// CHECK-NEXT: [[MUL12:%.*]] = fmul double [[MUL8]], [[CONV11]]135// CHECK-NEXT: [[TMP30:%.*]] = load float, ptr [[OFFSET_ADDR]], align 4136// CHECK-NEXT: [[CONV13:%.*]] = fpext float [[TMP30]] to double137// CHECK-NEXT: [[ADD:%.*]] = fadd double [[MUL12]], [[CONV13]]138// CHECK-NEXT: [[TMP31:%.*]] = load ptr, ptr [[A_ADDR]], align 8139// CHECK-NEXT: [[TMP32:%.*]] = load i32, ptr [[I]], align 4140// CHECK-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP32]] to i64141// CHECK-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds float, ptr [[TMP31]], i64 [[IDXPROM14]]142// CHECK-NEXT: [[TMP33:%.*]] = load float, ptr [[ARRAYIDX15]], align 4143// CHECK-NEXT: [[CONV16:%.*]] = fpext float [[TMP33]] to double144// CHECK-NEXT: [[ADD17:%.*]] = fadd double [[CONV16]], [[ADD]]145// CHECK-NEXT: [[CONV18:%.*]] = fptrunc double [[ADD17]] to float146// CHECK-NEXT: store float [[CONV18]], ptr [[ARRAYIDX15]], align 4147// CHECK-NEXT: br label [[OMP_TILE0_INC]]148// CHECK: omp_tile0.inc:149// CHECK-NEXT: [[OMP_TILE0_NEXT]] = add nuw i32 [[OMP_TILE0_IV]], 1150// CHECK-NEXT: br label [[OMP_TILE0_HEADER]], !llvm.loop [[LOOP3:![0-9]+]]151// CHECK: omp_tile0.exit:152// CHECK-NEXT: br label [[OMP_TILE0_AFTER:%.*]]153// CHECK: omp_tile0.after:154// CHECK-NEXT: br label [[OMP_FLOOR0_INC]]155// CHECK: omp_floor0.inc:156// CHECK-NEXT: [[OMP_FLOOR0_NEXT]] = add nuw i32 [[OMP_FLOOR0_IV]], 1157// CHECK-NEXT: br label [[OMP_FLOOR0_HEADER]]158// CHECK: omp_floor0.exit:159// CHECK-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]])160// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM19:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])161// CHECK-NEXT: call void @__kmpc_barrier(ptr @[[GLOB2:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM19]])162// CHECK-NEXT: br label [[OMP_FLOOR0_AFTER:%.*]]163// CHECK: omp_floor0.after:164// CHECK-NEXT: br label [[OMP_LOOP_AFTER:%.*]]165// CHECK: omp_loop.after:166// CHECK-NEXT: ret void167//168//169// CHECK-LABEL: define {{[^@]+}}@__captured_stmt170// CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[DISTANCE:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {171// CHECK-NEXT: entry:172// CHECK-NEXT: [[DISTANCE_ADDR:%.*]] = alloca ptr, align 8173// CHECK-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8174// CHECK-NEXT: [[DOTSTART:%.*]] = alloca i32, align 4175// CHECK-NEXT: [[DOTSTOP:%.*]] = alloca i32, align 4176// CHECK-NEXT: [[DOTSTEP:%.*]] = alloca i32, align 4177// CHECK-NEXT: store ptr [[DISTANCE]], ptr [[DISTANCE_ADDR]], align 8178// CHECK-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8179// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8180// CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP0]], i32 0, i32 0181// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8182// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4183// CHECK-NEXT: store i32 [[TMP3]], ptr [[DOTSTART]], align 4184// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[TMP0]], i32 0, i32 1185// CHECK-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8186// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4187// CHECK-NEXT: store i32 [[TMP6]], ptr [[DOTSTOP]], align 4188// CHECK-NEXT: store i32 1, ptr [[DOTSTEP]], align 4189// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTSTART]], align 4190// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTSTOP]], align 4191// CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]]192// CHECK-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]193// CHECK: cond.true:194// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTSTOP]], align 4195// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTSTART]], align 4196// CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[TMP10]]197// CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTSTEP]], align 4198// CHECK-NEXT: [[SUB1:%.*]] = sub i32 [[TMP11]], 1199// CHECK-NEXT: [[ADD:%.*]] = add i32 [[SUB]], [[SUB1]]200// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTSTEP]], align 4201// CHECK-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], [[TMP12]]202// CHECK-NEXT: br label [[COND_END:%.*]]203// CHECK: cond.false:204// CHECK-NEXT: br label [[COND_END]]205// CHECK: cond.end:206// CHECK-NEXT: [[COND:%.*]] = phi i32 [ [[DIV]], [[COND_TRUE]] ], [ 0, [[COND_FALSE]] ]207// CHECK-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DISTANCE_ADDR]], align 8208// CHECK-NEXT: store i32 [[COND]], ptr [[TMP13]], align 4209// CHECK-NEXT: ret void210//211//212// CHECK-LABEL: define {{[^@]+}}@__captured_stmt.1213// CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[LOOPVAR:%.*]], i32 noundef [[LOGICAL:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {214// CHECK-NEXT: entry:215// CHECK-NEXT: [[LOOPVAR_ADDR:%.*]] = alloca ptr, align 8216// CHECK-NEXT: [[LOGICAL_ADDR:%.*]] = alloca i32, align 4217// CHECK-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8218// CHECK-NEXT: store ptr [[LOOPVAR]], ptr [[LOOPVAR_ADDR]], align 8219// CHECK-NEXT: store i32 [[LOGICAL]], ptr [[LOGICAL_ADDR]], align 4220// CHECK-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8221// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8222// CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0223// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4224// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[LOGICAL_ADDR]], align 4225// CHECK-NEXT: [[MUL:%.*]] = mul i32 1, [[TMP3]]226// CHECK-NEXT: [[ADD:%.*]] = add i32 [[TMP2]], [[MUL]]227// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[LOOPVAR_ADDR]], align 8228// CHECK-NEXT: store i32 [[ADD]], ptr [[TMP4]], align 4229// CHECK-NEXT: ret void230//231