654 lines · cpp
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _2// Test target codegen - host bc file has to be created first.3// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc4// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK45// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc6// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK57// RUN: %clang_cc1 -verify -fopenmp -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK58 9// expected-no-diagnostics10#ifndef HEADER11#define HEADER12 13int a;14 15int foo(int *a);16 17int main(int argc, char **argv) {18 int b[10], c[10], d[10];19#pragma omp target teams map(tofrom:a)20#pragma omp distribute parallel for firstprivate(b) lastprivate(c) if(a)21 for (int i= 0; i < argc; ++i)22 a = foo(&i) + foo(&a) + foo(&b[i]) + foo(&c[i]) + foo(&d[i]);23 return 0;24}25 26#endif27// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l1928// CHECK4-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[ARGC:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[D:%.*]]) #[[ATTR0:[0-9]+]] {29// CHECK4-NEXT: entry:30// CHECK4-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 831// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 832// CHECK4-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 833// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 834// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 835// CHECK4-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 836// CHECK4-NEXT: [[ARGC_CASTED:%.*]] = alloca i64, align 837// CHECK4-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 438// CHECK4-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 439// CHECK4-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 840// CHECK4-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 841// CHECK4-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 842// CHECK4-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 843// CHECK4-NEXT: store i64 [[ARGC]], ptr [[ARGC_ADDR]], align 844// CHECK4-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 845// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 846// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C_ADDR]], align 847// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 848// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 849// CHECK4-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l19_kernel_environment, ptr [[DYN_PTR]])50// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -151// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]52// CHECK4: user_code.entry:53// CHECK4-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])54// CHECK4-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARGC_ADDR]], align 455// CHECK4-NEXT: store i32 [[TMP6]], ptr [[ARGC_CASTED]], align 456// CHECK4-NEXT: [[TMP7:%.*]] = load i64, ptr [[ARGC_CASTED]], align 857// CHECK4-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 458// CHECK4-NEXT: store i32 [[TMP5]], ptr [[DOTTHREADID_TEMP_]], align 459// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l19_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], i64 [[TMP7]], ptr [[TMP3]]) #[[ATTR4:[0-9]+]]60// CHECK4-NEXT: call void @__kmpc_target_deinit()61// CHECK4-NEXT: ret void62// CHECK4: worker.exit:63// CHECK4-NEXT: ret void64//65//66// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l19_omp_outlined67// CHECK4-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[ARGC:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[D:%.*]]) #[[ATTR1:[0-9]+]] {68// CHECK4-NEXT: entry:69// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 870// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 871// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 872// CHECK4-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 873// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 874// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 875// CHECK4-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 876// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 477// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 478// CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 479// CHECK4-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 480// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 481// CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 482// CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 483// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 484// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 485// CHECK4-NEXT: [[B4:%.*]] = alloca [10 x i32], align 486// CHECK4-NEXT: [[I5:%.*]] = alloca i32, align 487// CHECK4-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [7 x ptr], align 888// CHECK4-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 889// CHECK4-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 890// CHECK4-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 891// CHECK4-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 892// CHECK4-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 893// CHECK4-NEXT: store i64 [[ARGC]], ptr [[ARGC_ADDR]], align 894// CHECK4-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 895// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 896// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C_ADDR]], align 897// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 898// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 899// CHECK4-NEXT: [[C1:%.*]] = call align 8 ptr @__kmpc_alloc_shared(i64 40)100// CHECK4-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4101// CHECK4-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4102// CHECK4-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4103// CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0104// CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1105// CHECK4-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1106// CHECK4-NEXT: store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_2]], align 4107// CHECK4-NEXT: store i32 0, ptr [[I]], align 4108// CHECK4-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4109// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]]110// CHECK4-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]111// CHECK4: omp.precond.then:112// CHECK4-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4113// CHECK4-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4114// CHECK4-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_COMB_UB]], align 4115// CHECK4-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4116// CHECK4-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4117// CHECK4-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B4]], ptr align 4 [[TMP0]], i64 40, i1 false)118// CHECK4-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()119// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8120// CHECK4-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4121// CHECK4-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP9]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])122// CHECK4-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4123// CHECK4-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4124// CHECK4-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]]125// CHECK4-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]126// CHECK4: cond.true:127// CHECK4-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4128// CHECK4-NEXT: br label [[COND_END:%.*]]129// CHECK4: cond.false:130// CHECK4-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4131// CHECK4-NEXT: br label [[COND_END]]132// CHECK4: cond.end:133// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]134// CHECK4-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4135// CHECK4-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4136// CHECK4-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV]], align 4137// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]138// CHECK4: omp.inner.for.cond:139// CHECK4-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4140// CHECK4-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4141// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1142// CHECK4-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP15]], [[ADD]]143// CHECK4-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]144// CHECK4: omp.inner.for.body:145// CHECK4-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4146// CHECK4-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64147// CHECK4-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4148// CHECK4-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64149// CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0150// CHECK4-NEXT: [[TMP22:%.*]] = inttoptr i64 [[TMP18]] to ptr151// CHECK4-NEXT: store ptr [[TMP22]], ptr [[TMP21]], align 8152// CHECK4-NEXT: [[TMP23:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1153// CHECK4-NEXT: [[TMP24:%.*]] = inttoptr i64 [[TMP20]] to ptr154// CHECK4-NEXT: store ptr [[TMP24]], ptr [[TMP23]], align 8155// CHECK4-NEXT: [[TMP25:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2156// CHECK4-NEXT: store ptr [[ARGC_ADDR]], ptr [[TMP25]], align 8157// CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3158// CHECK4-NEXT: store ptr [[TMP2]], ptr [[TMP26]], align 8159// CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 4160// CHECK4-NEXT: store ptr [[B4]], ptr [[TMP27]], align 8161// CHECK4-NEXT: [[TMP28:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 5162// CHECK4-NEXT: store ptr [[C1]], ptr [[TMP28]], align 8163// CHECK4-NEXT: [[TMP29:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 6164// CHECK4-NEXT: store ptr [[TMP3]], ptr [[TMP29]], align 8165// CHECK4-NEXT: [[TMP30:%.*]] = load i32, ptr [[TMP2]], align 4166// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP30]], 0167// CHECK4-NEXT: [[TMP31:%.*]] = zext i1 [[TOBOOL]] to i32168// CHECK4-NEXT: [[TMP32:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8169// CHECK4-NEXT: [[TMP33:%.*]] = load i32, ptr [[TMP32]], align 4170// CHECK4-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP33]], i32 [[TMP31]], i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l19_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 7)171// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]172// CHECK4: omp.inner.for.inc:173// CHECK4-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4174// CHECK4-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4175// CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP34]], [[TMP35]]176// CHECK4-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4177// CHECK4-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4178// CHECK4-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4179// CHECK4-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP36]], [[TMP37]]180// CHECK4-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_COMB_LB]], align 4181// CHECK4-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4182// CHECK4-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4183// CHECK4-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP38]], [[TMP39]]184// CHECK4-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_COMB_UB]], align 4185// CHECK4-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4186// CHECK4-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4187// CHECK4-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[TMP40]], [[TMP41]]188// CHECK4-NEXT: br i1 [[CMP11]], label [[COND_TRUE12:%.*]], label [[COND_FALSE13:%.*]]189// CHECK4: cond.true12:190// CHECK4-NEXT: [[TMP42:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4191// CHECK4-NEXT: br label [[COND_END14:%.*]]192// CHECK4: cond.false13:193// CHECK4-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4194// CHECK4-NEXT: br label [[COND_END14]]195// CHECK4: cond.end14:196// CHECK4-NEXT: [[COND15:%.*]] = phi i32 [ [[TMP42]], [[COND_TRUE12]] ], [ [[TMP43]], [[COND_FALSE13]] ]197// CHECK4-NEXT: store i32 [[COND15]], ptr [[DOTOMP_COMB_UB]], align 4198// CHECK4-NEXT: [[TMP44:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4199// CHECK4-NEXT: store i32 [[TMP44]], ptr [[DOTOMP_IV]], align 4200// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]]201// CHECK4: omp.inner.for.end:202// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]203// CHECK4: omp.loop.exit:204// CHECK4-NEXT: [[TMP45:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8205// CHECK4-NEXT: [[TMP46:%.*]] = load i32, ptr [[TMP45]], align 4206// CHECK4-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP46]])207// CHECK4-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4208// CHECK4-NEXT: [[TMP48:%.*]] = icmp ne i32 [[TMP47]], 0209// CHECK4-NEXT: br i1 [[TMP48]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]210// CHECK4: .omp.lastprivate.then:211// CHECK4-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP1]], ptr align 4 [[C1]], i64 40, i1 false)212// CHECK4-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]213// CHECK4: .omp.lastprivate.done:214// CHECK4-NEXT: br label [[OMP_PRECOND_END]]215// CHECK4: omp.precond.end:216// CHECK4-NEXT: call void @__kmpc_free_shared(ptr [[C1]], i64 40)217// CHECK4-NEXT: ret void218//219//220// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l19_omp_outlined_omp_outlined221// CHECK4-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[D:%.*]]) #[[ATTR1]] {222// CHECK4-NEXT: entry:223// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8224// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8225// CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8226// CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8227// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 8228// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8229// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8230// CHECK4-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8231// CHECK4-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8232// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4233// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4234// CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4235// CHECK4-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4236// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4237// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4238// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4239// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4240// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4241// CHECK4-NEXT: [[B4:%.*]] = alloca [10 x i32], align 4242// CHECK4-NEXT: [[C5:%.*]] = alloca [10 x i32], align 4243// CHECK4-NEXT: [[I6:%.*]] = alloca i32, align 4244// CHECK4-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8245// CHECK4-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8246// CHECK4-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8247// CHECK4-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8248// CHECK4-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8249// CHECK4-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8250// CHECK4-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8251// CHECK4-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8252// CHECK4-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8253// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8254// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8255// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8256// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8257// CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[D_ADDR]], align 8258// CHECK4-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4259// CHECK4-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4260// CHECK4-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4261// CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], 0262// CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1263// CHECK4-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1264// CHECK4-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4265// CHECK4-NEXT: store i32 0, ptr [[I]], align 4266// CHECK4-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4267// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]]268// CHECK4-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]269// CHECK4: omp.precond.then:270// CHECK4-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4271// CHECK4-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4272// CHECK4-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_UB]], align 4273// CHECK4-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8274// CHECK4-NEXT: [[CONV:%.*]] = trunc i64 [[TMP9]] to i32275// CHECK4-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8276// CHECK4-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP10]] to i32277// CHECK4-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4278// CHECK4-NEXT: store i32 [[CONV3]], ptr [[DOTOMP_UB]], align 4279// CHECK4-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4280// CHECK4-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4281// CHECK4-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B4]], ptr align 4 [[TMP2]], i64 40, i1 false)282// CHECK4-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8283// CHECK4-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4284// CHECK4-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3:[0-9]+]], i32 [[TMP12]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)285// CHECK4-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4286// CHECK4-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4287// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]288// CHECK4: omp.inner.for.cond:289// CHECK4-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4290// CHECK4-NEXT: [[CONV7:%.*]] = sext i32 [[TMP14]] to i64291// CHECK4-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8292// CHECK4-NEXT: [[CMP8:%.*]] = icmp ule i64 [[CONV7]], [[TMP15]]293// CHECK4-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]294// CHECK4: omp.inner.for.body:295// CHECK4-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4296// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1297// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]298// CHECK4-NEXT: store i32 [[ADD]], ptr [[I6]], align 4299// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooPi(ptr noundef [[I6]]) #[[ATTR8:[0-9]+]]300// CHECK4-NEXT: [[CALL9:%.*]] = call noundef i32 @_Z3fooPi(ptr noundef [[TMP1]]) #[[ATTR8]]301// CHECK4-NEXT: [[ADD10:%.*]] = add nsw i32 [[CALL]], [[CALL9]]302// CHECK4-NEXT: [[TMP17:%.*]] = load i32, ptr [[I6]], align 4303// CHECK4-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64304// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B4]], i64 0, i64 [[IDXPROM]]305// CHECK4-NEXT: [[CALL11:%.*]] = call noundef i32 @_Z3fooPi(ptr noundef [[ARRAYIDX]]) #[[ATTR8]]306// CHECK4-NEXT: [[ADD12:%.*]] = add nsw i32 [[ADD10]], [[CALL11]]307// CHECK4-NEXT: [[TMP18:%.*]] = load i32, ptr [[I6]], align 4308// CHECK4-NEXT: [[IDXPROM13:%.*]] = sext i32 [[TMP18]] to i64309// CHECK4-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x i32], ptr [[C5]], i64 0, i64 [[IDXPROM13]]310// CHECK4-NEXT: [[CALL15:%.*]] = call noundef i32 @_Z3fooPi(ptr noundef [[ARRAYIDX14]]) #[[ATTR8]]311// CHECK4-NEXT: [[ADD16:%.*]] = add nsw i32 [[ADD12]], [[CALL15]]312// CHECK4-NEXT: [[TMP19:%.*]] = load i32, ptr [[I6]], align 4313// CHECK4-NEXT: [[IDXPROM17:%.*]] = sext i32 [[TMP19]] to i64314// CHECK4-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP4]], i64 0, i64 [[IDXPROM17]]315// CHECK4-NEXT: [[CALL19:%.*]] = call noundef i32 @_Z3fooPi(ptr noundef [[ARRAYIDX18]]) #[[ATTR8]]316// CHECK4-NEXT: [[ADD20:%.*]] = add nsw i32 [[ADD16]], [[CALL19]]317// CHECK4-NEXT: store i32 [[ADD20]], ptr [[TMP1]], align 4318// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]319// CHECK4: omp.body.continue:320// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]321// CHECK4: omp.inner.for.inc:322// CHECK4-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4323// CHECK4-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4324// CHECK4-NEXT: [[ADD21:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]325// CHECK4-NEXT: store i32 [[ADD21]], ptr [[DOTOMP_IV]], align 4326// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]]327// CHECK4: omp.inner.for.end:328// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]329// CHECK4: omp.loop.exit:330// CHECK4-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8331// CHECK4-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4332// CHECK4-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP23]])333// CHECK4-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4334// CHECK4-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0335// CHECK4-NEXT: br i1 [[TMP25]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]336// CHECK4: .omp.lastprivate.then:337// CHECK4-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP3]], ptr align 4 [[C5]], i64 40, i1 false)338// CHECK4-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]339// CHECK4: .omp.lastprivate.done:340// CHECK4-NEXT: br label [[OMP_PRECOND_END]]341// CHECK4: omp.precond.end:342// CHECK4-NEXT: ret void343//344//345// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l19346// CHECK5-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[ARGC:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[D:%.*]]) #[[ATTR0:[0-9]+]] {347// CHECK5-NEXT: entry:348// CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4349// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4350// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4351// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4352// CHECK5-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4353// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4354// CHECK5-NEXT: [[ARGC_CASTED:%.*]] = alloca i32, align 4355// CHECK5-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4356// CHECK5-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4357// CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4358// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4359// CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4360// CHECK5-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4361// CHECK5-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4362// CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4363// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4364// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C_ADDR]], align 4365// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 4366// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4367// CHECK5-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l19_kernel_environment, ptr [[DYN_PTR]])368// CHECK5-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1369// CHECK5-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]370// CHECK5: user_code.entry:371// CHECK5-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])372// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4373// CHECK5-NEXT: store i32 [[TMP6]], ptr [[ARGC_CASTED]], align 4374// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARGC_CASTED]], align 4375// CHECK5-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4376// CHECK5-NEXT: store i32 [[TMP5]], ptr [[DOTTHREADID_TEMP_]], align 4377// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l19_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], i32 [[TMP7]], ptr [[TMP3]]) #[[ATTR4:[0-9]+]]378// CHECK5-NEXT: call void @__kmpc_target_deinit()379// CHECK5-NEXT: ret void380// CHECK5: worker.exit:381// CHECK5-NEXT: ret void382//383//384// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l19_omp_outlined385// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[ARGC:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[D:%.*]]) #[[ATTR1:[0-9]+]] {386// CHECK5-NEXT: entry:387// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4388// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4389// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4390// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4391// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4392// CHECK5-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4393// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4394// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4395// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4396// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4397// CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4398// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4399// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4400// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4401// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4402// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4403// CHECK5-NEXT: [[B4:%.*]] = alloca [10 x i32], align 4404// CHECK5-NEXT: [[I5:%.*]] = alloca i32, align 4405// CHECK5-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [7 x ptr], align 4406// CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4407// CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4408// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4409// CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4410// CHECK5-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4411// CHECK5-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4412// CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4413// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4414// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C_ADDR]], align 4415// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 4416// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4417// CHECK5-NEXT: [[C1:%.*]] = call align 8 ptr @__kmpc_alloc_shared(i32 40)418// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4419// CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4420// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4421// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0422// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1423// CHECK5-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1424// CHECK5-NEXT: store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_2]], align 4425// CHECK5-NEXT: store i32 0, ptr [[I]], align 4426// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4427// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]]428// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]429// CHECK5: omp.precond.then:430// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4431// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4432// CHECK5-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_COMB_UB]], align 4433// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4434// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4435// CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B4]], ptr align 4 [[TMP0]], i32 40, i1 false)436// CHECK5-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()437// CHECK5-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4438// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4439// CHECK5-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP9]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])440// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4441// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4442// CHECK5-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]]443// CHECK5-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]444// CHECK5: cond.true:445// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4446// CHECK5-NEXT: br label [[COND_END:%.*]]447// CHECK5: cond.false:448// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4449// CHECK5-NEXT: br label [[COND_END]]450// CHECK5: cond.end:451// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]452// CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4453// CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4454// CHECK5-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV]], align 4455// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]456// CHECK5: omp.inner.for.cond:457// CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4458// CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4459// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1460// CHECK5-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP15]], [[ADD]]461// CHECK5-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]462// CHECK5: omp.inner.for.body:463// CHECK5-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4464// CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4465// CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0466// CHECK5-NEXT: [[TMP20:%.*]] = inttoptr i32 [[TMP17]] to ptr467// CHECK5-NEXT: store ptr [[TMP20]], ptr [[TMP19]], align 4468// CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1469// CHECK5-NEXT: [[TMP22:%.*]] = inttoptr i32 [[TMP18]] to ptr470// CHECK5-NEXT: store ptr [[TMP22]], ptr [[TMP21]], align 4471// CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2472// CHECK5-NEXT: store ptr [[ARGC_ADDR]], ptr [[TMP23]], align 4473// CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 3474// CHECK5-NEXT: store ptr [[TMP2]], ptr [[TMP24]], align 4475// CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 4476// CHECK5-NEXT: store ptr [[B4]], ptr [[TMP25]], align 4477// CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 5478// CHECK5-NEXT: store ptr [[C1]], ptr [[TMP26]], align 4479// CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 6480// CHECK5-NEXT: store ptr [[TMP3]], ptr [[TMP27]], align 4481// CHECK5-NEXT: [[TMP28:%.*]] = load i32, ptr [[TMP2]], align 4482// CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP28]], 0483// CHECK5-NEXT: [[TMP29:%.*]] = zext i1 [[TOBOOL]] to i32484// CHECK5-NEXT: [[TMP30:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4485// CHECK5-NEXT: [[TMP31:%.*]] = load i32, ptr [[TMP30]], align 4486// CHECK5-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP31]], i32 [[TMP29]], i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l19_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 7)487// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]488// CHECK5: omp.inner.for.inc:489// CHECK5-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4490// CHECK5-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4491// CHECK5-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP32]], [[TMP33]]492// CHECK5-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4493// CHECK5-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4494// CHECK5-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4495// CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP34]], [[TMP35]]496// CHECK5-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_COMB_LB]], align 4497// CHECK5-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4498// CHECK5-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4499// CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP36]], [[TMP37]]500// CHECK5-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_COMB_UB]], align 4501// CHECK5-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4502// CHECK5-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4503// CHECK5-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[TMP38]], [[TMP39]]504// CHECK5-NEXT: br i1 [[CMP11]], label [[COND_TRUE12:%.*]], label [[COND_FALSE13:%.*]]505// CHECK5: cond.true12:506// CHECK5-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4507// CHECK5-NEXT: br label [[COND_END14:%.*]]508// CHECK5: cond.false13:509// CHECK5-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4510// CHECK5-NEXT: br label [[COND_END14]]511// CHECK5: cond.end14:512// CHECK5-NEXT: [[COND15:%.*]] = phi i32 [ [[TMP40]], [[COND_TRUE12]] ], [ [[TMP41]], [[COND_FALSE13]] ]513// CHECK5-NEXT: store i32 [[COND15]], ptr [[DOTOMP_COMB_UB]], align 4514// CHECK5-NEXT: [[TMP42:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4515// CHECK5-NEXT: store i32 [[TMP42]], ptr [[DOTOMP_IV]], align 4516// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]]517// CHECK5: omp.inner.for.end:518// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]519// CHECK5: omp.loop.exit:520// CHECK5-NEXT: [[TMP43:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4521// CHECK5-NEXT: [[TMP44:%.*]] = load i32, ptr [[TMP43]], align 4522// CHECK5-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP44]])523// CHECK5-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4524// CHECK5-NEXT: [[TMP46:%.*]] = icmp ne i32 [[TMP45]], 0525// CHECK5-NEXT: br i1 [[TMP46]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]526// CHECK5: .omp.lastprivate.then:527// CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP1]], ptr align 4 [[C1]], i32 40, i1 false)528// CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]529// CHECK5: .omp.lastprivate.done:530// CHECK5-NEXT: br label [[OMP_PRECOND_END]]531// CHECK5: omp.precond.end:532// CHECK5-NEXT: call void @__kmpc_free_shared(ptr [[C1]], i32 40)533// CHECK5-NEXT: ret void534//535//536// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l19_omp_outlined_omp_outlined537// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[D:%.*]]) #[[ATTR1]] {538// CHECK5-NEXT: entry:539// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4540// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4541// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4542// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4543// CHECK5-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 4544// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4545// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4546// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4547// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4548// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4549// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4550// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4551// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4552// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4553// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4554// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4555// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4556// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4557// CHECK5-NEXT: [[B3:%.*]] = alloca [10 x i32], align 4558// CHECK5-NEXT: [[C4:%.*]] = alloca [10 x i32], align 4559// CHECK5-NEXT: [[I5:%.*]] = alloca i32, align 4560// CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4561// CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4562// CHECK5-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4563// CHECK5-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4564// CHECK5-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 4565// CHECK5-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4566// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4567// CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4568// CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4569// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 4570// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4571// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 4572// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4573// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[D_ADDR]], align 4574// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4575// CHECK5-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4576// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4577// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], 0578// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1579// CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1580// CHECK5-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4581// CHECK5-NEXT: store i32 0, ptr [[I]], align 4582// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4583// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]]584// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]585// CHECK5: omp.precond.then:586// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4587// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4588// CHECK5-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_UB]], align 4589// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4590// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4591// CHECK5-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_LB]], align 4592// CHECK5-NEXT: store i32 [[TMP10]], ptr [[DOTOMP_UB]], align 4593// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4594// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4595// CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B3]], ptr align 4 [[TMP2]], i32 40, i1 false)596// CHECK5-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4597// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4598// CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3:[0-9]+]], i32 [[TMP12]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)599// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4600// CHECK5-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4601// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]602// CHECK5: omp.inner.for.cond:603// CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4604// CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4605// CHECK5-NEXT: [[CMP6:%.*]] = icmp ule i32 [[TMP14]], [[TMP15]]606// CHECK5-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]607// CHECK5: omp.inner.for.body:608// CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4609// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1610// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]611// CHECK5-NEXT: store i32 [[ADD]], ptr [[I5]], align 4612// CHECK5-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooPi(ptr noundef [[I5]]) #[[ATTR8:[0-9]+]]613// CHECK5-NEXT: [[CALL7:%.*]] = call noundef i32 @_Z3fooPi(ptr noundef [[TMP1]]) #[[ATTR8]]614// CHECK5-NEXT: [[ADD8:%.*]] = add nsw i32 [[CALL]], [[CALL7]]615// CHECK5-NEXT: [[TMP17:%.*]] = load i32, ptr [[I5]], align 4616// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B3]], i32 0, i32 [[TMP17]]617// CHECK5-NEXT: [[CALL9:%.*]] = call noundef i32 @_Z3fooPi(ptr noundef [[ARRAYIDX]]) #[[ATTR8]]618// CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[ADD8]], [[CALL9]]619// CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[I5]], align 4620// CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x i32], ptr [[C4]], i32 0, i32 [[TMP18]]621// CHECK5-NEXT: [[CALL12:%.*]] = call noundef i32 @_Z3fooPi(ptr noundef [[ARRAYIDX11]]) #[[ATTR8]]622// CHECK5-NEXT: [[ADD13:%.*]] = add nsw i32 [[ADD10]], [[CALL12]]623// CHECK5-NEXT: [[TMP19:%.*]] = load i32, ptr [[I5]], align 4624// CHECK5-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP4]], i32 0, i32 [[TMP19]]625// CHECK5-NEXT: [[CALL15:%.*]] = call noundef i32 @_Z3fooPi(ptr noundef [[ARRAYIDX14]]) #[[ATTR8]]626// CHECK5-NEXT: [[ADD16:%.*]] = add nsw i32 [[ADD13]], [[CALL15]]627// CHECK5-NEXT: store i32 [[ADD16]], ptr [[TMP1]], align 4628// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]629// CHECK5: omp.body.continue:630// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]631// CHECK5: omp.inner.for.inc:632// CHECK5-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4633// CHECK5-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4634// CHECK5-NEXT: [[ADD17:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]635// CHECK5-NEXT: store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4636// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]]637// CHECK5: omp.inner.for.end:638// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]639// CHECK5: omp.loop.exit:640// CHECK5-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4641// CHECK5-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4642// CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP23]])643// CHECK5-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4644// CHECK5-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0645// CHECK5-NEXT: br i1 [[TMP25]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]646// CHECK5: .omp.lastprivate.then:647// CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP3]], ptr align 4 [[C4]], i32 40, i1 false)648// CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]649// CHECK5: .omp.lastprivate.done:650// CHECK5-NEXT: br label [[OMP_PRECOND_END]]651// CHECK5: omp.precond.end:652// CHECK5-NEXT: ret void653//654