263 lines · cpp
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _2// Test target codegen - host bc file has to be created first.3// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc4// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK15// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc6// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK27// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK28 9// RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc10// RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK111// RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc12// RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK213// RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK214 15// expected-no-diagnostics16#ifndef HEADER17#define HEADER18 19template<typename tx>20tx ftemplate(int n) {21 tx a = 0;22 short aa = 0;23 tx b[10];24 25 #pragma omp target parallel if(target: 0)26 {27 a += 1;28 }29 30 #pragma omp target parallel map(tofrom: aa)31 {32 aa += 1;33 }34 35 #pragma omp target parallel map(tofrom:a, aa, b) if(target: n>40)36 {37 a += 1;38 aa += 1;39 b[2] += 1;40 }41 42 return a;43}44 45int bar(int n){46 int a = 0;47 48 a += ftemplate<int>(n);49 50 return a;51}52 53#endif54// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l3055// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {56// CHECK1-NEXT: entry:57// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 858// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 859// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x ptr], align 860// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 861// CHECK1-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 862// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 863// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30_kernel_environment, ptr [[DYN_PTR]])64// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -165// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]66// CHECK1: user_code.entry:67// CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])68// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 069// CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP3]], align 870// CHECK1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 1)71// CHECK1-NEXT: call void @__kmpc_target_deinit()72// CHECK1-NEXT: ret void73// CHECK1: worker.exit:74// CHECK1-NEXT: ret void75//76//77// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30_omp_outlined78// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] {79// CHECK1-NEXT: entry:80// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 881// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 882// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 883// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 884// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 885// CHECK1-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 886// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 887// CHECK1-NEXT: [[TMP1:%.*]] = load i16, ptr [[TMP0]], align 288// CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i3289// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 190// CHECK1-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i1691// CHECK1-NEXT: store i16 [[CONV1]], ptr [[TMP0]], align 292// CHECK1-NEXT: ret void93//94//95// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l3596// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {97// CHECK1-NEXT: entry:98// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 899// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8100// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 8101// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8102// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x ptr], align 8103// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8104// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8105// CHECK1-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8106// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8107// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8108// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 8109// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8110// CHECK1-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l35_kernel_environment, ptr [[DYN_PTR]])111// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1112// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]113// CHECK1: user_code.entry:114// CHECK1-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])115// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0116// CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP5]], align 8117// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1118// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP6]], align 8119// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2120// CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP7]], align 8121// CHECK1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP4]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l35_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 3)122// CHECK1-NEXT: call void @__kmpc_target_deinit()123// CHECK1-NEXT: ret void124// CHECK1: worker.exit:125// CHECK1-NEXT: ret void126//127//128// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l35_omp_outlined129// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {130// CHECK1-NEXT: entry:131// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8132// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8133// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8134// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 8135// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8136// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8137// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8138// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8139// CHECK1-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8140// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8141// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8142// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 8143// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8144// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP0]], align 4145// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1146// CHECK1-NEXT: store i32 [[ADD]], ptr [[TMP0]], align 4147// CHECK1-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP1]], align 2148// CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32149// CHECK1-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1150// CHECK1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16151// CHECK1-NEXT: store i16 [[CONV2]], ptr [[TMP1]], align 2152// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP2]], i64 0, i64 2153// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX]], align 4154// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1155// CHECK1-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4156// CHECK1-NEXT: ret void157//158//159// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30160// CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {161// CHECK2-NEXT: entry:162// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4163// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 4164// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x ptr], align 4165// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4166// CHECK2-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4167// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4168// CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30_kernel_environment, ptr [[DYN_PTR]])169// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1170// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]171// CHECK2: user_code.entry:172// CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])173// CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0174// CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP3]], align 4175// CHECK2-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 1)176// CHECK2-NEXT: call void @__kmpc_target_deinit()177// CHECK2-NEXT: ret void178// CHECK2: worker.exit:179// CHECK2-NEXT: ret void180//181//182// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30_omp_outlined183// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] {184// CHECK2-NEXT: entry:185// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4186// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4187// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 4188// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4189// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4190// CHECK2-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4191// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4192// CHECK2-NEXT: [[TMP1:%.*]] = load i16, ptr [[TMP0]], align 2193// CHECK2-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32194// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1195// CHECK2-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16196// CHECK2-NEXT: store i16 [[CONV1]], ptr [[TMP0]], align 2197// CHECK2-NEXT: ret void198//199//200// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l35201// CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {202// CHECK2-NEXT: entry:203// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4204// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4205// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 4206// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4207// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x ptr], align 4208// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4209// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4210// CHECK2-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4211// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4212// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4213// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 4214// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 4215// CHECK2-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l35_kernel_environment, ptr [[DYN_PTR]])216// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1217// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]218// CHECK2: user_code.entry:219// CHECK2-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])220// CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0221// CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP5]], align 4222// CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1223// CHECK2-NEXT: store ptr [[TMP1]], ptr [[TMP6]], align 4224// CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2225// CHECK2-NEXT: store ptr [[TMP2]], ptr [[TMP7]], align 4226// CHECK2-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP4]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l35_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 3)227// CHECK2-NEXT: call void @__kmpc_target_deinit()228// CHECK2-NEXT: ret void229// CHECK2: worker.exit:230// CHECK2-NEXT: ret void231//232//233// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l35_omp_outlined234// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {235// CHECK2-NEXT: entry:236// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4237// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4238// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4239// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 4240// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4241// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4242// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4243// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4244// CHECK2-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4245// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4246// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4247// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 4248// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 4249// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP0]], align 4250// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1251// CHECK2-NEXT: store i32 [[ADD]], ptr [[TMP0]], align 4252// CHECK2-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP1]], align 2253// CHECK2-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32254// CHECK2-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1255// CHECK2-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16256// CHECK2-NEXT: store i16 [[CONV2]], ptr [[TMP1]], align 2257// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP2]], i32 0, i32 2258// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX]], align 4259// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1260// CHECK2-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4261// CHECK2-NEXT: ret void262//263