264 lines · cpp
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _2// Test target codegen - host bc file has to be created first.3// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc4// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK15// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc6// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK27// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK28 9// RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc10// RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK111// RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc12// RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK213// RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK214 15// expected-no-diagnostics16#ifndef HEADER17#define HEADER18 19template<typename tx>20tx ftemplate(int n) {21 tx a = 0;22 short aa = 0;23 tx b[10];24 25 #pragma omp target parallel map(tofrom: aa) num_threads(1024)26 {27 aa += 1;28 }29 30 #pragma omp target parallel map(tofrom:a, aa, b) if(target: n>40) num_threads(n)31 {32 a += 1;33 aa += 1;34 b[2] += 1;35 }36 37 return a;38}39 40int bar(int n){41 int a = 0;42 43 a += ftemplate<int>(n);44 45 return a;46}47 48#endif49// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l2550// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {51// CHECK1-NEXT: entry:52// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 853// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 854// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x ptr], align 855// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 856// CHECK1-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 857// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 858// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25_kernel_environment, ptr [[DYN_PTR]])59// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -160// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]61// CHECK1: user_code.entry:62// CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])63// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 064// CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP3]], align 865// CHECK1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 1024, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 1)66// CHECK1-NEXT: call void @__kmpc_target_deinit()67// CHECK1-NEXT: ret void68// CHECK1: worker.exit:69// CHECK1-NEXT: ret void70//71//72// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25_omp_outlined73// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] {74// CHECK1-NEXT: entry:75// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 876// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 877// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 878// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 879// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 880// CHECK1-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 881// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 882// CHECK1-NEXT: [[TMP1:%.*]] = load i16, ptr [[TMP0]], align 283// CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i3284// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 185// CHECK1-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i1686// CHECK1-NEXT: store i16 [[CONV1]], ptr [[TMP0]], align 287// CHECK1-NEXT: ret void88//89//90// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l3091// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR4:[0-9]+]] {92// CHECK1-NEXT: entry:93// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 894// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 895// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 896// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 897// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 898// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x ptr], align 899// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8100// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8101// CHECK1-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8102// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8103// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8104// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8105// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 8106// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8107// CHECK1-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30_kernel_environment, ptr [[DYN_PTR]])108// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1109// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]110// CHECK1: user_code.entry:111// CHECK1-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])112// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4113// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0114// CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP6]], align 8115// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1116// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP7]], align 8117// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2118// CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP8]], align 8119// CHECK1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP4]], i32 1, i32 [[TMP5]], i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 3)120// CHECK1-NEXT: call void @__kmpc_target_deinit()121// CHECK1-NEXT: ret void122// CHECK1: worker.exit:123// CHECK1-NEXT: ret void124//125//126// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30_omp_outlined127// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {128// CHECK1-NEXT: entry:129// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8130// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8131// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8132// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 8133// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8134// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8135// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8136// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8137// CHECK1-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8138// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8139// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8140// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 8141// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8142// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP0]], align 4143// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1144// CHECK1-NEXT: store i32 [[ADD]], ptr [[TMP0]], align 4145// CHECK1-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP1]], align 2146// CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32147// CHECK1-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1148// CHECK1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16149// CHECK1-NEXT: store i16 [[CONV2]], ptr [[TMP1]], align 2150// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP2]], i64 0, i64 2151// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX]], align 4152// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1153// CHECK1-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4154// CHECK1-NEXT: ret void155//156//157// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25158// CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {159// CHECK2-NEXT: entry:160// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4161// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 4162// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x ptr], align 4163// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4164// CHECK2-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4165// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4166// CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25_kernel_environment, ptr [[DYN_PTR]])167// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1168// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]169// CHECK2: user_code.entry:170// CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])171// CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0172// CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP3]], align 4173// CHECK2-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 1024, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 1)174// CHECK2-NEXT: call void @__kmpc_target_deinit()175// CHECK2-NEXT: ret void176// CHECK2: worker.exit:177// CHECK2-NEXT: ret void178//179//180// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25_omp_outlined181// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] {182// CHECK2-NEXT: entry:183// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4184// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4185// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 4186// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4187// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4188// CHECK2-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4189// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4190// CHECK2-NEXT: [[TMP1:%.*]] = load i16, ptr [[TMP0]], align 2191// CHECK2-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32192// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1193// CHECK2-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16194// CHECK2-NEXT: store i16 [[CONV1]], ptr [[TMP0]], align 2195// CHECK2-NEXT: ret void196//197//198// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30199// CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR4:[0-9]+]] {200// CHECK2-NEXT: entry:201// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4202// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4203// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 4204// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4205// CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4206// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x ptr], align 4207// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4208// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4209// CHECK2-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4210// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4211// CHECK2-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4212// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4213// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 4214// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 4215// CHECK2-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30_kernel_environment, ptr [[DYN_PTR]])216// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1217// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]218// CHECK2: user_code.entry:219// CHECK2-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])220// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4221// CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0222// CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP6]], align 4223// CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1224// CHECK2-NEXT: store ptr [[TMP1]], ptr [[TMP7]], align 4225// CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2226// CHECK2-NEXT: store ptr [[TMP2]], ptr [[TMP8]], align 4227// CHECK2-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP4]], i32 1, i32 [[TMP5]], i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 3)228// CHECK2-NEXT: call void @__kmpc_target_deinit()229// CHECK2-NEXT: ret void230// CHECK2: worker.exit:231// CHECK2-NEXT: ret void232//233//234// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30_omp_outlined235// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {236// CHECK2-NEXT: entry:237// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4238// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4239// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4240// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 4241// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4242// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4243// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4244// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4245// CHECK2-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4246// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4247// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4248// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 4249// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 4250// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP0]], align 4251// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1252// CHECK2-NEXT: store i32 [[ADD]], ptr [[TMP0]], align 4253// CHECK2-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP1]], align 2254// CHECK2-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32255// CHECK2-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1256// CHECK2-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16257// CHECK2-NEXT: store i16 [[CONV2]], ptr [[TMP1]], align 2258// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP2]], i32 0, i32 2259// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX]], align 4260// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1261// CHECK2-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4262// CHECK2-NEXT: ret void263//264