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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _2// Test target codegen - host bc file has to be created first.3// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc4// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK45-645// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc6// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK45-327// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK45-32-EX8 9// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc10// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK-6411// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc12// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK-3213// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -fopenmp -fopenmp-cuda-mode -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK-32-EX14 15// expected-no-diagnostics16#ifndef HEADER17#define HEADER18 19// Check that the execution mode of all 2 target regions on the gpu is set to NonSPMD Mode.20 21#define N 100022#define M 1023 24template<typename tx>25tx ftemplate(int n) {26  tx a[N];27  short aa[N];28  tx b[10];29  tx c[M][M];30  tx f = n;31  tx l;32  int k;33 34#pragma omp target teams distribute simd lastprivate(l) dist_schedule(static,128)35  for(int i = 0; i < n; i++) {36    a[i] = 1;37    l = i;38  }39 40  #pragma omp target teams distribute simd map(tofrom: aa) num_teams(M) thread_limit(64)41  for(int i = 0; i < n; i++) {42    aa[i] += 1;43  }44 45#pragma omp target teams distribute simd map(tofrom:a, aa, b) if(target: n>40)46  for(int i = 0; i < 10; i++) {47    b[i] += 1;48  }49 50#pragma omp target teams distribute simd collapse(2) firstprivate(f) private(k)51  for(int i = 0; i < M; i++) {52    for(int j = 0; j < M; j++) {53      k = M;54      c[i][j] = i + j * f + k;55    }56  }57 58  return a[0];59}60 61int bar(int n){62  int a = 0;63 64  a += ftemplate<int>(n);65 66  return a;67}68 69#endif70// CHECK45-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l3471// CHECK45-64-SAME: (ptr noalias [[DYN_PTR:%.*]], i64 [[N:%.*]], ptr nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 [[L:%.*]]) #[[ATTR0:[0-9]+]] {72// CHECK45-64-NEXT:  entry:73// CHECK45-64-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 874// CHECK45-64-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 875// CHECK45-64-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 876// CHECK45-64-NEXT:    [[L_ADDR:%.*]] = alloca i64, align 877// CHECK45-64-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 878// CHECK45-64-NEXT:    [[L_CASTED:%.*]] = alloca i64, align 879// CHECK45-64-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 480// CHECK45-64-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 481// CHECK45-64-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 882// CHECK45-64-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 883// CHECK45-64-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 884// CHECK45-64-NEXT:    store i64 [[L]], ptr [[L_ADDR]], align 885// CHECK45-64-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 886// CHECK45-64-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_kernel_environment, ptr [[DYN_PTR]])87// CHECK45-64-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -188// CHECK45-64-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]89// CHECK45-64:       user_code.entry:90// CHECK45-64-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])91// CHECK45-64-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 492// CHECK45-64-NEXT:    store i32 [[TMP3]], ptr [[N_CASTED]], align 493// CHECK45-64-NEXT:    [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 894// CHECK45-64-NEXT:    [[TMP5:%.*]] = load i32, ptr [[L_ADDR]], align 495// CHECK45-64-NEXT:    store i32 [[TMP5]], ptr [[L_CASTED]], align 496// CHECK45-64-NEXT:    [[TMP6:%.*]] = load i64, ptr [[L_CASTED]], align 897// CHECK45-64-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 498// CHECK45-64-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 499// CHECK45-64-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]], i64 [[TMP6]]) #[[ATTR2:[0-9]+]]100// CHECK45-64-NEXT:    call void @__kmpc_target_deinit()101// CHECK45-64-NEXT:    ret void102// CHECK45-64:       worker.exit:103// CHECK45-64-NEXT:    ret void104//105//106// CHECK45-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined107// CHECK45-64-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], ptr nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 [[L:%.*]]) #[[ATTR1:[0-9]+]] {108// CHECK45-64-NEXT:  entry:109// CHECK45-64-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8110// CHECK45-64-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8111// CHECK45-64-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8112// CHECK45-64-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8113// CHECK45-64-NEXT:    [[L_ADDR:%.*]] = alloca i64, align 8114// CHECK45-64-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4115// CHECK45-64-NEXT:    [[TMP:%.*]] = alloca i32, align 4116// CHECK45-64-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4117// CHECK45-64-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4118// CHECK45-64-NEXT:    [[I:%.*]] = alloca i32, align 4119// CHECK45-64-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4120// CHECK45-64-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4121// CHECK45-64-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4122// CHECK45-64-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4123// CHECK45-64-NEXT:    [[I3:%.*]] = alloca i32, align 4124// CHECK45-64-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8125// CHECK45-64-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8126// CHECK45-64-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8127// CHECK45-64-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8128// CHECK45-64-NEXT:    store i64 [[L]], ptr [[L_ADDR]], align 8129// CHECK45-64-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8130// CHECK45-64-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4131// CHECK45-64-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4132// CHECK45-64-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4133// CHECK45-64-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0134// CHECK45-64-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1135// CHECK45-64-NEXT:    [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1136// CHECK45-64-NEXT:    store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4137// CHECK45-64-NEXT:    store i32 0, ptr [[I]], align 4138// CHECK45-64-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4139// CHECK45-64-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]140// CHECK45-64-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]141// CHECK45-64:       omp.precond.then:142// CHECK45-64-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4143// CHECK45-64-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4144// CHECK45-64-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4145// CHECK45-64-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4146// CHECK45-64-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4147// CHECK45-64-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8148// CHECK45-64-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4149// CHECK45-64-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 128)150// CHECK45-64-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]151// CHECK45-64:       omp.dispatch.cond:152// CHECK45-64-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4153// CHECK45-64-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4154// CHECK45-64-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]]155// CHECK45-64-NEXT:    br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]156// CHECK45-64:       cond.true:157// CHECK45-64-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4158// CHECK45-64-NEXT:    br label [[COND_END:%.*]]159// CHECK45-64:       cond.false:160// CHECK45-64-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4161// CHECK45-64-NEXT:    br label [[COND_END]]162// CHECK45-64:       cond.end:163// CHECK45-64-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]164// CHECK45-64-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4165// CHECK45-64-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4166// CHECK45-64-NEXT:    store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4167// CHECK45-64-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4168// CHECK45-64-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4169// CHECK45-64-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]170// CHECK45-64-NEXT:    br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]171// CHECK45-64:       omp.dispatch.body:172// CHECK45-64-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]173// CHECK45-64:       omp.inner.for.cond:174// CHECK45-64-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]]175// CHECK45-64-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP18]]176// CHECK45-64-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]177// CHECK45-64-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]178// CHECK45-64:       omp.inner.for.body:179// CHECK45-64-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]180// CHECK45-64-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1181// CHECK45-64-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]182// CHECK45-64-NEXT:    store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP18]]183// CHECK45-64-NEXT:    [[TMP17:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP18]]184// CHECK45-64-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64185// CHECK45-64-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]186// CHECK45-64-NEXT:    store i32 1, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP18]]187// CHECK45-64-NEXT:    [[TMP18:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP18]]188// CHECK45-64-NEXT:    store i32 [[TMP18]], ptr [[L_ADDR]], align 4, !llvm.access.group [[ACC_GRP18]]189// CHECK45-64-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]190// CHECK45-64:       omp.body.continue:191// CHECK45-64-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]192// CHECK45-64:       omp.inner.for.inc:193// CHECK45-64-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]194// CHECK45-64-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1195// CHECK45-64-NEXT:    store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]196// CHECK45-64-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]197// CHECK45-64:       omp.inner.for.end:198// CHECK45-64-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]199// CHECK45-64:       omp.dispatch.inc:200// CHECK45-64-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4201// CHECK45-64-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4202// CHECK45-64-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]203// CHECK45-64-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_LB]], align 4204// CHECK45-64-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4205// CHECK45-64-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4206// CHECK45-64-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]207// CHECK45-64-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_UB]], align 4208// CHECK45-64-NEXT:    br label [[OMP_DISPATCH_COND]]209// CHECK45-64:       omp.dispatch.end:210// CHECK45-64-NEXT:    [[TMP24:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8211// CHECK45-64-NEXT:    [[TMP25:%.*]] = load i32, ptr [[TMP24]], align 4212// CHECK45-64-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP25]])213// CHECK45-64-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4214// CHECK45-64-NEXT:    [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0215// CHECK45-64-NEXT:    br i1 [[TMP27]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]216// CHECK45-64:       .omp.final.then:217// CHECK45-64-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4218// CHECK45-64-NEXT:    [[SUB10:%.*]] = sub nsw i32 [[TMP28]], 0219// CHECK45-64-NEXT:    [[DIV11:%.*]] = sdiv i32 [[SUB10]], 1220// CHECK45-64-NEXT:    [[MUL12:%.*]] = mul nsw i32 [[DIV11]], 1221// CHECK45-64-NEXT:    [[ADD13:%.*]] = add nsw i32 0, [[MUL12]]222// CHECK45-64-NEXT:    store i32 [[ADD13]], ptr [[I3]], align 4223// CHECK45-64-NEXT:    br label [[DOTOMP_FINAL_DONE]]224// CHECK45-64:       .omp.final.done:225// CHECK45-64-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4226// CHECK45-64-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0227// CHECK45-64-NEXT:    br i1 [[TMP30]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]228// CHECK45-64:       .omp.lastprivate.then:229// CHECK45-64-NEXT:    [[TMP31:%.*]] = load i32, ptr [[L_ADDR]], align 4230// CHECK45-64-NEXT:    store i32 [[TMP31]], ptr [[L_ADDR]], align 4231// CHECK45-64-NEXT:    br label [[DOTOMP_LASTPRIVATE_DONE]]232// CHECK45-64:       .omp.lastprivate.done:233// CHECK45-64-NEXT:    br label [[OMP_PRECOND_END]]234// CHECK45-64:       omp.precond.end:235// CHECK45-64-NEXT:    ret void236//237//238// CHECK45-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l40239// CHECK45-64-SAME: (ptr noalias [[DYN_PTR:%.*]], i64 [[N:%.*]], ptr nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR3:[0-9]+]] {240// CHECK45-64-NEXT:  entry:241// CHECK45-64-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8242// CHECK45-64-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8243// CHECK45-64-NEXT:    [[AA_ADDR:%.*]] = alloca ptr, align 8244// CHECK45-64-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8245// CHECK45-64-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4246// CHECK45-64-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4247// CHECK45-64-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8248// CHECK45-64-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8249// CHECK45-64-NEXT:    store ptr [[AA]], ptr [[AA_ADDR]], align 8250// CHECK45-64-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8251// CHECK45-64-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l40_kernel_environment, ptr [[DYN_PTR]])252// CHECK45-64-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1253// CHECK45-64-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]254// CHECK45-64:       user_code.entry:255// CHECK45-64-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])256// CHECK45-64-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4257// CHECK45-64-NEXT:    store i32 [[TMP3]], ptr [[N_CASTED]], align 4258// CHECK45-64-NEXT:    [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8259// CHECK45-64-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 4260// CHECK45-64-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4261// CHECK45-64-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l40_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]]) #[[ATTR2]]262// CHECK45-64-NEXT:    call void @__kmpc_target_deinit()263// CHECK45-64-NEXT:    ret void264// CHECK45-64:       worker.exit:265// CHECK45-64-NEXT:    ret void266//267//268// CHECK45-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l40_omp_outlined269// CHECK45-64-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], ptr nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR1]] {270// CHECK45-64-NEXT:  entry:271// CHECK45-64-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8272// CHECK45-64-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8273// CHECK45-64-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8274// CHECK45-64-NEXT:    [[AA_ADDR:%.*]] = alloca ptr, align 8275// CHECK45-64-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4276// CHECK45-64-NEXT:    [[TMP:%.*]] = alloca i32, align 4277// CHECK45-64-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4278// CHECK45-64-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4279// CHECK45-64-NEXT:    [[I:%.*]] = alloca i32, align 4280// CHECK45-64-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4281// CHECK45-64-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4282// CHECK45-64-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4283// CHECK45-64-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4284// CHECK45-64-NEXT:    [[I3:%.*]] = alloca i32, align 4285// CHECK45-64-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8286// CHECK45-64-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8287// CHECK45-64-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8288// CHECK45-64-NEXT:    store ptr [[AA]], ptr [[AA_ADDR]], align 8289// CHECK45-64-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8290// CHECK45-64-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4291// CHECK45-64-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4292// CHECK45-64-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4293// CHECK45-64-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0294// CHECK45-64-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1295// CHECK45-64-NEXT:    [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1296// CHECK45-64-NEXT:    store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4297// CHECK45-64-NEXT:    store i32 0, ptr [[I]], align 4298// CHECK45-64-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4299// CHECK45-64-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]300// CHECK45-64-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]301// CHECK45-64:       omp.precond.then:302// CHECK45-64-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4303// CHECK45-64-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4304// CHECK45-64-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4305// CHECK45-64-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4306// CHECK45-64-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4307// CHECK45-64-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()308// CHECK45-64-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8309// CHECK45-64-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4310// CHECK45-64-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])311// CHECK45-64-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]312// CHECK45-64:       omp.dispatch.cond:313// CHECK45-64-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4314// CHECK45-64-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4315// CHECK45-64-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]]316// CHECK45-64-NEXT:    br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]317// CHECK45-64:       cond.true:318// CHECK45-64-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4319// CHECK45-64-NEXT:    br label [[COND_END:%.*]]320// CHECK45-64:       cond.false:321// CHECK45-64-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4322// CHECK45-64-NEXT:    br label [[COND_END]]323// CHECK45-64:       cond.end:324// CHECK45-64-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]325// CHECK45-64-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4326// CHECK45-64-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4327// CHECK45-64-NEXT:    store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4328// CHECK45-64-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4329// CHECK45-64-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4330// CHECK45-64-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]331// CHECK45-64-NEXT:    br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]332// CHECK45-64:       omp.dispatch.body:333// CHECK45-64-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]334// CHECK45-64:       omp.inner.for.cond:335// CHECK45-64-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22:![0-9]+]]336// CHECK45-64-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP22]]337// CHECK45-64-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]338// CHECK45-64-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]339// CHECK45-64:       omp.inner.for.body:340// CHECK45-64-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]341// CHECK45-64-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1342// CHECK45-64-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]343// CHECK45-64-NEXT:    store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP22]]344// CHECK45-64-NEXT:    [[TMP17:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP22]]345// CHECK45-64-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64346// CHECK45-64-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]347// CHECK45-64-NEXT:    [[TMP18:%.*]] = load i16, ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP22]]348// CHECK45-64-NEXT:    [[CONV:%.*]] = sext i16 [[TMP18]] to i32349// CHECK45-64-NEXT:    [[ADD7:%.*]] = add nsw i32 [[CONV]], 1350// CHECK45-64-NEXT:    [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16351// CHECK45-64-NEXT:    store i16 [[CONV8]], ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP22]]352// CHECK45-64-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]353// CHECK45-64:       omp.body.continue:354// CHECK45-64-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]355// CHECK45-64:       omp.inner.for.inc:356// CHECK45-64-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]357// CHECK45-64-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP19]], 1358// CHECK45-64-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]359// CHECK45-64-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]360// CHECK45-64:       omp.inner.for.end:361// CHECK45-64-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]362// CHECK45-64:       omp.dispatch.inc:363// CHECK45-64-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4364// CHECK45-64-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4365// CHECK45-64-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]366// CHECK45-64-NEXT:    store i32 [[ADD10]], ptr [[DOTOMP_LB]], align 4367// CHECK45-64-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4368// CHECK45-64-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4369// CHECK45-64-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]370// CHECK45-64-NEXT:    store i32 [[ADD11]], ptr [[DOTOMP_UB]], align 4371// CHECK45-64-NEXT:    br label [[OMP_DISPATCH_COND]]372// CHECK45-64:       omp.dispatch.end:373// CHECK45-64-NEXT:    [[TMP24:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8374// CHECK45-64-NEXT:    [[TMP25:%.*]] = load i32, ptr [[TMP24]], align 4375// CHECK45-64-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP25]])376// CHECK45-64-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4377// CHECK45-64-NEXT:    [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0378// CHECK45-64-NEXT:    br i1 [[TMP27]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]379// CHECK45-64:       .omp.final.then:380// CHECK45-64-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4381// CHECK45-64-NEXT:    [[SUB12:%.*]] = sub nsw i32 [[TMP28]], 0382// CHECK45-64-NEXT:    [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1383// CHECK45-64-NEXT:    [[MUL14:%.*]] = mul nsw i32 [[DIV13]], 1384// CHECK45-64-NEXT:    [[ADD15:%.*]] = add nsw i32 0, [[MUL14]]385// CHECK45-64-NEXT:    store i32 [[ADD15]], ptr [[I3]], align 4386// CHECK45-64-NEXT:    br label [[DOTOMP_FINAL_DONE]]387// CHECK45-64:       .omp.final.done:388// CHECK45-64-NEXT:    br label [[OMP_PRECOND_END]]389// CHECK45-64:       omp.precond.end:390// CHECK45-64-NEXT:    ret void391//392//393// CHECK45-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l45394// CHECK45-64-SAME: (ptr noalias [[DYN_PTR:%.*]], ptr nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {395// CHECK45-64-NEXT:  entry:396// CHECK45-64-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8397// CHECK45-64-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8398// CHECK45-64-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4399// CHECK45-64-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4400// CHECK45-64-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8401// CHECK45-64-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8402// CHECK45-64-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8403// CHECK45-64-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l45_kernel_environment, ptr [[DYN_PTR]])404// CHECK45-64-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1405// CHECK45-64-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]406// CHECK45-64:       user_code.entry:407// CHECK45-64-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])408// CHECK45-64-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 4409// CHECK45-64-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4410// CHECK45-64-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l45_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]]) #[[ATTR2]]411// CHECK45-64-NEXT:    call void @__kmpc_target_deinit()412// CHECK45-64-NEXT:    ret void413// CHECK45-64:       worker.exit:414// CHECK45-64-NEXT:    ret void415//416//417// CHECK45-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l45_omp_outlined418// CHECK45-64-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {419// CHECK45-64-NEXT:  entry:420// CHECK45-64-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8421// CHECK45-64-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8422// CHECK45-64-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8423// CHECK45-64-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4424// CHECK45-64-NEXT:    [[TMP:%.*]] = alloca i32, align 4425// CHECK45-64-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4426// CHECK45-64-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4427// CHECK45-64-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4428// CHECK45-64-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4429// CHECK45-64-NEXT:    [[I:%.*]] = alloca i32, align 4430// CHECK45-64-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8431// CHECK45-64-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8432// CHECK45-64-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8433// CHECK45-64-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8434// CHECK45-64-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4435// CHECK45-64-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4436// CHECK45-64-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4437// CHECK45-64-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4438// CHECK45-64-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()439// CHECK45-64-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8440// CHECK45-64-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4441// CHECK45-64-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])442// CHECK45-64-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]443// CHECK45-64:       omp.dispatch.cond:444// CHECK45-64-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4445// CHECK45-64-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9446// CHECK45-64-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]447// CHECK45-64:       cond.true:448// CHECK45-64-NEXT:    br label [[COND_END:%.*]]449// CHECK45-64:       cond.false:450// CHECK45-64-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4451// CHECK45-64-NEXT:    br label [[COND_END]]452// CHECK45-64:       cond.end:453// CHECK45-64-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]454// CHECK45-64-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4455// CHECK45-64-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4456// CHECK45-64-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4457// CHECK45-64-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4458// CHECK45-64-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4459// CHECK45-64-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]460// CHECK45-64-NEXT:    br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]461// CHECK45-64:       omp.dispatch.body:462// CHECK45-64-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]463// CHECK45-64:       omp.inner.for.cond:464// CHECK45-64-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25:![0-9]+]]465// CHECK45-64-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP25]]466// CHECK45-64-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]467// CHECK45-64-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]468// CHECK45-64:       omp.inner.for.body:469// CHECK45-64-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]]470// CHECK45-64-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1471// CHECK45-64-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]472// CHECK45-64-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP25]]473// CHECK45-64-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP25]]474// CHECK45-64-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64475// CHECK45-64-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]476// CHECK45-64-NEXT:    [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]]477// CHECK45-64-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1478// CHECK45-64-NEXT:    store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]]479// CHECK45-64-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]480// CHECK45-64:       omp.body.continue:481// CHECK45-64-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]482// CHECK45-64:       omp.inner.for.inc:483// CHECK45-64-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]]484// CHECK45-64-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1485// CHECK45-64-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]]486// CHECK45-64-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]487// CHECK45-64:       omp.inner.for.end:488// CHECK45-64-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]489// CHECK45-64:       omp.dispatch.inc:490// CHECK45-64-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4491// CHECK45-64-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4492// CHECK45-64-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]493// CHECK45-64-NEXT:    store i32 [[ADD5]], ptr [[DOTOMP_LB]], align 4494// CHECK45-64-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4495// CHECK45-64-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4496// CHECK45-64-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]497// CHECK45-64-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_UB]], align 4498// CHECK45-64-NEXT:    br label [[OMP_DISPATCH_COND]]499// CHECK45-64:       omp.dispatch.end:500// CHECK45-64-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP2]])501// CHECK45-64-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4502// CHECK45-64-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0503// CHECK45-64-NEXT:    br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]504// CHECK45-64:       .omp.final.then:505// CHECK45-64-NEXT:    store i32 10, ptr [[I]], align 4506// CHECK45-64-NEXT:    br label [[DOTOMP_FINAL_DONE]]507// CHECK45-64:       .omp.final.done:508// CHECK45-64-NEXT:    ret void509//510//511// CHECK45-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l50512// CHECK45-64-SAME: (ptr noalias [[DYN_PTR:%.*]], ptr nonnull align 4 dereferenceable(400) [[C:%.*]], i64 [[F:%.*]]) #[[ATTR0]] {513// CHECK45-64-NEXT:  entry:514// CHECK45-64-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8515// CHECK45-64-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8516// CHECK45-64-NEXT:    [[F_ADDR:%.*]] = alloca i64, align 8517// CHECK45-64-NEXT:    [[F_CASTED:%.*]] = alloca i64, align 8518// CHECK45-64-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4519// CHECK45-64-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4520// CHECK45-64-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8521// CHECK45-64-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8522// CHECK45-64-NEXT:    store i64 [[F]], ptr [[F_ADDR]], align 8523// CHECK45-64-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8524// CHECK45-64-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l50_kernel_environment, ptr [[DYN_PTR]])525// CHECK45-64-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1526// CHECK45-64-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]527// CHECK45-64:       user_code.entry:528// CHECK45-64-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])529// CHECK45-64-NEXT:    [[TMP3:%.*]] = load i32, ptr [[F_ADDR]], align 4530// CHECK45-64-NEXT:    store i32 [[TMP3]], ptr [[F_CASTED]], align 4531// CHECK45-64-NEXT:    [[TMP4:%.*]] = load i64, ptr [[F_CASTED]], align 8532// CHECK45-64-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 4533// CHECK45-64-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4534// CHECK45-64-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l50_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i64 [[TMP4]]) #[[ATTR2]]535// CHECK45-64-NEXT:    call void @__kmpc_target_deinit()536// CHECK45-64-NEXT:    ret void537// CHECK45-64:       worker.exit:538// CHECK45-64-NEXT:    ret void539//540//541// CHECK45-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l50_omp_outlined542// CHECK45-64-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(400) [[C:%.*]], i64 [[F:%.*]]) #[[ATTR1]] {543// CHECK45-64-NEXT:  entry:544// CHECK45-64-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8545// CHECK45-64-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8546// CHECK45-64-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8547// CHECK45-64-NEXT:    [[F_ADDR:%.*]] = alloca i64, align 8548// CHECK45-64-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4549// CHECK45-64-NEXT:    [[TMP:%.*]] = alloca i32, align 4550// CHECK45-64-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4551// CHECK45-64-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4552// CHECK45-64-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4553// CHECK45-64-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4554// CHECK45-64-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4555// CHECK45-64-NEXT:    [[K:%.*]] = alloca i32, align 4556// CHECK45-64-NEXT:    [[I:%.*]] = alloca i32, align 4557// CHECK45-64-NEXT:    [[J:%.*]] = alloca i32, align 4558// CHECK45-64-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8559// CHECK45-64-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8560// CHECK45-64-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8561// CHECK45-64-NEXT:    store i64 [[F]], ptr [[F_ADDR]], align 8562// CHECK45-64-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8563// CHECK45-64-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4564// CHECK45-64-NEXT:    store i32 99, ptr [[DOTOMP_UB]], align 4565// CHECK45-64-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4566// CHECK45-64-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4567// CHECK45-64-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()568// CHECK45-64-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8569// CHECK45-64-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4570// CHECK45-64-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])571// CHECK45-64-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]572// CHECK45-64:       omp.dispatch.cond:573// CHECK45-64-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4574// CHECK45-64-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 99575// CHECK45-64-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]576// CHECK45-64:       cond.true:577// CHECK45-64-NEXT:    br label [[COND_END:%.*]]578// CHECK45-64:       cond.false:579// CHECK45-64-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4580// CHECK45-64-NEXT:    br label [[COND_END]]581// CHECK45-64:       cond.end:582// CHECK45-64-NEXT:    [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]583// CHECK45-64-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4584// CHECK45-64-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4585// CHECK45-64-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4586// CHECK45-64-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4587// CHECK45-64-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4588// CHECK45-64-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]589// CHECK45-64-NEXT:    br i1 [[CMP2]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]590// CHECK45-64:       omp.dispatch.body:591// CHECK45-64-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]592// CHECK45-64:       omp.inner.for.cond:593// CHECK45-64-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28:![0-9]+]]594// CHECK45-64-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP28]]595// CHECK45-64-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]596// CHECK45-64-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]597// CHECK45-64:       omp.inner.for.body:598// CHECK45-64-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]599// CHECK45-64-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP10]], 10600// CHECK45-64-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 1601// CHECK45-64-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]602// CHECK45-64-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP28]]603// CHECK45-64-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]604// CHECK45-64-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]605// CHECK45-64-NEXT:    [[DIV4:%.*]] = sdiv i32 [[TMP12]], 10606// CHECK45-64-NEXT:    [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 10607// CHECK45-64-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL5]]608// CHECK45-64-NEXT:    [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1609// CHECK45-64-NEXT:    [[ADD7:%.*]] = add nsw i32 0, [[MUL6]]610// CHECK45-64-NEXT:    store i32 [[ADD7]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP28]]611// CHECK45-64-NEXT:    store i32 10, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP28]]612// CHECK45-64-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP28]]613// CHECK45-64-NEXT:    [[TMP14:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP28]]614// CHECK45-64-NEXT:    [[TMP15:%.*]] = load i32, ptr [[F_ADDR]], align 4, !llvm.access.group [[ACC_GRP28]]615// CHECK45-64-NEXT:    [[MUL8:%.*]] = mul nsw i32 [[TMP14]], [[TMP15]]616// CHECK45-64-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP13]], [[MUL8]]617// CHECK45-64-NEXT:    [[TMP16:%.*]] = load i32, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP28]]618// CHECK45-64-NEXT:    [[ADD10:%.*]] = add nsw i32 [[ADD9]], [[TMP16]]619// CHECK45-64-NEXT:    [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP28]]620// CHECK45-64-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64621// CHECK45-64-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]622// CHECK45-64-NEXT:    [[TMP18:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP28]]623// CHECK45-64-NEXT:    [[IDXPROM11:%.*]] = sext i32 [[TMP18]] to i64624// CHECK45-64-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM11]]625// CHECK45-64-NEXT:    store i32 [[ADD10]], ptr [[ARRAYIDX12]], align 4, !llvm.access.group [[ACC_GRP28]]626// CHECK45-64-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]627// CHECK45-64:       omp.body.continue:628// CHECK45-64-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]629// CHECK45-64:       omp.inner.for.inc:630// CHECK45-64-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]631// CHECK45-64-NEXT:    [[ADD13:%.*]] = add nsw i32 [[TMP19]], 1632// CHECK45-64-NEXT:    store i32 [[ADD13]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]633// CHECK45-64-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]634// CHECK45-64:       omp.inner.for.end:635// CHECK45-64-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]636// CHECK45-64:       omp.dispatch.inc:637// CHECK45-64-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4638// CHECK45-64-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4639// CHECK45-64-NEXT:    [[ADD14:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]640// CHECK45-64-NEXT:    store i32 [[ADD14]], ptr [[DOTOMP_LB]], align 4641// CHECK45-64-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4642// CHECK45-64-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4643// CHECK45-64-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]644// CHECK45-64-NEXT:    store i32 [[ADD15]], ptr [[DOTOMP_UB]], align 4645// CHECK45-64-NEXT:    br label [[OMP_DISPATCH_COND]]646// CHECK45-64:       omp.dispatch.end:647// CHECK45-64-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP2]])648// CHECK45-64-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4649// CHECK45-64-NEXT:    [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0650// CHECK45-64-NEXT:    br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]651// CHECK45-64:       .omp.final.then:652// CHECK45-64-NEXT:    store i32 10, ptr [[I]], align 4653// CHECK45-64-NEXT:    store i32 10, ptr [[J]], align 4654// CHECK45-64-NEXT:    br label [[DOTOMP_FINAL_DONE]]655// CHECK45-64:       .omp.final.done:656// CHECK45-64-NEXT:    ret void657//658//659// CHECK45-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34660// CHECK45-32-SAME: (ptr noalias [[DYN_PTR:%.*]], i32 [[N:%.*]], ptr nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[L:%.*]]) #[[ATTR0:[0-9]+]] {661// CHECK45-32-NEXT:  entry:662// CHECK45-32-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4663// CHECK45-32-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4664// CHECK45-32-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4665// CHECK45-32-NEXT:    [[L_ADDR:%.*]] = alloca i32, align 4666// CHECK45-32-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4667// CHECK45-32-NEXT:    [[L_CASTED:%.*]] = alloca i32, align 4668// CHECK45-32-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4669// CHECK45-32-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4670// CHECK45-32-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4671// CHECK45-32-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4672// CHECK45-32-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4673// CHECK45-32-NEXT:    store i32 [[L]], ptr [[L_ADDR]], align 4674// CHECK45-32-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4675// CHECK45-32-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_kernel_environment, ptr [[DYN_PTR]])676// CHECK45-32-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1677// CHECK45-32-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]678// CHECK45-32:       user_code.entry:679// CHECK45-32-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])680// CHECK45-32-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4681// CHECK45-32-NEXT:    store i32 [[TMP3]], ptr [[N_CASTED]], align 4682// CHECK45-32-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_CASTED]], align 4683// CHECK45-32-NEXT:    [[TMP5:%.*]] = load i32, ptr [[L_ADDR]], align 4684// CHECK45-32-NEXT:    store i32 [[TMP5]], ptr [[L_CASTED]], align 4685// CHECK45-32-NEXT:    [[TMP6:%.*]] = load i32, ptr [[L_CASTED]], align 4686// CHECK45-32-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 4687// CHECK45-32-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4688// CHECK45-32-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]], i32 [[TMP6]]) #[[ATTR2:[0-9]+]]689// CHECK45-32-NEXT:    call void @__kmpc_target_deinit()690// CHECK45-32-NEXT:    ret void691// CHECK45-32:       worker.exit:692// CHECK45-32-NEXT:    ret void693//694//695// CHECK45-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined696// CHECK45-32-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], ptr nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[L:%.*]]) #[[ATTR1:[0-9]+]] {697// CHECK45-32-NEXT:  entry:698// CHECK45-32-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4699// CHECK45-32-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4700// CHECK45-32-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4701// CHECK45-32-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4702// CHECK45-32-NEXT:    [[L_ADDR:%.*]] = alloca i32, align 4703// CHECK45-32-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4704// CHECK45-32-NEXT:    [[TMP:%.*]] = alloca i32, align 4705// CHECK45-32-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4706// CHECK45-32-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4707// CHECK45-32-NEXT:    [[I:%.*]] = alloca i32, align 4708// CHECK45-32-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4709// CHECK45-32-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4710// CHECK45-32-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4711// CHECK45-32-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4712// CHECK45-32-NEXT:    [[I3:%.*]] = alloca i32, align 4713// CHECK45-32-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4714// CHECK45-32-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4715// CHECK45-32-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4716// CHECK45-32-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4717// CHECK45-32-NEXT:    store i32 [[L]], ptr [[L_ADDR]], align 4718// CHECK45-32-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4719// CHECK45-32-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4720// CHECK45-32-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4721// CHECK45-32-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4722// CHECK45-32-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0723// CHECK45-32-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1724// CHECK45-32-NEXT:    [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1725// CHECK45-32-NEXT:    store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4726// CHECK45-32-NEXT:    store i32 0, ptr [[I]], align 4727// CHECK45-32-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4728// CHECK45-32-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]729// CHECK45-32-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]730// CHECK45-32:       omp.precond.then:731// CHECK45-32-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4732// CHECK45-32-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4733// CHECK45-32-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4734// CHECK45-32-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4735// CHECK45-32-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4736// CHECK45-32-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4737// CHECK45-32-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4738// CHECK45-32-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 128)739// CHECK45-32-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]740// CHECK45-32:       omp.dispatch.cond:741// CHECK45-32-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4742// CHECK45-32-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4743// CHECK45-32-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]]744// CHECK45-32-NEXT:    br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]745// CHECK45-32:       cond.true:746// CHECK45-32-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4747// CHECK45-32-NEXT:    br label [[COND_END:%.*]]748// CHECK45-32:       cond.false:749// CHECK45-32-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4750// CHECK45-32-NEXT:    br label [[COND_END]]751// CHECK45-32:       cond.end:752// CHECK45-32-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]753// CHECK45-32-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4754// CHECK45-32-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4755// CHECK45-32-NEXT:    store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4756// CHECK45-32-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4757// CHECK45-32-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4758// CHECK45-32-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]759// CHECK45-32-NEXT:    br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]760// CHECK45-32:       omp.dispatch.body:761// CHECK45-32-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]762// CHECK45-32:       omp.inner.for.cond:763// CHECK45-32-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]]764// CHECK45-32-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP18]]765// CHECK45-32-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]766// CHECK45-32-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]767// CHECK45-32:       omp.inner.for.body:768// CHECK45-32-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]769// CHECK45-32-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1770// CHECK45-32-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]771// CHECK45-32-NEXT:    store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP18]]772// CHECK45-32-NEXT:    [[TMP17:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP18]]773// CHECK45-32-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i32 0, i32 [[TMP17]]774// CHECK45-32-NEXT:    store i32 1, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP18]]775// CHECK45-32-NEXT:    [[TMP18:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP18]]776// CHECK45-32-NEXT:    store i32 [[TMP18]], ptr [[L_ADDR]], align 4, !llvm.access.group [[ACC_GRP18]]777// CHECK45-32-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]778// CHECK45-32:       omp.body.continue:779// CHECK45-32-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]780// CHECK45-32:       omp.inner.for.inc:781// CHECK45-32-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]782// CHECK45-32-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1783// CHECK45-32-NEXT:    store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]784// CHECK45-32-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]785// CHECK45-32:       omp.inner.for.end:786// CHECK45-32-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]787// CHECK45-32:       omp.dispatch.inc:788// CHECK45-32-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4789// CHECK45-32-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4790// CHECK45-32-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]791// CHECK45-32-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_LB]], align 4792// CHECK45-32-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4793// CHECK45-32-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4794// CHECK45-32-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]795// CHECK45-32-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_UB]], align 4796// CHECK45-32-NEXT:    br label [[OMP_DISPATCH_COND]]797// CHECK45-32:       omp.dispatch.end:798// CHECK45-32-NEXT:    [[TMP24:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4799// CHECK45-32-NEXT:    [[TMP25:%.*]] = load i32, ptr [[TMP24]], align 4800// CHECK45-32-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP25]])801// CHECK45-32-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4802// CHECK45-32-NEXT:    [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0803// CHECK45-32-NEXT:    br i1 [[TMP27]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]804// CHECK45-32:       .omp.final.then:805// CHECK45-32-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4806// CHECK45-32-NEXT:    [[SUB10:%.*]] = sub nsw i32 [[TMP28]], 0807// CHECK45-32-NEXT:    [[DIV11:%.*]] = sdiv i32 [[SUB10]], 1808// CHECK45-32-NEXT:    [[MUL12:%.*]] = mul nsw i32 [[DIV11]], 1809// CHECK45-32-NEXT:    [[ADD13:%.*]] = add nsw i32 0, [[MUL12]]810// CHECK45-32-NEXT:    store i32 [[ADD13]], ptr [[I3]], align 4811// CHECK45-32-NEXT:    br label [[DOTOMP_FINAL_DONE]]812// CHECK45-32:       .omp.final.done:813// CHECK45-32-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4814// CHECK45-32-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0815// CHECK45-32-NEXT:    br i1 [[TMP30]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]816// CHECK45-32:       .omp.lastprivate.then:817// CHECK45-32-NEXT:    [[TMP31:%.*]] = load i32, ptr [[L_ADDR]], align 4818// CHECK45-32-NEXT:    store i32 [[TMP31]], ptr [[L_ADDR]], align 4819// CHECK45-32-NEXT:    br label [[DOTOMP_LASTPRIVATE_DONE]]820// CHECK45-32:       .omp.lastprivate.done:821// CHECK45-32-NEXT:    br label [[OMP_PRECOND_END]]822// CHECK45-32:       omp.precond.end:823// CHECK45-32-NEXT:    ret void824//825//826// CHECK45-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l40827// CHECK45-32-SAME: (ptr noalias [[DYN_PTR:%.*]], i32 [[N:%.*]], ptr nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR3:[0-9]+]] {828// CHECK45-32-NEXT:  entry:829// CHECK45-32-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4830// CHECK45-32-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4831// CHECK45-32-NEXT:    [[AA_ADDR:%.*]] = alloca ptr, align 4832// CHECK45-32-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4833// CHECK45-32-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4834// CHECK45-32-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4835// CHECK45-32-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4836// CHECK45-32-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4837// CHECK45-32-NEXT:    store ptr [[AA]], ptr [[AA_ADDR]], align 4838// CHECK45-32-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4839// CHECK45-32-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l40_kernel_environment, ptr [[DYN_PTR]])840// CHECK45-32-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1841// CHECK45-32-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]842// CHECK45-32:       user_code.entry:843// CHECK45-32-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])844// CHECK45-32-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4845// CHECK45-32-NEXT:    store i32 [[TMP3]], ptr [[N_CASTED]], align 4846// CHECK45-32-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_CASTED]], align 4847// CHECK45-32-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 4848// CHECK45-32-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4849// CHECK45-32-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l40_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]]) #[[ATTR2]]850// CHECK45-32-NEXT:    call void @__kmpc_target_deinit()851// CHECK45-32-NEXT:    ret void852// CHECK45-32:       worker.exit:853// CHECK45-32-NEXT:    ret void854//855//856// CHECK45-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l40_omp_outlined857// CHECK45-32-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], ptr nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR1]] {858// CHECK45-32-NEXT:  entry:859// CHECK45-32-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4860// CHECK45-32-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4861// CHECK45-32-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4862// CHECK45-32-NEXT:    [[AA_ADDR:%.*]] = alloca ptr, align 4863// CHECK45-32-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4864// CHECK45-32-NEXT:    [[TMP:%.*]] = alloca i32, align 4865// CHECK45-32-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4866// CHECK45-32-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4867// CHECK45-32-NEXT:    [[I:%.*]] = alloca i32, align 4868// CHECK45-32-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4869// CHECK45-32-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4870// CHECK45-32-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4871// CHECK45-32-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4872// CHECK45-32-NEXT:    [[I3:%.*]] = alloca i32, align 4873// CHECK45-32-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4874// CHECK45-32-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4875// CHECK45-32-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4876// CHECK45-32-NEXT:    store ptr [[AA]], ptr [[AA_ADDR]], align 4877// CHECK45-32-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4878// CHECK45-32-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4879// CHECK45-32-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4880// CHECK45-32-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4881// CHECK45-32-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0882// CHECK45-32-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1883// CHECK45-32-NEXT:    [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1884// CHECK45-32-NEXT:    store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4885// CHECK45-32-NEXT:    store i32 0, ptr [[I]], align 4886// CHECK45-32-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4887// CHECK45-32-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]888// CHECK45-32-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]889// CHECK45-32:       omp.precond.then:890// CHECK45-32-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4891// CHECK45-32-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4892// CHECK45-32-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4893// CHECK45-32-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4894// CHECK45-32-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4895// CHECK45-32-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()896// CHECK45-32-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4897// CHECK45-32-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4898// CHECK45-32-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])899// CHECK45-32-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]900// CHECK45-32:       omp.dispatch.cond:901// CHECK45-32-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4902// CHECK45-32-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4903// CHECK45-32-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]]904// CHECK45-32-NEXT:    br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]905// CHECK45-32:       cond.true:906// CHECK45-32-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4907// CHECK45-32-NEXT:    br label [[COND_END:%.*]]908// CHECK45-32:       cond.false:909// CHECK45-32-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4910// CHECK45-32-NEXT:    br label [[COND_END]]911// CHECK45-32:       cond.end:912// CHECK45-32-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]913// CHECK45-32-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4914// CHECK45-32-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4915// CHECK45-32-NEXT:    store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4916// CHECK45-32-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4917// CHECK45-32-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4918// CHECK45-32-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]919// CHECK45-32-NEXT:    br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]920// CHECK45-32:       omp.dispatch.body:921// CHECK45-32-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]922// CHECK45-32:       omp.inner.for.cond:923// CHECK45-32-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22:![0-9]+]]924// CHECK45-32-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP22]]925// CHECK45-32-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]926// CHECK45-32-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]927// CHECK45-32:       omp.inner.for.body:928// CHECK45-32-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]929// CHECK45-32-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1930// CHECK45-32-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]931// CHECK45-32-NEXT:    store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP22]]932// CHECK45-32-NEXT:    [[TMP17:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP22]]933// CHECK45-32-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], i32 0, i32 [[TMP17]]934// CHECK45-32-NEXT:    [[TMP18:%.*]] = load i16, ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP22]]935// CHECK45-32-NEXT:    [[CONV:%.*]] = sext i16 [[TMP18]] to i32936// CHECK45-32-NEXT:    [[ADD7:%.*]] = add nsw i32 [[CONV]], 1937// CHECK45-32-NEXT:    [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16938// CHECK45-32-NEXT:    store i16 [[CONV8]], ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP22]]939// CHECK45-32-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]940// CHECK45-32:       omp.body.continue:941// CHECK45-32-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]942// CHECK45-32:       omp.inner.for.inc:943// CHECK45-32-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]944// CHECK45-32-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP19]], 1945// CHECK45-32-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]946// CHECK45-32-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]947// CHECK45-32:       omp.inner.for.end:948// CHECK45-32-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]949// CHECK45-32:       omp.dispatch.inc:950// CHECK45-32-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4951// CHECK45-32-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4952// CHECK45-32-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]953// CHECK45-32-NEXT:    store i32 [[ADD10]], ptr [[DOTOMP_LB]], align 4954// CHECK45-32-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4955// CHECK45-32-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4956// CHECK45-32-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]957// CHECK45-32-NEXT:    store i32 [[ADD11]], ptr [[DOTOMP_UB]], align 4958// CHECK45-32-NEXT:    br label [[OMP_DISPATCH_COND]]959// CHECK45-32:       omp.dispatch.end:960// CHECK45-32-NEXT:    [[TMP24:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4961// CHECK45-32-NEXT:    [[TMP25:%.*]] = load i32, ptr [[TMP24]], align 4962// CHECK45-32-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP25]])963// CHECK45-32-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4964// CHECK45-32-NEXT:    [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0965// CHECK45-32-NEXT:    br i1 [[TMP27]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]966// CHECK45-32:       .omp.final.then:967// CHECK45-32-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4968// CHECK45-32-NEXT:    [[SUB12:%.*]] = sub nsw i32 [[TMP28]], 0969// CHECK45-32-NEXT:    [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1970// CHECK45-32-NEXT:    [[MUL14:%.*]] = mul nsw i32 [[DIV13]], 1971// CHECK45-32-NEXT:    [[ADD15:%.*]] = add nsw i32 0, [[MUL14]]972// CHECK45-32-NEXT:    store i32 [[ADD15]], ptr [[I3]], align 4973// CHECK45-32-NEXT:    br label [[DOTOMP_FINAL_DONE]]974// CHECK45-32:       .omp.final.done:975// CHECK45-32-NEXT:    br label [[OMP_PRECOND_END]]976// CHECK45-32:       omp.precond.end:977// CHECK45-32-NEXT:    ret void978//979//980// CHECK45-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l45981// CHECK45-32-SAME: (ptr noalias [[DYN_PTR:%.*]], ptr nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {982// CHECK45-32-NEXT:  entry:983// CHECK45-32-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4984// CHECK45-32-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4985// CHECK45-32-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4986// CHECK45-32-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4987// CHECK45-32-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4988// CHECK45-32-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4989// CHECK45-32-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4990// CHECK45-32-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l45_kernel_environment, ptr [[DYN_PTR]])991// CHECK45-32-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1992// CHECK45-32-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]993// CHECK45-32:       user_code.entry:994// CHECK45-32-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])995// CHECK45-32-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 4996// CHECK45-32-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4997// CHECK45-32-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l45_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]]) #[[ATTR2]]998// CHECK45-32-NEXT:    call void @__kmpc_target_deinit()999// CHECK45-32-NEXT:    ret void1000// CHECK45-32:       worker.exit:1001// CHECK45-32-NEXT:    ret void1002//1003//1004// CHECK45-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l45_omp_outlined1005// CHECK45-32-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {1006// CHECK45-32-NEXT:  entry:1007// CHECK45-32-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 41008// CHECK45-32-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 41009// CHECK45-32-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 41010// CHECK45-32-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 41011// CHECK45-32-NEXT:    [[TMP:%.*]] = alloca i32, align 41012// CHECK45-32-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 41013// CHECK45-32-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 41014// CHECK45-32-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41015// CHECK45-32-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41016// CHECK45-32-NEXT:    [[I:%.*]] = alloca i32, align 41017// CHECK45-32-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 41018// CHECK45-32-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 41019// CHECK45-32-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 41020// CHECK45-32-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 41021// CHECK45-32-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 41022// CHECK45-32-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 41023// CHECK45-32-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 41024// CHECK45-32-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 41025// CHECK45-32-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()1026// CHECK45-32-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41027// CHECK45-32-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 41028// CHECK45-32-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])1029// CHECK45-32-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]1030// CHECK45-32:       omp.dispatch.cond:1031// CHECK45-32-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41032// CHECK45-32-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 91033// CHECK45-32-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1034// CHECK45-32:       cond.true:1035// CHECK45-32-NEXT:    br label [[COND_END:%.*]]1036// CHECK45-32:       cond.false:1037// CHECK45-32-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41038// CHECK45-32-NEXT:    br label [[COND_END]]1039// CHECK45-32:       cond.end:1040// CHECK45-32-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]1041// CHECK45-32-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 41042// CHECK45-32-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41043// CHECK45-32-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 41044// CHECK45-32-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41045// CHECK45-32-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41046// CHECK45-32-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]1047// CHECK45-32-NEXT:    br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]1048// CHECK45-32:       omp.dispatch.body:1049// CHECK45-32-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]1050// CHECK45-32:       omp.inner.for.cond:1051// CHECK45-32-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25:![0-9]+]]1052// CHECK45-32-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP25]]1053// CHECK45-32-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]1054// CHECK45-32-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1055// CHECK45-32:       omp.inner.for.body:1056// CHECK45-32-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]]1057// CHECK45-32-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP10]], 11058// CHECK45-32-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]1059// CHECK45-32-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP25]]1060// CHECK45-32-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP25]]1061// CHECK45-32-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP11]]1062// CHECK45-32-NEXT:    [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]]1063// CHECK45-32-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP12]], 11064// CHECK45-32-NEXT:    store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]]1065// CHECK45-32-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]1066// CHECK45-32:       omp.body.continue:1067// CHECK45-32-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]1068// CHECK45-32:       omp.inner.for.inc:1069// CHECK45-32-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]]1070// CHECK45-32-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP13]], 11071// CHECK45-32-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]]1072// CHECK45-32-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]1073// CHECK45-32:       omp.inner.for.end:1074// CHECK45-32-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]1075// CHECK45-32:       omp.dispatch.inc:1076// CHECK45-32-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41077// CHECK45-32-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 41078// CHECK45-32-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]1079// CHECK45-32-NEXT:    store i32 [[ADD5]], ptr [[DOTOMP_LB]], align 41080// CHECK45-32-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41081// CHECK45-32-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 41082// CHECK45-32-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]1083// CHECK45-32-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_UB]], align 41084// CHECK45-32-NEXT:    br label [[OMP_DISPATCH_COND]]1085// CHECK45-32:       omp.dispatch.end:1086// CHECK45-32-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP2]])1087// CHECK45-32-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 41088// CHECK45-32-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 01089// CHECK45-32-NEXT:    br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]1090// CHECK45-32:       .omp.final.then:1091// CHECK45-32-NEXT:    store i32 10, ptr [[I]], align 41092// CHECK45-32-NEXT:    br label [[DOTOMP_FINAL_DONE]]1093// CHECK45-32:       .omp.final.done:1094// CHECK45-32-NEXT:    ret void1095//1096//1097// CHECK45-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l501098// CHECK45-32-SAME: (ptr noalias [[DYN_PTR:%.*]], ptr nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[F:%.*]]) #[[ATTR0]] {1099// CHECK45-32-NEXT:  entry:1100// CHECK45-32-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 41101// CHECK45-32-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 41102// CHECK45-32-NEXT:    [[F_ADDR:%.*]] = alloca i32, align 41103// CHECK45-32-NEXT:    [[F_CASTED:%.*]] = alloca i32, align 41104// CHECK45-32-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 41105// CHECK45-32-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 41106// CHECK45-32-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 41107// CHECK45-32-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 41108// CHECK45-32-NEXT:    store i32 [[F]], ptr [[F_ADDR]], align 41109// CHECK45-32-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 41110// CHECK45-32-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l50_kernel_environment, ptr [[DYN_PTR]])1111// CHECK45-32-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -11112// CHECK45-32-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]1113// CHECK45-32:       user_code.entry:1114// CHECK45-32-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])1115// CHECK45-32-NEXT:    [[TMP3:%.*]] = load i32, ptr [[F_ADDR]], align 41116// CHECK45-32-NEXT:    store i32 [[TMP3]], ptr [[F_CASTED]], align 41117// CHECK45-32-NEXT:    [[TMP4:%.*]] = load i32, ptr [[F_CASTED]], align 41118// CHECK45-32-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 41119// CHECK45-32-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 41120// CHECK45-32-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l50_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i32 [[TMP4]]) #[[ATTR2]]1121// CHECK45-32-NEXT:    call void @__kmpc_target_deinit()1122// CHECK45-32-NEXT:    ret void1123// CHECK45-32:       worker.exit:1124// CHECK45-32-NEXT:    ret void1125//1126//1127// CHECK45-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l50_omp_outlined1128// CHECK45-32-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[F:%.*]]) #[[ATTR1]] {1129// CHECK45-32-NEXT:  entry:1130// CHECK45-32-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 41131// CHECK45-32-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 41132// CHECK45-32-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 41133// CHECK45-32-NEXT:    [[F_ADDR:%.*]] = alloca i32, align 41134// CHECK45-32-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 41135// CHECK45-32-NEXT:    [[TMP:%.*]] = alloca i32, align 41136// CHECK45-32-NEXT:    [[_TMP1:%.*]] = alloca i32, align 41137// CHECK45-32-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 41138// CHECK45-32-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 41139// CHECK45-32-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41140// CHECK45-32-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41141// CHECK45-32-NEXT:    [[K:%.*]] = alloca i32, align 41142// CHECK45-32-NEXT:    [[I:%.*]] = alloca i32, align 41143// CHECK45-32-NEXT:    [[J:%.*]] = alloca i32, align 41144// CHECK45-32-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 41145// CHECK45-32-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 41146// CHECK45-32-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 41147// CHECK45-32-NEXT:    store i32 [[F]], ptr [[F_ADDR]], align 41148// CHECK45-32-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 41149// CHECK45-32-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 41150// CHECK45-32-NEXT:    store i32 99, ptr [[DOTOMP_UB]], align 41151// CHECK45-32-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 41152// CHECK45-32-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 41153// CHECK45-32-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()1154// CHECK45-32-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41155// CHECK45-32-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 41156// CHECK45-32-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])1157// CHECK45-32-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]1158// CHECK45-32:       omp.dispatch.cond:1159// CHECK45-32-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41160// CHECK45-32-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 991161// CHECK45-32-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1162// CHECK45-32:       cond.true:1163// CHECK45-32-NEXT:    br label [[COND_END:%.*]]1164// CHECK45-32:       cond.false:1165// CHECK45-32-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41166// CHECK45-32-NEXT:    br label [[COND_END]]1167// CHECK45-32:       cond.end:1168// CHECK45-32-NEXT:    [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]1169// CHECK45-32-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 41170// CHECK45-32-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41171// CHECK45-32-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 41172// CHECK45-32-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41173// CHECK45-32-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41174// CHECK45-32-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]1175// CHECK45-32-NEXT:    br i1 [[CMP2]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]1176// CHECK45-32:       omp.dispatch.body:1177// CHECK45-32-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]1178// CHECK45-32:       omp.inner.for.cond:1179// CHECK45-32-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28:![0-9]+]]1180// CHECK45-32-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP28]]1181// CHECK45-32-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]1182// CHECK45-32-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1183// CHECK45-32:       omp.inner.for.body:1184// CHECK45-32-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]1185// CHECK45-32-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP10]], 101186// CHECK45-32-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 11187// CHECK45-32-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]1188// CHECK45-32-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP28]]1189// CHECK45-32-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]1190// CHECK45-32-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]1191// CHECK45-32-NEXT:    [[DIV4:%.*]] = sdiv i32 [[TMP12]], 101192// CHECK45-32-NEXT:    [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 101193// CHECK45-32-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL5]]1194// CHECK45-32-NEXT:    [[MUL6:%.*]] = mul nsw i32 [[SUB]], 11195// CHECK45-32-NEXT:    [[ADD7:%.*]] = add nsw i32 0, [[MUL6]]1196// CHECK45-32-NEXT:    store i32 [[ADD7]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP28]]1197// CHECK45-32-NEXT:    store i32 10, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP28]]1198// CHECK45-32-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP28]]1199// CHECK45-32-NEXT:    [[TMP14:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP28]]1200// CHECK45-32-NEXT:    [[TMP15:%.*]] = load i32, ptr [[F_ADDR]], align 4, !llvm.access.group [[ACC_GRP28]]1201// CHECK45-32-NEXT:    [[MUL8:%.*]] = mul nsw i32 [[TMP14]], [[TMP15]]1202// CHECK45-32-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP13]], [[MUL8]]1203// CHECK45-32-NEXT:    [[TMP16:%.*]] = load i32, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP28]]1204// CHECK45-32-NEXT:    [[ADD10:%.*]] = add nsw i32 [[ADD9]], [[TMP16]]1205// CHECK45-32-NEXT:    [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP28]]1206// CHECK45-32-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], i32 0, i32 [[TMP17]]1207// CHECK45-32-NEXT:    [[TMP18:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP28]]1208// CHECK45-32-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP18]]1209// CHECK45-32-NEXT:    store i32 [[ADD10]], ptr [[ARRAYIDX11]], align 4, !llvm.access.group [[ACC_GRP28]]1210// CHECK45-32-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]1211// CHECK45-32:       omp.body.continue:1212// CHECK45-32-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]1213// CHECK45-32:       omp.inner.for.inc:1214// CHECK45-32-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]1215// CHECK45-32-NEXT:    [[ADD12:%.*]] = add nsw i32 [[TMP19]], 11216// CHECK45-32-NEXT:    store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]1217// CHECK45-32-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]1218// CHECK45-32:       omp.inner.for.end:1219// CHECK45-32-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]1220// CHECK45-32:       omp.dispatch.inc:1221// CHECK45-32-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41222// CHECK45-32-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 41223// CHECK45-32-NEXT:    [[ADD13:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]1224// CHECK45-32-NEXT:    store i32 [[ADD13]], ptr [[DOTOMP_LB]], align 41225// CHECK45-32-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41226// CHECK45-32-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 41227// CHECK45-32-NEXT:    [[ADD14:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]1228// CHECK45-32-NEXT:    store i32 [[ADD14]], ptr [[DOTOMP_UB]], align 41229// CHECK45-32-NEXT:    br label [[OMP_DISPATCH_COND]]1230// CHECK45-32:       omp.dispatch.end:1231// CHECK45-32-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP2]])1232// CHECK45-32-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 41233// CHECK45-32-NEXT:    [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 01234// CHECK45-32-NEXT:    br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]1235// CHECK45-32:       .omp.final.then:1236// CHECK45-32-NEXT:    store i32 10, ptr [[I]], align 41237// CHECK45-32-NEXT:    store i32 10, ptr [[J]], align 41238// CHECK45-32-NEXT:    br label [[DOTOMP_FINAL_DONE]]1239// CHECK45-32:       .omp.final.done:1240// CHECK45-32-NEXT:    ret void1241//1242//1243// CHECK45-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l341244// CHECK45-32-EX-SAME: (ptr noalias [[DYN_PTR:%.*]], i32 [[N:%.*]], ptr nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[L:%.*]]) #[[ATTR0:[0-9]+]] {1245// CHECK45-32-EX-NEXT:  entry:1246// CHECK45-32-EX-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 41247// CHECK45-32-EX-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 41248// CHECK45-32-EX-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 41249// CHECK45-32-EX-NEXT:    [[L_ADDR:%.*]] = alloca i32, align 41250// CHECK45-32-EX-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 41251// CHECK45-32-EX-NEXT:    [[L_CASTED:%.*]] = alloca i32, align 41252// CHECK45-32-EX-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 41253// CHECK45-32-EX-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 41254// CHECK45-32-EX-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 41255// CHECK45-32-EX-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 41256// CHECK45-32-EX-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 41257// CHECK45-32-EX-NEXT:    store i32 [[L]], ptr [[L_ADDR]], align 41258// CHECK45-32-EX-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 41259// CHECK45-32-EX-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_kernel_environment, ptr [[DYN_PTR]])1260// CHECK45-32-EX-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -11261// CHECK45-32-EX-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]1262// CHECK45-32-EX:       user_code.entry:1263// CHECK45-32-EX-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])1264// CHECK45-32-EX-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 41265// CHECK45-32-EX-NEXT:    store i32 [[TMP3]], ptr [[N_CASTED]], align 41266// CHECK45-32-EX-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_CASTED]], align 41267// CHECK45-32-EX-NEXT:    [[TMP5:%.*]] = load i32, ptr [[L_ADDR]], align 41268// CHECK45-32-EX-NEXT:    store i32 [[TMP5]], ptr [[L_CASTED]], align 41269// CHECK45-32-EX-NEXT:    [[TMP6:%.*]] = load i32, ptr [[L_CASTED]], align 41270// CHECK45-32-EX-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 41271// CHECK45-32-EX-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 41272// CHECK45-32-EX-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]], i32 [[TMP6]]) #[[ATTR2:[0-9]+]]1273// CHECK45-32-EX-NEXT:    call void @__kmpc_target_deinit()1274// CHECK45-32-EX-NEXT:    ret void1275// CHECK45-32-EX:       worker.exit:1276// CHECK45-32-EX-NEXT:    ret void1277//1278//1279// CHECK45-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined1280// CHECK45-32-EX-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], ptr nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[L:%.*]]) #[[ATTR1:[0-9]+]] {1281// CHECK45-32-EX-NEXT:  entry:1282// CHECK45-32-EX-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 41283// CHECK45-32-EX-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 41284// CHECK45-32-EX-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 41285// CHECK45-32-EX-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 41286// CHECK45-32-EX-NEXT:    [[L_ADDR:%.*]] = alloca i32, align 41287// CHECK45-32-EX-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 41288// CHECK45-32-EX-NEXT:    [[TMP:%.*]] = alloca i32, align 41289// CHECK45-32-EX-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 41290// CHECK45-32-EX-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 41291// CHECK45-32-EX-NEXT:    [[I:%.*]] = alloca i32, align 41292// CHECK45-32-EX-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 41293// CHECK45-32-EX-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 41294// CHECK45-32-EX-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41295// CHECK45-32-EX-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41296// CHECK45-32-EX-NEXT:    [[I3:%.*]] = alloca i32, align 41297// CHECK45-32-EX-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 41298// CHECK45-32-EX-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 41299// CHECK45-32-EX-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 41300// CHECK45-32-EX-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 41301// CHECK45-32-EX-NEXT:    store i32 [[L]], ptr [[L_ADDR]], align 41302// CHECK45-32-EX-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 41303// CHECK45-32-EX-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 41304// CHECK45-32-EX-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 41305// CHECK45-32-EX-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41306// CHECK45-32-EX-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 01307// CHECK45-32-EX-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 11308// CHECK45-32-EX-NEXT:    [[SUB2:%.*]] = sub nsw i32 [[DIV]], 11309// CHECK45-32-EX-NEXT:    store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 41310// CHECK45-32-EX-NEXT:    store i32 0, ptr [[I]], align 41311// CHECK45-32-EX-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41312// CHECK45-32-EX-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]1313// CHECK45-32-EX-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]1314// CHECK45-32-EX:       omp.precond.then:1315// CHECK45-32-EX-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 41316// CHECK45-32-EX-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 41317// CHECK45-32-EX-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 41318// CHECK45-32-EX-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 41319// CHECK45-32-EX-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 41320// CHECK45-32-EX-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41321// CHECK45-32-EX-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 41322// CHECK45-32-EX-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 128)1323// CHECK45-32-EX-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]1324// CHECK45-32-EX:       omp.dispatch.cond:1325// CHECK45-32-EX-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41326// CHECK45-32-EX-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 41327// CHECK45-32-EX-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]]1328// CHECK45-32-EX-NEXT:    br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1329// CHECK45-32-EX:       cond.true:1330// CHECK45-32-EX-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 41331// CHECK45-32-EX-NEXT:    br label [[COND_END:%.*]]1332// CHECK45-32-EX:       cond.false:1333// CHECK45-32-EX-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41334// CHECK45-32-EX-NEXT:    br label [[COND_END]]1335// CHECK45-32-EX:       cond.end:1336// CHECK45-32-EX-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]1337// CHECK45-32-EX-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 41338// CHECK45-32-EX-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41339// CHECK45-32-EX-NEXT:    store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 41340// CHECK45-32-EX-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41341// CHECK45-32-EX-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41342// CHECK45-32-EX-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]1343// CHECK45-32-EX-NEXT:    br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]1344// CHECK45-32-EX:       omp.dispatch.body:1345// CHECK45-32-EX-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]1346// CHECK45-32-EX:       omp.inner.for.cond:1347// CHECK45-32-EX-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]]1348// CHECK45-32-EX-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP18]]1349// CHECK45-32-EX-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]1350// CHECK45-32-EX-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1351// CHECK45-32-EX:       omp.inner.for.body:1352// CHECK45-32-EX-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]1353// CHECK45-32-EX-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP16]], 11354// CHECK45-32-EX-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]1355// CHECK45-32-EX-NEXT:    store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP18]]1356// CHECK45-32-EX-NEXT:    [[TMP17:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP18]]1357// CHECK45-32-EX-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i32 0, i32 [[TMP17]]1358// CHECK45-32-EX-NEXT:    store i32 1, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP18]]1359// CHECK45-32-EX-NEXT:    [[TMP18:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP18]]1360// CHECK45-32-EX-NEXT:    store i32 [[TMP18]], ptr [[L_ADDR]], align 4, !llvm.access.group [[ACC_GRP18]]1361// CHECK45-32-EX-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]1362// CHECK45-32-EX:       omp.body.continue:1363// CHECK45-32-EX-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]1364// CHECK45-32-EX:       omp.inner.for.inc:1365// CHECK45-32-EX-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]1366// CHECK45-32-EX-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP19]], 11367// CHECK45-32-EX-NEXT:    store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]1368// CHECK45-32-EX-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]1369// CHECK45-32-EX:       omp.inner.for.end:1370// CHECK45-32-EX-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]1371// CHECK45-32-EX:       omp.dispatch.inc:1372// CHECK45-32-EX-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41373// CHECK45-32-EX-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 41374// CHECK45-32-EX-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]1375// CHECK45-32-EX-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_LB]], align 41376// CHECK45-32-EX-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41377// CHECK45-32-EX-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 41378// CHECK45-32-EX-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]1379// CHECK45-32-EX-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_UB]], align 41380// CHECK45-32-EX-NEXT:    br label [[OMP_DISPATCH_COND]]1381// CHECK45-32-EX:       omp.dispatch.end:1382// CHECK45-32-EX-NEXT:    [[TMP24:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41383// CHECK45-32-EX-NEXT:    [[TMP25:%.*]] = load i32, ptr [[TMP24]], align 41384// CHECK45-32-EX-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP25]])1385// CHECK45-32-EX-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 41386// CHECK45-32-EX-NEXT:    [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 01387// CHECK45-32-EX-NEXT:    br i1 [[TMP27]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]1388// CHECK45-32-EX:       .omp.final.then:1389// CHECK45-32-EX-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41390// CHECK45-32-EX-NEXT:    [[SUB10:%.*]] = sub nsw i32 [[TMP28]], 01391// CHECK45-32-EX-NEXT:    [[DIV11:%.*]] = sdiv i32 [[SUB10]], 11392// CHECK45-32-EX-NEXT:    [[MUL12:%.*]] = mul nsw i32 [[DIV11]], 11393// CHECK45-32-EX-NEXT:    [[ADD13:%.*]] = add nsw i32 0, [[MUL12]]1394// CHECK45-32-EX-NEXT:    store i32 [[ADD13]], ptr [[I3]], align 41395// CHECK45-32-EX-NEXT:    br label [[DOTOMP_FINAL_DONE]]1396// CHECK45-32-EX:       .omp.final.done:1397// CHECK45-32-EX-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 41398// CHECK45-32-EX-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 01399// CHECK45-32-EX-NEXT:    br i1 [[TMP30]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]1400// CHECK45-32-EX:       .omp.lastprivate.then:1401// CHECK45-32-EX-NEXT:    [[TMP31:%.*]] = load i32, ptr [[L_ADDR]], align 41402// CHECK45-32-EX-NEXT:    store i32 [[TMP31]], ptr [[L_ADDR]], align 41403// CHECK45-32-EX-NEXT:    br label [[DOTOMP_LASTPRIVATE_DONE]]1404// CHECK45-32-EX:       .omp.lastprivate.done:1405// CHECK45-32-EX-NEXT:    br label [[OMP_PRECOND_END]]1406// CHECK45-32-EX:       omp.precond.end:1407// CHECK45-32-EX-NEXT:    ret void1408//1409//1410// CHECK45-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l401411// CHECK45-32-EX-SAME: (ptr noalias [[DYN_PTR:%.*]], i32 [[N:%.*]], ptr nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR3:[0-9]+]] {1412// CHECK45-32-EX-NEXT:  entry:1413// CHECK45-32-EX-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 41414// CHECK45-32-EX-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 41415// CHECK45-32-EX-NEXT:    [[AA_ADDR:%.*]] = alloca ptr, align 41416// CHECK45-32-EX-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 41417// CHECK45-32-EX-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 41418// CHECK45-32-EX-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 41419// CHECK45-32-EX-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 41420// CHECK45-32-EX-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 41421// CHECK45-32-EX-NEXT:    store ptr [[AA]], ptr [[AA_ADDR]], align 41422// CHECK45-32-EX-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 41423// CHECK45-32-EX-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l40_kernel_environment, ptr [[DYN_PTR]])1424// CHECK45-32-EX-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -11425// CHECK45-32-EX-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]1426// CHECK45-32-EX:       user_code.entry:1427// CHECK45-32-EX-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])1428// CHECK45-32-EX-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 41429// CHECK45-32-EX-NEXT:    store i32 [[TMP3]], ptr [[N_CASTED]], align 41430// CHECK45-32-EX-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_CASTED]], align 41431// CHECK45-32-EX-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 41432// CHECK45-32-EX-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 41433// CHECK45-32-EX-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l40_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]]) #[[ATTR2]]1434// CHECK45-32-EX-NEXT:    call void @__kmpc_target_deinit()1435// CHECK45-32-EX-NEXT:    ret void1436// CHECK45-32-EX:       worker.exit:1437// CHECK45-32-EX-NEXT:    ret void1438//1439//1440// CHECK45-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l40_omp_outlined1441// CHECK45-32-EX-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], ptr nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR1]] {1442// CHECK45-32-EX-NEXT:  entry:1443// CHECK45-32-EX-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 41444// CHECK45-32-EX-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 41445// CHECK45-32-EX-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 41446// CHECK45-32-EX-NEXT:    [[AA_ADDR:%.*]] = alloca ptr, align 41447// CHECK45-32-EX-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 41448// CHECK45-32-EX-NEXT:    [[TMP:%.*]] = alloca i32, align 41449// CHECK45-32-EX-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 41450// CHECK45-32-EX-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 41451// CHECK45-32-EX-NEXT:    [[I:%.*]] = alloca i32, align 41452// CHECK45-32-EX-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 41453// CHECK45-32-EX-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 41454// CHECK45-32-EX-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41455// CHECK45-32-EX-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41456// CHECK45-32-EX-NEXT:    [[I3:%.*]] = alloca i32, align 41457// CHECK45-32-EX-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 41458// CHECK45-32-EX-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 41459// CHECK45-32-EX-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 41460// CHECK45-32-EX-NEXT:    store ptr [[AA]], ptr [[AA_ADDR]], align 41461// CHECK45-32-EX-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 41462// CHECK45-32-EX-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 41463// CHECK45-32-EX-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 41464// CHECK45-32-EX-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41465// CHECK45-32-EX-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 01466// CHECK45-32-EX-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 11467// CHECK45-32-EX-NEXT:    [[SUB2:%.*]] = sub nsw i32 [[DIV]], 11468// CHECK45-32-EX-NEXT:    store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 41469// CHECK45-32-EX-NEXT:    store i32 0, ptr [[I]], align 41470// CHECK45-32-EX-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41471// CHECK45-32-EX-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]1472// CHECK45-32-EX-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]1473// CHECK45-32-EX:       omp.precond.then:1474// CHECK45-32-EX-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 41475// CHECK45-32-EX-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 41476// CHECK45-32-EX-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 41477// CHECK45-32-EX-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 41478// CHECK45-32-EX-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 41479// CHECK45-32-EX-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()1480// CHECK45-32-EX-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41481// CHECK45-32-EX-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 41482// CHECK45-32-EX-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])1483// CHECK45-32-EX-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]1484// CHECK45-32-EX:       omp.dispatch.cond:1485// CHECK45-32-EX-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41486// CHECK45-32-EX-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 41487// CHECK45-32-EX-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]]1488// CHECK45-32-EX-NEXT:    br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1489// CHECK45-32-EX:       cond.true:1490// CHECK45-32-EX-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 41491// CHECK45-32-EX-NEXT:    br label [[COND_END:%.*]]1492// CHECK45-32-EX:       cond.false:1493// CHECK45-32-EX-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41494// CHECK45-32-EX-NEXT:    br label [[COND_END]]1495// CHECK45-32-EX:       cond.end:1496// CHECK45-32-EX-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]1497// CHECK45-32-EX-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 41498// CHECK45-32-EX-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41499// CHECK45-32-EX-NEXT:    store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 41500// CHECK45-32-EX-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41501// CHECK45-32-EX-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41502// CHECK45-32-EX-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]1503// CHECK45-32-EX-NEXT:    br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]1504// CHECK45-32-EX:       omp.dispatch.body:1505// CHECK45-32-EX-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]1506// CHECK45-32-EX:       omp.inner.for.cond:1507// CHECK45-32-EX-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22:![0-9]+]]1508// CHECK45-32-EX-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP22]]1509// CHECK45-32-EX-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]1510// CHECK45-32-EX-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1511// CHECK45-32-EX:       omp.inner.for.body:1512// CHECK45-32-EX-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]1513// CHECK45-32-EX-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP16]], 11514// CHECK45-32-EX-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]1515// CHECK45-32-EX-NEXT:    store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP22]]1516// CHECK45-32-EX-NEXT:    [[TMP17:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP22]]1517// CHECK45-32-EX-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], i32 0, i32 [[TMP17]]1518// CHECK45-32-EX-NEXT:    [[TMP18:%.*]] = load i16, ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP22]]1519// CHECK45-32-EX-NEXT:    [[CONV:%.*]] = sext i16 [[TMP18]] to i321520// CHECK45-32-EX-NEXT:    [[ADD7:%.*]] = add nsw i32 [[CONV]], 11521// CHECK45-32-EX-NEXT:    [[CONV8:%.*]] = trunc i32 [[ADD7]] to i161522// CHECK45-32-EX-NEXT:    store i16 [[CONV8]], ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP22]]1523// CHECK45-32-EX-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]1524// CHECK45-32-EX:       omp.body.continue:1525// CHECK45-32-EX-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]1526// CHECK45-32-EX:       omp.inner.for.inc:1527// CHECK45-32-EX-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]1528// CHECK45-32-EX-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP19]], 11529// CHECK45-32-EX-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]1530// CHECK45-32-EX-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]1531// CHECK45-32-EX:       omp.inner.for.end:1532// CHECK45-32-EX-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]1533// CHECK45-32-EX:       omp.dispatch.inc:1534// CHECK45-32-EX-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41535// CHECK45-32-EX-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 41536// CHECK45-32-EX-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]1537// CHECK45-32-EX-NEXT:    store i32 [[ADD10]], ptr [[DOTOMP_LB]], align 41538// CHECK45-32-EX-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41539// CHECK45-32-EX-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 41540// CHECK45-32-EX-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]1541// CHECK45-32-EX-NEXT:    store i32 [[ADD11]], ptr [[DOTOMP_UB]], align 41542// CHECK45-32-EX-NEXT:    br label [[OMP_DISPATCH_COND]]1543// CHECK45-32-EX:       omp.dispatch.end:1544// CHECK45-32-EX-NEXT:    [[TMP24:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41545// CHECK45-32-EX-NEXT:    [[TMP25:%.*]] = load i32, ptr [[TMP24]], align 41546// CHECK45-32-EX-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP25]])1547// CHECK45-32-EX-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 41548// CHECK45-32-EX-NEXT:    [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 01549// CHECK45-32-EX-NEXT:    br i1 [[TMP27]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]1550// CHECK45-32-EX:       .omp.final.then:1551// CHECK45-32-EX-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41552// CHECK45-32-EX-NEXT:    [[SUB12:%.*]] = sub nsw i32 [[TMP28]], 01553// CHECK45-32-EX-NEXT:    [[DIV13:%.*]] = sdiv i32 [[SUB12]], 11554// CHECK45-32-EX-NEXT:    [[MUL14:%.*]] = mul nsw i32 [[DIV13]], 11555// CHECK45-32-EX-NEXT:    [[ADD15:%.*]] = add nsw i32 0, [[MUL14]]1556// CHECK45-32-EX-NEXT:    store i32 [[ADD15]], ptr [[I3]], align 41557// CHECK45-32-EX-NEXT:    br label [[DOTOMP_FINAL_DONE]]1558// CHECK45-32-EX:       .omp.final.done:1559// CHECK45-32-EX-NEXT:    br label [[OMP_PRECOND_END]]1560// CHECK45-32-EX:       omp.precond.end:1561// CHECK45-32-EX-NEXT:    ret void1562//1563//1564// CHECK45-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l451565// CHECK45-32-EX-SAME: (ptr noalias [[DYN_PTR:%.*]], ptr nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {1566// CHECK45-32-EX-NEXT:  entry:1567// CHECK45-32-EX-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 41568// CHECK45-32-EX-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 41569// CHECK45-32-EX-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 41570// CHECK45-32-EX-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 41571// CHECK45-32-EX-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 41572// CHECK45-32-EX-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 41573// CHECK45-32-EX-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 41574// CHECK45-32-EX-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l45_kernel_environment, ptr [[DYN_PTR]])1575// CHECK45-32-EX-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -11576// CHECK45-32-EX-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]1577// CHECK45-32-EX:       user_code.entry:1578// CHECK45-32-EX-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])1579// CHECK45-32-EX-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 41580// CHECK45-32-EX-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 41581// CHECK45-32-EX-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l45_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]]) #[[ATTR2]]1582// CHECK45-32-EX-NEXT:    call void @__kmpc_target_deinit()1583// CHECK45-32-EX-NEXT:    ret void1584// CHECK45-32-EX:       worker.exit:1585// CHECK45-32-EX-NEXT:    ret void1586//1587//1588// CHECK45-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l45_omp_outlined1589// CHECK45-32-EX-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {1590// CHECK45-32-EX-NEXT:  entry:1591// CHECK45-32-EX-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 41592// CHECK45-32-EX-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 41593// CHECK45-32-EX-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 41594// CHECK45-32-EX-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 41595// CHECK45-32-EX-NEXT:    [[TMP:%.*]] = alloca i32, align 41596// CHECK45-32-EX-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 41597// CHECK45-32-EX-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 41598// CHECK45-32-EX-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41599// CHECK45-32-EX-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41600// CHECK45-32-EX-NEXT:    [[I:%.*]] = alloca i32, align 41601// CHECK45-32-EX-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 41602// CHECK45-32-EX-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 41603// CHECK45-32-EX-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 41604// CHECK45-32-EX-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 41605// CHECK45-32-EX-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 41606// CHECK45-32-EX-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 41607// CHECK45-32-EX-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 41608// CHECK45-32-EX-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 41609// CHECK45-32-EX-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()1610// CHECK45-32-EX-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41611// CHECK45-32-EX-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 41612// CHECK45-32-EX-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])1613// CHECK45-32-EX-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]1614// CHECK45-32-EX:       omp.dispatch.cond:1615// CHECK45-32-EX-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41616// CHECK45-32-EX-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 91617// CHECK45-32-EX-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1618// CHECK45-32-EX:       cond.true:1619// CHECK45-32-EX-NEXT:    br label [[COND_END:%.*]]1620// CHECK45-32-EX:       cond.false:1621// CHECK45-32-EX-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41622// CHECK45-32-EX-NEXT:    br label [[COND_END]]1623// CHECK45-32-EX:       cond.end:1624// CHECK45-32-EX-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]1625// CHECK45-32-EX-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 41626// CHECK45-32-EX-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41627// CHECK45-32-EX-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 41628// CHECK45-32-EX-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41629// CHECK45-32-EX-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41630// CHECK45-32-EX-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]1631// CHECK45-32-EX-NEXT:    br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]1632// CHECK45-32-EX:       omp.dispatch.body:1633// CHECK45-32-EX-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]1634// CHECK45-32-EX:       omp.inner.for.cond:1635// CHECK45-32-EX-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25:![0-9]+]]1636// CHECK45-32-EX-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP25]]1637// CHECK45-32-EX-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]1638// CHECK45-32-EX-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1639// CHECK45-32-EX:       omp.inner.for.body:1640// CHECK45-32-EX-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]]1641// CHECK45-32-EX-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP10]], 11642// CHECK45-32-EX-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]1643// CHECK45-32-EX-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP25]]1644// CHECK45-32-EX-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP25]]1645// CHECK45-32-EX-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP11]]1646// CHECK45-32-EX-NEXT:    [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]]1647// CHECK45-32-EX-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP12]], 11648// CHECK45-32-EX-NEXT:    store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]]1649// CHECK45-32-EX-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]1650// CHECK45-32-EX:       omp.body.continue:1651// CHECK45-32-EX-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]1652// CHECK45-32-EX:       omp.inner.for.inc:1653// CHECK45-32-EX-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]]1654// CHECK45-32-EX-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP13]], 11655// CHECK45-32-EX-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]]1656// CHECK45-32-EX-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]1657// CHECK45-32-EX:       omp.inner.for.end:1658// CHECK45-32-EX-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]1659// CHECK45-32-EX:       omp.dispatch.inc:1660// CHECK45-32-EX-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41661// CHECK45-32-EX-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 41662// CHECK45-32-EX-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]1663// CHECK45-32-EX-NEXT:    store i32 [[ADD5]], ptr [[DOTOMP_LB]], align 41664// CHECK45-32-EX-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41665// CHECK45-32-EX-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 41666// CHECK45-32-EX-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]1667// CHECK45-32-EX-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_UB]], align 41668// CHECK45-32-EX-NEXT:    br label [[OMP_DISPATCH_COND]]1669// CHECK45-32-EX:       omp.dispatch.end:1670// CHECK45-32-EX-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP2]])1671// CHECK45-32-EX-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 41672// CHECK45-32-EX-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 01673// CHECK45-32-EX-NEXT:    br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]1674// CHECK45-32-EX:       .omp.final.then:1675// CHECK45-32-EX-NEXT:    store i32 10, ptr [[I]], align 41676// CHECK45-32-EX-NEXT:    br label [[DOTOMP_FINAL_DONE]]1677// CHECK45-32-EX:       .omp.final.done:1678// CHECK45-32-EX-NEXT:    ret void1679//1680//1681// CHECK45-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l501682// CHECK45-32-EX-SAME: (ptr noalias [[DYN_PTR:%.*]], ptr nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[F:%.*]]) #[[ATTR0]] {1683// CHECK45-32-EX-NEXT:  entry:1684// CHECK45-32-EX-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 41685// CHECK45-32-EX-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 41686// CHECK45-32-EX-NEXT:    [[F_ADDR:%.*]] = alloca i32, align 41687// CHECK45-32-EX-NEXT:    [[F_CASTED:%.*]] = alloca i32, align 41688// CHECK45-32-EX-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 41689// CHECK45-32-EX-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 41690// CHECK45-32-EX-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 41691// CHECK45-32-EX-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 41692// CHECK45-32-EX-NEXT:    store i32 [[F]], ptr [[F_ADDR]], align 41693// CHECK45-32-EX-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 41694// CHECK45-32-EX-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l50_kernel_environment, ptr [[DYN_PTR]])1695// CHECK45-32-EX-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -11696// CHECK45-32-EX-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]1697// CHECK45-32-EX:       user_code.entry:1698// CHECK45-32-EX-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])1699// CHECK45-32-EX-NEXT:    [[TMP3:%.*]] = load i32, ptr [[F_ADDR]], align 41700// CHECK45-32-EX-NEXT:    store i32 [[TMP3]], ptr [[F_CASTED]], align 41701// CHECK45-32-EX-NEXT:    [[TMP4:%.*]] = load i32, ptr [[F_CASTED]], align 41702// CHECK45-32-EX-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 41703// CHECK45-32-EX-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 41704// CHECK45-32-EX-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l50_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i32 [[TMP4]]) #[[ATTR2]]1705// CHECK45-32-EX-NEXT:    call void @__kmpc_target_deinit()1706// CHECK45-32-EX-NEXT:    ret void1707// CHECK45-32-EX:       worker.exit:1708// CHECK45-32-EX-NEXT:    ret void1709//1710//1711// CHECK45-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l50_omp_outlined1712// CHECK45-32-EX-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[F:%.*]]) #[[ATTR1]] {1713// CHECK45-32-EX-NEXT:  entry:1714// CHECK45-32-EX-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 41715// CHECK45-32-EX-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 41716// CHECK45-32-EX-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 41717// CHECK45-32-EX-NEXT:    [[F_ADDR:%.*]] = alloca i32, align 41718// CHECK45-32-EX-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 41719// CHECK45-32-EX-NEXT:    [[TMP:%.*]] = alloca i32, align 41720// CHECK45-32-EX-NEXT:    [[_TMP1:%.*]] = alloca i32, align 41721// CHECK45-32-EX-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 41722// CHECK45-32-EX-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 41723// CHECK45-32-EX-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41724// CHECK45-32-EX-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41725// CHECK45-32-EX-NEXT:    [[K:%.*]] = alloca i32, align 41726// CHECK45-32-EX-NEXT:    [[I:%.*]] = alloca i32, align 41727// CHECK45-32-EX-NEXT:    [[J:%.*]] = alloca i32, align 41728// CHECK45-32-EX-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 41729// CHECK45-32-EX-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 41730// CHECK45-32-EX-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 41731// CHECK45-32-EX-NEXT:    store i32 [[F]], ptr [[F_ADDR]], align 41732// CHECK45-32-EX-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 41733// CHECK45-32-EX-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 41734// CHECK45-32-EX-NEXT:    store i32 99, ptr [[DOTOMP_UB]], align 41735// CHECK45-32-EX-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 41736// CHECK45-32-EX-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 41737// CHECK45-32-EX-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()1738// CHECK45-32-EX-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41739// CHECK45-32-EX-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 41740// CHECK45-32-EX-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])1741// CHECK45-32-EX-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]1742// CHECK45-32-EX:       omp.dispatch.cond:1743// CHECK45-32-EX-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41744// CHECK45-32-EX-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 991745// CHECK45-32-EX-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1746// CHECK45-32-EX:       cond.true:1747// CHECK45-32-EX-NEXT:    br label [[COND_END:%.*]]1748// CHECK45-32-EX:       cond.false:1749// CHECK45-32-EX-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41750// CHECK45-32-EX-NEXT:    br label [[COND_END]]1751// CHECK45-32-EX:       cond.end:1752// CHECK45-32-EX-NEXT:    [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]1753// CHECK45-32-EX-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 41754// CHECK45-32-EX-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41755// CHECK45-32-EX-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 41756// CHECK45-32-EX-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41757// CHECK45-32-EX-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41758// CHECK45-32-EX-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]1759// CHECK45-32-EX-NEXT:    br i1 [[CMP2]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]1760// CHECK45-32-EX:       omp.dispatch.body:1761// CHECK45-32-EX-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]1762// CHECK45-32-EX:       omp.inner.for.cond:1763// CHECK45-32-EX-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28:![0-9]+]]1764// CHECK45-32-EX-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP28]]1765// CHECK45-32-EX-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]1766// CHECK45-32-EX-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1767// CHECK45-32-EX:       omp.inner.for.body:1768// CHECK45-32-EX-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]1769// CHECK45-32-EX-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP10]], 101770// CHECK45-32-EX-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 11771// CHECK45-32-EX-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]1772// CHECK45-32-EX-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP28]]1773// CHECK45-32-EX-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]1774// CHECK45-32-EX-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]1775// CHECK45-32-EX-NEXT:    [[DIV4:%.*]] = sdiv i32 [[TMP12]], 101776// CHECK45-32-EX-NEXT:    [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 101777// CHECK45-32-EX-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL5]]1778// CHECK45-32-EX-NEXT:    [[MUL6:%.*]] = mul nsw i32 [[SUB]], 11779// CHECK45-32-EX-NEXT:    [[ADD7:%.*]] = add nsw i32 0, [[MUL6]]1780// CHECK45-32-EX-NEXT:    store i32 [[ADD7]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP28]]1781// CHECK45-32-EX-NEXT:    store i32 10, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP28]]1782// CHECK45-32-EX-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP28]]1783// CHECK45-32-EX-NEXT:    [[TMP14:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP28]]1784// CHECK45-32-EX-NEXT:    [[TMP15:%.*]] = load i32, ptr [[F_ADDR]], align 4, !llvm.access.group [[ACC_GRP28]]1785// CHECK45-32-EX-NEXT:    [[MUL8:%.*]] = mul nsw i32 [[TMP14]], [[TMP15]]1786// CHECK45-32-EX-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP13]], [[MUL8]]1787// CHECK45-32-EX-NEXT:    [[TMP16:%.*]] = load i32, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP28]]1788// CHECK45-32-EX-NEXT:    [[ADD10:%.*]] = add nsw i32 [[ADD9]], [[TMP16]]1789// CHECK45-32-EX-NEXT:    [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP28]]1790// CHECK45-32-EX-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], i32 0, i32 [[TMP17]]1791// CHECK45-32-EX-NEXT:    [[TMP18:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP28]]1792// CHECK45-32-EX-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP18]]1793// CHECK45-32-EX-NEXT:    store i32 [[ADD10]], ptr [[ARRAYIDX11]], align 4, !llvm.access.group [[ACC_GRP28]]1794// CHECK45-32-EX-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]1795// CHECK45-32-EX:       omp.body.continue:1796// CHECK45-32-EX-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]1797// CHECK45-32-EX:       omp.inner.for.inc:1798// CHECK45-32-EX-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]1799// CHECK45-32-EX-NEXT:    [[ADD12:%.*]] = add nsw i32 [[TMP19]], 11800// CHECK45-32-EX-NEXT:    store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]1801// CHECK45-32-EX-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]1802// CHECK45-32-EX:       omp.inner.for.end:1803// CHECK45-32-EX-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]1804// CHECK45-32-EX:       omp.dispatch.inc:1805// CHECK45-32-EX-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41806// CHECK45-32-EX-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 41807// CHECK45-32-EX-NEXT:    [[ADD13:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]1808// CHECK45-32-EX-NEXT:    store i32 [[ADD13]], ptr [[DOTOMP_LB]], align 41809// CHECK45-32-EX-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41810// CHECK45-32-EX-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 41811// CHECK45-32-EX-NEXT:    [[ADD14:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]1812// CHECK45-32-EX-NEXT:    store i32 [[ADD14]], ptr [[DOTOMP_UB]], align 41813// CHECK45-32-EX-NEXT:    br label [[OMP_DISPATCH_COND]]1814// CHECK45-32-EX:       omp.dispatch.end:1815// CHECK45-32-EX-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP2]])1816// CHECK45-32-EX-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 41817// CHECK45-32-EX-NEXT:    [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 01818// CHECK45-32-EX-NEXT:    br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]1819// CHECK45-32-EX:       .omp.final.then:1820// CHECK45-32-EX-NEXT:    store i32 10, ptr [[I]], align 41821// CHECK45-32-EX-NEXT:    store i32 10, ptr [[J]], align 41822// CHECK45-32-EX-NEXT:    br label [[DOTOMP_FINAL_DONE]]1823// CHECK45-32-EX:       .omp.final.done:1824// CHECK45-32-EX-NEXT:    ret void1825//1826//1827// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l341828// CHECK-64-SAME: (ptr noalias [[DYN_PTR:%.*]], i64 [[N:%.*]], ptr nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 [[L:%.*]]) #[[ATTR0:[0-9]+]] {1829// CHECK-64-NEXT:  entry:1830// CHECK-64-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 81831// CHECK-64-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 81832// CHECK-64-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 81833// CHECK-64-NEXT:    [[L_ADDR:%.*]] = alloca i64, align 81834// CHECK-64-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 81835// CHECK-64-NEXT:    [[L_CASTED:%.*]] = alloca i64, align 81836// CHECK-64-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 41837// CHECK-64-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 41838// CHECK-64-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 81839// CHECK-64-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 81840// CHECK-64-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 81841// CHECK-64-NEXT:    store i64 [[L]], ptr [[L_ADDR]], align 81842// CHECK-64-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 81843// CHECK-64-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_kernel_environment, ptr [[DYN_PTR]])1844// CHECK-64-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -11845// CHECK-64-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]1846// CHECK-64:       user_code.entry:1847// CHECK-64-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])1848// CHECK-64-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 41849// CHECK-64-NEXT:    store i32 [[TMP3]], ptr [[N_CASTED]], align 41850// CHECK-64-NEXT:    [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 81851// CHECK-64-NEXT:    [[TMP5:%.*]] = load i32, ptr [[L_ADDR]], align 41852// CHECK-64-NEXT:    store i32 [[TMP5]], ptr [[L_CASTED]], align 41853// CHECK-64-NEXT:    [[TMP6:%.*]] = load i64, ptr [[L_CASTED]], align 81854// CHECK-64-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 41855// CHECK-64-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 41856// CHECK-64-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]], i64 [[TMP6]]) #[[ATTR2:[0-9]+]]1857// CHECK-64-NEXT:    call void @__kmpc_target_deinit()1858// CHECK-64-NEXT:    ret void1859// CHECK-64:       worker.exit:1860// CHECK-64-NEXT:    ret void1861//1862//1863// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined1864// CHECK-64-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], ptr nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 [[L:%.*]]) #[[ATTR1:[0-9]+]] {1865// CHECK-64-NEXT:  entry:1866// CHECK-64-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81867// CHECK-64-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81868// CHECK-64-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 81869// CHECK-64-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 81870// CHECK-64-NEXT:    [[L_ADDR:%.*]] = alloca i64, align 81871// CHECK-64-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 41872// CHECK-64-NEXT:    [[TMP:%.*]] = alloca i32, align 41873// CHECK-64-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 41874// CHECK-64-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 41875// CHECK-64-NEXT:    [[I:%.*]] = alloca i32, align 41876// CHECK-64-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 41877// CHECK-64-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 41878// CHECK-64-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41879// CHECK-64-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41880// CHECK-64-NEXT:    [[I3:%.*]] = alloca i32, align 41881// CHECK-64-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81882// CHECK-64-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81883// CHECK-64-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 81884// CHECK-64-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 81885// CHECK-64-NEXT:    store i64 [[L]], ptr [[L_ADDR]], align 81886// CHECK-64-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 81887// CHECK-64-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 41888// CHECK-64-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 41889// CHECK-64-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41890// CHECK-64-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 01891// CHECK-64-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 11892// CHECK-64-NEXT:    [[SUB2:%.*]] = sub nsw i32 [[DIV]], 11893// CHECK-64-NEXT:    store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 41894// CHECK-64-NEXT:    store i32 0, ptr [[I]], align 41895// CHECK-64-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41896// CHECK-64-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]1897// CHECK-64-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]1898// CHECK-64:       omp.precond.then:1899// CHECK-64-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 41900// CHECK-64-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 41901// CHECK-64-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 41902// CHECK-64-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 41903// CHECK-64-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 41904// CHECK-64-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81905// CHECK-64-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 41906// CHECK-64-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 128)1907// CHECK-64-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]1908// CHECK-64:       omp.dispatch.cond:1909// CHECK-64-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41910// CHECK-64-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 41911// CHECK-64-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]]1912// CHECK-64-NEXT:    br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1913// CHECK-64:       cond.true:1914// CHECK-64-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 41915// CHECK-64-NEXT:    br label [[COND_END:%.*]]1916// CHECK-64:       cond.false:1917// CHECK-64-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41918// CHECK-64-NEXT:    br label [[COND_END]]1919// CHECK-64:       cond.end:1920// CHECK-64-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]1921// CHECK-64-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 41922// CHECK-64-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41923// CHECK-64-NEXT:    store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 41924// CHECK-64-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41925// CHECK-64-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41926// CHECK-64-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]1927// CHECK-64-NEXT:    br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]1928// CHECK-64:       omp.dispatch.body:1929// CHECK-64-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]1930// CHECK-64:       omp.inner.for.cond:1931// CHECK-64-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]]1932// CHECK-64-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP18]]1933// CHECK-64-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]1934// CHECK-64-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1935// CHECK-64:       omp.inner.for.body:1936// CHECK-64-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]1937// CHECK-64-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP16]], 11938// CHECK-64-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]1939// CHECK-64-NEXT:    store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP18]]1940// CHECK-64-NEXT:    [[TMP17:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP18]]1941// CHECK-64-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i641942// CHECK-64-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]1943// CHECK-64-NEXT:    store i32 1, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP18]]1944// CHECK-64-NEXT:    [[TMP18:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP18]]1945// CHECK-64-NEXT:    store i32 [[TMP18]], ptr [[L_ADDR]], align 4, !llvm.access.group [[ACC_GRP18]]1946// CHECK-64-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]1947// CHECK-64:       omp.body.continue:1948// CHECK-64-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]1949// CHECK-64:       omp.inner.for.inc:1950// CHECK-64-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]1951// CHECK-64-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP19]], 11952// CHECK-64-NEXT:    store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]1953// CHECK-64-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]1954// CHECK-64:       omp.inner.for.end:1955// CHECK-64-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]1956// CHECK-64:       omp.dispatch.inc:1957// CHECK-64-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41958// CHECK-64-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 41959// CHECK-64-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]1960// CHECK-64-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_LB]], align 41961// CHECK-64-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41962// CHECK-64-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 41963// CHECK-64-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]1964// CHECK-64-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_UB]], align 41965// CHECK-64-NEXT:    br label [[OMP_DISPATCH_COND]]1966// CHECK-64:       omp.dispatch.end:1967// CHECK-64-NEXT:    [[TMP24:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81968// CHECK-64-NEXT:    [[TMP25:%.*]] = load i32, ptr [[TMP24]], align 41969// CHECK-64-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP25]])1970// CHECK-64-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 41971// CHECK-64-NEXT:    [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 01972// CHECK-64-NEXT:    br i1 [[TMP27]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]1973// CHECK-64:       .omp.final.then:1974// CHECK-64-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41975// CHECK-64-NEXT:    [[SUB10:%.*]] = sub nsw i32 [[TMP28]], 01976// CHECK-64-NEXT:    [[DIV11:%.*]] = sdiv i32 [[SUB10]], 11977// CHECK-64-NEXT:    [[MUL12:%.*]] = mul nsw i32 [[DIV11]], 11978// CHECK-64-NEXT:    [[ADD13:%.*]] = add nsw i32 0, [[MUL12]]1979// CHECK-64-NEXT:    store i32 [[ADD13]], ptr [[I3]], align 41980// CHECK-64-NEXT:    br label [[DOTOMP_FINAL_DONE]]1981// CHECK-64:       .omp.final.done:1982// CHECK-64-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 41983// CHECK-64-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 01984// CHECK-64-NEXT:    br i1 [[TMP30]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]1985// CHECK-64:       .omp.lastprivate.then:1986// CHECK-64-NEXT:    [[TMP31:%.*]] = load i32, ptr [[L_ADDR]], align 41987// CHECK-64-NEXT:    store i32 [[TMP31]], ptr [[L_ADDR]], align 41988// CHECK-64-NEXT:    br label [[DOTOMP_LASTPRIVATE_DONE]]1989// CHECK-64:       .omp.lastprivate.done:1990// CHECK-64-NEXT:    br label [[OMP_PRECOND_END]]1991// CHECK-64:       omp.precond.end:1992// CHECK-64-NEXT:    ret void1993//1994//1995// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l401996// CHECK-64-SAME: (ptr noalias [[DYN_PTR:%.*]], i64 [[N:%.*]], ptr nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR3:[0-9]+]] {1997// CHECK-64-NEXT:  entry:1998// CHECK-64-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 81999// CHECK-64-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 82000// CHECK-64-NEXT:    [[AA_ADDR:%.*]] = alloca ptr, align 82001// CHECK-64-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 82002// CHECK-64-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 42003// CHECK-64-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 42004// CHECK-64-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 82005// CHECK-64-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 82006// CHECK-64-NEXT:    store ptr [[AA]], ptr [[AA_ADDR]], align 82007// CHECK-64-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 82008// CHECK-64-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l40_kernel_environment, ptr [[DYN_PTR]])2009// CHECK-64-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -12010// CHECK-64-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]2011// CHECK-64:       user_code.entry:2012// CHECK-64-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])2013// CHECK-64-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 42014// CHECK-64-NEXT:    store i32 [[TMP3]], ptr [[N_CASTED]], align 42015// CHECK-64-NEXT:    [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 82016// CHECK-64-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 42017// CHECK-64-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 42018// CHECK-64-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l40_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]]) #[[ATTR2]]2019// CHECK-64-NEXT:    call void @__kmpc_target_deinit()2020// CHECK-64-NEXT:    ret void2021// CHECK-64:       worker.exit:2022// CHECK-64-NEXT:    ret void2023//2024//2025// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l40_omp_outlined2026// CHECK-64-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], ptr nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR1]] {2027// CHECK-64-NEXT:  entry:2028// CHECK-64-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 82029// CHECK-64-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 82030// CHECK-64-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 82031// CHECK-64-NEXT:    [[AA_ADDR:%.*]] = alloca ptr, align 82032// CHECK-64-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 42033// CHECK-64-NEXT:    [[TMP:%.*]] = alloca i32, align 42034// CHECK-64-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 42035// CHECK-64-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 42036// CHECK-64-NEXT:    [[I:%.*]] = alloca i32, align 42037// CHECK-64-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 42038// CHECK-64-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 42039// CHECK-64-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42040// CHECK-64-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42041// CHECK-64-NEXT:    [[I3:%.*]] = alloca i32, align 42042// CHECK-64-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 82043// CHECK-64-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 82044// CHECK-64-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 82045// CHECK-64-NEXT:    store ptr [[AA]], ptr [[AA_ADDR]], align 82046// CHECK-64-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 82047// CHECK-64-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 42048// CHECK-64-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 42049// CHECK-64-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 42050// CHECK-64-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 02051// CHECK-64-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 12052// CHECK-64-NEXT:    [[SUB2:%.*]] = sub nsw i32 [[DIV]], 12053// CHECK-64-NEXT:    store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 42054// CHECK-64-NEXT:    store i32 0, ptr [[I]], align 42055// CHECK-64-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 42056// CHECK-64-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]2057// CHECK-64-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]2058// CHECK-64:       omp.precond.then:2059// CHECK-64-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 42060// CHECK-64-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 42061// CHECK-64-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 42062// CHECK-64-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 42063// CHECK-64-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 42064// CHECK-64-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()2065// CHECK-64-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 82066// CHECK-64-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 42067// CHECK-64-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])2068// CHECK-64-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]2069// CHECK-64:       omp.dispatch.cond:2070// CHECK-64-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42071// CHECK-64-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 42072// CHECK-64-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]]2073// CHECK-64-NEXT:    br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2074// CHECK-64:       cond.true:2075// CHECK-64-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 42076// CHECK-64-NEXT:    br label [[COND_END:%.*]]2077// CHECK-64:       cond.false:2078// CHECK-64-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42079// CHECK-64-NEXT:    br label [[COND_END]]2080// CHECK-64:       cond.end:2081// CHECK-64-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]2082// CHECK-64-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 42083// CHECK-64-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42084// CHECK-64-NEXT:    store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 42085// CHECK-64-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42086// CHECK-64-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42087// CHECK-64-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]2088// CHECK-64-NEXT:    br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]2089// CHECK-64:       omp.dispatch.body:2090// CHECK-64-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]2091// CHECK-64:       omp.inner.for.cond:2092// CHECK-64-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22:![0-9]+]]2093// CHECK-64-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP22]]2094// CHECK-64-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]2095// CHECK-64-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2096// CHECK-64:       omp.inner.for.body:2097// CHECK-64-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]2098// CHECK-64-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP16]], 12099// CHECK-64-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]2100// CHECK-64-NEXT:    store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP22]]2101// CHECK-64-NEXT:    [[TMP17:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP22]]2102// CHECK-64-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i642103// CHECK-64-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]2104// CHECK-64-NEXT:    [[TMP18:%.*]] = load i16, ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP22]]2105// CHECK-64-NEXT:    [[CONV:%.*]] = sext i16 [[TMP18]] to i322106// CHECK-64-NEXT:    [[ADD7:%.*]] = add nsw i32 [[CONV]], 12107// CHECK-64-NEXT:    [[CONV8:%.*]] = trunc i32 [[ADD7]] to i162108// CHECK-64-NEXT:    store i16 [[CONV8]], ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP22]]2109// CHECK-64-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]2110// CHECK-64:       omp.body.continue:2111// CHECK-64-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]2112// CHECK-64:       omp.inner.for.inc:2113// CHECK-64-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]2114// CHECK-64-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP19]], 12115// CHECK-64-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]2116// CHECK-64-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]2117// CHECK-64:       omp.inner.for.end:2118// CHECK-64-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]2119// CHECK-64:       omp.dispatch.inc:2120// CHECK-64-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42121// CHECK-64-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 42122// CHECK-64-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]2123// CHECK-64-NEXT:    store i32 [[ADD10]], ptr [[DOTOMP_LB]], align 42124// CHECK-64-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42125// CHECK-64-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 42126// CHECK-64-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]2127// CHECK-64-NEXT:    store i32 [[ADD11]], ptr [[DOTOMP_UB]], align 42128// CHECK-64-NEXT:    br label [[OMP_DISPATCH_COND]]2129// CHECK-64:       omp.dispatch.end:2130// CHECK-64-NEXT:    [[TMP24:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 82131// CHECK-64-NEXT:    [[TMP25:%.*]] = load i32, ptr [[TMP24]], align 42132// CHECK-64-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP25]])2133// CHECK-64-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 42134// CHECK-64-NEXT:    [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 02135// CHECK-64-NEXT:    br i1 [[TMP27]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]2136// CHECK-64:       .omp.final.then:2137// CHECK-64-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 42138// CHECK-64-NEXT:    [[SUB12:%.*]] = sub nsw i32 [[TMP28]], 02139// CHECK-64-NEXT:    [[DIV13:%.*]] = sdiv i32 [[SUB12]], 12140// CHECK-64-NEXT:    [[MUL14:%.*]] = mul nsw i32 [[DIV13]], 12141// CHECK-64-NEXT:    [[ADD15:%.*]] = add nsw i32 0, [[MUL14]]2142// CHECK-64-NEXT:    store i32 [[ADD15]], ptr [[I3]], align 42143// CHECK-64-NEXT:    br label [[DOTOMP_FINAL_DONE]]2144// CHECK-64:       .omp.final.done:2145// CHECK-64-NEXT:    br label [[OMP_PRECOND_END]]2146// CHECK-64:       omp.precond.end:2147// CHECK-64-NEXT:    ret void2148//2149//2150// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l452151// CHECK-64-SAME: (ptr noalias [[DYN_PTR:%.*]], ptr nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {2152// CHECK-64-NEXT:  entry:2153// CHECK-64-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 82154// CHECK-64-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 82155// CHECK-64-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 42156// CHECK-64-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 42157// CHECK-64-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 82158// CHECK-64-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 82159// CHECK-64-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 82160// CHECK-64-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l45_kernel_environment, ptr [[DYN_PTR]])2161// CHECK-64-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -12162// CHECK-64-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]2163// CHECK-64:       user_code.entry:2164// CHECK-64-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])2165// CHECK-64-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 42166// CHECK-64-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 42167// CHECK-64-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l45_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]]) #[[ATTR2]]2168// CHECK-64-NEXT:    call void @__kmpc_target_deinit()2169// CHECK-64-NEXT:    ret void2170// CHECK-64:       worker.exit:2171// CHECK-64-NEXT:    ret void2172//2173//2174// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l45_omp_outlined2175// CHECK-64-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {2176// CHECK-64-NEXT:  entry:2177// CHECK-64-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 82178// CHECK-64-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 82179// CHECK-64-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 82180// CHECK-64-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 42181// CHECK-64-NEXT:    [[TMP:%.*]] = alloca i32, align 42182// CHECK-64-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 42183// CHECK-64-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 42184// CHECK-64-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42185// CHECK-64-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42186// CHECK-64-NEXT:    [[I:%.*]] = alloca i32, align 42187// CHECK-64-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 82188// CHECK-64-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 82189// CHECK-64-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 82190// CHECK-64-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 82191// CHECK-64-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 42192// CHECK-64-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 42193// CHECK-64-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 42194// CHECK-64-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 42195// CHECK-64-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()2196// CHECK-64-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 82197// CHECK-64-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 42198// CHECK-64-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])2199// CHECK-64-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]2200// CHECK-64:       omp.dispatch.cond:2201// CHECK-64-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42202// CHECK-64-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 92203// CHECK-64-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2204// CHECK-64:       cond.true:2205// CHECK-64-NEXT:    br label [[COND_END:%.*]]2206// CHECK-64:       cond.false:2207// CHECK-64-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42208// CHECK-64-NEXT:    br label [[COND_END]]2209// CHECK-64:       cond.end:2210// CHECK-64-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]2211// CHECK-64-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 42212// CHECK-64-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42213// CHECK-64-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 42214// CHECK-64-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42215// CHECK-64-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42216// CHECK-64-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]2217// CHECK-64-NEXT:    br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]2218// CHECK-64:       omp.dispatch.body:2219// CHECK-64-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]2220// CHECK-64:       omp.inner.for.cond:2221// CHECK-64-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25:![0-9]+]]2222// CHECK-64-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP25]]2223// CHECK-64-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]2224// CHECK-64-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2225// CHECK-64:       omp.inner.for.body:2226// CHECK-64-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]]2227// CHECK-64-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP10]], 12228// CHECK-64-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]2229// CHECK-64-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP25]]2230// CHECK-64-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP25]]2231// CHECK-64-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i642232// CHECK-64-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]2233// CHECK-64-NEXT:    [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]]2234// CHECK-64-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP12]], 12235// CHECK-64-NEXT:    store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]]2236// CHECK-64-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]2237// CHECK-64:       omp.body.continue:2238// CHECK-64-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]2239// CHECK-64:       omp.inner.for.inc:2240// CHECK-64-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]]2241// CHECK-64-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP13]], 12242// CHECK-64-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]]2243// CHECK-64-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]2244// CHECK-64:       omp.inner.for.end:2245// CHECK-64-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]2246// CHECK-64:       omp.dispatch.inc:2247// CHECK-64-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42248// CHECK-64-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 42249// CHECK-64-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]2250// CHECK-64-NEXT:    store i32 [[ADD5]], ptr [[DOTOMP_LB]], align 42251// CHECK-64-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42252// CHECK-64-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 42253// CHECK-64-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]2254// CHECK-64-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_UB]], align 42255// CHECK-64-NEXT:    br label [[OMP_DISPATCH_COND]]2256// CHECK-64:       omp.dispatch.end:2257// CHECK-64-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP2]])2258// CHECK-64-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 42259// CHECK-64-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 02260// CHECK-64-NEXT:    br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]2261// CHECK-64:       .omp.final.then:2262// CHECK-64-NEXT:    store i32 10, ptr [[I]], align 42263// CHECK-64-NEXT:    br label [[DOTOMP_FINAL_DONE]]2264// CHECK-64:       .omp.final.done:2265// CHECK-64-NEXT:    ret void2266//2267//2268// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l502269// CHECK-64-SAME: (ptr noalias [[DYN_PTR:%.*]], ptr nonnull align 4 dereferenceable(400) [[C:%.*]], i64 [[F:%.*]]) #[[ATTR0]] {2270// CHECK-64-NEXT:  entry:2271// CHECK-64-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 82272// CHECK-64-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 82273// CHECK-64-NEXT:    [[F_ADDR:%.*]] = alloca i64, align 82274// CHECK-64-NEXT:    [[F_CASTED:%.*]] = alloca i64, align 82275// CHECK-64-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 42276// CHECK-64-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 42277// CHECK-64-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 82278// CHECK-64-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 82279// CHECK-64-NEXT:    store i64 [[F]], ptr [[F_ADDR]], align 82280// CHECK-64-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 82281// CHECK-64-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l50_kernel_environment, ptr [[DYN_PTR]])2282// CHECK-64-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -12283// CHECK-64-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]2284// CHECK-64:       user_code.entry:2285// CHECK-64-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])2286// CHECK-64-NEXT:    [[TMP3:%.*]] = load i32, ptr [[F_ADDR]], align 42287// CHECK-64-NEXT:    store i32 [[TMP3]], ptr [[F_CASTED]], align 42288// CHECK-64-NEXT:    [[TMP4:%.*]] = load i64, ptr [[F_CASTED]], align 82289// CHECK-64-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 42290// CHECK-64-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 42291// CHECK-64-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l50_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i64 [[TMP4]]) #[[ATTR2]]2292// CHECK-64-NEXT:    call void @__kmpc_target_deinit()2293// CHECK-64-NEXT:    ret void2294// CHECK-64:       worker.exit:2295// CHECK-64-NEXT:    ret void2296//2297//2298// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l50_omp_outlined2299// CHECK-64-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(400) [[C:%.*]], i64 [[F:%.*]]) #[[ATTR1]] {2300// CHECK-64-NEXT:  entry:2301// CHECK-64-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 82302// CHECK-64-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 82303// CHECK-64-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 82304// CHECK-64-NEXT:    [[F_ADDR:%.*]] = alloca i64, align 82305// CHECK-64-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 42306// CHECK-64-NEXT:    [[TMP:%.*]] = alloca i32, align 42307// CHECK-64-NEXT:    [[_TMP1:%.*]] = alloca i32, align 42308// CHECK-64-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 42309// CHECK-64-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 42310// CHECK-64-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42311// CHECK-64-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42312// CHECK-64-NEXT:    [[K:%.*]] = alloca i32, align 42313// CHECK-64-NEXT:    [[I:%.*]] = alloca i32, align 42314// CHECK-64-NEXT:    [[J:%.*]] = alloca i32, align 42315// CHECK-64-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 82316// CHECK-64-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 82317// CHECK-64-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 82318// CHECK-64-NEXT:    store i64 [[F]], ptr [[F_ADDR]], align 82319// CHECK-64-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 82320// CHECK-64-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 42321// CHECK-64-NEXT:    store i32 99, ptr [[DOTOMP_UB]], align 42322// CHECK-64-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 42323// CHECK-64-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 42324// CHECK-64-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()2325// CHECK-64-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 82326// CHECK-64-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 42327// CHECK-64-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])2328// CHECK-64-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]2329// CHECK-64:       omp.dispatch.cond:2330// CHECK-64-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42331// CHECK-64-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 992332// CHECK-64-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2333// CHECK-64:       cond.true:2334// CHECK-64-NEXT:    br label [[COND_END:%.*]]2335// CHECK-64:       cond.false:2336// CHECK-64-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42337// CHECK-64-NEXT:    br label [[COND_END]]2338// CHECK-64:       cond.end:2339// CHECK-64-NEXT:    [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]2340// CHECK-64-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 42341// CHECK-64-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42342// CHECK-64-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 42343// CHECK-64-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42344// CHECK-64-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42345// CHECK-64-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]2346// CHECK-64-NEXT:    br i1 [[CMP2]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]2347// CHECK-64:       omp.dispatch.body:2348// CHECK-64-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]2349// CHECK-64:       omp.inner.for.cond:2350// CHECK-64-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28:![0-9]+]]2351// CHECK-64-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP28]]2352// CHECK-64-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]2353// CHECK-64-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2354// CHECK-64:       omp.inner.for.body:2355// CHECK-64-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]2356// CHECK-64-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP10]], 102357// CHECK-64-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 12358// CHECK-64-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]2359// CHECK-64-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP28]]2360// CHECK-64-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]2361// CHECK-64-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]2362// CHECK-64-NEXT:    [[DIV4:%.*]] = sdiv i32 [[TMP12]], 102363// CHECK-64-NEXT:    [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 102364// CHECK-64-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL5]]2365// CHECK-64-NEXT:    [[MUL6:%.*]] = mul nsw i32 [[SUB]], 12366// CHECK-64-NEXT:    [[ADD7:%.*]] = add nsw i32 0, [[MUL6]]2367// CHECK-64-NEXT:    store i32 [[ADD7]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP28]]2368// CHECK-64-NEXT:    store i32 10, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP28]]2369// CHECK-64-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP28]]2370// CHECK-64-NEXT:    [[TMP14:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP28]]2371// CHECK-64-NEXT:    [[TMP15:%.*]] = load i32, ptr [[F_ADDR]], align 4, !llvm.access.group [[ACC_GRP28]]2372// CHECK-64-NEXT:    [[MUL8:%.*]] = mul nsw i32 [[TMP14]], [[TMP15]]2373// CHECK-64-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP13]], [[MUL8]]2374// CHECK-64-NEXT:    [[TMP16:%.*]] = load i32, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP28]]2375// CHECK-64-NEXT:    [[ADD10:%.*]] = add nsw i32 [[ADD9]], [[TMP16]]2376// CHECK-64-NEXT:    [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP28]]2377// CHECK-64-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i642378// CHECK-64-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]2379// CHECK-64-NEXT:    [[TMP18:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP28]]2380// CHECK-64-NEXT:    [[IDXPROM11:%.*]] = sext i32 [[TMP18]] to i642381// CHECK-64-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM11]]2382// CHECK-64-NEXT:    store i32 [[ADD10]], ptr [[ARRAYIDX12]], align 4, !llvm.access.group [[ACC_GRP28]]2383// CHECK-64-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]2384// CHECK-64:       omp.body.continue:2385// CHECK-64-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]2386// CHECK-64:       omp.inner.for.inc:2387// CHECK-64-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]2388// CHECK-64-NEXT:    [[ADD13:%.*]] = add nsw i32 [[TMP19]], 12389// CHECK-64-NEXT:    store i32 [[ADD13]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]2390// CHECK-64-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]2391// CHECK-64:       omp.inner.for.end:2392// CHECK-64-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]2393// CHECK-64:       omp.dispatch.inc:2394// CHECK-64-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42395// CHECK-64-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 42396// CHECK-64-NEXT:    [[ADD14:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]2397// CHECK-64-NEXT:    store i32 [[ADD14]], ptr [[DOTOMP_LB]], align 42398// CHECK-64-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42399// CHECK-64-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 42400// CHECK-64-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]2401// CHECK-64-NEXT:    store i32 [[ADD15]], ptr [[DOTOMP_UB]], align 42402// CHECK-64-NEXT:    br label [[OMP_DISPATCH_COND]]2403// CHECK-64:       omp.dispatch.end:2404// CHECK-64-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP2]])2405// CHECK-64-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 42406// CHECK-64-NEXT:    [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 02407// CHECK-64-NEXT:    br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]2408// CHECK-64:       .omp.final.then:2409// CHECK-64-NEXT:    store i32 10, ptr [[I]], align 42410// CHECK-64-NEXT:    store i32 10, ptr [[J]], align 42411// CHECK-64-NEXT:    br label [[DOTOMP_FINAL_DONE]]2412// CHECK-64:       .omp.final.done:2413// CHECK-64-NEXT:    ret void2414//2415//2416// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l342417// CHECK-32-SAME: (ptr noalias [[DYN_PTR:%.*]], i32 [[N:%.*]], ptr nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[L:%.*]]) #[[ATTR0:[0-9]+]] {2418// CHECK-32-NEXT:  entry:2419// CHECK-32-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 42420// CHECK-32-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 42421// CHECK-32-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 42422// CHECK-32-NEXT:    [[L_ADDR:%.*]] = alloca i32, align 42423// CHECK-32-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 42424// CHECK-32-NEXT:    [[L_CASTED:%.*]] = alloca i32, align 42425// CHECK-32-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 42426// CHECK-32-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 42427// CHECK-32-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 42428// CHECK-32-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 42429// CHECK-32-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 42430// CHECK-32-NEXT:    store i32 [[L]], ptr [[L_ADDR]], align 42431// CHECK-32-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 42432// CHECK-32-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_kernel_environment, ptr [[DYN_PTR]])2433// CHECK-32-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -12434// CHECK-32-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]2435// CHECK-32:       user_code.entry:2436// CHECK-32-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])2437// CHECK-32-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 42438// CHECK-32-NEXT:    store i32 [[TMP3]], ptr [[N_CASTED]], align 42439// CHECK-32-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_CASTED]], align 42440// CHECK-32-NEXT:    [[TMP5:%.*]] = load i32, ptr [[L_ADDR]], align 42441// CHECK-32-NEXT:    store i32 [[TMP5]], ptr [[L_CASTED]], align 42442// CHECK-32-NEXT:    [[TMP6:%.*]] = load i32, ptr [[L_CASTED]], align 42443// CHECK-32-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 42444// CHECK-32-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 42445// CHECK-32-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]], i32 [[TMP6]]) #[[ATTR2:[0-9]+]]2446// CHECK-32-NEXT:    call void @__kmpc_target_deinit()2447// CHECK-32-NEXT:    ret void2448// CHECK-32:       worker.exit:2449// CHECK-32-NEXT:    ret void2450//2451//2452// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined2453// CHECK-32-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], ptr nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[L:%.*]]) #[[ATTR1:[0-9]+]] {2454// CHECK-32-NEXT:  entry:2455// CHECK-32-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 42456// CHECK-32-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 42457// CHECK-32-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 42458// CHECK-32-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 42459// CHECK-32-NEXT:    [[L_ADDR:%.*]] = alloca i32, align 42460// CHECK-32-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 42461// CHECK-32-NEXT:    [[TMP:%.*]] = alloca i32, align 42462// CHECK-32-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 42463// CHECK-32-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 42464// CHECK-32-NEXT:    [[I:%.*]] = alloca i32, align 42465// CHECK-32-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 42466// CHECK-32-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 42467// CHECK-32-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42468// CHECK-32-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42469// CHECK-32-NEXT:    [[I3:%.*]] = alloca i32, align 42470// CHECK-32-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 42471// CHECK-32-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 42472// CHECK-32-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 42473// CHECK-32-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 42474// CHECK-32-NEXT:    store i32 [[L]], ptr [[L_ADDR]], align 42475// CHECK-32-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 42476// CHECK-32-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 42477// CHECK-32-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 42478// CHECK-32-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 42479// CHECK-32-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 02480// CHECK-32-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 12481// CHECK-32-NEXT:    [[SUB2:%.*]] = sub nsw i32 [[DIV]], 12482// CHECK-32-NEXT:    store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 42483// CHECK-32-NEXT:    store i32 0, ptr [[I]], align 42484// CHECK-32-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 42485// CHECK-32-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]2486// CHECK-32-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]2487// CHECK-32:       omp.precond.then:2488// CHECK-32-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 42489// CHECK-32-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 42490// CHECK-32-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 42491// CHECK-32-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 42492// CHECK-32-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 42493// CHECK-32-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 42494// CHECK-32-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 42495// CHECK-32-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 128)2496// CHECK-32-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]2497// CHECK-32:       omp.dispatch.cond:2498// CHECK-32-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42499// CHECK-32-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 42500// CHECK-32-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]]2501// CHECK-32-NEXT:    br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2502// CHECK-32:       cond.true:2503// CHECK-32-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 42504// CHECK-32-NEXT:    br label [[COND_END:%.*]]2505// CHECK-32:       cond.false:2506// CHECK-32-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42507// CHECK-32-NEXT:    br label [[COND_END]]2508// CHECK-32:       cond.end:2509// CHECK-32-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]2510// CHECK-32-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 42511// CHECK-32-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42512// CHECK-32-NEXT:    store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 42513// CHECK-32-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42514// CHECK-32-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42515// CHECK-32-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]2516// CHECK-32-NEXT:    br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]2517// CHECK-32:       omp.dispatch.body:2518// CHECK-32-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]2519// CHECK-32:       omp.inner.for.cond:2520// CHECK-32-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]]2521// CHECK-32-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP18]]2522// CHECK-32-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]2523// CHECK-32-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2524// CHECK-32:       omp.inner.for.body:2525// CHECK-32-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]2526// CHECK-32-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP16]], 12527// CHECK-32-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]2528// CHECK-32-NEXT:    store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP18]]2529// CHECK-32-NEXT:    [[TMP17:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP18]]2530// CHECK-32-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i32 0, i32 [[TMP17]]2531// CHECK-32-NEXT:    store i32 1, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP18]]2532// CHECK-32-NEXT:    [[TMP18:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP18]]2533// CHECK-32-NEXT:    store i32 [[TMP18]], ptr [[L_ADDR]], align 4, !llvm.access.group [[ACC_GRP18]]2534// CHECK-32-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]2535// CHECK-32:       omp.body.continue:2536// CHECK-32-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]2537// CHECK-32:       omp.inner.for.inc:2538// CHECK-32-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]2539// CHECK-32-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP19]], 12540// CHECK-32-NEXT:    store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]2541// CHECK-32-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]2542// CHECK-32:       omp.inner.for.end:2543// CHECK-32-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]2544// CHECK-32:       omp.dispatch.inc:2545// CHECK-32-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42546// CHECK-32-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 42547// CHECK-32-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]2548// CHECK-32-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_LB]], align 42549// CHECK-32-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42550// CHECK-32-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 42551// CHECK-32-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]2552// CHECK-32-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_UB]], align 42553// CHECK-32-NEXT:    br label [[OMP_DISPATCH_COND]]2554// CHECK-32:       omp.dispatch.end:2555// CHECK-32-NEXT:    [[TMP24:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 42556// CHECK-32-NEXT:    [[TMP25:%.*]] = load i32, ptr [[TMP24]], align 42557// CHECK-32-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP25]])2558// CHECK-32-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 42559// CHECK-32-NEXT:    [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 02560// CHECK-32-NEXT:    br i1 [[TMP27]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]2561// CHECK-32:       .omp.final.then:2562// CHECK-32-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 42563// CHECK-32-NEXT:    [[SUB10:%.*]] = sub nsw i32 [[TMP28]], 02564// CHECK-32-NEXT:    [[DIV11:%.*]] = sdiv i32 [[SUB10]], 12565// CHECK-32-NEXT:    [[MUL12:%.*]] = mul nsw i32 [[DIV11]], 12566// CHECK-32-NEXT:    [[ADD13:%.*]] = add nsw i32 0, [[MUL12]]2567// CHECK-32-NEXT:    store i32 [[ADD13]], ptr [[I3]], align 42568// CHECK-32-NEXT:    br label [[DOTOMP_FINAL_DONE]]2569// CHECK-32:       .omp.final.done:2570// CHECK-32-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 42571// CHECK-32-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 02572// CHECK-32-NEXT:    br i1 [[TMP30]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]2573// CHECK-32:       .omp.lastprivate.then:2574// CHECK-32-NEXT:    [[TMP31:%.*]] = load i32, ptr [[L_ADDR]], align 42575// CHECK-32-NEXT:    store i32 [[TMP31]], ptr [[L_ADDR]], align 42576// CHECK-32-NEXT:    br label [[DOTOMP_LASTPRIVATE_DONE]]2577// CHECK-32:       .omp.lastprivate.done:2578// CHECK-32-NEXT:    br label [[OMP_PRECOND_END]]2579// CHECK-32:       omp.precond.end:2580// CHECK-32-NEXT:    ret void2581//2582//2583// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l402584// CHECK-32-SAME: (ptr noalias [[DYN_PTR:%.*]], i32 [[N:%.*]], ptr nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR3:[0-9]+]] {2585// CHECK-32-NEXT:  entry:2586// CHECK-32-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 42587// CHECK-32-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 42588// CHECK-32-NEXT:    [[AA_ADDR:%.*]] = alloca ptr, align 42589// CHECK-32-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 42590// CHECK-32-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 42591// CHECK-32-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 42592// CHECK-32-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 42593// CHECK-32-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 42594// CHECK-32-NEXT:    store ptr [[AA]], ptr [[AA_ADDR]], align 42595// CHECK-32-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 42596// CHECK-32-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l40_kernel_environment, ptr [[DYN_PTR]])2597// CHECK-32-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -12598// CHECK-32-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]2599// CHECK-32:       user_code.entry:2600// CHECK-32-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])2601// CHECK-32-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 42602// CHECK-32-NEXT:    store i32 [[TMP3]], ptr [[N_CASTED]], align 42603// CHECK-32-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_CASTED]], align 42604// CHECK-32-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 42605// CHECK-32-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 42606// CHECK-32-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l40_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]]) #[[ATTR2]]2607// CHECK-32-NEXT:    call void @__kmpc_target_deinit()2608// CHECK-32-NEXT:    ret void2609// CHECK-32:       worker.exit:2610// CHECK-32-NEXT:    ret void2611//2612//2613// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l40_omp_outlined2614// CHECK-32-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], ptr nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR1]] {2615// CHECK-32-NEXT:  entry:2616// CHECK-32-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 42617// CHECK-32-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 42618// CHECK-32-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 42619// CHECK-32-NEXT:    [[AA_ADDR:%.*]] = alloca ptr, align 42620// CHECK-32-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 42621// CHECK-32-NEXT:    [[TMP:%.*]] = alloca i32, align 42622// CHECK-32-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 42623// CHECK-32-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 42624// CHECK-32-NEXT:    [[I:%.*]] = alloca i32, align 42625// CHECK-32-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 42626// CHECK-32-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 42627// CHECK-32-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42628// CHECK-32-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42629// CHECK-32-NEXT:    [[I3:%.*]] = alloca i32, align 42630// CHECK-32-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 42631// CHECK-32-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 42632// CHECK-32-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 42633// CHECK-32-NEXT:    store ptr [[AA]], ptr [[AA_ADDR]], align 42634// CHECK-32-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 42635// CHECK-32-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 42636// CHECK-32-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 42637// CHECK-32-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 42638// CHECK-32-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 02639// CHECK-32-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 12640// CHECK-32-NEXT:    [[SUB2:%.*]] = sub nsw i32 [[DIV]], 12641// CHECK-32-NEXT:    store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 42642// CHECK-32-NEXT:    store i32 0, ptr [[I]], align 42643// CHECK-32-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 42644// CHECK-32-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]2645// CHECK-32-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]2646// CHECK-32:       omp.precond.then:2647// CHECK-32-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 42648// CHECK-32-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 42649// CHECK-32-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 42650// CHECK-32-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 42651// CHECK-32-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 42652// CHECK-32-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()2653// CHECK-32-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 42654// CHECK-32-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 42655// CHECK-32-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])2656// CHECK-32-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]2657// CHECK-32:       omp.dispatch.cond:2658// CHECK-32-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42659// CHECK-32-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 42660// CHECK-32-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]]2661// CHECK-32-NEXT:    br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2662// CHECK-32:       cond.true:2663// CHECK-32-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 42664// CHECK-32-NEXT:    br label [[COND_END:%.*]]2665// CHECK-32:       cond.false:2666// CHECK-32-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42667// CHECK-32-NEXT:    br label [[COND_END]]2668// CHECK-32:       cond.end:2669// CHECK-32-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]2670// CHECK-32-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 42671// CHECK-32-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42672// CHECK-32-NEXT:    store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 42673// CHECK-32-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42674// CHECK-32-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42675// CHECK-32-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]2676// CHECK-32-NEXT:    br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]2677// CHECK-32:       omp.dispatch.body:2678// CHECK-32-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]2679// CHECK-32:       omp.inner.for.cond:2680// CHECK-32-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22:![0-9]+]]2681// CHECK-32-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP22]]2682// CHECK-32-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]2683// CHECK-32-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2684// CHECK-32:       omp.inner.for.body:2685// CHECK-32-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]2686// CHECK-32-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP16]], 12687// CHECK-32-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]2688// CHECK-32-NEXT:    store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP22]]2689// CHECK-32-NEXT:    [[TMP17:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP22]]2690// CHECK-32-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], i32 0, i32 [[TMP17]]2691// CHECK-32-NEXT:    [[TMP18:%.*]] = load i16, ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP22]]2692// CHECK-32-NEXT:    [[CONV:%.*]] = sext i16 [[TMP18]] to i322693// CHECK-32-NEXT:    [[ADD7:%.*]] = add nsw i32 [[CONV]], 12694// CHECK-32-NEXT:    [[CONV8:%.*]] = trunc i32 [[ADD7]] to i162695// CHECK-32-NEXT:    store i16 [[CONV8]], ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP22]]2696// CHECK-32-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]2697// CHECK-32:       omp.body.continue:2698// CHECK-32-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]2699// CHECK-32:       omp.inner.for.inc:2700// CHECK-32-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]2701// CHECK-32-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP19]], 12702// CHECK-32-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]2703// CHECK-32-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]2704// CHECK-32:       omp.inner.for.end:2705// CHECK-32-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]2706// CHECK-32:       omp.dispatch.inc:2707// CHECK-32-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42708// CHECK-32-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 42709// CHECK-32-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]2710// CHECK-32-NEXT:    store i32 [[ADD10]], ptr [[DOTOMP_LB]], align 42711// CHECK-32-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42712// CHECK-32-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 42713// CHECK-32-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]2714// CHECK-32-NEXT:    store i32 [[ADD11]], ptr [[DOTOMP_UB]], align 42715// CHECK-32-NEXT:    br label [[OMP_DISPATCH_COND]]2716// CHECK-32:       omp.dispatch.end:2717// CHECK-32-NEXT:    [[TMP24:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 42718// CHECK-32-NEXT:    [[TMP25:%.*]] = load i32, ptr [[TMP24]], align 42719// CHECK-32-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP25]])2720// CHECK-32-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 42721// CHECK-32-NEXT:    [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 02722// CHECK-32-NEXT:    br i1 [[TMP27]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]2723// CHECK-32:       .omp.final.then:2724// CHECK-32-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 42725// CHECK-32-NEXT:    [[SUB12:%.*]] = sub nsw i32 [[TMP28]], 02726// CHECK-32-NEXT:    [[DIV13:%.*]] = sdiv i32 [[SUB12]], 12727// CHECK-32-NEXT:    [[MUL14:%.*]] = mul nsw i32 [[DIV13]], 12728// CHECK-32-NEXT:    [[ADD15:%.*]] = add nsw i32 0, [[MUL14]]2729// CHECK-32-NEXT:    store i32 [[ADD15]], ptr [[I3]], align 42730// CHECK-32-NEXT:    br label [[DOTOMP_FINAL_DONE]]2731// CHECK-32:       .omp.final.done:2732// CHECK-32-NEXT:    br label [[OMP_PRECOND_END]]2733// CHECK-32:       omp.precond.end:2734// CHECK-32-NEXT:    ret void2735//2736//2737// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l452738// CHECK-32-SAME: (ptr noalias [[DYN_PTR:%.*]], ptr nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {2739// CHECK-32-NEXT:  entry:2740// CHECK-32-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 42741// CHECK-32-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 42742// CHECK-32-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 42743// CHECK-32-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 42744// CHECK-32-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 42745// CHECK-32-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 42746// CHECK-32-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 42747// CHECK-32-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l45_kernel_environment, ptr [[DYN_PTR]])2748// CHECK-32-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -12749// CHECK-32-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]2750// CHECK-32:       user_code.entry:2751// CHECK-32-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])2752// CHECK-32-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 42753// CHECK-32-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 42754// CHECK-32-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l45_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]]) #[[ATTR2]]2755// CHECK-32-NEXT:    call void @__kmpc_target_deinit()2756// CHECK-32-NEXT:    ret void2757// CHECK-32:       worker.exit:2758// CHECK-32-NEXT:    ret void2759//2760//2761// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l45_omp_outlined2762// CHECK-32-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {2763// CHECK-32-NEXT:  entry:2764// CHECK-32-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 42765// CHECK-32-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 42766// CHECK-32-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 42767// CHECK-32-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 42768// CHECK-32-NEXT:    [[TMP:%.*]] = alloca i32, align 42769// CHECK-32-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 42770// CHECK-32-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 42771// CHECK-32-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42772// CHECK-32-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42773// CHECK-32-NEXT:    [[I:%.*]] = alloca i32, align 42774// CHECK-32-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 42775// CHECK-32-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 42776// CHECK-32-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 42777// CHECK-32-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 42778// CHECK-32-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 42779// CHECK-32-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 42780// CHECK-32-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 42781// CHECK-32-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 42782// CHECK-32-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()2783// CHECK-32-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 42784// CHECK-32-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 42785// CHECK-32-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])2786// CHECK-32-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]2787// CHECK-32:       omp.dispatch.cond:2788// CHECK-32-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42789// CHECK-32-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 92790// CHECK-32-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2791// CHECK-32:       cond.true:2792// CHECK-32-NEXT:    br label [[COND_END:%.*]]2793// CHECK-32:       cond.false:2794// CHECK-32-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42795// CHECK-32-NEXT:    br label [[COND_END]]2796// CHECK-32:       cond.end:2797// CHECK-32-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]2798// CHECK-32-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 42799// CHECK-32-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42800// CHECK-32-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 42801// CHECK-32-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42802// CHECK-32-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42803// CHECK-32-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]2804// CHECK-32-NEXT:    br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]2805// CHECK-32:       omp.dispatch.body:2806// CHECK-32-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]2807// CHECK-32:       omp.inner.for.cond:2808// CHECK-32-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25:![0-9]+]]2809// CHECK-32-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP25]]2810// CHECK-32-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]2811// CHECK-32-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2812// CHECK-32:       omp.inner.for.body:2813// CHECK-32-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]]2814// CHECK-32-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP10]], 12815// CHECK-32-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]2816// CHECK-32-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP25]]2817// CHECK-32-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP25]]2818// CHECK-32-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP11]]2819// CHECK-32-NEXT:    [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]]2820// CHECK-32-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP12]], 12821// CHECK-32-NEXT:    store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]]2822// CHECK-32-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]2823// CHECK-32:       omp.body.continue:2824// CHECK-32-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]2825// CHECK-32:       omp.inner.for.inc:2826// CHECK-32-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]]2827// CHECK-32-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP13]], 12828// CHECK-32-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]]2829// CHECK-32-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]2830// CHECK-32:       omp.inner.for.end:2831// CHECK-32-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]2832// CHECK-32:       omp.dispatch.inc:2833// CHECK-32-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42834// CHECK-32-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 42835// CHECK-32-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]2836// CHECK-32-NEXT:    store i32 [[ADD5]], ptr [[DOTOMP_LB]], align 42837// CHECK-32-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42838// CHECK-32-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 42839// CHECK-32-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]2840// CHECK-32-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_UB]], align 42841// CHECK-32-NEXT:    br label [[OMP_DISPATCH_COND]]2842// CHECK-32:       omp.dispatch.end:2843// CHECK-32-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP2]])2844// CHECK-32-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 42845// CHECK-32-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 02846// CHECK-32-NEXT:    br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]2847// CHECK-32:       .omp.final.then:2848// CHECK-32-NEXT:    store i32 10, ptr [[I]], align 42849// CHECK-32-NEXT:    br label [[DOTOMP_FINAL_DONE]]2850// CHECK-32:       .omp.final.done:2851// CHECK-32-NEXT:    ret void2852//2853//2854// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l502855// CHECK-32-SAME: (ptr noalias [[DYN_PTR:%.*]], ptr nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[F:%.*]]) #[[ATTR0]] {2856// CHECK-32-NEXT:  entry:2857// CHECK-32-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 42858// CHECK-32-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 42859// CHECK-32-NEXT:    [[F_ADDR:%.*]] = alloca i32, align 42860// CHECK-32-NEXT:    [[F_CASTED:%.*]] = alloca i32, align 42861// CHECK-32-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 42862// CHECK-32-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 42863// CHECK-32-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 42864// CHECK-32-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 42865// CHECK-32-NEXT:    store i32 [[F]], ptr [[F_ADDR]], align 42866// CHECK-32-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 42867// CHECK-32-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l50_kernel_environment, ptr [[DYN_PTR]])2868// CHECK-32-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -12869// CHECK-32-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]2870// CHECK-32:       user_code.entry:2871// CHECK-32-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])2872// CHECK-32-NEXT:    [[TMP3:%.*]] = load i32, ptr [[F_ADDR]], align 42873// CHECK-32-NEXT:    store i32 [[TMP3]], ptr [[F_CASTED]], align 42874// CHECK-32-NEXT:    [[TMP4:%.*]] = load i32, ptr [[F_CASTED]], align 42875// CHECK-32-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 42876// CHECK-32-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 42877// CHECK-32-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l50_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i32 [[TMP4]]) #[[ATTR2]]2878// CHECK-32-NEXT:    call void @__kmpc_target_deinit()2879// CHECK-32-NEXT:    ret void2880// CHECK-32:       worker.exit:2881// CHECK-32-NEXT:    ret void2882//2883//2884// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l50_omp_outlined2885// CHECK-32-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[F:%.*]]) #[[ATTR1]] {2886// CHECK-32-NEXT:  entry:2887// CHECK-32-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 42888// CHECK-32-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 42889// CHECK-32-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 42890// CHECK-32-NEXT:    [[F_ADDR:%.*]] = alloca i32, align 42891// CHECK-32-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 42892// CHECK-32-NEXT:    [[TMP:%.*]] = alloca i32, align 42893// CHECK-32-NEXT:    [[_TMP1:%.*]] = alloca i32, align 42894// CHECK-32-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 42895// CHECK-32-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 42896// CHECK-32-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42897// CHECK-32-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42898// CHECK-32-NEXT:    [[K:%.*]] = alloca i32, align 42899// CHECK-32-NEXT:    [[I:%.*]] = alloca i32, align 42900// CHECK-32-NEXT:    [[J:%.*]] = alloca i32, align 42901// CHECK-32-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 42902// CHECK-32-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 42903// CHECK-32-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 42904// CHECK-32-NEXT:    store i32 [[F]], ptr [[F_ADDR]], align 42905// CHECK-32-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 42906// CHECK-32-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 42907// CHECK-32-NEXT:    store i32 99, ptr [[DOTOMP_UB]], align 42908// CHECK-32-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 42909// CHECK-32-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 42910// CHECK-32-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()2911// CHECK-32-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 42912// CHECK-32-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 42913// CHECK-32-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])2914// CHECK-32-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]2915// CHECK-32:       omp.dispatch.cond:2916// CHECK-32-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42917// CHECK-32-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 992918// CHECK-32-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2919// CHECK-32:       cond.true:2920// CHECK-32-NEXT:    br label [[COND_END:%.*]]2921// CHECK-32:       cond.false:2922// CHECK-32-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42923// CHECK-32-NEXT:    br label [[COND_END]]2924// CHECK-32:       cond.end:2925// CHECK-32-NEXT:    [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]2926// CHECK-32-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 42927// CHECK-32-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42928// CHECK-32-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 42929// CHECK-32-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42930// CHECK-32-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42931// CHECK-32-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]2932// CHECK-32-NEXT:    br i1 [[CMP2]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]2933// CHECK-32:       omp.dispatch.body:2934// CHECK-32-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]2935// CHECK-32:       omp.inner.for.cond:2936// CHECK-32-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28:![0-9]+]]2937// CHECK-32-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP28]]2938// CHECK-32-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]2939// CHECK-32-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2940// CHECK-32:       omp.inner.for.body:2941// CHECK-32-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]2942// CHECK-32-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP10]], 102943// CHECK-32-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 12944// CHECK-32-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]2945// CHECK-32-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP28]]2946// CHECK-32-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]2947// CHECK-32-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]2948// CHECK-32-NEXT:    [[DIV4:%.*]] = sdiv i32 [[TMP12]], 102949// CHECK-32-NEXT:    [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 102950// CHECK-32-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL5]]2951// CHECK-32-NEXT:    [[MUL6:%.*]] = mul nsw i32 [[SUB]], 12952// CHECK-32-NEXT:    [[ADD7:%.*]] = add nsw i32 0, [[MUL6]]2953// CHECK-32-NEXT:    store i32 [[ADD7]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP28]]2954// CHECK-32-NEXT:    store i32 10, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP28]]2955// CHECK-32-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP28]]2956// CHECK-32-NEXT:    [[TMP14:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP28]]2957// CHECK-32-NEXT:    [[TMP15:%.*]] = load i32, ptr [[F_ADDR]], align 4, !llvm.access.group [[ACC_GRP28]]2958// CHECK-32-NEXT:    [[MUL8:%.*]] = mul nsw i32 [[TMP14]], [[TMP15]]2959// CHECK-32-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP13]], [[MUL8]]2960// CHECK-32-NEXT:    [[TMP16:%.*]] = load i32, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP28]]2961// CHECK-32-NEXT:    [[ADD10:%.*]] = add nsw i32 [[ADD9]], [[TMP16]]2962// CHECK-32-NEXT:    [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP28]]2963// CHECK-32-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], i32 0, i32 [[TMP17]]2964// CHECK-32-NEXT:    [[TMP18:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP28]]2965// CHECK-32-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP18]]2966// CHECK-32-NEXT:    store i32 [[ADD10]], ptr [[ARRAYIDX11]], align 4, !llvm.access.group [[ACC_GRP28]]2967// CHECK-32-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]2968// CHECK-32:       omp.body.continue:2969// CHECK-32-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]2970// CHECK-32:       omp.inner.for.inc:2971// CHECK-32-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]2972// CHECK-32-NEXT:    [[ADD12:%.*]] = add nsw i32 [[TMP19]], 12973// CHECK-32-NEXT:    store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]2974// CHECK-32-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]2975// CHECK-32:       omp.inner.for.end:2976// CHECK-32-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]2977// CHECK-32:       omp.dispatch.inc:2978// CHECK-32-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42979// CHECK-32-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 42980// CHECK-32-NEXT:    [[ADD13:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]2981// CHECK-32-NEXT:    store i32 [[ADD13]], ptr [[DOTOMP_LB]], align 42982// CHECK-32-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42983// CHECK-32-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 42984// CHECK-32-NEXT:    [[ADD14:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]2985// CHECK-32-NEXT:    store i32 [[ADD14]], ptr [[DOTOMP_UB]], align 42986// CHECK-32-NEXT:    br label [[OMP_DISPATCH_COND]]2987// CHECK-32:       omp.dispatch.end:2988// CHECK-32-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP2]])2989// CHECK-32-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 42990// CHECK-32-NEXT:    [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 02991// CHECK-32-NEXT:    br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]2992// CHECK-32:       .omp.final.then:2993// CHECK-32-NEXT:    store i32 10, ptr [[I]], align 42994// CHECK-32-NEXT:    store i32 10, ptr [[J]], align 42995// CHECK-32-NEXT:    br label [[DOTOMP_FINAL_DONE]]2996// CHECK-32:       .omp.final.done:2997// CHECK-32-NEXT:    ret void2998//2999//3000// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l343001// CHECK-32-EX-SAME: (ptr noalias [[DYN_PTR:%.*]], i32 [[N:%.*]], ptr nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[L:%.*]]) #[[ATTR0:[0-9]+]] {3002// CHECK-32-EX-NEXT:  entry:3003// CHECK-32-EX-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 43004// CHECK-32-EX-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 43005// CHECK-32-EX-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 43006// CHECK-32-EX-NEXT:    [[L_ADDR:%.*]] = alloca i32, align 43007// CHECK-32-EX-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 43008// CHECK-32-EX-NEXT:    [[L_CASTED:%.*]] = alloca i32, align 43009// CHECK-32-EX-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 43010// CHECK-32-EX-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 43011// CHECK-32-EX-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 43012// CHECK-32-EX-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 43013// CHECK-32-EX-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 43014// CHECK-32-EX-NEXT:    store i32 [[L]], ptr [[L_ADDR]], align 43015// CHECK-32-EX-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 43016// CHECK-32-EX-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_kernel_environment, ptr [[DYN_PTR]])3017// CHECK-32-EX-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -13018// CHECK-32-EX-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]3019// CHECK-32-EX:       user_code.entry:3020// CHECK-32-EX-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])3021// CHECK-32-EX-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 43022// CHECK-32-EX-NEXT:    store i32 [[TMP3]], ptr [[N_CASTED]], align 43023// CHECK-32-EX-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_CASTED]], align 43024// CHECK-32-EX-NEXT:    [[TMP5:%.*]] = load i32, ptr [[L_ADDR]], align 43025// CHECK-32-EX-NEXT:    store i32 [[TMP5]], ptr [[L_CASTED]], align 43026// CHECK-32-EX-NEXT:    [[TMP6:%.*]] = load i32, ptr [[L_CASTED]], align 43027// CHECK-32-EX-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 43028// CHECK-32-EX-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 43029// CHECK-32-EX-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]], i32 [[TMP6]]) #[[ATTR2:[0-9]+]]3030// CHECK-32-EX-NEXT:    call void @__kmpc_target_deinit()3031// CHECK-32-EX-NEXT:    ret void3032// CHECK-32-EX:       worker.exit:3033// CHECK-32-EX-NEXT:    ret void3034//3035//3036// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined3037// CHECK-32-EX-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], ptr nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[L:%.*]]) #[[ATTR1:[0-9]+]] {3038// CHECK-32-EX-NEXT:  entry:3039// CHECK-32-EX-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 43040// CHECK-32-EX-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 43041// CHECK-32-EX-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 43042// CHECK-32-EX-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 43043// CHECK-32-EX-NEXT:    [[L_ADDR:%.*]] = alloca i32, align 43044// CHECK-32-EX-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 43045// CHECK-32-EX-NEXT:    [[TMP:%.*]] = alloca i32, align 43046// CHECK-32-EX-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 43047// CHECK-32-EX-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 43048// CHECK-32-EX-NEXT:    [[I:%.*]] = alloca i32, align 43049// CHECK-32-EX-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 43050// CHECK-32-EX-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 43051// CHECK-32-EX-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 43052// CHECK-32-EX-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 43053// CHECK-32-EX-NEXT:    [[I3:%.*]] = alloca i32, align 43054// CHECK-32-EX-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 43055// CHECK-32-EX-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 43056// CHECK-32-EX-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 43057// CHECK-32-EX-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 43058// CHECK-32-EX-NEXT:    store i32 [[L]], ptr [[L_ADDR]], align 43059// CHECK-32-EX-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 43060// CHECK-32-EX-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 43061// CHECK-32-EX-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 43062// CHECK-32-EX-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 43063// CHECK-32-EX-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 03064// CHECK-32-EX-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 13065// CHECK-32-EX-NEXT:    [[SUB2:%.*]] = sub nsw i32 [[DIV]], 13066// CHECK-32-EX-NEXT:    store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 43067// CHECK-32-EX-NEXT:    store i32 0, ptr [[I]], align 43068// CHECK-32-EX-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 43069// CHECK-32-EX-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]3070// CHECK-32-EX-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]3071// CHECK-32-EX:       omp.precond.then:3072// CHECK-32-EX-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 43073// CHECK-32-EX-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 43074// CHECK-32-EX-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 43075// CHECK-32-EX-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 43076// CHECK-32-EX-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 43077// CHECK-32-EX-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 43078// CHECK-32-EX-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 43079// CHECK-32-EX-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 128)3080// CHECK-32-EX-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]3081// CHECK-32-EX:       omp.dispatch.cond:3082// CHECK-32-EX-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43083// CHECK-32-EX-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 43084// CHECK-32-EX-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]]3085// CHECK-32-EX-NEXT:    br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]3086// CHECK-32-EX:       cond.true:3087// CHECK-32-EX-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 43088// CHECK-32-EX-NEXT:    br label [[COND_END:%.*]]3089// CHECK-32-EX:       cond.false:3090// CHECK-32-EX-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43091// CHECK-32-EX-NEXT:    br label [[COND_END]]3092// CHECK-32-EX:       cond.end:3093// CHECK-32-EX-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]3094// CHECK-32-EX-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 43095// CHECK-32-EX-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 43096// CHECK-32-EX-NEXT:    store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 43097// CHECK-32-EX-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43098// CHECK-32-EX-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43099// CHECK-32-EX-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]3100// CHECK-32-EX-NEXT:    br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]3101// CHECK-32-EX:       omp.dispatch.body:3102// CHECK-32-EX-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]3103// CHECK-32-EX:       omp.inner.for.cond:3104// CHECK-32-EX-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]]3105// CHECK-32-EX-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP18]]3106// CHECK-32-EX-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]3107// CHECK-32-EX-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]3108// CHECK-32-EX:       omp.inner.for.body:3109// CHECK-32-EX-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]3110// CHECK-32-EX-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP16]], 13111// CHECK-32-EX-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]3112// CHECK-32-EX-NEXT:    store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP18]]3113// CHECK-32-EX-NEXT:    [[TMP17:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP18]]3114// CHECK-32-EX-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i32 0, i32 [[TMP17]]3115// CHECK-32-EX-NEXT:    store i32 1, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP18]]3116// CHECK-32-EX-NEXT:    [[TMP18:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP18]]3117// CHECK-32-EX-NEXT:    store i32 [[TMP18]], ptr [[L_ADDR]], align 4, !llvm.access.group [[ACC_GRP18]]3118// CHECK-32-EX-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]3119// CHECK-32-EX:       omp.body.continue:3120// CHECK-32-EX-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]3121// CHECK-32-EX:       omp.inner.for.inc:3122// CHECK-32-EX-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]3123// CHECK-32-EX-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP19]], 13124// CHECK-32-EX-NEXT:    store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]3125// CHECK-32-EX-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]3126// CHECK-32-EX:       omp.inner.for.end:3127// CHECK-32-EX-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]3128// CHECK-32-EX:       omp.dispatch.inc:3129// CHECK-32-EX-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_LB]], align 43130// CHECK-32-EX-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 43131// CHECK-32-EX-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]3132// CHECK-32-EX-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_LB]], align 43133// CHECK-32-EX-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43134// CHECK-32-EX-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 43135// CHECK-32-EX-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]3136// CHECK-32-EX-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_UB]], align 43137// CHECK-32-EX-NEXT:    br label [[OMP_DISPATCH_COND]]3138// CHECK-32-EX:       omp.dispatch.end:3139// CHECK-32-EX-NEXT:    [[TMP24:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 43140// CHECK-32-EX-NEXT:    [[TMP25:%.*]] = load i32, ptr [[TMP24]], align 43141// CHECK-32-EX-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP25]])3142// CHECK-32-EX-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 43143// CHECK-32-EX-NEXT:    [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 03144// CHECK-32-EX-NEXT:    br i1 [[TMP27]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]3145// CHECK-32-EX:       .omp.final.then:3146// CHECK-32-EX-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 43147// CHECK-32-EX-NEXT:    [[SUB10:%.*]] = sub nsw i32 [[TMP28]], 03148// CHECK-32-EX-NEXT:    [[DIV11:%.*]] = sdiv i32 [[SUB10]], 13149// CHECK-32-EX-NEXT:    [[MUL12:%.*]] = mul nsw i32 [[DIV11]], 13150// CHECK-32-EX-NEXT:    [[ADD13:%.*]] = add nsw i32 0, [[MUL12]]3151// CHECK-32-EX-NEXT:    store i32 [[ADD13]], ptr [[I3]], align 43152// CHECK-32-EX-NEXT:    br label [[DOTOMP_FINAL_DONE]]3153// CHECK-32-EX:       .omp.final.done:3154// CHECK-32-EX-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 43155// CHECK-32-EX-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 03156// CHECK-32-EX-NEXT:    br i1 [[TMP30]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]3157// CHECK-32-EX:       .omp.lastprivate.then:3158// CHECK-32-EX-NEXT:    [[TMP31:%.*]] = load i32, ptr [[L_ADDR]], align 43159// CHECK-32-EX-NEXT:    store i32 [[TMP31]], ptr [[L_ADDR]], align 43160// CHECK-32-EX-NEXT:    br label [[DOTOMP_LASTPRIVATE_DONE]]3161// CHECK-32-EX:       .omp.lastprivate.done:3162// CHECK-32-EX-NEXT:    br label [[OMP_PRECOND_END]]3163// CHECK-32-EX:       omp.precond.end:3164// CHECK-32-EX-NEXT:    ret void3165//3166//3167// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l403168// CHECK-32-EX-SAME: (ptr noalias [[DYN_PTR:%.*]], i32 [[N:%.*]], ptr nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR3:[0-9]+]] {3169// CHECK-32-EX-NEXT:  entry:3170// CHECK-32-EX-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 43171// CHECK-32-EX-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 43172// CHECK-32-EX-NEXT:    [[AA_ADDR:%.*]] = alloca ptr, align 43173// CHECK-32-EX-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 43174// CHECK-32-EX-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 43175// CHECK-32-EX-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 43176// CHECK-32-EX-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 43177// CHECK-32-EX-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 43178// CHECK-32-EX-NEXT:    store ptr [[AA]], ptr [[AA_ADDR]], align 43179// CHECK-32-EX-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 43180// CHECK-32-EX-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l40_kernel_environment, ptr [[DYN_PTR]])3181// CHECK-32-EX-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -13182// CHECK-32-EX-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]3183// CHECK-32-EX:       user_code.entry:3184// CHECK-32-EX-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])3185// CHECK-32-EX-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 43186// CHECK-32-EX-NEXT:    store i32 [[TMP3]], ptr [[N_CASTED]], align 43187// CHECK-32-EX-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_CASTED]], align 43188// CHECK-32-EX-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 43189// CHECK-32-EX-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 43190// CHECK-32-EX-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l40_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]]) #[[ATTR2]]3191// CHECK-32-EX-NEXT:    call void @__kmpc_target_deinit()3192// CHECK-32-EX-NEXT:    ret void3193// CHECK-32-EX:       worker.exit:3194// CHECK-32-EX-NEXT:    ret void3195//3196//3197// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l40_omp_outlined3198// CHECK-32-EX-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], ptr nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR1]] {3199// CHECK-32-EX-NEXT:  entry:3200// CHECK-32-EX-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 43201// CHECK-32-EX-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 43202// CHECK-32-EX-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 43203// CHECK-32-EX-NEXT:    [[AA_ADDR:%.*]] = alloca ptr, align 43204// CHECK-32-EX-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 43205// CHECK-32-EX-NEXT:    [[TMP:%.*]] = alloca i32, align 43206// CHECK-32-EX-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 43207// CHECK-32-EX-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 43208// CHECK-32-EX-NEXT:    [[I:%.*]] = alloca i32, align 43209// CHECK-32-EX-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 43210// CHECK-32-EX-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 43211// CHECK-32-EX-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 43212// CHECK-32-EX-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 43213// CHECK-32-EX-NEXT:    [[I3:%.*]] = alloca i32, align 43214// CHECK-32-EX-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 43215// CHECK-32-EX-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 43216// CHECK-32-EX-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 43217// CHECK-32-EX-NEXT:    store ptr [[AA]], ptr [[AA_ADDR]], align 43218// CHECK-32-EX-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 43219// CHECK-32-EX-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 43220// CHECK-32-EX-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 43221// CHECK-32-EX-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 43222// CHECK-32-EX-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 03223// CHECK-32-EX-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 13224// CHECK-32-EX-NEXT:    [[SUB2:%.*]] = sub nsw i32 [[DIV]], 13225// CHECK-32-EX-NEXT:    store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 43226// CHECK-32-EX-NEXT:    store i32 0, ptr [[I]], align 43227// CHECK-32-EX-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 43228// CHECK-32-EX-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]3229// CHECK-32-EX-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]3230// CHECK-32-EX:       omp.precond.then:3231// CHECK-32-EX-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 43232// CHECK-32-EX-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 43233// CHECK-32-EX-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 43234// CHECK-32-EX-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 43235// CHECK-32-EX-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 43236// CHECK-32-EX-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()3237// CHECK-32-EX-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 43238// CHECK-32-EX-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 43239// CHECK-32-EX-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])3240// CHECK-32-EX-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]3241// CHECK-32-EX:       omp.dispatch.cond:3242// CHECK-32-EX-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43243// CHECK-32-EX-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 43244// CHECK-32-EX-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]]3245// CHECK-32-EX-NEXT:    br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]3246// CHECK-32-EX:       cond.true:3247// CHECK-32-EX-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 43248// CHECK-32-EX-NEXT:    br label [[COND_END:%.*]]3249// CHECK-32-EX:       cond.false:3250// CHECK-32-EX-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43251// CHECK-32-EX-NEXT:    br label [[COND_END]]3252// CHECK-32-EX:       cond.end:3253// CHECK-32-EX-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]3254// CHECK-32-EX-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 43255// CHECK-32-EX-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 43256// CHECK-32-EX-NEXT:    store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 43257// CHECK-32-EX-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43258// CHECK-32-EX-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43259// CHECK-32-EX-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]3260// CHECK-32-EX-NEXT:    br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]3261// CHECK-32-EX:       omp.dispatch.body:3262// CHECK-32-EX-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]3263// CHECK-32-EX:       omp.inner.for.cond:3264// CHECK-32-EX-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22:![0-9]+]]3265// CHECK-32-EX-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP22]]3266// CHECK-32-EX-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]3267// CHECK-32-EX-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]3268// CHECK-32-EX:       omp.inner.for.body:3269// CHECK-32-EX-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]3270// CHECK-32-EX-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP16]], 13271// CHECK-32-EX-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]3272// CHECK-32-EX-NEXT:    store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP22]]3273// CHECK-32-EX-NEXT:    [[TMP17:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP22]]3274// CHECK-32-EX-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], i32 0, i32 [[TMP17]]3275// CHECK-32-EX-NEXT:    [[TMP18:%.*]] = load i16, ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP22]]3276// CHECK-32-EX-NEXT:    [[CONV:%.*]] = sext i16 [[TMP18]] to i323277// CHECK-32-EX-NEXT:    [[ADD7:%.*]] = add nsw i32 [[CONV]], 13278// CHECK-32-EX-NEXT:    [[CONV8:%.*]] = trunc i32 [[ADD7]] to i163279// CHECK-32-EX-NEXT:    store i16 [[CONV8]], ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP22]]3280// CHECK-32-EX-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]3281// CHECK-32-EX:       omp.body.continue:3282// CHECK-32-EX-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]3283// CHECK-32-EX:       omp.inner.for.inc:3284// CHECK-32-EX-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]3285// CHECK-32-EX-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP19]], 13286// CHECK-32-EX-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]3287// CHECK-32-EX-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]3288// CHECK-32-EX:       omp.inner.for.end:3289// CHECK-32-EX-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]3290// CHECK-32-EX:       omp.dispatch.inc:3291// CHECK-32-EX-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_LB]], align 43292// CHECK-32-EX-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 43293// CHECK-32-EX-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]3294// CHECK-32-EX-NEXT:    store i32 [[ADD10]], ptr [[DOTOMP_LB]], align 43295// CHECK-32-EX-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43296// CHECK-32-EX-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 43297// CHECK-32-EX-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]3298// CHECK-32-EX-NEXT:    store i32 [[ADD11]], ptr [[DOTOMP_UB]], align 43299// CHECK-32-EX-NEXT:    br label [[OMP_DISPATCH_COND]]3300// CHECK-32-EX:       omp.dispatch.end:3301// CHECK-32-EX-NEXT:    [[TMP24:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 43302// CHECK-32-EX-NEXT:    [[TMP25:%.*]] = load i32, ptr [[TMP24]], align 43303// CHECK-32-EX-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP25]])3304// CHECK-32-EX-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 43305// CHECK-32-EX-NEXT:    [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 03306// CHECK-32-EX-NEXT:    br i1 [[TMP27]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]3307// CHECK-32-EX:       .omp.final.then:3308// CHECK-32-EX-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 43309// CHECK-32-EX-NEXT:    [[SUB12:%.*]] = sub nsw i32 [[TMP28]], 03310// CHECK-32-EX-NEXT:    [[DIV13:%.*]] = sdiv i32 [[SUB12]], 13311// CHECK-32-EX-NEXT:    [[MUL14:%.*]] = mul nsw i32 [[DIV13]], 13312// CHECK-32-EX-NEXT:    [[ADD15:%.*]] = add nsw i32 0, [[MUL14]]3313// CHECK-32-EX-NEXT:    store i32 [[ADD15]], ptr [[I3]], align 43314// CHECK-32-EX-NEXT:    br label [[DOTOMP_FINAL_DONE]]3315// CHECK-32-EX:       .omp.final.done:3316// CHECK-32-EX-NEXT:    br label [[OMP_PRECOND_END]]3317// CHECK-32-EX:       omp.precond.end:3318// CHECK-32-EX-NEXT:    ret void3319//3320//3321// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l453322// CHECK-32-EX-SAME: (ptr noalias [[DYN_PTR:%.*]], ptr nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {3323// CHECK-32-EX-NEXT:  entry:3324// CHECK-32-EX-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 43325// CHECK-32-EX-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 43326// CHECK-32-EX-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 43327// CHECK-32-EX-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 43328// CHECK-32-EX-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 43329// CHECK-32-EX-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 43330// CHECK-32-EX-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 43331// CHECK-32-EX-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l45_kernel_environment, ptr [[DYN_PTR]])3332// CHECK-32-EX-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -13333// CHECK-32-EX-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]3334// CHECK-32-EX:       user_code.entry:3335// CHECK-32-EX-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])3336// CHECK-32-EX-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 43337// CHECK-32-EX-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 43338// CHECK-32-EX-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l45_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]]) #[[ATTR2]]3339// CHECK-32-EX-NEXT:    call void @__kmpc_target_deinit()3340// CHECK-32-EX-NEXT:    ret void3341// CHECK-32-EX:       worker.exit:3342// CHECK-32-EX-NEXT:    ret void3343//3344//3345// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l45_omp_outlined3346// CHECK-32-EX-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {3347// CHECK-32-EX-NEXT:  entry:3348// CHECK-32-EX-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 43349// CHECK-32-EX-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 43350// CHECK-32-EX-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 43351// CHECK-32-EX-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 43352// CHECK-32-EX-NEXT:    [[TMP:%.*]] = alloca i32, align 43353// CHECK-32-EX-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 43354// CHECK-32-EX-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 43355// CHECK-32-EX-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 43356// CHECK-32-EX-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 43357// CHECK-32-EX-NEXT:    [[I:%.*]] = alloca i32, align 43358// CHECK-32-EX-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 43359// CHECK-32-EX-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 43360// CHECK-32-EX-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 43361// CHECK-32-EX-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 43362// CHECK-32-EX-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 43363// CHECK-32-EX-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 43364// CHECK-32-EX-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 43365// CHECK-32-EX-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 43366// CHECK-32-EX-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()3367// CHECK-32-EX-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 43368// CHECK-32-EX-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 43369// CHECK-32-EX-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])3370// CHECK-32-EX-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]3371// CHECK-32-EX:       omp.dispatch.cond:3372// CHECK-32-EX-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43373// CHECK-32-EX-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 93374// CHECK-32-EX-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]3375// CHECK-32-EX:       cond.true:3376// CHECK-32-EX-NEXT:    br label [[COND_END:%.*]]3377// CHECK-32-EX:       cond.false:3378// CHECK-32-EX-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43379// CHECK-32-EX-NEXT:    br label [[COND_END]]3380// CHECK-32-EX:       cond.end:3381// CHECK-32-EX-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]3382// CHECK-32-EX-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 43383// CHECK-32-EX-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 43384// CHECK-32-EX-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 43385// CHECK-32-EX-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43386// CHECK-32-EX-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43387// CHECK-32-EX-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]3388// CHECK-32-EX-NEXT:    br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]3389// CHECK-32-EX:       omp.dispatch.body:3390// CHECK-32-EX-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]3391// CHECK-32-EX:       omp.inner.for.cond:3392// CHECK-32-EX-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25:![0-9]+]]3393// CHECK-32-EX-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP25]]3394// CHECK-32-EX-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]3395// CHECK-32-EX-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]3396// CHECK-32-EX:       omp.inner.for.body:3397// CHECK-32-EX-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]]3398// CHECK-32-EX-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP10]], 13399// CHECK-32-EX-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]3400// CHECK-32-EX-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP25]]3401// CHECK-32-EX-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP25]]3402// CHECK-32-EX-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP11]]3403// CHECK-32-EX-NEXT:    [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]]3404// CHECK-32-EX-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP12]], 13405// CHECK-32-EX-NEXT:    store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]]3406// CHECK-32-EX-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]3407// CHECK-32-EX:       omp.body.continue:3408// CHECK-32-EX-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]3409// CHECK-32-EX:       omp.inner.for.inc:3410// CHECK-32-EX-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]]3411// CHECK-32-EX-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP13]], 13412// CHECK-32-EX-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]]3413// CHECK-32-EX-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]3414// CHECK-32-EX:       omp.inner.for.end:3415// CHECK-32-EX-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]3416// CHECK-32-EX:       omp.dispatch.inc:3417// CHECK-32-EX-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_LB]], align 43418// CHECK-32-EX-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 43419// CHECK-32-EX-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]3420// CHECK-32-EX-NEXT:    store i32 [[ADD5]], ptr [[DOTOMP_LB]], align 43421// CHECK-32-EX-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43422// CHECK-32-EX-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 43423// CHECK-32-EX-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]3424// CHECK-32-EX-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_UB]], align 43425// CHECK-32-EX-NEXT:    br label [[OMP_DISPATCH_COND]]3426// CHECK-32-EX:       omp.dispatch.end:3427// CHECK-32-EX-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP2]])3428// CHECK-32-EX-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 43429// CHECK-32-EX-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 03430// CHECK-32-EX-NEXT:    br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]3431// CHECK-32-EX:       .omp.final.then:3432// CHECK-32-EX-NEXT:    store i32 10, ptr [[I]], align 43433// CHECK-32-EX-NEXT:    br label [[DOTOMP_FINAL_DONE]]3434// CHECK-32-EX:       .omp.final.done:3435// CHECK-32-EX-NEXT:    ret void3436//3437//3438// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l503439// CHECK-32-EX-SAME: (ptr noalias [[DYN_PTR:%.*]], ptr nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[F:%.*]]) #[[ATTR0]] {3440// CHECK-32-EX-NEXT:  entry:3441// CHECK-32-EX-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 43442// CHECK-32-EX-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 43443// CHECK-32-EX-NEXT:    [[F_ADDR:%.*]] = alloca i32, align 43444// CHECK-32-EX-NEXT:    [[F_CASTED:%.*]] = alloca i32, align 43445// CHECK-32-EX-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 43446// CHECK-32-EX-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 43447// CHECK-32-EX-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 43448// CHECK-32-EX-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 43449// CHECK-32-EX-NEXT:    store i32 [[F]], ptr [[F_ADDR]], align 43450// CHECK-32-EX-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 43451// CHECK-32-EX-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l50_kernel_environment, ptr [[DYN_PTR]])3452// CHECK-32-EX-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -13453// CHECK-32-EX-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]3454// CHECK-32-EX:       user_code.entry:3455// CHECK-32-EX-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])3456// CHECK-32-EX-NEXT:    [[TMP3:%.*]] = load i32, ptr [[F_ADDR]], align 43457// CHECK-32-EX-NEXT:    store i32 [[TMP3]], ptr [[F_CASTED]], align 43458// CHECK-32-EX-NEXT:    [[TMP4:%.*]] = load i32, ptr [[F_CASTED]], align 43459// CHECK-32-EX-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 43460// CHECK-32-EX-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 43461// CHECK-32-EX-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l50_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i32 [[TMP4]]) #[[ATTR2]]3462// CHECK-32-EX-NEXT:    call void @__kmpc_target_deinit()3463// CHECK-32-EX-NEXT:    ret void3464// CHECK-32-EX:       worker.exit:3465// CHECK-32-EX-NEXT:    ret void3466//3467//3468// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l50_omp_outlined3469// CHECK-32-EX-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[F:%.*]]) #[[ATTR1]] {3470// CHECK-32-EX-NEXT:  entry:3471// CHECK-32-EX-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 43472// CHECK-32-EX-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 43473// CHECK-32-EX-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 43474// CHECK-32-EX-NEXT:    [[F_ADDR:%.*]] = alloca i32, align 43475// CHECK-32-EX-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 43476// CHECK-32-EX-NEXT:    [[TMP:%.*]] = alloca i32, align 43477// CHECK-32-EX-NEXT:    [[_TMP1:%.*]] = alloca i32, align 43478// CHECK-32-EX-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 43479// CHECK-32-EX-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 43480// CHECK-32-EX-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 43481// CHECK-32-EX-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 43482// CHECK-32-EX-NEXT:    [[K:%.*]] = alloca i32, align 43483// CHECK-32-EX-NEXT:    [[I:%.*]] = alloca i32, align 43484// CHECK-32-EX-NEXT:    [[J:%.*]] = alloca i32, align 43485// CHECK-32-EX-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 43486// CHECK-32-EX-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 43487// CHECK-32-EX-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 43488// CHECK-32-EX-NEXT:    store i32 [[F]], ptr [[F_ADDR]], align 43489// CHECK-32-EX-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 43490// CHECK-32-EX-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 43491// CHECK-32-EX-NEXT:    store i32 99, ptr [[DOTOMP_UB]], align 43492// CHECK-32-EX-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 43493// CHECK-32-EX-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 43494// CHECK-32-EX-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()3495// CHECK-32-EX-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 43496// CHECK-32-EX-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 43497// CHECK-32-EX-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])3498// CHECK-32-EX-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]3499// CHECK-32-EX:       omp.dispatch.cond:3500// CHECK-32-EX-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43501// CHECK-32-EX-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 993502// CHECK-32-EX-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]3503// CHECK-32-EX:       cond.true:3504// CHECK-32-EX-NEXT:    br label [[COND_END:%.*]]3505// CHECK-32-EX:       cond.false:3506// CHECK-32-EX-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43507// CHECK-32-EX-NEXT:    br label [[COND_END]]3508// CHECK-32-EX:       cond.end:3509// CHECK-32-EX-NEXT:    [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]3510// CHECK-32-EX-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 43511// CHECK-32-EX-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 43512// CHECK-32-EX-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 43513// CHECK-32-EX-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43514// CHECK-32-EX-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43515// CHECK-32-EX-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]3516// CHECK-32-EX-NEXT:    br i1 [[CMP2]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]3517// CHECK-32-EX:       omp.dispatch.body:3518// CHECK-32-EX-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]3519// CHECK-32-EX:       omp.inner.for.cond:3520// CHECK-32-EX-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28:![0-9]+]]3521// CHECK-32-EX-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP28]]3522// CHECK-32-EX-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]3523// CHECK-32-EX-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]3524// CHECK-32-EX:       omp.inner.for.body:3525// CHECK-32-EX-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]3526// CHECK-32-EX-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP10]], 103527// CHECK-32-EX-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 13528// CHECK-32-EX-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]3529// CHECK-32-EX-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP28]]3530// CHECK-32-EX-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]3531// CHECK-32-EX-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]3532// CHECK-32-EX-NEXT:    [[DIV4:%.*]] = sdiv i32 [[TMP12]], 103533// CHECK-32-EX-NEXT:    [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 103534// CHECK-32-EX-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL5]]3535// CHECK-32-EX-NEXT:    [[MUL6:%.*]] = mul nsw i32 [[SUB]], 13536// CHECK-32-EX-NEXT:    [[ADD7:%.*]] = add nsw i32 0, [[MUL6]]3537// CHECK-32-EX-NEXT:    store i32 [[ADD7]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP28]]3538// CHECK-32-EX-NEXT:    store i32 10, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP28]]3539// CHECK-32-EX-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP28]]3540// CHECK-32-EX-NEXT:    [[TMP14:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP28]]3541// CHECK-32-EX-NEXT:    [[TMP15:%.*]] = load i32, ptr [[F_ADDR]], align 4, !llvm.access.group [[ACC_GRP28]]3542// CHECK-32-EX-NEXT:    [[MUL8:%.*]] = mul nsw i32 [[TMP14]], [[TMP15]]3543// CHECK-32-EX-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP13]], [[MUL8]]3544// CHECK-32-EX-NEXT:    [[TMP16:%.*]] = load i32, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP28]]3545// CHECK-32-EX-NEXT:    [[ADD10:%.*]] = add nsw i32 [[ADD9]], [[TMP16]]3546// CHECK-32-EX-NEXT:    [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP28]]3547// CHECK-32-EX-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], i32 0, i32 [[TMP17]]3548// CHECK-32-EX-NEXT:    [[TMP18:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP28]]3549// CHECK-32-EX-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP18]]3550// CHECK-32-EX-NEXT:    store i32 [[ADD10]], ptr [[ARRAYIDX11]], align 4, !llvm.access.group [[ACC_GRP28]]3551// CHECK-32-EX-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]3552// CHECK-32-EX:       omp.body.continue:3553// CHECK-32-EX-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]3554// CHECK-32-EX:       omp.inner.for.inc:3555// CHECK-32-EX-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]3556// CHECK-32-EX-NEXT:    [[ADD12:%.*]] = add nsw i32 [[TMP19]], 13557// CHECK-32-EX-NEXT:    store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]3558// CHECK-32-EX-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]3559// CHECK-32-EX:       omp.inner.for.end:3560// CHECK-32-EX-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]3561// CHECK-32-EX:       omp.dispatch.inc:3562// CHECK-32-EX-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_LB]], align 43563// CHECK-32-EX-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 43564// CHECK-32-EX-NEXT:    [[ADD13:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]3565// CHECK-32-EX-NEXT:    store i32 [[ADD13]], ptr [[DOTOMP_LB]], align 43566// CHECK-32-EX-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43567// CHECK-32-EX-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 43568// CHECK-32-EX-NEXT:    [[ADD14:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]3569// CHECK-32-EX-NEXT:    store i32 [[ADD14]], ptr [[DOTOMP_UB]], align 43570// CHECK-32-EX-NEXT:    br label [[OMP_DISPATCH_COND]]3571// CHECK-32-EX:       omp.dispatch.end:3572// CHECK-32-EX-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP2]])3573// CHECK-32-EX-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 43574// CHECK-32-EX-NEXT:    [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 03575// CHECK-32-EX-NEXT:    br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]3576// CHECK-32-EX:       .omp.final.then:3577// CHECK-32-EX-NEXT:    store i32 10, ptr [[I]], align 43578// CHECK-32-EX-NEXT:    store i32 10, ptr [[J]], align 43579// CHECK-32-EX-NEXT:    br label [[DOTOMP_FINAL_DONE]]3580// CHECK-32-EX:       .omp.final.done:3581// CHECK-32-EX-NEXT:    ret void3582//3583