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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _2// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefixes=CHECK13// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s4// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK15 6// RUN: %clang_cc1 -verify -fopenmp -fopenmp-enable-irbuilder -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefixes=CHECK1-IRBUILDER7// RUN: %clang_cc1 -fopenmp -fopenmp-enable-irbuilder -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s8// RUN: %clang_cc1 -fopenmp -fopenmp-enable-irbuilder -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK1-IRBUILDER9 10// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -fopenmp-version=45 -o - | FileCheck %s --check-prefixes=CHECK311// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -fopenmp-version=45 -o %t %s12// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK313 14// RUN: %clang_cc1 -verify -fopenmp -fopenmp-enable-irbuilder -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -fopenmp-version=45 -o - | FileCheck %s --check-prefixes=CHECK3-IRBUILDER15// RUN: %clang_cc1 -fopenmp -fopenmp-enable-irbuilder -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -fopenmp-version=45 -o %t %s16// RUN: %clang_cc1 -fopenmp -fopenmp-enable-irbuilder -fopenmp-version=45 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK3-IRBUILDER17 18// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK519// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s20// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK521// expected-no-diagnostics22#ifndef HEADER23#define HEADER24 25void static_not_chunked(float *a, float *b, float *c, float *d) {26  #pragma omp for schedule(static) ordered27 28// Loop header29 30  for (int i = 32000000; i > 33; i += -7) {31// Start of body: calculate i from IV:32 33// ... start of ordered region ...34// ... loop body ...35// End of body: store into a[i]:36// ... end of ordered region ...37    #pragma omp ordered38    a[i] = b[i] * c[i] * d[i];39  }40}41 42void dynamic1(float *a, float *b, float *c, float *d) {43  #pragma omp for schedule(dynamic) ordered44 45// Loop header46 47  for (unsigned long long i = 131071; i < 2147483647; i += 127) {48// Start of body: calculate i from IV:49 50// ... start of ordered region ...51// ... loop body ...52// End of body: store into a[i]:53// ... end of ordered region ...54    #pragma omp ordered threads55    a[i] = b[i] * c[i] * d[i];56 57// ... end iteration for ordered loop ...58  }59}60 61void test_auto(float *a, float *b, float *c, float *d) {62  unsigned int x = 0;63  unsigned int y = 0;64  #pragma omp for schedule(auto) collapse(2) ordered65 66// Loop header67 68// FIXME: When the iteration count of some nested loop is not a known constant,69// we should pre-calculate it, like we do for the total number of iterations!70  for (char i = static_cast<char>(y); i <= '9'; ++i)71    for (x = 11; x > 0; --x) {72// Start of body: indices are calculated from IV:73 74// ... start of ordered region ...75// ... loop body ...76// End of body: store into a[i]:77// ... end of ordered region ...78    #pragma omp ordered79    a[i] = b[i] * c[i] * d[i];80 81// ... end iteration for ordered loop ...82  }83}84 85void runtime(float *a, float *b, float *c, float *d) {86  int x = 0;87  #pragma omp for collapse(2) schedule(runtime) ordered88 89// Loop header90 91  for (unsigned char i = '0' ; i <= '9'; ++i)92    for (x = -10; x < 10; ++x) {93// Start of body: indices are calculated from IV:94 95// ... start of ordered region ...96// ... loop body ...97// End of body: store into a[i]:98// ... end of ordered region ...99    #pragma omp ordered threads100    a[i] = b[i] * c[i] * d[i];101 102// ... end iteration for ordered loop ...103  }104}105 106float f[10];107void foo_simd(int low, int up) {108#pragma omp simd109  for (int i = low; i < up; ++i) {110    f[i] = 0.0;111#pragma omp ordered simd112    f[i] = 1.0;113  }114#pragma omp for simd ordered115  for (int i = low; i < up; ++i) {116    f[i] = 0.0;117#pragma omp ordered simd118    f[i] = 1.0;119  }120}121 122 123#endif // HEADER124 125// CHECK1-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_126// CHECK1-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] {127// CHECK1-NEXT:  entry:128// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8129// CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8130// CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8131// CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8132// CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4133// CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4134// CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4135// CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4136// CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4137// CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4138// CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4139// CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])140// CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8141// CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8142// CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8143// CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8144// CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4145// CHECK1-NEXT:    store i32 4571423, ptr [[DOTOMP_UB]], align 4146// CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4147// CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4148// CHECK1-NEXT:    call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP0]], i32 66, i32 0, i32 4571423, i32 1, i32 1)149// CHECK1-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]150// CHECK1:       omp.dispatch.cond:151// CHECK1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])152// CHECK1-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0153// CHECK1-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]154// CHECK1:       omp.dispatch.body:155// CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4156// CHECK1-NEXT:    store i32 [[TMP2]], ptr [[DOTOMP_IV]], align 4157// CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]158// CHECK1:       omp.inner.for.cond:159// CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4160// CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4161// CHECK1-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP3]], [[TMP4]]162// CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]163// CHECK1:       omp.inner.for.body:164// CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4165// CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP5]], 7166// CHECK1-NEXT:    [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]167// CHECK1-NEXT:    store i32 [[SUB]], ptr [[I]], align 4168// CHECK1-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[TMP0]])169// CHECK1-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[B_ADDR]], align 8170// CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[I]], align 4171// CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64172// CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP6]], i64 [[IDXPROM]]173// CHECK1-NEXT:    [[TMP8:%.*]] = load float, ptr [[ARRAYIDX]], align 4174// CHECK1-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[C_ADDR]], align 8175// CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[I]], align 4176// CHECK1-NEXT:    [[IDXPROM1:%.*]] = sext i32 [[TMP10]] to i64177// CHECK1-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP9]], i64 [[IDXPROM1]]178// CHECK1-NEXT:    [[TMP11:%.*]] = load float, ptr [[ARRAYIDX2]], align 4179// CHECK1-NEXT:    [[MUL3:%.*]] = fmul float [[TMP8]], [[TMP11]]180// CHECK1-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[D_ADDR]], align 8181// CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 4182// CHECK1-NEXT:    [[IDXPROM4:%.*]] = sext i32 [[TMP13]] to i64183// CHECK1-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[IDXPROM4]]184// CHECK1-NEXT:    [[TMP14:%.*]] = load float, ptr [[ARRAYIDX5]], align 4185// CHECK1-NEXT:    [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP14]]186// CHECK1-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[A_ADDR]], align 8187// CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I]], align 4188// CHECK1-NEXT:    [[IDXPROM7:%.*]] = sext i32 [[TMP16]] to i64189// CHECK1-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[IDXPROM7]]190// CHECK1-NEXT:    store float [[MUL6]], ptr [[ARRAYIDX8]], align 4191// CHECK1-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[TMP0]])192// CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]193// CHECK1:       omp.body.continue:194// CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]195// CHECK1:       omp.inner.for.inc:196// CHECK1-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4197// CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP17]], 1198// CHECK1-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4199// CHECK1-NEXT:    call void @__kmpc_dispatch_fini_4(ptr @[[GLOB1]], i32 [[TMP0]])200// CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]201// CHECK1:       omp.inner.for.end:202// CHECK1-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]203// CHECK1:       omp.dispatch.inc:204// CHECK1-NEXT:    br label [[OMP_DISPATCH_COND]]205// CHECK1:       omp.dispatch.end:206// CHECK1-NEXT:    call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP0]])207// CHECK1-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2:[0-9]+]], i32 [[TMP0]])208// CHECK1-NEXT:    ret void209//210//211// CHECK1-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_212// CHECK1-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {213// CHECK1-NEXT:  entry:214// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8215// CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8216// CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8217// CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8218// CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8219// CHECK1-NEXT:    [[TMP:%.*]] = alloca i64, align 8220// CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8221// CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8222// CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8223// CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4224// CHECK1-NEXT:    [[I:%.*]] = alloca i64, align 8225// CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])226// CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8227// CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8228// CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8229// CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8230// CHECK1-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8231// CHECK1-NEXT:    store i64 16908287, ptr [[DOTOMP_UB]], align 8232// CHECK1-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8233// CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4234// CHECK1-NEXT:    call void @__kmpc_dispatch_init_8u(ptr @[[GLOB1]], i32 [[TMP0]], i32 1073741891, i64 0, i64 16908287, i64 1, i64 1)235// CHECK1-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]236// CHECK1:       omp.dispatch.cond:237// CHECK1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_8u(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])238// CHECK1-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0239// CHECK1-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]240// CHECK1:       omp.dispatch.body:241// CHECK1-NEXT:    [[TMP2:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8242// CHECK1-NEXT:    store i64 [[TMP2]], ptr [[DOTOMP_IV]], align 8243// CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]244// CHECK1:       omp.inner.for.cond:245// CHECK1-NEXT:    [[TMP3:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8246// CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8247// CHECK1-NEXT:    [[ADD:%.*]] = add i64 [[TMP4]], 1248// CHECK1-NEXT:    [[CMP:%.*]] = icmp ult i64 [[TMP3]], [[ADD]]249// CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]250// CHECK1:       omp.inner.for.body:251// CHECK1-NEXT:    [[TMP5:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8252// CHECK1-NEXT:    [[MUL:%.*]] = mul i64 [[TMP5]], 127253// CHECK1-NEXT:    [[ADD1:%.*]] = add i64 131071, [[MUL]]254// CHECK1-NEXT:    store i64 [[ADD1]], ptr [[I]], align 8255// CHECK1-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[TMP0]])256// CHECK1-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[B_ADDR]], align 8257// CHECK1-NEXT:    [[TMP7:%.*]] = load i64, ptr [[I]], align 8258// CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP6]], i64 [[TMP7]]259// CHECK1-NEXT:    [[TMP8:%.*]] = load float, ptr [[ARRAYIDX]], align 4260// CHECK1-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[C_ADDR]], align 8261// CHECK1-NEXT:    [[TMP10:%.*]] = load i64, ptr [[I]], align 8262// CHECK1-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw float, ptr [[TMP9]], i64 [[TMP10]]263// CHECK1-NEXT:    [[TMP11:%.*]] = load float, ptr [[ARRAYIDX2]], align 4264// CHECK1-NEXT:    [[MUL3:%.*]] = fmul float [[TMP8]], [[TMP11]]265// CHECK1-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[D_ADDR]], align 8266// CHECK1-NEXT:    [[TMP13:%.*]] = load i64, ptr [[I]], align 8267// CHECK1-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw float, ptr [[TMP12]], i64 [[TMP13]]268// CHECK1-NEXT:    [[TMP14:%.*]] = load float, ptr [[ARRAYIDX4]], align 4269// CHECK1-NEXT:    [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP14]]270// CHECK1-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[A_ADDR]], align 8271// CHECK1-NEXT:    [[TMP16:%.*]] = load i64, ptr [[I]], align 8272// CHECK1-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds nuw float, ptr [[TMP15]], i64 [[TMP16]]273// CHECK1-NEXT:    store float [[MUL5]], ptr [[ARRAYIDX6]], align 4274// CHECK1-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[TMP0]])275// CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]276// CHECK1:       omp.body.continue:277// CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]278// CHECK1:       omp.inner.for.inc:279// CHECK1-NEXT:    [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8280// CHECK1-NEXT:    [[ADD7:%.*]] = add i64 [[TMP17]], 1281// CHECK1-NEXT:    store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8282// CHECK1-NEXT:    call void @__kmpc_dispatch_fini_8u(ptr @[[GLOB1]], i32 [[TMP0]])283// CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]284// CHECK1:       omp.inner.for.end:285// CHECK1-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]286// CHECK1:       omp.dispatch.inc:287// CHECK1-NEXT:    br label [[OMP_DISPATCH_COND]]288// CHECK1:       omp.dispatch.end:289// CHECK1-NEXT:    call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP0]])290// CHECK1-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2]], i32 [[TMP0]])291// CHECK1-NEXT:    ret void292//293//294// CHECK1-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_295// CHECK1-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {296// CHECK1-NEXT:  entry:297// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8298// CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8299// CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8300// CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8301// CHECK1-NEXT:    [[X:%.*]] = alloca i32, align 4302// CHECK1-NEXT:    [[Y:%.*]] = alloca i32, align 4303// CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8304// CHECK1-NEXT:    [[TMP:%.*]] = alloca i8, align 1305// CHECK1-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4306// CHECK1-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1307// CHECK1-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8308// CHECK1-NEXT:    [[I:%.*]] = alloca i8, align 1309// CHECK1-NEXT:    [[X6:%.*]] = alloca i32, align 4310// CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8311// CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8312// CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8313// CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4314// CHECK1-NEXT:    [[I8:%.*]] = alloca i8, align 1315// CHECK1-NEXT:    [[X9:%.*]] = alloca i32, align 4316// CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])317// CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8318// CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8319// CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8320// CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8321// CHECK1-NEXT:    store i32 0, ptr [[X]], align 4322// CHECK1-NEXT:    store i32 0, ptr [[Y]], align 4323// CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[Y]], align 4324// CHECK1-NEXT:    [[CONV:%.*]] = trunc i32 [[TMP1]] to i8325// CHECK1-NEXT:    store i8 [[CONV]], ptr [[DOTCAPTURE_EXPR_]], align 1326// CHECK1-NEXT:    [[TMP2:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1327// CHECK1-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP2]] to i32328// CHECK1-NEXT:    [[SUB:%.*]] = sub i32 57, [[CONV3]]329// CHECK1-NEXT:    [[ADD:%.*]] = add i32 [[SUB]], 1330// CHECK1-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1331// CHECK1-NEXT:    [[CONV4:%.*]] = zext i32 [[DIV]] to i64332// CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11333// CHECK1-NEXT:    [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1334// CHECK1-NEXT:    store i64 [[SUB5]], ptr [[DOTCAPTURE_EXPR_2]], align 8335// CHECK1-NEXT:    [[TMP3:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1336// CHECK1-NEXT:    store i8 [[TMP3]], ptr [[I]], align 1337// CHECK1-NEXT:    store i32 11, ptr [[X6]], align 4338// CHECK1-NEXT:    [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1339// CHECK1-NEXT:    [[CONV7:%.*]] = sext i8 [[TMP4]] to i32340// CHECK1-NEXT:    [[CMP:%.*]] = icmp sle i32 [[CONV7]], 57341// CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]342// CHECK1:       omp.precond.then:343// CHECK1-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8344// CHECK1-NEXT:    [[TMP5:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8345// CHECK1-NEXT:    store i64 [[TMP5]], ptr [[DOTOMP_UB]], align 8346// CHECK1-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8347// CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4348// CHECK1-NEXT:    [[TMP6:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8349// CHECK1-NEXT:    call void @__kmpc_dispatch_init_8(ptr @[[GLOB1]], i32 [[TMP0]], i32 1073741894, i64 0, i64 [[TMP6]], i64 1, i64 1)350// CHECK1-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]351// CHECK1:       omp.dispatch.cond:352// CHECK1-NEXT:    [[TMP7:%.*]] = call i32 @__kmpc_dispatch_next_8(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])353// CHECK1-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0354// CHECK1-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]355// CHECK1:       omp.dispatch.body:356// CHECK1-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8357// CHECK1-NEXT:    store i64 [[TMP8]], ptr [[DOTOMP_IV]], align 8358// CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]359// CHECK1:       omp.inner.for.cond:360// CHECK1-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8361// CHECK1-NEXT:    [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8362// CHECK1-NEXT:    [[CMP10:%.*]] = icmp sle i64 [[TMP9]], [[TMP10]]363// CHECK1-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]364// CHECK1:       omp.inner.for.body:365// CHECK1-NEXT:    [[TMP11:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1366// CHECK1-NEXT:    [[CONV11:%.*]] = sext i8 [[TMP11]] to i64367// CHECK1-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8368// CHECK1-NEXT:    [[DIV12:%.*]] = sdiv i64 [[TMP12]], 11369// CHECK1-NEXT:    [[MUL13:%.*]] = mul nsw i64 [[DIV12]], 1370// CHECK1-NEXT:    [[ADD14:%.*]] = add nsw i64 [[CONV11]], [[MUL13]]371// CHECK1-NEXT:    [[CONV15:%.*]] = trunc i64 [[ADD14]] to i8372// CHECK1-NEXT:    store i8 [[CONV15]], ptr [[I8]], align 1373// CHECK1-NEXT:    [[TMP13:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8374// CHECK1-NEXT:    [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8375// CHECK1-NEXT:    [[DIV16:%.*]] = sdiv i64 [[TMP14]], 11376// CHECK1-NEXT:    [[MUL17:%.*]] = mul nsw i64 [[DIV16]], 11377// CHECK1-NEXT:    [[SUB18:%.*]] = sub nsw i64 [[TMP13]], [[MUL17]]378// CHECK1-NEXT:    [[MUL19:%.*]] = mul nsw i64 [[SUB18]], 1379// CHECK1-NEXT:    [[SUB20:%.*]] = sub nsw i64 11, [[MUL19]]380// CHECK1-NEXT:    [[CONV21:%.*]] = trunc i64 [[SUB20]] to i32381// CHECK1-NEXT:    store i32 [[CONV21]], ptr [[X9]], align 4382// CHECK1-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[TMP0]])383// CHECK1-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[B_ADDR]], align 8384// CHECK1-NEXT:    [[TMP16:%.*]] = load i8, ptr [[I8]], align 1385// CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i8 [[TMP16]] to i64386// CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[IDXPROM]]387// CHECK1-NEXT:    [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4388// CHECK1-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[C_ADDR]], align 8389// CHECK1-NEXT:    [[TMP19:%.*]] = load i8, ptr [[I8]], align 1390// CHECK1-NEXT:    [[IDXPROM22:%.*]] = sext i8 [[TMP19]] to i64391// CHECK1-NEXT:    [[ARRAYIDX23:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[IDXPROM22]]392// CHECK1-NEXT:    [[TMP20:%.*]] = load float, ptr [[ARRAYIDX23]], align 4393// CHECK1-NEXT:    [[MUL24:%.*]] = fmul float [[TMP17]], [[TMP20]]394// CHECK1-NEXT:    [[TMP21:%.*]] = load ptr, ptr [[D_ADDR]], align 8395// CHECK1-NEXT:    [[TMP22:%.*]] = load i8, ptr [[I8]], align 1396// CHECK1-NEXT:    [[IDXPROM25:%.*]] = sext i8 [[TMP22]] to i64397// CHECK1-NEXT:    [[ARRAYIDX26:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i64 [[IDXPROM25]]398// CHECK1-NEXT:    [[TMP23:%.*]] = load float, ptr [[ARRAYIDX26]], align 4399// CHECK1-NEXT:    [[MUL27:%.*]] = fmul float [[MUL24]], [[TMP23]]400// CHECK1-NEXT:    [[TMP24:%.*]] = load ptr, ptr [[A_ADDR]], align 8401// CHECK1-NEXT:    [[TMP25:%.*]] = load i8, ptr [[I8]], align 1402// CHECK1-NEXT:    [[IDXPROM28:%.*]] = sext i8 [[TMP25]] to i64403// CHECK1-NEXT:    [[ARRAYIDX29:%.*]] = getelementptr inbounds float, ptr [[TMP24]], i64 [[IDXPROM28]]404// CHECK1-NEXT:    store float [[MUL27]], ptr [[ARRAYIDX29]], align 4405// CHECK1-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[TMP0]])406// CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]407// CHECK1:       omp.body.continue:408// CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]409// CHECK1:       omp.inner.for.inc:410// CHECK1-NEXT:    [[TMP26:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8411// CHECK1-NEXT:    [[ADD30:%.*]] = add nsw i64 [[TMP26]], 1412// CHECK1-NEXT:    store i64 [[ADD30]], ptr [[DOTOMP_IV]], align 8413// CHECK1-NEXT:    call void @__kmpc_dispatch_fini_8(ptr @[[GLOB1]], i32 [[TMP0]])414// CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]415// CHECK1:       omp.inner.for.end:416// CHECK1-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]417// CHECK1:       omp.dispatch.inc:418// CHECK1-NEXT:    br label [[OMP_DISPATCH_COND]]419// CHECK1:       omp.dispatch.end:420// CHECK1-NEXT:    call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP0]])421// CHECK1-NEXT:    br label [[OMP_PRECOND_END]]422// CHECK1:       omp.precond.end:423// CHECK1-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2]], i32 [[TMP0]])424// CHECK1-NEXT:    ret void425//426//427// CHECK1-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_428// CHECK1-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {429// CHECK1-NEXT:  entry:430// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8431// CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8432// CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8433// CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8434// CHECK1-NEXT:    [[X:%.*]] = alloca i32, align 4435// CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4436// CHECK1-NEXT:    [[TMP:%.*]] = alloca i8, align 1437// CHECK1-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4438// CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4439// CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4440// CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4441// CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4442// CHECK1-NEXT:    [[I:%.*]] = alloca i8, align 1443// CHECK1-NEXT:    [[X2:%.*]] = alloca i32, align 4444// CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])445// CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8446// CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8447// CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8448// CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8449// CHECK1-NEXT:    store i32 0, ptr [[X]], align 4450// CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4451// CHECK1-NEXT:    store i32 199, ptr [[DOTOMP_UB]], align 4452// CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4453// CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4454// CHECK1-NEXT:    call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP0]], i32 1073741893, i32 0, i32 199, i32 1, i32 1)455// CHECK1-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]456// CHECK1:       omp.dispatch.cond:457// CHECK1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])458// CHECK1-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0459// CHECK1-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]460// CHECK1:       omp.dispatch.body:461// CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4462// CHECK1-NEXT:    store i32 [[TMP2]], ptr [[DOTOMP_IV]], align 4463// CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]464// CHECK1:       omp.inner.for.cond:465// CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4466// CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4467// CHECK1-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP3]], [[TMP4]]468// CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]469// CHECK1:       omp.inner.for.body:470// CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4471// CHECK1-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP5]], 20472// CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 1473// CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 48, [[MUL]]474// CHECK1-NEXT:    [[CONV:%.*]] = trunc i32 [[ADD]] to i8475// CHECK1-NEXT:    store i8 [[CONV]], ptr [[I]], align 1476// CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4477// CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4478// CHECK1-NEXT:    [[DIV3:%.*]] = sdiv i32 [[TMP7]], 20479// CHECK1-NEXT:    [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 20480// CHECK1-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP6]], [[MUL4]]481// CHECK1-NEXT:    [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1482// CHECK1-NEXT:    [[ADD6:%.*]] = add nsw i32 -10, [[MUL5]]483// CHECK1-NEXT:    store i32 [[ADD6]], ptr [[X2]], align 4484// CHECK1-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[TMP0]])485// CHECK1-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[B_ADDR]], align 8486// CHECK1-NEXT:    [[TMP9:%.*]] = load i8, ptr [[I]], align 1487// CHECK1-NEXT:    [[IDXPROM:%.*]] = zext i8 [[TMP9]] to i64488// CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP8]], i64 [[IDXPROM]]489// CHECK1-NEXT:    [[TMP10:%.*]] = load float, ptr [[ARRAYIDX]], align 4490// CHECK1-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[C_ADDR]], align 8491// CHECK1-NEXT:    [[TMP12:%.*]] = load i8, ptr [[I]], align 1492// CHECK1-NEXT:    [[IDXPROM7:%.*]] = zext i8 [[TMP12]] to i64493// CHECK1-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds nuw float, ptr [[TMP11]], i64 [[IDXPROM7]]494// CHECK1-NEXT:    [[TMP13:%.*]] = load float, ptr [[ARRAYIDX8]], align 4495// CHECK1-NEXT:    [[MUL9:%.*]] = fmul float [[TMP10]], [[TMP13]]496// CHECK1-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[D_ADDR]], align 8497// CHECK1-NEXT:    [[TMP15:%.*]] = load i8, ptr [[I]], align 1498// CHECK1-NEXT:    [[IDXPROM10:%.*]] = zext i8 [[TMP15]] to i64499// CHECK1-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds nuw float, ptr [[TMP14]], i64 [[IDXPROM10]]500// CHECK1-NEXT:    [[TMP16:%.*]] = load float, ptr [[ARRAYIDX11]], align 4501// CHECK1-NEXT:    [[MUL12:%.*]] = fmul float [[MUL9]], [[TMP16]]502// CHECK1-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[A_ADDR]], align 8503// CHECK1-NEXT:    [[TMP18:%.*]] = load i8, ptr [[I]], align 1504// CHECK1-NEXT:    [[IDXPROM13:%.*]] = zext i8 [[TMP18]] to i64505// CHECK1-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds nuw float, ptr [[TMP17]], i64 [[IDXPROM13]]506// CHECK1-NEXT:    store float [[MUL12]], ptr [[ARRAYIDX14]], align 4507// CHECK1-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[TMP0]])508// CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]509// CHECK1:       omp.body.continue:510// CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]511// CHECK1:       omp.inner.for.inc:512// CHECK1-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4513// CHECK1-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP19]], 1514// CHECK1-NEXT:    store i32 [[ADD15]], ptr [[DOTOMP_IV]], align 4515// CHECK1-NEXT:    call void @__kmpc_dispatch_fini_4(ptr @[[GLOB1]], i32 [[TMP0]])516// CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]517// CHECK1:       omp.inner.for.end:518// CHECK1-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]519// CHECK1:       omp.dispatch.inc:520// CHECK1-NEXT:    br label [[OMP_DISPATCH_COND]]521// CHECK1:       omp.dispatch.end:522// CHECK1-NEXT:    call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP0]])523// CHECK1-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2]], i32 [[TMP0]])524// CHECK1-NEXT:    ret void525//526//527// CHECK1-LABEL: define {{[^@]+}}@_Z8foo_simdii528// CHECK1-SAME: (i32 noundef [[LOW:%.*]], i32 noundef [[UP:%.*]]) #[[ATTR3:[0-9]+]] {529// CHECK1-NEXT:  entry:530// CHECK1-NEXT:    [[LOW_ADDR:%.*]] = alloca i32, align 4531// CHECK1-NEXT:    [[UP_ADDR:%.*]] = alloca i32, align 4532// CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4533// CHECK1-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4534// CHECK1-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4535// CHECK1-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4536// CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4537// CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4538// CHECK1-NEXT:    [[I5:%.*]] = alloca i32, align 4539// CHECK1-NEXT:    [[DOTOMP_IV16:%.*]] = alloca i32, align 4540// CHECK1-NEXT:    [[_TMP17:%.*]] = alloca i32, align 4541// CHECK1-NEXT:    [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4542// CHECK1-NEXT:    [[DOTCAPTURE_EXPR_19:%.*]] = alloca i32, align 4543// CHECK1-NEXT:    [[DOTCAPTURE_EXPR_20:%.*]] = alloca i32, align 4544// CHECK1-NEXT:    [[I26:%.*]] = alloca i32, align 4545// CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4546// CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4547// CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4548// CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4549// CHECK1-NEXT:    [[I28:%.*]] = alloca i32, align 4550// CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])551// CHECK1-NEXT:    store i32 [[LOW]], ptr [[LOW_ADDR]], align 4552// CHECK1-NEXT:    store i32 [[UP]], ptr [[UP_ADDR]], align 4553// CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[LOW_ADDR]], align 4554// CHECK1-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4555// CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[UP_ADDR]], align 4556// CHECK1-NEXT:    store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_1]], align 4557// CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4558// CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4559// CHECK1-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]560// CHECK1-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1561// CHECK1-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1562// CHECK1-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1563// CHECK1-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 1564// CHECK1-NEXT:    store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4565// CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4566// CHECK1-NEXT:    store i32 [[TMP5]], ptr [[I]], align 4567// CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4568// CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4569// CHECK1-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]570// CHECK1-NEXT:    br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]571// CHECK1:       simd.if.then:572// CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IV]], align 4573// CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]574// CHECK1:       omp.inner.for.cond:575// CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4576// CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4577// CHECK1-NEXT:    [[ADD6:%.*]] = add i32 [[TMP9]], 1578// CHECK1-NEXT:    [[CMP7:%.*]] = icmp ult i32 [[TMP8]], [[ADD6]]579// CHECK1-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]580// CHECK1:       omp.inner.for.body:581// CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4582// CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4583// CHECK1-NEXT:    [[MUL:%.*]] = mul i32 [[TMP11]], 1584// CHECK1-NEXT:    [[ADD8:%.*]] = add i32 [[TMP10]], [[MUL]]585// CHECK1-NEXT:    store i32 [[ADD8]], ptr [[I5]], align 4586// CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[I5]], align 4587// CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64588// CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]]589// CHECK1-NEXT:    store float 0.000000e+00, ptr [[ARRAYIDX]], align 4590// CHECK1-NEXT:    call void @__captured_stmt(ptr [[I5]])591// CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]592// CHECK1:       omp.body.continue:593// CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]594// CHECK1:       omp.inner.for.inc:595// CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4596// CHECK1-NEXT:    [[ADD9:%.*]] = add i32 [[TMP13]], 1597// CHECK1-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4598// CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]599// CHECK1:       omp.inner.for.end:600// CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4601// CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4602// CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4603// CHECK1-NEXT:    [[SUB10:%.*]] = sub i32 [[TMP15]], [[TMP16]]604// CHECK1-NEXT:    [[SUB11:%.*]] = sub i32 [[SUB10]], 1605// CHECK1-NEXT:    [[ADD12:%.*]] = add i32 [[SUB11]], 1606// CHECK1-NEXT:    [[DIV13:%.*]] = udiv i32 [[ADD12]], 1607// CHECK1-NEXT:    [[MUL14:%.*]] = mul i32 [[DIV13]], 1608// CHECK1-NEXT:    [[ADD15:%.*]] = add i32 [[TMP14]], [[MUL14]]609// CHECK1-NEXT:    store i32 [[ADD15]], ptr [[I5]], align 4610// CHECK1-NEXT:    br label [[SIMD_IF_END]]611// CHECK1:       simd.if.end:612// CHECK1-NEXT:    [[TMP17:%.*]] = load i32, ptr [[LOW_ADDR]], align 4613// CHECK1-NEXT:    store i32 [[TMP17]], ptr [[DOTCAPTURE_EXPR_18]], align 4614// CHECK1-NEXT:    [[TMP18:%.*]] = load i32, ptr [[UP_ADDR]], align 4615// CHECK1-NEXT:    store i32 [[TMP18]], ptr [[DOTCAPTURE_EXPR_19]], align 4616// CHECK1-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 4617// CHECK1-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4618// CHECK1-NEXT:    [[SUB21:%.*]] = sub i32 [[TMP19]], [[TMP20]]619// CHECK1-NEXT:    [[SUB22:%.*]] = sub i32 [[SUB21]], 1620// CHECK1-NEXT:    [[ADD23:%.*]] = add i32 [[SUB22]], 1621// CHECK1-NEXT:    [[DIV24:%.*]] = udiv i32 [[ADD23]], 1622// CHECK1-NEXT:    [[SUB25:%.*]] = sub i32 [[DIV24]], 1623// CHECK1-NEXT:    store i32 [[SUB25]], ptr [[DOTCAPTURE_EXPR_20]], align 4624// CHECK1-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4625// CHECK1-NEXT:    store i32 [[TMP21]], ptr [[I26]], align 4626// CHECK1-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4627// CHECK1-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 4628// CHECK1-NEXT:    [[CMP27:%.*]] = icmp slt i32 [[TMP22]], [[TMP23]]629// CHECK1-NEXT:    br i1 [[CMP27]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]630// CHECK1:       omp.precond.then:631// CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4632// CHECK1-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_20]], align 4633// CHECK1-NEXT:    store i32 [[TMP24]], ptr [[DOTOMP_UB]], align 4634// CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4635// CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4636// CHECK1-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_20]], align 4637// CHECK1-NEXT:    call void @__kmpc_dispatch_init_4u(ptr @[[GLOB1]], i32 [[TMP0]], i32 66, i32 0, i32 [[TMP25]], i32 1, i32 1)638// CHECK1-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]639// CHECK1:       omp.dispatch.cond:640// CHECK1-NEXT:    [[TMP26:%.*]] = call i32 @__kmpc_dispatch_next_4u(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])641// CHECK1-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP26]], 0642// CHECK1-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]643// CHECK1:       omp.dispatch.body:644// CHECK1-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4645// CHECK1-NEXT:    store i32 [[TMP27]], ptr [[DOTOMP_IV16]], align 4646// CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND29:%.*]]647// CHECK1:       omp.inner.for.cond29:648// CHECK1-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTOMP_IV16]], align 4649// CHECK1-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4650// CHECK1-NEXT:    [[ADD30:%.*]] = add i32 [[TMP29]], 1651// CHECK1-NEXT:    [[CMP31:%.*]] = icmp ult i32 [[TMP28]], [[ADD30]]652// CHECK1-NEXT:    br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END40:%.*]]653// CHECK1:       omp.inner.for.body32:654// CHECK1-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4655// CHECK1-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IV16]], align 4656// CHECK1-NEXT:    [[MUL33:%.*]] = mul i32 [[TMP31]], 1657// CHECK1-NEXT:    [[ADD34:%.*]] = add i32 [[TMP30]], [[MUL33]]658// CHECK1-NEXT:    store i32 [[ADD34]], ptr [[I28]], align 4659// CHECK1-NEXT:    [[TMP32:%.*]] = load i32, ptr [[I28]], align 4660// CHECK1-NEXT:    [[IDXPROM35:%.*]] = sext i32 [[TMP32]] to i64661// CHECK1-NEXT:    [[ARRAYIDX36:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM35]]662// CHECK1-NEXT:    store float 0.000000e+00, ptr [[ARRAYIDX36]], align 4663// CHECK1-NEXT:    call void @__captured_stmt.1(ptr [[I28]])664// CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE37:%.*]]665// CHECK1:       omp.body.continue37:666// CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC38:%.*]]667// CHECK1:       omp.inner.for.inc38:668// CHECK1-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTOMP_IV16]], align 4669// CHECK1-NEXT:    [[ADD39:%.*]] = add i32 [[TMP33]], 1670// CHECK1-NEXT:    store i32 [[ADD39]], ptr [[DOTOMP_IV16]], align 4671// CHECK1-NEXT:    call void @__kmpc_dispatch_fini_4u(ptr @[[GLOB1]], i32 [[TMP0]])672// CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP5:![0-9]+]]673// CHECK1:       omp.inner.for.end40:674// CHECK1-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]675// CHECK1:       omp.dispatch.inc:676// CHECK1-NEXT:    br label [[OMP_DISPATCH_COND]]677// CHECK1:       omp.dispatch.end:678// CHECK1-NEXT:    call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP0]])679// CHECK1-NEXT:    [[TMP34:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4680// CHECK1-NEXT:    [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0681// CHECK1-NEXT:    br i1 [[TMP35]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]682// CHECK1:       .omp.final.then:683// CHECK1-NEXT:    [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4684// CHECK1-NEXT:    [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 4685// CHECK1-NEXT:    [[TMP38:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4686// CHECK1-NEXT:    [[SUB41:%.*]] = sub i32 [[TMP37]], [[TMP38]]687// CHECK1-NEXT:    [[SUB42:%.*]] = sub i32 [[SUB41]], 1688// CHECK1-NEXT:    [[ADD43:%.*]] = add i32 [[SUB42]], 1689// CHECK1-NEXT:    [[DIV44:%.*]] = udiv i32 [[ADD43]], 1690// CHECK1-NEXT:    [[MUL45:%.*]] = mul i32 [[DIV44]], 1691// CHECK1-NEXT:    [[ADD46:%.*]] = add i32 [[TMP36]], [[MUL45]]692// CHECK1-NEXT:    store i32 [[ADD46]], ptr [[I28]], align 4693// CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]694// CHECK1:       .omp.final.done:695// CHECK1-NEXT:    br label [[OMP_PRECOND_END]]696// CHECK1:       omp.precond.end:697// CHECK1-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2]], i32 [[TMP0]])698// CHECK1-NEXT:    ret void699//700//701// CHECK1-LABEL: define {{[^@]+}}@__captured_stmt702// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR4:[0-9]+]] {703// CHECK1-NEXT:  entry:704// CHECK1-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 8705// CHECK1-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 8706// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8707// CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4708// CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64709// CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]]710// CHECK1-NEXT:    store float 1.000000e+00, ptr [[ARRAYIDX]], align 4711// CHECK1-NEXT:    ret void712//713//714// CHECK1-LABEL: define {{[^@]+}}@__captured_stmt.1715// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR4]] {716// CHECK1-NEXT:  entry:717// CHECK1-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 8718// CHECK1-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 8719// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8720// CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4721// CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64722// CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]]723// CHECK1-NEXT:    store float 1.000000e+00, ptr [[ARRAYIDX]], align 4724// CHECK1-NEXT:    ret void725//726//727// CHECK1-IRBUILDER-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_728// CHECK1-IRBUILDER-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] {729// CHECK1-IRBUILDER-NEXT:  entry:730// CHECK1-IRBUILDER-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8731// CHECK1-IRBUILDER-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8732// CHECK1-IRBUILDER-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8733// CHECK1-IRBUILDER-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8734// CHECK1-IRBUILDER-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4735// CHECK1-IRBUILDER-NEXT:    [[TMP:%.*]] = alloca i32, align 4736// CHECK1-IRBUILDER-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4737// CHECK1-IRBUILDER-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4738// CHECK1-IRBUILDER-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4739// CHECK1-IRBUILDER-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4740// CHECK1-IRBUILDER-NEXT:    [[I:%.*]] = alloca i32, align 4741// CHECK1-IRBUILDER-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8742// CHECK1-IRBUILDER-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8743// CHECK1-IRBUILDER-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8744// CHECK1-IRBUILDER-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8745// CHECK1-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4746// CHECK1-IRBUILDER-NEXT:    store i32 4571423, ptr [[DOTOMP_UB]], align 4747// CHECK1-IRBUILDER-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4748// CHECK1-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4749// CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]])750// CHECK1-IRBUILDER-NEXT:    call void @__kmpc_dispatch_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 66, i32 0, i32 4571423, i32 1, i32 1)751// CHECK1-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]752// CHECK1-IRBUILDER:       omp.dispatch.cond:753// CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3]])754// CHECK1-IRBUILDER-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM1]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])755// CHECK1-IRBUILDER-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0756// CHECK1-IRBUILDER-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]757// CHECK1-IRBUILDER:       omp.dispatch.body:758// CHECK1-IRBUILDER-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4759// CHECK1-IRBUILDER-NEXT:    store i32 [[TMP1]], ptr [[DOTOMP_IV]], align 4760// CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]761// CHECK1-IRBUILDER:       omp.inner.for.cond:762// CHECK1-IRBUILDER-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4763// CHECK1-IRBUILDER-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4764// CHECK1-IRBUILDER-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]765// CHECK1-IRBUILDER-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]766// CHECK1-IRBUILDER:       omp.inner.for.body:767// CHECK1-IRBUILDER-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4768// CHECK1-IRBUILDER-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7769// CHECK1-IRBUILDER-NEXT:    [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]770// CHECK1-IRBUILDER-NEXT:    store i32 [[SUB]], ptr [[I]], align 4771// CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])772// CHECK1-IRBUILDER-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM2]])773// CHECK1-IRBUILDER-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[B_ADDR]], align 8774// CHECK1-IRBUILDER-NEXT:    [[TMP6:%.*]] = load i32, ptr [[I]], align 4775// CHECK1-IRBUILDER-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64776// CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP5]], i64 [[IDXPROM]]777// CHECK1-IRBUILDER-NEXT:    [[TMP7:%.*]] = load float, ptr [[ARRAYIDX]], align 4778// CHECK1-IRBUILDER-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[C_ADDR]], align 8779// CHECK1-IRBUILDER-NEXT:    [[TMP9:%.*]] = load i32, ptr [[I]], align 4780// CHECK1-IRBUILDER-NEXT:    [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64781// CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP8]], i64 [[IDXPROM3]]782// CHECK1-IRBUILDER-NEXT:    [[TMP10:%.*]] = load float, ptr [[ARRAYIDX4]], align 4783// CHECK1-IRBUILDER-NEXT:    [[MUL5:%.*]] = fmul float [[TMP7]], [[TMP10]]784// CHECK1-IRBUILDER-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[D_ADDR]], align 8785// CHECK1-IRBUILDER-NEXT:    [[TMP12:%.*]] = load i32, ptr [[I]], align 4786// CHECK1-IRBUILDER-NEXT:    [[IDXPROM6:%.*]] = sext i32 [[TMP12]] to i64787// CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP11]], i64 [[IDXPROM6]]788// CHECK1-IRBUILDER-NEXT:    [[TMP13:%.*]] = load float, ptr [[ARRAYIDX7]], align 4789// CHECK1-IRBUILDER-NEXT:    [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP13]]790// CHECK1-IRBUILDER-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[A_ADDR]], align 8791// CHECK1-IRBUILDER-NEXT:    [[TMP15:%.*]] = load i32, ptr [[I]], align 4792// CHECK1-IRBUILDER-NEXT:    [[IDXPROM9:%.*]] = sext i32 [[TMP15]] to i64793// CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 [[IDXPROM9]]794// CHECK1-IRBUILDER-NEXT:    store float [[MUL8]], ptr [[ARRAYIDX10]], align 4795// CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]]796// CHECK1-IRBUILDER:       omp.inner.for.body.ordered.after:797// CHECK1-IRBUILDER-NEXT:    br label [[OMP_REGION_FINALIZE:%.*]]798// CHECK1-IRBUILDER:       omp_region.finalize:799// CHECK1-IRBUILDER-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM2]])800// CHECK1-IRBUILDER-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]801// CHECK1-IRBUILDER:       omp.body.continue:802// CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]803// CHECK1-IRBUILDER:       omp.inner.for.inc:804// CHECK1-IRBUILDER-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4805// CHECK1-IRBUILDER-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP16]], 1806// CHECK1-IRBUILDER-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4807// CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM11:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3]])808// CHECK1-IRBUILDER-NEXT:    call void @__kmpc_dispatch_fini_4(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM11]])809// CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND]]810// CHECK1-IRBUILDER:       omp.inner.for.end:811// CHECK1-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]812// CHECK1-IRBUILDER:       omp.dispatch.inc:813// CHECK1-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND]]814// CHECK1-IRBUILDER:       omp.dispatch.end:815// CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM12:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3]])816// CHECK1-IRBUILDER-NEXT:    call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM12]])817// CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM13:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])818// CHECK1-IRBUILDER-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB4:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM13]])819// CHECK1-IRBUILDER-NEXT:    ret void820//821//822// CHECK1-IRBUILDER-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_823// CHECK1-IRBUILDER-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {824// CHECK1-IRBUILDER-NEXT:  entry:825// CHECK1-IRBUILDER-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8826// CHECK1-IRBUILDER-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8827// CHECK1-IRBUILDER-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8828// CHECK1-IRBUILDER-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8829// CHECK1-IRBUILDER-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8830// CHECK1-IRBUILDER-NEXT:    [[TMP:%.*]] = alloca i64, align 8831// CHECK1-IRBUILDER-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8832// CHECK1-IRBUILDER-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8833// CHECK1-IRBUILDER-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8834// CHECK1-IRBUILDER-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4835// CHECK1-IRBUILDER-NEXT:    [[I:%.*]] = alloca i64, align 8836// CHECK1-IRBUILDER-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8837// CHECK1-IRBUILDER-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8838// CHECK1-IRBUILDER-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8839// CHECK1-IRBUILDER-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8840// CHECK1-IRBUILDER-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8841// CHECK1-IRBUILDER-NEXT:    store i64 16908287, ptr [[DOTOMP_UB]], align 8842// CHECK1-IRBUILDER-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8843// CHECK1-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4844// CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB6:[0-9]+]])845// CHECK1-IRBUILDER-NEXT:    call void @__kmpc_dispatch_init_8u(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 1073741891, i64 0, i64 16908287, i64 1, i64 1)846// CHECK1-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]847// CHECK1-IRBUILDER:       omp.dispatch.cond:848// CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB6]])849// CHECK1-IRBUILDER-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_dispatch_next_8u(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM1]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])850// CHECK1-IRBUILDER-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0851// CHECK1-IRBUILDER-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]852// CHECK1-IRBUILDER:       omp.dispatch.body:853// CHECK1-IRBUILDER-NEXT:    [[TMP1:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8854// CHECK1-IRBUILDER-NEXT:    store i64 [[TMP1]], ptr [[DOTOMP_IV]], align 8855// CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]856// CHECK1-IRBUILDER:       omp.inner.for.cond:857// CHECK1-IRBUILDER-NEXT:    [[TMP2:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8858// CHECK1-IRBUILDER-NEXT:    [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8859// CHECK1-IRBUILDER-NEXT:    [[ADD:%.*]] = add i64 [[TMP3]], 1860// CHECK1-IRBUILDER-NEXT:    [[CMP:%.*]] = icmp ult i64 [[TMP2]], [[ADD]]861// CHECK1-IRBUILDER-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]862// CHECK1-IRBUILDER:       omp.inner.for.body:863// CHECK1-IRBUILDER-NEXT:    [[TMP4:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8864// CHECK1-IRBUILDER-NEXT:    [[MUL:%.*]] = mul i64 [[TMP4]], 127865// CHECK1-IRBUILDER-NEXT:    [[ADD2:%.*]] = add i64 131071, [[MUL]]866// CHECK1-IRBUILDER-NEXT:    store i64 [[ADD2]], ptr [[I]], align 8867// CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])868// CHECK1-IRBUILDER-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM3]])869// CHECK1-IRBUILDER-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[B_ADDR]], align 8870// CHECK1-IRBUILDER-NEXT:    [[TMP6:%.*]] = load i64, ptr [[I]], align 8871// CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP5]], i64 [[TMP6]]872// CHECK1-IRBUILDER-NEXT:    [[TMP7:%.*]] = load float, ptr [[ARRAYIDX]], align 4873// CHECK1-IRBUILDER-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[C_ADDR]], align 8874// CHECK1-IRBUILDER-NEXT:    [[TMP9:%.*]] = load i64, ptr [[I]], align 8875// CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw float, ptr [[TMP8]], i64 [[TMP9]]876// CHECK1-IRBUILDER-NEXT:    [[TMP10:%.*]] = load float, ptr [[ARRAYIDX4]], align 4877// CHECK1-IRBUILDER-NEXT:    [[MUL5:%.*]] = fmul float [[TMP7]], [[TMP10]]878// CHECK1-IRBUILDER-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[D_ADDR]], align 8879// CHECK1-IRBUILDER-NEXT:    [[TMP12:%.*]] = load i64, ptr [[I]], align 8880// CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds nuw float, ptr [[TMP11]], i64 [[TMP12]]881// CHECK1-IRBUILDER-NEXT:    [[TMP13:%.*]] = load float, ptr [[ARRAYIDX6]], align 4882// CHECK1-IRBUILDER-NEXT:    [[MUL7:%.*]] = fmul float [[MUL5]], [[TMP13]]883// CHECK1-IRBUILDER-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[A_ADDR]], align 8884// CHECK1-IRBUILDER-NEXT:    [[TMP15:%.*]] = load i64, ptr [[I]], align 8885// CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds nuw float, ptr [[TMP14]], i64 [[TMP15]]886// CHECK1-IRBUILDER-NEXT:    store float [[MUL7]], ptr [[ARRAYIDX8]], align 4887// CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]]888// CHECK1-IRBUILDER:       omp.inner.for.body.ordered.after:889// CHECK1-IRBUILDER-NEXT:    br label [[OMP_REGION_FINALIZE:%.*]]890// CHECK1-IRBUILDER:       omp_region.finalize:891// CHECK1-IRBUILDER-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM3]])892// CHECK1-IRBUILDER-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]893// CHECK1-IRBUILDER:       omp.body.continue:894// CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]895// CHECK1-IRBUILDER:       omp.inner.for.inc:896// CHECK1-IRBUILDER-NEXT:    [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8897// CHECK1-IRBUILDER-NEXT:    [[ADD9:%.*]] = add i64 [[TMP16]], 1898// CHECK1-IRBUILDER-NEXT:    store i64 [[ADD9]], ptr [[DOTOMP_IV]], align 8899// CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM10:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB6]])900// CHECK1-IRBUILDER-NEXT:    call void @__kmpc_dispatch_fini_8u(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM10]])901// CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND]]902// CHECK1-IRBUILDER:       omp.inner.for.end:903// CHECK1-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]904// CHECK1-IRBUILDER:       omp.dispatch.inc:905// CHECK1-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND]]906// CHECK1-IRBUILDER:       omp.dispatch.end:907// CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM11:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB6]])908// CHECK1-IRBUILDER-NEXT:    call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM11]])909// CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM12:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])910// CHECK1-IRBUILDER-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM12]])911// CHECK1-IRBUILDER-NEXT:    ret void912//913//914// CHECK1-IRBUILDER-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_915// CHECK1-IRBUILDER-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {916// CHECK1-IRBUILDER-NEXT:  entry:917// CHECK1-IRBUILDER-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8918// CHECK1-IRBUILDER-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8919// CHECK1-IRBUILDER-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8920// CHECK1-IRBUILDER-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8921// CHECK1-IRBUILDER-NEXT:    [[X:%.*]] = alloca i32, align 4922// CHECK1-IRBUILDER-NEXT:    [[Y:%.*]] = alloca i32, align 4923// CHECK1-IRBUILDER-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8924// CHECK1-IRBUILDER-NEXT:    [[TMP:%.*]] = alloca i8, align 1925// CHECK1-IRBUILDER-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4926// CHECK1-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1927// CHECK1-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8928// CHECK1-IRBUILDER-NEXT:    [[I:%.*]] = alloca i8, align 1929// CHECK1-IRBUILDER-NEXT:    [[X6:%.*]] = alloca i32, align 4930// CHECK1-IRBUILDER-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8931// CHECK1-IRBUILDER-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8932// CHECK1-IRBUILDER-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8933// CHECK1-IRBUILDER-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4934// CHECK1-IRBUILDER-NEXT:    [[I8:%.*]] = alloca i8, align 1935// CHECK1-IRBUILDER-NEXT:    [[X9:%.*]] = alloca i32, align 4936// CHECK1-IRBUILDER-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8937// CHECK1-IRBUILDER-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8938// CHECK1-IRBUILDER-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8939// CHECK1-IRBUILDER-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8940// CHECK1-IRBUILDER-NEXT:    store i32 0, ptr [[X]], align 4941// CHECK1-IRBUILDER-NEXT:    store i32 0, ptr [[Y]], align 4942// CHECK1-IRBUILDER-NEXT:    [[TMP0:%.*]] = load i32, ptr [[Y]], align 4943// CHECK1-IRBUILDER-NEXT:    [[CONV:%.*]] = trunc i32 [[TMP0]] to i8944// CHECK1-IRBUILDER-NEXT:    store i8 [[CONV]], ptr [[DOTCAPTURE_EXPR_]], align 1945// CHECK1-IRBUILDER-NEXT:    [[TMP1:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1946// CHECK1-IRBUILDER-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP1]] to i32947// CHECK1-IRBUILDER-NEXT:    [[SUB:%.*]] = sub i32 57, [[CONV3]]948// CHECK1-IRBUILDER-NEXT:    [[ADD:%.*]] = add i32 [[SUB]], 1949// CHECK1-IRBUILDER-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1950// CHECK1-IRBUILDER-NEXT:    [[CONV4:%.*]] = zext i32 [[DIV]] to i64951// CHECK1-IRBUILDER-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11952// CHECK1-IRBUILDER-NEXT:    [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1953// CHECK1-IRBUILDER-NEXT:    store i64 [[SUB5]], ptr [[DOTCAPTURE_EXPR_2]], align 8954// CHECK1-IRBUILDER-NEXT:    [[TMP2:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1955// CHECK1-IRBUILDER-NEXT:    store i8 [[TMP2]], ptr [[I]], align 1956// CHECK1-IRBUILDER-NEXT:    store i32 11, ptr [[X6]], align 4957// CHECK1-IRBUILDER-NEXT:    [[TMP3:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1958// CHECK1-IRBUILDER-NEXT:    [[CONV7:%.*]] = sext i8 [[TMP3]] to i32959// CHECK1-IRBUILDER-NEXT:    [[CMP:%.*]] = icmp sle i32 [[CONV7]], 57960// CHECK1-IRBUILDER-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]961// CHECK1-IRBUILDER:       omp.precond.then:962// CHECK1-IRBUILDER-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8963// CHECK1-IRBUILDER-NEXT:    [[TMP4:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8964// CHECK1-IRBUILDER-NEXT:    store i64 [[TMP4]], ptr [[DOTOMP_UB]], align 8965// CHECK1-IRBUILDER-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8966// CHECK1-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4967// CHECK1-IRBUILDER-NEXT:    [[TMP5:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8968// CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB8:[0-9]+]])969// CHECK1-IRBUILDER-NEXT:    call void @__kmpc_dispatch_init_8(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 1073741894, i64 0, i64 [[TMP5]], i64 1, i64 1)970// CHECK1-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]971// CHECK1-IRBUILDER:       omp.dispatch.cond:972// CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM10:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB8]])973// CHECK1-IRBUILDER-NEXT:    [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM10]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])974// CHECK1-IRBUILDER-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0975// CHECK1-IRBUILDER-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]976// CHECK1-IRBUILDER:       omp.dispatch.body:977// CHECK1-IRBUILDER-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8978// CHECK1-IRBUILDER-NEXT:    store i64 [[TMP7]], ptr [[DOTOMP_IV]], align 8979// CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]980// CHECK1-IRBUILDER:       omp.inner.for.cond:981// CHECK1-IRBUILDER-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8982// CHECK1-IRBUILDER-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8983// CHECK1-IRBUILDER-NEXT:    [[CMP11:%.*]] = icmp sle i64 [[TMP8]], [[TMP9]]984// CHECK1-IRBUILDER-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]985// CHECK1-IRBUILDER:       omp.inner.for.body:986// CHECK1-IRBUILDER-NEXT:    [[TMP10:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1987// CHECK1-IRBUILDER-NEXT:    [[CONV12:%.*]] = sext i8 [[TMP10]] to i64988// CHECK1-IRBUILDER-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8989// CHECK1-IRBUILDER-NEXT:    [[DIV13:%.*]] = sdiv i64 [[TMP11]], 11990// CHECK1-IRBUILDER-NEXT:    [[MUL14:%.*]] = mul nsw i64 [[DIV13]], 1991// CHECK1-IRBUILDER-NEXT:    [[ADD15:%.*]] = add nsw i64 [[CONV12]], [[MUL14]]992// CHECK1-IRBUILDER-NEXT:    [[CONV16:%.*]] = trunc i64 [[ADD15]] to i8993// CHECK1-IRBUILDER-NEXT:    store i8 [[CONV16]], ptr [[I8]], align 1994// CHECK1-IRBUILDER-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8995// CHECK1-IRBUILDER-NEXT:    [[TMP13:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8996// CHECK1-IRBUILDER-NEXT:    [[DIV17:%.*]] = sdiv i64 [[TMP13]], 11997// CHECK1-IRBUILDER-NEXT:    [[MUL18:%.*]] = mul nsw i64 [[DIV17]], 11998// CHECK1-IRBUILDER-NEXT:    [[SUB19:%.*]] = sub nsw i64 [[TMP12]], [[MUL18]]999// CHECK1-IRBUILDER-NEXT:    [[MUL20:%.*]] = mul nsw i64 [[SUB19]], 11000// CHECK1-IRBUILDER-NEXT:    [[SUB21:%.*]] = sub nsw i64 11, [[MUL20]]1001// CHECK1-IRBUILDER-NEXT:    [[CONV22:%.*]] = trunc i64 [[SUB21]] to i321002// CHECK1-IRBUILDER-NEXT:    store i32 [[CONV22]], ptr [[X9]], align 41003// CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM23:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])1004// CHECK1-IRBUILDER-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM23]])1005// CHECK1-IRBUILDER-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[B_ADDR]], align 81006// CHECK1-IRBUILDER-NEXT:    [[TMP15:%.*]] = load i8, ptr [[I8]], align 11007// CHECK1-IRBUILDER-NEXT:    [[IDXPROM:%.*]] = sext i8 [[TMP15]] to i641008// CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 [[IDXPROM]]1009// CHECK1-IRBUILDER-NEXT:    [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 41010// CHECK1-IRBUILDER-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[C_ADDR]], align 81011// CHECK1-IRBUILDER-NEXT:    [[TMP18:%.*]] = load i8, ptr [[I8]], align 11012// CHECK1-IRBUILDER-NEXT:    [[IDXPROM24:%.*]] = sext i8 [[TMP18]] to i641013// CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX25:%.*]] = getelementptr inbounds float, ptr [[TMP17]], i64 [[IDXPROM24]]1014// CHECK1-IRBUILDER-NEXT:    [[TMP19:%.*]] = load float, ptr [[ARRAYIDX25]], align 41015// CHECK1-IRBUILDER-NEXT:    [[MUL26:%.*]] = fmul float [[TMP16]], [[TMP19]]1016// CHECK1-IRBUILDER-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[D_ADDR]], align 81017// CHECK1-IRBUILDER-NEXT:    [[TMP21:%.*]] = load i8, ptr [[I8]], align 11018// CHECK1-IRBUILDER-NEXT:    [[IDXPROM27:%.*]] = sext i8 [[TMP21]] to i641019// CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX28:%.*]] = getelementptr inbounds float, ptr [[TMP20]], i64 [[IDXPROM27]]1020// CHECK1-IRBUILDER-NEXT:    [[TMP22:%.*]] = load float, ptr [[ARRAYIDX28]], align 41021// CHECK1-IRBUILDER-NEXT:    [[MUL29:%.*]] = fmul float [[MUL26]], [[TMP22]]1022// CHECK1-IRBUILDER-NEXT:    [[TMP23:%.*]] = load ptr, ptr [[A_ADDR]], align 81023// CHECK1-IRBUILDER-NEXT:    [[TMP24:%.*]] = load i8, ptr [[I8]], align 11024// CHECK1-IRBUILDER-NEXT:    [[IDXPROM30:%.*]] = sext i8 [[TMP24]] to i641025// CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX31:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i64 [[IDXPROM30]]1026// CHECK1-IRBUILDER-NEXT:    store float [[MUL29]], ptr [[ARRAYIDX31]], align 41027// CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]]1028// CHECK1-IRBUILDER:       omp.inner.for.body.ordered.after:1029// CHECK1-IRBUILDER-NEXT:    br label [[OMP_REGION_FINALIZE:%.*]]1030// CHECK1-IRBUILDER:       omp_region.finalize:1031// CHECK1-IRBUILDER-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM23]])1032// CHECK1-IRBUILDER-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]1033// CHECK1-IRBUILDER:       omp.body.continue:1034// CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]1035// CHECK1-IRBUILDER:       omp.inner.for.inc:1036// CHECK1-IRBUILDER-NEXT:    [[TMP25:%.*]] = load i64, ptr [[DOTOMP_IV]], align 81037// CHECK1-IRBUILDER-NEXT:    [[ADD32:%.*]] = add nsw i64 [[TMP25]], 11038// CHECK1-IRBUILDER-NEXT:    store i64 [[ADD32]], ptr [[DOTOMP_IV]], align 81039// CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM33:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB8]])1040// CHECK1-IRBUILDER-NEXT:    call void @__kmpc_dispatch_fini_8(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM33]])1041// CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND]]1042// CHECK1-IRBUILDER:       omp.inner.for.end:1043// CHECK1-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]1044// CHECK1-IRBUILDER:       omp.dispatch.inc:1045// CHECK1-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND]]1046// CHECK1-IRBUILDER:       omp.dispatch.end:1047// CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM34:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB8]])1048// CHECK1-IRBUILDER-NEXT:    call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM34]])1049// CHECK1-IRBUILDER-NEXT:    br label [[OMP_PRECOND_END]]1050// CHECK1-IRBUILDER:       omp.precond.end:1051// CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM35:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])1052// CHECK1-IRBUILDER-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM35]])1053// CHECK1-IRBUILDER-NEXT:    ret void1054//1055//1056// CHECK1-IRBUILDER-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_1057// CHECK1-IRBUILDER-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {1058// CHECK1-IRBUILDER-NEXT:  entry:1059// CHECK1-IRBUILDER-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 81060// CHECK1-IRBUILDER-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 81061// CHECK1-IRBUILDER-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 81062// CHECK1-IRBUILDER-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 81063// CHECK1-IRBUILDER-NEXT:    [[X:%.*]] = alloca i32, align 41064// CHECK1-IRBUILDER-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 41065// CHECK1-IRBUILDER-NEXT:    [[TMP:%.*]] = alloca i8, align 11066// CHECK1-IRBUILDER-NEXT:    [[_TMP1:%.*]] = alloca i32, align 41067// CHECK1-IRBUILDER-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 41068// CHECK1-IRBUILDER-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 41069// CHECK1-IRBUILDER-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41070// CHECK1-IRBUILDER-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41071// CHECK1-IRBUILDER-NEXT:    [[I:%.*]] = alloca i8, align 11072// CHECK1-IRBUILDER-NEXT:    [[X2:%.*]] = alloca i32, align 41073// CHECK1-IRBUILDER-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 81074// CHECK1-IRBUILDER-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 81075// CHECK1-IRBUILDER-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 81076// CHECK1-IRBUILDER-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 81077// CHECK1-IRBUILDER-NEXT:    store i32 0, ptr [[X]], align 41078// CHECK1-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 41079// CHECK1-IRBUILDER-NEXT:    store i32 199, ptr [[DOTOMP_UB]], align 41080// CHECK1-IRBUILDER-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 41081// CHECK1-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 41082// CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB10:[0-9]+]])1083// CHECK1-IRBUILDER-NEXT:    call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 1073741893, i32 0, i32 199, i32 1, i32 1)1084// CHECK1-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]1085// CHECK1-IRBUILDER:       omp.dispatch.cond:1086// CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB10]])1087// CHECK1-IRBUILDER-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM3]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])1088// CHECK1-IRBUILDER-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 01089// CHECK1-IRBUILDER-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]1090// CHECK1-IRBUILDER:       omp.dispatch.body:1091// CHECK1-IRBUILDER-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41092// CHECK1-IRBUILDER-NEXT:    store i32 [[TMP1]], ptr [[DOTOMP_IV]], align 41093// CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]1094// CHECK1-IRBUILDER:       omp.inner.for.cond:1095// CHECK1-IRBUILDER-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41096// CHECK1-IRBUILDER-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41097// CHECK1-IRBUILDER-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]1098// CHECK1-IRBUILDER-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1099// CHECK1-IRBUILDER:       omp.inner.for.body:1100// CHECK1-IRBUILDER-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41101// CHECK1-IRBUILDER-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP4]], 201102// CHECK1-IRBUILDER-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 11103// CHECK1-IRBUILDER-NEXT:    [[ADD:%.*]] = add nsw i32 48, [[MUL]]1104// CHECK1-IRBUILDER-NEXT:    [[CONV:%.*]] = trunc i32 [[ADD]] to i81105// CHECK1-IRBUILDER-NEXT:    store i8 [[CONV]], ptr [[I]], align 11106// CHECK1-IRBUILDER-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41107// CHECK1-IRBUILDER-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41108// CHECK1-IRBUILDER-NEXT:    [[DIV4:%.*]] = sdiv i32 [[TMP6]], 201109// CHECK1-IRBUILDER-NEXT:    [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 201110// CHECK1-IRBUILDER-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP5]], [[MUL5]]1111// CHECK1-IRBUILDER-NEXT:    [[MUL6:%.*]] = mul nsw i32 [[SUB]], 11112// CHECK1-IRBUILDER-NEXT:    [[ADD7:%.*]] = add nsw i32 -10, [[MUL6]]1113// CHECK1-IRBUILDER-NEXT:    store i32 [[ADD7]], ptr [[X2]], align 41114// CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM8:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])1115// CHECK1-IRBUILDER-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM8]])1116// CHECK1-IRBUILDER-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[B_ADDR]], align 81117// CHECK1-IRBUILDER-NEXT:    [[TMP8:%.*]] = load i8, ptr [[I]], align 11118// CHECK1-IRBUILDER-NEXT:    [[IDXPROM:%.*]] = zext i8 [[TMP8]] to i641119// CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP7]], i64 [[IDXPROM]]1120// CHECK1-IRBUILDER-NEXT:    [[TMP9:%.*]] = load float, ptr [[ARRAYIDX]], align 41121// CHECK1-IRBUILDER-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[C_ADDR]], align 81122// CHECK1-IRBUILDER-NEXT:    [[TMP11:%.*]] = load i8, ptr [[I]], align 11123// CHECK1-IRBUILDER-NEXT:    [[IDXPROM9:%.*]] = zext i8 [[TMP11]] to i641124// CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds nuw float, ptr [[TMP10]], i64 [[IDXPROM9]]1125// CHECK1-IRBUILDER-NEXT:    [[TMP12:%.*]] = load float, ptr [[ARRAYIDX10]], align 41126// CHECK1-IRBUILDER-NEXT:    [[MUL11:%.*]] = fmul float [[TMP9]], [[TMP12]]1127// CHECK1-IRBUILDER-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[D_ADDR]], align 81128// CHECK1-IRBUILDER-NEXT:    [[TMP14:%.*]] = load i8, ptr [[I]], align 11129// CHECK1-IRBUILDER-NEXT:    [[IDXPROM12:%.*]] = zext i8 [[TMP14]] to i641130// CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX13:%.*]] = getelementptr inbounds nuw float, ptr [[TMP13]], i64 [[IDXPROM12]]1131// CHECK1-IRBUILDER-NEXT:    [[TMP15:%.*]] = load float, ptr [[ARRAYIDX13]], align 41132// CHECK1-IRBUILDER-NEXT:    [[MUL14:%.*]] = fmul float [[MUL11]], [[TMP15]]1133// CHECK1-IRBUILDER-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[A_ADDR]], align 81134// CHECK1-IRBUILDER-NEXT:    [[TMP17:%.*]] = load i8, ptr [[I]], align 11135// CHECK1-IRBUILDER-NEXT:    [[IDXPROM15:%.*]] = zext i8 [[TMP17]] to i641136// CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds nuw float, ptr [[TMP16]], i64 [[IDXPROM15]]1137// CHECK1-IRBUILDER-NEXT:    store float [[MUL14]], ptr [[ARRAYIDX16]], align 41138// CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]]1139// CHECK1-IRBUILDER:       omp.inner.for.body.ordered.after:1140// CHECK1-IRBUILDER-NEXT:    br label [[OMP_REGION_FINALIZE:%.*]]1141// CHECK1-IRBUILDER:       omp_region.finalize:1142// CHECK1-IRBUILDER-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM8]])1143// CHECK1-IRBUILDER-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]1144// CHECK1-IRBUILDER:       omp.body.continue:1145// CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]1146// CHECK1-IRBUILDER:       omp.inner.for.inc:1147// CHECK1-IRBUILDER-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41148// CHECK1-IRBUILDER-NEXT:    [[ADD17:%.*]] = add nsw i32 [[TMP18]], 11149// CHECK1-IRBUILDER-NEXT:    store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 41150// CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM18:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB10]])1151// CHECK1-IRBUILDER-NEXT:    call void @__kmpc_dispatch_fini_4(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM18]])1152// CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND]]1153// CHECK1-IRBUILDER:       omp.inner.for.end:1154// CHECK1-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]1155// CHECK1-IRBUILDER:       omp.dispatch.inc:1156// CHECK1-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND]]1157// CHECK1-IRBUILDER:       omp.dispatch.end:1158// CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM19:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB10]])1159// CHECK1-IRBUILDER-NEXT:    call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM19]])1160// CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM20:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])1161// CHECK1-IRBUILDER-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM20]])1162// CHECK1-IRBUILDER-NEXT:    ret void1163//1164//1165// CHECK1-IRBUILDER-LABEL: define {{[^@]+}}@_Z8foo_simdii1166// CHECK1-IRBUILDER-SAME: (i32 noundef [[LOW:%.*]], i32 noundef [[UP:%.*]]) #[[ATTR3:[0-9]+]] {1167// CHECK1-IRBUILDER-NEXT:  entry:1168// CHECK1-IRBUILDER-NEXT:    [[LOW_ADDR:%.*]] = alloca i32, align 41169// CHECK1-IRBUILDER-NEXT:    [[UP_ADDR:%.*]] = alloca i32, align 41170// CHECK1-IRBUILDER-NEXT:    [[TMP:%.*]] = alloca i32, align 41171// CHECK1-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 41172// CHECK1-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 41173// CHECK1-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 41174// CHECK1-IRBUILDER-NEXT:    [[I:%.*]] = alloca i32, align 41175// CHECK1-IRBUILDER-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 41176// CHECK1-IRBUILDER-NEXT:    [[I5:%.*]] = alloca i32, align 41177// CHECK1-IRBUILDER-NEXT:    [[DOTOMP_IV16:%.*]] = alloca i32, align 41178// CHECK1-IRBUILDER-NEXT:    [[_TMP17:%.*]] = alloca i32, align 41179// CHECK1-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 41180// CHECK1-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_19:%.*]] = alloca i32, align 41181// CHECK1-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_20:%.*]] = alloca i32, align 41182// CHECK1-IRBUILDER-NEXT:    [[I26:%.*]] = alloca i32, align 41183// CHECK1-IRBUILDER-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 41184// CHECK1-IRBUILDER-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 41185// CHECK1-IRBUILDER-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41186// CHECK1-IRBUILDER-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41187// CHECK1-IRBUILDER-NEXT:    [[I28:%.*]] = alloca i32, align 41188// CHECK1-IRBUILDER-NEXT:    store i32 [[LOW]], ptr [[LOW_ADDR]], align 41189// CHECK1-IRBUILDER-NEXT:    store i32 [[UP]], ptr [[UP_ADDR]], align 41190// CHECK1-IRBUILDER-NEXT:    [[TMP0:%.*]] = load i32, ptr [[LOW_ADDR]], align 41191// CHECK1-IRBUILDER-NEXT:    store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 41192// CHECK1-IRBUILDER-NEXT:    [[TMP1:%.*]] = load i32, ptr [[UP_ADDR]], align 41193// CHECK1-IRBUILDER-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_1]], align 41194// CHECK1-IRBUILDER-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 41195// CHECK1-IRBUILDER-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41196// CHECK1-IRBUILDER-NEXT:    [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]]1197// CHECK1-IRBUILDER-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 11198// CHECK1-IRBUILDER-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 11199// CHECK1-IRBUILDER-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 11200// CHECK1-IRBUILDER-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 11201// CHECK1-IRBUILDER-NEXT:    store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 41202// CHECK1-IRBUILDER-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41203// CHECK1-IRBUILDER-NEXT:    store i32 [[TMP4]], ptr [[I]], align 41204// CHECK1-IRBUILDER-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41205// CHECK1-IRBUILDER-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 41206// CHECK1-IRBUILDER-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP5]], [[TMP6]]1207// CHECK1-IRBUILDER-NEXT:    br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]1208// CHECK1-IRBUILDER:       simd.if.then:1209// CHECK1-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_IV]], align 41210// CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]1211// CHECK1-IRBUILDER:       omp.inner.for.cond:1212// CHECK1-IRBUILDER-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41213// CHECK1-IRBUILDER-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 41214// CHECK1-IRBUILDER-NEXT:    [[ADD6:%.*]] = add i32 [[TMP8]], 11215// CHECK1-IRBUILDER-NEXT:    [[CMP7:%.*]] = icmp ult i32 [[TMP7]], [[ADD6]]1216// CHECK1-IRBUILDER-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1217// CHECK1-IRBUILDER:       omp.inner.for.body:1218// CHECK1-IRBUILDER-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41219// CHECK1-IRBUILDER-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41220// CHECK1-IRBUILDER-NEXT:    [[MUL:%.*]] = mul i32 [[TMP10]], 11221// CHECK1-IRBUILDER-NEXT:    [[ADD8:%.*]] = add i32 [[TMP9]], [[MUL]]1222// CHECK1-IRBUILDER-NEXT:    store i32 [[ADD8]], ptr [[I5]], align 41223// CHECK1-IRBUILDER-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I5]], align 41224// CHECK1-IRBUILDER-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i641225// CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]]1226// CHECK1-IRBUILDER-NEXT:    store float 0.000000e+00, ptr [[ARRAYIDX]], align 41227// CHECK1-IRBUILDER-NEXT:    call void @__captured_stmt(ptr [[I5]])1228// CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]]1229// CHECK1-IRBUILDER:       omp.inner.for.body.ordered.after:1230// CHECK1-IRBUILDER-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]1231// CHECK1-IRBUILDER:       omp.body.continue:1232// CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]1233// CHECK1-IRBUILDER:       omp.inner.for.inc:1234// CHECK1-IRBUILDER-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41235// CHECK1-IRBUILDER-NEXT:    [[ADD9:%.*]] = add i32 [[TMP12]], 11236// CHECK1-IRBUILDER-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 41237// CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]1238// CHECK1-IRBUILDER:       omp.inner.for.end:1239// CHECK1-IRBUILDER-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41240// CHECK1-IRBUILDER-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 41241// CHECK1-IRBUILDER-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41242// CHECK1-IRBUILDER-NEXT:    [[SUB10:%.*]] = sub i32 [[TMP14]], [[TMP15]]1243// CHECK1-IRBUILDER-NEXT:    [[SUB11:%.*]] = sub i32 [[SUB10]], 11244// CHECK1-IRBUILDER-NEXT:    [[ADD12:%.*]] = add i32 [[SUB11]], 11245// CHECK1-IRBUILDER-NEXT:    [[DIV13:%.*]] = udiv i32 [[ADD12]], 11246// CHECK1-IRBUILDER-NEXT:    [[MUL14:%.*]] = mul i32 [[DIV13]], 11247// CHECK1-IRBUILDER-NEXT:    [[ADD15:%.*]] = add i32 [[TMP13]], [[MUL14]]1248// CHECK1-IRBUILDER-NEXT:    store i32 [[ADD15]], ptr [[I5]], align 41249// CHECK1-IRBUILDER-NEXT:    br label [[SIMD_IF_END]]1250// CHECK1-IRBUILDER:       simd.if.end:1251// CHECK1-IRBUILDER-NEXT:    [[TMP16:%.*]] = load i32, ptr [[LOW_ADDR]], align 41252// CHECK1-IRBUILDER-NEXT:    store i32 [[TMP16]], ptr [[DOTCAPTURE_EXPR_18]], align 41253// CHECK1-IRBUILDER-NEXT:    [[TMP17:%.*]] = load i32, ptr [[UP_ADDR]], align 41254// CHECK1-IRBUILDER-NEXT:    store i32 [[TMP17]], ptr [[DOTCAPTURE_EXPR_19]], align 41255// CHECK1-IRBUILDER-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 41256// CHECK1-IRBUILDER-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 41257// CHECK1-IRBUILDER-NEXT:    [[SUB21:%.*]] = sub i32 [[TMP18]], [[TMP19]]1258// CHECK1-IRBUILDER-NEXT:    [[SUB22:%.*]] = sub i32 [[SUB21]], 11259// CHECK1-IRBUILDER-NEXT:    [[ADD23:%.*]] = add i32 [[SUB22]], 11260// CHECK1-IRBUILDER-NEXT:    [[DIV24:%.*]] = udiv i32 [[ADD23]], 11261// CHECK1-IRBUILDER-NEXT:    [[SUB25:%.*]] = sub i32 [[DIV24]], 11262// CHECK1-IRBUILDER-NEXT:    store i32 [[SUB25]], ptr [[DOTCAPTURE_EXPR_20]], align 41263// CHECK1-IRBUILDER-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 41264// CHECK1-IRBUILDER-NEXT:    store i32 [[TMP20]], ptr [[I26]], align 41265// CHECK1-IRBUILDER-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 41266// CHECK1-IRBUILDER-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 41267// CHECK1-IRBUILDER-NEXT:    [[CMP27:%.*]] = icmp slt i32 [[TMP21]], [[TMP22]]1268// CHECK1-IRBUILDER-NEXT:    br i1 [[CMP27]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]1269// CHECK1-IRBUILDER:       omp.precond.then:1270// CHECK1-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 41271// CHECK1-IRBUILDER-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_20]], align 41272// CHECK1-IRBUILDER-NEXT:    store i32 [[TMP23]], ptr [[DOTOMP_UB]], align 41273// CHECK1-IRBUILDER-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 41274// CHECK1-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 41275// CHECK1-IRBUILDER-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_20]], align 41276// CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB12:[0-9]+]])1277// CHECK1-IRBUILDER-NEXT:    call void @__kmpc_dispatch_init_4u(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 66, i32 0, i32 [[TMP24]], i32 1, i32 1)1278// CHECK1-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]1279// CHECK1-IRBUILDER:       omp.dispatch.cond:1280// CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM29:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB12]])1281// CHECK1-IRBUILDER-NEXT:    [[TMP25:%.*]] = call i32 @__kmpc_dispatch_next_4u(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM29]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])1282// CHECK1-IRBUILDER-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP25]], 01283// CHECK1-IRBUILDER-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]1284// CHECK1-IRBUILDER:       omp.dispatch.body:1285// CHECK1-IRBUILDER-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41286// CHECK1-IRBUILDER-NEXT:    store i32 [[TMP26]], ptr [[DOTOMP_IV16]], align 41287// CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND30:%.*]]1288// CHECK1-IRBUILDER:       omp.inner.for.cond30:1289// CHECK1-IRBUILDER-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV16]], align 41290// CHECK1-IRBUILDER-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41291// CHECK1-IRBUILDER-NEXT:    [[ADD31:%.*]] = add i32 [[TMP28]], 11292// CHECK1-IRBUILDER-NEXT:    [[CMP32:%.*]] = icmp ult i32 [[TMP27]], [[ADD31]]1293// CHECK1-IRBUILDER-NEXT:    br i1 [[CMP32]], label [[OMP_INNER_FOR_BODY33:%.*]], label [[OMP_INNER_FOR_END42:%.*]]1294// CHECK1-IRBUILDER:       omp.inner.for.body33:1295// CHECK1-IRBUILDER-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 41296// CHECK1-IRBUILDER-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IV16]], align 41297// CHECK1-IRBUILDER-NEXT:    [[MUL34:%.*]] = mul i32 [[TMP30]], 11298// CHECK1-IRBUILDER-NEXT:    [[ADD35:%.*]] = add i32 [[TMP29]], [[MUL34]]1299// CHECK1-IRBUILDER-NEXT:    store i32 [[ADD35]], ptr [[I28]], align 41300// CHECK1-IRBUILDER-NEXT:    [[TMP31:%.*]] = load i32, ptr [[I28]], align 41301// CHECK1-IRBUILDER-NEXT:    [[IDXPROM36:%.*]] = sext i32 [[TMP31]] to i641302// CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX37:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM36]]1303// CHECK1-IRBUILDER-NEXT:    store float 0.000000e+00, ptr [[ARRAYIDX37]], align 41304// CHECK1-IRBUILDER-NEXT:    call void @__captured_stmt.1(ptr [[I28]])1305// CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_BODY33_ORDERED_AFTER:%.*]]1306// CHECK1-IRBUILDER:       omp.inner.for.body33.ordered.after:1307// CHECK1-IRBUILDER-NEXT:    br label [[OMP_REGION_FINALIZE38:%.*]]1308// CHECK1-IRBUILDER:       omp_region.finalize38:1309// CHECK1-IRBUILDER-NEXT:    br label [[OMP_BODY_CONTINUE39:%.*]]1310// CHECK1-IRBUILDER:       omp.body.continue39:1311// CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_INC40:%.*]]1312// CHECK1-IRBUILDER:       omp.inner.for.inc40:1313// CHECK1-IRBUILDER-NEXT:    [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV16]], align 41314// CHECK1-IRBUILDER-NEXT:    [[ADD40:%.*]] = add i32 [[TMP32]], 11315// CHECK1-IRBUILDER-NEXT:    store i32 [[ADD40]], ptr [[DOTOMP_IV16]], align 41316// CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM41:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB12]])1317// CHECK1-IRBUILDER-NEXT:    call void @__kmpc_dispatch_fini_4u(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM41]])1318// CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND30]], !llvm.loop [[LOOP5:![0-9]+]]1319// CHECK1-IRBUILDER:       omp.inner.for.end43:1320// CHECK1-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]1321// CHECK1-IRBUILDER:       omp.dispatch.inc:1322// CHECK1-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND]]1323// CHECK1-IRBUILDER:       omp.dispatch.end:1324// CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM43:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB12]])1325// CHECK1-IRBUILDER-NEXT:    call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM43]])1326// CHECK1-IRBUILDER-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 41327// CHECK1-IRBUILDER-NEXT:    [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 01328// CHECK1-IRBUILDER-NEXT:    br i1 [[TMP34]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]1329// CHECK1-IRBUILDER:       .omp.final.then:1330// CHECK1-IRBUILDER-NEXT:    [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 41331// CHECK1-IRBUILDER-NEXT:    [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 41332// CHECK1-IRBUILDER-NEXT:    [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 41333// CHECK1-IRBUILDER-NEXT:    [[SUB44:%.*]] = sub i32 [[TMP36]], [[TMP37]]1334// CHECK1-IRBUILDER-NEXT:    [[SUB45:%.*]] = sub i32 [[SUB44]], 11335// CHECK1-IRBUILDER-NEXT:    [[ADD46:%.*]] = add i32 [[SUB45]], 11336// CHECK1-IRBUILDER-NEXT:    [[DIV47:%.*]] = udiv i32 [[ADD46]], 11337// CHECK1-IRBUILDER-NEXT:    [[MUL48:%.*]] = mul i32 [[DIV47]], 11338// CHECK1-IRBUILDER-NEXT:    [[ADD49:%.*]] = add i32 [[TMP35]], [[MUL48]]1339// CHECK1-IRBUILDER-NEXT:    store i32 [[ADD49]], ptr [[I28]], align 41340// CHECK1-IRBUILDER-NEXT:    br label [[DOTOMP_FINAL_DONE]]1341// CHECK1-IRBUILDER:       .omp.final.done:1342// CHECK1-IRBUILDER-NEXT:    br label [[OMP_PRECOND_END]]1343// CHECK1-IRBUILDER:       omp.precond.end:1344// CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM50:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])1345// CHECK1-IRBUILDER-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM50]])1346// CHECK1-IRBUILDER-NEXT:    ret void1347//1348//1349// CHECK1-IRBUILDER-LABEL: define {{[^@]+}}@__captured_stmt1350// CHECK1-IRBUILDER-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR4:[0-9]+]] {1351// CHECK1-IRBUILDER-NEXT:  entry:1352// CHECK1-IRBUILDER-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 81353// CHECK1-IRBUILDER-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 81354// CHECK1-IRBUILDER-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 81355// CHECK1-IRBUILDER-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 41356// CHECK1-IRBUILDER-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i641357// CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]]1358// CHECK1-IRBUILDER-NEXT:    store float 1.000000e+00, ptr [[ARRAYIDX]], align 41359// CHECK1-IRBUILDER-NEXT:    ret void1360//1361//1362// CHECK1-IRBUILDER-LABEL: define {{[^@]+}}@__captured_stmt.11363// CHECK1-IRBUILDER-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR4]] {1364// CHECK1-IRBUILDER-NEXT:  entry:1365// CHECK1-IRBUILDER-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 81366// CHECK1-IRBUILDER-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 81367// CHECK1-IRBUILDER-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 81368// CHECK1-IRBUILDER-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 41369// CHECK1-IRBUILDER-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i641370// CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]]1371// CHECK1-IRBUILDER-NEXT:    store float 1.000000e+00, ptr [[ARRAYIDX]], align 41372// CHECK1-IRBUILDER-NEXT:    ret void1373//1374//1375// CHECK3-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_1376// CHECK3-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] {1377// CHECK3-NEXT:  entry:1378// CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 81379// CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 81380// CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 81381// CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 81382// CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 41383// CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 41384// CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 41385// CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 41386// CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41387// CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41388// CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 41389// CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])1390// CHECK3-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 81391// CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 81392// CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 81393// CHECK3-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 81394// CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 41395// CHECK3-NEXT:    store i32 4571423, ptr [[DOTOMP_UB]], align 41396// CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 41397// CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 41398// CHECK3-NEXT:    call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP0]], i32 66, i32 0, i32 4571423, i32 1, i32 1)1399// CHECK3-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]1400// CHECK3:       omp.dispatch.cond:1401// CHECK3-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])1402// CHECK3-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 01403// CHECK3-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]1404// CHECK3:       omp.dispatch.body:1405// CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41406// CHECK3-NEXT:    store i32 [[TMP2]], ptr [[DOTOMP_IV]], align 41407// CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]1408// CHECK3:       omp.inner.for.cond:1409// CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41410// CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41411// CHECK3-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP3]], [[TMP4]]1412// CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1413// CHECK3:       omp.inner.for.body:1414// CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41415// CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP5]], 71416// CHECK3-NEXT:    [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]1417// CHECK3-NEXT:    store i32 [[SUB]], ptr [[I]], align 41418// CHECK3-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[TMP0]])1419// CHECK3-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[B_ADDR]], align 81420// CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[I]], align 41421// CHECK3-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i641422// CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP6]], i64 [[IDXPROM]]1423// CHECK3-NEXT:    [[TMP8:%.*]] = load float, ptr [[ARRAYIDX]], align 41424// CHECK3-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[C_ADDR]], align 81425// CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[I]], align 41426// CHECK3-NEXT:    [[IDXPROM1:%.*]] = sext i32 [[TMP10]] to i641427// CHECK3-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP9]], i64 [[IDXPROM1]]1428// CHECK3-NEXT:    [[TMP11:%.*]] = load float, ptr [[ARRAYIDX2]], align 41429// CHECK3-NEXT:    [[MUL3:%.*]] = fmul float [[TMP8]], [[TMP11]]1430// CHECK3-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[D_ADDR]], align 81431// CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 41432// CHECK3-NEXT:    [[IDXPROM4:%.*]] = sext i32 [[TMP13]] to i641433// CHECK3-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[IDXPROM4]]1434// CHECK3-NEXT:    [[TMP14:%.*]] = load float, ptr [[ARRAYIDX5]], align 41435// CHECK3-NEXT:    [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP14]]1436// CHECK3-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[A_ADDR]], align 81437// CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I]], align 41438// CHECK3-NEXT:    [[IDXPROM7:%.*]] = sext i32 [[TMP16]] to i641439// CHECK3-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[IDXPROM7]]1440// CHECK3-NEXT:    store float [[MUL6]], ptr [[ARRAYIDX8]], align 41441// CHECK3-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[TMP0]])1442// CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]1443// CHECK3:       omp.body.continue:1444// CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]1445// CHECK3:       omp.inner.for.inc:1446// CHECK3-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41447// CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP17]], 11448// CHECK3-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 41449// CHECK3-NEXT:    call void @__kmpc_dispatch_fini_4(ptr @[[GLOB1]], i32 [[TMP0]])1450// CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]1451// CHECK3:       omp.inner.for.end:1452// CHECK3-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]1453// CHECK3:       omp.dispatch.inc:1454// CHECK3-NEXT:    br label [[OMP_DISPATCH_COND]]1455// CHECK3:       omp.dispatch.end:1456// CHECK3-NEXT:    call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP0]])1457// CHECK3-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2:[0-9]+]], i32 [[TMP0]])1458// CHECK3-NEXT:    ret void1459//1460//1461// CHECK3-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_1462// CHECK3-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {1463// CHECK3-NEXT:  entry:1464// CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 81465// CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 81466// CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 81467// CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 81468// CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 81469// CHECK3-NEXT:    [[TMP:%.*]] = alloca i64, align 81470// CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 81471// CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 81472// CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 81473// CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41474// CHECK3-NEXT:    [[I:%.*]] = alloca i64, align 81475// CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])1476// CHECK3-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 81477// CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 81478// CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 81479// CHECK3-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 81480// CHECK3-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 81481// CHECK3-NEXT:    store i64 16908287, ptr [[DOTOMP_UB]], align 81482// CHECK3-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 81483// CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 41484// CHECK3-NEXT:    call void @__kmpc_dispatch_init_8u(ptr @[[GLOB1]], i32 [[TMP0]], i32 67, i64 0, i64 16908287, i64 1, i64 1)1485// CHECK3-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]1486// CHECK3:       omp.dispatch.cond:1487// CHECK3-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_8u(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])1488// CHECK3-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 01489// CHECK3-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]1490// CHECK3:       omp.dispatch.body:1491// CHECK3-NEXT:    [[TMP2:%.*]] = load i64, ptr [[DOTOMP_LB]], align 81492// CHECK3-NEXT:    store i64 [[TMP2]], ptr [[DOTOMP_IV]], align 81493// CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]1494// CHECK3:       omp.inner.for.cond:1495// CHECK3-NEXT:    [[TMP3:%.*]] = load i64, ptr [[DOTOMP_IV]], align 81496// CHECK3-NEXT:    [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 81497// CHECK3-NEXT:    [[ADD:%.*]] = add i64 [[TMP4]], 11498// CHECK3-NEXT:    [[CMP:%.*]] = icmp ult i64 [[TMP3]], [[ADD]]1499// CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1500// CHECK3:       omp.inner.for.body:1501// CHECK3-NEXT:    [[TMP5:%.*]] = load i64, ptr [[DOTOMP_IV]], align 81502// CHECK3-NEXT:    [[MUL:%.*]] = mul i64 [[TMP5]], 1271503// CHECK3-NEXT:    [[ADD1:%.*]] = add i64 131071, [[MUL]]1504// CHECK3-NEXT:    store i64 [[ADD1]], ptr [[I]], align 81505// CHECK3-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[TMP0]])1506// CHECK3-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[B_ADDR]], align 81507// CHECK3-NEXT:    [[TMP7:%.*]] = load i64, ptr [[I]], align 81508// CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP6]], i64 [[TMP7]]1509// CHECK3-NEXT:    [[TMP8:%.*]] = load float, ptr [[ARRAYIDX]], align 41510// CHECK3-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[C_ADDR]], align 81511// CHECK3-NEXT:    [[TMP10:%.*]] = load i64, ptr [[I]], align 81512// CHECK3-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw float, ptr [[TMP9]], i64 [[TMP10]]1513// CHECK3-NEXT:    [[TMP11:%.*]] = load float, ptr [[ARRAYIDX2]], align 41514// CHECK3-NEXT:    [[MUL3:%.*]] = fmul float [[TMP8]], [[TMP11]]1515// CHECK3-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[D_ADDR]], align 81516// CHECK3-NEXT:    [[TMP13:%.*]] = load i64, ptr [[I]], align 81517// CHECK3-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw float, ptr [[TMP12]], i64 [[TMP13]]1518// CHECK3-NEXT:    [[TMP14:%.*]] = load float, ptr [[ARRAYIDX4]], align 41519// CHECK3-NEXT:    [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP14]]1520// CHECK3-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[A_ADDR]], align 81521// CHECK3-NEXT:    [[TMP16:%.*]] = load i64, ptr [[I]], align 81522// CHECK3-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds nuw float, ptr [[TMP15]], i64 [[TMP16]]1523// CHECK3-NEXT:    store float [[MUL5]], ptr [[ARRAYIDX6]], align 41524// CHECK3-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[TMP0]])1525// CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]1526// CHECK3:       omp.body.continue:1527// CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]1528// CHECK3:       omp.inner.for.inc:1529// CHECK3-NEXT:    [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 81530// CHECK3-NEXT:    [[ADD7:%.*]] = add i64 [[TMP17]], 11531// CHECK3-NEXT:    store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 81532// CHECK3-NEXT:    call void @__kmpc_dispatch_fini_8u(ptr @[[GLOB1]], i32 [[TMP0]])1533// CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]1534// CHECK3:       omp.inner.for.end:1535// CHECK3-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]1536// CHECK3:       omp.dispatch.inc:1537// CHECK3-NEXT:    br label [[OMP_DISPATCH_COND]]1538// CHECK3:       omp.dispatch.end:1539// CHECK3-NEXT:    call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP0]])1540// CHECK3-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2]], i32 [[TMP0]])1541// CHECK3-NEXT:    ret void1542//1543//1544// CHECK3-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_1545// CHECK3-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {1546// CHECK3-NEXT:  entry:1547// CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 81548// CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 81549// CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 81550// CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 81551// CHECK3-NEXT:    [[X:%.*]] = alloca i32, align 41552// CHECK3-NEXT:    [[Y:%.*]] = alloca i32, align 41553// CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 81554// CHECK3-NEXT:    [[TMP:%.*]] = alloca i8, align 11555// CHECK3-NEXT:    [[_TMP1:%.*]] = alloca i32, align 41556// CHECK3-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 11557// CHECK3-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 81558// CHECK3-NEXT:    [[I:%.*]] = alloca i8, align 11559// CHECK3-NEXT:    [[X6:%.*]] = alloca i32, align 41560// CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 81561// CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 81562// CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 81563// CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41564// CHECK3-NEXT:    [[I8:%.*]] = alloca i8, align 11565// CHECK3-NEXT:    [[X9:%.*]] = alloca i32, align 41566// CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])1567// CHECK3-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 81568// CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 81569// CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 81570// CHECK3-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 81571// CHECK3-NEXT:    store i32 0, ptr [[X]], align 41572// CHECK3-NEXT:    store i32 0, ptr [[Y]], align 41573// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[Y]], align 41574// CHECK3-NEXT:    [[CONV:%.*]] = trunc i32 [[TMP1]] to i81575// CHECK3-NEXT:    store i8 [[CONV]], ptr [[DOTCAPTURE_EXPR_]], align 11576// CHECK3-NEXT:    [[TMP2:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 11577// CHECK3-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP2]] to i321578// CHECK3-NEXT:    [[SUB:%.*]] = sub i32 57, [[CONV3]]1579// CHECK3-NEXT:    [[ADD:%.*]] = add i32 [[SUB]], 11580// CHECK3-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 11581// CHECK3-NEXT:    [[CONV4:%.*]] = zext i32 [[DIV]] to i641582// CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV4]], 111583// CHECK3-NEXT:    [[SUB5:%.*]] = sub nsw i64 [[MUL]], 11584// CHECK3-NEXT:    store i64 [[SUB5]], ptr [[DOTCAPTURE_EXPR_2]], align 81585// CHECK3-NEXT:    [[TMP3:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 11586// CHECK3-NEXT:    store i8 [[TMP3]], ptr [[I]], align 11587// CHECK3-NEXT:    store i32 11, ptr [[X6]], align 41588// CHECK3-NEXT:    [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 11589// CHECK3-NEXT:    [[CONV7:%.*]] = sext i8 [[TMP4]] to i321590// CHECK3-NEXT:    [[CMP:%.*]] = icmp sle i32 [[CONV7]], 571591// CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]1592// CHECK3:       omp.precond.then:1593// CHECK3-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 81594// CHECK3-NEXT:    [[TMP5:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 81595// CHECK3-NEXT:    store i64 [[TMP5]], ptr [[DOTOMP_UB]], align 81596// CHECK3-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 81597// CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 41598// CHECK3-NEXT:    [[TMP6:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 81599// CHECK3-NEXT:    call void @__kmpc_dispatch_init_8(ptr @[[GLOB1]], i32 [[TMP0]], i32 70, i64 0, i64 [[TMP6]], i64 1, i64 1)1600// CHECK3-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]1601// CHECK3:       omp.dispatch.cond:1602// CHECK3-NEXT:    [[TMP7:%.*]] = call i32 @__kmpc_dispatch_next_8(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])1603// CHECK3-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 01604// CHECK3-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]1605// CHECK3:       omp.dispatch.body:1606// CHECK3-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTOMP_LB]], align 81607// CHECK3-NEXT:    store i64 [[TMP8]], ptr [[DOTOMP_IV]], align 81608// CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]1609// CHECK3:       omp.inner.for.cond:1610// CHECK3-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 81611// CHECK3-NEXT:    [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 81612// CHECK3-NEXT:    [[CMP10:%.*]] = icmp sle i64 [[TMP9]], [[TMP10]]1613// CHECK3-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1614// CHECK3:       omp.inner.for.body:1615// CHECK3-NEXT:    [[TMP11:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 11616// CHECK3-NEXT:    [[CONV11:%.*]] = sext i8 [[TMP11]] to i641617// CHECK3-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 81618// CHECK3-NEXT:    [[DIV12:%.*]] = sdiv i64 [[TMP12]], 111619// CHECK3-NEXT:    [[MUL13:%.*]] = mul nsw i64 [[DIV12]], 11620// CHECK3-NEXT:    [[ADD14:%.*]] = add nsw i64 [[CONV11]], [[MUL13]]1621// CHECK3-NEXT:    [[CONV15:%.*]] = trunc i64 [[ADD14]] to i81622// CHECK3-NEXT:    store i8 [[CONV15]], ptr [[I8]], align 11623// CHECK3-NEXT:    [[TMP13:%.*]] = load i64, ptr [[DOTOMP_IV]], align 81624// CHECK3-NEXT:    [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 81625// CHECK3-NEXT:    [[DIV16:%.*]] = sdiv i64 [[TMP14]], 111626// CHECK3-NEXT:    [[MUL17:%.*]] = mul nsw i64 [[DIV16]], 111627// CHECK3-NEXT:    [[SUB18:%.*]] = sub nsw i64 [[TMP13]], [[MUL17]]1628// CHECK3-NEXT:    [[MUL19:%.*]] = mul nsw i64 [[SUB18]], 11629// CHECK3-NEXT:    [[SUB20:%.*]] = sub nsw i64 11, [[MUL19]]1630// CHECK3-NEXT:    [[CONV21:%.*]] = trunc i64 [[SUB20]] to i321631// CHECK3-NEXT:    store i32 [[CONV21]], ptr [[X9]], align 41632// CHECK3-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[TMP0]])1633// CHECK3-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[B_ADDR]], align 81634// CHECK3-NEXT:    [[TMP16:%.*]] = load i8, ptr [[I8]], align 11635// CHECK3-NEXT:    [[IDXPROM:%.*]] = sext i8 [[TMP16]] to i641636// CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[IDXPROM]]1637// CHECK3-NEXT:    [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 41638// CHECK3-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[C_ADDR]], align 81639// CHECK3-NEXT:    [[TMP19:%.*]] = load i8, ptr [[I8]], align 11640// CHECK3-NEXT:    [[IDXPROM22:%.*]] = sext i8 [[TMP19]] to i641641// CHECK3-NEXT:    [[ARRAYIDX23:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[IDXPROM22]]1642// CHECK3-NEXT:    [[TMP20:%.*]] = load float, ptr [[ARRAYIDX23]], align 41643// CHECK3-NEXT:    [[MUL24:%.*]] = fmul float [[TMP17]], [[TMP20]]1644// CHECK3-NEXT:    [[TMP21:%.*]] = load ptr, ptr [[D_ADDR]], align 81645// CHECK3-NEXT:    [[TMP22:%.*]] = load i8, ptr [[I8]], align 11646// CHECK3-NEXT:    [[IDXPROM25:%.*]] = sext i8 [[TMP22]] to i641647// CHECK3-NEXT:    [[ARRAYIDX26:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i64 [[IDXPROM25]]1648// CHECK3-NEXT:    [[TMP23:%.*]] = load float, ptr [[ARRAYIDX26]], align 41649// CHECK3-NEXT:    [[MUL27:%.*]] = fmul float [[MUL24]], [[TMP23]]1650// CHECK3-NEXT:    [[TMP24:%.*]] = load ptr, ptr [[A_ADDR]], align 81651// CHECK3-NEXT:    [[TMP25:%.*]] = load i8, ptr [[I8]], align 11652// CHECK3-NEXT:    [[IDXPROM28:%.*]] = sext i8 [[TMP25]] to i641653// CHECK3-NEXT:    [[ARRAYIDX29:%.*]] = getelementptr inbounds float, ptr [[TMP24]], i64 [[IDXPROM28]]1654// CHECK3-NEXT:    store float [[MUL27]], ptr [[ARRAYIDX29]], align 41655// CHECK3-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[TMP0]])1656// CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]1657// CHECK3:       omp.body.continue:1658// CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]1659// CHECK3:       omp.inner.for.inc:1660// CHECK3-NEXT:    [[TMP26:%.*]] = load i64, ptr [[DOTOMP_IV]], align 81661// CHECK3-NEXT:    [[ADD30:%.*]] = add nsw i64 [[TMP26]], 11662// CHECK3-NEXT:    store i64 [[ADD30]], ptr [[DOTOMP_IV]], align 81663// CHECK3-NEXT:    call void @__kmpc_dispatch_fini_8(ptr @[[GLOB1]], i32 [[TMP0]])1664// CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]1665// CHECK3:       omp.inner.for.end:1666// CHECK3-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]1667// CHECK3:       omp.dispatch.inc:1668// CHECK3-NEXT:    br label [[OMP_DISPATCH_COND]]1669// CHECK3:       omp.dispatch.end:1670// CHECK3-NEXT:    call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP0]])1671// CHECK3-NEXT:    br label [[OMP_PRECOND_END]]1672// CHECK3:       omp.precond.end:1673// CHECK3-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2]], i32 [[TMP0]])1674// CHECK3-NEXT:    ret void1675//1676//1677// CHECK3-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_1678// CHECK3-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {1679// CHECK3-NEXT:  entry:1680// CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 81681// CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 81682// CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 81683// CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 81684// CHECK3-NEXT:    [[X:%.*]] = alloca i32, align 41685// CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 41686// CHECK3-NEXT:    [[TMP:%.*]] = alloca i8, align 11687// CHECK3-NEXT:    [[_TMP1:%.*]] = alloca i32, align 41688// CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 41689// CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 41690// CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41691// CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41692// CHECK3-NEXT:    [[I:%.*]] = alloca i8, align 11693// CHECK3-NEXT:    [[X2:%.*]] = alloca i32, align 41694// CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])1695// CHECK3-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 81696// CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 81697// CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 81698// CHECK3-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 81699// CHECK3-NEXT:    store i32 0, ptr [[X]], align 41700// CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 41701// CHECK3-NEXT:    store i32 199, ptr [[DOTOMP_UB]], align 41702// CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 41703// CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 41704// CHECK3-NEXT:    call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP0]], i32 69, i32 0, i32 199, i32 1, i32 1)1705// CHECK3-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]1706// CHECK3:       omp.dispatch.cond:1707// CHECK3-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])1708// CHECK3-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 01709// CHECK3-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]1710// CHECK3:       omp.dispatch.body:1711// CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41712// CHECK3-NEXT:    store i32 [[TMP2]], ptr [[DOTOMP_IV]], align 41713// CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]1714// CHECK3:       omp.inner.for.cond:1715// CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41716// CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41717// CHECK3-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP3]], [[TMP4]]1718// CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1719// CHECK3:       omp.inner.for.body:1720// CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41721// CHECK3-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP5]], 201722// CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 11723// CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 48, [[MUL]]1724// CHECK3-NEXT:    [[CONV:%.*]] = trunc i32 [[ADD]] to i81725// CHECK3-NEXT:    store i8 [[CONV]], ptr [[I]], align 11726// CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41727// CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41728// CHECK3-NEXT:    [[DIV3:%.*]] = sdiv i32 [[TMP7]], 201729// CHECK3-NEXT:    [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 201730// CHECK3-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP6]], [[MUL4]]1731// CHECK3-NEXT:    [[MUL5:%.*]] = mul nsw i32 [[SUB]], 11732// CHECK3-NEXT:    [[ADD6:%.*]] = add nsw i32 -10, [[MUL5]]1733// CHECK3-NEXT:    store i32 [[ADD6]], ptr [[X2]], align 41734// CHECK3-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[TMP0]])1735// CHECK3-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[B_ADDR]], align 81736// CHECK3-NEXT:    [[TMP9:%.*]] = load i8, ptr [[I]], align 11737// CHECK3-NEXT:    [[IDXPROM:%.*]] = zext i8 [[TMP9]] to i641738// CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP8]], i64 [[IDXPROM]]1739// CHECK3-NEXT:    [[TMP10:%.*]] = load float, ptr [[ARRAYIDX]], align 41740// CHECK3-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[C_ADDR]], align 81741// CHECK3-NEXT:    [[TMP12:%.*]] = load i8, ptr [[I]], align 11742// CHECK3-NEXT:    [[IDXPROM7:%.*]] = zext i8 [[TMP12]] to i641743// CHECK3-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds nuw float, ptr [[TMP11]], i64 [[IDXPROM7]]1744// CHECK3-NEXT:    [[TMP13:%.*]] = load float, ptr [[ARRAYIDX8]], align 41745// CHECK3-NEXT:    [[MUL9:%.*]] = fmul float [[TMP10]], [[TMP13]]1746// CHECK3-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[D_ADDR]], align 81747// CHECK3-NEXT:    [[TMP15:%.*]] = load i8, ptr [[I]], align 11748// CHECK3-NEXT:    [[IDXPROM10:%.*]] = zext i8 [[TMP15]] to i641749// CHECK3-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds nuw float, ptr [[TMP14]], i64 [[IDXPROM10]]1750// CHECK3-NEXT:    [[TMP16:%.*]] = load float, ptr [[ARRAYIDX11]], align 41751// CHECK3-NEXT:    [[MUL12:%.*]] = fmul float [[MUL9]], [[TMP16]]1752// CHECK3-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[A_ADDR]], align 81753// CHECK3-NEXT:    [[TMP18:%.*]] = load i8, ptr [[I]], align 11754// CHECK3-NEXT:    [[IDXPROM13:%.*]] = zext i8 [[TMP18]] to i641755// CHECK3-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds nuw float, ptr [[TMP17]], i64 [[IDXPROM13]]1756// CHECK3-NEXT:    store float [[MUL12]], ptr [[ARRAYIDX14]], align 41757// CHECK3-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[TMP0]])1758// CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]1759// CHECK3:       omp.body.continue:1760// CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]1761// CHECK3:       omp.inner.for.inc:1762// CHECK3-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41763// CHECK3-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP19]], 11764// CHECK3-NEXT:    store i32 [[ADD15]], ptr [[DOTOMP_IV]], align 41765// CHECK3-NEXT:    call void @__kmpc_dispatch_fini_4(ptr @[[GLOB1]], i32 [[TMP0]])1766// CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]1767// CHECK3:       omp.inner.for.end:1768// CHECK3-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]1769// CHECK3:       omp.dispatch.inc:1770// CHECK3-NEXT:    br label [[OMP_DISPATCH_COND]]1771// CHECK3:       omp.dispatch.end:1772// CHECK3-NEXT:    call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP0]])1773// CHECK3-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2]], i32 [[TMP0]])1774// CHECK3-NEXT:    ret void1775//1776//1777// CHECK3-LABEL: define {{[^@]+}}@_Z8foo_simdii1778// CHECK3-SAME: (i32 noundef [[LOW:%.*]], i32 noundef [[UP:%.*]]) #[[ATTR3:[0-9]+]] {1779// CHECK3-NEXT:  entry:1780// CHECK3-NEXT:    [[LOW_ADDR:%.*]] = alloca i32, align 41781// CHECK3-NEXT:    [[UP_ADDR:%.*]] = alloca i32, align 41782// CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 41783// CHECK3-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 41784// CHECK3-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 41785// CHECK3-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 41786// CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 41787// CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 41788// CHECK3-NEXT:    [[I5:%.*]] = alloca i32, align 41789// CHECK3-NEXT:    [[DOTOMP_IV16:%.*]] = alloca i32, align 41790// CHECK3-NEXT:    [[_TMP17:%.*]] = alloca i32, align 41791// CHECK3-NEXT:    [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 41792// CHECK3-NEXT:    [[DOTCAPTURE_EXPR_19:%.*]] = alloca i32, align 41793// CHECK3-NEXT:    [[DOTCAPTURE_EXPR_20:%.*]] = alloca i32, align 41794// CHECK3-NEXT:    [[I26:%.*]] = alloca i32, align 41795// CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 41796// CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 41797// CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41798// CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41799// CHECK3-NEXT:    [[I28:%.*]] = alloca i32, align 41800// CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])1801// CHECK3-NEXT:    store i32 [[LOW]], ptr [[LOW_ADDR]], align 41802// CHECK3-NEXT:    store i32 [[UP]], ptr [[UP_ADDR]], align 41803// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[LOW_ADDR]], align 41804// CHECK3-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 41805// CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[UP_ADDR]], align 41806// CHECK3-NEXT:    store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_1]], align 41807// CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 41808// CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41809// CHECK3-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]1810// CHECK3-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 11811// CHECK3-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 11812// CHECK3-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 11813// CHECK3-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 11814// CHECK3-NEXT:    store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 41815// CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41816// CHECK3-NEXT:    store i32 [[TMP5]], ptr [[I]], align 41817// CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41818// CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 41819// CHECK3-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]1820// CHECK3-NEXT:    br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]1821// CHECK3:       simd.if.then:1822// CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IV]], align 41823// CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]1824// CHECK3:       omp.inner.for.cond:1825// CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41826// CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 41827// CHECK3-NEXT:    [[ADD6:%.*]] = add i32 [[TMP9]], 11828// CHECK3-NEXT:    [[CMP7:%.*]] = icmp ult i32 [[TMP8]], [[ADD6]]1829// CHECK3-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1830// CHECK3:       omp.inner.for.body:1831// CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41832// CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41833// CHECK3-NEXT:    [[MUL:%.*]] = mul i32 [[TMP11]], 11834// CHECK3-NEXT:    [[ADD8:%.*]] = add i32 [[TMP10]], [[MUL]]1835// CHECK3-NEXT:    store i32 [[ADD8]], ptr [[I5]], align 41836// CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[I5]], align 41837// CHECK3-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i641838// CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]]1839// CHECK3-NEXT:    store float 0.000000e+00, ptr [[ARRAYIDX]], align 41840// CHECK3-NEXT:    call void @__captured_stmt(ptr [[I5]])1841// CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]1842// CHECK3:       omp.body.continue:1843// CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]1844// CHECK3:       omp.inner.for.inc:1845// CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41846// CHECK3-NEXT:    [[ADD9:%.*]] = add i32 [[TMP13]], 11847// CHECK3-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 41848// CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]1849// CHECK3:       omp.inner.for.end:1850// CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41851// CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 41852// CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41853// CHECK3-NEXT:    [[SUB10:%.*]] = sub i32 [[TMP15]], [[TMP16]]1854// CHECK3-NEXT:    [[SUB11:%.*]] = sub i32 [[SUB10]], 11855// CHECK3-NEXT:    [[ADD12:%.*]] = add i32 [[SUB11]], 11856// CHECK3-NEXT:    [[DIV13:%.*]] = udiv i32 [[ADD12]], 11857// CHECK3-NEXT:    [[MUL14:%.*]] = mul i32 [[DIV13]], 11858// CHECK3-NEXT:    [[ADD15:%.*]] = add i32 [[TMP14]], [[MUL14]]1859// CHECK3-NEXT:    store i32 [[ADD15]], ptr [[I5]], align 41860// CHECK3-NEXT:    br label [[SIMD_IF_END]]1861// CHECK3:       simd.if.end:1862// CHECK3-NEXT:    [[TMP17:%.*]] = load i32, ptr [[LOW_ADDR]], align 41863// CHECK3-NEXT:    store i32 [[TMP17]], ptr [[DOTCAPTURE_EXPR_18]], align 41864// CHECK3-NEXT:    [[TMP18:%.*]] = load i32, ptr [[UP_ADDR]], align 41865// CHECK3-NEXT:    store i32 [[TMP18]], ptr [[DOTCAPTURE_EXPR_19]], align 41866// CHECK3-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 41867// CHECK3-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 41868// CHECK3-NEXT:    [[SUB21:%.*]] = sub i32 [[TMP19]], [[TMP20]]1869// CHECK3-NEXT:    [[SUB22:%.*]] = sub i32 [[SUB21]], 11870// CHECK3-NEXT:    [[ADD23:%.*]] = add i32 [[SUB22]], 11871// CHECK3-NEXT:    [[DIV24:%.*]] = udiv i32 [[ADD23]], 11872// CHECK3-NEXT:    [[SUB25:%.*]] = sub i32 [[DIV24]], 11873// CHECK3-NEXT:    store i32 [[SUB25]], ptr [[DOTCAPTURE_EXPR_20]], align 41874// CHECK3-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 41875// CHECK3-NEXT:    store i32 [[TMP21]], ptr [[I26]], align 41876// CHECK3-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 41877// CHECK3-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 41878// CHECK3-NEXT:    [[CMP27:%.*]] = icmp slt i32 [[TMP22]], [[TMP23]]1879// CHECK3-NEXT:    br i1 [[CMP27]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]1880// CHECK3:       omp.precond.then:1881// CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 41882// CHECK3-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_20]], align 41883// CHECK3-NEXT:    store i32 [[TMP24]], ptr [[DOTOMP_UB]], align 41884// CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 41885// CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 41886// CHECK3-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_20]], align 41887// CHECK3-NEXT:    call void @__kmpc_dispatch_init_4u(ptr @[[GLOB1]], i32 [[TMP0]], i32 66, i32 0, i32 [[TMP25]], i32 1, i32 1)1888// CHECK3-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]1889// CHECK3:       omp.dispatch.cond:1890// CHECK3-NEXT:    [[TMP26:%.*]] = call i32 @__kmpc_dispatch_next_4u(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])1891// CHECK3-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP26]], 01892// CHECK3-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]1893// CHECK3:       omp.dispatch.body:1894// CHECK3-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41895// CHECK3-NEXT:    store i32 [[TMP27]], ptr [[DOTOMP_IV16]], align 41896// CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND29:%.*]]1897// CHECK3:       omp.inner.for.cond29:1898// CHECK3-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTOMP_IV16]], align 41899// CHECK3-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41900// CHECK3-NEXT:    [[ADD30:%.*]] = add i32 [[TMP29]], 11901// CHECK3-NEXT:    [[CMP31:%.*]] = icmp ult i32 [[TMP28]], [[ADD30]]1902// CHECK3-NEXT:    br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END40:%.*]]1903// CHECK3:       omp.inner.for.body32:1904// CHECK3-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 41905// CHECK3-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IV16]], align 41906// CHECK3-NEXT:    [[MUL33:%.*]] = mul i32 [[TMP31]], 11907// CHECK3-NEXT:    [[ADD34:%.*]] = add i32 [[TMP30]], [[MUL33]]1908// CHECK3-NEXT:    store i32 [[ADD34]], ptr [[I28]], align 41909// CHECK3-NEXT:    [[TMP32:%.*]] = load i32, ptr [[I28]], align 41910// CHECK3-NEXT:    [[IDXPROM35:%.*]] = sext i32 [[TMP32]] to i641911// CHECK3-NEXT:    [[ARRAYIDX36:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM35]]1912// CHECK3-NEXT:    store float 0.000000e+00, ptr [[ARRAYIDX36]], align 41913// CHECK3-NEXT:    call void @__captured_stmt.1(ptr [[I28]])1914// CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE37:%.*]]1915// CHECK3:       omp.body.continue37:1916// CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC38:%.*]]1917// CHECK3:       omp.inner.for.inc38:1918// CHECK3-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTOMP_IV16]], align 41919// CHECK3-NEXT:    [[ADD39:%.*]] = add i32 [[TMP33]], 11920// CHECK3-NEXT:    store i32 [[ADD39]], ptr [[DOTOMP_IV16]], align 41921// CHECK3-NEXT:    call void @__kmpc_dispatch_fini_4u(ptr @[[GLOB1]], i32 [[TMP0]])1922// CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP5:![0-9]+]]1923// CHECK3:       omp.inner.for.end40:1924// CHECK3-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]1925// CHECK3:       omp.dispatch.inc:1926// CHECK3-NEXT:    br label [[OMP_DISPATCH_COND]]1927// CHECK3:       omp.dispatch.end:1928// CHECK3-NEXT:    call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP0]])1929// CHECK3-NEXT:    [[TMP34:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 41930// CHECK3-NEXT:    [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 01931// CHECK3-NEXT:    br i1 [[TMP35]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]1932// CHECK3:       .omp.final.then:1933// CHECK3-NEXT:    [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 41934// CHECK3-NEXT:    [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 41935// CHECK3-NEXT:    [[TMP38:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 41936// CHECK3-NEXT:    [[SUB41:%.*]] = sub i32 [[TMP37]], [[TMP38]]1937// CHECK3-NEXT:    [[SUB42:%.*]] = sub i32 [[SUB41]], 11938// CHECK3-NEXT:    [[ADD43:%.*]] = add i32 [[SUB42]], 11939// CHECK3-NEXT:    [[DIV44:%.*]] = udiv i32 [[ADD43]], 11940// CHECK3-NEXT:    [[MUL45:%.*]] = mul i32 [[DIV44]], 11941// CHECK3-NEXT:    [[ADD46:%.*]] = add i32 [[TMP36]], [[MUL45]]1942// CHECK3-NEXT:    store i32 [[ADD46]], ptr [[I28]], align 41943// CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]1944// CHECK3:       .omp.final.done:1945// CHECK3-NEXT:    br label [[OMP_PRECOND_END]]1946// CHECK3:       omp.precond.end:1947// CHECK3-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2]], i32 [[TMP0]])1948// CHECK3-NEXT:    ret void1949//1950//1951// CHECK3-LABEL: define {{[^@]+}}@__captured_stmt1952// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR4:[0-9]+]] {1953// CHECK3-NEXT:  entry:1954// CHECK3-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 81955// CHECK3-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 81956// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 81957// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 41958// CHECK3-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i641959// CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]]1960// CHECK3-NEXT:    store float 1.000000e+00, ptr [[ARRAYIDX]], align 41961// CHECK3-NEXT:    ret void1962//1963//1964// CHECK3-LABEL: define {{[^@]+}}@__captured_stmt.11965// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR4]] {1966// CHECK3-NEXT:  entry:1967// CHECK3-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 81968// CHECK3-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 81969// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 81970// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 41971// CHECK3-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i641972// CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]]1973// CHECK3-NEXT:    store float 1.000000e+00, ptr [[ARRAYIDX]], align 41974// CHECK3-NEXT:    ret void1975//1976//1977// CHECK3-IRBUILDER-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_1978// CHECK3-IRBUILDER-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] {1979// CHECK3-IRBUILDER-NEXT:  entry:1980// CHECK3-IRBUILDER-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 81981// CHECK3-IRBUILDER-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 81982// CHECK3-IRBUILDER-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 81983// CHECK3-IRBUILDER-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 81984// CHECK3-IRBUILDER-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 41985// CHECK3-IRBUILDER-NEXT:    [[TMP:%.*]] = alloca i32, align 41986// CHECK3-IRBUILDER-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 41987// CHECK3-IRBUILDER-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 41988// CHECK3-IRBUILDER-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41989// CHECK3-IRBUILDER-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41990// CHECK3-IRBUILDER-NEXT:    [[I:%.*]] = alloca i32, align 41991// CHECK3-IRBUILDER-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 81992// CHECK3-IRBUILDER-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 81993// CHECK3-IRBUILDER-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 81994// CHECK3-IRBUILDER-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 81995// CHECK3-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 41996// CHECK3-IRBUILDER-NEXT:    store i32 4571423, ptr [[DOTOMP_UB]], align 41997// CHECK3-IRBUILDER-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 41998// CHECK3-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 41999// CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]])2000// CHECK3-IRBUILDER-NEXT:    call void @__kmpc_dispatch_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 66, i32 0, i32 4571423, i32 1, i32 1)2001// CHECK3-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]2002// CHECK3-IRBUILDER:       omp.dispatch.cond:2003// CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3]])2004// CHECK3-IRBUILDER-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM1]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])2005// CHECK3-IRBUILDER-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 02006// CHECK3-IRBUILDER-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]2007// CHECK3-IRBUILDER:       omp.dispatch.body:2008// CHECK3-IRBUILDER-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42009// CHECK3-IRBUILDER-NEXT:    store i32 [[TMP1]], ptr [[DOTOMP_IV]], align 42010// CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]2011// CHECK3-IRBUILDER:       omp.inner.for.cond:2012// CHECK3-IRBUILDER-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42013// CHECK3-IRBUILDER-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42014// CHECK3-IRBUILDER-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]2015// CHECK3-IRBUILDER-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2016// CHECK3-IRBUILDER:       omp.inner.for.body:2017// CHECK3-IRBUILDER-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42018// CHECK3-IRBUILDER-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP4]], 72019// CHECK3-IRBUILDER-NEXT:    [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]2020// CHECK3-IRBUILDER-NEXT:    store i32 [[SUB]], ptr [[I]], align 42021// CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])2022// CHECK3-IRBUILDER-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM2]])2023// CHECK3-IRBUILDER-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[B_ADDR]], align 82024// CHECK3-IRBUILDER-NEXT:    [[TMP6:%.*]] = load i32, ptr [[I]], align 42025// CHECK3-IRBUILDER-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i642026// CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP5]], i64 [[IDXPROM]]2027// CHECK3-IRBUILDER-NEXT:    [[TMP7:%.*]] = load float, ptr [[ARRAYIDX]], align 42028// CHECK3-IRBUILDER-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[C_ADDR]], align 82029// CHECK3-IRBUILDER-NEXT:    [[TMP9:%.*]] = load i32, ptr [[I]], align 42030// CHECK3-IRBUILDER-NEXT:    [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i642031// CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP8]], i64 [[IDXPROM3]]2032// CHECK3-IRBUILDER-NEXT:    [[TMP10:%.*]] = load float, ptr [[ARRAYIDX4]], align 42033// CHECK3-IRBUILDER-NEXT:    [[MUL5:%.*]] = fmul float [[TMP7]], [[TMP10]]2034// CHECK3-IRBUILDER-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[D_ADDR]], align 82035// CHECK3-IRBUILDER-NEXT:    [[TMP12:%.*]] = load i32, ptr [[I]], align 42036// CHECK3-IRBUILDER-NEXT:    [[IDXPROM6:%.*]] = sext i32 [[TMP12]] to i642037// CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP11]], i64 [[IDXPROM6]]2038// CHECK3-IRBUILDER-NEXT:    [[TMP13:%.*]] = load float, ptr [[ARRAYIDX7]], align 42039// CHECK3-IRBUILDER-NEXT:    [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP13]]2040// CHECK3-IRBUILDER-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[A_ADDR]], align 82041// CHECK3-IRBUILDER-NEXT:    [[TMP15:%.*]] = load i32, ptr [[I]], align 42042// CHECK3-IRBUILDER-NEXT:    [[IDXPROM9:%.*]] = sext i32 [[TMP15]] to i642043// CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 [[IDXPROM9]]2044// CHECK3-IRBUILDER-NEXT:    store float [[MUL8]], ptr [[ARRAYIDX10]], align 42045// CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]]2046// CHECK3-IRBUILDER:       omp.inner.for.body.ordered.after:2047// CHECK3-IRBUILDER-NEXT:    br label [[OMP_REGION_FINALIZE:%.*]]2048// CHECK3-IRBUILDER:       omp_region.finalize:2049// CHECK3-IRBUILDER-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM2]])2050// CHECK3-IRBUILDER-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]2051// CHECK3-IRBUILDER:       omp.body.continue:2052// CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]2053// CHECK3-IRBUILDER:       omp.inner.for.inc:2054// CHECK3-IRBUILDER-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42055// CHECK3-IRBUILDER-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP16]], 12056// CHECK3-IRBUILDER-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 42057// CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM11:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3]])2058// CHECK3-IRBUILDER-NEXT:    call void @__kmpc_dispatch_fini_4(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM11]])2059// CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND]]2060// CHECK3-IRBUILDER:       omp.inner.for.end:2061// CHECK3-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]2062// CHECK3-IRBUILDER:       omp.dispatch.inc:2063// CHECK3-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND]]2064// CHECK3-IRBUILDER:       omp.dispatch.end:2065// CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM12:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3]])2066// CHECK3-IRBUILDER-NEXT:    call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM12]])2067// CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM13:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])2068// CHECK3-IRBUILDER-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB4:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM13]])2069// CHECK3-IRBUILDER-NEXT:    ret void2070//2071//2072// CHECK3-IRBUILDER-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_2073// CHECK3-IRBUILDER-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {2074// CHECK3-IRBUILDER-NEXT:  entry:2075// CHECK3-IRBUILDER-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 82076// CHECK3-IRBUILDER-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 82077// CHECK3-IRBUILDER-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 82078// CHECK3-IRBUILDER-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 82079// CHECK3-IRBUILDER-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 82080// CHECK3-IRBUILDER-NEXT:    [[TMP:%.*]] = alloca i64, align 82081// CHECK3-IRBUILDER-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 82082// CHECK3-IRBUILDER-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 82083// CHECK3-IRBUILDER-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 82084// CHECK3-IRBUILDER-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42085// CHECK3-IRBUILDER-NEXT:    [[I:%.*]] = alloca i64, align 82086// CHECK3-IRBUILDER-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 82087// CHECK3-IRBUILDER-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 82088// CHECK3-IRBUILDER-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 82089// CHECK3-IRBUILDER-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 82090// CHECK3-IRBUILDER-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 82091// CHECK3-IRBUILDER-NEXT:    store i64 16908287, ptr [[DOTOMP_UB]], align 82092// CHECK3-IRBUILDER-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 82093// CHECK3-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 42094// CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB6:[0-9]+]])2095// CHECK3-IRBUILDER-NEXT:    call void @__kmpc_dispatch_init_8u(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 67, i64 0, i64 16908287, i64 1, i64 1)2096// CHECK3-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]2097// CHECK3-IRBUILDER:       omp.dispatch.cond:2098// CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB6]])2099// CHECK3-IRBUILDER-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_dispatch_next_8u(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM1]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])2100// CHECK3-IRBUILDER-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 02101// CHECK3-IRBUILDER-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]2102// CHECK3-IRBUILDER:       omp.dispatch.body:2103// CHECK3-IRBUILDER-NEXT:    [[TMP1:%.*]] = load i64, ptr [[DOTOMP_LB]], align 82104// CHECK3-IRBUILDER-NEXT:    store i64 [[TMP1]], ptr [[DOTOMP_IV]], align 82105// CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]2106// CHECK3-IRBUILDER:       omp.inner.for.cond:2107// CHECK3-IRBUILDER-NEXT:    [[TMP2:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82108// CHECK3-IRBUILDER-NEXT:    [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 82109// CHECK3-IRBUILDER-NEXT:    [[ADD:%.*]] = add i64 [[TMP3]], 12110// CHECK3-IRBUILDER-NEXT:    [[CMP:%.*]] = icmp ult i64 [[TMP2]], [[ADD]]2111// CHECK3-IRBUILDER-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2112// CHECK3-IRBUILDER:       omp.inner.for.body:2113// CHECK3-IRBUILDER-NEXT:    [[TMP4:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82114// CHECK3-IRBUILDER-NEXT:    [[MUL:%.*]] = mul i64 [[TMP4]], 1272115// CHECK3-IRBUILDER-NEXT:    [[ADD2:%.*]] = add i64 131071, [[MUL]]2116// CHECK3-IRBUILDER-NEXT:    store i64 [[ADD2]], ptr [[I]], align 82117// CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])2118// CHECK3-IRBUILDER-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM3]])2119// CHECK3-IRBUILDER-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[B_ADDR]], align 82120// CHECK3-IRBUILDER-NEXT:    [[TMP6:%.*]] = load i64, ptr [[I]], align 82121// CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP5]], i64 [[TMP6]]2122// CHECK3-IRBUILDER-NEXT:    [[TMP7:%.*]] = load float, ptr [[ARRAYIDX]], align 42123// CHECK3-IRBUILDER-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[C_ADDR]], align 82124// CHECK3-IRBUILDER-NEXT:    [[TMP9:%.*]] = load i64, ptr [[I]], align 82125// CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw float, ptr [[TMP8]], i64 [[TMP9]]2126// CHECK3-IRBUILDER-NEXT:    [[TMP10:%.*]] = load float, ptr [[ARRAYIDX4]], align 42127// CHECK3-IRBUILDER-NEXT:    [[MUL5:%.*]] = fmul float [[TMP7]], [[TMP10]]2128// CHECK3-IRBUILDER-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[D_ADDR]], align 82129// CHECK3-IRBUILDER-NEXT:    [[TMP12:%.*]] = load i64, ptr [[I]], align 82130// CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds nuw float, ptr [[TMP11]], i64 [[TMP12]]2131// CHECK3-IRBUILDER-NEXT:    [[TMP13:%.*]] = load float, ptr [[ARRAYIDX6]], align 42132// CHECK3-IRBUILDER-NEXT:    [[MUL7:%.*]] = fmul float [[MUL5]], [[TMP13]]2133// CHECK3-IRBUILDER-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[A_ADDR]], align 82134// CHECK3-IRBUILDER-NEXT:    [[TMP15:%.*]] = load i64, ptr [[I]], align 82135// CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds nuw float, ptr [[TMP14]], i64 [[TMP15]]2136// CHECK3-IRBUILDER-NEXT:    store float [[MUL7]], ptr [[ARRAYIDX8]], align 42137// CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]]2138// CHECK3-IRBUILDER:       omp.inner.for.body.ordered.after:2139// CHECK3-IRBUILDER-NEXT:    br label [[OMP_REGION_FINALIZE:%.*]]2140// CHECK3-IRBUILDER:       omp_region.finalize:2141// CHECK3-IRBUILDER-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM3]])2142// CHECK3-IRBUILDER-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]2143// CHECK3-IRBUILDER:       omp.body.continue:2144// CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]2145// CHECK3-IRBUILDER:       omp.inner.for.inc:2146// CHECK3-IRBUILDER-NEXT:    [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82147// CHECK3-IRBUILDER-NEXT:    [[ADD9:%.*]] = add i64 [[TMP16]], 12148// CHECK3-IRBUILDER-NEXT:    store i64 [[ADD9]], ptr [[DOTOMP_IV]], align 82149// CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM10:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB6]])2150// CHECK3-IRBUILDER-NEXT:    call void @__kmpc_dispatch_fini_8u(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM10]])2151// CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND]]2152// CHECK3-IRBUILDER:       omp.inner.for.end:2153// CHECK3-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]2154// CHECK3-IRBUILDER:       omp.dispatch.inc:2155// CHECK3-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND]]2156// CHECK3-IRBUILDER:       omp.dispatch.end:2157// CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM11:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB6]])2158// CHECK3-IRBUILDER-NEXT:    call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM11]])2159// CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM12:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])2160// CHECK3-IRBUILDER-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM12]])2161// CHECK3-IRBUILDER-NEXT:    ret void2162//2163//2164// CHECK3-IRBUILDER-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_2165// CHECK3-IRBUILDER-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {2166// CHECK3-IRBUILDER-NEXT:  entry:2167// CHECK3-IRBUILDER-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 82168// CHECK3-IRBUILDER-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 82169// CHECK3-IRBUILDER-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 82170// CHECK3-IRBUILDER-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 82171// CHECK3-IRBUILDER-NEXT:    [[X:%.*]] = alloca i32, align 42172// CHECK3-IRBUILDER-NEXT:    [[Y:%.*]] = alloca i32, align 42173// CHECK3-IRBUILDER-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 82174// CHECK3-IRBUILDER-NEXT:    [[TMP:%.*]] = alloca i8, align 12175// CHECK3-IRBUILDER-NEXT:    [[_TMP1:%.*]] = alloca i32, align 42176// CHECK3-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 12177// CHECK3-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 82178// CHECK3-IRBUILDER-NEXT:    [[I:%.*]] = alloca i8, align 12179// CHECK3-IRBUILDER-NEXT:    [[X6:%.*]] = alloca i32, align 42180// CHECK3-IRBUILDER-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 82181// CHECK3-IRBUILDER-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 82182// CHECK3-IRBUILDER-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 82183// CHECK3-IRBUILDER-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42184// CHECK3-IRBUILDER-NEXT:    [[I8:%.*]] = alloca i8, align 12185// CHECK3-IRBUILDER-NEXT:    [[X9:%.*]] = alloca i32, align 42186// CHECK3-IRBUILDER-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 82187// CHECK3-IRBUILDER-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 82188// CHECK3-IRBUILDER-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 82189// CHECK3-IRBUILDER-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 82190// CHECK3-IRBUILDER-NEXT:    store i32 0, ptr [[X]], align 42191// CHECK3-IRBUILDER-NEXT:    store i32 0, ptr [[Y]], align 42192// CHECK3-IRBUILDER-NEXT:    [[TMP0:%.*]] = load i32, ptr [[Y]], align 42193// CHECK3-IRBUILDER-NEXT:    [[CONV:%.*]] = trunc i32 [[TMP0]] to i82194// CHECK3-IRBUILDER-NEXT:    store i8 [[CONV]], ptr [[DOTCAPTURE_EXPR_]], align 12195// CHECK3-IRBUILDER-NEXT:    [[TMP1:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 12196// CHECK3-IRBUILDER-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP1]] to i322197// CHECK3-IRBUILDER-NEXT:    [[SUB:%.*]] = sub i32 57, [[CONV3]]2198// CHECK3-IRBUILDER-NEXT:    [[ADD:%.*]] = add i32 [[SUB]], 12199// CHECK3-IRBUILDER-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 12200// CHECK3-IRBUILDER-NEXT:    [[CONV4:%.*]] = zext i32 [[DIV]] to i642201// CHECK3-IRBUILDER-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV4]], 112202// CHECK3-IRBUILDER-NEXT:    [[SUB5:%.*]] = sub nsw i64 [[MUL]], 12203// CHECK3-IRBUILDER-NEXT:    store i64 [[SUB5]], ptr [[DOTCAPTURE_EXPR_2]], align 82204// CHECK3-IRBUILDER-NEXT:    [[TMP2:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 12205// CHECK3-IRBUILDER-NEXT:    store i8 [[TMP2]], ptr [[I]], align 12206// CHECK3-IRBUILDER-NEXT:    store i32 11, ptr [[X6]], align 42207// CHECK3-IRBUILDER-NEXT:    [[TMP3:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 12208// CHECK3-IRBUILDER-NEXT:    [[CONV7:%.*]] = sext i8 [[TMP3]] to i322209// CHECK3-IRBUILDER-NEXT:    [[CMP:%.*]] = icmp sle i32 [[CONV7]], 572210// CHECK3-IRBUILDER-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]2211// CHECK3-IRBUILDER:       omp.precond.then:2212// CHECK3-IRBUILDER-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 82213// CHECK3-IRBUILDER-NEXT:    [[TMP4:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 82214// CHECK3-IRBUILDER-NEXT:    store i64 [[TMP4]], ptr [[DOTOMP_UB]], align 82215// CHECK3-IRBUILDER-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 82216// CHECK3-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 42217// CHECK3-IRBUILDER-NEXT:    [[TMP5:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 82218// CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB8:[0-9]+]])2219// CHECK3-IRBUILDER-NEXT:    call void @__kmpc_dispatch_init_8(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 70, i64 0, i64 [[TMP5]], i64 1, i64 1)2220// CHECK3-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]2221// CHECK3-IRBUILDER:       omp.dispatch.cond:2222// CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM10:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB8]])2223// CHECK3-IRBUILDER-NEXT:    [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM10]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])2224// CHECK3-IRBUILDER-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 02225// CHECK3-IRBUILDER-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]2226// CHECK3-IRBUILDER:       omp.dispatch.body:2227// CHECK3-IRBUILDER-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTOMP_LB]], align 82228// CHECK3-IRBUILDER-NEXT:    store i64 [[TMP7]], ptr [[DOTOMP_IV]], align 82229// CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]2230// CHECK3-IRBUILDER:       omp.inner.for.cond:2231// CHECK3-IRBUILDER-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82232// CHECK3-IRBUILDER-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB]], align 82233// CHECK3-IRBUILDER-NEXT:    [[CMP11:%.*]] = icmp sle i64 [[TMP8]], [[TMP9]]2234// CHECK3-IRBUILDER-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2235// CHECK3-IRBUILDER:       omp.inner.for.body:2236// CHECK3-IRBUILDER-NEXT:    [[TMP10:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 12237// CHECK3-IRBUILDER-NEXT:    [[CONV12:%.*]] = sext i8 [[TMP10]] to i642238// CHECK3-IRBUILDER-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82239// CHECK3-IRBUILDER-NEXT:    [[DIV13:%.*]] = sdiv i64 [[TMP11]], 112240// CHECK3-IRBUILDER-NEXT:    [[MUL14:%.*]] = mul nsw i64 [[DIV13]], 12241// CHECK3-IRBUILDER-NEXT:    [[ADD15:%.*]] = add nsw i64 [[CONV12]], [[MUL14]]2242// CHECK3-IRBUILDER-NEXT:    [[CONV16:%.*]] = trunc i64 [[ADD15]] to i82243// CHECK3-IRBUILDER-NEXT:    store i8 [[CONV16]], ptr [[I8]], align 12244// CHECK3-IRBUILDER-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82245// CHECK3-IRBUILDER-NEXT:    [[TMP13:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82246// CHECK3-IRBUILDER-NEXT:    [[DIV17:%.*]] = sdiv i64 [[TMP13]], 112247// CHECK3-IRBUILDER-NEXT:    [[MUL18:%.*]] = mul nsw i64 [[DIV17]], 112248// CHECK3-IRBUILDER-NEXT:    [[SUB19:%.*]] = sub nsw i64 [[TMP12]], [[MUL18]]2249// CHECK3-IRBUILDER-NEXT:    [[MUL20:%.*]] = mul nsw i64 [[SUB19]], 12250// CHECK3-IRBUILDER-NEXT:    [[SUB21:%.*]] = sub nsw i64 11, [[MUL20]]2251// CHECK3-IRBUILDER-NEXT:    [[CONV22:%.*]] = trunc i64 [[SUB21]] to i322252// CHECK3-IRBUILDER-NEXT:    store i32 [[CONV22]], ptr [[X9]], align 42253// CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM23:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])2254// CHECK3-IRBUILDER-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM23]])2255// CHECK3-IRBUILDER-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[B_ADDR]], align 82256// CHECK3-IRBUILDER-NEXT:    [[TMP15:%.*]] = load i8, ptr [[I8]], align 12257// CHECK3-IRBUILDER-NEXT:    [[IDXPROM:%.*]] = sext i8 [[TMP15]] to i642258// CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 [[IDXPROM]]2259// CHECK3-IRBUILDER-NEXT:    [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 42260// CHECK3-IRBUILDER-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[C_ADDR]], align 82261// CHECK3-IRBUILDER-NEXT:    [[TMP18:%.*]] = load i8, ptr [[I8]], align 12262// CHECK3-IRBUILDER-NEXT:    [[IDXPROM24:%.*]] = sext i8 [[TMP18]] to i642263// CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX25:%.*]] = getelementptr inbounds float, ptr [[TMP17]], i64 [[IDXPROM24]]2264// CHECK3-IRBUILDER-NEXT:    [[TMP19:%.*]] = load float, ptr [[ARRAYIDX25]], align 42265// CHECK3-IRBUILDER-NEXT:    [[MUL26:%.*]] = fmul float [[TMP16]], [[TMP19]]2266// CHECK3-IRBUILDER-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[D_ADDR]], align 82267// CHECK3-IRBUILDER-NEXT:    [[TMP21:%.*]] = load i8, ptr [[I8]], align 12268// CHECK3-IRBUILDER-NEXT:    [[IDXPROM27:%.*]] = sext i8 [[TMP21]] to i642269// CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX28:%.*]] = getelementptr inbounds float, ptr [[TMP20]], i64 [[IDXPROM27]]2270// CHECK3-IRBUILDER-NEXT:    [[TMP22:%.*]] = load float, ptr [[ARRAYIDX28]], align 42271// CHECK3-IRBUILDER-NEXT:    [[MUL29:%.*]] = fmul float [[MUL26]], [[TMP22]]2272// CHECK3-IRBUILDER-NEXT:    [[TMP23:%.*]] = load ptr, ptr [[A_ADDR]], align 82273// CHECK3-IRBUILDER-NEXT:    [[TMP24:%.*]] = load i8, ptr [[I8]], align 12274// CHECK3-IRBUILDER-NEXT:    [[IDXPROM30:%.*]] = sext i8 [[TMP24]] to i642275// CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX31:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i64 [[IDXPROM30]]2276// CHECK3-IRBUILDER-NEXT:    store float [[MUL29]], ptr [[ARRAYIDX31]], align 42277// CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]]2278// CHECK3-IRBUILDER:       omp.inner.for.body.ordered.after:2279// CHECK3-IRBUILDER-NEXT:    br label [[OMP_REGION_FINALIZE:%.*]]2280// CHECK3-IRBUILDER:       omp_region.finalize:2281// CHECK3-IRBUILDER-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM23]])2282// CHECK3-IRBUILDER-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]2283// CHECK3-IRBUILDER:       omp.body.continue:2284// CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]2285// CHECK3-IRBUILDER:       omp.inner.for.inc:2286// CHECK3-IRBUILDER-NEXT:    [[TMP25:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82287// CHECK3-IRBUILDER-NEXT:    [[ADD32:%.*]] = add nsw i64 [[TMP25]], 12288// CHECK3-IRBUILDER-NEXT:    store i64 [[ADD32]], ptr [[DOTOMP_IV]], align 82289// CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM33:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB8]])2290// CHECK3-IRBUILDER-NEXT:    call void @__kmpc_dispatch_fini_8(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM33]])2291// CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND]]2292// CHECK3-IRBUILDER:       omp.inner.for.end:2293// CHECK3-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]2294// CHECK3-IRBUILDER:       omp.dispatch.inc:2295// CHECK3-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND]]2296// CHECK3-IRBUILDER:       omp.dispatch.end:2297// CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM34:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB8]])2298// CHECK3-IRBUILDER-NEXT:    call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM34]])2299// CHECK3-IRBUILDER-NEXT:    br label [[OMP_PRECOND_END]]2300// CHECK3-IRBUILDER:       omp.precond.end:2301// CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM35:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])2302// CHECK3-IRBUILDER-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM35]])2303// CHECK3-IRBUILDER-NEXT:    ret void2304//2305//2306// CHECK3-IRBUILDER-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_2307// CHECK3-IRBUILDER-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {2308// CHECK3-IRBUILDER-NEXT:  entry:2309// CHECK3-IRBUILDER-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 82310// CHECK3-IRBUILDER-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 82311// CHECK3-IRBUILDER-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 82312// CHECK3-IRBUILDER-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 82313// CHECK3-IRBUILDER-NEXT:    [[X:%.*]] = alloca i32, align 42314// CHECK3-IRBUILDER-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 42315// CHECK3-IRBUILDER-NEXT:    [[TMP:%.*]] = alloca i8, align 12316// CHECK3-IRBUILDER-NEXT:    [[_TMP1:%.*]] = alloca i32, align 42317// CHECK3-IRBUILDER-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 42318// CHECK3-IRBUILDER-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 42319// CHECK3-IRBUILDER-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42320// CHECK3-IRBUILDER-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42321// CHECK3-IRBUILDER-NEXT:    [[I:%.*]] = alloca i8, align 12322// CHECK3-IRBUILDER-NEXT:    [[X2:%.*]] = alloca i32, align 42323// CHECK3-IRBUILDER-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 82324// CHECK3-IRBUILDER-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 82325// CHECK3-IRBUILDER-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 82326// CHECK3-IRBUILDER-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 82327// CHECK3-IRBUILDER-NEXT:    store i32 0, ptr [[X]], align 42328// CHECK3-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 42329// CHECK3-IRBUILDER-NEXT:    store i32 199, ptr [[DOTOMP_UB]], align 42330// CHECK3-IRBUILDER-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 42331// CHECK3-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 42332// CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB10:[0-9]+]])2333// CHECK3-IRBUILDER-NEXT:    call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 69, i32 0, i32 199, i32 1, i32 1)2334// CHECK3-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]2335// CHECK3-IRBUILDER:       omp.dispatch.cond:2336// CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB10]])2337// CHECK3-IRBUILDER-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM3]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])2338// CHECK3-IRBUILDER-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 02339// CHECK3-IRBUILDER-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]2340// CHECK3-IRBUILDER:       omp.dispatch.body:2341// CHECK3-IRBUILDER-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42342// CHECK3-IRBUILDER-NEXT:    store i32 [[TMP1]], ptr [[DOTOMP_IV]], align 42343// CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]2344// CHECK3-IRBUILDER:       omp.inner.for.cond:2345// CHECK3-IRBUILDER-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42346// CHECK3-IRBUILDER-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42347// CHECK3-IRBUILDER-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]2348// CHECK3-IRBUILDER-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2349// CHECK3-IRBUILDER:       omp.inner.for.body:2350// CHECK3-IRBUILDER-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42351// CHECK3-IRBUILDER-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP4]], 202352// CHECK3-IRBUILDER-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 12353// CHECK3-IRBUILDER-NEXT:    [[ADD:%.*]] = add nsw i32 48, [[MUL]]2354// CHECK3-IRBUILDER-NEXT:    [[CONV:%.*]] = trunc i32 [[ADD]] to i82355// CHECK3-IRBUILDER-NEXT:    store i8 [[CONV]], ptr [[I]], align 12356// CHECK3-IRBUILDER-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42357// CHECK3-IRBUILDER-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42358// CHECK3-IRBUILDER-NEXT:    [[DIV4:%.*]] = sdiv i32 [[TMP6]], 202359// CHECK3-IRBUILDER-NEXT:    [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 202360// CHECK3-IRBUILDER-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP5]], [[MUL5]]2361// CHECK3-IRBUILDER-NEXT:    [[MUL6:%.*]] = mul nsw i32 [[SUB]], 12362// CHECK3-IRBUILDER-NEXT:    [[ADD7:%.*]] = add nsw i32 -10, [[MUL6]]2363// CHECK3-IRBUILDER-NEXT:    store i32 [[ADD7]], ptr [[X2]], align 42364// CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM8:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])2365// CHECK3-IRBUILDER-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM8]])2366// CHECK3-IRBUILDER-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[B_ADDR]], align 82367// CHECK3-IRBUILDER-NEXT:    [[TMP8:%.*]] = load i8, ptr [[I]], align 12368// CHECK3-IRBUILDER-NEXT:    [[IDXPROM:%.*]] = zext i8 [[TMP8]] to i642369// CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP7]], i64 [[IDXPROM]]2370// CHECK3-IRBUILDER-NEXT:    [[TMP9:%.*]] = load float, ptr [[ARRAYIDX]], align 42371// CHECK3-IRBUILDER-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[C_ADDR]], align 82372// CHECK3-IRBUILDER-NEXT:    [[TMP11:%.*]] = load i8, ptr [[I]], align 12373// CHECK3-IRBUILDER-NEXT:    [[IDXPROM9:%.*]] = zext i8 [[TMP11]] to i642374// CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds nuw float, ptr [[TMP10]], i64 [[IDXPROM9]]2375// CHECK3-IRBUILDER-NEXT:    [[TMP12:%.*]] = load float, ptr [[ARRAYIDX10]], align 42376// CHECK3-IRBUILDER-NEXT:    [[MUL11:%.*]] = fmul float [[TMP9]], [[TMP12]]2377// CHECK3-IRBUILDER-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[D_ADDR]], align 82378// CHECK3-IRBUILDER-NEXT:    [[TMP14:%.*]] = load i8, ptr [[I]], align 12379// CHECK3-IRBUILDER-NEXT:    [[IDXPROM12:%.*]] = zext i8 [[TMP14]] to i642380// CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX13:%.*]] = getelementptr inbounds nuw float, ptr [[TMP13]], i64 [[IDXPROM12]]2381// CHECK3-IRBUILDER-NEXT:    [[TMP15:%.*]] = load float, ptr [[ARRAYIDX13]], align 42382// CHECK3-IRBUILDER-NEXT:    [[MUL14:%.*]] = fmul float [[MUL11]], [[TMP15]]2383// CHECK3-IRBUILDER-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[A_ADDR]], align 82384// CHECK3-IRBUILDER-NEXT:    [[TMP17:%.*]] = load i8, ptr [[I]], align 12385// CHECK3-IRBUILDER-NEXT:    [[IDXPROM15:%.*]] = zext i8 [[TMP17]] to i642386// CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds nuw float, ptr [[TMP16]], i64 [[IDXPROM15]]2387// CHECK3-IRBUILDER-NEXT:    store float [[MUL14]], ptr [[ARRAYIDX16]], align 42388// CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]]2389// CHECK3-IRBUILDER:       omp.inner.for.body.ordered.after:2390// CHECK3-IRBUILDER-NEXT:    br label [[OMP_REGION_FINALIZE:%.*]]2391// CHECK3-IRBUILDER:       omp_region.finalize:2392// CHECK3-IRBUILDER-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM8]])2393// CHECK3-IRBUILDER-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]2394// CHECK3-IRBUILDER:       omp.body.continue:2395// CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]2396// CHECK3-IRBUILDER:       omp.inner.for.inc:2397// CHECK3-IRBUILDER-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42398// CHECK3-IRBUILDER-NEXT:    [[ADD17:%.*]] = add nsw i32 [[TMP18]], 12399// CHECK3-IRBUILDER-NEXT:    store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 42400// CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM18:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB10]])2401// CHECK3-IRBUILDER-NEXT:    call void @__kmpc_dispatch_fini_4(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM18]])2402// CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND]]2403// CHECK3-IRBUILDER:       omp.inner.for.end:2404// CHECK3-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]2405// CHECK3-IRBUILDER:       omp.dispatch.inc:2406// CHECK3-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND]]2407// CHECK3-IRBUILDER:       omp.dispatch.end:2408// CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM19:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB10]])2409// CHECK3-IRBUILDER-NEXT:    call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM19]])2410// CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM20:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])2411// CHECK3-IRBUILDER-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM20]])2412// CHECK3-IRBUILDER-NEXT:    ret void2413//2414//2415// CHECK3-IRBUILDER-LABEL: define {{[^@]+}}@_Z8foo_simdii2416// CHECK3-IRBUILDER-SAME: (i32 noundef [[LOW:%.*]], i32 noundef [[UP:%.*]]) #[[ATTR3:[0-9]+]] {2417// CHECK3-IRBUILDER-NEXT:  entry:2418// CHECK3-IRBUILDER-NEXT:    [[LOW_ADDR:%.*]] = alloca i32, align 42419// CHECK3-IRBUILDER-NEXT:    [[UP_ADDR:%.*]] = alloca i32, align 42420// CHECK3-IRBUILDER-NEXT:    [[TMP:%.*]] = alloca i32, align 42421// CHECK3-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 42422// CHECK3-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 42423// CHECK3-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 42424// CHECK3-IRBUILDER-NEXT:    [[I:%.*]] = alloca i32, align 42425// CHECK3-IRBUILDER-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 42426// CHECK3-IRBUILDER-NEXT:    [[I5:%.*]] = alloca i32, align 42427// CHECK3-IRBUILDER-NEXT:    [[DOTOMP_IV16:%.*]] = alloca i32, align 42428// CHECK3-IRBUILDER-NEXT:    [[_TMP17:%.*]] = alloca i32, align 42429// CHECK3-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 42430// CHECK3-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_19:%.*]] = alloca i32, align 42431// CHECK3-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_20:%.*]] = alloca i32, align 42432// CHECK3-IRBUILDER-NEXT:    [[I26:%.*]] = alloca i32, align 42433// CHECK3-IRBUILDER-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 42434// CHECK3-IRBUILDER-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 42435// CHECK3-IRBUILDER-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42436// CHECK3-IRBUILDER-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42437// CHECK3-IRBUILDER-NEXT:    [[I28:%.*]] = alloca i32, align 42438// CHECK3-IRBUILDER-NEXT:    store i32 [[LOW]], ptr [[LOW_ADDR]], align 42439// CHECK3-IRBUILDER-NEXT:    store i32 [[UP]], ptr [[UP_ADDR]], align 42440// CHECK3-IRBUILDER-NEXT:    [[TMP0:%.*]] = load i32, ptr [[LOW_ADDR]], align 42441// CHECK3-IRBUILDER-NEXT:    store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 42442// CHECK3-IRBUILDER-NEXT:    [[TMP1:%.*]] = load i32, ptr [[UP_ADDR]], align 42443// CHECK3-IRBUILDER-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_1]], align 42444// CHECK3-IRBUILDER-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 42445// CHECK3-IRBUILDER-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 42446// CHECK3-IRBUILDER-NEXT:    [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]]2447// CHECK3-IRBUILDER-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 12448// CHECK3-IRBUILDER-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 12449// CHECK3-IRBUILDER-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 12450// CHECK3-IRBUILDER-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 12451// CHECK3-IRBUILDER-NEXT:    store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 42452// CHECK3-IRBUILDER-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 42453// CHECK3-IRBUILDER-NEXT:    store i32 [[TMP4]], ptr [[I]], align 42454// CHECK3-IRBUILDER-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 42455// CHECK3-IRBUILDER-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 42456// CHECK3-IRBUILDER-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP5]], [[TMP6]]2457// CHECK3-IRBUILDER-NEXT:    br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]2458// CHECK3-IRBUILDER:       simd.if.then:2459// CHECK3-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_IV]], align 42460// CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]2461// CHECK3-IRBUILDER:       omp.inner.for.cond:2462// CHECK3-IRBUILDER-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42463// CHECK3-IRBUILDER-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 42464// CHECK3-IRBUILDER-NEXT:    [[ADD6:%.*]] = add i32 [[TMP8]], 12465// CHECK3-IRBUILDER-NEXT:    [[CMP7:%.*]] = icmp ult i32 [[TMP7]], [[ADD6]]2466// CHECK3-IRBUILDER-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2467// CHECK3-IRBUILDER:       omp.inner.for.body:2468// CHECK3-IRBUILDER-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 42469// CHECK3-IRBUILDER-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42470// CHECK3-IRBUILDER-NEXT:    [[MUL:%.*]] = mul i32 [[TMP10]], 12471// CHECK3-IRBUILDER-NEXT:    [[ADD8:%.*]] = add i32 [[TMP9]], [[MUL]]2472// CHECK3-IRBUILDER-NEXT:    store i32 [[ADD8]], ptr [[I5]], align 42473// CHECK3-IRBUILDER-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I5]], align 42474// CHECK3-IRBUILDER-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i642475// CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]]2476// CHECK3-IRBUILDER-NEXT:    store float 0.000000e+00, ptr [[ARRAYIDX]], align 42477// CHECK3-IRBUILDER-NEXT:    call void @__captured_stmt(ptr [[I5]])2478// CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]]2479// CHECK3-IRBUILDER:       omp.inner.for.body.ordered.after:2480// CHECK3-IRBUILDER-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]2481// CHECK3-IRBUILDER:       omp.body.continue:2482// CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]2483// CHECK3-IRBUILDER:       omp.inner.for.inc:2484// CHECK3-IRBUILDER-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42485// CHECK3-IRBUILDER-NEXT:    [[ADD9:%.*]] = add i32 [[TMP12]], 12486// CHECK3-IRBUILDER-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 42487// CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]2488// CHECK3-IRBUILDER:       omp.inner.for.end:2489// CHECK3-IRBUILDER-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 42490// CHECK3-IRBUILDER-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 42491// CHECK3-IRBUILDER-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 42492// CHECK3-IRBUILDER-NEXT:    [[SUB10:%.*]] = sub i32 [[TMP14]], [[TMP15]]2493// CHECK3-IRBUILDER-NEXT:    [[SUB11:%.*]] = sub i32 [[SUB10]], 12494// CHECK3-IRBUILDER-NEXT:    [[ADD12:%.*]] = add i32 [[SUB11]], 12495// CHECK3-IRBUILDER-NEXT:    [[DIV13:%.*]] = udiv i32 [[ADD12]], 12496// CHECK3-IRBUILDER-NEXT:    [[MUL14:%.*]] = mul i32 [[DIV13]], 12497// CHECK3-IRBUILDER-NEXT:    [[ADD15:%.*]] = add i32 [[TMP13]], [[MUL14]]2498// CHECK3-IRBUILDER-NEXT:    store i32 [[ADD15]], ptr [[I5]], align 42499// CHECK3-IRBUILDER-NEXT:    br label [[SIMD_IF_END]]2500// CHECK3-IRBUILDER:       simd.if.end:2501// CHECK3-IRBUILDER-NEXT:    [[TMP16:%.*]] = load i32, ptr [[LOW_ADDR]], align 42502// CHECK3-IRBUILDER-NEXT:    store i32 [[TMP16]], ptr [[DOTCAPTURE_EXPR_18]], align 42503// CHECK3-IRBUILDER-NEXT:    [[TMP17:%.*]] = load i32, ptr [[UP_ADDR]], align 42504// CHECK3-IRBUILDER-NEXT:    store i32 [[TMP17]], ptr [[DOTCAPTURE_EXPR_19]], align 42505// CHECK3-IRBUILDER-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 42506// CHECK3-IRBUILDER-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 42507// CHECK3-IRBUILDER-NEXT:    [[SUB21:%.*]] = sub i32 [[TMP18]], [[TMP19]]2508// CHECK3-IRBUILDER-NEXT:    [[SUB22:%.*]] = sub i32 [[SUB21]], 12509// CHECK3-IRBUILDER-NEXT:    [[ADD23:%.*]] = add i32 [[SUB22]], 12510// CHECK3-IRBUILDER-NEXT:    [[DIV24:%.*]] = udiv i32 [[ADD23]], 12511// CHECK3-IRBUILDER-NEXT:    [[SUB25:%.*]] = sub i32 [[DIV24]], 12512// CHECK3-IRBUILDER-NEXT:    store i32 [[SUB25]], ptr [[DOTCAPTURE_EXPR_20]], align 42513// CHECK3-IRBUILDER-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 42514// CHECK3-IRBUILDER-NEXT:    store i32 [[TMP20]], ptr [[I26]], align 42515// CHECK3-IRBUILDER-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 42516// CHECK3-IRBUILDER-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 42517// CHECK3-IRBUILDER-NEXT:    [[CMP27:%.*]] = icmp slt i32 [[TMP21]], [[TMP22]]2518// CHECK3-IRBUILDER-NEXT:    br i1 [[CMP27]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]2519// CHECK3-IRBUILDER:       omp.precond.then:2520// CHECK3-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 42521// CHECK3-IRBUILDER-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_20]], align 42522// CHECK3-IRBUILDER-NEXT:    store i32 [[TMP23]], ptr [[DOTOMP_UB]], align 42523// CHECK3-IRBUILDER-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 42524// CHECK3-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 42525// CHECK3-IRBUILDER-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_20]], align 42526// CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB12:[0-9]+]])2527// CHECK3-IRBUILDER-NEXT:    call void @__kmpc_dispatch_init_4u(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 66, i32 0, i32 [[TMP24]], i32 1, i32 1)2528// CHECK3-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]2529// CHECK3-IRBUILDER:       omp.dispatch.cond:2530// CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM29:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB12]])2531// CHECK3-IRBUILDER-NEXT:    [[TMP25:%.*]] = call i32 @__kmpc_dispatch_next_4u(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM29]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])2532// CHECK3-IRBUILDER-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP25]], 02533// CHECK3-IRBUILDER-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]2534// CHECK3-IRBUILDER:       omp.dispatch.body:2535// CHECK3-IRBUILDER-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42536// CHECK3-IRBUILDER-NEXT:    store i32 [[TMP26]], ptr [[DOTOMP_IV16]], align 42537// CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND30:%.*]]2538// CHECK3-IRBUILDER:       omp.inner.for.cond30:2539// CHECK3-IRBUILDER-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV16]], align 42540// CHECK3-IRBUILDER-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42541// CHECK3-IRBUILDER-NEXT:    [[ADD31:%.*]] = add i32 [[TMP28]], 12542// CHECK3-IRBUILDER-NEXT:    [[CMP32:%.*]] = icmp ult i32 [[TMP27]], [[ADD31]]2543// CHECK3-IRBUILDER-NEXT:    br i1 [[CMP32]], label [[OMP_INNER_FOR_BODY33:%.*]], label [[OMP_INNER_FOR_END42:%.*]]2544// CHECK3-IRBUILDER:       omp.inner.for.body33:2545// CHECK3-IRBUILDER-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 42546// CHECK3-IRBUILDER-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IV16]], align 42547// CHECK3-IRBUILDER-NEXT:    [[MUL34:%.*]] = mul i32 [[TMP30]], 12548// CHECK3-IRBUILDER-NEXT:    [[ADD35:%.*]] = add i32 [[TMP29]], [[MUL34]]2549// CHECK3-IRBUILDER-NEXT:    store i32 [[ADD35]], ptr [[I28]], align 42550// CHECK3-IRBUILDER-NEXT:    [[TMP31:%.*]] = load i32, ptr [[I28]], align 42551// CHECK3-IRBUILDER-NEXT:    [[IDXPROM36:%.*]] = sext i32 [[TMP31]] to i642552// CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX37:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM36]]2553// CHECK3-IRBUILDER-NEXT:    store float 0.000000e+00, ptr [[ARRAYIDX37]], align 42554// CHECK3-IRBUILDER-NEXT:    call void @__captured_stmt.1(ptr [[I28]])2555// CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_BODY33_ORDERED_AFTER:%.*]]2556// CHECK3-IRBUILDER:       omp.inner.for.body33.ordered.after:2557// CHECK3-IRBUILDER-NEXT:    br label [[OMP_REGION_FINALIZE38:%.*]]2558// CHECK3-IRBUILDER:       omp_region.finalize38:2559// CHECK3-IRBUILDER-NEXT:    br label [[OMP_BODY_CONTINUE39:%.*]]2560// CHECK3-IRBUILDER:       omp.body.continue39:2561// CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_INC40:%.*]]2562// CHECK3-IRBUILDER:       omp.inner.for.inc40:2563// CHECK3-IRBUILDER-NEXT:    [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV16]], align 42564// CHECK3-IRBUILDER-NEXT:    [[ADD40:%.*]] = add i32 [[TMP32]], 12565// CHECK3-IRBUILDER-NEXT:    store i32 [[ADD40]], ptr [[DOTOMP_IV16]], align 42566// CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM41:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB12]])2567// CHECK3-IRBUILDER-NEXT:    call void @__kmpc_dispatch_fini_4u(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM41]])2568// CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND30]], !llvm.loop [[LOOP5:![0-9]+]]2569// CHECK3-IRBUILDER:       omp.inner.for.end43:2570// CHECK3-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]2571// CHECK3-IRBUILDER:       omp.dispatch.inc:2572// CHECK3-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND]]2573// CHECK3-IRBUILDER:       omp.dispatch.end:2574// CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM43:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB12]])2575// CHECK3-IRBUILDER-NEXT:    call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM43]])2576// CHECK3-IRBUILDER-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 42577// CHECK3-IRBUILDER-NEXT:    [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 02578// CHECK3-IRBUILDER-NEXT:    br i1 [[TMP34]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]2579// CHECK3-IRBUILDER:       .omp.final.then:2580// CHECK3-IRBUILDER-NEXT:    [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 42581// CHECK3-IRBUILDER-NEXT:    [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 42582// CHECK3-IRBUILDER-NEXT:    [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 42583// CHECK3-IRBUILDER-NEXT:    [[SUB44:%.*]] = sub i32 [[TMP36]], [[TMP37]]2584// CHECK3-IRBUILDER-NEXT:    [[SUB45:%.*]] = sub i32 [[SUB44]], 12585// CHECK3-IRBUILDER-NEXT:    [[ADD46:%.*]] = add i32 [[SUB45]], 12586// CHECK3-IRBUILDER-NEXT:    [[DIV47:%.*]] = udiv i32 [[ADD46]], 12587// CHECK3-IRBUILDER-NEXT:    [[MUL48:%.*]] = mul i32 [[DIV47]], 12588// CHECK3-IRBUILDER-NEXT:    [[ADD49:%.*]] = add i32 [[TMP35]], [[MUL48]]2589// CHECK3-IRBUILDER-NEXT:    store i32 [[ADD49]], ptr [[I28]], align 42590// CHECK3-IRBUILDER-NEXT:    br label [[DOTOMP_FINAL_DONE]]2591// CHECK3-IRBUILDER:       .omp.final.done:2592// CHECK3-IRBUILDER-NEXT:    br label [[OMP_PRECOND_END]]2593// CHECK3-IRBUILDER:       omp.precond.end:2594// CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM50:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])2595// CHECK3-IRBUILDER-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM50]])2596// CHECK3-IRBUILDER-NEXT:    ret void2597//2598//2599// CHECK3-IRBUILDER-LABEL: define {{[^@]+}}@__captured_stmt2600// CHECK3-IRBUILDER-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR4:[0-9]+]] {2601// CHECK3-IRBUILDER-NEXT:  entry:2602// CHECK3-IRBUILDER-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 82603// CHECK3-IRBUILDER-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 82604// CHECK3-IRBUILDER-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 82605// CHECK3-IRBUILDER-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 42606// CHECK3-IRBUILDER-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i642607// CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]]2608// CHECK3-IRBUILDER-NEXT:    store float 1.000000e+00, ptr [[ARRAYIDX]], align 42609// CHECK3-IRBUILDER-NEXT:    ret void2610//2611//2612// CHECK3-IRBUILDER-LABEL: define {{[^@]+}}@__captured_stmt.12613// CHECK3-IRBUILDER-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR4]] {2614// CHECK3-IRBUILDER-NEXT:  entry:2615// CHECK3-IRBUILDER-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 82616// CHECK3-IRBUILDER-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 82617// CHECK3-IRBUILDER-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 82618// CHECK3-IRBUILDER-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 42619// CHECK3-IRBUILDER-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i642620// CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]]2621// CHECK3-IRBUILDER-NEXT:    store float 1.000000e+00, ptr [[ARRAYIDX]], align 42622// CHECK3-IRBUILDER-NEXT:    ret void2623//2624//2625// CHECK5-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_2626// CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] {2627// CHECK5-NEXT:  entry:2628// CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 82629// CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 82630// CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 82631// CHECK5-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 82632// CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 42633// CHECK5-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 82634// CHECK5-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 82635// CHECK5-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 82636// CHECK5-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 82637// CHECK5-NEXT:    store i32 32000000, ptr [[I]], align 42638// CHECK5-NEXT:    br label [[FOR_COND:%.*]]2639// CHECK5:       for.cond:2640// CHECK5-NEXT:    [[TMP0:%.*]] = load i32, ptr [[I]], align 42641// CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 332642// CHECK5-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]2643// CHECK5:       for.body:2644// CHECK5-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 82645// CHECK5-NEXT:    [[TMP2:%.*]] = load i32, ptr [[I]], align 42646// CHECK5-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i642647// CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP1]], i64 [[IDXPROM]]2648// CHECK5-NEXT:    [[TMP3:%.*]] = load float, ptr [[ARRAYIDX]], align 42649// CHECK5-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[C_ADDR]], align 82650// CHECK5-NEXT:    [[TMP5:%.*]] = load i32, ptr [[I]], align 42651// CHECK5-NEXT:    [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i642652// CHECK5-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP4]], i64 [[IDXPROM1]]2653// CHECK5-NEXT:    [[TMP6:%.*]] = load float, ptr [[ARRAYIDX2]], align 42654// CHECK5-NEXT:    [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]]2655// CHECK5-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 82656// CHECK5-NEXT:    [[TMP8:%.*]] = load i32, ptr [[I]], align 42657// CHECK5-NEXT:    [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i642658// CHECK5-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP7]], i64 [[IDXPROM3]]2659// CHECK5-NEXT:    [[TMP9:%.*]] = load float, ptr [[ARRAYIDX4]], align 42660// CHECK5-NEXT:    [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]]2661// CHECK5-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[A_ADDR]], align 82662// CHECK5-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 42663// CHECK5-NEXT:    [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i642664// CHECK5-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP10]], i64 [[IDXPROM6]]2665// CHECK5-NEXT:    store float [[MUL5]], ptr [[ARRAYIDX7]], align 42666// CHECK5-NEXT:    br label [[FOR_INC:%.*]]2667// CHECK5:       for.inc:2668// CHECK5-NEXT:    [[TMP12:%.*]] = load i32, ptr [[I]], align 42669// CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP12]], -72670// CHECK5-NEXT:    store i32 [[ADD]], ptr [[I]], align 42671// CHECK5-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]2672// CHECK5:       for.end:2673// CHECK5-NEXT:    ret void2674//2675//2676// CHECK5-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_2677// CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {2678// CHECK5-NEXT:  entry:2679// CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 82680// CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 82681// CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 82682// CHECK5-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 82683// CHECK5-NEXT:    [[I:%.*]] = alloca i64, align 82684// CHECK5-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 82685// CHECK5-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 82686// CHECK5-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 82687// CHECK5-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 82688// CHECK5-NEXT:    store i64 131071, ptr [[I]], align 82689// CHECK5-NEXT:    br label [[FOR_COND:%.*]]2690// CHECK5:       for.cond:2691// CHECK5-NEXT:    [[TMP0:%.*]] = load i64, ptr [[I]], align 82692// CHECK5-NEXT:    [[CMP:%.*]] = icmp ult i64 [[TMP0]], 21474836472693// CHECK5-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]2694// CHECK5:       for.body:2695// CHECK5-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 82696// CHECK5-NEXT:    [[TMP2:%.*]] = load i64, ptr [[I]], align 82697// CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP1]], i64 [[TMP2]]2698// CHECK5-NEXT:    [[TMP3:%.*]] = load float, ptr [[ARRAYIDX]], align 42699// CHECK5-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[C_ADDR]], align 82700// CHECK5-NEXT:    [[TMP5:%.*]] = load i64, ptr [[I]], align 82701// CHECK5-NEXT:    [[ARRAYIDX1:%.*]] = getelementptr inbounds nuw float, ptr [[TMP4]], i64 [[TMP5]]2702// CHECK5-NEXT:    [[TMP6:%.*]] = load float, ptr [[ARRAYIDX1]], align 42703// CHECK5-NEXT:    [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]]2704// CHECK5-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 82705// CHECK5-NEXT:    [[TMP8:%.*]] = load i64, ptr [[I]], align 82706// CHECK5-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw float, ptr [[TMP7]], i64 [[TMP8]]2707// CHECK5-NEXT:    [[TMP9:%.*]] = load float, ptr [[ARRAYIDX2]], align 42708// CHECK5-NEXT:    [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]]2709// CHECK5-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[A_ADDR]], align 82710// CHECK5-NEXT:    [[TMP11:%.*]] = load i64, ptr [[I]], align 82711// CHECK5-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw float, ptr [[TMP10]], i64 [[TMP11]]2712// CHECK5-NEXT:    store float [[MUL3]], ptr [[ARRAYIDX4]], align 42713// CHECK5-NEXT:    br label [[FOR_INC:%.*]]2714// CHECK5:       for.inc:2715// CHECK5-NEXT:    [[TMP12:%.*]] = load i64, ptr [[I]], align 82716// CHECK5-NEXT:    [[ADD:%.*]] = add i64 [[TMP12]], 1272717// CHECK5-NEXT:    store i64 [[ADD]], ptr [[I]], align 82718// CHECK5-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]2719// CHECK5:       for.end:2720// CHECK5-NEXT:    ret void2721//2722//2723// CHECK5-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_2724// CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {2725// CHECK5-NEXT:  entry:2726// CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 82727// CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 82728// CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 82729// CHECK5-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 82730// CHECK5-NEXT:    [[X:%.*]] = alloca i32, align 42731// CHECK5-NEXT:    [[Y:%.*]] = alloca i32, align 42732// CHECK5-NEXT:    [[I:%.*]] = alloca i8, align 12733// CHECK5-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 82734// CHECK5-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 82735// CHECK5-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 82736// CHECK5-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 82737// CHECK5-NEXT:    store i32 0, ptr [[X]], align 42738// CHECK5-NEXT:    store i32 0, ptr [[Y]], align 42739// CHECK5-NEXT:    [[TMP0:%.*]] = load i32, ptr [[Y]], align 42740// CHECK5-NEXT:    [[CONV:%.*]] = trunc i32 [[TMP0]] to i82741// CHECK5-NEXT:    store i8 [[CONV]], ptr [[I]], align 12742// CHECK5-NEXT:    br label [[FOR_COND:%.*]]2743// CHECK5:       for.cond:2744// CHECK5-NEXT:    [[TMP1:%.*]] = load i8, ptr [[I]], align 12745// CHECK5-NEXT:    [[CONV1:%.*]] = sext i8 [[TMP1]] to i322746// CHECK5-NEXT:    [[CMP:%.*]] = icmp sle i32 [[CONV1]], 572747// CHECK5-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END13:%.*]]2748// CHECK5:       for.body:2749// CHECK5-NEXT:    store i32 11, ptr [[X]], align 42750// CHECK5-NEXT:    br label [[FOR_COND2:%.*]]2751// CHECK5:       for.cond2:2752// CHECK5-NEXT:    [[TMP2:%.*]] = load i32, ptr [[X]], align 42753// CHECK5-NEXT:    [[CMP3:%.*]] = icmp ugt i32 [[TMP2]], 02754// CHECK5-NEXT:    br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]]2755// CHECK5:       for.body4:2756// CHECK5-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 82757// CHECK5-NEXT:    [[TMP4:%.*]] = load i8, ptr [[I]], align 12758// CHECK5-NEXT:    [[IDXPROM:%.*]] = sext i8 [[TMP4]] to i642759// CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP3]], i64 [[IDXPROM]]2760// CHECK5-NEXT:    [[TMP5:%.*]] = load float, ptr [[ARRAYIDX]], align 42761// CHECK5-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[C_ADDR]], align 82762// CHECK5-NEXT:    [[TMP7:%.*]] = load i8, ptr [[I]], align 12763// CHECK5-NEXT:    [[IDXPROM5:%.*]] = sext i8 [[TMP7]] to i642764// CHECK5-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP6]], i64 [[IDXPROM5]]2765// CHECK5-NEXT:    [[TMP8:%.*]] = load float, ptr [[ARRAYIDX6]], align 42766// CHECK5-NEXT:    [[MUL:%.*]] = fmul float [[TMP5]], [[TMP8]]2767// CHECK5-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[D_ADDR]], align 82768// CHECK5-NEXT:    [[TMP10:%.*]] = load i8, ptr [[I]], align 12769// CHECK5-NEXT:    [[IDXPROM7:%.*]] = sext i8 [[TMP10]] to i642770// CHECK5-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds float, ptr [[TMP9]], i64 [[IDXPROM7]]2771// CHECK5-NEXT:    [[TMP11:%.*]] = load float, ptr [[ARRAYIDX8]], align 42772// CHECK5-NEXT:    [[MUL9:%.*]] = fmul float [[MUL]], [[TMP11]]2773// CHECK5-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[A_ADDR]], align 82774// CHECK5-NEXT:    [[TMP13:%.*]] = load i8, ptr [[I]], align 12775// CHECK5-NEXT:    [[IDXPROM10:%.*]] = sext i8 [[TMP13]] to i642776// CHECK5-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[IDXPROM10]]2777// CHECK5-NEXT:    store float [[MUL9]], ptr [[ARRAYIDX11]], align 42778// CHECK5-NEXT:    br label [[FOR_INC:%.*]]2779// CHECK5:       for.inc:2780// CHECK5-NEXT:    [[TMP14:%.*]] = load i32, ptr [[X]], align 42781// CHECK5-NEXT:    [[DEC:%.*]] = add i32 [[TMP14]], -12782// CHECK5-NEXT:    store i32 [[DEC]], ptr [[X]], align 42783// CHECK5-NEXT:    br label [[FOR_COND2]], !llvm.loop [[LOOP5:![0-9]+]]2784// CHECK5:       for.end:2785// CHECK5-NEXT:    br label [[FOR_INC12:%.*]]2786// CHECK5:       for.inc12:2787// CHECK5-NEXT:    [[TMP15:%.*]] = load i8, ptr [[I]], align 12788// CHECK5-NEXT:    [[INC:%.*]] = add i8 [[TMP15]], 12789// CHECK5-NEXT:    store i8 [[INC]], ptr [[I]], align 12790// CHECK5-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]2791// CHECK5:       for.end13:2792// CHECK5-NEXT:    ret void2793//2794//2795// CHECK5-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_2796// CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {2797// CHECK5-NEXT:  entry:2798// CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 82799// CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 82800// CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 82801// CHECK5-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 82802// CHECK5-NEXT:    [[X:%.*]] = alloca i32, align 42803// CHECK5-NEXT:    [[I:%.*]] = alloca i8, align 12804// CHECK5-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 82805// CHECK5-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 82806// CHECK5-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 82807// CHECK5-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 82808// CHECK5-NEXT:    store i32 0, ptr [[X]], align 42809// CHECK5-NEXT:    store i8 48, ptr [[I]], align 12810// CHECK5-NEXT:    br label [[FOR_COND:%.*]]2811// CHECK5:       for.cond:2812// CHECK5-NEXT:    [[TMP0:%.*]] = load i8, ptr [[I]], align 12813// CHECK5-NEXT:    [[CONV:%.*]] = zext i8 [[TMP0]] to i322814// CHECK5-NEXT:    [[CMP:%.*]] = icmp sle i32 [[CONV]], 572815// CHECK5-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END13:%.*]]2816// CHECK5:       for.body:2817// CHECK5-NEXT:    store i32 -10, ptr [[X]], align 42818// CHECK5-NEXT:    br label [[FOR_COND1:%.*]]2819// CHECK5:       for.cond1:2820// CHECK5-NEXT:    [[TMP1:%.*]] = load i32, ptr [[X]], align 42821// CHECK5-NEXT:    [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 102822// CHECK5-NEXT:    br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]]2823// CHECK5:       for.body3:2824// CHECK5-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 82825// CHECK5-NEXT:    [[TMP3:%.*]] = load i8, ptr [[I]], align 12826// CHECK5-NEXT:    [[IDXPROM:%.*]] = zext i8 [[TMP3]] to i642827// CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP2]], i64 [[IDXPROM]]2828// CHECK5-NEXT:    [[TMP4:%.*]] = load float, ptr [[ARRAYIDX]], align 42829// CHECK5-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[C_ADDR]], align 82830// CHECK5-NEXT:    [[TMP6:%.*]] = load i8, ptr [[I]], align 12831// CHECK5-NEXT:    [[IDXPROM4:%.*]] = zext i8 [[TMP6]] to i642832// CHECK5-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds nuw float, ptr [[TMP5]], i64 [[IDXPROM4]]2833// CHECK5-NEXT:    [[TMP7:%.*]] = load float, ptr [[ARRAYIDX5]], align 42834// CHECK5-NEXT:    [[MUL:%.*]] = fmul float [[TMP4]], [[TMP7]]2835// CHECK5-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[D_ADDR]], align 82836// CHECK5-NEXT:    [[TMP9:%.*]] = load i8, ptr [[I]], align 12837// CHECK5-NEXT:    [[IDXPROM6:%.*]] = zext i8 [[TMP9]] to i642838// CHECK5-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds nuw float, ptr [[TMP8]], i64 [[IDXPROM6]]2839// CHECK5-NEXT:    [[TMP10:%.*]] = load float, ptr [[ARRAYIDX7]], align 42840// CHECK5-NEXT:    [[MUL8:%.*]] = fmul float [[MUL]], [[TMP10]]2841// CHECK5-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[A_ADDR]], align 82842// CHECK5-NEXT:    [[TMP12:%.*]] = load i8, ptr [[I]], align 12843// CHECK5-NEXT:    [[IDXPROM9:%.*]] = zext i8 [[TMP12]] to i642844// CHECK5-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds nuw float, ptr [[TMP11]], i64 [[IDXPROM9]]2845// CHECK5-NEXT:    store float [[MUL8]], ptr [[ARRAYIDX10]], align 42846// CHECK5-NEXT:    br label [[FOR_INC:%.*]]2847// CHECK5:       for.inc:2848// CHECK5-NEXT:    [[TMP13:%.*]] = load i32, ptr [[X]], align 42849// CHECK5-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP13]], 12850// CHECK5-NEXT:    store i32 [[INC]], ptr [[X]], align 42851// CHECK5-NEXT:    br label [[FOR_COND1]], !llvm.loop [[LOOP7:![0-9]+]]2852// CHECK5:       for.end:2853// CHECK5-NEXT:    br label [[FOR_INC11:%.*]]2854// CHECK5:       for.inc11:2855// CHECK5-NEXT:    [[TMP14:%.*]] = load i8, ptr [[I]], align 12856// CHECK5-NEXT:    [[INC12:%.*]] = add i8 [[TMP14]], 12857// CHECK5-NEXT:    store i8 [[INC12]], ptr [[I]], align 12858// CHECK5-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]2859// CHECK5:       for.end13:2860// CHECK5-NEXT:    ret void2861//2862//2863// CHECK5-LABEL: define {{[^@]+}}@_Z8foo_simdii2864// CHECK5-SAME: (i32 noundef [[LOW:%.*]], i32 noundef [[UP:%.*]]) #[[ATTR0]] {2865// CHECK5-NEXT:  entry:2866// CHECK5-NEXT:    [[LOW_ADDR:%.*]] = alloca i32, align 42867// CHECK5-NEXT:    [[UP_ADDR:%.*]] = alloca i32, align 42868// CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 42869// CHECK5-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 42870// CHECK5-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 42871// CHECK5-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 42872// CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 42873// CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 42874// CHECK5-NEXT:    [[I5:%.*]] = alloca i32, align 42875// CHECK5-NEXT:    [[_TMP18:%.*]] = alloca i32, align 42876// CHECK5-NEXT:    [[DOTCAPTURE_EXPR_19:%.*]] = alloca i32, align 42877// CHECK5-NEXT:    [[DOTCAPTURE_EXPR_20:%.*]] = alloca i32, align 42878// CHECK5-NEXT:    [[DOTCAPTURE_EXPR_21:%.*]] = alloca i32, align 42879// CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 42880// CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 42881// CHECK5-NEXT:    [[I27:%.*]] = alloca i32, align 42882// CHECK5-NEXT:    [[DOTOMP_IV30:%.*]] = alloca i32, align 42883// CHECK5-NEXT:    [[I31:%.*]] = alloca i32, align 42884// CHECK5-NEXT:    store i32 [[LOW]], ptr [[LOW_ADDR]], align 42885// CHECK5-NEXT:    store i32 [[UP]], ptr [[UP_ADDR]], align 42886// CHECK5-NEXT:    [[TMP0:%.*]] = load i32, ptr [[LOW_ADDR]], align 42887// CHECK5-NEXT:    store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 42888// CHECK5-NEXT:    [[TMP1:%.*]] = load i32, ptr [[UP_ADDR]], align 42889// CHECK5-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_1]], align 42890// CHECK5-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 42891// CHECK5-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 42892// CHECK5-NEXT:    [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]]2893// CHECK5-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 12894// CHECK5-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 12895// CHECK5-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 12896// CHECK5-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 12897// CHECK5-NEXT:    store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 42898// CHECK5-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 42899// CHECK5-NEXT:    store i32 [[TMP4]], ptr [[I]], align 42900// CHECK5-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 42901// CHECK5-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 42902// CHECK5-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP5]], [[TMP6]]2903// CHECK5-NEXT:    br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]2904// CHECK5:       simd.if.then:2905// CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_IV]], align 42906// CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]2907// CHECK5:       omp.inner.for.cond:2908// CHECK5-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42909// CHECK5-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 42910// CHECK5-NEXT:    [[ADD6:%.*]] = add i32 [[TMP8]], 12911// CHECK5-NEXT:    [[CMP7:%.*]] = icmp ult i32 [[TMP7]], [[ADD6]]2912// CHECK5-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2913// CHECK5:       omp.inner.for.body:2914// CHECK5-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 42915// CHECK5-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42916// CHECK5-NEXT:    [[MUL:%.*]] = mul i32 [[TMP10]], 12917// CHECK5-NEXT:    [[ADD8:%.*]] = add i32 [[TMP9]], [[MUL]]2918// CHECK5-NEXT:    store i32 [[ADD8]], ptr [[I5]], align 42919// CHECK5-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I5]], align 42920// CHECK5-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i642921// CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]]2922// CHECK5-NEXT:    store float 0.000000e+00, ptr [[ARRAYIDX]], align 42923// CHECK5-NEXT:    [[TMP12:%.*]] = load i32, ptr [[I5]], align 42924// CHECK5-NEXT:    [[IDXPROM9:%.*]] = sext i32 [[TMP12]] to i642925// CHECK5-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM9]]2926// CHECK5-NEXT:    store float 1.000000e+00, ptr [[ARRAYIDX10]], align 42927// CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]2928// CHECK5:       omp.body.continue:2929// CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]2930// CHECK5:       omp.inner.for.inc:2931// CHECK5-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42932// CHECK5-NEXT:    [[ADD11:%.*]] = add i32 [[TMP13]], 12933// CHECK5-NEXT:    store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 42934// CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]2935// CHECK5:       omp.inner.for.end:2936// CHECK5-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 42937// CHECK5-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 42938// CHECK5-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 42939// CHECK5-NEXT:    [[SUB12:%.*]] = sub i32 [[TMP15]], [[TMP16]]2940// CHECK5-NEXT:    [[SUB13:%.*]] = sub i32 [[SUB12]], 12941// CHECK5-NEXT:    [[ADD14:%.*]] = add i32 [[SUB13]], 12942// CHECK5-NEXT:    [[DIV15:%.*]] = udiv i32 [[ADD14]], 12943// CHECK5-NEXT:    [[MUL16:%.*]] = mul i32 [[DIV15]], 12944// CHECK5-NEXT:    [[ADD17:%.*]] = add i32 [[TMP14]], [[MUL16]]2945// CHECK5-NEXT:    store i32 [[ADD17]], ptr [[I5]], align 42946// CHECK5-NEXT:    br label [[SIMD_IF_END]]2947// CHECK5:       simd.if.end:2948// CHECK5-NEXT:    [[TMP17:%.*]] = load i32, ptr [[LOW_ADDR]], align 42949// CHECK5-NEXT:    store i32 [[TMP17]], ptr [[DOTCAPTURE_EXPR_19]], align 42950// CHECK5-NEXT:    [[TMP18:%.*]] = load i32, ptr [[UP_ADDR]], align 42951// CHECK5-NEXT:    store i32 [[TMP18]], ptr [[DOTCAPTURE_EXPR_20]], align 42952// CHECK5-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_20]], align 42953// CHECK5-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 42954// CHECK5-NEXT:    [[SUB22:%.*]] = sub i32 [[TMP19]], [[TMP20]]2955// CHECK5-NEXT:    [[SUB23:%.*]] = sub i32 [[SUB22]], 12956// CHECK5-NEXT:    [[ADD24:%.*]] = add i32 [[SUB23]], 12957// CHECK5-NEXT:    [[DIV25:%.*]] = udiv i32 [[ADD24]], 12958// CHECK5-NEXT:    [[SUB26:%.*]] = sub i32 [[DIV25]], 12959// CHECK5-NEXT:    store i32 [[SUB26]], ptr [[DOTCAPTURE_EXPR_21]], align 42960// CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 42961// CHECK5-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_21]], align 42962// CHECK5-NEXT:    store i32 [[TMP21]], ptr [[DOTOMP_UB]], align 42963// CHECK5-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 42964// CHECK5-NEXT:    store i32 [[TMP22]], ptr [[I27]], align 42965// CHECK5-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 42966// CHECK5-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_20]], align 42967// CHECK5-NEXT:    [[CMP28:%.*]] = icmp slt i32 [[TMP23]], [[TMP24]]2968// CHECK5-NEXT:    br i1 [[CMP28]], label [[SIMD_IF_THEN29:%.*]], label [[SIMD_IF_END52:%.*]]2969// CHECK5:       simd.if.then29:2970// CHECK5-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42971// CHECK5-NEXT:    store i32 [[TMP25]], ptr [[DOTOMP_IV30]], align 42972// CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND32:%.*]]2973// CHECK5:       omp.inner.for.cond32:2974// CHECK5-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_IV30]], align 42975// CHECK5-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42976// CHECK5-NEXT:    [[ADD33:%.*]] = add i32 [[TMP27]], 12977// CHECK5-NEXT:    [[CMP34:%.*]] = icmp ult i32 [[TMP26]], [[ADD33]]2978// CHECK5-NEXT:    br i1 [[CMP34]], label [[OMP_INNER_FOR_BODY35:%.*]], label [[OMP_INNER_FOR_END45:%.*]]2979// CHECK5:       omp.inner.for.body35:2980// CHECK5-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 42981// CHECK5-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV30]], align 42982// CHECK5-NEXT:    [[MUL36:%.*]] = mul i32 [[TMP29]], 12983// CHECK5-NEXT:    [[ADD37:%.*]] = add i32 [[TMP28]], [[MUL36]]2984// CHECK5-NEXT:    store i32 [[ADD37]], ptr [[I31]], align 42985// CHECK5-NEXT:    [[TMP30:%.*]] = load i32, ptr [[I31]], align 42986// CHECK5-NEXT:    [[IDXPROM38:%.*]] = sext i32 [[TMP30]] to i642987// CHECK5-NEXT:    [[ARRAYIDX39:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM38]]2988// CHECK5-NEXT:    store float 0.000000e+00, ptr [[ARRAYIDX39]], align 42989// CHECK5-NEXT:    [[TMP31:%.*]] = load i32, ptr [[I31]], align 42990// CHECK5-NEXT:    [[IDXPROM40:%.*]] = sext i32 [[TMP31]] to i642991// CHECK5-NEXT:    [[ARRAYIDX41:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM40]]2992// CHECK5-NEXT:    store float 1.000000e+00, ptr [[ARRAYIDX41]], align 42993// CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE42:%.*]]2994// CHECK5:       omp.body.continue42:2995// CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC43:%.*]]2996// CHECK5:       omp.inner.for.inc43:2997// CHECK5-NEXT:    [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV30]], align 42998// CHECK5-NEXT:    [[ADD44:%.*]] = add i32 [[TMP32]], 12999// CHECK5-NEXT:    store i32 [[ADD44]], ptr [[DOTOMP_IV30]], align 43000// CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND32]], !llvm.loop [[LOOP11:![0-9]+]]3001// CHECK5:       omp.inner.for.end45:3002// CHECK5-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 43003// CHECK5-NEXT:    [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_20]], align 43004// CHECK5-NEXT:    [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 43005// CHECK5-NEXT:    [[SUB46:%.*]] = sub i32 [[TMP34]], [[TMP35]]3006// CHECK5-NEXT:    [[SUB47:%.*]] = sub i32 [[SUB46]], 13007// CHECK5-NEXT:    [[ADD48:%.*]] = add i32 [[SUB47]], 13008// CHECK5-NEXT:    [[DIV49:%.*]] = udiv i32 [[ADD48]], 13009// CHECK5-NEXT:    [[MUL50:%.*]] = mul i32 [[DIV49]], 13010// CHECK5-NEXT:    [[ADD51:%.*]] = add i32 [[TMP33]], [[MUL50]]3011// CHECK5-NEXT:    store i32 [[ADD51]], ptr [[I31]], align 43012// CHECK5-NEXT:    br label [[SIMD_IF_END52]]3013// CHECK5:       simd.if.end52:3014// CHECK5-NEXT:    ret void3015//3016