995 lines · cpp
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _2// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -emit-llvm %s -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK13// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s4// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK25// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-enable-irbuilder -DIRBUILDER -x c++ -emit-llvm %s -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK36// RUN: %clang_cc1 -fopenmp -fopenmp-enable-irbuilder -DIRBUILDER -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s7// RUN: %clang_cc1 -fopenmp -fopenmp-enable-irbuilder -DIRBUILDER -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -gno-column-info -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK48 9// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -emit-llvm %s -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"10// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s11// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"12// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-enable-irbuilder -x c++ -emit-llvm %s -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"13// RUN: %clang_cc1 -fopenmp-simd -fopenmp-enable-irbuilder -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s14// RUN: %clang_cc1 -fopenmp-simd -fopenmp-enable-irbuilder -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"15// expected-no-diagnostics16#ifndef HEADER17#define HEADER18 19 20template <class T>21void foo(T argc) {}22 23template <typename T>24int tmain(T argc) {25 typedef double (*chunk_t)[argc[0][0]];26#pragma omp parallel27 {28 foo(argc);29 chunk_t var;(void)var[0][0];30 }31 return 0;32}33 34int global;35int main (int argc, char **argv) {36 int a[argc];37#pragma omp parallel shared(global, a) default(none)38 foo(a[1]), a[1] = global;39#ifndef IRBUILDER40// TODO: Support for privates in IRBuilder.41#pragma omp parallel private(global, a) default(none)42#pragma omp parallel shared(global, a) default(none)43 foo(a[1]), a[1] = global;44// FIXME: IRBuilder crashes in void llvm::OpenMPIRBuilder::finalize()45// Assertion `Extractor.isEligible() && "Expected OpenMP outlining to be possible!"' failed.46#pragma omp parallel shared(global, a) default(none)47#pragma omp parallel shared(global, a) default(none)48 foo(a[1]), a[1] = global;49#endif // IRBUILDER50 return tmain(argv);51}52 53 54 55 56 57 58 59 60 61 62 63 64// Note that OpenMPIRBuilder puts the trailing arguments in a different order:65// arguments that are wrapped into additional pointers precede the other66// arguments. This is expected and not problematic because both the call and the67// function are generated from the same place, and the function is internal.68 69 70 71 72#endif73// CHECK1-LABEL: define {{[^@]+}}@main74// CHECK1-SAME: (i32 noundef [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {75// CHECK1-NEXT: entry:76// CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 477// CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 478// CHECK1-NEXT: [[ARGV_ADDR:%.*]] = alloca ptr, align 879// CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 880// CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 881// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 482// CHECK1-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 483// CHECK1-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 884// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARGC_ADDR]], align 485// CHECK1-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i6486// CHECK1-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()87// CHECK1-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 888// CHECK1-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 1689// CHECK1-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 890// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 2, ptr @main.omp_outlined, i64 [[TMP1]], ptr [[VLA]])91// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @main.omp_outlined.1, i64 [[TMP1]])92// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @main.omp_outlined.2, i64 [[TMP1]], ptr [[VLA]])93// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[ARGV_ADDR]], align 894// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIPPcEiT_(ptr noundef [[TMP3]])95// CHECK1-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 496// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SAVED_STACK]], align 897// CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP4]])98// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[RETVAL]], align 499// CHECK1-NEXT: ret i32 [[TMP5]]100//101//102// CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined103// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] personality ptr @__gxx_personality_v0 {104// CHECK1-NEXT: entry:105// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8106// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8107// CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8108// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8109// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8110// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8111// CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8112// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8113// CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8114// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8115// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 1116// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4117// CHECK1-NEXT: invoke void @_Z3fooIiEvT_(i32 noundef [[TMP2]])118// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]]119// CHECK1: invoke.cont:120// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr @global, align 4121// CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 1122// CHECK1-NEXT: store i32 [[TMP3]], ptr [[ARRAYIDX1]], align 4123// CHECK1-NEXT: ret void124// CHECK1: terminate.lpad:125// CHECK1-NEXT: [[TMP4:%.*]] = landingpad { ptr, i32 }126// CHECK1-NEXT: catch ptr null127// CHECK1-NEXT: [[TMP5:%.*]] = extractvalue { ptr, i32 } [[TMP4]], 0128// CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP5]]) #[[ATTR6:[0-9]+]]129// CHECK1-NEXT: unreachable130//131//132// CHECK1-LABEL: define {{[^@]+}}@_Z3fooIiEvT_133// CHECK1-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR3:[0-9]+]] comdat {134// CHECK1-NEXT: entry:135// CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4136// CHECK1-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4137// CHECK1-NEXT: ret void138//139//140// CHECK1-LABEL: define {{[^@]+}}@__clang_call_terminate141// CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] comdat {142// CHECK1-NEXT: [[TMP2:%.*]] = call ptr @__cxa_begin_catch(ptr [[TMP0]]) #[[ATTR5:[0-9]+]]143// CHECK1-NEXT: call void @_ZSt9terminatev() #[[ATTR6]]144// CHECK1-NEXT: unreachable145//146//147// CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.1148// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR2]] {149// CHECK1-NEXT: entry:150// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8151// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8152// CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8153// CHECK1-NEXT: [[GLOBAL:%.*]] = alloca i32, align 4154// CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8155// CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8156// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8157// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8158// CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8159// CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8160// CHECK1-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()161// CHECK1-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 8162// CHECK1-NEXT: [[VLA1:%.*]] = alloca i32, i64 [[TMP0]], align 16163// CHECK1-NEXT: store i64 [[TMP0]], ptr [[__VLA_EXPR0]], align 8164// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 3, ptr @main.omp_outlined.1.omp_outlined, i64 [[TMP0]], ptr [[VLA1]], ptr [[GLOBAL]])165// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8166// CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP2]])167// CHECK1-NEXT: ret void168//169//170// CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.1.omp_outlined171// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[GLOBAL:%.*]]) #[[ATTR2]] personality ptr @__gxx_personality_v0 {172// CHECK1-NEXT: entry:173// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8174// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8175// CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8176// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8177// CHECK1-NEXT: [[GLOBAL_ADDR:%.*]] = alloca ptr, align 8178// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8179// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8180// CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8181// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8182// CHECK1-NEXT: store ptr [[GLOBAL]], ptr [[GLOBAL_ADDR]], align 8183// CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8184// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8185// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[GLOBAL_ADDR]], align 8186// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 1187// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4188// CHECK1-NEXT: invoke void @_Z3fooIiEvT_(i32 noundef [[TMP3]])189// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]]190// CHECK1: invoke.cont:191// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP2]], align 4192// CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 1193// CHECK1-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX1]], align 4194// CHECK1-NEXT: ret void195// CHECK1: terminate.lpad:196// CHECK1-NEXT: [[TMP5:%.*]] = landingpad { ptr, i32 }197// CHECK1-NEXT: catch ptr null198// CHECK1-NEXT: [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0199// CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP6]]) #[[ATTR6]]200// CHECK1-NEXT: unreachable201//202//203// CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.2204// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] {205// CHECK1-NEXT: entry:206// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8207// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8208// CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8209// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8210// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8211// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8212// CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8213// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8214// CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8215// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8216// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @main.omp_outlined.2.omp_outlined, i64 [[TMP0]], ptr [[TMP1]])217// CHECK1-NEXT: ret void218//219//220// CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.2.omp_outlined221// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] personality ptr @__gxx_personality_v0 {222// CHECK1-NEXT: entry:223// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8224// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8225// CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8226// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8227// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8228// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8229// CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8230// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8231// CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8232// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8233// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 1234// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4235// CHECK1-NEXT: invoke void @_Z3fooIiEvT_(i32 noundef [[TMP2]])236// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]]237// CHECK1: invoke.cont:238// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr @global, align 4239// CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 1240// CHECK1-NEXT: store i32 [[TMP3]], ptr [[ARRAYIDX1]], align 4241// CHECK1-NEXT: ret void242// CHECK1: terminate.lpad:243// CHECK1-NEXT: [[TMP4:%.*]] = landingpad { ptr, i32 }244// CHECK1-NEXT: catch ptr null245// CHECK1-NEXT: [[TMP5:%.*]] = extractvalue { ptr, i32 } [[TMP4]], 0246// CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP5]]) #[[ATTR6]]247// CHECK1-NEXT: unreachable248//249//250// CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_251// CHECK1-SAME: (ptr noundef [[ARGC:%.*]]) #[[ATTR3]] comdat {252// CHECK1-NEXT: entry:253// CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 8254// CHECK1-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8255// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8256// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i64 0257// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8258// CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i64 0259// CHECK1-NEXT: [[TMP2:%.*]] = load i8, ptr [[ARRAYIDX1]], align 1260// CHECK1-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i64261// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @_Z5tmainIPPcEiT_.omp_outlined, ptr [[ARGC_ADDR]], i64 [[TMP3]])262// CHECK1-NEXT: ret i32 0263//264//265// CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_.omp_outlined266// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[ARGC:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR2]] personality ptr @__gxx_personality_v0 {267// CHECK1-NEXT: entry:268// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8269// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8270// CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 8271// CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8272// CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8273// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8274// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8275// CHECK1-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8276// CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8277// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8278// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8279// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP0]], align 8280// CHECK1-NEXT: invoke void @_Z3fooIPPcEvT_(ptr noundef [[TMP2]])281// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]]282// CHECK1: invoke.cont:283// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR]], align 8284// CHECK1-NEXT: [[TMP4:%.*]] = mul nsw i64 0, [[TMP1]]285// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP3]], i64 [[TMP4]]286// CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX]], i64 0287// CHECK1-NEXT: ret void288// CHECK1: terminate.lpad:289// CHECK1-NEXT: [[TMP5:%.*]] = landingpad { ptr, i32 }290// CHECK1-NEXT: catch ptr null291// CHECK1-NEXT: [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0292// CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP6]]) #[[ATTR6]]293// CHECK1-NEXT: unreachable294//295//296// CHECK1-LABEL: define {{[^@]+}}@_Z3fooIPPcEvT_297// CHECK1-SAME: (ptr noundef [[ARGC:%.*]]) #[[ATTR3]] comdat {298// CHECK1-NEXT: entry:299// CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 8300// CHECK1-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8301// CHECK1-NEXT: ret void302//303//304// CHECK2-LABEL: define {{[^@]+}}@main305// CHECK2-SAME: (i32 noundef [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG11:![0-9]+]] {306// CHECK2-NEXT: entry:307// CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4308// CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4309// CHECK2-NEXT: [[ARGV_ADDR:%.*]] = alloca ptr, align 8310// CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8311// CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8312// CHECK2-NEXT: store i32 0, ptr [[RETVAL]], align 4313// CHECK2-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4314// CHECK2-NEXT: #dbg_declare(ptr [[ARGC_ADDR]], [[META18:![0-9]+]], !DIExpression(), [[META19:![0-9]+]])315// CHECK2-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8316// CHECK2-NEXT: #dbg_declare(ptr [[ARGV_ADDR]], [[META20:![0-9]+]], !DIExpression(), [[META21:![0-9]+]])317// CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4, !dbg [[DBG22:![0-9]+]]318// CHECK2-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64, !dbg [[DBG23:![0-9]+]]319// CHECK2-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0(), !dbg [[DBG23]]320// CHECK2-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8, !dbg [[DBG23]]321// CHECK2-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 16, !dbg [[DBG23]]322// CHECK2-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8, !dbg [[DBG23]]323// CHECK2-NEXT: #dbg_declare(ptr [[__VLA_EXPR0]], [[META24:![0-9]+]], !DIExpression(), [[META26:![0-9]+]])324// CHECK2-NEXT: #dbg_declare(ptr [[VLA]], [[META27:![0-9]+]], !DIExpression(), [[META31:![0-9]+]])325// CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 2, ptr @main.omp_outlined, i64 [[TMP1]], ptr [[VLA]]), !dbg [[DBG32:![0-9]+]]326// CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB5:[0-9]+]], i32 1, ptr @main.omp_outlined.1, i64 [[TMP1]]), !dbg [[DBG33:![0-9]+]]327// CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB9:[0-9]+]], i32 2, ptr @main.omp_outlined.3, i64 [[TMP1]], ptr [[VLA]]), !dbg [[DBG34:![0-9]+]]328// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[ARGV_ADDR]], align 8, !dbg [[DBG35:![0-9]+]]329// CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIPPcEiT_(ptr noundef [[TMP3]]), !dbg [[DBG36:![0-9]+]]330// CHECK2-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4, !dbg [[DBG37:![0-9]+]]331// CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8, !dbg [[DBG38:![0-9]+]]332// CHECK2-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP4]]), !dbg [[DBG38]]333// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[RETVAL]], align 4, !dbg [[DBG38]]334// CHECK2-NEXT: ret i32 [[TMP5]], !dbg [[DBG38]]335//336//337// CHECK2-LABEL: define {{[^@]+}}@main.omp_outlined_debug__338// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] personality ptr @__gxx_personality_v0 !dbg [[DBG39:![0-9]+]] {339// CHECK2-NEXT: entry:340// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8341// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8342// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8343// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8344// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8345// CHECK2-NEXT: #dbg_declare(ptr [[DOTGLOBAL_TID__ADDR]], [[META47:![0-9]+]], !DIExpression(), [[META48:![0-9]+]])346// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8347// CHECK2-NEXT: #dbg_declare(ptr [[DOTBOUND_TID__ADDR]], [[META49:![0-9]+]], !DIExpression(), [[META48]])348// CHECK2-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8349// CHECK2-NEXT: #dbg_declare(ptr [[VLA_ADDR]], [[META50:![0-9]+]], !DIExpression(), [[META48]])350// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8351// CHECK2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META51:![0-9]+]], !DIExpression(), [[META52:![0-9]+]])352// CHECK2-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8, !dbg [[DBG53:![0-9]+]]353// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG53]]354// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 1, !dbg [[DBG54:![0-9]+]]355// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !dbg [[DBG54]]356// CHECK2-NEXT: invoke void @_Z3fooIiEvT_(i32 noundef [[TMP2]])357// CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG53]]358// CHECK2: invoke.cont:359// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr @global, align 4, !dbg [[DBG55:![0-9]+]]360// CHECK2-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 1, !dbg [[DBG56:![0-9]+]]361// CHECK2-NEXT: store i32 [[TMP3]], ptr [[ARRAYIDX1]], align 4, !dbg [[DBG57:![0-9]+]]362// CHECK2-NEXT: ret void, !dbg [[DBG55]]363// CHECK2: terminate.lpad:364// CHECK2-NEXT: [[TMP4:%.*]] = landingpad { ptr, i32 }365// CHECK2-NEXT: catch ptr null, !dbg [[DBG53]]366// CHECK2-NEXT: [[TMP5:%.*]] = extractvalue { ptr, i32 } [[TMP4]], 0, !dbg [[DBG53]]367// CHECK2-NEXT: call void @__clang_call_terminate(ptr [[TMP5]]) #[[ATTR6:[0-9]+]], !dbg [[DBG53]]368// CHECK2-NEXT: unreachable, !dbg [[DBG53]]369//370//371// CHECK2-LABEL: define {{[^@]+}}@main.omp_outlined372// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] !dbg [[DBG58:![0-9]+]] {373// CHECK2-NEXT: entry:374// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8375// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8376// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8377// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8378// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8379// CHECK2-NEXT: #dbg_declare(ptr [[DOTGLOBAL_TID__ADDR]], [[META59:![0-9]+]], !DIExpression(), [[META60:![0-9]+]])380// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8381// CHECK2-NEXT: #dbg_declare(ptr [[DOTBOUND_TID__ADDR]], [[META61:![0-9]+]], !DIExpression(), [[META60]])382// CHECK2-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8383// CHECK2-NEXT: #dbg_declare(ptr [[VLA_ADDR]], [[META62:![0-9]+]], !DIExpression(), [[META60]])384// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8385// CHECK2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META63:![0-9]+]], !DIExpression(), [[META60]])386// CHECK2-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8, !dbg [[DBG64:![0-9]+]]387// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG64]]388// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG64]]389// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG64]]390// CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG64]]391// CHECK2-NEXT: call void @main.omp_outlined_debug__(ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP0]], ptr [[TMP4]]) #[[ATTR5:[0-9]+]], !dbg [[DBG64]]392// CHECK2-NEXT: ret void, !dbg [[DBG64]]393//394//395// CHECK2-LABEL: define {{[^@]+}}@_Z3fooIiEvT_396// CHECK2-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR3:[0-9]+]] comdat !dbg [[DBG65:![0-9]+]] {397// CHECK2-NEXT: entry:398// CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4399// CHECK2-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4400// CHECK2-NEXT: #dbg_declare(ptr [[ARGC_ADDR]], [[META70:![0-9]+]], !DIExpression(), [[META71:![0-9]+]])401// CHECK2-NEXT: ret void, !dbg [[DBG72:![0-9]+]]402//403//404// CHECK2-LABEL: define {{[^@]+}}@__clang_call_terminate405// CHECK2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] comdat {406// CHECK2-NEXT: [[TMP2:%.*]] = call ptr @__cxa_begin_catch(ptr [[TMP0]]) #[[ATTR5]]407// CHECK2-NEXT: call void @_ZSt9terminatev() #[[ATTR6]]408// CHECK2-NEXT: unreachable409//410//411// CHECK2-LABEL: define {{[^@]+}}@main.omp_outlined_debug__.2412// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR2]] !dbg [[DBG75:![0-9]+]] {413// CHECK2-NEXT: entry:414// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8415// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8416// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8417// CHECK2-NEXT: [[GLOBAL:%.*]] = alloca i32, align 4418// CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8419// CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8420// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8421// CHECK2-NEXT: #dbg_declare(ptr [[DOTGLOBAL_TID__ADDR]], [[META78:![0-9]+]], !DIExpression(), [[META79:![0-9]+]])422// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8423// CHECK2-NEXT: #dbg_declare(ptr [[DOTBOUND_TID__ADDR]], [[META80:![0-9]+]], !DIExpression(), [[META79]])424// CHECK2-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8425// CHECK2-NEXT: #dbg_declare(ptr [[VLA_ADDR]], [[META81:![0-9]+]], !DIExpression(), [[META79]])426// CHECK2-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8, !dbg [[DBG82:![0-9]+]]427// CHECK2-NEXT: #dbg_declare(ptr [[GLOBAL]], [[META83:![0-9]+]], !DIExpression(), [[META79]])428// CHECK2-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0(), !dbg [[DBG82]]429// CHECK2-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 8, !dbg [[DBG82]]430// CHECK2-NEXT: [[VLA1:%.*]] = alloca i32, i64 [[TMP0]], align 16, !dbg [[DBG82]]431// CHECK2-NEXT: store i64 [[TMP0]], ptr [[__VLA_EXPR0]], align 8, !dbg [[DBG82]]432// CHECK2-NEXT: #dbg_declare(ptr [[__VLA_EXPR0]], [[META84:![0-9]+]], !DIExpression(), [[META79]])433// CHECK2-NEXT: #dbg_declare(ptr [[VLA1]], [[META85:![0-9]+]], !DIExpression(), [[META79]])434// CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3:[0-9]+]], i32 3, ptr @main.omp_outlined_debug__.2.omp_outlined, i64 [[TMP0]], ptr [[VLA1]], ptr [[GLOBAL]]), !dbg [[DBG82]]435// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8, !dbg [[DBG86:![0-9]+]]436// CHECK2-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP2]]), !dbg [[DBG86]]437// CHECK2-NEXT: ret void, !dbg [[DBG88:![0-9]+]]438//439//440// CHECK2-LABEL: define {{[^@]+}}@main.omp_outlined.1441// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR2]] !dbg [[DBG89:![0-9]+]] {442// CHECK2-NEXT: entry:443// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8444// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8445// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8446// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8447// CHECK2-NEXT: #dbg_declare(ptr [[DOTGLOBAL_TID__ADDR]], [[META90:![0-9]+]], !DIExpression(), [[META91:![0-9]+]])448// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8449// CHECK2-NEXT: #dbg_declare(ptr [[DOTBOUND_TID__ADDR]], [[META92:![0-9]+]], !DIExpression(), [[META91]])450// CHECK2-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8451// CHECK2-NEXT: #dbg_declare(ptr [[VLA_ADDR]], [[META93:![0-9]+]], !DIExpression(), [[META91]])452// CHECK2-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8, !dbg [[DBG94:![0-9]+]]453// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG94]]454// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG94]]455// CHECK2-NEXT: call void @main.omp_outlined_debug__.2(ptr [[TMP1]], ptr [[TMP2]], i64 [[TMP0]]) #[[ATTR5]], !dbg [[DBG94]]456// CHECK2-NEXT: ret void, !dbg [[DBG94]]457//458//459// CHECK2-LABEL: define {{[^@]+}}@main.omp_outlined_debug__.2.omp_outlined_debug__460// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[GLOBAL:%.*]]) #[[ATTR2]] personality ptr @__gxx_personality_v0 !dbg [[DBG95:![0-9]+]] {461// CHECK2-NEXT: entry:462// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8463// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8464// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8465// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8466// CHECK2-NEXT: [[GLOBAL_ADDR:%.*]] = alloca ptr, align 8467// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8468// CHECK2-NEXT: #dbg_declare(ptr [[DOTGLOBAL_TID__ADDR]], [[META98:![0-9]+]], !DIExpression(), [[META99:![0-9]+]])469// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8470// CHECK2-NEXT: #dbg_declare(ptr [[DOTBOUND_TID__ADDR]], [[META100:![0-9]+]], !DIExpression(), [[META99]])471// CHECK2-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8472// CHECK2-NEXT: #dbg_declare(ptr [[VLA_ADDR]], [[META101:![0-9]+]], !DIExpression(), [[META99]])473// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8474// CHECK2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META102:![0-9]+]], !DIExpression(), [[META103:![0-9]+]])475// CHECK2-NEXT: store ptr [[GLOBAL]], ptr [[GLOBAL_ADDR]], align 8476// CHECK2-NEXT: #dbg_declare(ptr [[GLOBAL_ADDR]], [[META104:![0-9]+]], !DIExpression(), [[META105:![0-9]+]])477// CHECK2-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8, !dbg [[DBG106:![0-9]+]]478// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG106]]479// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[GLOBAL_ADDR]], align 8, !dbg [[DBG106]]480// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 1, !dbg [[DBG107:![0-9]+]]481// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !dbg [[DBG107]]482// CHECK2-NEXT: invoke void @_Z3fooIiEvT_(i32 noundef [[TMP3]])483// CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG106]]484// CHECK2: invoke.cont:485// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP2]], align 4, !dbg [[DBG108:![0-9]+]]486// CHECK2-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 1, !dbg [[DBG109:![0-9]+]]487// CHECK2-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX1]], align 4, !dbg [[DBG110:![0-9]+]]488// CHECK2-NEXT: ret void, !dbg [[DBG108]]489// CHECK2: terminate.lpad:490// CHECK2-NEXT: [[TMP5:%.*]] = landingpad { ptr, i32 }491// CHECK2-NEXT: catch ptr null, !dbg [[DBG106]]492// CHECK2-NEXT: [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0, !dbg [[DBG106]]493// CHECK2-NEXT: call void @__clang_call_terminate(ptr [[TMP6]]) #[[ATTR6]], !dbg [[DBG106]]494// CHECK2-NEXT: unreachable, !dbg [[DBG106]]495//496//497// CHECK2-LABEL: define {{[^@]+}}@main.omp_outlined_debug__.2.omp_outlined498// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[GLOBAL:%.*]]) #[[ATTR2]] !dbg [[DBG111:![0-9]+]] {499// CHECK2-NEXT: entry:500// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8501// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8502// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8503// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8504// CHECK2-NEXT: [[GLOBAL_ADDR:%.*]] = alloca ptr, align 8505// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8506// CHECK2-NEXT: #dbg_declare(ptr [[DOTGLOBAL_TID__ADDR]], [[META112:![0-9]+]], !DIExpression(), [[META113:![0-9]+]])507// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8508// CHECK2-NEXT: #dbg_declare(ptr [[DOTBOUND_TID__ADDR]], [[META114:![0-9]+]], !DIExpression(), [[META113]])509// CHECK2-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8510// CHECK2-NEXT: #dbg_declare(ptr [[VLA_ADDR]], [[META115:![0-9]+]], !DIExpression(), [[META113]])511// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8512// CHECK2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META116:![0-9]+]], !DIExpression(), [[META113]])513// CHECK2-NEXT: store ptr [[GLOBAL]], ptr [[GLOBAL_ADDR]], align 8514// CHECK2-NEXT: #dbg_declare(ptr [[GLOBAL_ADDR]], [[META117:![0-9]+]], !DIExpression(), [[META113]])515// CHECK2-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8, !dbg [[DBG118:![0-9]+]]516// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG118]]517// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[GLOBAL_ADDR]], align 8, !dbg [[DBG118]]518// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG118]]519// CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG118]]520// CHECK2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG118]]521// CHECK2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[GLOBAL_ADDR]], align 8, !dbg [[DBG118]]522// CHECK2-NEXT: call void @main.omp_outlined_debug__.2.omp_outlined_debug__(ptr [[TMP3]], ptr [[TMP4]], i64 [[TMP0]], ptr [[TMP5]], ptr [[TMP6]]) #[[ATTR5]], !dbg [[DBG118]]523// CHECK2-NEXT: ret void, !dbg [[DBG118]]524//525//526// CHECK2-LABEL: define {{[^@]+}}@main.omp_outlined_debug__.4527// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] !dbg [[DBG119:![0-9]+]] {528// CHECK2-NEXT: entry:529// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8530// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8531// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8532// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8533// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8534// CHECK2-NEXT: #dbg_declare(ptr [[DOTGLOBAL_TID__ADDR]], [[META120:![0-9]+]], !DIExpression(), [[META121:![0-9]+]])535// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8536// CHECK2-NEXT: #dbg_declare(ptr [[DOTBOUND_TID__ADDR]], [[META122:![0-9]+]], !DIExpression(), [[META121]])537// CHECK2-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8538// CHECK2-NEXT: #dbg_declare(ptr [[VLA_ADDR]], [[META123:![0-9]+]], !DIExpression(), [[META121]])539// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8540// CHECK2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META124:![0-9]+]], !DIExpression(), [[META125:![0-9]+]])541// CHECK2-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8, !dbg [[DBG126:![0-9]+]]542// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG126]]543// CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB7:[0-9]+]], i32 2, ptr @main.omp_outlined_debug__.4.omp_outlined, i64 [[TMP0]], ptr [[TMP1]]), !dbg [[DBG126]]544// CHECK2-NEXT: ret void, !dbg [[DBG127:![0-9]+]]545//546//547// CHECK2-LABEL: define {{[^@]+}}@main.omp_outlined.3548// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] !dbg [[DBG128:![0-9]+]] {549// CHECK2-NEXT: entry:550// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8551// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8552// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8553// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8554// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8555// CHECK2-NEXT: #dbg_declare(ptr [[DOTGLOBAL_TID__ADDR]], [[META129:![0-9]+]], !DIExpression(), [[META130:![0-9]+]])556// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8557// CHECK2-NEXT: #dbg_declare(ptr [[DOTBOUND_TID__ADDR]], [[META131:![0-9]+]], !DIExpression(), [[META130]])558// CHECK2-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8559// CHECK2-NEXT: #dbg_declare(ptr [[VLA_ADDR]], [[META132:![0-9]+]], !DIExpression(), [[META130]])560// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8561// CHECK2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META133:![0-9]+]], !DIExpression(), [[META130]])562// CHECK2-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8, !dbg [[DBG134:![0-9]+]]563// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG134]]564// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG134]]565// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG134]]566// CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG134]]567// CHECK2-NEXT: call void @main.omp_outlined_debug__.4(ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP0]], ptr [[TMP4]]) #[[ATTR5]], !dbg [[DBG134]]568// CHECK2-NEXT: ret void, !dbg [[DBG134]]569//570//571// CHECK2-LABEL: define {{[^@]+}}@main.omp_outlined_debug__.4.omp_outlined_debug__572// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] personality ptr @__gxx_personality_v0 !dbg [[DBG135:![0-9]+]] {573// CHECK2-NEXT: entry:574// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8575// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8576// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8577// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8578// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8579// CHECK2-NEXT: #dbg_declare(ptr [[DOTGLOBAL_TID__ADDR]], [[META136:![0-9]+]], !DIExpression(), [[META137:![0-9]+]])580// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8581// CHECK2-NEXT: #dbg_declare(ptr [[DOTBOUND_TID__ADDR]], [[META138:![0-9]+]], !DIExpression(), [[META137]])582// CHECK2-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8583// CHECK2-NEXT: #dbg_declare(ptr [[VLA_ADDR]], [[META139:![0-9]+]], !DIExpression(), [[META137]])584// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8585// CHECK2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META140:![0-9]+]], !DIExpression(), [[META141:![0-9]+]])586// CHECK2-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8, !dbg [[DBG142:![0-9]+]]587// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG142]]588// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 1, !dbg [[DBG143:![0-9]+]]589// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !dbg [[DBG143]]590// CHECK2-NEXT: invoke void @_Z3fooIiEvT_(i32 noundef [[TMP2]])591// CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG142]]592// CHECK2: invoke.cont:593// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr @global, align 4, !dbg [[DBG144:![0-9]+]]594// CHECK2-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 1, !dbg [[DBG145:![0-9]+]]595// CHECK2-NEXT: store i32 [[TMP3]], ptr [[ARRAYIDX1]], align 4, !dbg [[DBG146:![0-9]+]]596// CHECK2-NEXT: ret void, !dbg [[DBG144]]597// CHECK2: terminate.lpad:598// CHECK2-NEXT: [[TMP4:%.*]] = landingpad { ptr, i32 }599// CHECK2-NEXT: catch ptr null, !dbg [[DBG142]]600// CHECK2-NEXT: [[TMP5:%.*]] = extractvalue { ptr, i32 } [[TMP4]], 0, !dbg [[DBG142]]601// CHECK2-NEXT: call void @__clang_call_terminate(ptr [[TMP5]]) #[[ATTR6]], !dbg [[DBG142]]602// CHECK2-NEXT: unreachable, !dbg [[DBG142]]603//604//605// CHECK2-LABEL: define {{[^@]+}}@main.omp_outlined_debug__.4.omp_outlined606// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] !dbg [[DBG147:![0-9]+]] {607// CHECK2-NEXT: entry:608// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8609// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8610// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8611// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8612// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8613// CHECK2-NEXT: #dbg_declare(ptr [[DOTGLOBAL_TID__ADDR]], [[META148:![0-9]+]], !DIExpression(), [[META149:![0-9]+]])614// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8615// CHECK2-NEXT: #dbg_declare(ptr [[DOTBOUND_TID__ADDR]], [[META150:![0-9]+]], !DIExpression(), [[META149]])616// CHECK2-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8617// CHECK2-NEXT: #dbg_declare(ptr [[VLA_ADDR]], [[META151:![0-9]+]], !DIExpression(), [[META149]])618// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8619// CHECK2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META152:![0-9]+]], !DIExpression(), [[META149]])620// CHECK2-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8, !dbg [[DBG153:![0-9]+]]621// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG153]]622// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG153]]623// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG153]]624// CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG153]]625// CHECK2-NEXT: call void @main.omp_outlined_debug__.4.omp_outlined_debug__(ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP0]], ptr [[TMP4]]) #[[ATTR5]], !dbg [[DBG153]]626// CHECK2-NEXT: ret void, !dbg [[DBG153]]627//628//629// CHECK2-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_630// CHECK2-SAME: (ptr noundef [[ARGC:%.*]]) #[[ATTR3]] comdat !dbg [[DBG154:![0-9]+]] {631// CHECK2-NEXT: entry:632// CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 8633// CHECK2-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8634// CHECK2-NEXT: #dbg_declare(ptr [[ARGC_ADDR]], [[META159:![0-9]+]], !DIExpression(), [[META160:![0-9]+]])635// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8, !dbg [[DBG161:![0-9]+]]636// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i64 0, !dbg [[DBG161]]637// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8, !dbg [[DBG161]]638// CHECK2-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i64 0, !dbg [[DBG161]]639// CHECK2-NEXT: [[TMP2:%.*]] = load i8, ptr [[ARRAYIDX1]], align 1, !dbg [[DBG161]]640// CHECK2-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i64, !dbg [[DBG162:![0-9]+]]641// CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB11:[0-9]+]], i32 2, ptr @_Z5tmainIPPcEiT_.omp_outlined, ptr [[ARGC_ADDR]], i64 [[TMP3]]), !dbg [[DBG163:![0-9]+]]642// CHECK2-NEXT: ret i32 0, !dbg [[DBG164:![0-9]+]]643//644//645// CHECK2-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_.omp_outlined_debug__646// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[ARGC:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR2]] personality ptr @__gxx_personality_v0 !dbg [[DBG165:![0-9]+]] {647// CHECK2-NEXT: entry:648// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8649// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8650// CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 8651// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8652// CHECK2-NEXT: [[VAR:%.*]] = alloca ptr, align 8653// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8654// CHECK2-NEXT: #dbg_declare(ptr [[DOTGLOBAL_TID__ADDR]], [[META169:![0-9]+]], !DIExpression(), [[META170:![0-9]+]])655// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8656// CHECK2-NEXT: #dbg_declare(ptr [[DOTBOUND_TID__ADDR]], [[META171:![0-9]+]], !DIExpression(), [[META170]])657// CHECK2-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8658// CHECK2-NEXT: #dbg_declare(ptr [[ARGC_ADDR]], [[META172:![0-9]+]], !DIExpression(), [[META173:![0-9]+]])659// CHECK2-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8660// CHECK2-NEXT: #dbg_declare(ptr [[VLA_ADDR]], [[META174:![0-9]+]], !DIExpression(), [[META170]])661// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8, !dbg [[DBG175:![0-9]+]]662// CHECK2-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8, !dbg [[DBG175]]663// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP0]], align 8, !dbg [[DBG176:![0-9]+]]664// CHECK2-NEXT: invoke void @_Z3fooIPPcEvT_(ptr noundef [[TMP2]])665// CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG178:![0-9]+]]666// CHECK2: invoke.cont:667// CHECK2-NEXT: #dbg_declare(ptr [[VAR]], [[META179:![0-9]+]], !DIExpression(), [[META186:![0-9]+]])668// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR]], align 8, !dbg [[DBG187:![0-9]+]]669// CHECK2-NEXT: [[TMP4:%.*]] = mul nsw i64 0, [[TMP1]], !dbg [[DBG187]]670// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP3]], i64 [[TMP4]], !dbg [[DBG187]]671// CHECK2-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX]], i64 0, !dbg [[DBG187]]672// CHECK2-NEXT: ret void, !dbg [[DBG188:![0-9]+]]673// CHECK2: terminate.lpad:674// CHECK2-NEXT: [[TMP5:%.*]] = landingpad { ptr, i32 }675// CHECK2-NEXT: catch ptr null, !dbg [[DBG178]]676// CHECK2-NEXT: [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0, !dbg [[DBG178]]677// CHECK2-NEXT: call void @__clang_call_terminate(ptr [[TMP6]]) #[[ATTR6]], !dbg [[DBG178]]678// CHECK2-NEXT: unreachable, !dbg [[DBG178]]679//680//681// CHECK2-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_.omp_outlined682// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[ARGC:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR2]] !dbg [[DBG189:![0-9]+]] {683// CHECK2-NEXT: entry:684// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8685// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8686// CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 8687// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8688// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8689// CHECK2-NEXT: #dbg_declare(ptr [[DOTGLOBAL_TID__ADDR]], [[META190:![0-9]+]], !DIExpression(), [[META191:![0-9]+]])690// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8691// CHECK2-NEXT: #dbg_declare(ptr [[DOTBOUND_TID__ADDR]], [[META192:![0-9]+]], !DIExpression(), [[META191]])692// CHECK2-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8693// CHECK2-NEXT: #dbg_declare(ptr [[ARGC_ADDR]], [[META193:![0-9]+]], !DIExpression(), [[META191]])694// CHECK2-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8695// CHECK2-NEXT: #dbg_declare(ptr [[VLA_ADDR]], [[META194:![0-9]+]], !DIExpression(), [[META191]])696// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8, !dbg [[DBG195:![0-9]+]]697// CHECK2-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8, !dbg [[DBG195]]698// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG195]]699// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG195]]700// CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8, !dbg [[DBG195]]701// CHECK2-NEXT: call void @_Z5tmainIPPcEiT_.omp_outlined_debug__(ptr [[TMP2]], ptr [[TMP3]], ptr [[TMP4]], i64 [[TMP1]]) #[[ATTR5]], !dbg [[DBG195]]702// CHECK2-NEXT: ret void, !dbg [[DBG195]]703//704//705// CHECK2-LABEL: define {{[^@]+}}@_Z3fooIPPcEvT_706// CHECK2-SAME: (ptr noundef [[ARGC:%.*]]) #[[ATTR3]] comdat !dbg [[DBG196:![0-9]+]] {707// CHECK2-NEXT: entry:708// CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 8709// CHECK2-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8710// CHECK2-NEXT: #dbg_declare(ptr [[ARGC_ADDR]], [[META199:![0-9]+]], !DIExpression(), [[META200:![0-9]+]])711// CHECK2-NEXT: ret void, !dbg [[DBG201:![0-9]+]]712//713//714// CHECK3-LABEL: define {{[^@]+}}@main715// CHECK3-SAME: (i32 noundef [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {716// CHECK3-NEXT: entry:717// CHECK3-NEXT: [[STRUCTARG:%.*]] = alloca { ptr }, align 8718// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4719// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4720// CHECK3-NEXT: [[ARGV_ADDR:%.*]] = alloca ptr, align 8721// CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8722// CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8723// CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4724// CHECK3-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4725// CHECK3-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8726// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4727// CHECK3-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64728// CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()729// CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8730// CHECK3-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 16731// CHECK3-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8732// CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])733// CHECK3-NEXT: br label [[OMP_PARALLEL:%.*]]734// CHECK3: omp_parallel:735// CHECK3-NEXT: [[GEP_VLA:%.*]] = getelementptr { ptr }, ptr [[STRUCTARG]], i32 0, i32 0736// CHECK3-NEXT: store ptr [[VLA]], ptr [[GEP_VLA]], align 8737// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @main..omp_par, ptr [[STRUCTARG]])738// CHECK3-NEXT: br label [[OMP_PAR_OUTLINED_EXIT:%.*]]739// CHECK3: omp.par.exit:740// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[ARGV_ADDR]], align 8741// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIPPcEiT_(ptr noundef [[TMP3]])742// CHECK3-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4743// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8744// CHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP4]])745// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[RETVAL]], align 4746// CHECK3-NEXT: ret i32 [[TMP5]]747//748//749// CHECK3-LABEL: define {{[^@]+}}@main..omp_par750// CHECK3-SAME: (ptr noalias [[TID_ADDR:%.*]], ptr noalias [[ZERO_ADDR:%.*]], ptr [[TMP0:%.*]]) #[[ATTR1:[0-9]+]] {751// CHECK3-NEXT: omp.par.entry:752// CHECK3-NEXT: [[GEP_VLA:%.*]] = getelementptr { ptr }, ptr [[TMP0]], i32 0, i32 0753// CHECK3-NEXT: [[LOADGEP_VLA:%.*]] = load ptr, ptr [[GEP_VLA]], align 8754// CHECK3-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4755// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TID_ADDR]], align 4756// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TID_ADDR_LOCAL]], align 4757// CHECK3-NEXT: [[TID:%.*]] = load i32, ptr [[TID_ADDR_LOCAL]], align 4758// CHECK3-NEXT: br label [[OMP_PAR_REGION:%.*]]759// CHECK3: omp.par.region:760// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[LOADGEP_VLA]], i64 1761// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4762// CHECK3-NEXT: call void @_Z3fooIiEvT_(i32 noundef [[TMP2]])763// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr @global, align 4764// CHECK3-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, ptr [[LOADGEP_VLA]], i64 1765// CHECK3-NEXT: store i32 [[TMP3]], ptr [[ARRAYIDX1]], align 4766// CHECK3-NEXT: br label [[OMP_PAR_REGION_PARALLEL_AFTER:%.*]]767// CHECK3: omp.par.region.parallel.after:768// CHECK3-NEXT: br label [[OMP_PAR_PRE_FINALIZE:%.*]]769// CHECK3: omp.par.pre_finalize:770// CHECK3-NEXT: br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB:%.*]]771// CHECK3: omp.par.exit.exitStub:772// CHECK3-NEXT: ret void773//774//775// CHECK3-LABEL: define {{[^@]+}}@_Z3fooIiEvT_776// CHECK3-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat {777// CHECK3-NEXT: entry:778// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4779// CHECK3-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4780// CHECK3-NEXT: ret void781//782//783// CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_784// CHECK3-SAME: (ptr noundef [[ARGC:%.*]]) #[[ATTR5:[0-9]+]] comdat {785// CHECK3-NEXT: entry:786// CHECK3-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8787// CHECK3-NEXT: [[DOTRELOADED:%.*]] = alloca i64, align 8788// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 8789// CHECK3-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8790// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8791// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i64 0792// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8793// CHECK3-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i64 0794// CHECK3-NEXT: [[TMP2:%.*]] = load i8, ptr [[ARRAYIDX1]], align 1795// CHECK3-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i64796// CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])797// CHECK3-NEXT: store i64 [[TMP3]], ptr [[DOTRELOADED]], align 8798// CHECK3-NEXT: br label [[OMP_PARALLEL:%.*]]799// CHECK3: omp_parallel:800// CHECK3-NEXT: [[GEP__RELOADED:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0801// CHECK3-NEXT: store ptr [[DOTRELOADED]], ptr [[GEP__RELOADED]], align 8802// CHECK3-NEXT: [[GEP_ARGC_ADDR:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1803// CHECK3-NEXT: store ptr [[ARGC_ADDR]], ptr [[GEP_ARGC_ADDR]], align 8804// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @_Z5tmainIPPcEiT_..omp_par, ptr [[STRUCTARG]])805// CHECK3-NEXT: br label [[OMP_PAR_OUTLINED_EXIT:%.*]]806// CHECK3: omp.par.exit:807// CHECK3-NEXT: ret i32 0808//809//810// CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_..omp_par811// CHECK3-SAME: (ptr noalias [[TID_ADDR:%.*]], ptr noalias [[ZERO_ADDR:%.*]], ptr [[TMP0:%.*]]) #[[ATTR6:[0-9]+]] {812// CHECK3-NEXT: omp.par.entry:813// CHECK3-NEXT: [[GEP__RELOADED:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP0]], i32 0, i32 0814// CHECK3-NEXT: [[LOADGEP__RELOADED:%.*]] = load ptr, ptr [[GEP__RELOADED]], align 8815// CHECK3-NEXT: [[GEP_ARGC_ADDR:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP0]], i32 0, i32 1816// CHECK3-NEXT: [[LOADGEP_ARGC_ADDR:%.*]] = load ptr, ptr [[GEP_ARGC_ADDR]], align 8817// CHECK3-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4818// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TID_ADDR]], align 4819// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TID_ADDR_LOCAL]], align 4820// CHECK3-NEXT: [[TID:%.*]] = load i32, ptr [[TID_ADDR_LOCAL]], align 4821// CHECK3-NEXT: [[VAR:%.*]] = alloca ptr, align 8822// CHECK3-NEXT: [[TMP2:%.*]] = load i64, ptr [[LOADGEP__RELOADED]], align 8823// CHECK3-NEXT: br label [[OMP_PAR_REGION:%.*]]824// CHECK3: omp.par.region:825// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[LOADGEP_ARGC_ADDR]], align 8826// CHECK3-NEXT: call void @_Z3fooIPPcEvT_(ptr noundef [[TMP3]])827// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[VAR]], align 8828// CHECK3-NEXT: [[TMP5:%.*]] = mul nsw i64 0, [[TMP2]]829// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, ptr [[TMP4]], i64 [[TMP5]]830// CHECK3-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX2]], i64 0831// CHECK3-NEXT: br label [[OMP_PAR_REGION_PARALLEL_AFTER:%.*]]832// CHECK3: omp.par.region.parallel.after:833// CHECK3-NEXT: br label [[OMP_PAR_PRE_FINALIZE:%.*]]834// CHECK3: omp.par.pre_finalize:835// CHECK3-NEXT: br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB:%.*]]836// CHECK3: omp.par.exit.exitStub:837// CHECK3-NEXT: ret void838//839//840// CHECK3-LABEL: define {{[^@]+}}@_Z3fooIPPcEvT_841// CHECK3-SAME: (ptr noundef [[ARGC:%.*]]) #[[ATTR4]] comdat {842// CHECK3-NEXT: entry:843// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 8844// CHECK3-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8845// CHECK3-NEXT: ret void846//847//848// CHECK4-LABEL: define {{[^@]+}}@main849// CHECK4-SAME: (i32 noundef [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG11:![0-9]+]] {850// CHECK4-NEXT: entry:851// CHECK4-NEXT: [[STRUCTARG:%.*]] = alloca { ptr }, align 8852// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4853// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4854// CHECK4-NEXT: [[ARGV_ADDR:%.*]] = alloca ptr, align 8855// CHECK4-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8856// CHECK4-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8857// CHECK4-NEXT: store i32 0, ptr [[RETVAL]], align 4858// CHECK4-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4859// CHECK4-NEXT: #dbg_declare(ptr [[ARGC_ADDR]], [[META18:![0-9]+]], !DIExpression(), [[META19:![0-9]+]])860// CHECK4-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8861// CHECK4-NEXT: #dbg_declare(ptr [[ARGV_ADDR]], [[META20:![0-9]+]], !DIExpression(), [[META19]])862// CHECK4-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4, !dbg [[DBG21:![0-9]+]]863// CHECK4-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64, !dbg [[DBG21]]864// CHECK4-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0(), !dbg [[DBG21]]865// CHECK4-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8, !dbg [[DBG21]]866// CHECK4-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 16, !dbg [[DBG21]]867// CHECK4-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8, !dbg [[DBG21]]868// CHECK4-NEXT: #dbg_declare(ptr [[__VLA_EXPR0]], [[META22:![0-9]+]], !DIExpression(), [[META24:![0-9]+]])869// CHECK4-NEXT: #dbg_declare(ptr [[VLA]], [[META25:![0-9]+]], !DIExpression(), [[DBG21]])870// CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]), !dbg [[DBG29:![0-9]+]]871// CHECK4-NEXT: br label [[OMP_PARALLEL:%.*]]872// CHECK4: omp_parallel:873// CHECK4-NEXT: [[GEP_VLA:%.*]] = getelementptr { ptr }, ptr [[STRUCTARG]], i32 0, i32 0874// CHECK4-NEXT: store ptr [[VLA]], ptr [[GEP_VLA]], align 8875// CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @main..omp_par, ptr [[STRUCTARG]]), !dbg [[DBG30:![0-9]+]]876// CHECK4-NEXT: br label [[OMP_PAR_OUTLINED_EXIT:%.*]]877// CHECK4: omp.par.exit:878// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[ARGV_ADDR]], align 8, !dbg [[DBG31:![0-9]+]]879// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIPPcEiT_(ptr noundef [[TMP3]]), !dbg [[DBG31]]880// CHECK4-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4, !dbg [[DBG31]]881// CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8, !dbg [[DBG32:![0-9]+]]882// CHECK4-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP4]]), !dbg [[DBG32]]883// CHECK4-NEXT: [[TMP5:%.*]] = load i32, ptr [[RETVAL]], align 4, !dbg [[DBG32]]884// CHECK4-NEXT: ret i32 [[TMP5]], !dbg [[DBG32]]885//886//887// CHECK4-LABEL: define {{[^@]+}}@main..omp_par888// CHECK4-SAME: (ptr noalias [[TID_ADDR:%.*]], ptr noalias [[ZERO_ADDR:%.*]], ptr [[TMP0:%.*]]) #[[ATTR1:[0-9]+]] !dbg [[DBG33:![0-9]+]] {889// CHECK4-NEXT: omp.par.entry:890// CHECK4-NEXT: [[GEP_VLA:%.*]] = getelementptr { ptr }, ptr [[TMP0]], i32 0, i32 0891// CHECK4-NEXT: [[LOADGEP_VLA:%.*]] = load ptr, ptr [[GEP_VLA]], align 8892// CHECK4-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4893// CHECK4-NEXT: [[TMP1:%.*]] = load i32, ptr [[TID_ADDR]], align 4894// CHECK4-NEXT: store i32 [[TMP1]], ptr [[TID_ADDR_LOCAL]], align 4895// CHECK4-NEXT: [[TID:%.*]] = load i32, ptr [[TID_ADDR_LOCAL]], align 4896// CHECK4-NEXT: #dbg_declare(ptr [[LOADGEP_VLA]], [[META36:![0-9]+]], !DIExpression(), [[META37:![0-9]+]])897// CHECK4-NEXT: br label [[OMP_PAR_REGION:%.*]]898// CHECK4: omp.par.region:899// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[LOADGEP_VLA]], i64 1, !dbg [[DBG35:![0-9]+]]900// CHECK4-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !dbg [[DBG35]]901// CHECK4-NEXT: call void @_Z3fooIiEvT_(i32 noundef [[TMP2]]), !dbg [[DBG35]]902// CHECK4-NEXT: [[TMP3:%.*]] = load i32, ptr @global, align 4, !dbg [[DBG35]]903// CHECK4-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, ptr [[LOADGEP_VLA]], i64 1, !dbg [[DBG35]]904// CHECK4-NEXT: store i32 [[TMP3]], ptr [[ARRAYIDX1]], align 4, !dbg [[DBG35]]905// CHECK4-NEXT: br label [[OMP_PAR_REGION_PARALLEL_AFTER:%.*]], !dbg [[DBG35]]906// CHECK4: omp.par.region.parallel.after:907// CHECK4-NEXT: br label [[OMP_PAR_PRE_FINALIZE:%.*]]908// CHECK4: omp.par.pre_finalize:909// CHECK4-NEXT: br label [[FINI:%.*]]910// CHECK4: .fini:911// CHECK4-NEXT: br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB:%.*]], !dbg [[DBG35]]912// CHECK4: omp.par.exit.exitStub:913// CHECK4-NEXT: ret void914//915//916// CHECK4-LABEL: define {{[^@]+}}@_Z3fooIiEvT_917// CHECK4-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat !dbg [[DBG36:![0-9]+]] {918// CHECK4-NEXT: entry:919// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4920// CHECK4-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4921// CHECK4-NEXT: #dbg_declare(ptr [[ARGC_ADDR]], [[META41:![0-9]+]], !DIExpression(), [[META42:![0-9]+]])922// CHECK4-NEXT: ret void, !dbg [[META42]]923//924//925// CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_926// CHECK4-SAME: (ptr noundef [[ARGC:%.*]]) #[[ATTR5:[0-9]+]] comdat !dbg [[DBG43:![0-9]+]] {927// CHECK4-NEXT: entry:928// CHECK4-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8929// CHECK4-NEXT: [[DOTRELOADED:%.*]] = alloca i64, align 8930// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 8931// CHECK4-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8932// CHECK4-NEXT: #dbg_declare(ptr [[ARGC_ADDR]], [[META48:![0-9]+]], !DIExpression(), [[META49:![0-9]+]])933// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8, !dbg [[DBG50:![0-9]+]]934// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i64 0, !dbg [[DBG50]]935// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8, !dbg [[DBG50]]936// CHECK4-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i64 0, !dbg [[DBG50]]937// CHECK4-NEXT: [[TMP2:%.*]] = load i8, ptr [[ARRAYIDX1]], align 1, !dbg [[DBG50]]938// CHECK4-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i64, !dbg [[DBG50]]939// CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]]), !dbg [[DBG51:![0-9]+]]940// CHECK4-NEXT: store i64 [[TMP3]], ptr [[DOTRELOADED]], align 8941// CHECK4-NEXT: br label [[OMP_PARALLEL:%.*]]942// CHECK4: omp_parallel:943// CHECK4-NEXT: [[GEP__RELOADED:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0944// CHECK4-NEXT: store ptr [[DOTRELOADED]], ptr [[GEP__RELOADED]], align 8945// CHECK4-NEXT: [[GEP_ARGC_ADDR:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1946// CHECK4-NEXT: store ptr [[ARGC_ADDR]], ptr [[GEP_ARGC_ADDR]], align 8947// CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 1, ptr @_Z5tmainIPPcEiT_..omp_par, ptr [[STRUCTARG]]), !dbg [[DBG52:![0-9]+]]948// CHECK4-NEXT: br label [[OMP_PAR_OUTLINED_EXIT:%.*]]949// CHECK4: omp.par.exit:950// CHECK4-NEXT: ret i32 0, !dbg [[DBG54:![0-9]+]]951//952//953// CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_..omp_par954// CHECK4-SAME: (ptr noalias [[TID_ADDR:%.*]], ptr noalias [[ZERO_ADDR:%.*]], ptr [[TMP0:%.*]]) #[[ATTR6:[0-9]+]] !dbg [[DBG55:![0-9]+]] {955// CHECK4-NEXT: omp.par.entry:956// CHECK4-NEXT: [[GEP__RELOADED:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP0]], i32 0, i32 0957// CHECK4-NEXT: [[LOADGEP__RELOADED:%.*]] = load ptr, ptr [[GEP__RELOADED]], align 8958// CHECK4-NEXT: [[GEP_ARGC_ADDR:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP0]], i32 0, i32 1959// CHECK4-NEXT: [[LOADGEP_ARGC_ADDR:%.*]] = load ptr, ptr [[GEP_ARGC_ADDR]], align 8960// CHECK4-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4961// CHECK4-NEXT: [[TMP1:%.*]] = load i32, ptr [[TID_ADDR]], align 4962// CHECK4-NEXT: store i32 [[TMP1]], ptr [[TID_ADDR_LOCAL]], align 4963// CHECK4-NEXT: [[TID:%.*]] = load i32, ptr [[TID_ADDR_LOCAL]], align 4964// CHECK4-NEXT: [[VAR:%.*]] = alloca ptr, align 8965// CHECK4-NEXT: [[TMP2:%.*]] = load i64, ptr [[LOADGEP__RELOADED]], align 8966// CHECK4-NEXT: #dbg_declare(ptr [[LOADGEP_ARGC_ADDR]], [[META60:![0-9]+]], !DIExpression(), [[META61:![0-9]+]])967// CHECK4-NEXT: br label [[OMP_PAR_REGION:%.*]]968// CHECK4: omp.par.region:969// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[LOADGEP_ARGC_ADDR]], align 8, !dbg [[DBG56:![0-9]+]]970// CHECK4-NEXT: call void @_Z3fooIPPcEvT_(ptr noundef [[TMP3]]), !dbg [[DBG56]]971// CHECK4-NEXT: #dbg_declare(ptr [[VAR]], [[META58:![0-9]+]], !DIExpression(), [[META65:![0-9]+]])972// CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[VAR]], align 8, !dbg [[META65]]973// CHECK4-NEXT: [[TMP5:%.*]] = mul nsw i64 0, [[TMP2]], !dbg [[META65]]974// CHECK4-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, ptr [[TMP4]], i64 [[TMP5]], !dbg [[META65]]975// CHECK4-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX2]], i64 0, !dbg [[META65]]976// CHECK4-NEXT: br label [[OMP_PAR_REGION_PARALLEL_AFTER:%.*]], !dbg [[DBG66:![0-9]+]]977// CHECK4: omp.par.region.parallel.after:978// CHECK4-NEXT: br label [[OMP_PAR_PRE_FINALIZE:%.*]]979// CHECK4: omp.par.pre_finalize:980// CHECK4-NEXT: br label [[FINI:%.*]]981// CHECK4: .fini:982// CHECK4-NEXT: br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB:%.*]], !dbg [[DBG66]]983// CHECK4: omp.par.exit.exitStub:984// CHECK4-NEXT: ret void985//986//987// CHECK4-LABEL: define {{[^@]+}}@_Z3fooIPPcEvT_988// CHECK4-SAME: (ptr noundef [[ARGC:%.*]]) #[[ATTR4]] comdat !dbg [[DBG69:![0-9]+]] {989// CHECK4-NEXT: entry:990// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 8991// CHECK4-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8992// CHECK4-NEXT: #dbg_declare(ptr [[ARGC_ADDR]], [[META72:![0-9]+]], !DIExpression(), [[META73:![0-9]+]])993// CHECK4-NEXT: ret void, !dbg [[META73]]994//995