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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _2// RUN: %clang_cc1 -verify -fopenmp -fnoopenmp-use-tls -x c++ -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13// RUN: %clang_cc1 -fopenmp -fnoopenmp-use-tls -x c++ -std=c++11 -triple x86_64-linux -emit-pch -o %t %s4// RUN: %clang_cc1 -fopenmp -fnoopenmp-use-tls -x c++ -triple x86_64-linux -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15// RUN: %clang_cc1 -verify -fopenmp -fnoopenmp-use-tls -x c++ -std=c++11 -DLAMBDA -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK36// RUN: %clang_cc1 -verify -fopenmp -fnoopenmp-use-tls -x c++ -fblocks -DBLOCKS -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK47// RUN: %clang_cc1 -verify -fopenmp -fnoopenmp-use-tls -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK58 9// RUN: %clang_cc1 -verify -fopenmp-simd -fnoopenmp-use-tls -x c++ -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"10// RUN: %clang_cc1 -fopenmp-simd -fnoopenmp-use-tls -x c++ -std=c++11 -triple x86_64-linux -emit-pch -o %t %s11// RUN: %clang_cc1 -fopenmp-simd -fnoopenmp-use-tls -x c++ -triple x86_64-linux -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"12// RUN: %clang_cc1 -verify -fopenmp-simd -fnoopenmp-use-tls -x c++ -std=c++11 -DLAMBDA -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"13// RUN: %clang_cc1 -verify -fopenmp-simd -fnoopenmp-use-tls -x c++ -fblocks -DBLOCKS -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"14// RUN: %clang_cc1 -verify -fopenmp-simd -fnoopenmp-use-tls -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"15 16// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1117// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-linux -emit-pch -o %t %s18// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-linux -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1119// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1320// RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1421// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1522// RUN: %clang_cc1 -verify -fopenmp -x c++ -DNESTED -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1623 24// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"25// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-linux -emit-pch -o %t %s26// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-linux -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"27// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"28// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"29// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"30// expected-no-diagnostics31#if !defined(ARRAY) && !defined(NESTED)32#ifndef HEADER33#define HEADER34 35volatile int g __attribute__((aligned(128))) = 1212;36#pragma omp threadprivate(g)37 38template <class T>39struct S {40  T f;41  S(T a) : f(a + g) {}42  S() : f(g) {}43  S &operator=(const S &) { return *this; };44  operator T() { return T(); }45  ~S() {}46};47 48 49 50template <typename T>51T tmain() {52  S<T> test;53  test = S<T>();54  static T t_var __attribute__((aligned(128))) = 333;55  static T vec[] __attribute__((aligned(128))) = {3, 3};56  static S<T> s_arr[] __attribute__((aligned(128))) = {1, 2};57  static S<T> var __attribute__((aligned(128))) (3);58#pragma omp threadprivate(t_var, vec, s_arr, var)59#pragma omp parallel copyin(t_var, vec, s_arr, var)60  {61    vec[0] = t_var;62    s_arr[0] = var;63  }64#pragma omp parallel copyin(t_var)65  {}66  return T();67}68 69int main() {70#ifdef LAMBDA71  [&]() {72 73 74#pragma omp parallel copyin(g)75  {76 77    // threadprivate_g = g;78 79 80    g = 1;81 82    [&]() {83      g = 2;84 85    }();86  }87  }();88  return 0;89#elif defined(BLOCKS)90 91  ^{92 93 94#pragma omp parallel copyin(g)95  {96 97    // threadprivate_g = g;98 99 100    g = 1;101 102 103    ^{104      g = 2;105 106    }();107  }108  }();109  return 0;110#else111  S<float> test;112  test = S<float>();113  static int t_var = 1122;114  static int vec[] = {1, 2};115  static S<float> s_arr[] = {1, 2};116  static S<float> var(3);117#pragma omp threadprivate(t_var, vec, s_arr, var)118#pragma omp parallel copyin(t_var, vec, s_arr, var)119  {120    vec[0] = t_var;121    s_arr[0] = var;122  }123#pragma omp parallel copyin(t_var) default(none)124  ++t_var;125  return tmain<int>();126#endif127}128 129 130 131 132 133// threadprivate_t_var = t_var;134 135 136 137// threadprivate_vec = vec;138 139 140// threadprivate_s_arr = s_arr;141 142 143// threadprivate_var = var;144 145 146 147 148 149 150// threadprivate_t_var = t_var;151 152 153 154 155 156 157 158// threadprivate_t_var = t_var;159 160 161 162// threadprivate_vec = vec;163 164 165// threadprivate_s_arr = s_arr;166 167 168// threadprivate_var = var;169 170 171 172 173 174 175// threadprivate_t_var = t_var;176 177 178 179 180 181#endif182#elif defined(ARRAY)183 184struct St {185  int a, b;186  St() : a(0), b(0) {}187  St &operator=(const St &) { return *this; };188  ~St() {}189};190 191void array_func() {192  static int a[2];193  static St s[2];194 195 196#pragma omp threadprivate(a, s)197#pragma omp parallel copyin(a, s)198  ;199}200#elif defined(NESTED)201int t_init();202int t = t_init();203#pragma omp threadprivate(t)204void foo() {205#pragma omp parallel206#pragma omp parallel copyin(t)207  ++t;208}209 210#endif // NESTED211 212// CHECK1-LABEL: define {{[^@]+}}@main213// CHECK1-SAME: () #[[ATTR0:[0-9]+]] {214// CHECK1-NEXT:  entry:215// CHECK1-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4216// CHECK1-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4217// CHECK1-NEXT:    [[REF_TMP:%.*]] = alloca [[STRUCT_S]], align 4218// CHECK1-NEXT:    store i32 0, ptr [[RETVAL]], align 4219// CHECK1-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])220// CHECK1-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]])221// CHECK1-NEXT:    [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]], ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]])222// CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR2:[0-9]+]]223// CHECK1-NEXT:    [[TMP0:%.*]] = load atomic i8, ptr @_ZGVZ4mainE5s_arr acquire, align 8224// CHECK1-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0225// CHECK1-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF3:![0-9]+]]226// CHECK1:       init.check:227// CHECK1-NEXT:    [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(ptr @_ZGVZ4mainE5s_arr) #[[ATTR2]]228// CHECK1-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0229// CHECK1-NEXT:    br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]]230// CHECK1:       init:231// CHECK1-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])232// CHECK1-NEXT:    call void @__kmpc_threadprivate_register(ptr @[[GLOB1]], ptr @_ZZ4mainE5s_arr, ptr @.__kmpc_global_ctor_., ptr null, ptr @.__kmpc_global_dtor_.)233// CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE5s_arr, float noundef 1.000000e+00)234// CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S]], ptr @_ZZ4mainE5s_arr, i64 1), float noundef 2.000000e+00)235// CHECK1-NEXT:    [[TMP3:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]236// CHECK1-NEXT:    call void @__cxa_guard_release(ptr @_ZGVZ4mainE5s_arr) #[[ATTR2]]237// CHECK1-NEXT:    br label [[INIT_END]]238// CHECK1:       init.end:239// CHECK1-NEXT:    [[TMP4:%.*]] = load atomic i8, ptr @_ZGVZ4mainE3var acquire, align 8240// CHECK1-NEXT:    [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP4]], 0241// CHECK1-NEXT:    br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END5:%.*]], !prof [[PROF3]]242// CHECK1:       init.check2:243// CHECK1-NEXT:    [[TMP5:%.*]] = call i32 @__cxa_guard_acquire(ptr @_ZGVZ4mainE3var) #[[ATTR2]]244// CHECK1-NEXT:    [[TOBOOL3:%.*]] = icmp ne i32 [[TMP5]], 0245// CHECK1-NEXT:    br i1 [[TOBOOL3]], label [[INIT4:%.*]], label [[INIT_END5]]246// CHECK1:       init4:247// CHECK1-NEXT:    [[TMP6:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])248// CHECK1-NEXT:    call void @__kmpc_threadprivate_register(ptr @[[GLOB1]], ptr @_ZZ4mainE3var, ptr @.__kmpc_global_ctor_..1, ptr null, ptr @.__kmpc_global_dtor_..2)249// CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE3var, float noundef 3.000000e+00)250// CHECK1-NEXT:    [[TMP7:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @_ZZ4mainE3var, ptr @__dso_handle) #[[ATTR2]]251// CHECK1-NEXT:    call void @__cxa_guard_release(ptr @_ZGVZ4mainE3var) #[[ATTR2]]252// CHECK1-NEXT:    br label [[INIT_END5]]253// CHECK1:       init.end5:254// CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @main.omp_outlined)255// CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @main.omp_outlined.3)256// CHECK1-NEXT:    [[CALL6:%.*]] = call noundef i32 @_Z5tmainIiET_v()257// CHECK1-NEXT:    store i32 [[CALL6]], ptr [[RETVAL]], align 4258// CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]259// CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[RETVAL]], align 4260// CHECK1-NEXT:    ret i32 [[TMP8]]261//262//263// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev264// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {265// CHECK1-NEXT:  entry:266// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8267// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8268// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8269// CHECK1-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])270// CHECK1-NEXT:    ret void271//272//273// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEaSERKS0_274// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR1]] comdat align 2 {275// CHECK1-NEXT:  entry:276// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8277// CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8278// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8279// CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8280// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8281// CHECK1-NEXT:    ret ptr [[THIS1]]282//283//284// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev285// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {286// CHECK1-NEXT:  entry:287// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8288// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8289// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8290// CHECK1-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]291// CHECK1-NEXT:    ret void292//293//294// CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_.295// CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR3:[0-9]+]] section ".text.startup" {296// CHECK1-NEXT:  entry:297// CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8298// CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8299// CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8300// CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]], float noundef 1.000000e+00)301// CHECK1-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[TMP1]], i64 1302// CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00)303// CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8304// CHECK1-NEXT:    ret ptr [[TMP2]]305//306//307// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef308// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {309// CHECK1-NEXT:  entry:310// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8311// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4312// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8313// CHECK1-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4314// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8315// CHECK1-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4316// CHECK1-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])317// CHECK1-NEXT:    ret void318//319//320// CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_.321// CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR3]] section ".text.startup" {322// CHECK1-NEXT:  entry:323// CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8324// CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8325// CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8326// CHECK1-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[TMP1]], i64 2327// CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]328// CHECK1:       arraydestroy.body:329// CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]330// CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1331// CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]332// CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[TMP1]]333// CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]334// CHECK1:       arraydestroy.done1:335// CHECK1-NEXT:    ret void336//337//338// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor339// CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR3]] section ".text.startup" {340// CHECK1-NEXT:  entry:341// CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8342// CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8343// CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]344// CHECK1:       arraydestroy.body:345// CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @_ZZ4mainE5s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]346// CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1347// CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]348// CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @_ZZ4mainE5s_arr349// CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]350// CHECK1:       arraydestroy.done1:351// CHECK1-NEXT:    ret void352//353//354// CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..1355// CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR3]] section ".text.startup" {356// CHECK1-NEXT:  entry:357// CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8358// CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8359// CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8360// CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]], float noundef 3.000000e+00)361// CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8362// CHECK1-NEXT:    ret ptr [[TMP2]]363//364//365// CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..2366// CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR3]] section ".text.startup" {367// CHECK1-NEXT:  entry:368// CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8369// CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8370// CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8371// CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]]) #[[ATTR2]]372// CHECK1-NEXT:    ret void373//374//375// CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined376// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4:[0-9]+]] {377// CHECK1-NEXT:  entry:378// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8379// CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8380// CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8381// CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8382// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8383// CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4384// CHECK1-NEXT:    [[TMP2:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ4mainE5t_var, i64 4, ptr @_ZZ4mainE5t_var.cache.)385// CHECK1-NEXT:    [[TMP3:%.*]] = ptrtoint ptr [[TMP2]] to i64386// CHECK1-NEXT:    [[TMP4:%.*]] = icmp ne i64 ptrtoint (ptr @_ZZ4mainE5t_var to i64), [[TMP3]]387// CHECK1-NEXT:    br i1 [[TMP4]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]388// CHECK1:       copyin.not.master:389// CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr @_ZZ4mainE5t_var, align 4390// CHECK1-NEXT:    store i32 [[TMP5]], ptr [[TMP2]], align 4391// CHECK1-NEXT:    [[TMP6:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ4mainE3vec, i64 8, ptr @_ZZ4mainE3vec.cache.)392// CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP6]], ptr align 4 @_ZZ4mainE3vec, i64 8, i1 false)393// CHECK1-NEXT:    [[TMP7:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ4mainE5s_arr, i64 8, ptr @_ZZ4mainE5s_arr.cache.)394// CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP7]], i32 0, i32 0395// CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 2396// CHECK1-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP8]]397// CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]398// CHECK1:       omp.arraycpy.body:399// CHECK1-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ @_ZZ4mainE5s_arr, [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]400// CHECK1-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]401// CHECK1-NEXT:    [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]])402// CHECK1-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1403// CHECK1-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1404// CHECK1-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]]405// CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]]406// CHECK1:       omp.arraycpy.done1:407// CHECK1-NEXT:    [[TMP9:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ4mainE3var, i64 4, ptr @_ZZ4mainE3var.cache.)408// CHECK1-NEXT:    [[CALL2:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[TMP9]], ptr noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE3var)409// CHECK1-NEXT:    br label [[COPYIN_NOT_MASTER_END]]410// CHECK1:       copyin.not.master.end:411// CHECK1-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2:[0-9]+]], i32 [[TMP1]])412// CHECK1-NEXT:    [[TMP10:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ4mainE5t_var, i64 4, ptr @_ZZ4mainE5t_var.cache.)413// CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4414// CHECK1-NEXT:    [[TMP12:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ4mainE3vec, i64 8, ptr @_ZZ4mainE3vec.cache.)415// CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP12]], i64 0, i64 0416// CHECK1-NEXT:    store i32 [[TMP11]], ptr [[ARRAYIDX]], align 4417// CHECK1-NEXT:    [[TMP13:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ4mainE3var, i64 4, ptr @_ZZ4mainE3var.cache.)418// CHECK1-NEXT:    [[TMP14:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ4mainE5s_arr, i64 8, ptr @_ZZ4mainE5s_arr.cache.)419// CHECK1-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP14]], i64 0, i64 0420// CHECK1-NEXT:    [[CALL4:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYIDX3]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP13]])421// CHECK1-NEXT:    ret void422//423//424// CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.3425// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {426// CHECK1-NEXT:  entry:427// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8428// CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8429// CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8430// CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8431// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8432// CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4433// CHECK1-NEXT:    [[TMP2:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ4mainE5t_var, i64 4, ptr @_ZZ4mainE5t_var.cache.)434// CHECK1-NEXT:    [[TMP3:%.*]] = ptrtoint ptr [[TMP2]] to i64435// CHECK1-NEXT:    [[TMP4:%.*]] = icmp ne i64 ptrtoint (ptr @_ZZ4mainE5t_var to i64), [[TMP3]]436// CHECK1-NEXT:    br i1 [[TMP4]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]437// CHECK1:       copyin.not.master:438// CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr @_ZZ4mainE5t_var, align 4439// CHECK1-NEXT:    store i32 [[TMP5]], ptr [[TMP2]], align 4440// CHECK1-NEXT:    br label [[COPYIN_NOT_MASTER_END]]441// CHECK1:       copyin.not.master.end:442// CHECK1-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2]], i32 [[TMP1]])443// CHECK1-NEXT:    [[TMP6:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ4mainE5t_var, i64 4, ptr @_ZZ4mainE5t_var.cache.)444// CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4445// CHECK1-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP7]], 1446// CHECK1-NEXT:    store i32 [[INC]], ptr [[TMP6]], align 4447// CHECK1-NEXT:    ret void448//449//450// CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v451// CHECK1-SAME: () #[[ATTR1]] comdat {452// CHECK1-NEXT:  entry:453// CHECK1-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4454// CHECK1-NEXT:    [[REF_TMP:%.*]] = alloca [[STRUCT_S_0]], align 4455// CHECK1-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])456// CHECK1-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]])457// CHECK1-NEXT:    [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIiEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]], ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]])458// CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR2]]459// CHECK1-NEXT:    [[TMP0:%.*]] = load atomic i8, ptr @_ZGVZ5tmainIiET_vE5s_arr acquire, align 8460// CHECK1-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0461// CHECK1-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF3]]462// CHECK1:       init.check:463// CHECK1-NEXT:    [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(ptr @_ZGVZ5tmainIiET_vE5s_arr) #[[ATTR2]]464// CHECK1-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0465// CHECK1-NEXT:    br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]]466// CHECK1:       init:467// CHECK1-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])468// CHECK1-NEXT:    call void @__kmpc_threadprivate_register(ptr @[[GLOB1]], ptr @_ZZ5tmainIiET_vE5s_arr, ptr @.__kmpc_global_ctor_..4, ptr null, ptr @.__kmpc_global_dtor_..5)469// CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE5s_arr, i32 noundef 1)470// CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S_0]], ptr @_ZZ5tmainIiET_vE5s_arr, i64 1), i32 noundef 2)471// CHECK1-NEXT:    [[TMP3:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor.6, ptr null, ptr @__dso_handle) #[[ATTR2]]472// CHECK1-NEXT:    call void @__cxa_guard_release(ptr @_ZGVZ5tmainIiET_vE5s_arr) #[[ATTR2]]473// CHECK1-NEXT:    br label [[INIT_END]]474// CHECK1:       init.end:475// CHECK1-NEXT:    [[TMP4:%.*]] = load atomic i8, ptr @_ZGVZ5tmainIiET_vE3var acquire, align 8476// CHECK1-NEXT:    [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP4]], 0477// CHECK1-NEXT:    br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END5:%.*]], !prof [[PROF3]]478// CHECK1:       init.check2:479// CHECK1-NEXT:    [[TMP5:%.*]] = call i32 @__cxa_guard_acquire(ptr @_ZGVZ5tmainIiET_vE3var) #[[ATTR2]]480// CHECK1-NEXT:    [[TOBOOL3:%.*]] = icmp ne i32 [[TMP5]], 0481// CHECK1-NEXT:    br i1 [[TOBOOL3]], label [[INIT4:%.*]], label [[INIT_END5]]482// CHECK1:       init4:483// CHECK1-NEXT:    [[TMP6:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])484// CHECK1-NEXT:    call void @__kmpc_threadprivate_register(ptr @[[GLOB1]], ptr @_ZZ5tmainIiET_vE3var, ptr @.__kmpc_global_ctor_..7, ptr null, ptr @.__kmpc_global_dtor_..8)485// CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var, i32 noundef 3)486// CHECK1-NEXT:    [[TMP7:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIiED1Ev, ptr @_ZZ5tmainIiET_vE3var, ptr @__dso_handle) #[[ATTR2]]487// CHECK1-NEXT:    call void @__cxa_guard_release(ptr @_ZGVZ5tmainIiET_vE3var) #[[ATTR2]]488// CHECK1-NEXT:    br label [[INIT_END5]]489// CHECK1:       init.end5:490// CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @_Z5tmainIiET_v.omp_outlined)491// CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @_Z5tmainIiET_v.omp_outlined.9)492// CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]493// CHECK1-NEXT:    ret i32 0494//495//496// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev497// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {498// CHECK1-NEXT:  entry:499// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8500// CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])501// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8502// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8503// CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0504// CHECK1-NEXT:    [[TMP1:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @g, i64 4, ptr @g.cache.)505// CHECK1-NEXT:    [[TMP2:%.*]] = load volatile i32, ptr [[TMP1]], align 128506// CHECK1-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP2]] to float507// CHECK1-NEXT:    store float [[CONV]], ptr [[F]], align 4508// CHECK1-NEXT:    ret void509//510//511// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev512// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {513// CHECK1-NEXT:  entry:514// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8515// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8516// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8517// CHECK1-NEXT:    ret void518//519//520// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef521// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {522// CHECK1-NEXT:  entry:523// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8524// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4525// CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])526// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8527// CHECK1-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4528// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8529// CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0530// CHECK1-NEXT:    [[TMP1:%.*]] = load float, ptr [[A_ADDR]], align 4531// CHECK1-NEXT:    [[TMP2:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @g, i64 4, ptr @g.cache.)532// CHECK1-NEXT:    [[TMP3:%.*]] = load volatile i32, ptr [[TMP2]], align 128533// CHECK1-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP3]] to float534// CHECK1-NEXT:    [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]535// CHECK1-NEXT:    store float [[ADD]], ptr [[F]], align 4536// CHECK1-NEXT:    ret void537//538//539// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev540// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {541// CHECK1-NEXT:  entry:542// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8543// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8544// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8545// CHECK1-NEXT:    call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])546// CHECK1-NEXT:    ret void547//548//549// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEaSERKS0_550// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR1]] comdat align 2 {551// CHECK1-NEXT:  entry:552// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8553// CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8554// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8555// CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8556// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8557// CHECK1-NEXT:    ret ptr [[THIS1]]558//559//560// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev561// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {562// CHECK1-NEXT:  entry:563// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8564// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8565// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8566// CHECK1-NEXT:    call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]567// CHECK1-NEXT:    ret void568//569//570// CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..4571// CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR3]] section ".text.startup" {572// CHECK1-NEXT:  entry:573// CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8574// CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8575// CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8576// CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]], i32 noundef 1)577// CHECK1-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[TMP1]], i64 1578// CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)579// CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8580// CHECK1-NEXT:    ret ptr [[TMP2]]581//582//583// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei584// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {585// CHECK1-NEXT:  entry:586// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8587// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4588// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8589// CHECK1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4590// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8591// CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4592// CHECK1-NEXT:    call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])593// CHECK1-NEXT:    ret void594//595//596// CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..5597// CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR3]] section ".text.startup" {598// CHECK1-NEXT:  entry:599// CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8600// CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8601// CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8602// CHECK1-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[TMP1]], i64 2603// CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]604// CHECK1:       arraydestroy.body:605// CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]606// CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1607// CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]608// CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[TMP1]]609// CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]610// CHECK1:       arraydestroy.done1:611// CHECK1-NEXT:    ret void612//613//614// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor.6615// CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR3]] section ".text.startup" {616// CHECK1-NEXT:  entry:617// CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8618// CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8619// CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]620// CHECK1:       arraydestroy.body:621// CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S_0:%.*]], ptr @_ZZ5tmainIiET_vE5s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]622// CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1623// CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]624// CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @_ZZ5tmainIiET_vE5s_arr625// CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]626// CHECK1:       arraydestroy.done1:627// CHECK1-NEXT:    ret void628//629//630// CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..7631// CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR3]] section ".text.startup" {632// CHECK1-NEXT:  entry:633// CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8634// CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8635// CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8636// CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]], i32 noundef 3)637// CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8638// CHECK1-NEXT:    ret ptr [[TMP2]]639//640//641// CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..8642// CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR3]] section ".text.startup" {643// CHECK1-NEXT:  entry:644// CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8645// CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8646// CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8647// CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]]) #[[ATTR2]]648// CHECK1-NEXT:    ret void649//650//651// CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v.omp_outlined652// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {653// CHECK1-NEXT:  entry:654// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8655// CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8656// CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8657// CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8658// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8659// CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4660// CHECK1-NEXT:    [[TMP2:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ5tmainIiET_vE5t_var, i64 4, ptr @_ZZ5tmainIiET_vE5t_var.cache.)661// CHECK1-NEXT:    [[TMP3:%.*]] = ptrtoint ptr [[TMP2]] to i64662// CHECK1-NEXT:    [[TMP4:%.*]] = icmp ne i64 ptrtoint (ptr @_ZZ5tmainIiET_vE5t_var to i64), [[TMP3]]663// CHECK1-NEXT:    br i1 [[TMP4]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]664// CHECK1:       copyin.not.master:665// CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr @_ZZ5tmainIiET_vE5t_var, align 128666// CHECK1-NEXT:    store i32 [[TMP5]], ptr [[TMP2]], align 128667// CHECK1-NEXT:    [[TMP6:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ5tmainIiET_vE3vec, i64 8, ptr @_ZZ5tmainIiET_vE3vec.cache.)668// CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[TMP6]], ptr align 128 @_ZZ5tmainIiET_vE3vec, i64 8, i1 false)669// CHECK1-NEXT:    [[TMP7:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ5tmainIiET_vE5s_arr, i64 8, ptr @_ZZ5tmainIiET_vE5s_arr.cache.)670// CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP7]], i32 0, i32 0671// CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[ARRAY_BEGIN]], i64 2672// CHECK1-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP8]]673// CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]674// CHECK1:       omp.arraycpy.body:675// CHECK1-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ @_ZZ5tmainIiET_vE5s_arr, [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]676// CHECK1-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]677// CHECK1-NEXT:    [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIiEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]])678// CHECK1-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1679// CHECK1-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1680// CHECK1-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]]681// CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]]682// CHECK1:       omp.arraycpy.done1:683// CHECK1-NEXT:    [[TMP9:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ5tmainIiET_vE3var, i64 4, ptr @_ZZ5tmainIiET_vE3var.cache.)684// CHECK1-NEXT:    [[CALL2:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIiEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[TMP9]], ptr noundef nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var)685// CHECK1-NEXT:    br label [[COPYIN_NOT_MASTER_END]]686// CHECK1:       copyin.not.master.end:687// CHECK1-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2]], i32 [[TMP1]])688// CHECK1-NEXT:    [[TMP10:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ5tmainIiET_vE5t_var, i64 4, ptr @_ZZ5tmainIiET_vE5t_var.cache.)689// CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 128690// CHECK1-NEXT:    [[TMP12:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ5tmainIiET_vE3vec, i64 8, ptr @_ZZ5tmainIiET_vE3vec.cache.)691// CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP12]], i64 0, i64 0692// CHECK1-NEXT:    store i32 [[TMP11]], ptr [[ARRAYIDX]], align 128693// CHECK1-NEXT:    [[TMP13:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ5tmainIiET_vE3var, i64 4, ptr @_ZZ5tmainIiET_vE3var.cache.)694// CHECK1-NEXT:    [[TMP14:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ5tmainIiET_vE5s_arr, i64 8, ptr @_ZZ5tmainIiET_vE5s_arr.cache.)695// CHECK1-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP14]], i64 0, i64 0696// CHECK1-NEXT:    [[CALL4:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIiEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYIDX3]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP13]])697// CHECK1-NEXT:    ret void698//699//700// CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v.omp_outlined.9701// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {702// CHECK1-NEXT:  entry:703// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8704// CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8705// CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8706// CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8707// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8708// CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4709// CHECK1-NEXT:    [[TMP2:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ5tmainIiET_vE5t_var, i64 4, ptr @_ZZ5tmainIiET_vE5t_var.cache.)710// CHECK1-NEXT:    [[TMP3:%.*]] = ptrtoint ptr [[TMP2]] to i64711// CHECK1-NEXT:    [[TMP4:%.*]] = icmp ne i64 ptrtoint (ptr @_ZZ5tmainIiET_vE5t_var to i64), [[TMP3]]712// CHECK1-NEXT:    br i1 [[TMP4]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]713// CHECK1:       copyin.not.master:714// CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr @_ZZ5tmainIiET_vE5t_var, align 128715// CHECK1-NEXT:    store i32 [[TMP5]], ptr [[TMP2]], align 128716// CHECK1-NEXT:    br label [[COPYIN_NOT_MASTER_END]]717// CHECK1:       copyin.not.master.end:718// CHECK1-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2]], i32 [[TMP1]])719// CHECK1-NEXT:    ret void720//721//722// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev723// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {724// CHECK1-NEXT:  entry:725// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8726// CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])727// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8728// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8729// CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0730// CHECK1-NEXT:    [[TMP1:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @g, i64 4, ptr @g.cache.)731// CHECK1-NEXT:    [[TMP2:%.*]] = load volatile i32, ptr [[TMP1]], align 128732// CHECK1-NEXT:    store i32 [[TMP2]], ptr [[F]], align 4733// CHECK1-NEXT:    ret void734//735//736// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev737// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {738// CHECK1-NEXT:  entry:739// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8740// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8741// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8742// CHECK1-NEXT:    ret void743//744//745// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei746// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {747// CHECK1-NEXT:  entry:748// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8749// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4750// CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])751// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8752// CHECK1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4753// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8754// CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0755// CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4756// CHECK1-NEXT:    [[TMP2:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @g, i64 4, ptr @g.cache.)757// CHECK1-NEXT:    [[TMP3:%.*]] = load volatile i32, ptr [[TMP2]], align 128758// CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP3]]759// CHECK1-NEXT:    store i32 [[ADD]], ptr [[F]], align 4760// CHECK1-NEXT:    ret void761//762//763// CHECK3-LABEL: define {{[^@]+}}@main764// CHECK3-SAME: () #[[ATTR0:[0-9]+]] {765// CHECK3-NEXT:  entry:766// CHECK3-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4767// CHECK3-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1768// CHECK3-NEXT:    store i32 0, ptr [[RETVAL]], align 4769// CHECK3-NEXT:    call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])770// CHECK3-NEXT:    ret i32 0771//772//773// CHECK4-LABEL: define {{[^@]+}}@main774// CHECK4-SAME: () #[[ATTR1:[0-9]+]] {775// CHECK4-NEXT:  entry:776// CHECK4-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4777// CHECK4-NEXT:    store i32 0, ptr [[RETVAL]], align 4778// CHECK4-NEXT:    [[TMP0:%.*]] = load ptr, ptr getelementptr inbounds nuw ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr @__block_literal_global, i32 0, i32 3), align 8779// CHECK4-NEXT:    call void [[TMP0]](ptr noundef @__block_literal_global)780// CHECK4-NEXT:    ret i32 0781//782//783// CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke784// CHECK4-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] {785// CHECK4-NEXT:  entry:786// CHECK4-NEXT:    [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8787// CHECK4-NEXT:    [[BLOCK_ADDR:%.*]] = alloca ptr, align 8788// CHECK4-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8789// CHECK4-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8790// CHECK4-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 0, ptr @__main_block_invoke.omp_outlined)791// CHECK4-NEXT:    ret void792//793//794// CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke.omp_outlined795// CHECK4-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {796// CHECK4-NEXT:  entry:797// CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8798// CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8799// CHECK4-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8800// CHECK4-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8801// CHECK4-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8802// CHECK4-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4803// CHECK4-NEXT:    [[TMP2:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @g, i64 4, ptr @g.cache.)804// CHECK4-NEXT:    [[TMP3:%.*]] = ptrtoint ptr [[TMP2]] to i64805// CHECK4-NEXT:    [[TMP4:%.*]] = icmp ne i64 ptrtoint (ptr @g to i64), [[TMP3]]806// CHECK4-NEXT:    br i1 [[TMP4]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]807// CHECK4:       copyin.not.master:808// CHECK4-NEXT:    [[TMP5:%.*]] = load i32, ptr @g, align 128809// CHECK4-NEXT:    store volatile i32 [[TMP5]], ptr [[TMP2]], align 128810// CHECK4-NEXT:    br label [[COPYIN_NOT_MASTER_END]]811// CHECK4:       copyin.not.master.end:812// CHECK4-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2:[0-9]+]], i32 [[TMP1]])813// CHECK4-NEXT:    [[TMP6:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @g, i64 4, ptr @g.cache.)814// CHECK4-NEXT:    store volatile i32 1, ptr [[TMP6]], align 128815// CHECK4-NEXT:    [[TMP7:%.*]] = load ptr, ptr getelementptr inbounds nuw ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr @__block_literal_global.2, i32 0, i32 3), align 8816// CHECK4-NEXT:    call void [[TMP7]](ptr noundef @__block_literal_global.2)817// CHECK4-NEXT:    ret void818//819//820// CHECK4-LABEL: define {{[^@]+}}@g_block_invoke821// CHECK4-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] {822// CHECK4-NEXT:  entry:823// CHECK4-NEXT:    [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8824// CHECK4-NEXT:    [[BLOCK_ADDR:%.*]] = alloca ptr, align 8825// CHECK4-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])826// CHECK4-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8827// CHECK4-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8828// CHECK4-NEXT:    [[TMP1:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @g, i64 4, ptr @g.cache.)829// CHECK4-NEXT:    store volatile i32 2, ptr [[TMP1]], align 128830// CHECK4-NEXT:    ret void831//832//833// CHECK5-LABEL: define {{[^@]+}}@_Z10array_funcv834// CHECK5-SAME: () #[[ATTR0:[0-9]+]] {835// CHECK5-NEXT:  entry:836// CHECK5-NEXT:    [[TMP0:%.*]] = load atomic i8, ptr @_ZGVZ10array_funcvE1s acquire, align 8837// CHECK5-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0838// CHECK5-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF3:![0-9]+]]839// CHECK5:       init.check:840// CHECK5-NEXT:    [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(ptr @_ZGVZ10array_funcvE1s) #[[ATTR1:[0-9]+]]841// CHECK5-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0842// CHECK5-NEXT:    br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]]843// CHECK5:       init:844// CHECK5-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])845// CHECK5-NEXT:    call void @__kmpc_threadprivate_register(ptr @[[GLOB1]], ptr @_ZZ10array_funcvE1s, ptr @.__kmpc_global_ctor_., ptr null, ptr @.__kmpc_global_dtor_.)846// CHECK5-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]847// CHECK5:       arrayctor.loop:848// CHECK5-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ @_ZZ10array_funcvE1s, [[INIT]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]849// CHECK5-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[ARRAYCTOR_CUR]])850// CHECK5-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[ARRAYCTOR_CUR]], i64 1851// CHECK5-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], getelementptr inbounds ([[STRUCT_ST]], ptr @_ZZ10array_funcvE1s, i64 2)852// CHECK5-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]853// CHECK5:       arrayctor.cont:854// CHECK5-NEXT:    [[TMP3:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR1]]855// CHECK5-NEXT:    call void @__cxa_guard_release(ptr @_ZGVZ10array_funcvE1s) #[[ATTR1]]856// CHECK5-NEXT:    br label [[INIT_END]]857// CHECK5:       init.end:858// CHECK5-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @_Z10array_funcv.omp_outlined)859// CHECK5-NEXT:    ret void860//861//862// CHECK5-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_.863// CHECK5-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" {864// CHECK5-NEXT:  entry:865// CHECK5-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8866// CHECK5-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8867// CHECK5-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8868// CHECK5-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.St], ptr [[TMP1]], i32 0, i32 0869// CHECK5-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[ARRAY_BEGIN]], i64 2870// CHECK5-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]871// CHECK5:       arrayctor.loop:872// CHECK5-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]873// CHECK5-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[ARRAYCTOR_CUR]])874// CHECK5-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_ST]], ptr [[ARRAYCTOR_CUR]], i64 1875// CHECK5-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]876// CHECK5-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]877// CHECK5:       arrayctor.cont:878// CHECK5-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8879// CHECK5-NEXT:    ret ptr [[TMP2]]880//881//882// CHECK5-LABEL: define {{[^@]+}}@_ZN2StC1Ev883// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 {884// CHECK5-NEXT:  entry:885// CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8886// CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8887// CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8888// CHECK5-NEXT:    call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]])889// CHECK5-NEXT:    ret void890//891//892// CHECK5-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_.893// CHECK5-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR2]] section "__TEXT,__StaticInit,regular,pure_instructions" {894// CHECK5-NEXT:  entry:895// CHECK5-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8896// CHECK5-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8897// CHECK5-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8898// CHECK5-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[TMP1]], i64 2899// CHECK5-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]900// CHECK5:       arraydestroy.body:901// CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]902// CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_ST]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1903// CHECK5-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR1]]904// CHECK5-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[TMP1]]905// CHECK5-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]906// CHECK5:       arraydestroy.done1:907// CHECK5-NEXT:    ret void908//909//910// CHECK5-LABEL: define {{[^@]+}}@_ZN2StD1Ev911// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 {912// CHECK5-NEXT:  entry:913// CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8914// CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8915// CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8916// CHECK5-NEXT:    call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR1]]917// CHECK5-NEXT:    ret void918//919//920// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor921// CHECK5-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR2]] section "__TEXT,__StaticInit,regular,pure_instructions" {922// CHECK5-NEXT:  entry:923// CHECK5-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8924// CHECK5-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8925// CHECK5-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]926// CHECK5:       arraydestroy.body:927// CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_ST:%.*]], ptr @_ZZ10array_funcvE1s, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]928// CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_ST]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1929// CHECK5-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR1]]930// CHECK5-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @_ZZ10array_funcvE1s931// CHECK5-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]932// CHECK5:       arraydestroy.done1:933// CHECK5-NEXT:    ret void934//935//936// CHECK5-LABEL: define {{[^@]+}}@_Z10array_funcv.omp_outlined937// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {938// CHECK5-NEXT:  entry:939// CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8940// CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8941// CHECK5-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8942// CHECK5-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8943// CHECK5-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8944// CHECK5-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4945// CHECK5-NEXT:    [[TMP2:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ10array_funcvE1a, i64 8, ptr @_ZZ10array_funcvE1a.cache.)946// CHECK5-NEXT:    [[TMP3:%.*]] = ptrtoint ptr [[TMP2]] to i64947// CHECK5-NEXT:    [[TMP4:%.*]] = icmp ne i64 ptrtoint (ptr @_ZZ10array_funcvE1a to i64), [[TMP3]]948// CHECK5-NEXT:    br i1 [[TMP4]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]949// CHECK5:       copyin.not.master:950// CHECK5-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP2]], ptr align 4 @_ZZ10array_funcvE1a, i64 8, i1 false)951// CHECK5-NEXT:    [[TMP5:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ10array_funcvE1s, i64 16, ptr @_ZZ10array_funcvE1s.cache.)952// CHECK5-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.St], ptr [[TMP5]], i32 0, i32 0953// CHECK5-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[ARRAY_BEGIN]], i64 2954// CHECK5-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP6]]955// CHECK5-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]956// CHECK5:       omp.arraycpy.body:957// CHECK5-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ @_ZZ10array_funcvE1s, [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]958// CHECK5-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]959// CHECK5-NEXT:    [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(8) ptr @_ZN2StaSERKS_(ptr noundef nonnull align 4 dereferenceable(8) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(8) [[OMP_ARRAYCPY_SRCELEMENTPAST]])960// CHECK5-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_ST]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1961// CHECK5-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_ST]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1962// CHECK5-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]963// CHECK5-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]]964// CHECK5:       omp.arraycpy.done1:965// CHECK5-NEXT:    br label [[COPYIN_NOT_MASTER_END]]966// CHECK5:       copyin.not.master.end:967// CHECK5-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2:[0-9]+]], i32 [[TMP1]])968// CHECK5-NEXT:    ret void969//970//971// CHECK5-LABEL: define {{[^@]+}}@_ZN2StaSERKS_972// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[TMP0:%.*]]) #[[ATTR0]] align 2 {973// CHECK5-NEXT:  entry:974// CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8975// CHECK5-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8976// CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8977// CHECK5-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8978// CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8979// CHECK5-NEXT:    ret ptr [[THIS1]]980//981//982// CHECK5-LABEL: define {{[^@]+}}@_ZN2StC2Ev983// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 {984// CHECK5-NEXT:  entry:985// CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8986// CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8987// CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8988// CHECK5-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0989// CHECK5-NEXT:    store i32 0, ptr [[A]], align 4990// CHECK5-NEXT:    [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1991// CHECK5-NEXT:    store i32 0, ptr [[B]], align 4992// CHECK5-NEXT:    ret void993//994//995// CHECK5-LABEL: define {{[^@]+}}@_ZN2StD2Ev996// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 {997// CHECK5-NEXT:  entry:998// CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8999// CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81000// CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81001// CHECK5-NEXT:    ret void1002//1003//1004// CHECK11-LABEL: define {{[^@]+}}@main1005// CHECK11-SAME: () #[[ATTR0:[0-9]+]] {1006// CHECK11-NEXT:  entry:1007// CHECK11-NEXT:    [[RETVAL:%.*]] = alloca i32, align 41008// CHECK11-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 41009// CHECK11-NEXT:    [[REF_TMP:%.*]] = alloca [[STRUCT_S]], align 41010// CHECK11-NEXT:    store i32 0, ptr [[RETVAL]], align 41011// CHECK11-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])1012// CHECK11-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]])1013// CHECK11-NEXT:    [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]], ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]])1014// CHECK11-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR3:[0-9]+]]1015// CHECK11-NEXT:    [[TMP0:%.*]] = load i8, ptr @_ZGVZ4mainE5s_arr, align 11016// CHECK11-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 01017// CHECK11-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF3:![0-9]+]]1018// CHECK11:       init.check:1019// CHECK11-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE5s_arr, float noundef 1.000000e+00)1020// CHECK11-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S]], ptr @_ZZ4mainE5s_arr, i64 1), float noundef 2.000000e+00)1021// CHECK11-NEXT:    [[TMP1:%.*]] = call i32 @__cxa_thread_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]]1022// CHECK11-NEXT:    store i8 1, ptr @_ZGVZ4mainE5s_arr, align 11023// CHECK11-NEXT:    br label [[INIT_END]]1024// CHECK11:       init.end:1025// CHECK11-NEXT:    [[TMP2:%.*]] = load i8, ptr @_ZGVZ4mainE3var, align 11026// CHECK11-NEXT:    [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP2]], 01027// CHECK11-NEXT:    br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END3:%.*]], !prof [[PROF3]]1028// CHECK11:       init.check2:1029// CHECK11-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE3var, float noundef 3.000000e+00)1030// CHECK11-NEXT:    [[TMP3:%.*]] = call i32 @__cxa_thread_atexit(ptr @_ZN1SIfED1Ev, ptr @_ZZ4mainE3var, ptr @__dso_handle) #[[ATTR3]]1031// CHECK11-NEXT:    store i8 1, ptr @_ZGVZ4mainE3var, align 11032// CHECK11-NEXT:    br label [[INIT_END3]]1033// CHECK11:       init.end3:1034// CHECK11-NEXT:    [[TMP4:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ4mainE5t_var)1035// CHECK11-NEXT:    [[TMP5:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ4mainE3vec)1036// CHECK11-NEXT:    [[TMP6:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ4mainE5s_arr)1037// CHECK11-NEXT:    [[TMP7:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ4mainE3var)1038// CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @main.omp_outlined, ptr [[TMP4]], ptr [[TMP5]], ptr [[TMP6]], ptr [[TMP7]])1039// CHECK11-NEXT:    [[TMP8:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ4mainE5t_var)1040// CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @main.omp_outlined.1, ptr [[TMP8]])1041// CHECK11-NEXT:    [[CALL4:%.*]] = call noundef i32 @_Z5tmainIiET_v()1042// CHECK11-NEXT:    store i32 [[CALL4]], ptr [[RETVAL]], align 41043// CHECK11-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]]1044// CHECK11-NEXT:    [[TMP9:%.*]] = load i32, ptr [[RETVAL]], align 41045// CHECK11-NEXT:    ret i32 [[TMP9]]1046//1047//1048// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev1049// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {1050// CHECK11-NEXT:  entry:1051// CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81052// CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81053// CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81054// CHECK11-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])1055// CHECK11-NEXT:    ret void1056//1057//1058// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEaSERKS0_1059// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR1]] comdat align 2 {1060// CHECK11-NEXT:  entry:1061// CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81062// CHECK11-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 81063// CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81064// CHECK11-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 81065// CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81066// CHECK11-NEXT:    ret ptr [[THIS1]]1067//1068//1069// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev1070// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1071// CHECK11-NEXT:  entry:1072// CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81073// CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81074// CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81075// CHECK11-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]]1076// CHECK11-NEXT:    ret void1077//1078//1079// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef1080// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1081// CHECK11-NEXT:  entry:1082// CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81083// CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca float, align 41084// CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81085// CHECK11-NEXT:    store float [[A]], ptr [[A_ADDR]], align 41086// CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81087// CHECK11-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 41088// CHECK11-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])1089// CHECK11-NEXT:    ret void1090//1091//1092// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor1093// CHECK11-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] section ".text.startup" {1094// CHECK11-NEXT:  entry:1095// CHECK11-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 81096// CHECK11-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 81097// CHECK11-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]1098// CHECK11:       arraydestroy.body:1099// CHECK11-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @_ZZ4mainE5s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1100// CHECK11-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -11101// CHECK11-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]1102// CHECK11-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @_ZZ4mainE5s_arr1103// CHECK11-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]1104// CHECK11:       arraydestroy.done1:1105// CHECK11-NEXT:    ret void1106//1107//1108// CHECK11-LABEL: define {{[^@]+}}@main.omp_outlined1109// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4:[0-9]+]] {1110// CHECK11-NEXT:  entry:1111// CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81112// CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81113// CHECK11-NEXT:    [[T_VAR_ADDR:%.*]] = alloca ptr, align 81114// CHECK11-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 81115// CHECK11-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 81116// CHECK11-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 81117// CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81118// CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81119// CHECK11-NEXT:    store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 81120// CHECK11-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 81121// CHECK11-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 81122// CHECK11-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 81123// CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 81124// CHECK11-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 81125// CHECK11-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 81126// CHECK11-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 81127// CHECK11-NEXT:    [[TMP4:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ4mainE5t_var)1128// CHECK11-NEXT:    [[TMP5:%.*]] = ptrtoint ptr [[TMP0]] to i641129// CHECK11-NEXT:    [[TMP6:%.*]] = ptrtoint ptr [[TMP4]] to i641130// CHECK11-NEXT:    [[TMP7:%.*]] = icmp ne i64 [[TMP5]], [[TMP6]]1131// CHECK11-NEXT:    br i1 [[TMP7]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]1132// CHECK11:       copyin.not.master:1133// CHECK11-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP0]], align 41134// CHECK11-NEXT:    store i32 [[TMP8]], ptr [[TMP4]], align 41135// CHECK11-NEXT:    [[TMP9:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ4mainE3vec)1136// CHECK11-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP9]], ptr align 4 [[TMP1]], i64 8, i1 false)1137// CHECK11-NEXT:    [[TMP10:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ4mainE5s_arr)1138// CHECK11-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP10]], i32 0, i32 01139// CHECK11-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 21140// CHECK11-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP11]]1141// CHECK11-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]1142// CHECK11:       omp.arraycpy.body:1143// CHECK11-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1144// CHECK11-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1145// CHECK11-NEXT:    [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]])1146// CHECK11-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 11147// CHECK11-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 11148// CHECK11-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP11]]1149// CHECK11-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]]1150// CHECK11:       omp.arraycpy.done1:1151// CHECK11-NEXT:    [[TMP12:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ4mainE3var)1152// CHECK11-NEXT:    [[CALL2:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[TMP12]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP3]])1153// CHECK11-NEXT:    br label [[COPYIN_NOT_MASTER_END]]1154// CHECK11:       copyin.not.master.end:1155// CHECK11-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81156// CHECK11-NEXT:    [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 41157// CHECK11-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB1:[0-9]+]], i32 [[TMP14]])1158// CHECK11-NEXT:    [[TMP15:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ4mainE5t_var)1159// CHECK11-NEXT:    [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 41160// CHECK11-NEXT:    [[TMP17:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ4mainE3vec)1161// CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP17]], i64 0, i64 01162// CHECK11-NEXT:    store i32 [[TMP16]], ptr [[ARRAYIDX]], align 41163// CHECK11-NEXT:    [[TMP18:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ4mainE3var)1164// CHECK11-NEXT:    [[TMP19:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ4mainE5s_arr)1165// CHECK11-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP19]], i64 0, i64 01166// CHECK11-NEXT:    [[CALL4:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYIDX3]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP18]])1167// CHECK11-NEXT:    ret void1168//1169//1170// CHECK11-LABEL: define {{[^@]+}}@main.omp_outlined.11171// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR4]] {1172// CHECK11-NEXT:  entry:1173// CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81174// CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81175// CHECK11-NEXT:    [[T_VAR_ADDR:%.*]] = alloca ptr, align 81176// CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81177// CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81178// CHECK11-NEXT:    store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 81179// CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 81180// CHECK11-NEXT:    [[TMP1:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ4mainE5t_var)1181// CHECK11-NEXT:    [[TMP2:%.*]] = ptrtoint ptr [[TMP0]] to i641182// CHECK11-NEXT:    [[TMP3:%.*]] = ptrtoint ptr [[TMP1]] to i641183// CHECK11-NEXT:    [[TMP4:%.*]] = icmp ne i64 [[TMP2]], [[TMP3]]1184// CHECK11-NEXT:    br i1 [[TMP4]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]1185// CHECK11:       copyin.not.master:1186// CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 41187// CHECK11-NEXT:    store i32 [[TMP5]], ptr [[TMP1]], align 41188// CHECK11-NEXT:    br label [[COPYIN_NOT_MASTER_END]]1189// CHECK11:       copyin.not.master.end:1190// CHECK11-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81191// CHECK11-NEXT:    [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 41192// CHECK11-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB1]], i32 [[TMP7]])1193// CHECK11-NEXT:    [[TMP8:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ4mainE5t_var)1194// CHECK11-NEXT:    [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 41195// CHECK11-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP9]], 11196// CHECK11-NEXT:    store i32 [[INC]], ptr [[TMP8]], align 41197// CHECK11-NEXT:    ret void1198//1199//1200// CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiET_v1201// CHECK11-SAME: () #[[ATTR1]] comdat {1202// CHECK11-NEXT:  entry:1203// CHECK11-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 41204// CHECK11-NEXT:    [[REF_TMP:%.*]] = alloca [[STRUCT_S_0]], align 41205// CHECK11-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])1206// CHECK11-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]])1207// CHECK11-NEXT:    [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIiEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]], ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]])1208// CHECK11-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR3]]1209// CHECK11-NEXT:    [[TMP0:%.*]] = load i8, ptr @_ZGVZ5tmainIiET_vE5s_arr, align 81210// CHECK11-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 01211// CHECK11-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF3]]1212// CHECK11:       init.check:1213// CHECK11-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE5s_arr, i32 noundef 1)1214// CHECK11-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S_0]], ptr @_ZZ5tmainIiET_vE5s_arr, i64 1), i32 noundef 2)1215// CHECK11-NEXT:    [[TMP1:%.*]] = call i32 @__cxa_thread_atexit(ptr @__cxx_global_array_dtor.2, ptr null, ptr @__dso_handle) #[[ATTR3]]1216// CHECK11-NEXT:    store i8 1, ptr @_ZGVZ5tmainIiET_vE5s_arr, align 81217// CHECK11-NEXT:    br label [[INIT_END]]1218// CHECK11:       init.end:1219// CHECK11-NEXT:    [[TMP2:%.*]] = load i8, ptr @_ZGVZ5tmainIiET_vE3var, align 81220// CHECK11-NEXT:    [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP2]], 01221// CHECK11-NEXT:    br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END3:%.*]], !prof [[PROF3]]1222// CHECK11:       init.check2:1223// CHECK11-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var, i32 noundef 3)1224// CHECK11-NEXT:    [[TMP3:%.*]] = call i32 @__cxa_thread_atexit(ptr @_ZN1SIiED1Ev, ptr @_ZZ5tmainIiET_vE3var, ptr @__dso_handle) #[[ATTR3]]1225// CHECK11-NEXT:    store i8 1, ptr @_ZGVZ5tmainIiET_vE3var, align 81226// CHECK11-NEXT:    br label [[INIT_END3]]1227// CHECK11:       init.end3:1228// CHECK11-NEXT:    [[TMP4:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @_ZZ5tmainIiET_vE5t_var)1229// CHECK11-NEXT:    [[TMP5:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @_ZZ5tmainIiET_vE3vec)1230// CHECK11-NEXT:    [[TMP6:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @_ZZ5tmainIiET_vE5s_arr)1231// CHECK11-NEXT:    [[TMP7:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @_ZZ5tmainIiET_vE3var)1232// CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_Z5tmainIiET_v.omp_outlined, ptr [[TMP4]], ptr [[TMP5]], ptr [[TMP6]], ptr [[TMP7]])1233// CHECK11-NEXT:    [[TMP8:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @_ZZ5tmainIiET_vE5t_var)1234// CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @_Z5tmainIiET_v.omp_outlined.3, ptr [[TMP8]])1235// CHECK11-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]]1236// CHECK11-NEXT:    ret i32 01237//1238//1239// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev1240// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1241// CHECK11-NEXT:  entry:1242// CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81243// CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81244// CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81245// CHECK11-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 01246// CHECK11-NEXT:    [[TMP0:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @g)1247// CHECK11-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr [[TMP0]], align 1281248// CHECK11-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float1249// CHECK11-NEXT:    store float [[CONV]], ptr [[F]], align 41250// CHECK11-NEXT:    ret void1251//1252//1253// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev1254// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1255// CHECK11-NEXT:  entry:1256// CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81257// CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81258// CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81259// CHECK11-NEXT:    ret void1260//1261//1262// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef1263// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1264// CHECK11-NEXT:  entry:1265// CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81266// CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca float, align 41267// CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81268// CHECK11-NEXT:    store float [[A]], ptr [[A_ADDR]], align 41269// CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81270// CHECK11-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 01271// CHECK11-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 41272// CHECK11-NEXT:    [[TMP1:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @g)1273// CHECK11-NEXT:    [[TMP2:%.*]] = load volatile i32, ptr [[TMP1]], align 1281274// CHECK11-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP2]] to float1275// CHECK11-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]1276// CHECK11-NEXT:    store float [[ADD]], ptr [[F]], align 41277// CHECK11-NEXT:    ret void1278//1279//1280// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev1281// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1282// CHECK11-NEXT:  entry:1283// CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81284// CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81285// CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81286// CHECK11-NEXT:    call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])1287// CHECK11-NEXT:    ret void1288//1289//1290// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEaSERKS0_1291// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR1]] comdat align 2 {1292// CHECK11-NEXT:  entry:1293// CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81294// CHECK11-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 81295// CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81296// CHECK11-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 81297// CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81298// CHECK11-NEXT:    ret ptr [[THIS1]]1299//1300//1301// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev1302// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1303// CHECK11-NEXT:  entry:1304// CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81305// CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81306// CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81307// CHECK11-NEXT:    call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]]1308// CHECK11-NEXT:    ret void1309//1310//1311// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei1312// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1313// CHECK11-NEXT:  entry:1314// CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81315// CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 41316// CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81317// CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 41318// CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81319// CHECK11-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41320// CHECK11-NEXT:    call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])1321// CHECK11-NEXT:    ret void1322//1323//1324// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor.21325// CHECK11-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR2]] section ".text.startup" {1326// CHECK11-NEXT:  entry:1327// CHECK11-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 81328// CHECK11-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 81329// CHECK11-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]1330// CHECK11:       arraydestroy.body:1331// CHECK11-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S_0:%.*]], ptr @_ZZ5tmainIiET_vE5s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1332// CHECK11-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -11333// CHECK11-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]1334// CHECK11-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @_ZZ5tmainIiET_vE5s_arr1335// CHECK11-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]1336// CHECK11:       arraydestroy.done1:1337// CHECK11-NEXT:    ret void1338//1339//1340// CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiET_v.omp_outlined1341// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {1342// CHECK11-NEXT:  entry:1343// CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81344// CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81345// CHECK11-NEXT:    [[T_VAR_ADDR:%.*]] = alloca ptr, align 81346// CHECK11-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 81347// CHECK11-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 81348// CHECK11-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 81349// CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81350// CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81351// CHECK11-NEXT:    store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 81352// CHECK11-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 81353// CHECK11-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 81354// CHECK11-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 81355// CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 81356// CHECK11-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 81357// CHECK11-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 81358// CHECK11-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 81359// CHECK11-NEXT:    [[TMP4:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @_ZZ5tmainIiET_vE5t_var)1360// CHECK11-NEXT:    [[TMP5:%.*]] = ptrtoint ptr [[TMP0]] to i641361// CHECK11-NEXT:    [[TMP6:%.*]] = ptrtoint ptr [[TMP4]] to i641362// CHECK11-NEXT:    [[TMP7:%.*]] = icmp ne i64 [[TMP5]], [[TMP6]]1363// CHECK11-NEXT:    br i1 [[TMP7]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]1364// CHECK11:       copyin.not.master:1365// CHECK11-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP0]], align 1281366// CHECK11-NEXT:    store i32 [[TMP8]], ptr [[TMP4]], align 1281367// CHECK11-NEXT:    [[TMP9:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @_ZZ5tmainIiET_vE3vec)1368// CHECK11-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[TMP9]], ptr align 128 [[TMP1]], i64 8, i1 false)1369// CHECK11-NEXT:    [[TMP10:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @_ZZ5tmainIiET_vE5s_arr)1370// CHECK11-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP10]], i32 0, i32 01371// CHECK11-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[ARRAY_BEGIN]], i64 21372// CHECK11-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP11]]1373// CHECK11-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]1374// CHECK11:       omp.arraycpy.body:1375// CHECK11-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1376// CHECK11-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1377// CHECK11-NEXT:    [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIiEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]])1378// CHECK11-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 11379// CHECK11-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 11380// CHECK11-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP11]]1381// CHECK11-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]]1382// CHECK11:       omp.arraycpy.done1:1383// CHECK11-NEXT:    [[TMP12:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @_ZZ5tmainIiET_vE3var)1384// CHECK11-NEXT:    [[CALL2:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIiEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[TMP12]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP3]])1385// CHECK11-NEXT:    br label [[COPYIN_NOT_MASTER_END]]1386// CHECK11:       copyin.not.master.end:1387// CHECK11-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81388// CHECK11-NEXT:    [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 41389// CHECK11-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB1]], i32 [[TMP14]])1390// CHECK11-NEXT:    [[TMP15:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @_ZZ5tmainIiET_vE5t_var)1391// CHECK11-NEXT:    [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 1281392// CHECK11-NEXT:    [[TMP17:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @_ZZ5tmainIiET_vE3vec)1393// CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP17]], i64 0, i64 01394// CHECK11-NEXT:    store i32 [[TMP16]], ptr [[ARRAYIDX]], align 1281395// CHECK11-NEXT:    [[TMP18:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @_ZZ5tmainIiET_vE3var)1396// CHECK11-NEXT:    [[TMP19:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @_ZZ5tmainIiET_vE5s_arr)1397// CHECK11-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP19]], i64 0, i64 01398// CHECK11-NEXT:    [[CALL4:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIiEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYIDX3]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP18]])1399// CHECK11-NEXT:    ret void1400//1401//1402// CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiET_v.omp_outlined.31403// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR4]] {1404// CHECK11-NEXT:  entry:1405// CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81406// CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81407// CHECK11-NEXT:    [[T_VAR_ADDR:%.*]] = alloca ptr, align 81408// CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81409// CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81410// CHECK11-NEXT:    store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 81411// CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 81412// CHECK11-NEXT:    [[TMP1:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @_ZZ5tmainIiET_vE5t_var)1413// CHECK11-NEXT:    [[TMP2:%.*]] = ptrtoint ptr [[TMP0]] to i641414// CHECK11-NEXT:    [[TMP3:%.*]] = ptrtoint ptr [[TMP1]] to i641415// CHECK11-NEXT:    [[TMP4:%.*]] = icmp ne i64 [[TMP2]], [[TMP3]]1416// CHECK11-NEXT:    br i1 [[TMP4]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]1417// CHECK11:       copyin.not.master:1418// CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 1281419// CHECK11-NEXT:    store i32 [[TMP5]], ptr [[TMP1]], align 1281420// CHECK11-NEXT:    br label [[COPYIN_NOT_MASTER_END]]1421// CHECK11:       copyin.not.master.end:1422// CHECK11-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81423// CHECK11-NEXT:    [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 41424// CHECK11-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB1]], i32 [[TMP7]])1425// CHECK11-NEXT:    ret void1426//1427//1428// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev1429// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1430// CHECK11-NEXT:  entry:1431// CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81432// CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81433// CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81434// CHECK11-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 01435// CHECK11-NEXT:    [[TMP0:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @g)1436// CHECK11-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr [[TMP0]], align 1281437// CHECK11-NEXT:    store i32 [[TMP1]], ptr [[F]], align 41438// CHECK11-NEXT:    ret void1439//1440//1441// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev1442// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1443// CHECK11-NEXT:  entry:1444// CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81445// CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81446// CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81447// CHECK11-NEXT:    ret void1448//1449//1450// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei1451// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1452// CHECK11-NEXT:  entry:1453// CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81454// CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 41455// CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81456// CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 41457// CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81458// CHECK11-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 01459// CHECK11-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41460// CHECK11-NEXT:    [[TMP1:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @g)1461// CHECK11-NEXT:    [[TMP2:%.*]] = load volatile i32, ptr [[TMP1]], align 1281462// CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP2]]1463// CHECK11-NEXT:    store i32 [[ADD]], ptr [[F]], align 41464// CHECK11-NEXT:    ret void1465//1466//1467// CHECK11-LABEL: define {{[^@]+}}@_ZTW1g1468// CHECK11-SAME: () #[[ATTR8:[0-9]+]] comdat {1469// CHECK11-NEXT:    [[TMP1:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @g)1470// CHECK11-NEXT:    ret ptr [[TMP1]]1471//1472//1473// CHECK13-LABEL: define {{[^@]+}}@main1474// CHECK13-SAME: () #[[ATTR0:[0-9]+]] {1475// CHECK13-NEXT:  entry:1476// CHECK13-NEXT:    [[RETVAL:%.*]] = alloca i32, align 41477// CHECK13-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 11478// CHECK13-NEXT:    store i32 0, ptr [[RETVAL]], align 41479// CHECK13-NEXT:    call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])1480// CHECK13-NEXT:    ret i32 01481//1482//1483// CHECK13-LABEL: define {{[^@]+}}@_ZTW1g1484// CHECK13-SAME: () #[[ATTR6:[0-9]+]] comdat {1485// CHECK13-NEXT:    [[TMP1:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @g)1486// CHECK13-NEXT:    ret ptr [[TMP1]]1487//1488//1489// CHECK14-LABEL: define {{[^@]+}}@main1490// CHECK14-SAME: () #[[ATTR1:[0-9]+]] {1491// CHECK14-NEXT:  entry:1492// CHECK14-NEXT:    [[RETVAL:%.*]] = alloca i32, align 41493// CHECK14-NEXT:    store i32 0, ptr [[RETVAL]], align 41494// CHECK14-NEXT:    [[TMP0:%.*]] = load ptr, ptr getelementptr inbounds nuw ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr @__block_literal_global, i32 0, i32 3), align 81495// CHECK14-NEXT:    call void [[TMP0]](ptr noundef @__block_literal_global)1496// CHECK14-NEXT:    ret i32 01497//1498//1499// CHECK14-LABEL: define {{[^@]+}}@__main_block_invoke1500// CHECK14-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] {1501// CHECK14-NEXT:  entry:1502// CHECK14-NEXT:    [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 81503// CHECK14-NEXT:    [[BLOCK_ADDR:%.*]] = alloca ptr, align 81504// CHECK14-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 81505// CHECK14-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 81506// CHECK14-NEXT:    [[TMP0:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @g)1507// CHECK14-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 1, ptr @__main_block_invoke.omp_outlined, ptr [[TMP0]])1508// CHECK14-NEXT:    ret void1509//1510//1511// CHECK14-LABEL: define {{[^@]+}}@__main_block_invoke.omp_outlined1512// CHECK14-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[G:%.*]]) #[[ATTR3:[0-9]+]] {1513// CHECK14-NEXT:  entry:1514// CHECK14-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81515// CHECK14-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81516// CHECK14-NEXT:    [[G_ADDR:%.*]] = alloca ptr, align 81517// CHECK14-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81518// CHECK14-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81519// CHECK14-NEXT:    store ptr [[G]], ptr [[G_ADDR]], align 81520// CHECK14-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 81521// CHECK14-NEXT:    [[TMP1:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @g)1522// CHECK14-NEXT:    [[TMP2:%.*]] = ptrtoint ptr [[TMP0]] to i641523// CHECK14-NEXT:    [[TMP3:%.*]] = ptrtoint ptr [[TMP1]] to i641524// CHECK14-NEXT:    [[TMP4:%.*]] = icmp ne i64 [[TMP2]], [[TMP3]]1525// CHECK14-NEXT:    br i1 [[TMP4]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]1526// CHECK14:       copyin.not.master:1527// CHECK14-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 1281528// CHECK14-NEXT:    store volatile i32 [[TMP5]], ptr [[TMP1]], align 1281529// CHECK14-NEXT:    br label [[COPYIN_NOT_MASTER_END]]1530// CHECK14:       copyin.not.master.end:1531// CHECK14-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81532// CHECK14-NEXT:    [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 41533// CHECK14-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB1:[0-9]+]], i32 [[TMP7]])1534// CHECK14-NEXT:    [[TMP8:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @g)1535// CHECK14-NEXT:    store volatile i32 1, ptr [[TMP8]], align 1281536// CHECK14-NEXT:    [[TMP9:%.*]] = load ptr, ptr getelementptr inbounds nuw ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr @__block_literal_global.2, i32 0, i32 3), align 81537// CHECK14-NEXT:    call void [[TMP9]](ptr noundef @__block_literal_global.2)1538// CHECK14-NEXT:    ret void1539//1540//1541// CHECK14-LABEL: define {{[^@]+}}@g_block_invoke1542// CHECK14-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] {1543// CHECK14-NEXT:  entry:1544// CHECK14-NEXT:    [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 81545// CHECK14-NEXT:    [[BLOCK_ADDR:%.*]] = alloca ptr, align 81546// CHECK14-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 81547// CHECK14-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 81548// CHECK14-NEXT:    [[TMP0:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @g)1549// CHECK14-NEXT:    store volatile i32 2, ptr [[TMP0]], align 1281550// CHECK14-NEXT:    ret void1551//1552//1553// CHECK14-LABEL: define {{[^@]+}}@_ZTW1g1554// CHECK14-SAME: () #[[ATTR7:[0-9]+]] comdat {1555// CHECK14-NEXT:    [[TMP1:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @g)1556// CHECK14-NEXT:    ret ptr [[TMP1]]1557//1558//1559// CHECK15-LABEL: define {{[^@]+}}@_Z10array_funcv1560// CHECK15-SAME: () #[[ATTR0:[0-9]+]] {1561// CHECK15-NEXT:  entry:1562// CHECK15-NEXT:    [[TMP0:%.*]] = load i8, ptr @_ZGVZ10array_funcvE1s, align 11563// CHECK15-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 01564// CHECK15-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF3:![0-9]+]]1565// CHECK15:       init.check:1566// CHECK15-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]1567// CHECK15:       arrayctor.loop:1568// CHECK15-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ @_ZZ10array_funcvE1s, [[INIT_CHECK]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]1569// CHECK15-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[ARRAYCTOR_CUR]])1570// CHECK15-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[ARRAYCTOR_CUR]], i64 11571// CHECK15-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], getelementptr inbounds ([[STRUCT_ST]], ptr @_ZZ10array_funcvE1s, i64 2)1572// CHECK15-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]1573// CHECK15:       arrayctor.cont:1574// CHECK15-NEXT:    [[TMP1:%.*]] = call i32 @__cxa_thread_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2:[0-9]+]]1575// CHECK15-NEXT:    store i8 1, ptr @_ZGVZ10array_funcvE1s, align 11576// CHECK15-NEXT:    br label [[INIT_END]]1577// CHECK15:       init.end:1578// CHECK15-NEXT:    [[TMP2:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ10array_funcvE1a)1579// CHECK15-NEXT:    [[TMP3:%.*]] = call align 16 ptr @llvm.threadlocal.address.p0(ptr align 16 @_ZZ10array_funcvE1s)1580// CHECK15-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 2, ptr @_Z10array_funcv.omp_outlined, ptr [[TMP2]], ptr [[TMP3]])1581// CHECK15-NEXT:    ret void1582//1583//1584// CHECK15-LABEL: define {{[^@]+}}@_ZN2StC1Ev1585// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat align 2 {1586// CHECK15-NEXT:  entry:1587// CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81588// CHECK15-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81589// CHECK15-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81590// CHECK15-NEXT:    call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]])1591// CHECK15-NEXT:    ret void1592//1593//1594// CHECK15-LABEL: define {{[^@]+}}@__cxx_global_array_dtor1595// CHECK15-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR1:[0-9]+]] section ".text.startup" {1596// CHECK15-NEXT:  entry:1597// CHECK15-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 81598// CHECK15-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 81599// CHECK15-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]1600// CHECK15:       arraydestroy.body:1601// CHECK15-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_ST:%.*]], ptr @_ZZ10array_funcvE1s, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1602// CHECK15-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_ST]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -11603// CHECK15-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]1604// CHECK15-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @_ZZ10array_funcvE1s1605// CHECK15-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]1606// CHECK15:       arraydestroy.done1:1607// CHECK15-NEXT:    ret void1608//1609//1610// CHECK15-LABEL: define {{[^@]+}}@_ZN2StD1Ev1611// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat align 2 {1612// CHECK15-NEXT:  entry:1613// CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81614// CHECK15-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81615// CHECK15-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81616// CHECK15-NEXT:    call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]]1617// CHECK15-NEXT:    ret void1618//1619//1620// CHECK15-LABEL: define {{[^@]+}}@_Z10array_funcv.omp_outlined1621// CHECK15-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(16) [[S:%.*]]) #[[ATTR3:[0-9]+]] {1622// CHECK15-NEXT:  entry:1623// CHECK15-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81624// CHECK15-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81625// CHECK15-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 81626// CHECK15-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 81627// CHECK15-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81628// CHECK15-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81629// CHECK15-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 81630// CHECK15-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 81631// CHECK15-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 81632// CHECK15-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ADDR]], align 81633// CHECK15-NEXT:    [[TMP2:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ10array_funcvE1a)1634// CHECK15-NEXT:    [[TMP3:%.*]] = ptrtoint ptr [[TMP0]] to i641635// CHECK15-NEXT:    [[TMP4:%.*]] = ptrtoint ptr [[TMP2]] to i641636// CHECK15-NEXT:    [[TMP5:%.*]] = icmp ne i64 [[TMP3]], [[TMP4]]1637// CHECK15-NEXT:    br i1 [[TMP5]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]1638// CHECK15:       copyin.not.master:1639// CHECK15-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP2]], ptr align 4 [[TMP0]], i64 8, i1 false)1640// CHECK15-NEXT:    [[TMP6:%.*]] = call align 16 ptr @llvm.threadlocal.address.p0(ptr align 16 @_ZZ10array_funcvE1s)1641// CHECK15-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.St], ptr [[TMP6]], i32 0, i32 01642// CHECK15-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[ARRAY_BEGIN]], i64 21643// CHECK15-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP7]]1644// CHECK15-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]1645// CHECK15:       omp.arraycpy.body:1646// CHECK15-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1647// CHECK15-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1648// CHECK15-NEXT:    [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(8) ptr @_ZN2StaSERKS_(ptr noundef nonnull align 4 dereferenceable(8) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(8) [[OMP_ARRAYCPY_SRCELEMENTPAST]])1649// CHECK15-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_ST]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 11650// CHECK15-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_ST]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 11651// CHECK15-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP7]]1652// CHECK15-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]]1653// CHECK15:       omp.arraycpy.done1:1654// CHECK15-NEXT:    br label [[COPYIN_NOT_MASTER_END]]1655// CHECK15:       copyin.not.master.end:1656// CHECK15-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81657// CHECK15-NEXT:    [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 41658// CHECK15-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB1:[0-9]+]], i32 [[TMP9]])1659// CHECK15-NEXT:    ret void1660//1661//1662// CHECK15-LABEL: define {{[^@]+}}@_ZN2StaSERKS_1663// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[TMP0:%.*]]) #[[ATTR0]] comdat align 2 {1664// CHECK15-NEXT:  entry:1665// CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81666// CHECK15-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 81667// CHECK15-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81668// CHECK15-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 81669// CHECK15-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81670// CHECK15-NEXT:    ret ptr [[THIS1]]1671//1672//1673// CHECK15-LABEL: define {{[^@]+}}@_ZN2StC2Ev1674// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat align 2 {1675// CHECK15-NEXT:  entry:1676// CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81677// CHECK15-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81678// CHECK15-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81679// CHECK15-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 01680// CHECK15-NEXT:    store i32 0, ptr [[A]], align 41681// CHECK15-NEXT:    [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 11682// CHECK15-NEXT:    store i32 0, ptr [[B]], align 41683// CHECK15-NEXT:    ret void1684//1685//1686// CHECK15-LABEL: define {{[^@]+}}@_ZN2StD2Ev1687// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat align 2 {1688// CHECK15-NEXT:  entry:1689// CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81690// CHECK15-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81691// CHECK15-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81692// CHECK15-NEXT:    ret void1693//1694//1695// CHECK16-LABEL: define {{[^@]+}}@__cxx_global_var_init1696// CHECK16-SAME: () #[[ATTR0:[0-9]+]] section ".text.startup" {1697// CHECK16-NEXT:  entry:1698// CHECK16-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z6t_initv()1699// CHECK16-NEXT:    [[TMP0:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @t)1700// CHECK16-NEXT:    store i32 [[CALL]], ptr [[TMP0]], align 41701// CHECK16-NEXT:    ret void1702//1703//1704// CHECK16-LABEL: define {{[^@]+}}@_Z3foov1705// CHECK16-SAME: () #[[ATTR3:[0-9]+]] {1706// CHECK16-NEXT:  entry:1707// CHECK16-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @_Z3foov.omp_outlined)1708// CHECK16-NEXT:    ret void1709//1710//1711// CHECK16-LABEL: define {{[^@]+}}@_Z3foov.omp_outlined1712// CHECK16-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4:[0-9]+]] {1713// CHECK16-NEXT:  entry:1714// CHECK16-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81715// CHECK16-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81716// CHECK16-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81717// CHECK16-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81718// CHECK16-NEXT:    [[TMP0:%.*]] = call ptr @_ZTW1t()1719// CHECK16-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @_Z3foov.omp_outlined.omp_outlined, ptr [[TMP0]])1720// CHECK16-NEXT:    ret void1721//1722//1723// CHECK16-LABEL: define {{[^@]+}}@_Z3foov.omp_outlined.omp_outlined1724// CHECK16-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T:%.*]]) #[[ATTR4]] {1725// CHECK16-NEXT:  entry:1726// CHECK16-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81727// CHECK16-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81728// CHECK16-NEXT:    [[T_ADDR:%.*]] = alloca ptr, align 81729// CHECK16-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81730// CHECK16-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81731// CHECK16-NEXT:    store ptr [[T]], ptr [[T_ADDR]], align 81732// CHECK16-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[T_ADDR]], align 81733// CHECK16-NEXT:    [[TMP1:%.*]] = call ptr @_ZTW1t()1734// CHECK16-NEXT:    [[TMP2:%.*]] = ptrtoint ptr [[TMP0]] to i641735// CHECK16-NEXT:    [[TMP3:%.*]] = ptrtoint ptr [[TMP1]] to i641736// CHECK16-NEXT:    [[TMP4:%.*]] = icmp ne i64 [[TMP2]], [[TMP3]]1737// CHECK16-NEXT:    br i1 [[TMP4]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]1738// CHECK16:       copyin.not.master:1739// CHECK16-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 41740// CHECK16-NEXT:    store i32 [[TMP5]], ptr [[TMP1]], align 41741// CHECK16-NEXT:    br label [[COPYIN_NOT_MASTER_END]]1742// CHECK16:       copyin.not.master.end:1743// CHECK16-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81744// CHECK16-NEXT:    [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 41745// CHECK16-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB1:[0-9]+]], i32 [[TMP7]])1746// CHECK16-NEXT:    [[TMP8:%.*]] = call ptr @_ZTW1t()1747// CHECK16-NEXT:    [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 41748// CHECK16-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP9]], 11749// CHECK16-NEXT:    store i32 [[INC]], ptr [[TMP8]], align 41750// CHECK16-NEXT:    ret void1751//1752//1753// CHECK16-LABEL: define {{[^@]+}}@_ZTW1t1754// CHECK16-SAME: () #[[ATTR5:[0-9]+]] comdat {1755// CHECK16-NEXT:    call void @_ZTH1t()1756// CHECK16-NEXT:    [[TMP1:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @t)1757// CHECK16-NEXT:    ret ptr [[TMP1]]1758//1759//1760// CHECK16-LABEL: define {{[^@]+}}@__tls_init1761// CHECK16-SAME: () #[[ATTR0]] {1762// CHECK16-NEXT:  entry:1763// CHECK16-NEXT:    [[TMP0:%.*]] = load i8, ptr @__tls_guard, align 11764// CHECK16-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 01765// CHECK16-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT:%.*]], label [[EXIT:%.*]], !prof [[PROF5:![0-9]+]]1766// CHECK16:       init:1767// CHECK16-NEXT:    store i8 1, ptr @__tls_guard, align 11768// CHECK16-NEXT:    call void @__cxx_global_var_init()1769// CHECK16-NEXT:    br label [[EXIT]]1770// CHECK16:       exit:1771// CHECK16-NEXT:    ret void1772//1773