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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _2// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp -x c++ -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -std=c++11 -triple i386-pc-linux-gnu -emit-pch -o %t %s4// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -triple i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DLAMBDA -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK36// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp -x c++ -fblocks -DBLOCKS -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK47 8// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"9// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -x c++ -std=c++11 -triple i386-pc-linux-gnu -emit-pch -o %t %s10// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -x c++ -triple i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"11// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"12// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"13 14// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp -x c++ -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK915// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -std=c++11 -triple x86_64-pc-linux-gnu -emit-pch -o %t %s16// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -triple x86_64-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK917// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1118// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1219 20// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp-simd -x c++ -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"21// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -x c++ -std=c++11 -triple x86_64-pc-linux-gnu -emit-pch -o %t %s22// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -x c++ -triple x86_64-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"23// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"24// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"25 26// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1727 28// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"29// expected-no-diagnostics30#ifndef ARRAY31#ifndef HEADER32#define HEADER33 34enum omp_allocator_handle_t {35  omp_null_allocator = 0,36  omp_default_mem_alloc = 1,37  omp_large_cap_mem_alloc = 2,38  omp_const_mem_alloc = 3,39  omp_high_bw_mem_alloc = 4,40  omp_low_lat_mem_alloc = 5,41  omp_cgroup_mem_alloc = 6,42  omp_pteam_mem_alloc = 7,43  omp_thread_mem_alloc = 8,44  KMP_ALLOCATOR_MAX_HANDLE = __UINTPTR_MAX__45};46 47struct St {48  int a, b;49  St() : a(0), b(0) {}50  St(const St &st) : a(st.a + st.b), b(0) {}51  ~St() {}52};53 54volatile int g __attribute__((aligned(128))) = 1212;55 56struct SS {57  int a;58  int b : 4;59  int &c;60  int e[4];61  SS(int &d) : a(0), b(0), c(d) {62#pragma omp parallel firstprivate(a, b, c, e)63#ifdef LAMBDA64    [&]() {65      ++this->a, --b, (this)->c /= 1;66#pragma omp parallel firstprivate(a, b, c)67      ++(this)->a, --b, this->c /= 1;68    }();69#elif defined(BLOCKS)70    ^{71      ++a;72      --this->b;73      (this)->c /= 1;74#pragma omp parallel firstprivate(a, b, c)75      ++(this)->a, --b, this->c /= 1;76    }();77#else78    ++this->a, --b, c /= 1, e[2] = 1111;79#endif80  }81};82 83template<typename T>84struct SST {85  T a;86  SST() : a(T()) {87#pragma omp parallel firstprivate(a)88#ifdef LAMBDA89    [&]() {90      [&]() {91        ++this->a;92#pragma omp parallel firstprivate(a)93        ++(this)->a;94      }();95    }();96#elif defined(BLOCKS)97    ^{98      ^{99        ++a;100#pragma omp parallel firstprivate(a)101        ++(this)->a;102      }();103    }();104#else105    ++(this)->a;106#endif107  }108};109 110template <class T>111struct S {112  T f;113  S(T a) : f(a + g) {}114  S() : f(g) {}115  S(const S &s, St t = St()) : f(s.f + t.a) {}116  operator T() { return T(); }117  ~S() {}118};119 120 121template <typename T>122T tmain() {123  S<T> test;124  SST<T> sst;125  T t_var __attribute__((aligned(128))) = T();126  T vec[] __attribute__((aligned(128))) = {1, 2};127  S<T> s_arr[] __attribute__((aligned(128))) = {1, 2};128  S<T> var __attribute__((aligned(128))) (3);129#pragma omp parallel firstprivate(t_var, vec, s_arr, var)130  {131    vec[0] = t_var;132    s_arr[0] = var;133  }134#pragma omp parallel firstprivate(t_var)135  {}136  return T();137}138 139int main() {140  static int sivar;141  SS ss(sivar);142#ifdef LAMBDA143  [&]() {144#pragma omp parallel firstprivate(g, sivar)145  {146 147 148 149    g = 1;150    sivar = 2;151    [&]() {152      g = 2;153      sivar = 4;154    }();155  }156  }();157  return 0;158#elif defined(BLOCKS)159  ^{160#pragma omp parallel firstprivate(g, sivar)161  {162    g = 1;163    sivar = 2;164    ^{165      g = 2;166      sivar = 4;167    }();168  }169  }();170  return 0;171 172 173#else174  S<float> test;175  int t_var = 0;176  int vec[] = {1, 2};177  S<float> s_arr[] = {1, 2};178  S<float> var(3);179#pragma omp parallel firstprivate(t_var, vec, s_arr, var, sivar)180  {181    vec[0] = t_var;182    s_arr[0] = var;183    sivar = 2;184  }185  const int a = 0;186#pragma omp parallel allocate(omp_default_mem_alloc: t_var) firstprivate(t_var, a)187  { t_var = a; }188  return tmain<int>();189#endif190}191 192 193 194 195 196 197 198 199 200 201 202 203 204#endif205#else206 207enum omp_allocator_handle_t {208  omp_null_allocator = 0,209  omp_default_mem_alloc = 1,210  omp_large_cap_mem_alloc = 2,211  omp_const_mem_alloc = 3,212  omp_high_bw_mem_alloc = 4,213  omp_low_lat_mem_alloc = 5,214  omp_cgroup_mem_alloc = 6,215  omp_pteam_mem_alloc = 7,216  omp_thread_mem_alloc = 8,217  KMP_ALLOCATOR_MAX_HANDLE = __UINTPTR_MAX__218};219 220struct St {221  int a, b;222  St() : a(0), b(0) {}223  St(const St &) { }224  ~St() {}225  void St_func(St s[2], int n, long double vla1[n]) {226    double vla2[n][n] __attribute__((aligned(128)));227    a = b;228#pragma omp parallel allocate(omp_thread_mem_alloc:vla2) firstprivate(s, vla1, vla2)229    vla1[b] = vla2[1][n - 1] = a = b;230  }231};232 233void array_func(float a[3], St s[2], int n, long double vla1[n]) {234  double vla2[n][n] __attribute__((aligned(128)));235#pragma omp parallel firstprivate(a, s, vla1, vla2)236  s[0].St_func(s, n, vla1);237  ;238}239 240#endif241 242// CHECK1-LABEL: define {{[^@]+}}@main243// CHECK1-SAME: () #[[ATTR0:[0-9]+]] {244// CHECK1-NEXT:  entry:245// CHECK1-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4246// CHECK1-NEXT:    [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 4247// CHECK1-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4248// CHECK1-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4249// CHECK1-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4250// CHECK1-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4251// CHECK1-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S]], align 4252// CHECK1-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 4253// CHECK1-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i32, align 4254// CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 4255// CHECK1-NEXT:    [[T_VAR_CASTED1:%.*]] = alloca i32, align 4256// CHECK1-NEXT:    store i32 0, ptr [[RETVAL]], align 4257// CHECK1-NEXT:    call void @_ZN2SSC1ERi(ptr nonnull align 4 dereferenceable(28) [[SS]], ptr nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar)258// CHECK1-NEXT:    call void @_ZN1SIfEC1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]])259// CHECK1-NEXT:    store i32 0, ptr [[T_VAR]], align 4260// CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i32 8, i1 false)261// CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) [[S_ARR]], float 1.000000e+00)262// CHECK1-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i32 1263// CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00)264// CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00)265// CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 4266// CHECK1-NEXT:    store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4267// CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4268// CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4269// CHECK1-NEXT:    store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 4270// CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4271// CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 5, ptr @main.omp_outlined, ptr [[VEC]], i32 [[TMP1]], ptr [[S_ARR]], ptr [[VAR]], i32 [[TMP3]])272// CHECK1-NEXT:    store i32 0, ptr [[A]], align 4273// CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[T_VAR]], align 4274// CHECK1-NEXT:    store i32 [[TMP4]], ptr [[T_VAR_CASTED1]], align 4275// CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[T_VAR_CASTED1]], align 4276// CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @main.omp_outlined.1, i32 [[TMP5]])277// CHECK1-NEXT:    [[CALL:%.*]] = call i32 @_Z5tmainIiET_v()278// CHECK1-NEXT:    store i32 [[CALL]], ptr [[RETVAL]], align 4279// CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]]280// CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0281// CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2282// CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]283// CHECK1:       arraydestroy.body:284// CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]285// CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1286// CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]287// CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]288// CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]289// CHECK1:       arraydestroy.done2:290// CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]291// CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[RETVAL]], align 4292// CHECK1-NEXT:    ret i32 [[TMP7]]293//294//295// CHECK1-LABEL: define {{[^@]+}}@_ZN2SSC1ERi296// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(28) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {297// CHECK1-NEXT:  entry:298// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4299// CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4300// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4301// CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4302// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4303// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 4304// CHECK1-NEXT:    call void @_ZN2SSC2ERi(ptr nonnull align 4 dereferenceable(28) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]])305// CHECK1-NEXT:    ret void306//307//308// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev309// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {310// CHECK1-NEXT:  entry:311// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4312// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4313// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4314// CHECK1-NEXT:    call void @_ZN1SIfEC2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]])315// CHECK1-NEXT:    ret void316//317//318// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef319// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {320// CHECK1-NEXT:  entry:321// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4322// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4323// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4324// CHECK1-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4325// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4326// CHECK1-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4327// CHECK1-NEXT:    call void @_ZN1SIfEC2Ef(ptr nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])328// CHECK1-NEXT:    ret void329//330//331// CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined332// CHECK1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], ptr nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] {333// CHECK1-NEXT:  entry:334// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4335// CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4336// CHECK1-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 4337// CHECK1-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 4338// CHECK1-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 4339// CHECK1-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 4340// CHECK1-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i32, align 4341// CHECK1-NEXT:    [[VEC1:%.*]] = alloca [2 x i32], align 4342// CHECK1-NEXT:    [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4343// CHECK1-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4344// CHECK1-NEXT:    [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4345// CHECK1-NEXT:    [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4346// CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4347// CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4348// CHECK1-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 4349// CHECK1-NEXT:    store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4350// CHECK1-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4351// CHECK1-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 4352// CHECK1-NEXT:    store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4353// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META4:![0-9]+]], !align [[META5:![0-9]+]]354// CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META4]], !align [[META5]]355// CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META4]], !align [[META5]]356// CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i32 8, i1 false)357// CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0358// CHECK1-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2359// CHECK1-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]]360// CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]361// CHECK1:       omp.arraycpy.body:362// CHECK1-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]363// CHECK1-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]364// CHECK1-NEXT:    call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]])365// CHECK1-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr [[AGG_TMP]])366// CHECK1-NEXT:    call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]]367// CHECK1-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1368// CHECK1-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1369// CHECK1-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]]370// CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]371// CHECK1:       omp.arraycpy.done3:372// CHECK1-NEXT:    call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]])373// CHECK1-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR4]], ptr nonnull align 4 dereferenceable(4) [[TMP2]], ptr [[AGG_TMP5]])374// CHECK1-NEXT:    call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]]375// CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4376// CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 0377// CHECK1-NEXT:    store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4378// CHECK1-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0379// CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[VAR4]], i32 4, i1 false)380// CHECK1-NEXT:    store i32 2, ptr [[SIVAR_ADDR]], align 4381// CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]]382// CHECK1-NEXT:    [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0383// CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i32 2384// CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]385// CHECK1:       arraydestroy.body:386// CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[OMP_ARRAYCPY_DONE3]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]387// CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1388// CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]389// CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]390// CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]391// CHECK1:       arraydestroy.done8:392// CHECK1-NEXT:    ret void393//394//395// CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev396// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {397// CHECK1-NEXT:  entry:398// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4399// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4400// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4401// CHECK1-NEXT:    call void @_ZN2StC2Ev(ptr nonnull align 4 dereferenceable(8) [[THIS1]])402// CHECK1-NEXT:    ret void403//404//405// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St406// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {407// CHECK1-NEXT:  entry:408// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4409// CHECK1-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4410// CHECK1-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4411// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4412// CHECK1-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4413// CHECK1-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4414// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4415// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4416// CHECK1-NEXT:    call void @_ZN1SIfEC2ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]], ptr [[T]])417// CHECK1-NEXT:    ret void418//419//420// CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev421// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {422// CHECK1-NEXT:  entry:423// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4424// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4425// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4426// CHECK1-NEXT:    call void @_ZN2StD2Ev(ptr nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]]427// CHECK1-NEXT:    ret void428//429//430// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev431// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {432// CHECK1-NEXT:  entry:433// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4434// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4435// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4436// CHECK1-NEXT:    call void @_ZN1SIfED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]437// CHECK1-NEXT:    ret void438//439//440// CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.1441// CHECK1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i32 [[T_VAR:%.*]]) #[[ATTR3]] {442// CHECK1-NEXT:  entry:443// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4444// CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4445// CHECK1-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 4446// CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4447// CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4448// CHECK1-NEXT:    store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4449// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4450// CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4451// CHECK1-NEXT:    [[DOTT_VAR__VOID_ADDR:%.*]] = call ptr @__kmpc_alloc(i32 [[TMP1]], i32 4, ptr inttoptr (i32 1 to ptr))452// CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4453// CHECK1-NEXT:    store i32 [[TMP2]], ptr [[DOTT_VAR__VOID_ADDR]], align 4454// CHECK1-NEXT:    store i32 0, ptr [[DOTT_VAR__VOID_ADDR]], align 4455// CHECK1-NEXT:    call void @__kmpc_free(i32 [[TMP1]], ptr [[DOTT_VAR__VOID_ADDR]], ptr inttoptr (i32 1 to ptr))456// CHECK1-NEXT:    ret void457//458//459// CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v460// CHECK1-SAME: () #[[ATTR1]] comdat {461// CHECK1-NEXT:  entry:462// CHECK1-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4463// CHECK1-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4464// CHECK1-NEXT:    [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4465// CHECK1-NEXT:    [[T_VAR:%.*]] = alloca i32, align 128466// CHECK1-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 128467// CHECK1-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128468// CHECK1-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128469// CHECK1-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 4470// CHECK1-NEXT:    [[T_VAR_CASTED1:%.*]] = alloca i32, align 4471// CHECK1-NEXT:    call void @_ZN1SIiEC1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]])472// CHECK1-NEXT:    call void @_ZN3SSTIiEC1Ev(ptr nonnull align 4 dereferenceable(4) [[SST]])473// CHECK1-NEXT:    store i32 0, ptr [[T_VAR]], align 128474// CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 128 [[VEC]], ptr align 128 @__const._Z5tmainIiET_v.vec, i32 8, i1 false)475// CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[S_ARR]], i32 1)476// CHECK1-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 1477// CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2)478// CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[VAR]], i32 3)479// CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 128480// CHECK1-NEXT:    store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4481// CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4482// CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @_Z5tmainIiET_v.omp_outlined, ptr [[VEC]], i32 [[TMP1]], ptr [[S_ARR]], ptr [[VAR]])483// CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[T_VAR]], align 128484// CHECK1-NEXT:    store i32 [[TMP2]], ptr [[T_VAR_CASTED1]], align 4485// CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[T_VAR_CASTED1]], align 4486// CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @_Z5tmainIiET_v.omp_outlined.2, i32 [[TMP3]])487// CHECK1-NEXT:    store i32 0, ptr [[RETVAL]], align 4488// CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]]489// CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0490// CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2491// CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]492// CHECK1:       arraydestroy.body:493// CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]494// CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1495// CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]496// CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]497// CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]498// CHECK1:       arraydestroy.done2:499// CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]500// CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[RETVAL]], align 4501// CHECK1-NEXT:    ret i32 [[TMP5]]502//503//504// CHECK1-LABEL: define {{[^@]+}}@_ZN2SSC2ERi505// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(28) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {506// CHECK1-NEXT:  entry:507// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4508// CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4509// CHECK1-NEXT:    [[A2:%.*]] = alloca ptr, align 4510// CHECK1-NEXT:    [[B4:%.*]] = alloca i32, align 4511// CHECK1-NEXT:    [[C7:%.*]] = alloca ptr, align 4512// CHECK1-NEXT:    [[E:%.*]] = alloca ptr, align 4513// CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4514// CHECK1-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4515// CHECK1-NEXT:    [[C_CASTED:%.*]] = alloca i32, align 4516// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4517// CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4518// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4519// CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0520// CHECK1-NEXT:    store i32 0, ptr [[A]], align 4521// CHECK1-NEXT:    [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1522// CHECK1-NEXT:    [[BF_LOAD:%.*]] = load i8, ptr [[B]], align 4523// CHECK1-NEXT:    [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16524// CHECK1-NEXT:    [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0525// CHECK1-NEXT:    store i8 [[BF_SET]], ptr [[B]], align 4526// CHECK1-NEXT:    [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2527// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 4, !nonnull [[META4]], !align [[META5]]528// CHECK1-NEXT:    store ptr [[TMP0]], ptr [[C]], align 4529// CHECK1-NEXT:    [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0530// CHECK1-NEXT:    store ptr [[A3]], ptr [[A2]], align 4531// CHECK1-NEXT:    [[B5:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1532// CHECK1-NEXT:    [[BF_LOAD6:%.*]] = load i8, ptr [[B5]], align 4533// CHECK1-NEXT:    [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4534// CHECK1-NEXT:    [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4535// CHECK1-NEXT:    [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32536// CHECK1-NEXT:    store i32 [[BF_CAST]], ptr [[B4]], align 4537// CHECK1-NEXT:    [[C8:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2538// CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[C8]], align 4, !nonnull [[META4]], !align [[META5]]539// CHECK1-NEXT:    store ptr [[TMP1]], ptr [[C7]], align 4540// CHECK1-NEXT:    [[E9:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 3541// CHECK1-NEXT:    store ptr [[E9]], ptr [[E]], align 4542// CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[A2]], align 4, !nonnull [[META4]], !align [[META5]]543// CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4544// CHECK1-NEXT:    store i32 [[TMP3]], ptr [[A_CASTED]], align 4545// CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A_CASTED]], align 4546// CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B4]], align 4547// CHECK1-NEXT:    store i32 [[TMP5]], ptr [[B_CASTED]], align 4548// CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[B_CASTED]], align 4549// CHECK1-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[C7]], align 4, !nonnull [[META4]], !align [[META5]]550// CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4551// CHECK1-NEXT:    store i32 [[TMP8]], ptr [[C_CASTED]], align 4552// CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[C_CASTED]], align 4553// CHECK1-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[E]], align 4, !nonnull [[META4]], !align [[META5]]554// CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @_ZN2SSC2ERi.omp_outlined, ptr [[THIS1]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP9]], ptr [[TMP10]])555// CHECK1-NEXT:    ret void556//557//558// CHECK1-LABEL: define {{[^@]+}}@_ZN2SSC2ERi.omp_outlined559// CHECK1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr [[THIS:%.*]], i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]], ptr nonnull align 4 dereferenceable(16) [[E:%.*]]) #[[ATTR3]] {560// CHECK1-NEXT:  entry:561// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4562// CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4563// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4564// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4565// CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4566// CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca i32, align 4567// CHECK1-NEXT:    [[E_ADDR:%.*]] = alloca ptr, align 4568// CHECK1-NEXT:    [[TMP:%.*]] = alloca ptr, align 4569// CHECK1-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 4570// CHECK1-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 4571// CHECK1-NEXT:    [[E3:%.*]] = alloca [4 x i32], align 4572// CHECK1-NEXT:    [[_TMP4:%.*]] = alloca ptr, align 4573// CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4574// CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4575// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4576// CHECK1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4577// CHECK1-NEXT:    store i32 [[B]], ptr [[B_ADDR]], align 4578// CHECK1-NEXT:    store i32 [[C]], ptr [[C_ADDR]], align 4579// CHECK1-NEXT:    store ptr [[E]], ptr [[E_ADDR]], align 4580// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4581// CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[E_ADDR]], align 4, !nonnull [[META4]], !align [[META5]]582// CHECK1-NEXT:    store ptr [[A_ADDR]], ptr [[TMP]], align 4583// CHECK1-NEXT:    store ptr [[C_ADDR]], ptr [[_TMP1]], align 4584// CHECK1-NEXT:    store ptr [[TMP1]], ptr [[_TMP2]], align 4585// CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META4]], !align [[META5]]586// CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[E3]], ptr align 4 [[TMP2]], i32 16, i1 false)587// CHECK1-NEXT:    store ptr [[E3]], ptr [[_TMP4]], align 4588// CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META4]], !align [[META5]]589// CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4590// CHECK1-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP4]], 1591// CHECK1-NEXT:    store i32 [[INC]], ptr [[TMP3]], align 4592// CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B_ADDR]], align 4593// CHECK1-NEXT:    [[DEC:%.*]] = add nsw i32 [[TMP5]], -1594// CHECK1-NEXT:    store i32 [[DEC]], ptr [[B_ADDR]], align 4595// CHECK1-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 4, !nonnull [[META4]], !align [[META5]]596// CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4597// CHECK1-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP7]], 1598// CHECK1-NEXT:    store i32 [[DIV]], ptr [[TMP6]], align 4599// CHECK1-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[_TMP4]], align 4, !nonnull [[META4]], !align [[META5]]600// CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x i32], ptr [[TMP8]], i32 0, i32 2601// CHECK1-NEXT:    store i32 1111, ptr [[ARRAYIDX]], align 4602// CHECK1-NEXT:    ret void603//604//605// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev606// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {607// CHECK1-NEXT:  entry:608// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4609// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4610// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4611// CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0612// CHECK1-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 128613// CHECK1-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float614// CHECK1-NEXT:    store float [[CONV]], ptr [[F]], align 4615// CHECK1-NEXT:    ret void616//617//618// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef619// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {620// CHECK1-NEXT:  entry:621// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4622// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4623// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4624// CHECK1-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4625// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4626// CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0627// CHECK1-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4628// CHECK1-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 128629// CHECK1-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float630// CHECK1-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]631// CHECK1-NEXT:    store float [[ADD]], ptr [[F]], align 4632// CHECK1-NEXT:    ret void633//634//635// CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev636// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {637// CHECK1-NEXT:  entry:638// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4639// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4640// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4641// CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0642// CHECK1-NEXT:    store i32 0, ptr [[A]], align 4643// CHECK1-NEXT:    [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1644// CHECK1-NEXT:    store i32 0, ptr [[B]], align 4645// CHECK1-NEXT:    ret void646//647//648// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St649// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {650// CHECK1-NEXT:  entry:651// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4652// CHECK1-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4653// CHECK1-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4654// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4655// CHECK1-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4656// CHECK1-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4657// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4658// CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0659// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4, !nonnull [[META4]], !align [[META5]]660// CHECK1-NEXT:    [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0661// CHECK1-NEXT:    [[TMP1:%.*]] = load float, ptr [[F2]], align 4662// CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0663// CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 4664// CHECK1-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP2]] to float665// CHECK1-NEXT:    [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]666// CHECK1-NEXT:    store float [[ADD]], ptr [[F]], align 4667// CHECK1-NEXT:    ret void668//669//670// CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev671// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {672// CHECK1-NEXT:  entry:673// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4674// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4675// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4676// CHECK1-NEXT:    ret void677//678//679// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev680// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {681// CHECK1-NEXT:  entry:682// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4683// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4684// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4685// CHECK1-NEXT:    ret void686//687//688// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev689// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {690// CHECK1-NEXT:  entry:691// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4692// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4693// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4694// CHECK1-NEXT:    call void @_ZN1SIiEC2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]])695// CHECK1-NEXT:    ret void696//697//698// CHECK1-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev699// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {700// CHECK1-NEXT:  entry:701// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4702// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4703// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4704// CHECK1-NEXT:    call void @_ZN3SSTIiEC2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]])705// CHECK1-NEXT:    ret void706//707//708// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei709// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {710// CHECK1-NEXT:  entry:711// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4712// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4713// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4714// CHECK1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4715// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4716// CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4717// CHECK1-NEXT:    call void @_ZN1SIiEC2Ei(ptr nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]])718// CHECK1-NEXT:    ret void719//720//721// CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v.omp_outlined722// CHECK1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], ptr nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {723// CHECK1-NEXT:  entry:724// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4725// CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4726// CHECK1-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 4727// CHECK1-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 4728// CHECK1-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 4729// CHECK1-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 4730// CHECK1-NEXT:    [[VEC1:%.*]] = alloca [2 x i32], align 128731// CHECK1-NEXT:    [[S_ARR2:%.*]] = alloca [2 x %struct.S.0], align 128732// CHECK1-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4733// CHECK1-NEXT:    [[VAR4:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128734// CHECK1-NEXT:    [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4735// CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4736// CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4737// CHECK1-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 4738// CHECK1-NEXT:    store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4739// CHECK1-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4740// CHECK1-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 4741// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META4]], !align [[META5]]742// CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META4]], !align [[META5]]743// CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META4]], !align [[META5]]744// CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 128 [[VEC1]], ptr align 128 [[TMP0]], i32 8, i1 false)745// CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i32 0, i32 0746// CHECK1-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2747// CHECK1-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]]748// CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]749// CHECK1:       omp.arraycpy.body:750// CHECK1-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]751// CHECK1-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]752// CHECK1-NEXT:    call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]])753// CHECK1-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr [[AGG_TMP]])754// CHECK1-NEXT:    call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]]755// CHECK1-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1756// CHECK1-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1757// CHECK1-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]]758// CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]759// CHECK1:       omp.arraycpy.done3:760// CHECK1-NEXT:    call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]])761// CHECK1-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR4]], ptr nonnull align 4 dereferenceable(4) [[TMP2]], ptr [[AGG_TMP5]])762// CHECK1-NEXT:    call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]]763// CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4764// CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 0765// CHECK1-NEXT:    store i32 [[TMP4]], ptr [[ARRAYIDX]], align 128766// CHECK1-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i32 0, i32 0767// CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 128 [[ARRAYIDX6]], ptr align 128 [[VAR4]], i32 4, i1 false)768// CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]]769// CHECK1-NEXT:    [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i32 0, i32 0770// CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i32 2771// CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]772// CHECK1:       arraydestroy.body:773// CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[OMP_ARRAYCPY_DONE3]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]774// CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1775// CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]776// CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]777// CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]778// CHECK1:       arraydestroy.done8:779// CHECK1-NEXT:    ret void780//781//782// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St783// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {784// CHECK1-NEXT:  entry:785// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4786// CHECK1-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4787// CHECK1-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4788// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4789// CHECK1-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4790// CHECK1-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4791// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4792// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4793// CHECK1-NEXT:    call void @_ZN1SIiEC2ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]], ptr [[T]])794// CHECK1-NEXT:    ret void795//796//797// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev798// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {799// CHECK1-NEXT:  entry:800// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4801// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4802// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4803// CHECK1-NEXT:    call void @_ZN1SIiED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]804// CHECK1-NEXT:    ret void805//806//807// CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v.omp_outlined.2808// CHECK1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i32 [[T_VAR:%.*]]) #[[ATTR3]] {809// CHECK1-NEXT:  entry:810// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4811// CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4812// CHECK1-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 4813// CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4814// CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4815// CHECK1-NEXT:    store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4816// CHECK1-NEXT:    ret void817//818//819// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev820// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {821// CHECK1-NEXT:  entry:822// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4823// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4824// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4825// CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0826// CHECK1-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 128827// CHECK1-NEXT:    store i32 [[TMP0]], ptr [[F]], align 4828// CHECK1-NEXT:    ret void829//830//831// CHECK1-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev832// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {833// CHECK1-NEXT:  entry:834// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4835// CHECK1-NEXT:    [[A2:%.*]] = alloca ptr, align 4836// CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4837// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4838// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4839// CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SST:%.*]], ptr [[THIS1]], i32 0, i32 0840// CHECK1-NEXT:    store i32 0, ptr [[A]], align 4841// CHECK1-NEXT:    [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_SST]], ptr [[THIS1]], i32 0, i32 0842// CHECK1-NEXT:    store ptr [[A3]], ptr [[A2]], align 4843// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A2]], align 4, !nonnull [[META4]], !align [[META5]]844// CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4845// CHECK1-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4846// CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4847// CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @_ZN3SSTIiEC2Ev.omp_outlined, ptr [[THIS1]], i32 [[TMP2]])848// CHECK1-NEXT:    ret void849//850//851// CHECK1-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev.omp_outlined852// CHECK1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr [[THIS:%.*]], i32 [[A:%.*]]) #[[ATTR3]] {853// CHECK1-NEXT:  entry:854// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4855// CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4856// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4857// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4858// CHECK1-NEXT:    [[TMP:%.*]] = alloca ptr, align 4859// CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4860// CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4861// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4862// CHECK1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4863// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4864// CHECK1-NEXT:    store ptr [[A_ADDR]], ptr [[TMP]], align 4865// CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META4]], !align [[META5]]866// CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4867// CHECK1-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP2]], 1868// CHECK1-NEXT:    store i32 [[INC]], ptr [[TMP1]], align 4869// CHECK1-NEXT:    ret void870//871//872// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei873// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {874// CHECK1-NEXT:  entry:875// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4876// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4877// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4878// CHECK1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4879// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4880// CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0881// CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4882// CHECK1-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 128883// CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]884// CHECK1-NEXT:    store i32 [[ADD]], ptr [[F]], align 4885// CHECK1-NEXT:    ret void886//887//888// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St889// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {890// CHECK1-NEXT:  entry:891// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4892// CHECK1-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4893// CHECK1-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4894// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4895// CHECK1-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4896// CHECK1-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4897// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4898// CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0899// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4, !nonnull [[META4]], !align [[META5]]900// CHECK1-NEXT:    [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0901// CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[F2]], align 4902// CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0903// CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 4904// CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]905// CHECK1-NEXT:    store i32 [[ADD]], ptr [[F]], align 4906// CHECK1-NEXT:    ret void907//908//909// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev910// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {911// CHECK1-NEXT:  entry:912// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4913// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4914// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4915// CHECK1-NEXT:    ret void916//917//918// CHECK3-LABEL: define {{[^@]+}}@main919// CHECK3-SAME: () #[[ATTR0:[0-9]+]] {920// CHECK3-NEXT:  entry:921// CHECK3-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4922// CHECK3-NEXT:    [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 4923// CHECK3-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4924// CHECK3-NEXT:    store i32 0, ptr [[RETVAL]], align 4925// CHECK3-NEXT:    call void @_ZN2SSC1ERi(ptr nonnull align 4 dereferenceable(28) [[SS]], ptr nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar)926// CHECK3-NEXT:    [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0927// CHECK3-NEXT:    store ptr @_ZZ4mainE5sivar, ptr [[TMP0]], align 4928// CHECK3-NEXT:    call void @"_ZZ4mainENK3$_0clEv"(ptr nonnull align 4 dereferenceable(4) [[REF_TMP]])929// CHECK3-NEXT:    ret i32 0930//931//932// CHECK3-LABEL: define {{[^@]+}}@_ZN2SSC1ERi933// CHECK3-SAME: (ptr nonnull align 4 dereferenceable(28) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {934// CHECK3-NEXT:  entry:935// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4936// CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4937// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4938// CHECK3-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4939// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4940// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 4941// CHECK3-NEXT:    call void @_ZN2SSC2ERi(ptr nonnull align 4 dereferenceable(28) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]])942// CHECK3-NEXT:    ret void943//944//945// CHECK3-LABEL: define {{[^@]+}}@_ZN2SSC2ERi946// CHECK3-SAME: (ptr nonnull align 4 dereferenceable(28) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {947// CHECK3-NEXT:  entry:948// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4949// CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4950// CHECK3-NEXT:    [[A2:%.*]] = alloca ptr, align 4951// CHECK3-NEXT:    [[B4:%.*]] = alloca i32, align 4952// CHECK3-NEXT:    [[C7:%.*]] = alloca ptr, align 4953// CHECK3-NEXT:    [[E:%.*]] = alloca ptr, align 4954// CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4955// CHECK3-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4956// CHECK3-NEXT:    [[C_CASTED:%.*]] = alloca i32, align 4957// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4958// CHECK3-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4959// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4960// CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0961// CHECK3-NEXT:    store i32 0, ptr [[A]], align 4962// CHECK3-NEXT:    [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1963// CHECK3-NEXT:    [[BF_LOAD:%.*]] = load i8, ptr [[B]], align 4964// CHECK3-NEXT:    [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16965// CHECK3-NEXT:    [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0966// CHECK3-NEXT:    store i8 [[BF_SET]], ptr [[B]], align 4967// CHECK3-NEXT:    [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2968// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 4, !nonnull [[META4:![0-9]+]], !align [[META5:![0-9]+]]969// CHECK3-NEXT:    store ptr [[TMP0]], ptr [[C]], align 4970// CHECK3-NEXT:    [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0971// CHECK3-NEXT:    store ptr [[A3]], ptr [[A2]], align 4972// CHECK3-NEXT:    [[B5:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1973// CHECK3-NEXT:    [[BF_LOAD6:%.*]] = load i8, ptr [[B5]], align 4974// CHECK3-NEXT:    [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4975// CHECK3-NEXT:    [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4976// CHECK3-NEXT:    [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32977// CHECK3-NEXT:    store i32 [[BF_CAST]], ptr [[B4]], align 4978// CHECK3-NEXT:    [[C8:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2979// CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[C8]], align 4, !nonnull [[META4]], !align [[META5]]980// CHECK3-NEXT:    store ptr [[TMP1]], ptr [[C7]], align 4981// CHECK3-NEXT:    [[E9:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 3982// CHECK3-NEXT:    store ptr [[E9]], ptr [[E]], align 4983// CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[A2]], align 4, !nonnull [[META4]], !align [[META5]]984// CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4985// CHECK3-NEXT:    store i32 [[TMP3]], ptr [[A_CASTED]], align 4986// CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A_CASTED]], align 4987// CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B4]], align 4988// CHECK3-NEXT:    store i32 [[TMP5]], ptr [[B_CASTED]], align 4989// CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[B_CASTED]], align 4990// CHECK3-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[C7]], align 4, !nonnull [[META4]], !align [[META5]]991// CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4992// CHECK3-NEXT:    store i32 [[TMP8]], ptr [[C_CASTED]], align 4993// CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[C_CASTED]], align 4994// CHECK3-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[E]], align 4, !nonnull [[META4]], !align [[META5]]995// CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 5, ptr @_ZN2SSC2ERi.omp_outlined, ptr [[THIS1]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP9]], ptr [[TMP10]])996// CHECK3-NEXT:    ret void997//998//999// CHECK3-LABEL: define {{[^@]+}}@_ZN2SSC2ERi.omp_outlined1000// CHECK3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr [[THIS:%.*]], i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]], ptr nonnull align 4 dereferenceable(16) [[E:%.*]]) #[[ATTR2:[0-9]+]] {1001// CHECK3-NEXT:  entry:1002// CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 41003// CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 41004// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41005// CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 41006// CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 41007// CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca i32, align 41008// CHECK3-NEXT:    [[E_ADDR:%.*]] = alloca ptr, align 41009// CHECK3-NEXT:    [[TMP:%.*]] = alloca ptr, align 41010// CHECK3-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 41011// CHECK3-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 41012// CHECK3-NEXT:    [[E3:%.*]] = alloca [4 x i32], align 41013// CHECK3-NEXT:    [[_TMP4:%.*]] = alloca ptr, align 41014// CHECK3-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 41015// CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 41016// CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 41017// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41018// CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 41019// CHECK3-NEXT:    store i32 [[B]], ptr [[B_ADDR]], align 41020// CHECK3-NEXT:    store i32 [[C]], ptr [[C_ADDR]], align 41021// CHECK3-NEXT:    store ptr [[E]], ptr [[E_ADDR]], align 41022// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41023// CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[E_ADDR]], align 4, !nonnull [[META4]], !align [[META5]]1024// CHECK3-NEXT:    store ptr [[A_ADDR]], ptr [[TMP]], align 41025// CHECK3-NEXT:    store ptr [[C_ADDR]], ptr [[_TMP1]], align 41026// CHECK3-NEXT:    store ptr [[TMP1]], ptr [[_TMP2]], align 41027// CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META4]], !align [[META5]]1028// CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[E3]], ptr align 4 [[TMP2]], i32 16, i1 false)1029// CHECK3-NEXT:    store ptr [[E3]], ptr [[_TMP4]], align 41030// CHECK3-NEXT:    [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 01031// CHECK3-NEXT:    store ptr [[TMP0]], ptr [[TMP3]], align 41032// CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 11033// CHECK3-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META4]], !align [[META5]]1034// CHECK3-NEXT:    store ptr [[TMP5]], ptr [[TMP4]], align 41035// CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 21036// CHECK3-NEXT:    store ptr [[B_ADDR]], ptr [[TMP6]], align 41037// CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 31038// CHECK3-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 4, !nonnull [[META4]], !align [[META5]]1039// CHECK3-NEXT:    store ptr [[TMP8]], ptr [[TMP7]], align 41040// CHECK3-NEXT:    call void @_ZZN2SSC1ERiENKUlvE_clEv(ptr nonnull align 4 dereferenceable(16) [[REF_TMP]])1041// CHECK3-NEXT:    ret void1042//1043//1044// CHECK3-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv1045// CHECK3-SAME: (ptr nonnull align 4 dereferenceable(16) [[THIS:%.*]]) #[[ATTR1]] align 2 {1046// CHECK3-NEXT:  entry:1047// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41048// CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 41049// CHECK3-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 41050// CHECK3-NEXT:    [[C_CASTED:%.*]] = alloca i32, align 41051// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41052// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41053// CHECK3-NEXT:    [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0:%.*]], ptr [[THIS1]], i32 0, i32 01054// CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 41055// CHECK3-NEXT:    [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 11056// CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4, !nonnull [[META4]], !align [[META5]]1057// CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 41058// CHECK3-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP4]], 11059// CHECK3-NEXT:    store i32 [[INC]], ptr [[TMP3]], align 41060// CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 21061// CHECK3-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 4, !nonnull [[META4]], !align [[META5]]1062// CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 41063// CHECK3-NEXT:    [[DEC:%.*]] = add nsw i32 [[TMP7]], -11064// CHECK3-NEXT:    store i32 [[DEC]], ptr [[TMP6]], align 41065// CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 31066// CHECK3-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 4, !nonnull [[META4]], !align [[META5]]1067// CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 41068// CHECK3-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP10]], 11069// CHECK3-NEXT:    store i32 [[DIV]], ptr [[TMP9]], align 41070// CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 11071// CHECK3-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 4, !nonnull [[META4]], !align [[META5]]1072// CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 41073// CHECK3-NEXT:    store i32 [[TMP13]], ptr [[A_CASTED]], align 41074// CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[A_CASTED]], align 41075// CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 21076// CHECK3-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 4, !nonnull [[META4]], !align [[META5]]1077// CHECK3-NEXT:    [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 41078// CHECK3-NEXT:    store i32 [[TMP17]], ptr [[B_CASTED]], align 41079// CHECK3-NEXT:    [[TMP18:%.*]] = load i32, ptr [[B_CASTED]], align 41080// CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 31081// CHECK3-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 4, !nonnull [[META4]], !align [[META5]]1082// CHECK3-NEXT:    [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 41083// CHECK3-NEXT:    store i32 [[TMP21]], ptr [[C_CASTED]], align 41084// CHECK3-NEXT:    [[TMP22:%.*]] = load i32, ptr [[C_CASTED]], align 41085// CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined, ptr [[TMP1]], i32 [[TMP14]], i32 [[TMP18]], i32 [[TMP22]])1086// CHECK3-NEXT:    ret void1087//1088//1089// CHECK3-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined1090// CHECK3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr [[THIS:%.*]], i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]]) #[[ATTR2]] {1091// CHECK3-NEXT:  entry:1092// CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 41093// CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 41094// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41095// CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 41096// CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 41097// CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca i32, align 41098// CHECK3-NEXT:    [[TMP:%.*]] = alloca ptr, align 41099// CHECK3-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 41100// CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 41101// CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 41102// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41103// CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 41104// CHECK3-NEXT:    store i32 [[B]], ptr [[B_ADDR]], align 41105// CHECK3-NEXT:    store i32 [[C]], ptr [[C_ADDR]], align 41106// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41107// CHECK3-NEXT:    store ptr [[A_ADDR]], ptr [[TMP]], align 41108// CHECK3-NEXT:    store ptr [[C_ADDR]], ptr [[_TMP1]], align 41109// CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META4]], !align [[META5]]1110// CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 41111// CHECK3-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP2]], 11112// CHECK3-NEXT:    store i32 [[INC]], ptr [[TMP1]], align 41113// CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[B_ADDR]], align 41114// CHECK3-NEXT:    [[DEC:%.*]] = add nsw i32 [[TMP3]], -11115// CHECK3-NEXT:    store i32 [[DEC]], ptr [[B_ADDR]], align 41116// CHECK3-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[_TMP1]], align 4, !nonnull [[META4]], !align [[META5]]1117// CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 41118// CHECK3-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP5]], 11119// CHECK3-NEXT:    store i32 [[DIV]], ptr [[TMP4]], align 41120// CHECK3-NEXT:    ret void1121//1122//1123// CHECK4-LABEL: define {{[^@]+}}@main1124// CHECK4-SAME: () #[[ATTR0:[0-9]+]] {1125// CHECK4-NEXT:  entry:1126// CHECK4-NEXT:    [[RETVAL:%.*]] = alloca i32, align 41127// CHECK4-NEXT:    [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 41128// CHECK4-NEXT:    [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, i32 }>, align 41129// CHECK4-NEXT:    store i32 0, ptr [[RETVAL]], align 41130// CHECK4-NEXT:    call void @_ZN2SSC1ERi(ptr nonnull align 4 dereferenceable(28) [[SS]], ptr nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar)1131// CHECK4-NEXT:    [[BLOCK_ISA:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 01132// CHECK4-NEXT:    store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 41133// CHECK4-NEXT:    [[BLOCK_FLAGS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 11134// CHECK4-NEXT:    store i32 1073741824, ptr [[BLOCK_FLAGS]], align 41135// CHECK4-NEXT:    [[BLOCK_RESERVED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 21136// CHECK4-NEXT:    store i32 0, ptr [[BLOCK_RESERVED]], align 41137// CHECK4-NEXT:    [[BLOCK_INVOKE:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 31138// CHECK4-NEXT:    store ptr @__main_block_invoke, ptr [[BLOCK_INVOKE]], align 41139// CHECK4-NEXT:    [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 41140// CHECK4-NEXT:    store ptr @__block_descriptor_tmp.1, ptr [[BLOCK_DESCRIPTOR]], align 41141// CHECK4-NEXT:    [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 51142// CHECK4-NEXT:    [[TMP0:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 41143// CHECK4-NEXT:    store i32 [[TMP0]], ptr [[BLOCK_CAPTURED]], align 41144// CHECK4-NEXT:    [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 31145// CHECK4-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 41146// CHECK4-NEXT:    call void [[TMP2]](ptr [[BLOCK]])1147// CHECK4-NEXT:    ret i32 01148//1149//1150// CHECK4-LABEL: define {{[^@]+}}@_ZN2SSC1ERi1151// CHECK4-SAME: (ptr nonnull align 4 dereferenceable(28) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {1152// CHECK4-NEXT:  entry:1153// CHECK4-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41154// CHECK4-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 41155// CHECK4-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41156// CHECK4-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 41157// CHECK4-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41158// CHECK4-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 41159// CHECK4-NEXT:    call void @_ZN2SSC2ERi(ptr nonnull align 4 dereferenceable(28) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]])1160// CHECK4-NEXT:    ret void1161//1162//1163// CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke1164// CHECK4-SAME: (ptr [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] {1165// CHECK4-NEXT:  entry:1166// CHECK4-NEXT:    [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 41167// CHECK4-NEXT:    [[BLOCK_ADDR:%.*]] = alloca ptr, align 41168// CHECK4-NEXT:    [[G_CASTED:%.*]] = alloca i32, align 41169// CHECK4-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i32, align 41170// CHECK4-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 41171// CHECK4-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 41172// CHECK4-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 1281173// CHECK4-NEXT:    store i32 [[TMP0]], ptr [[G_CASTED]], align 41174// CHECK4-NEXT:    [[TMP1:%.*]] = load i32, ptr [[G_CASTED]], align 41175// CHECK4-NEXT:    [[TMP2:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 41176// CHECK4-NEXT:    store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 41177// CHECK4-NEXT:    [[TMP3:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 41178// CHECK4-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 2, ptr @__main_block_invoke.omp_outlined, i32 [[TMP1]], i32 [[TMP3]])1179// CHECK4-NEXT:    ret void1180//1181//1182// CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke.omp_outlined1183// CHECK4-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i32 [[G:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] {1184// CHECK4-NEXT:  entry:1185// CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 41186// CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 41187// CHECK4-NEXT:    [[G_ADDR:%.*]] = alloca i32, align 41188// CHECK4-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i32, align 41189// CHECK4-NEXT:    [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, i32, [104 x i8], i32 }>, align 1281190// CHECK4-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 41191// CHECK4-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 41192// CHECK4-NEXT:    store i32 [[G]], ptr [[G_ADDR]], align 41193// CHECK4-NEXT:    store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 41194// CHECK4-NEXT:    store i32 1, ptr [[G_ADDR]], align 41195// CHECK4-NEXT:    store i32 2, ptr [[SIVAR_ADDR]], align 41196// CHECK4-NEXT:    [[BLOCK_ISA:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [104 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 01197// CHECK4-NEXT:    store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 1281198// CHECK4-NEXT:    [[BLOCK_FLAGS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [104 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 11199// CHECK4-NEXT:    store i32 1073741824, ptr [[BLOCK_FLAGS]], align 41200// CHECK4-NEXT:    [[BLOCK_RESERVED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [104 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 21201// CHECK4-NEXT:    store i32 0, ptr [[BLOCK_RESERVED]], align 81202// CHECK4-NEXT:    [[BLOCK_INVOKE:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [104 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 31203// CHECK4-NEXT:    store ptr @g_block_invoke, ptr [[BLOCK_INVOKE]], align 41204// CHECK4-NEXT:    [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [104 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 41205// CHECK4-NEXT:    store ptr @__block_descriptor_tmp, ptr [[BLOCK_DESCRIPTOR]], align 161206// CHECK4-NEXT:    [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [104 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 71207// CHECK4-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr [[G_ADDR]], align 41208// CHECK4-NEXT:    store volatile i32 [[TMP0]], ptr [[BLOCK_CAPTURED]], align 1281209// CHECK4-NEXT:    [[BLOCK_CAPTURED1:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [104 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 51210// CHECK4-NEXT:    [[TMP1:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 41211// CHECK4-NEXT:    store i32 [[TMP1]], ptr [[BLOCK_CAPTURED1]], align 41212// CHECK4-NEXT:    [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 31213// CHECK4-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 41214// CHECK4-NEXT:    call void [[TMP3]](ptr [[BLOCK]])1215// CHECK4-NEXT:    ret void1216//1217//1218// CHECK4-LABEL: define {{[^@]+}}@g_block_invoke1219// CHECK4-SAME: (ptr [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] {1220// CHECK4-NEXT:  entry:1221// CHECK4-NEXT:    [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 41222// CHECK4-NEXT:    [[BLOCK_ADDR:%.*]] = alloca ptr, align 41223// CHECK4-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 41224// CHECK4-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 41225// CHECK4-NEXT:    [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [104 x i8], i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 71226// CHECK4-NEXT:    store i32 2, ptr [[BLOCK_CAPTURE_ADDR]], align 1281227// CHECK4-NEXT:    [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [104 x i8], i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 51228// CHECK4-NEXT:    store i32 4, ptr [[BLOCK_CAPTURE_ADDR1]], align 41229// CHECK4-NEXT:    ret void1230//1231//1232// CHECK4-LABEL: define {{[^@]+}}@_ZN2SSC2ERi1233// CHECK4-SAME: (ptr nonnull align 4 dereferenceable(28) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1234// CHECK4-NEXT:  entry:1235// CHECK4-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41236// CHECK4-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 41237// CHECK4-NEXT:    [[A2:%.*]] = alloca ptr, align 41238// CHECK4-NEXT:    [[B4:%.*]] = alloca i32, align 41239// CHECK4-NEXT:    [[C7:%.*]] = alloca ptr, align 41240// CHECK4-NEXT:    [[E:%.*]] = alloca ptr, align 41241// CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 41242// CHECK4-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 41243// CHECK4-NEXT:    [[C_CASTED:%.*]] = alloca i32, align 41244// CHECK4-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41245// CHECK4-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 41246// CHECK4-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41247// CHECK4-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 01248// CHECK4-NEXT:    store i32 0, ptr [[A]], align 41249// CHECK4-NEXT:    [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 11250// CHECK4-NEXT:    [[BF_LOAD:%.*]] = load i8, ptr [[B]], align 41251// CHECK4-NEXT:    [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -161252// CHECK4-NEXT:    [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 01253// CHECK4-NEXT:    store i8 [[BF_SET]], ptr [[B]], align 41254// CHECK4-NEXT:    [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 21255// CHECK4-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 4, !nonnull [[META6:![0-9]+]], !align [[META7:![0-9]+]]1256// CHECK4-NEXT:    store ptr [[TMP0]], ptr [[C]], align 41257// CHECK4-NEXT:    [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 01258// CHECK4-NEXT:    store ptr [[A3]], ptr [[A2]], align 41259// CHECK4-NEXT:    [[B5:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 11260// CHECK4-NEXT:    [[BF_LOAD6:%.*]] = load i8, ptr [[B5]], align 41261// CHECK4-NEXT:    [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 41262// CHECK4-NEXT:    [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 41263// CHECK4-NEXT:    [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i321264// CHECK4-NEXT:    store i32 [[BF_CAST]], ptr [[B4]], align 41265// CHECK4-NEXT:    [[C8:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 21266// CHECK4-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[C8]], align 4, !nonnull [[META6]], !align [[META7]]1267// CHECK4-NEXT:    store ptr [[TMP1]], ptr [[C7]], align 41268// CHECK4-NEXT:    [[E9:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 31269// CHECK4-NEXT:    store ptr [[E9]], ptr [[E]], align 41270// CHECK4-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[A2]], align 4, !nonnull [[META6]], !align [[META7]]1271// CHECK4-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 41272// CHECK4-NEXT:    store i32 [[TMP3]], ptr [[A_CASTED]], align 41273// CHECK4-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A_CASTED]], align 41274// CHECK4-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B4]], align 41275// CHECK4-NEXT:    store i32 [[TMP5]], ptr [[B_CASTED]], align 41276// CHECK4-NEXT:    [[TMP6:%.*]] = load i32, ptr [[B_CASTED]], align 41277// CHECK4-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[C7]], align 4, !nonnull [[META6]], !align [[META7]]1278// CHECK4-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 41279// CHECK4-NEXT:    store i32 [[TMP8]], ptr [[C_CASTED]], align 41280// CHECK4-NEXT:    [[TMP9:%.*]] = load i32, ptr [[C_CASTED]], align 41281// CHECK4-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[E]], align 4, !nonnull [[META6]], !align [[META7]]1282// CHECK4-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @_ZN2SSC2ERi.omp_outlined, ptr [[THIS1]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP9]], ptr [[TMP10]])1283// CHECK4-NEXT:    ret void1284//1285//1286// CHECK4-LABEL: define {{[^@]+}}@_ZN2SSC2ERi.omp_outlined1287// CHECK4-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr [[THIS:%.*]], i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]], ptr nonnull align 4 dereferenceable(16) [[E:%.*]]) #[[ATTR3]] {1288// CHECK4-NEXT:  entry:1289// CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 41290// CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 41291// CHECK4-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41292// CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 41293// CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 41294// CHECK4-NEXT:    [[C_ADDR:%.*]] = alloca i32, align 41295// CHECK4-NEXT:    [[E_ADDR:%.*]] = alloca ptr, align 41296// CHECK4-NEXT:    [[TMP:%.*]] = alloca ptr, align 41297// CHECK4-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 41298// CHECK4-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 41299// CHECK4-NEXT:    [[E3:%.*]] = alloca [4 x i32], align 41300// CHECK4-NEXT:    [[_TMP4:%.*]] = alloca ptr, align 41301// CHECK4-NEXT:    [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, align 41302// CHECK4-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 41303// CHECK4-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 41304// CHECK4-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41305// CHECK4-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 41306// CHECK4-NEXT:    store i32 [[B]], ptr [[B_ADDR]], align 41307// CHECK4-NEXT:    store i32 [[C]], ptr [[C_ADDR]], align 41308// CHECK4-NEXT:    store ptr [[E]], ptr [[E_ADDR]], align 41309// CHECK4-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41310// CHECK4-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[E_ADDR]], align 4, !nonnull [[META6]], !align [[META7]]1311// CHECK4-NEXT:    store ptr [[A_ADDR]], ptr [[TMP]], align 41312// CHECK4-NEXT:    store ptr [[C_ADDR]], ptr [[_TMP1]], align 41313// CHECK4-NEXT:    store ptr [[TMP1]], ptr [[_TMP2]], align 41314// CHECK4-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META6]], !align [[META7]]1315// CHECK4-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[E3]], ptr align 4 [[TMP2]], i32 16, i1 false)1316// CHECK4-NEXT:    store ptr [[E3]], ptr [[_TMP4]], align 41317// CHECK4-NEXT:    [[BLOCK_ISA:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[BLOCK]], i32 0, i32 01318// CHECK4-NEXT:    store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 41319// CHECK4-NEXT:    [[BLOCK_FLAGS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[BLOCK]], i32 0, i32 11320// CHECK4-NEXT:    store i32 1073741824, ptr [[BLOCK_FLAGS]], align 41321// CHECK4-NEXT:    [[BLOCK_RESERVED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[BLOCK]], i32 0, i32 21322// CHECK4-NEXT:    store i32 0, ptr [[BLOCK_RESERVED]], align 41323// CHECK4-NEXT:    [[BLOCK_INVOKE:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[BLOCK]], i32 0, i32 31324// CHECK4-NEXT:    store ptr @g_block_invoke_2, ptr [[BLOCK_INVOKE]], align 41325// CHECK4-NEXT:    [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[BLOCK]], i32 0, i32 41326// CHECK4-NEXT:    store ptr @__block_descriptor_tmp.2, ptr [[BLOCK_DESCRIPTOR]], align 41327// CHECK4-NEXT:    [[BLOCK_CAPTURED_THIS_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[BLOCK]], i32 0, i32 51328// CHECK4-NEXT:    store ptr [[TMP0]], ptr [[BLOCK_CAPTURED_THIS_ADDR]], align 41329// CHECK4-NEXT:    [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[BLOCK]], i32 0, i32 61330// CHECK4-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META6]], !align [[META7]]1331// CHECK4-NEXT:    store ptr [[TMP3]], ptr [[BLOCK_CAPTURED]], align 41332// CHECK4-NEXT:    [[BLOCK_CAPTURED5:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[BLOCK]], i32 0, i32 71333// CHECK4-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 41334// CHECK4-NEXT:    store i32 [[TMP4]], ptr [[BLOCK_CAPTURED5]], align 41335// CHECK4-NEXT:    [[BLOCK_CAPTURED6:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[BLOCK]], i32 0, i32 81336// CHECK4-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 4, !nonnull [[META6]], !align [[META7]]1337// CHECK4-NEXT:    store ptr [[TMP5]], ptr [[BLOCK_CAPTURED6]], align 41338// CHECK4-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 31339// CHECK4-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 41340// CHECK4-NEXT:    call void [[TMP7]](ptr [[BLOCK]])1341// CHECK4-NEXT:    ret void1342//1343//1344// CHECK4-LABEL: define {{[^@]+}}@g_block_invoke_21345// CHECK4-SAME: (ptr [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] {1346// CHECK4-NEXT:  entry:1347// CHECK4-NEXT:    [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 41348// CHECK4-NEXT:    [[BLOCK_ADDR:%.*]] = alloca ptr, align 41349// CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 41350// CHECK4-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 41351// CHECK4-NEXT:    [[C_CASTED:%.*]] = alloca i32, align 41352// CHECK4-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 41353// CHECK4-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 41354// CHECK4-NEXT:    [[BLOCK_CAPTURED_THIS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 51355// CHECK4-NEXT:    [[THIS:%.*]] = load ptr, ptr [[BLOCK_CAPTURED_THIS]], align 41356// CHECK4-NEXT:    [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 61357// CHECK4-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR]], align 4, !nonnull [[META6]], !align [[META7]]1358// CHECK4-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 41359// CHECK4-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP1]], 11360// CHECK4-NEXT:    store i32 [[INC]], ptr [[TMP0]], align 41361// CHECK4-NEXT:    [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 71362// CHECK4-NEXT:    [[TMP2:%.*]] = load i32, ptr [[BLOCK_CAPTURE_ADDR1]], align 41363// CHECK4-NEXT:    [[DEC:%.*]] = add nsw i32 [[TMP2]], -11364// CHECK4-NEXT:    store i32 [[DEC]], ptr [[BLOCK_CAPTURE_ADDR1]], align 41365// CHECK4-NEXT:    [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 81366// CHECK4-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR2]], align 4, !nonnull [[META6]], !align [[META7]]1367// CHECK4-NEXT:    [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 41368// CHECK4-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP4]], 11369// CHECK4-NEXT:    store i32 [[DIV]], ptr [[TMP3]], align 41370// CHECK4-NEXT:    [[BLOCK_CAPTURE_ADDR3:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 61371// CHECK4-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR3]], align 4, !nonnull [[META6]], !align [[META7]]1372// CHECK4-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 41373// CHECK4-NEXT:    store i32 [[TMP6]], ptr [[A_CASTED]], align 41374// CHECK4-NEXT:    [[TMP7:%.*]] = load i32, ptr [[A_CASTED]], align 41375// CHECK4-NEXT:    [[BLOCK_CAPTURE_ADDR4:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 71376// CHECK4-NEXT:    [[TMP8:%.*]] = load i32, ptr [[BLOCK_CAPTURE_ADDR4]], align 41377// CHECK4-NEXT:    store i32 [[TMP8]], ptr [[B_CASTED]], align 41378// CHECK4-NEXT:    [[TMP9:%.*]] = load i32, ptr [[B_CASTED]], align 41379// CHECK4-NEXT:    [[BLOCK_CAPTURE_ADDR5:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 81380// CHECK4-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR5]], align 4, !nonnull [[META6]], !align [[META7]]1381// CHECK4-NEXT:    [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 41382// CHECK4-NEXT:    store i32 [[TMP11]], ptr [[C_CASTED]], align 41383// CHECK4-NEXT:    [[TMP12:%.*]] = load i32, ptr [[C_CASTED]], align 41384// CHECK4-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @g_block_invoke_2.omp_outlined, ptr [[THIS]], i32 [[TMP7]], i32 [[TMP9]], i32 [[TMP12]])1385// CHECK4-NEXT:    ret void1386//1387//1388// CHECK4-LABEL: define {{[^@]+}}@g_block_invoke_2.omp_outlined1389// CHECK4-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr [[THIS:%.*]], i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]]) #[[ATTR3]] {1390// CHECK4-NEXT:  entry:1391// CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 41392// CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 41393// CHECK4-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41394// CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 41395// CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 41396// CHECK4-NEXT:    [[C_ADDR:%.*]] = alloca i32, align 41397// CHECK4-NEXT:    [[TMP:%.*]] = alloca ptr, align 41398// CHECK4-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 41399// CHECK4-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 41400// CHECK4-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 41401// CHECK4-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41402// CHECK4-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 41403// CHECK4-NEXT:    store i32 [[B]], ptr [[B_ADDR]], align 41404// CHECK4-NEXT:    store i32 [[C]], ptr [[C_ADDR]], align 41405// CHECK4-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41406// CHECK4-NEXT:    store ptr [[A_ADDR]], ptr [[TMP]], align 41407// CHECK4-NEXT:    store ptr [[C_ADDR]], ptr [[_TMP1]], align 41408// CHECK4-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META6]], !align [[META7]]1409// CHECK4-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 41410// CHECK4-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP2]], 11411// CHECK4-NEXT:    store i32 [[INC]], ptr [[TMP1]], align 41412// CHECK4-NEXT:    [[TMP3:%.*]] = load i32, ptr [[B_ADDR]], align 41413// CHECK4-NEXT:    [[DEC:%.*]] = add nsw i32 [[TMP3]], -11414// CHECK4-NEXT:    store i32 [[DEC]], ptr [[B_ADDR]], align 41415// CHECK4-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[_TMP1]], align 4, !nonnull [[META6]], !align [[META7]]1416// CHECK4-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 41417// CHECK4-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP5]], 11418// CHECK4-NEXT:    store i32 [[DIV]], ptr [[TMP4]], align 41419// CHECK4-NEXT:    ret void1420//1421//1422// CHECK9-LABEL: define {{[^@]+}}@main1423// CHECK9-SAME: () #[[ATTR0:[0-9]+]] {1424// CHECK9-NEXT:  entry:1425// CHECK9-NEXT:    [[RETVAL:%.*]] = alloca i32, align 41426// CHECK9-NEXT:    [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 81427// CHECK9-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 41428// CHECK9-NEXT:    [[T_VAR:%.*]] = alloca i32, align 41429// CHECK9-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 41430// CHECK9-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S], align 41431// CHECK9-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S]], align 41432// CHECK9-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 81433// CHECK9-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i64, align 81434// CHECK9-NEXT:    [[A:%.*]] = alloca i32, align 41435// CHECK9-NEXT:    [[T_VAR_CASTED1:%.*]] = alloca i64, align 81436// CHECK9-NEXT:    store i32 0, ptr [[RETVAL]], align 41437// CHECK9-NEXT:    call void @_ZN2SSC1ERi(ptr nonnull align 8 dereferenceable(32) [[SS]], ptr nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar)1438// CHECK9-NEXT:    call void @_ZN1SIfEC1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]])1439// CHECK9-NEXT:    store i32 0, ptr [[T_VAR]], align 41440// CHECK9-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i64 8, i1 false)1441// CHECK9-NEXT:    call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) [[S_ARR]], float 1.000000e+00)1442// CHECK9-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i64 11443// CHECK9-NEXT:    call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00)1444// CHECK9-NEXT:    call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00)1445// CHECK9-NEXT:    [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 41446// CHECK9-NEXT:    store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 41447// CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 81448// CHECK9-NEXT:    [[TMP2:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 41449// CHECK9-NEXT:    store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 41450// CHECK9-NEXT:    [[TMP3:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 81451// CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 5, ptr @main.omp_outlined, ptr [[VEC]], i64 [[TMP1]], ptr [[S_ARR]], ptr [[VAR]], i64 [[TMP3]])1452// CHECK9-NEXT:    store i32 0, ptr [[A]], align 41453// CHECK9-NEXT:    [[TMP4:%.*]] = load i32, ptr [[T_VAR]], align 41454// CHECK9-NEXT:    store i32 [[TMP4]], ptr [[T_VAR_CASTED1]], align 41455// CHECK9-NEXT:    [[TMP5:%.*]] = load i64, ptr [[T_VAR_CASTED1]], align 81456// CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @main.omp_outlined.1, i64 [[TMP5]])1457// CHECK9-NEXT:    [[CALL:%.*]] = call i32 @_Z5tmainIiET_v()1458// CHECK9-NEXT:    store i32 [[CALL]], ptr [[RETVAL]], align 41459// CHECK9-NEXT:    call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]]1460// CHECK9-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 01461// CHECK9-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 21462// CHECK9-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]1463// CHECK9:       arraydestroy.body:1464// CHECK9-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1465// CHECK9-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -11466// CHECK9-NEXT:    call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]1467// CHECK9-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]1468// CHECK9-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]1469// CHECK9:       arraydestroy.done2:1470// CHECK9-NEXT:    call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]1471// CHECK9-NEXT:    [[TMP7:%.*]] = load i32, ptr [[RETVAL]], align 41472// CHECK9-NEXT:    ret i32 [[TMP7]]1473//1474//1475// CHECK9-LABEL: define {{[^@]+}}@_ZN2SSC1ERi1476// CHECK9-SAME: (ptr nonnull align 8 dereferenceable(32) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {1477// CHECK9-NEXT:  entry:1478// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81479// CHECK9-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 81480// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81481// CHECK9-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 81482// CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81483// CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 81484// CHECK9-NEXT:    call void @_ZN2SSC2ERi(ptr nonnull align 8 dereferenceable(32) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]])1485// CHECK9-NEXT:    ret void1486//1487//1488// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev1489// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1490// CHECK9-NEXT:  entry:1491// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81492// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81493// CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81494// CHECK9-NEXT:    call void @_ZN1SIfEC2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]])1495// CHECK9-NEXT:    ret void1496//1497//1498// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef1499// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1500// CHECK9-NEXT:  entry:1501// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81502// CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca float, align 41503// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81504// CHECK9-NEXT:    store float [[A]], ptr [[A_ADDR]], align 41505// CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81506// CHECK9-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 41507// CHECK9-NEXT:    call void @_ZN1SIfEC2Ef(ptr nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])1508// CHECK9-NEXT:    ret void1509//1510//1511// CHECK9-LABEL: define {{[^@]+}}@main.omp_outlined1512// CHECK9-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], ptr nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] {1513// CHECK9-NEXT:  entry:1514// CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81515// CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81516// CHECK9-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 81517// CHECK9-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 81518// CHECK9-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 81519// CHECK9-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 81520// CHECK9-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i64, align 81521// CHECK9-NEXT:    [[VEC1:%.*]] = alloca [2 x i32], align 41522// CHECK9-NEXT:    [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 41523// CHECK9-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 41524// CHECK9-NEXT:    [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 41525// CHECK9-NEXT:    [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 41526// CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81527// CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81528// CHECK9-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 81529// CHECK9-NEXT:    store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 81530// CHECK9-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 81531// CHECK9-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 81532// CHECK9-NEXT:    store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 81533// CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]]1534// CHECK9-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]]1535// CHECK9-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]]1536// CHECK9-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i64 8, i1 false)1537// CHECK9-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 01538// CHECK9-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 21539// CHECK9-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]]1540// CHECK9-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]1541// CHECK9:       omp.arraycpy.body:1542// CHECK9-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1543// CHECK9-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1544// CHECK9-NEXT:    call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]])1545// CHECK9-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr [[AGG_TMP]])1546// CHECK9-NEXT:    call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]]1547// CHECK9-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 11548// CHECK9-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 11549// CHECK9-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]]1550// CHECK9-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]1551// CHECK9:       omp.arraycpy.done3:1552// CHECK9-NEXT:    call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]])1553// CHECK9-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR4]], ptr nonnull align 4 dereferenceable(4) [[TMP2]], ptr [[AGG_TMP5]])1554// CHECK9-NEXT:    call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]]1555// CHECK9-NEXT:    [[TMP4:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 41556// CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i64 0, i64 01557// CHECK9-NEXT:    store i32 [[TMP4]], ptr [[ARRAYIDX]], align 41558// CHECK9-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i64 0, i64 01559// CHECK9-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[VAR4]], i64 4, i1 false)1560// CHECK9-NEXT:    store i32 2, ptr [[SIVAR_ADDR]], align 41561// CHECK9-NEXT:    call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]]1562// CHECK9-NEXT:    [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 01563// CHECK9-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 21564// CHECK9-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]1565// CHECK9:       arraydestroy.body:1566// CHECK9-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[OMP_ARRAYCPY_DONE3]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1567// CHECK9-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -11568// CHECK9-NEXT:    call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]1569// CHECK9-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]1570// CHECK9-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]1571// CHECK9:       arraydestroy.done8:1572// CHECK9-NEXT:    ret void1573//1574//1575// CHECK9-LABEL: define {{[^@]+}}@_ZN2StC1Ev1576// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1577// CHECK9-NEXT:  entry:1578// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81579// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81580// CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81581// CHECK9-NEXT:    call void @_ZN2StC2Ev(ptr nonnull align 4 dereferenceable(8) [[THIS1]])1582// CHECK9-NEXT:    ret void1583//1584//1585// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St1586// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1587// CHECK9-NEXT:  entry:1588// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81589// CHECK9-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 81590// CHECK9-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 81591// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81592// CHECK9-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 81593// CHECK9-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 81594// CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81595// CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 81596// CHECK9-NEXT:    call void @_ZN1SIfEC2ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]], ptr [[T]])1597// CHECK9-NEXT:    ret void1598//1599//1600// CHECK9-LABEL: define {{[^@]+}}@_ZN2StD1Ev1601// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1602// CHECK9-NEXT:  entry:1603// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81604// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81605// CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81606// CHECK9-NEXT:    call void @_ZN2StD2Ev(ptr nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]]1607// CHECK9-NEXT:    ret void1608//1609//1610// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev1611// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1612// CHECK9-NEXT:  entry:1613// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81614// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81615// CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81616// CHECK9-NEXT:    call void @_ZN1SIfED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]1617// CHECK9-NEXT:    ret void1618//1619//1620// CHECK9-LABEL: define {{[^@]+}}@main.omp_outlined.11621// CHECK9-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i64 [[T_VAR:%.*]]) #[[ATTR3]] {1622// CHECK9-NEXT:  entry:1623// CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81624// CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81625// CHECK9-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 81626// CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81627// CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81628// CHECK9-NEXT:    store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 81629// CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81630// CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 41631// CHECK9-NEXT:    [[DOTT_VAR__VOID_ADDR:%.*]] = call ptr @__kmpc_alloc(i32 [[TMP1]], i64 4, ptr inttoptr (i64 1 to ptr))1632// CHECK9-NEXT:    [[TMP2:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 41633// CHECK9-NEXT:    store i32 [[TMP2]], ptr [[DOTT_VAR__VOID_ADDR]], align 41634// CHECK9-NEXT:    store i32 0, ptr [[DOTT_VAR__VOID_ADDR]], align 41635// CHECK9-NEXT:    call void @__kmpc_free(i32 [[TMP1]], ptr [[DOTT_VAR__VOID_ADDR]], ptr inttoptr (i64 1 to ptr))1636// CHECK9-NEXT:    ret void1637//1638//1639// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v1640// CHECK9-SAME: () #[[ATTR1]] comdat {1641// CHECK9-NEXT:  entry:1642// CHECK9-NEXT:    [[RETVAL:%.*]] = alloca i32, align 41643// CHECK9-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 41644// CHECK9-NEXT:    [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 41645// CHECK9-NEXT:    [[T_VAR:%.*]] = alloca i32, align 1281646// CHECK9-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 1281647// CHECK9-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 1281648// CHECK9-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 1281649// CHECK9-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 81650// CHECK9-NEXT:    [[T_VAR_CASTED1:%.*]] = alloca i64, align 81651// CHECK9-NEXT:    call void @_ZN1SIiEC1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]])1652// CHECK9-NEXT:    call void @_ZN3SSTIiEC1Ev(ptr nonnull align 4 dereferenceable(4) [[SST]])1653// CHECK9-NEXT:    store i32 0, ptr [[T_VAR]], align 1281654// CHECK9-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[VEC]], ptr align 128 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)1655// CHECK9-NEXT:    call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[S_ARR]], i32 1)1656// CHECK9-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 11657// CHECK9-NEXT:    call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2)1658// CHECK9-NEXT:    call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[VAR]], i32 3)1659// CHECK9-NEXT:    [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 1281660// CHECK9-NEXT:    store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 41661// CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 81662// CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @_Z5tmainIiET_v.omp_outlined, ptr [[VEC]], i64 [[TMP1]], ptr [[S_ARR]], ptr [[VAR]])1663// CHECK9-NEXT:    [[TMP2:%.*]] = load i32, ptr [[T_VAR]], align 1281664// CHECK9-NEXT:    store i32 [[TMP2]], ptr [[T_VAR_CASTED1]], align 41665// CHECK9-NEXT:    [[TMP3:%.*]] = load i64, ptr [[T_VAR_CASTED1]], align 81666// CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @_Z5tmainIiET_v.omp_outlined.2, i64 [[TMP3]])1667// CHECK9-NEXT:    store i32 0, ptr [[RETVAL]], align 41668// CHECK9-NEXT:    call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]]1669// CHECK9-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 01670// CHECK9-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 21671// CHECK9-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]1672// CHECK9:       arraydestroy.body:1673// CHECK9-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1674// CHECK9-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -11675// CHECK9-NEXT:    call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]1676// CHECK9-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]1677// CHECK9-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]1678// CHECK9:       arraydestroy.done2:1679// CHECK9-NEXT:    call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]1680// CHECK9-NEXT:    [[TMP5:%.*]] = load i32, ptr [[RETVAL]], align 41681// CHECK9-NEXT:    ret i32 [[TMP5]]1682//1683//1684// CHECK9-LABEL: define {{[^@]+}}@_ZN2SSC2ERi1685// CHECK9-SAME: (ptr nonnull align 8 dereferenceable(32) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1686// CHECK9-NEXT:  entry:1687// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81688// CHECK9-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 81689// CHECK9-NEXT:    [[A2:%.*]] = alloca ptr, align 81690// CHECK9-NEXT:    [[B4:%.*]] = alloca i32, align 41691// CHECK9-NEXT:    [[C7:%.*]] = alloca ptr, align 81692// CHECK9-NEXT:    [[E:%.*]] = alloca ptr, align 81693// CHECK9-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 81694// CHECK9-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 81695// CHECK9-NEXT:    [[C_CASTED:%.*]] = alloca i64, align 81696// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81697// CHECK9-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 81698// CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81699// CHECK9-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 01700// CHECK9-NEXT:    store i32 0, ptr [[A]], align 81701// CHECK9-NEXT:    [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 11702// CHECK9-NEXT:    [[BF_LOAD:%.*]] = load i8, ptr [[B]], align 41703// CHECK9-NEXT:    [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -161704// CHECK9-NEXT:    [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 01705// CHECK9-NEXT:    store i8 [[BF_SET]], ptr [[B]], align 41706// CHECK9-NEXT:    [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 21707// CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META3]], !align [[META4]]1708// CHECK9-NEXT:    store ptr [[TMP0]], ptr [[C]], align 81709// CHECK9-NEXT:    [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 01710// CHECK9-NEXT:    store ptr [[A3]], ptr [[A2]], align 81711// CHECK9-NEXT:    [[B5:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 11712// CHECK9-NEXT:    [[BF_LOAD6:%.*]] = load i8, ptr [[B5]], align 41713// CHECK9-NEXT:    [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 41714// CHECK9-NEXT:    [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 41715// CHECK9-NEXT:    [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i321716// CHECK9-NEXT:    store i32 [[BF_CAST]], ptr [[B4]], align 41717// CHECK9-NEXT:    [[C8:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 21718// CHECK9-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[C8]], align 8, !nonnull [[META3]], !align [[META4]]1719// CHECK9-NEXT:    store ptr [[TMP1]], ptr [[C7]], align 81720// CHECK9-NEXT:    [[E9:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 31721// CHECK9-NEXT:    store ptr [[E9]], ptr [[E]], align 81722// CHECK9-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[A2]], align 8, !nonnull [[META3]], !align [[META4]]1723// CHECK9-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 41724// CHECK9-NEXT:    store i32 [[TMP3]], ptr [[A_CASTED]], align 41725// CHECK9-NEXT:    [[TMP4:%.*]] = load i64, ptr [[A_CASTED]], align 81726// CHECK9-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B4]], align 41727// CHECK9-NEXT:    store i32 [[TMP5]], ptr [[B_CASTED]], align 41728// CHECK9-NEXT:    [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 81729// CHECK9-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[C7]], align 8, !nonnull [[META3]], !align [[META4]]1730// CHECK9-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 41731// CHECK9-NEXT:    store i32 [[TMP8]], ptr [[C_CASTED]], align 41732// CHECK9-NEXT:    [[TMP9:%.*]] = load i64, ptr [[C_CASTED]], align 81733// CHECK9-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[E]], align 8, !nonnull [[META3]], !align [[META4]]1734// CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @_ZN2SSC2ERi.omp_outlined, ptr [[THIS1]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP9]], ptr [[TMP10]])1735// CHECK9-NEXT:    ret void1736//1737//1738// CHECK9-LABEL: define {{[^@]+}}@_ZN2SSC2ERi.omp_outlined1739// CHECK9-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]], ptr nonnull align 4 dereferenceable(16) [[E:%.*]]) #[[ATTR3]] {1740// CHECK9-NEXT:  entry:1741// CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81742// CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81743// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81744// CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 81745// CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 81746// CHECK9-NEXT:    [[C_ADDR:%.*]] = alloca i64, align 81747// CHECK9-NEXT:    [[E_ADDR:%.*]] = alloca ptr, align 81748// CHECK9-NEXT:    [[TMP:%.*]] = alloca ptr, align 81749// CHECK9-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 81750// CHECK9-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 81751// CHECK9-NEXT:    [[E3:%.*]] = alloca [4 x i32], align 161752// CHECK9-NEXT:    [[_TMP4:%.*]] = alloca ptr, align 81753// CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81754// CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81755// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81756// CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 81757// CHECK9-NEXT:    store i64 [[B]], ptr [[B_ADDR]], align 81758// CHECK9-NEXT:    store i64 [[C]], ptr [[C_ADDR]], align 81759// CHECK9-NEXT:    store ptr [[E]], ptr [[E_ADDR]], align 81760// CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81761// CHECK9-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[E_ADDR]], align 8, !nonnull [[META3]], !align [[META4]]1762// CHECK9-NEXT:    store ptr [[A_ADDR]], ptr [[TMP]], align 81763// CHECK9-NEXT:    store ptr [[C_ADDR]], ptr [[_TMP1]], align 81764// CHECK9-NEXT:    store ptr [[TMP1]], ptr [[_TMP2]], align 81765// CHECK9-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META3]], !align [[META4]]1766// CHECK9-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[E3]], ptr align 4 [[TMP2]], i64 16, i1 false)1767// CHECK9-NEXT:    store ptr [[E3]], ptr [[_TMP4]], align 81768// CHECK9-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META3]], !align [[META4]]1769// CHECK9-NEXT:    [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 41770// CHECK9-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP4]], 11771// CHECK9-NEXT:    store i32 [[INC]], ptr [[TMP3]], align 41772// CHECK9-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B_ADDR]], align 41773// CHECK9-NEXT:    [[DEC:%.*]] = add nsw i32 [[TMP5]], -11774// CHECK9-NEXT:    store i32 [[DEC]], ptr [[B_ADDR]], align 41775// CHECK9-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META3]], !align [[META4]]1776// CHECK9-NEXT:    [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 41777// CHECK9-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP7]], 11778// CHECK9-NEXT:    store i32 [[DIV]], ptr [[TMP6]], align 41779// CHECK9-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[_TMP4]], align 8, !nonnull [[META3]], !align [[META4]]1780// CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x i32], ptr [[TMP8]], i64 0, i64 21781// CHECK9-NEXT:    store i32 1111, ptr [[ARRAYIDX]], align 41782// CHECK9-NEXT:    ret void1783//1784//1785// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev1786// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1787// CHECK9-NEXT:  entry:1788// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81789// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81790// CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81791// CHECK9-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 01792// CHECK9-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 1281793// CHECK9-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float1794// CHECK9-NEXT:    store float [[CONV]], ptr [[F]], align 41795// CHECK9-NEXT:    ret void1796//1797//1798// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef1799// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1800// CHECK9-NEXT:  entry:1801// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81802// CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca float, align 41803// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81804// CHECK9-NEXT:    store float [[A]], ptr [[A_ADDR]], align 41805// CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81806// CHECK9-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 01807// CHECK9-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 41808// CHECK9-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 1281809// CHECK9-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float1810// CHECK9-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]1811// CHECK9-NEXT:    store float [[ADD]], ptr [[F]], align 41812// CHECK9-NEXT:    ret void1813//1814//1815// CHECK9-LABEL: define {{[^@]+}}@_ZN2StC2Ev1816// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1817// CHECK9-NEXT:  entry:1818// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81819// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81820// CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81821// CHECK9-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 01822// CHECK9-NEXT:    store i32 0, ptr [[A]], align 41823// CHECK9-NEXT:    [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 11824// CHECK9-NEXT:    store i32 0, ptr [[B]], align 41825// CHECK9-NEXT:    ret void1826//1827//1828// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St1829// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1830// CHECK9-NEXT:  entry:1831// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81832// CHECK9-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 81833// CHECK9-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 81834// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81835// CHECK9-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 81836// CHECK9-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 81837// CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81838// CHECK9-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 01839// CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8, !nonnull [[META3]], !align [[META4]]1840// CHECK9-NEXT:    [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 01841// CHECK9-NEXT:    [[TMP1:%.*]] = load float, ptr [[F2]], align 41842// CHECK9-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 01843// CHECK9-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 41844// CHECK9-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP2]] to float1845// CHECK9-NEXT:    [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]1846// CHECK9-NEXT:    store float [[ADD]], ptr [[F]], align 41847// CHECK9-NEXT:    ret void1848//1849//1850// CHECK9-LABEL: define {{[^@]+}}@_ZN2StD2Ev1851// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1852// CHECK9-NEXT:  entry:1853// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81854// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81855// CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81856// CHECK9-NEXT:    ret void1857//1858//1859// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev1860// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1861// CHECK9-NEXT:  entry:1862// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81863// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81864// CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81865// CHECK9-NEXT:    ret void1866//1867//1868// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev1869// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1870// CHECK9-NEXT:  entry:1871// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81872// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81873// CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81874// CHECK9-NEXT:    call void @_ZN1SIiEC2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]])1875// CHECK9-NEXT:    ret void1876//1877//1878// CHECK9-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev1879// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1880// CHECK9-NEXT:  entry:1881// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81882// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81883// CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81884// CHECK9-NEXT:    call void @_ZN3SSTIiEC2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]])1885// CHECK9-NEXT:    ret void1886//1887//1888// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei1889// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1890// CHECK9-NEXT:  entry:1891// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81892// CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 41893// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81894// CHECK9-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 41895// CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81896// CHECK9-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41897// CHECK9-NEXT:    call void @_ZN1SIiEC2Ei(ptr nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]])1898// CHECK9-NEXT:    ret void1899//1900//1901// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v.omp_outlined1902// CHECK9-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], ptr nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {1903// CHECK9-NEXT:  entry:1904// CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81905// CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81906// CHECK9-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 81907// CHECK9-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 81908// CHECK9-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 81909// CHECK9-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 81910// CHECK9-NEXT:    [[VEC1:%.*]] = alloca [2 x i32], align 1281911// CHECK9-NEXT:    [[S_ARR2:%.*]] = alloca [2 x %struct.S.0], align 1281912// CHECK9-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 41913// CHECK9-NEXT:    [[VAR4:%.*]] = alloca [[STRUCT_S_0:%.*]], align 1281914// CHECK9-NEXT:    [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 41915// CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81916// CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81917// CHECK9-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 81918// CHECK9-NEXT:    store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 81919// CHECK9-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 81920// CHECK9-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 81921// CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META3]], !align [[META4]]1922// CHECK9-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]]1923// CHECK9-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]]1924// CHECK9-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[VEC1]], ptr align 128 [[TMP0]], i64 8, i1 false)1925// CHECK9-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i32 0, i32 01926// CHECK9-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 21927// CHECK9-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]]1928// CHECK9-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]1929// CHECK9:       omp.arraycpy.body:1930// CHECK9-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1931// CHECK9-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1932// CHECK9-NEXT:    call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]])1933// CHECK9-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr [[AGG_TMP]])1934// CHECK9-NEXT:    call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]]1935// CHECK9-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 11936// CHECK9-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 11937// CHECK9-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]]1938// CHECK9-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]1939// CHECK9:       omp.arraycpy.done3:1940// CHECK9-NEXT:    call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]])1941// CHECK9-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR4]], ptr nonnull align 4 dereferenceable(4) [[TMP2]], ptr [[AGG_TMP5]])1942// CHECK9-NEXT:    call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]]1943// CHECK9-NEXT:    [[TMP4:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 41944// CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i64 0, i64 01945// CHECK9-NEXT:    store i32 [[TMP4]], ptr [[ARRAYIDX]], align 1281946// CHECK9-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i64 0, i64 01947// CHECK9-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[ARRAYIDX6]], ptr align 128 [[VAR4]], i64 4, i1 false)1948// CHECK9-NEXT:    call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]]1949// CHECK9-NEXT:    [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i32 0, i32 01950// CHECK9-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i64 21951// CHECK9-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]1952// CHECK9:       arraydestroy.body:1953// CHECK9-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[OMP_ARRAYCPY_DONE3]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1954// CHECK9-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -11955// CHECK9-NEXT:    call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]1956// CHECK9-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]1957// CHECK9-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]1958// CHECK9:       arraydestroy.done8:1959// CHECK9-NEXT:    ret void1960//1961//1962// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St1963// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1964// CHECK9-NEXT:  entry:1965// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81966// CHECK9-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 81967// CHECK9-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 81968// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81969// CHECK9-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 81970// CHECK9-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 81971// CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81972// CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 81973// CHECK9-NEXT:    call void @_ZN1SIiEC2ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]], ptr [[T]])1974// CHECK9-NEXT:    ret void1975//1976//1977// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev1978// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1979// CHECK9-NEXT:  entry:1980// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81981// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81982// CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81983// CHECK9-NEXT:    call void @_ZN1SIiED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]1984// CHECK9-NEXT:    ret void1985//1986//1987// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v.omp_outlined.21988// CHECK9-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i64 [[T_VAR:%.*]]) #[[ATTR3]] {1989// CHECK9-NEXT:  entry:1990// CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81991// CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81992// CHECK9-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 81993// CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81994// CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81995// CHECK9-NEXT:    store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 81996// CHECK9-NEXT:    ret void1997//1998//1999// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev2000// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2001// CHECK9-NEXT:  entry:2002// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82003// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82004// CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82005// CHECK9-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 02006// CHECK9-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 1282007// CHECK9-NEXT:    store i32 [[TMP0]], ptr [[F]], align 42008// CHECK9-NEXT:    ret void2009//2010//2011// CHECK9-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev2012// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2013// CHECK9-NEXT:  entry:2014// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82015// CHECK9-NEXT:    [[A2:%.*]] = alloca ptr, align 82016// CHECK9-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 82017// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82018// CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82019// CHECK9-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SST:%.*]], ptr [[THIS1]], i32 0, i32 02020// CHECK9-NEXT:    store i32 0, ptr [[A]], align 42021// CHECK9-NEXT:    [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_SST]], ptr [[THIS1]], i32 0, i32 02022// CHECK9-NEXT:    store ptr [[A3]], ptr [[A2]], align 82023// CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A2]], align 8, !nonnull [[META3]], !align [[META4]]2024// CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 42025// CHECK9-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 42026// CHECK9-NEXT:    [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 82027// CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @_ZN3SSTIiEC2Ev.omp_outlined, ptr [[THIS1]], i64 [[TMP2]])2028// CHECK9-NEXT:    ret void2029//2030//2031// CHECK9-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev.omp_outlined2032// CHECK9-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr [[THIS:%.*]], i64 [[A:%.*]]) #[[ATTR3]] {2033// CHECK9-NEXT:  entry:2034// CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 82035// CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 82036// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82037// CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 82038// CHECK9-NEXT:    [[TMP:%.*]] = alloca ptr, align 82039// CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 82040// CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 82041// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82042// CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 82043// CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82044// CHECK9-NEXT:    store ptr [[A_ADDR]], ptr [[TMP]], align 82045// CHECK9-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META3]], !align [[META4]]2046// CHECK9-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 42047// CHECK9-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP2]], 12048// CHECK9-NEXT:    store i32 [[INC]], ptr [[TMP1]], align 42049// CHECK9-NEXT:    ret void2050//2051//2052// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei2053// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2054// CHECK9-NEXT:  entry:2055// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82056// CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 42057// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82058// CHECK9-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 42059// CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82060// CHECK9-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 02061// CHECK9-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 42062// CHECK9-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 1282063// CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]2064// CHECK9-NEXT:    store i32 [[ADD]], ptr [[F]], align 42065// CHECK9-NEXT:    ret void2066//2067//2068// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St2069// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2070// CHECK9-NEXT:  entry:2071// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82072// CHECK9-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 82073// CHECK9-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 82074// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82075// CHECK9-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 82076// CHECK9-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 82077// CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82078// CHECK9-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 02079// CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8, !nonnull [[META3]], !align [[META4]]2080// CHECK9-NEXT:    [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 02081// CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[F2]], align 42082// CHECK9-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 02083// CHECK9-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 42084// CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]2085// CHECK9-NEXT:    store i32 [[ADD]], ptr [[F]], align 42086// CHECK9-NEXT:    ret void2087//2088//2089// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev2090// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2091// CHECK9-NEXT:  entry:2092// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82093// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82094// CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82095// CHECK9-NEXT:    ret void2096//2097//2098// CHECK11-LABEL: define {{[^@]+}}@main2099// CHECK11-SAME: () #[[ATTR0:[0-9]+]] {2100// CHECK11-NEXT:  entry:2101// CHECK11-NEXT:    [[RETVAL:%.*]] = alloca i32, align 42102// CHECK11-NEXT:    [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 82103// CHECK11-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 82104// CHECK11-NEXT:    store i32 0, ptr [[RETVAL]], align 42105// CHECK11-NEXT:    call void @_ZN2SSC1ERi(ptr nonnull align 8 dereferenceable(32) [[SS]], ptr nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar)2106// CHECK11-NEXT:    [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 02107// CHECK11-NEXT:    store ptr @_ZZ4mainE5sivar, ptr [[TMP0]], align 82108// CHECK11-NEXT:    call void @"_ZZ4mainENK3$_0clEv"(ptr nonnull align 8 dereferenceable(8) [[REF_TMP]])2109// CHECK11-NEXT:    ret i32 02110//2111//2112// CHECK11-LABEL: define {{[^@]+}}@_ZN2SSC1ERi2113// CHECK11-SAME: (ptr nonnull align 8 dereferenceable(32) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {2114// CHECK11-NEXT:  entry:2115// CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82116// CHECK11-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 82117// CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82118// CHECK11-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 82119// CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82120// CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 82121// CHECK11-NEXT:    call void @_ZN2SSC2ERi(ptr nonnull align 8 dereferenceable(32) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]])2122// CHECK11-NEXT:    ret void2123//2124//2125// CHECK11-LABEL: define {{[^@]+}}@_ZN2SSC2ERi2126// CHECK11-SAME: (ptr nonnull align 8 dereferenceable(32) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2127// CHECK11-NEXT:  entry:2128// CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82129// CHECK11-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 82130// CHECK11-NEXT:    [[A2:%.*]] = alloca ptr, align 82131// CHECK11-NEXT:    [[B4:%.*]] = alloca i32, align 42132// CHECK11-NEXT:    [[C7:%.*]] = alloca ptr, align 82133// CHECK11-NEXT:    [[E:%.*]] = alloca ptr, align 82134// CHECK11-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 82135// CHECK11-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 82136// CHECK11-NEXT:    [[C_CASTED:%.*]] = alloca i64, align 82137// CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82138// CHECK11-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 82139// CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82140// CHECK11-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 02141// CHECK11-NEXT:    store i32 0, ptr [[A]], align 82142// CHECK11-NEXT:    [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 12143// CHECK11-NEXT:    [[BF_LOAD:%.*]] = load i8, ptr [[B]], align 42144// CHECK11-NEXT:    [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -162145// CHECK11-NEXT:    [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 02146// CHECK11-NEXT:    store i8 [[BF_SET]], ptr [[B]], align 42147// CHECK11-NEXT:    [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 22148// CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]]2149// CHECK11-NEXT:    store ptr [[TMP0]], ptr [[C]], align 82150// CHECK11-NEXT:    [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 02151// CHECK11-NEXT:    store ptr [[A3]], ptr [[A2]], align 82152// CHECK11-NEXT:    [[B5:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 12153// CHECK11-NEXT:    [[BF_LOAD6:%.*]] = load i8, ptr [[B5]], align 42154// CHECK11-NEXT:    [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 42155// CHECK11-NEXT:    [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 42156// CHECK11-NEXT:    [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i322157// CHECK11-NEXT:    store i32 [[BF_CAST]], ptr [[B4]], align 42158// CHECK11-NEXT:    [[C8:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 22159// CHECK11-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[C8]], align 8, !nonnull [[META3]], !align [[META4]]2160// CHECK11-NEXT:    store ptr [[TMP1]], ptr [[C7]], align 82161// CHECK11-NEXT:    [[E9:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 32162// CHECK11-NEXT:    store ptr [[E9]], ptr [[E]], align 82163// CHECK11-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[A2]], align 8, !nonnull [[META3]], !align [[META4]]2164// CHECK11-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 42165// CHECK11-NEXT:    store i32 [[TMP3]], ptr [[A_CASTED]], align 42166// CHECK11-NEXT:    [[TMP4:%.*]] = load i64, ptr [[A_CASTED]], align 82167// CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B4]], align 42168// CHECK11-NEXT:    store i32 [[TMP5]], ptr [[B_CASTED]], align 42169// CHECK11-NEXT:    [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 82170// CHECK11-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[C7]], align 8, !nonnull [[META3]], !align [[META4]]2171// CHECK11-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 42172// CHECK11-NEXT:    store i32 [[TMP8]], ptr [[C_CASTED]], align 42173// CHECK11-NEXT:    [[TMP9:%.*]] = load i64, ptr [[C_CASTED]], align 82174// CHECK11-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[E]], align 8, !nonnull [[META3]], !align [[META4]]2175// CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 5, ptr @_ZN2SSC2ERi.omp_outlined, ptr [[THIS1]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP9]], ptr [[TMP10]])2176// CHECK11-NEXT:    ret void2177//2178//2179// CHECK11-LABEL: define {{[^@]+}}@_ZN2SSC2ERi.omp_outlined2180// CHECK11-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]], ptr nonnull align 4 dereferenceable(16) [[E:%.*]]) #[[ATTR2:[0-9]+]] {2181// CHECK11-NEXT:  entry:2182// CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 82183// CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 82184// CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82185// CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 82186// CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 82187// CHECK11-NEXT:    [[C_ADDR:%.*]] = alloca i64, align 82188// CHECK11-NEXT:    [[E_ADDR:%.*]] = alloca ptr, align 82189// CHECK11-NEXT:    [[TMP:%.*]] = alloca ptr, align 82190// CHECK11-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 82191// CHECK11-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 82192// CHECK11-NEXT:    [[E3:%.*]] = alloca [4 x i32], align 162193// CHECK11-NEXT:    [[_TMP4:%.*]] = alloca ptr, align 82194// CHECK11-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 82195// CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 82196// CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 82197// CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82198// CHECK11-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 82199// CHECK11-NEXT:    store i64 [[B]], ptr [[B_ADDR]], align 82200// CHECK11-NEXT:    store i64 [[C]], ptr [[C_ADDR]], align 82201// CHECK11-NEXT:    store ptr [[E]], ptr [[E_ADDR]], align 82202// CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82203// CHECK11-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[E_ADDR]], align 8, !nonnull [[META3]], !align [[META4]]2204// CHECK11-NEXT:    store ptr [[A_ADDR]], ptr [[TMP]], align 82205// CHECK11-NEXT:    store ptr [[C_ADDR]], ptr [[_TMP1]], align 82206// CHECK11-NEXT:    store ptr [[TMP1]], ptr [[_TMP2]], align 82207// CHECK11-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META3]], !align [[META4]]2208// CHECK11-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[E3]], ptr align 4 [[TMP2]], i64 16, i1 false)2209// CHECK11-NEXT:    store ptr [[E3]], ptr [[_TMP4]], align 82210// CHECK11-NEXT:    [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 02211// CHECK11-NEXT:    store ptr [[TMP0]], ptr [[TMP3]], align 82212// CHECK11-NEXT:    [[TMP4:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 12213// CHECK11-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META3]], !align [[META4]]2214// CHECK11-NEXT:    store ptr [[TMP5]], ptr [[TMP4]], align 82215// CHECK11-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 22216// CHECK11-NEXT:    store ptr [[B_ADDR]], ptr [[TMP6]], align 82217// CHECK11-NEXT:    [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 32218// CHECK11-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META3]], !align [[META4]]2219// CHECK11-NEXT:    store ptr [[TMP8]], ptr [[TMP7]], align 82220// CHECK11-NEXT:    call void @_ZZN2SSC1ERiENKUlvE_clEv(ptr nonnull align 8 dereferenceable(32) [[REF_TMP]])2221// CHECK11-NEXT:    ret void2222//2223//2224// CHECK11-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv2225// CHECK11-SAME: (ptr nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR1]] align 2 {2226// CHECK11-NEXT:  entry:2227// CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82228// CHECK11-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 82229// CHECK11-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 82230// CHECK11-NEXT:    [[C_CASTED:%.*]] = alloca i64, align 82231// CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82232// CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82233// CHECK11-NEXT:    [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0:%.*]], ptr [[THIS1]], i32 0, i32 02234// CHECK11-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 82235// CHECK11-NEXT:    [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 12236// CHECK11-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8, !nonnull [[META3]], !align [[META4]]2237// CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 42238// CHECK11-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP4]], 12239// CHECK11-NEXT:    store i32 [[INC]], ptr [[TMP3]], align 42240// CHECK11-NEXT:    [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 22241// CHECK11-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8, !nonnull [[META3]], !align [[META4]]2242// CHECK11-NEXT:    [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 42243// CHECK11-NEXT:    [[DEC:%.*]] = add nsw i32 [[TMP7]], -12244// CHECK11-NEXT:    store i32 [[DEC]], ptr [[TMP6]], align 42245// CHECK11-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 32246// CHECK11-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8, !nonnull [[META3]], !align [[META4]]2247// CHECK11-NEXT:    [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 42248// CHECK11-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP10]], 12249// CHECK11-NEXT:    store i32 [[DIV]], ptr [[TMP9]], align 42250// CHECK11-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 12251// CHECK11-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8, !nonnull [[META3]], !align [[META4]]2252// CHECK11-NEXT:    [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 42253// CHECK11-NEXT:    store i32 [[TMP13]], ptr [[A_CASTED]], align 42254// CHECK11-NEXT:    [[TMP14:%.*]] = load i64, ptr [[A_CASTED]], align 82255// CHECK11-NEXT:    [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 22256// CHECK11-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8, !nonnull [[META3]], !align [[META4]]2257// CHECK11-NEXT:    [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 42258// CHECK11-NEXT:    store i32 [[TMP17]], ptr [[B_CASTED]], align 42259// CHECK11-NEXT:    [[TMP18:%.*]] = load i64, ptr [[B_CASTED]], align 82260// CHECK11-NEXT:    [[TMP19:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 32261// CHECK11-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8, !nonnull [[META3]], !align [[META4]]2262// CHECK11-NEXT:    [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 42263// CHECK11-NEXT:    store i32 [[TMP21]], ptr [[C_CASTED]], align 42264// CHECK11-NEXT:    [[TMP22:%.*]] = load i64, ptr [[C_CASTED]], align 82265// CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined, ptr [[TMP1]], i64 [[TMP14]], i64 [[TMP18]], i64 [[TMP22]])2266// CHECK11-NEXT:    ret void2267//2268//2269// CHECK11-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined2270// CHECK11-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]]) #[[ATTR2]] {2271// CHECK11-NEXT:  entry:2272// CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 82273// CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 82274// CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82275// CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 82276// CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 82277// CHECK11-NEXT:    [[C_ADDR:%.*]] = alloca i64, align 82278// CHECK11-NEXT:    [[TMP:%.*]] = alloca ptr, align 82279// CHECK11-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 82280// CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 82281// CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 82282// CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82283// CHECK11-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 82284// CHECK11-NEXT:    store i64 [[B]], ptr [[B_ADDR]], align 82285// CHECK11-NEXT:    store i64 [[C]], ptr [[C_ADDR]], align 82286// CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82287// CHECK11-NEXT:    store ptr [[A_ADDR]], ptr [[TMP]], align 82288// CHECK11-NEXT:    store ptr [[C_ADDR]], ptr [[_TMP1]], align 82289// CHECK11-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META3]], !align [[META4]]2290// CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 42291// CHECK11-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP2]], 12292// CHECK11-NEXT:    store i32 [[INC]], ptr [[TMP1]], align 42293// CHECK11-NEXT:    [[TMP3:%.*]] = load i32, ptr [[B_ADDR]], align 42294// CHECK11-NEXT:    [[DEC:%.*]] = add nsw i32 [[TMP3]], -12295// CHECK11-NEXT:    store i32 [[DEC]], ptr [[B_ADDR]], align 42296// CHECK11-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META3]], !align [[META4]]2297// CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 42298// CHECK11-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP5]], 12299// CHECK11-NEXT:    store i32 [[DIV]], ptr [[TMP4]], align 42300// CHECK11-NEXT:    ret void2301//2302//2303// CHECK12-LABEL: define {{[^@]+}}@main2304// CHECK12-SAME: () #[[ATTR0:[0-9]+]] {2305// CHECK12-NEXT:  entry:2306// CHECK12-NEXT:    [[RETVAL:%.*]] = alloca i32, align 42307// CHECK12-NEXT:    [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 82308// CHECK12-NEXT:    [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, i32 }>, align 82309// CHECK12-NEXT:    store i32 0, ptr [[RETVAL]], align 42310// CHECK12-NEXT:    call void @_ZN2SSC1ERi(ptr nonnull align 8 dereferenceable(32) [[SS]], ptr nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar)2311// CHECK12-NEXT:    [[BLOCK_ISA:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 02312// CHECK12-NEXT:    store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 82313// CHECK12-NEXT:    [[BLOCK_FLAGS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 12314// CHECK12-NEXT:    store i32 1073741824, ptr [[BLOCK_FLAGS]], align 82315// CHECK12-NEXT:    [[BLOCK_RESERVED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 22316// CHECK12-NEXT:    store i32 0, ptr [[BLOCK_RESERVED]], align 42317// CHECK12-NEXT:    [[BLOCK_INVOKE:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 32318// CHECK12-NEXT:    store ptr @__main_block_invoke, ptr [[BLOCK_INVOKE]], align 82319// CHECK12-NEXT:    [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 42320// CHECK12-NEXT:    store ptr @__block_descriptor_tmp.1, ptr [[BLOCK_DESCRIPTOR]], align 82321// CHECK12-NEXT:    [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 52322// CHECK12-NEXT:    [[TMP0:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 42323// CHECK12-NEXT:    store i32 [[TMP0]], ptr [[BLOCK_CAPTURED]], align 82324// CHECK12-NEXT:    [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 32325// CHECK12-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 82326// CHECK12-NEXT:    call void [[TMP2]](ptr [[BLOCK]])2327// CHECK12-NEXT:    ret i32 02328//2329//2330// CHECK12-LABEL: define {{[^@]+}}@_ZN2SSC1ERi2331// CHECK12-SAME: (ptr nonnull align 8 dereferenceable(32) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {2332// CHECK12-NEXT:  entry:2333// CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82334// CHECK12-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 82335// CHECK12-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82336// CHECK12-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 82337// CHECK12-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82338// CHECK12-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 82339// CHECK12-NEXT:    call void @_ZN2SSC2ERi(ptr nonnull align 8 dereferenceable(32) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]])2340// CHECK12-NEXT:    ret void2341//2342//2343// CHECK12-LABEL: define {{[^@]+}}@__main_block_invoke2344// CHECK12-SAME: (ptr [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] {2345// CHECK12-NEXT:  entry:2346// CHECK12-NEXT:    [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 82347// CHECK12-NEXT:    [[BLOCK_ADDR:%.*]] = alloca ptr, align 82348// CHECK12-NEXT:    [[G_CASTED:%.*]] = alloca i64, align 82349// CHECK12-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i64, align 82350// CHECK12-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 82351// CHECK12-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 82352// CHECK12-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 1282353// CHECK12-NEXT:    store i32 [[TMP0]], ptr [[G_CASTED]], align 42354// CHECK12-NEXT:    [[TMP1:%.*]] = load i64, ptr [[G_CASTED]], align 82355// CHECK12-NEXT:    [[TMP2:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 42356// CHECK12-NEXT:    store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 42357// CHECK12-NEXT:    [[TMP3:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 82358// CHECK12-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 2, ptr @__main_block_invoke.omp_outlined, i64 [[TMP1]], i64 [[TMP3]])2359// CHECK12-NEXT:    ret void2360//2361//2362// CHECK12-LABEL: define {{[^@]+}}@__main_block_invoke.omp_outlined2363// CHECK12-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] {2364// CHECK12-NEXT:  entry:2365// CHECK12-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 82366// CHECK12-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 82367// CHECK12-NEXT:    [[G_ADDR:%.*]] = alloca i64, align 82368// CHECK12-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i64, align 82369// CHECK12-NEXT:    [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, align 1282370// CHECK12-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 82371// CHECK12-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 82372// CHECK12-NEXT:    store i64 [[G]], ptr [[G_ADDR]], align 82373// CHECK12-NEXT:    store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 82374// CHECK12-NEXT:    store i32 1, ptr [[G_ADDR]], align 42375// CHECK12-NEXT:    store i32 2, ptr [[SIVAR_ADDR]], align 42376// CHECK12-NEXT:    [[BLOCK_ISA:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 02377// CHECK12-NEXT:    store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 1282378// CHECK12-NEXT:    [[BLOCK_FLAGS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 12379// CHECK12-NEXT:    store i32 1073741824, ptr [[BLOCK_FLAGS]], align 82380// CHECK12-NEXT:    [[BLOCK_RESERVED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 22381// CHECK12-NEXT:    store i32 0, ptr [[BLOCK_RESERVED]], align 42382// CHECK12-NEXT:    [[BLOCK_INVOKE:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 32383// CHECK12-NEXT:    store ptr @g_block_invoke, ptr [[BLOCK_INVOKE]], align 162384// CHECK12-NEXT:    [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 42385// CHECK12-NEXT:    store ptr @__block_descriptor_tmp, ptr [[BLOCK_DESCRIPTOR]], align 82386// CHECK12-NEXT:    [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 72387// CHECK12-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr [[G_ADDR]], align 42388// CHECK12-NEXT:    store volatile i32 [[TMP0]], ptr [[BLOCK_CAPTURED]], align 1282389// CHECK12-NEXT:    [[BLOCK_CAPTURED1:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 52390// CHECK12-NEXT:    [[TMP1:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 42391// CHECK12-NEXT:    store i32 [[TMP1]], ptr [[BLOCK_CAPTURED1]], align 322392// CHECK12-NEXT:    [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 32393// CHECK12-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 82394// CHECK12-NEXT:    call void [[TMP3]](ptr [[BLOCK]])2395// CHECK12-NEXT:    ret void2396//2397//2398// CHECK12-LABEL: define {{[^@]+}}@g_block_invoke2399// CHECK12-SAME: (ptr [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] {2400// CHECK12-NEXT:  entry:2401// CHECK12-NEXT:    [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 82402// CHECK12-NEXT:    [[BLOCK_ADDR:%.*]] = alloca ptr, align 82403// CHECK12-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 82404// CHECK12-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 82405// CHECK12-NEXT:    [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 72406// CHECK12-NEXT:    store i32 2, ptr [[BLOCK_CAPTURE_ADDR]], align 1282407// CHECK12-NEXT:    [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 52408// CHECK12-NEXT:    store i32 4, ptr [[BLOCK_CAPTURE_ADDR1]], align 322409// CHECK12-NEXT:    ret void2410//2411//2412// CHECK12-LABEL: define {{[^@]+}}@_ZN2SSC2ERi2413// CHECK12-SAME: (ptr nonnull align 8 dereferenceable(32) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2414// CHECK12-NEXT:  entry:2415// CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82416// CHECK12-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 82417// CHECK12-NEXT:    [[A2:%.*]] = alloca ptr, align 82418// CHECK12-NEXT:    [[B4:%.*]] = alloca i32, align 42419// CHECK12-NEXT:    [[C7:%.*]] = alloca ptr, align 82420// CHECK12-NEXT:    [[E:%.*]] = alloca ptr, align 82421// CHECK12-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 82422// CHECK12-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 82423// CHECK12-NEXT:    [[C_CASTED:%.*]] = alloca i64, align 82424// CHECK12-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82425// CHECK12-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 82426// CHECK12-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82427// CHECK12-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 02428// CHECK12-NEXT:    store i32 0, ptr [[A]], align 82429// CHECK12-NEXT:    [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 12430// CHECK12-NEXT:    [[BF_LOAD:%.*]] = load i8, ptr [[B]], align 42431// CHECK12-NEXT:    [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -162432// CHECK12-NEXT:    [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 02433// CHECK12-NEXT:    store i8 [[BF_SET]], ptr [[B]], align 42434// CHECK12-NEXT:    [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 22435// CHECK12-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]]2436// CHECK12-NEXT:    store ptr [[TMP0]], ptr [[C]], align 82437// CHECK12-NEXT:    [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 02438// CHECK12-NEXT:    store ptr [[A3]], ptr [[A2]], align 82439// CHECK12-NEXT:    [[B5:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 12440// CHECK12-NEXT:    [[BF_LOAD6:%.*]] = load i8, ptr [[B5]], align 42441// CHECK12-NEXT:    [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 42442// CHECK12-NEXT:    [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 42443// CHECK12-NEXT:    [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i322444// CHECK12-NEXT:    store i32 [[BF_CAST]], ptr [[B4]], align 42445// CHECK12-NEXT:    [[C8:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 22446// CHECK12-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[C8]], align 8, !nonnull [[META5]], !align [[META6]]2447// CHECK12-NEXT:    store ptr [[TMP1]], ptr [[C7]], align 82448// CHECK12-NEXT:    [[E9:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 32449// CHECK12-NEXT:    store ptr [[E9]], ptr [[E]], align 82450// CHECK12-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[A2]], align 8, !nonnull [[META5]], !align [[META6]]2451// CHECK12-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 42452// CHECK12-NEXT:    store i32 [[TMP3]], ptr [[A_CASTED]], align 42453// CHECK12-NEXT:    [[TMP4:%.*]] = load i64, ptr [[A_CASTED]], align 82454// CHECK12-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B4]], align 42455// CHECK12-NEXT:    store i32 [[TMP5]], ptr [[B_CASTED]], align 42456// CHECK12-NEXT:    [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 82457// CHECK12-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[C7]], align 8, !nonnull [[META5]], !align [[META6]]2458// CHECK12-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 42459// CHECK12-NEXT:    store i32 [[TMP8]], ptr [[C_CASTED]], align 42460// CHECK12-NEXT:    [[TMP9:%.*]] = load i64, ptr [[C_CASTED]], align 82461// CHECK12-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[E]], align 8, !nonnull [[META5]], !align [[META6]]2462// CHECK12-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @_ZN2SSC2ERi.omp_outlined, ptr [[THIS1]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP9]], ptr [[TMP10]])2463// CHECK12-NEXT:    ret void2464//2465//2466// CHECK12-LABEL: define {{[^@]+}}@_ZN2SSC2ERi.omp_outlined2467// CHECK12-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]], ptr nonnull align 4 dereferenceable(16) [[E:%.*]]) #[[ATTR3]] {2468// CHECK12-NEXT:  entry:2469// CHECK12-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 82470// CHECK12-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 82471// CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82472// CHECK12-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 82473// CHECK12-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 82474// CHECK12-NEXT:    [[C_ADDR:%.*]] = alloca i64, align 82475// CHECK12-NEXT:    [[E_ADDR:%.*]] = alloca ptr, align 82476// CHECK12-NEXT:    [[TMP:%.*]] = alloca ptr, align 82477// CHECK12-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 82478// CHECK12-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 82479// CHECK12-NEXT:    [[E3:%.*]] = alloca [4 x i32], align 162480// CHECK12-NEXT:    [[_TMP4:%.*]] = alloca ptr, align 82481// CHECK12-NEXT:    [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, align 82482// CHECK12-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 82483// CHECK12-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 82484// CHECK12-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82485// CHECK12-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 82486// CHECK12-NEXT:    store i64 [[B]], ptr [[B_ADDR]], align 82487// CHECK12-NEXT:    store i64 [[C]], ptr [[C_ADDR]], align 82488// CHECK12-NEXT:    store ptr [[E]], ptr [[E_ADDR]], align 82489// CHECK12-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82490// CHECK12-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[E_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]2491// CHECK12-NEXT:    store ptr [[A_ADDR]], ptr [[TMP]], align 82492// CHECK12-NEXT:    store ptr [[C_ADDR]], ptr [[_TMP1]], align 82493// CHECK12-NEXT:    store ptr [[TMP1]], ptr [[_TMP2]], align 82494// CHECK12-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META5]], !align [[META6]]2495// CHECK12-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[E3]], ptr align 4 [[TMP2]], i64 16, i1 false)2496// CHECK12-NEXT:    store ptr [[E3]], ptr [[_TMP4]], align 82497// CHECK12-NEXT:    [[BLOCK_ISA:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 02498// CHECK12-NEXT:    store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 82499// CHECK12-NEXT:    [[BLOCK_FLAGS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 12500// CHECK12-NEXT:    store i32 1073741824, ptr [[BLOCK_FLAGS]], align 82501// CHECK12-NEXT:    [[BLOCK_RESERVED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 22502// CHECK12-NEXT:    store i32 0, ptr [[BLOCK_RESERVED]], align 42503// CHECK12-NEXT:    [[BLOCK_INVOKE:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 32504// CHECK12-NEXT:    store ptr @g_block_invoke_2, ptr [[BLOCK_INVOKE]], align 82505// CHECK12-NEXT:    [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 42506// CHECK12-NEXT:    store ptr @__block_descriptor_tmp.2, ptr [[BLOCK_DESCRIPTOR]], align 82507// CHECK12-NEXT:    [[BLOCK_CAPTURED_THIS_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 52508// CHECK12-NEXT:    store ptr [[TMP0]], ptr [[BLOCK_CAPTURED_THIS_ADDR]], align 82509// CHECK12-NEXT:    [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 62510// CHECK12-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]]2511// CHECK12-NEXT:    store ptr [[TMP3]], ptr [[BLOCK_CAPTURED]], align 82512// CHECK12-NEXT:    [[BLOCK_CAPTURED5:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 82513// CHECK12-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 42514// CHECK12-NEXT:    store i32 [[TMP4]], ptr [[BLOCK_CAPTURED5]], align 82515// CHECK12-NEXT:    [[BLOCK_CAPTURED6:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 72516// CHECK12-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META6]]2517// CHECK12-NEXT:    store ptr [[TMP5]], ptr [[BLOCK_CAPTURED6]], align 82518// CHECK12-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 32519// CHECK12-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 82520// CHECK12-NEXT:    call void [[TMP7]](ptr [[BLOCK]])2521// CHECK12-NEXT:    ret void2522//2523//2524// CHECK12-LABEL: define {{[^@]+}}@g_block_invoke_22525// CHECK12-SAME: (ptr [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] {2526// CHECK12-NEXT:  entry:2527// CHECK12-NEXT:    [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 82528// CHECK12-NEXT:    [[BLOCK_ADDR:%.*]] = alloca ptr, align 82529// CHECK12-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 82530// CHECK12-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 82531// CHECK12-NEXT:    [[C_CASTED:%.*]] = alloca i64, align 82532// CHECK12-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 82533// CHECK12-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 82534// CHECK12-NEXT:    [[BLOCK_CAPTURED_THIS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 52535// CHECK12-NEXT:    [[THIS:%.*]] = load ptr, ptr [[BLOCK_CAPTURED_THIS]], align 82536// CHECK12-NEXT:    [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 62537// CHECK12-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]2538// CHECK12-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 42539// CHECK12-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP1]], 12540// CHECK12-NEXT:    store i32 [[INC]], ptr [[TMP0]], align 42541// CHECK12-NEXT:    [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 82542// CHECK12-NEXT:    [[TMP2:%.*]] = load i32, ptr [[BLOCK_CAPTURE_ADDR1]], align 82543// CHECK12-NEXT:    [[DEC:%.*]] = add nsw i32 [[TMP2]], -12544// CHECK12-NEXT:    store i32 [[DEC]], ptr [[BLOCK_CAPTURE_ADDR1]], align 82545// CHECK12-NEXT:    [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 72546// CHECK12-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR2]], align 8, !nonnull [[META5]], !align [[META6]]2547// CHECK12-NEXT:    [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 42548// CHECK12-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP4]], 12549// CHECK12-NEXT:    store i32 [[DIV]], ptr [[TMP3]], align 42550// CHECK12-NEXT:    [[BLOCK_CAPTURE_ADDR3:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 62551// CHECK12-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR3]], align 8, !nonnull [[META5]], !align [[META6]]2552// CHECK12-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 42553// CHECK12-NEXT:    store i32 [[TMP6]], ptr [[A_CASTED]], align 42554// CHECK12-NEXT:    [[TMP7:%.*]] = load i64, ptr [[A_CASTED]], align 82555// CHECK12-NEXT:    [[BLOCK_CAPTURE_ADDR4:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 82556// CHECK12-NEXT:    [[TMP8:%.*]] = load i32, ptr [[BLOCK_CAPTURE_ADDR4]], align 82557// CHECK12-NEXT:    store i32 [[TMP8]], ptr [[B_CASTED]], align 42558// CHECK12-NEXT:    [[TMP9:%.*]] = load i64, ptr [[B_CASTED]], align 82559// CHECK12-NEXT:    [[BLOCK_CAPTURE_ADDR5:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 72560// CHECK12-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR5]], align 8, !nonnull [[META5]], !align [[META6]]2561// CHECK12-NEXT:    [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 42562// CHECK12-NEXT:    store i32 [[TMP11]], ptr [[C_CASTED]], align 42563// CHECK12-NEXT:    [[TMP12:%.*]] = load i64, ptr [[C_CASTED]], align 82564// CHECK12-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @g_block_invoke_2.omp_outlined, ptr [[THIS]], i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP12]])2565// CHECK12-NEXT:    ret void2566//2567//2568// CHECK12-LABEL: define {{[^@]+}}@g_block_invoke_2.omp_outlined2569// CHECK12-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]]) #[[ATTR3]] {2570// CHECK12-NEXT:  entry:2571// CHECK12-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 82572// CHECK12-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 82573// CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82574// CHECK12-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 82575// CHECK12-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 82576// CHECK12-NEXT:    [[C_ADDR:%.*]] = alloca i64, align 82577// CHECK12-NEXT:    [[TMP:%.*]] = alloca ptr, align 82578// CHECK12-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 82579// CHECK12-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 82580// CHECK12-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 82581// CHECK12-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82582// CHECK12-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 82583// CHECK12-NEXT:    store i64 [[B]], ptr [[B_ADDR]], align 82584// CHECK12-NEXT:    store i64 [[C]], ptr [[C_ADDR]], align 82585// CHECK12-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82586// CHECK12-NEXT:    store ptr [[A_ADDR]], ptr [[TMP]], align 82587// CHECK12-NEXT:    store ptr [[C_ADDR]], ptr [[_TMP1]], align 82588// CHECK12-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]]2589// CHECK12-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 42590// CHECK12-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP2]], 12591// CHECK12-NEXT:    store i32 [[INC]], ptr [[TMP1]], align 42592// CHECK12-NEXT:    [[TMP3:%.*]] = load i32, ptr [[B_ADDR]], align 42593// CHECK12-NEXT:    [[DEC:%.*]] = add nsw i32 [[TMP3]], -12594// CHECK12-NEXT:    store i32 [[DEC]], ptr [[B_ADDR]], align 42595// CHECK12-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META6]]2596// CHECK12-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 42597// CHECK12-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP5]], 12598// CHECK12-NEXT:    store i32 [[DIV]], ptr [[TMP4]], align 42599// CHECK12-NEXT:    ret void2600//2601//2602// CHECK17-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPe2603// CHECK17-SAME: (ptr [[A:%.*]], ptr [[S:%.*]], i32 [[N:%.*]], ptr [[VLA1:%.*]]) #[[ATTR0:[0-9]+]] {2604// CHECK17-NEXT:  entry:2605// CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 82606// CHECK17-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 82607// CHECK17-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 42608// CHECK17-NEXT:    [[VLA1_ADDR:%.*]] = alloca ptr, align 82609// CHECK17-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 82610// CHECK17-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 82611// CHECK17-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 82612// CHECK17-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 82613// CHECK17-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 82614// CHECK17-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 42615// CHECK17-NEXT:    store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 82616// CHECK17-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 42617// CHECK17-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i642618// CHECK17-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 42619// CHECK17-NEXT:    [[TMP3:%.*]] = zext i32 [[TMP2]] to i642620// CHECK17-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 42621// CHECK17-NEXT:    [[TMP5:%.*]] = zext i32 [[TMP4]] to i642622// CHECK17-NEXT:    [[TMP6:%.*]] = call ptr @llvm.stacksave.p0()2623// CHECK17-NEXT:    store ptr [[TMP6]], ptr [[SAVED_STACK]], align 82624// CHECK17-NEXT:    [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]]2625// CHECK17-NEXT:    [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 1282626// CHECK17-NEXT:    store i64 [[TMP3]], ptr [[__VLA_EXPR0]], align 82627// CHECK17-NEXT:    store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 82628// CHECK17-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[S_ADDR]], align 82629// CHECK17-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 82630// CHECK17-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[A_ADDR]], align 82631// CHECK17-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 8, ptr @_Z10array_funcPfP2StiPe.omp_outlined, ptr [[TMP8]], ptr [[N_ADDR]], i64 [[TMP1]], ptr [[TMP9]], ptr [[TMP10]], i64 [[TMP3]], i64 [[TMP5]], ptr [[VLA]])2632// CHECK17-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 82633// CHECK17-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP11]])2634// CHECK17-NEXT:    ret void2635//2636//2637// CHECK17-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPe.omp_outlined2638// CHECK17-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr [[S:%.*]], ptr nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], ptr [[VLA1:%.*]], ptr [[A:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], ptr nonnull align 8 dereferenceable(8) [[VLA26:%.*]]) #[[ATTR2:[0-9]+]] {2639// CHECK17-NEXT:  entry:2640// CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 82641// CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 82642// CHECK17-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 82643// CHECK17-NEXT:    [[N_ADDR:%.*]] = alloca ptr, align 82644// CHECK17-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 82645// CHECK17-NEXT:    [[VLA1_ADDR:%.*]] = alloca ptr, align 82646// CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 82647// CHECK17-NEXT:    [[VLA_ADDR3:%.*]] = alloca i64, align 82648// CHECK17-NEXT:    [[VLA_ADDR5:%.*]] = alloca i64, align 82649// CHECK17-NEXT:    [[VLA2_ADDR:%.*]] = alloca ptr, align 82650// CHECK17-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 82651// CHECK17-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 82652// CHECK17-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 82653// CHECK17-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 82654// CHECK17-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 82655// CHECK17-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 82656// CHECK17-NEXT:    store ptr [[N]], ptr [[N_ADDR]], align 82657// CHECK17-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 82658// CHECK17-NEXT:    store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 82659// CHECK17-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 82660// CHECK17-NEXT:    store i64 [[VLA2]], ptr [[VLA_ADDR3]], align 82661// CHECK17-NEXT:    store i64 [[VLA4]], ptr [[VLA_ADDR5]], align 82662// CHECK17-NEXT:    store ptr [[VLA26]], ptr [[VLA2_ADDR]], align 82663// CHECK17-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[N_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]]2664// CHECK17-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 82665// CHECK17-NEXT:    [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR3]], align 82666// CHECK17-NEXT:    [[TMP3:%.*]] = load i64, ptr [[VLA_ADDR5]], align 82667// CHECK17-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[VLA2_ADDR]], align 8, !nonnull [[META3]], !align [[META5:![0-9]+]]2668// CHECK17-NEXT:    [[TMP5:%.*]] = call ptr @llvm.stacksave.p0()2669// CHECK17-NEXT:    store ptr [[TMP5]], ptr [[SAVED_STACK]], align 82670// CHECK17-NEXT:    [[TMP6:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]]2671// CHECK17-NEXT:    [[VLA7:%.*]] = alloca double, i64 [[TMP6]], align 1282672// CHECK17-NEXT:    store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 82673// CHECK17-NEXT:    store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 82674// CHECK17-NEXT:    [[TMP7:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]]2675// CHECK17-NEXT:    [[TMP8:%.*]] = mul nuw i64 [[TMP7]], 82676// CHECK17-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[VLA7]], ptr align 128 [[TMP4]], i64 [[TMP8]], i1 false)2677// CHECK17-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[S_ADDR]], align 82678// CHECK17-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[TMP9]], i64 02679// CHECK17-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[S_ADDR]], align 82680// CHECK17-NEXT:    [[TMP11:%.*]] = load i32, ptr [[TMP0]], align 42681// CHECK17-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 82682// CHECK17-NEXT:    call void @_ZN2St7St_funcEPS_iPe(ptr nonnull align 4 dereferenceable(8) [[ARRAYIDX]], ptr [[TMP10]], i32 [[TMP11]], ptr [[TMP12]])2683// CHECK17-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[SAVED_STACK]], align 82684// CHECK17-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP13]])2685// CHECK17-NEXT:    ret void2686//2687//2688// CHECK17-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPe2689// CHECK17-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]], ptr [[S:%.*]], i32 [[N:%.*]], ptr [[VLA1:%.*]]) #[[ATTR0]] align 2 {2690// CHECK17-NEXT:  entry:2691// CHECK17-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82692// CHECK17-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 82693// CHECK17-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 42694// CHECK17-NEXT:    [[VLA1_ADDR:%.*]] = alloca ptr, align 82695// CHECK17-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 82696// CHECK17-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 82697// CHECK17-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 82698// CHECK17-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82699// CHECK17-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 82700// CHECK17-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 42701// CHECK17-NEXT:    store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 82702// CHECK17-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82703// CHECK17-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 42704// CHECK17-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i642705// CHECK17-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 42706// CHECK17-NEXT:    [[TMP3:%.*]] = zext i32 [[TMP2]] to i642707// CHECK17-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 42708// CHECK17-NEXT:    [[TMP5:%.*]] = zext i32 [[TMP4]] to i642709// CHECK17-NEXT:    [[TMP6:%.*]] = call ptr @llvm.stacksave.p0()2710// CHECK17-NEXT:    store ptr [[TMP6]], ptr [[SAVED_STACK]], align 82711// CHECK17-NEXT:    [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]]2712// CHECK17-NEXT:    [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 1282713// CHECK17-NEXT:    store i64 [[TMP3]], ptr [[__VLA_EXPR0]], align 82714// CHECK17-NEXT:    store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 82715// CHECK17-NEXT:    [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 12716// CHECK17-NEXT:    [[TMP8:%.*]] = load i32, ptr [[B]], align 42717// CHECK17-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 02718// CHECK17-NEXT:    store i32 [[TMP8]], ptr [[A]], align 42719// CHECK17-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 82720// CHECK17-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[S_ADDR]], align 82721// CHECK17-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 8, ptr @_ZN2St7St_funcEPS_iPe.omp_outlined, i64 [[TMP1]], ptr [[TMP9]], ptr [[THIS1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[VLA]], ptr [[N_ADDR]], ptr [[TMP10]])2722// CHECK17-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 82723// CHECK17-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP11]])2724// CHECK17-NEXT:    ret void2725//2726//2727// CHECK17-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPe.omp_outlined2728// CHECK17-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], ptr [[VLA1:%.*]], ptr [[THIS:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], ptr nonnull align 8 dereferenceable(8) [[VLA26:%.*]], ptr nonnull align 4 dereferenceable(4) [[N:%.*]], ptr [[S:%.*]]) #[[ATTR2]] {2729// CHECK17-NEXT:  entry:2730// CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 82731// CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 82732// CHECK17-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 82733// CHECK17-NEXT:    [[VLA1_ADDR:%.*]] = alloca ptr, align 82734// CHECK17-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82735// CHECK17-NEXT:    [[VLA_ADDR3:%.*]] = alloca i64, align 82736// CHECK17-NEXT:    [[VLA_ADDR5:%.*]] = alloca i64, align 82737// CHECK17-NEXT:    [[VLA2_ADDR:%.*]] = alloca ptr, align 82738// CHECK17-NEXT:    [[N_ADDR:%.*]] = alloca ptr, align 82739// CHECK17-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 82740// CHECK17-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 82741// CHECK17-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 82742// CHECK17-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 82743// CHECK17-NEXT:    store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 82744// CHECK17-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82745// CHECK17-NEXT:    store i64 [[VLA2]], ptr [[VLA_ADDR3]], align 82746// CHECK17-NEXT:    store i64 [[VLA4]], ptr [[VLA_ADDR5]], align 82747// CHECK17-NEXT:    store ptr [[VLA26]], ptr [[VLA2_ADDR]], align 82748// CHECK17-NEXT:    store ptr [[N]], ptr [[N_ADDR]], align 82749// CHECK17-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 82750// CHECK17-NEXT:    [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 82751// CHECK17-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82752// CHECK17-NEXT:    [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR3]], align 82753// CHECK17-NEXT:    [[TMP3:%.*]] = load i64, ptr [[VLA_ADDR5]], align 82754// CHECK17-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[VLA2_ADDR]], align 8, !nonnull [[META3]], !align [[META5]]2755// CHECK17-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[N_ADDR]], align 8, !nonnull [[META3]], !align [[META4]]2756// CHECK17-NEXT:    [[TMP6:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]]2757// CHECK17-NEXT:    [[TMP7:%.*]] = mul nuw i64 [[TMP6]], 82758// CHECK17-NEXT:    [[TMP8:%.*]] = add nuw i64 [[TMP7]], 1272759// CHECK17-NEXT:    [[TMP9:%.*]] = udiv i64 [[TMP8]], 1282760// CHECK17-NEXT:    [[TMP10:%.*]] = mul nuw i64 [[TMP9]], 1282761// CHECK17-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 82762// CHECK17-NEXT:    [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 42763// CHECK17-NEXT:    [[DOTVLA2__VOID_ADDR:%.*]] = call ptr @__kmpc_alloc(i32 [[TMP12]], i64 [[TMP10]], ptr inttoptr (i64 8 to ptr))2764// CHECK17-NEXT:    [[TMP13:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]]2765// CHECK17-NEXT:    [[TMP14:%.*]] = mul nuw i64 [[TMP13]], 82766// CHECK17-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[DOTVLA2__VOID_ADDR]], ptr align 128 [[TMP4]], i64 [[TMP14]], i1 false)2767// CHECK17-NEXT:    [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[TMP1]], i32 0, i32 12768// CHECK17-NEXT:    [[TMP15:%.*]] = load i32, ptr [[B]], align 42769// CHECK17-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[TMP1]], i32 0, i32 02770// CHECK17-NEXT:    store i32 [[TMP15]], ptr [[A]], align 42771// CHECK17-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP15]] to double2772// CHECK17-NEXT:    [[TMP16:%.*]] = mul nsw i64 1, [[TMP3]]2773// CHECK17-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[DOTVLA2__VOID_ADDR]], i64 [[TMP16]]2774// CHECK17-NEXT:    [[TMP17:%.*]] = load i32, ptr [[TMP5]], align 42775// CHECK17-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP17]], 12776// CHECK17-NEXT:    [[IDXPROM:%.*]] = sext i32 [[SUB]] to i642777// CHECK17-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX]], i64 [[IDXPROM]]2778// CHECK17-NEXT:    store double [[CONV]], ptr [[ARRAYIDX7]], align 82779// CHECK17-NEXT:    [[CONV8:%.*]] = fpext double [[CONV]] to x86_fp802780// CHECK17-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 82781// CHECK17-NEXT:    [[B9:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[TMP1]], i32 0, i32 12782// CHECK17-NEXT:    [[TMP19:%.*]] = load i32, ptr [[B9]], align 42783// CHECK17-NEXT:    [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i642784// CHECK17-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds x86_fp80, ptr [[TMP18]], i64 [[IDXPROM10]]2785// CHECK17-NEXT:    store x86_fp80 [[CONV8]], ptr [[ARRAYIDX11]], align 162786// CHECK17-NEXT:    call void @__kmpc_free(i32 [[TMP12]], ptr [[DOTVLA2__VOID_ADDR]], ptr inttoptr (i64 8 to ptr))2787// CHECK17-NEXT:    ret void2788//2789