5118 lines · cpp
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _2// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK13// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK24 5// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s6// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK17 8// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s9// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK210 11// RUN: %clang_cc1 -verify -Wno-vla -triple x86_64-apple-darwin10 -fopenmp -fexceptions -fcxx-exceptions -debug-info-kind=line-tables-only -gno-column-info -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK512// RUN: %clang_cc1 -verify -Wno-vla -triple x86_64-apple-darwin10 -fopenmp -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK613 14// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"15// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s16// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"17// RUN: %clang_cc1 -verify -Wno-vla -triple x86_64-apple-darwin10 -fopenmp-simd -fexceptions -fcxx-exceptions -debug-info-kind=line-tables-only -x c++ -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"18// RUN: %clang_cc1 -verify -Wno-vla -triple x86_64-apple-darwin10 -fopenmp-simd -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"19// expected-no-diagnostics20 21// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK1122// RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s23// RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1124// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"25// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s26// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"27#ifndef HEADER28#define HEADER29 30#ifndef OMP531 32void with_var_schedule() {33 double a = 5;34 35#pragma omp parallel for schedule(static, char(a)) private(a)36 for (unsigned long long i = 1; i < 2 + a; ++i) {37 }38}39 40void without_schedule_clause(float *a, float *b, float *c, float *d) {41 #pragma omp parallel for42// UB = min(UB, GlobalUB)43// Loop header44 for (int i = 33; i < 32000000; i += 7) {45// Start of body: calculate i from IV:46// ... loop body ...47// End of body: store into a[i]:48 a[i] = b[i] * c[i] * d[i];49 }50}51 52void static_not_chunked(float *a, float *b, float *c, float *d) {53 #pragma omp parallel for schedule(static)54// UB = min(UB, GlobalUB)55// Loop header56 for (int i = 32000000; i > 33; i += -7) {57// Start of body: calculate i from IV:58// ... loop body ...59// End of body: store into a[i]:60 a[i] = b[i] * c[i] * d[i];61 }62}63 64void static_chunked(float *a, float *b, float *c, float *d) {65 #pragma omp parallel for schedule(static, 5)66// UB = min(UB, GlobalUB)67 68// Outer loop header69 70// Loop header71 for (unsigned i = 131071; i <= 2147483647; i += 127) {72// Start of body: calculate i from IV:73// ... loop body ...74// End of body: store into a[i]:75 a[i] = b[i] * c[i] * d[i];76 }77// Update the counters, adding stride78 79}80 81void dynamic1(float *a, float *b, float *c, float *d) {82 #pragma omp parallel for schedule(dynamic)83 84// Loop header85 86 for (unsigned long long i = 131071; i < 2147483647; i += 127) {87// Start of body: calculate i from IV:88// ... loop body ...89// End of body: store into a[i]:90 a[i] = b[i] * c[i] * d[i];91 }92}93 94void guided7(float *a, float *b, float *c, float *d) {95 #pragma omp parallel for schedule(guided, 7)96 97// Loop header98 99 for (unsigned long long i = 131071; i < 2147483647; i += 127) {100// Start of body: calculate i from IV:101// ... loop body ...102// End of body: store into a[i]:103 a[i] = b[i] * c[i] * d[i];104 }105}106 107void test_auto(float *a, float *b, float *c, float *d) {108 unsigned int x = 0;109 unsigned int y = 0;110 #pragma omp parallel for schedule(auto) collapse(2)111 112// Loop header113 114// FIXME: When the iteration count of some nested loop is not a known constant,115// we should pre-calculate it, like we do for the total number of iterations!116 for (char i = static_cast<char>(y); i <= '9'; ++i)117 for (x = 11; x > 0; --x) {118// Start of body: indices are calculated from IV:119// ... loop body ...120// End of body: store into a[i]:121 a[i] = b[i] * c[i] * d[i];122 }123}124 125void runtime(float *a, float *b, float *c, float *d) {126 int x = 0;127 #pragma omp parallel for collapse(2) schedule(runtime)128 129// Loop header130 131 for (unsigned char i = '0' ; i <= '9'; ++i)132 for (x = -10; x < 10; ++x) {133// Start of body: indices are calculated from IV:134// ... loop body ...135// End of body: store into a[i]:136 a[i] = b[i] * c[i] * d[i];137 }138}139 140int foo() { extern void mayThrow(); mayThrow(); return 0; };141 142void parallel_for(float *a, const int n) {143 float arr[n];144#pragma omp parallel for schedule(static, 5) private(arr) default(none) firstprivate(n) shared(a)145 for (unsigned i = 131071; i <= 2147483647; i += 127)146 a[i] += foo() + arr[i] + n;147}148// Check source line corresponds to "#pragma omp parallel for schedule(static, 5)" above:149 150#else // OMP5151int increment () {152 #pragma omp for153// Determine UB = min(UB, GlobalUB)154 155// Loop header156 157 for (int i = 0 ; i != 5; ++i)158// Start of body: calculate i from IV:159 ;160 return 0;161}162 163int decrement_nowait () {164 #pragma omp for nowait165// Determine UB = min(UB, GlobalUB)166 167// Loop header168 for (int j = 5 ; j != 0; --j)169// Start of body: calculate i from IV:170 ;171 return 0;172}173 174void range_for_single() {175 int arr[10] = {0};176#pragma omp parallel for177 for (auto &a : arr)178 (void)a;179}180 181 182// __range = arr;183 184// __end = end(_range);185 186 187// calculate number of elements.188 189// __begin = begin(range);190 191// __begin >= __end ? goto then : goto exit;192 193 194// lb = 0;195 196// ub = number of elements197 198// stride = 1;199 200// is_last = 0;201 202// loop.203 204// ub = (ub > number_of_elems ? number_of_elems : ub);205 206 207 208// OMP%: store i64 [[MIN]], ptr [[UB]],209 210// iv = lb;211 212// goto loop;213// loop:214 215 216// iv <= ub ? goto body : goto end;217 218// body:219// __begin = begin(arr) + iv * 1;220 221// a = *__begin;222 223// (void)a;224 225// iv += 1;226 227// goto loop;228 229// end:230// exit:231 232void range_for_collapsed() {233 int arr[10] = {0};234#pragma omp parallel for collapse(2)235 for (auto &a : arr)236 for (auto b : arr)237 a = b;238}239#endif // OMP5240 241#endif // HEADER242 243// CHECK1-LABEL: define {{[^@]+}}@_Z17with_var_schedulev244// CHECK1-SAME: () #[[ATTR0:[0-9]+]] {245// CHECK1-NEXT: entry:246// CHECK1-NEXT: [[A:%.*]] = alloca double, align 8247// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1248// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8249// CHECK1-NEXT: store double 5.000000e+00, ptr [[A]], align 8250// CHECK1-NEXT: [[TMP0:%.*]] = load double, ptr [[A]], align 8251// CHECK1-NEXT: [[CONV:%.*]] = fptosi double [[TMP0]] to i8252// CHECK1-NEXT: store i8 [[CONV]], ptr [[DOTCAPTURE_EXPR_]], align 1253// CHECK1-NEXT: [[TMP1:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1254// CHECK1-NEXT: store i8 [[TMP1]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1255// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8256// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 1, ptr @_Z17with_var_schedulev.omp_outlined, i64 [[TMP2]])257// CHECK1-NEXT: ret void258//259//260// CHECK1-LABEL: define {{[^@]+}}@_Z17with_var_schedulev.omp_outlined261// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] {262// CHECK1-NEXT: entry:263// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8264// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8265// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8266// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8267// CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8268// CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca double, align 8269// CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8270// CHECK1-NEXT: [[I:%.*]] = alloca i64, align 8271// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8272// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8273// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8274// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4275// CHECK1-NEXT: [[A:%.*]] = alloca double, align 8276// CHECK1-NEXT: [[I4:%.*]] = alloca i64, align 8277// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8278// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8279// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8280// CHECK1-NEXT: [[TMP0:%.*]] = load double, ptr undef, align 8281// CHECK1-NEXT: [[ADD:%.*]] = fadd double 2.000000e+00, [[TMP0]]282// CHECK1-NEXT: store double [[ADD]], ptr [[DOTCAPTURE_EXPR_1]], align 8283// CHECK1-NEXT: [[TMP1:%.*]] = load double, ptr [[DOTCAPTURE_EXPR_1]], align 8284// CHECK1-NEXT: [[SUB:%.*]] = fsub double [[TMP1]], 1.000000e+00285// CHECK1-NEXT: [[DIV:%.*]] = fdiv double [[SUB]], 1.000000e+00286// CHECK1-NEXT: [[CONV:%.*]] = fptoui double [[DIV]] to i64287// CHECK1-NEXT: [[SUB3:%.*]] = sub i64 [[CONV]], 1288// CHECK1-NEXT: store i64 [[SUB3]], ptr [[DOTCAPTURE_EXPR_2]], align 8289// CHECK1-NEXT: store i64 1, ptr [[I]], align 8290// CHECK1-NEXT: [[TMP2:%.*]] = load double, ptr [[DOTCAPTURE_EXPR_1]], align 8291// CHECK1-NEXT: [[CMP:%.*]] = fcmp olt double 1.000000e+00, [[TMP2]]292// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]293// CHECK1: omp.precond.then:294// CHECK1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8295// CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8296// CHECK1-NEXT: store i64 [[TMP3]], ptr [[DOTOMP_UB]], align 8297// CHECK1-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8298// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4299// CHECK1-NEXT: [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1300// CHECK1-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i64301// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8302// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4303// CHECK1-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 [[CONV5]])304// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]]305// CHECK1: omp.dispatch.cond:306// CHECK1-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8307// CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8308// CHECK1-NEXT: [[CMP6:%.*]] = icmp ugt i64 [[TMP7]], [[TMP8]]309// CHECK1-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]310// CHECK1: cond.true:311// CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8312// CHECK1-NEXT: br label [[COND_END:%.*]]313// CHECK1: cond.false:314// CHECK1-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8315// CHECK1-NEXT: br label [[COND_END]]316// CHECK1: cond.end:317// CHECK1-NEXT: [[COND:%.*]] = phi i64 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]318// CHECK1-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8319// CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8320// CHECK1-NEXT: store i64 [[TMP11]], ptr [[DOTOMP_IV]], align 8321// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8322// CHECK1-NEXT: [[TMP13:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8323// CHECK1-NEXT: [[ADD7:%.*]] = add i64 [[TMP13]], 1324// CHECK1-NEXT: [[CMP8:%.*]] = icmp ult i64 [[TMP12]], [[ADD7]]325// CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]326// CHECK1: omp.dispatch.body:327// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]328// CHECK1: omp.inner.for.cond:329// CHECK1-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8330// CHECK1-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8331// CHECK1-NEXT: [[ADD9:%.*]] = add i64 [[TMP15]], 1332// CHECK1-NEXT: [[CMP10:%.*]] = icmp ult i64 [[TMP14]], [[ADD9]]333// CHECK1-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]334// CHECK1: omp.inner.for.body:335// CHECK1-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8336// CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP16]], 1337// CHECK1-NEXT: [[ADD11:%.*]] = add i64 1, [[MUL]]338// CHECK1-NEXT: store i64 [[ADD11]], ptr [[I4]], align 8339// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]340// CHECK1: omp.body.continue:341// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]342// CHECK1: omp.inner.for.inc:343// CHECK1-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8344// CHECK1-NEXT: [[ADD12:%.*]] = add i64 [[TMP17]], 1345// CHECK1-NEXT: store i64 [[ADD12]], ptr [[DOTOMP_IV]], align 8346// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]347// CHECK1: omp.inner.for.end:348// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]349// CHECK1: omp.dispatch.inc:350// CHECK1-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8351// CHECK1-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_STRIDE]], align 8352// CHECK1-NEXT: [[ADD13:%.*]] = add i64 [[TMP18]], [[TMP19]]353// CHECK1-NEXT: store i64 [[ADD13]], ptr [[DOTOMP_LB]], align 8354// CHECK1-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8355// CHECK1-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_STRIDE]], align 8356// CHECK1-NEXT: [[ADD14:%.*]] = add i64 [[TMP20]], [[TMP21]]357// CHECK1-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_UB]], align 8358// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]359// CHECK1: omp.dispatch.end:360// CHECK1-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8361// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4362// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP23]])363// CHECK1-NEXT: br label [[OMP_PRECOND_END]]364// CHECK1: omp.precond.end:365// CHECK1-NEXT: ret void366//367//368// CHECK1-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_369// CHECK1-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {370// CHECK1-NEXT: entry:371// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8372// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8373// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8374// CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8375// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8376// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8377// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8378// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8379// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_Z23without_schedule_clausePfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])380// CHECK1-NEXT: ret void381//382//383// CHECK1-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_.omp_outlined384// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {385// CHECK1-NEXT: entry:386// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8387// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8388// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8389// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8390// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8391// CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8392// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4393// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4394// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4395// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4396// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4397// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4398// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4399// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8400// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8401// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8402// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8403// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8404// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8405// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8406// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8407// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8408// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8409// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4410// CHECK1-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 4411// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4412// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4413// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8414// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4415// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)416// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4417// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423418// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]419// CHECK1: cond.true:420// CHECK1-NEXT: br label [[COND_END:%.*]]421// CHECK1: cond.false:422// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4423// CHECK1-NEXT: br label [[COND_END]]424// CHECK1: cond.end:425// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]426// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4427// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4428// CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4429// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]430// CHECK1: omp.inner.for.cond:431// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4432// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4433// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]434// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]435// CHECK1: omp.inner.for.body:436// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4437// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7438// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]439// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4440// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 8441// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4442// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64443// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[IDXPROM]]444// CHECK1-NEXT: [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4445// CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP2]], align 8446// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4447// CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64448// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[IDXPROM2]]449// CHECK1-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX3]], align 4450// CHECK1-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]]451// CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP3]], align 8452// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4453// CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64454// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[IDXPROM5]]455// CHECK1-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX6]], align 4456// CHECK1-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]]457// CHECK1-NEXT: [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 8458// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[I]], align 4459// CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64460// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i64 [[IDXPROM8]]461// CHECK1-NEXT: store float [[MUL7]], ptr [[ARRAYIDX9]], align 4462// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]463// CHECK1: omp.body.continue:464// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]465// CHECK1: omp.inner.for.inc:466// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4467// CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP23]], 1468// CHECK1-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4469// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]470// CHECK1: omp.inner.for.end:471// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]472// CHECK1: omp.loop.exit:473// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])474// CHECK1-NEXT: ret void475//476//477// CHECK1-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_478// CHECK1-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {479// CHECK1-NEXT: entry:480// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8481// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8482// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8483// CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8484// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8485// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8486// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8487// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8488// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_Z18static_not_chunkedPfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])489// CHECK1-NEXT: ret void490//491//492// CHECK1-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_.omp_outlined493// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {494// CHECK1-NEXT: entry:495// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8496// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8497// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8498// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8499// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8500// CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8501// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4502// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4503// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4504// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4505// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4506// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4507// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4508// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8509// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8510// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8511// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8512// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8513// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8514// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8515// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8516// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8517// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8518// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4519// CHECK1-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 4520// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4521// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4522// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8523// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4524// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)525// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4526// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423527// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]528// CHECK1: cond.true:529// CHECK1-NEXT: br label [[COND_END:%.*]]530// CHECK1: cond.false:531// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4532// CHECK1-NEXT: br label [[COND_END]]533// CHECK1: cond.end:534// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]535// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4536// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4537// CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4538// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]539// CHECK1: omp.inner.for.cond:540// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4541// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4542// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]543// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]544// CHECK1: omp.inner.for.body:545// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4546// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7547// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]548// CHECK1-NEXT: store i32 [[SUB]], ptr [[I]], align 4549// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 8550// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4551// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64552// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[IDXPROM]]553// CHECK1-NEXT: [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4554// CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP2]], align 8555// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4556// CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64557// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[IDXPROM2]]558// CHECK1-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX3]], align 4559// CHECK1-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]]560// CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP3]], align 8561// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4562// CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64563// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[IDXPROM5]]564// CHECK1-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX6]], align 4565// CHECK1-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]]566// CHECK1-NEXT: [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 8567// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[I]], align 4568// CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64569// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i64 [[IDXPROM8]]570// CHECK1-NEXT: store float [[MUL7]], ptr [[ARRAYIDX9]], align 4571// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]572// CHECK1: omp.body.continue:573// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]574// CHECK1: omp.inner.for.inc:575// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4576// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1577// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4578// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]579// CHECK1: omp.inner.for.end:580// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]581// CHECK1: omp.loop.exit:582// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])583// CHECK1-NEXT: ret void584//585//586// CHECK1-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_587// CHECK1-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {588// CHECK1-NEXT: entry:589// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8590// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8591// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8592// CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8593// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8594// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8595// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8596// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8597// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_Z14static_chunkedPfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])598// CHECK1-NEXT: ret void599//600//601// CHECK1-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_.omp_outlined602// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {603// CHECK1-NEXT: entry:604// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8605// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8606// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8607// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8608// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8609// CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8610// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4611// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4612// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4613// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4614// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4615// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4616// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4617// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8618// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8619// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8620// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8621// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8622// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8623// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8624// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8625// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8626// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8627// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4628// CHECK1-NEXT: store i32 16908288, ptr [[DOTOMP_UB]], align 4629// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4630// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4631// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8632// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4633// CHECK1-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP5]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5)634// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]]635// CHECK1: omp.dispatch.cond:636// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4637// CHECK1-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288638// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]639// CHECK1: cond.true:640// CHECK1-NEXT: br label [[COND_END:%.*]]641// CHECK1: cond.false:642// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4643// CHECK1-NEXT: br label [[COND_END]]644// CHECK1: cond.end:645// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]646// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4647// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4648// CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4649// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4650// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4651// CHECK1-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]652// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]653// CHECK1: omp.dispatch.body:654// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]655// CHECK1: omp.inner.for.cond:656// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4657// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4658// CHECK1-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]659// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]660// CHECK1: omp.inner.for.body:661// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4662// CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127663// CHECK1-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]664// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4665// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP1]], align 8666// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4667// CHECK1-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64668// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP14]], i64 [[IDXPROM]]669// CHECK1-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4670// CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP2]], align 8671// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4672// CHECK1-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64673// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw float, ptr [[TMP17]], i64 [[IDXPROM3]]674// CHECK1-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4675// CHECK1-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]676// CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP3]], align 8677// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4678// CHECK1-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64679// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds nuw float, ptr [[TMP20]], i64 [[IDXPROM6]]680// CHECK1-NEXT: [[TMP22:%.*]] = load float, ptr [[ARRAYIDX7]], align 4681// CHECK1-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]682// CHECK1-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP0]], align 8683// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[I]], align 4684// CHECK1-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64685// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds nuw float, ptr [[TMP23]], i64 [[IDXPROM9]]686// CHECK1-NEXT: store float [[MUL8]], ptr [[ARRAYIDX10]], align 4687// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]688// CHECK1: omp.body.continue:689// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]690// CHECK1: omp.inner.for.inc:691// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4692// CHECK1-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1693// CHECK1-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4694// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]695// CHECK1: omp.inner.for.end:696// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]697// CHECK1: omp.dispatch.inc:698// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4699// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4700// CHECK1-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]701// CHECK1-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_LB]], align 4702// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4703// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4704// CHECK1-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]]705// CHECK1-NEXT: store i32 [[ADD13]], ptr [[DOTOMP_UB]], align 4706// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]707// CHECK1: omp.dispatch.end:708// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])709// CHECK1-NEXT: ret void710//711//712// CHECK1-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_713// CHECK1-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {714// CHECK1-NEXT: entry:715// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8716// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8717// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8718// CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8719// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8720// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8721// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8722// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8723// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_Z8dynamic1PfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])724// CHECK1-NEXT: ret void725//726//727// CHECK1-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_.omp_outlined728// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {729// CHECK1-NEXT: entry:730// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8731// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8732// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8733// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8734// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8735// CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8736// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8737// CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8738// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8739// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8740// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8741// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4742// CHECK1-NEXT: [[I:%.*]] = alloca i64, align 8743// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8744// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8745// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8746// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8747// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8748// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8749// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8750// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8751// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8752// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8753// CHECK1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8754// CHECK1-NEXT: store i64 16908287, ptr [[DOTOMP_UB]], align 8755// CHECK1-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8756// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4757// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8758// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4759// CHECK1-NEXT: call void @__kmpc_dispatch_init_8u(ptr @[[GLOB2]], i32 [[TMP5]], i32 1073741859, i64 0, i64 16908287, i64 1, i64 1)760// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]]761// CHECK1: omp.dispatch.cond:762// CHECK1-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8u(ptr @[[GLOB2]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])763// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0764// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]765// CHECK1: omp.dispatch.body:766// CHECK1-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8767// CHECK1-NEXT: store i64 [[TMP7]], ptr [[DOTOMP_IV]], align 8768// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]769// CHECK1: omp.inner.for.cond:770// CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5:![0-9]+]]771// CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP5]]772// CHECK1-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1773// CHECK1-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]]774// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]775// CHECK1: omp.inner.for.body:776// CHECK1-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]]777// CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127778// CHECK1-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]]779// CHECK1-NEXT: store i64 [[ADD1]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP5]]780// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP5]]781// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP5]]782// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP11]], i64 [[TMP12]]783// CHECK1-NEXT: [[TMP13:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]]784// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP5]]785// CHECK1-NEXT: [[TMP15:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP5]]786// CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw float, ptr [[TMP14]], i64 [[TMP15]]787// CHECK1-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP5]]788// CHECK1-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]]789// CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP5]]790// CHECK1-NEXT: [[TMP18:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP5]]791// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw float, ptr [[TMP17]], i64 [[TMP18]]792// CHECK1-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP5]]793// CHECK1-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]]794// CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP5]]795// CHECK1-NEXT: [[TMP21:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP5]]796// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds nuw float, ptr [[TMP20]], i64 [[TMP21]]797// CHECK1-NEXT: store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP5]]798// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]799// CHECK1: omp.body.continue:800// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]801// CHECK1: omp.inner.for.inc:802// CHECK1-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]]803// CHECK1-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1804// CHECK1-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]]805// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]806// CHECK1: omp.inner.for.end:807// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]808// CHECK1: omp.dispatch.inc:809// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]810// CHECK1: omp.dispatch.end:811// CHECK1-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB2]], i32 [[TMP5]])812// CHECK1-NEXT: ret void813//814//815// CHECK1-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_816// CHECK1-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {817// CHECK1-NEXT: entry:818// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8819// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8820// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8821// CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8822// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8823// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8824// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8825// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8826// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_Z7guided7PfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])827// CHECK1-NEXT: ret void828//829//830// CHECK1-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_.omp_outlined831// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {832// CHECK1-NEXT: entry:833// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8834// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8835// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8836// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8837// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8838// CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8839// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8840// CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8841// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8842// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8843// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8844// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4845// CHECK1-NEXT: [[I:%.*]] = alloca i64, align 8846// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8847// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8848// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8849// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8850// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8851// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8852// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8853// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8854// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8855// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8856// CHECK1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8857// CHECK1-NEXT: store i64 16908287, ptr [[DOTOMP_UB]], align 8858// CHECK1-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8859// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4860// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8861// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4862// CHECK1-NEXT: call void @__kmpc_dispatch_init_8u(ptr @[[GLOB2]], i32 [[TMP5]], i32 1073741860, i64 0, i64 16908287, i64 1, i64 7)863// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]]864// CHECK1: omp.dispatch.cond:865// CHECK1-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8u(ptr @[[GLOB2]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])866// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0867// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]868// CHECK1: omp.dispatch.body:869// CHECK1-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8870// CHECK1-NEXT: store i64 [[TMP7]], ptr [[DOTOMP_IV]], align 8871// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]872// CHECK1: omp.inner.for.cond:873// CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP8:![0-9]+]]874// CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP8]]875// CHECK1-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1876// CHECK1-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]]877// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]878// CHECK1: omp.inner.for.body:879// CHECK1-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP8]]880// CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127881// CHECK1-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]]882// CHECK1-NEXT: store i64 [[ADD1]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP8]]883// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP8]]884// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP8]]885// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP11]], i64 [[TMP12]]886// CHECK1-NEXT: [[TMP13:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP8]]887// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP8]]888// CHECK1-NEXT: [[TMP15:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP8]]889// CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw float, ptr [[TMP14]], i64 [[TMP15]]890// CHECK1-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP8]]891// CHECK1-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]]892// CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP8]]893// CHECK1-NEXT: [[TMP18:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP8]]894// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw float, ptr [[TMP17]], i64 [[TMP18]]895// CHECK1-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP8]]896// CHECK1-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]]897// CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP8]]898// CHECK1-NEXT: [[TMP21:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP8]]899// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds nuw float, ptr [[TMP20]], i64 [[TMP21]]900// CHECK1-NEXT: store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP8]]901// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]902// CHECK1: omp.body.continue:903// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]904// CHECK1: omp.inner.for.inc:905// CHECK1-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP8]]906// CHECK1-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1907// CHECK1-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP8]]908// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]909// CHECK1: omp.inner.for.end:910// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]911// CHECK1: omp.dispatch.inc:912// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]913// CHECK1: omp.dispatch.end:914// CHECK1-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB2]], i32 [[TMP5]])915// CHECK1-NEXT: ret void916//917//918// CHECK1-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_919// CHECK1-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {920// CHECK1-NEXT: entry:921// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8922// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8923// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8924// CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8925// CHECK1-NEXT: [[X:%.*]] = alloca i32, align 4926// CHECK1-NEXT: [[Y:%.*]] = alloca i32, align 4927// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8928// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8929// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8930// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8931// CHECK1-NEXT: store i32 0, ptr [[X]], align 4932// CHECK1-NEXT: store i32 0, ptr [[Y]], align 4933// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @_Z9test_autoPfS_S_S_.omp_outlined, ptr [[Y]], ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])934// CHECK1-NEXT: ret void935//936//937// CHECK1-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_.omp_outlined938// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[Y:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {939// CHECK1-NEXT: entry:940// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8941// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8942// CHECK1-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 8943// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8944// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8945// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8946// CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8947// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8948// CHECK1-NEXT: [[TMP:%.*]] = alloca i8, align 1949// CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4950// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1951// CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8952// CHECK1-NEXT: [[I:%.*]] = alloca i8, align 1953// CHECK1-NEXT: [[X:%.*]] = alloca i32, align 4954// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8955// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8956// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8957// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4958// CHECK1-NEXT: [[I7:%.*]] = alloca i8, align 1959// CHECK1-NEXT: [[X8:%.*]] = alloca i32, align 4960// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8961// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8962// CHECK1-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 8963// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8964// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8965// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8966// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8967// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 8968// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8969// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8970// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8971// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[D_ADDR]], align 8972// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4973// CHECK1-NEXT: [[CONV:%.*]] = trunc i32 [[TMP5]] to i8974// CHECK1-NEXT: store i8 [[CONV]], ptr [[DOTCAPTURE_EXPR_]], align 1975// CHECK1-NEXT: [[TMP6:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1976// CHECK1-NEXT: [[CONV3:%.*]] = sext i8 [[TMP6]] to i32977// CHECK1-NEXT: [[SUB:%.*]] = sub i32 57, [[CONV3]]978// CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB]], 1979// CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1980// CHECK1-NEXT: [[CONV4:%.*]] = zext i32 [[DIV]] to i64981// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11982// CHECK1-NEXT: [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1983// CHECK1-NEXT: store i64 [[SUB5]], ptr [[DOTCAPTURE_EXPR_2]], align 8984// CHECK1-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1985// CHECK1-NEXT: store i8 [[TMP7]], ptr [[I]], align 1986// CHECK1-NEXT: store i32 11, ptr [[X]], align 4987// CHECK1-NEXT: [[TMP8:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1988// CHECK1-NEXT: [[CONV6:%.*]] = sext i8 [[TMP8]] to i32989// CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV6]], 57990// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]991// CHECK1: omp.precond.then:992// CHECK1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8993// CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8994// CHECK1-NEXT: store i64 [[TMP9]], ptr [[DOTOMP_UB]], align 8995// CHECK1-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8996// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4997// CHECK1-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8998// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8999// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 41000// CHECK1-NEXT: call void @__kmpc_dispatch_init_8(ptr @[[GLOB2]], i32 [[TMP12]], i32 1073741862, i64 0, i64 [[TMP10]], i64 1, i64 1)1001// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]]1002// CHECK1: omp.dispatch.cond:1003// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81004// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 41005// CHECK1-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_dispatch_next_8(ptr @[[GLOB2]], i32 [[TMP14]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])1006// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 01007// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]1008// CHECK1: omp.dispatch.body:1009// CHECK1-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_LB]], align 81010// CHECK1-NEXT: store i64 [[TMP16]], ptr [[DOTOMP_IV]], align 81011// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1012// CHECK1: omp.inner.for.cond:1013// CHECK1-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11:![0-9]+]]1014// CHECK1-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP11]]1015// CHECK1-NEXT: [[CMP9:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]]1016// CHECK1-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1017// CHECK1: omp.inner.for.body:1018// CHECK1-NEXT: [[TMP19:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP11]]1019// CHECK1-NEXT: [[CONV10:%.*]] = sext i8 [[TMP19]] to i641020// CHECK1-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11]]1021// CHECK1-NEXT: [[DIV11:%.*]] = sdiv i64 [[TMP20]], 111022// CHECK1-NEXT: [[MUL12:%.*]] = mul nsw i64 [[DIV11]], 11023// CHECK1-NEXT: [[ADD13:%.*]] = add nsw i64 [[CONV10]], [[MUL12]]1024// CHECK1-NEXT: [[CONV14:%.*]] = trunc i64 [[ADD13]] to i81025// CHECK1-NEXT: store i8 [[CONV14]], ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP11]]1026// CHECK1-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11]]1027// CHECK1-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11]]1028// CHECK1-NEXT: [[DIV15:%.*]] = sdiv i64 [[TMP22]], 111029// CHECK1-NEXT: [[MUL16:%.*]] = mul nsw i64 [[DIV15]], 111030// CHECK1-NEXT: [[SUB17:%.*]] = sub nsw i64 [[TMP21]], [[MUL16]]1031// CHECK1-NEXT: [[MUL18:%.*]] = mul nsw i64 [[SUB17]], 11032// CHECK1-NEXT: [[SUB19:%.*]] = sub nsw i64 11, [[MUL18]]1033// CHECK1-NEXT: [[CONV20:%.*]] = trunc i64 [[SUB19]] to i321034// CHECK1-NEXT: store i32 [[CONV20]], ptr [[X8]], align 4, !llvm.access.group [[ACC_GRP11]]1035// CHECK1-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP11]]1036// CHECK1-NEXT: [[TMP24:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP11]]1037// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP24]] to i641038// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i64 [[IDXPROM]]1039// CHECK1-NEXT: [[TMP25:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP11]]1040// CHECK1-NEXT: [[TMP26:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP11]]1041// CHECK1-NEXT: [[TMP27:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP11]]1042// CHECK1-NEXT: [[IDXPROM21:%.*]] = sext i8 [[TMP27]] to i641043// CHECK1-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds float, ptr [[TMP26]], i64 [[IDXPROM21]]1044// CHECK1-NEXT: [[TMP28:%.*]] = load float, ptr [[ARRAYIDX22]], align 4, !llvm.access.group [[ACC_GRP11]]1045// CHECK1-NEXT: [[MUL23:%.*]] = fmul float [[TMP25]], [[TMP28]]1046// CHECK1-NEXT: [[TMP29:%.*]] = load ptr, ptr [[TMP4]], align 8, !llvm.access.group [[ACC_GRP11]]1047// CHECK1-NEXT: [[TMP30:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP11]]1048// CHECK1-NEXT: [[IDXPROM24:%.*]] = sext i8 [[TMP30]] to i641049// CHECK1-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds float, ptr [[TMP29]], i64 [[IDXPROM24]]1050// CHECK1-NEXT: [[TMP31:%.*]] = load float, ptr [[ARRAYIDX25]], align 4, !llvm.access.group [[ACC_GRP11]]1051// CHECK1-NEXT: [[MUL26:%.*]] = fmul float [[MUL23]], [[TMP31]]1052// CHECK1-NEXT: [[TMP32:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP11]]1053// CHECK1-NEXT: [[TMP33:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP11]]1054// CHECK1-NEXT: [[IDXPROM27:%.*]] = sext i8 [[TMP33]] to i641055// CHECK1-NEXT: [[ARRAYIDX28:%.*]] = getelementptr inbounds float, ptr [[TMP32]], i64 [[IDXPROM27]]1056// CHECK1-NEXT: store float [[MUL26]], ptr [[ARRAYIDX28]], align 4, !llvm.access.group [[ACC_GRP11]]1057// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1058// CHECK1: omp.body.continue:1059// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1060// CHECK1: omp.inner.for.inc:1061// CHECK1-NEXT: [[TMP34:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11]]1062// CHECK1-NEXT: [[ADD29:%.*]] = add nsw i64 [[TMP34]], 11063// CHECK1-NEXT: store i64 [[ADD29]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11]]1064// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]1065// CHECK1: omp.inner.for.end:1066// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]1067// CHECK1: omp.dispatch.inc:1068// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]1069// CHECK1: omp.dispatch.end:1070// CHECK1-NEXT: [[TMP35:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81071// CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[TMP35]], align 41072// CHECK1-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB2]], i32 [[TMP36]])1073// CHECK1-NEXT: br label [[OMP_PRECOND_END]]1074// CHECK1: omp.precond.end:1075// CHECK1-NEXT: ret void1076//1077//1078// CHECK1-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_1079// CHECK1-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {1080// CHECK1-NEXT: entry:1081// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 81082// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 81083// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 81084// CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 81085// CHECK1-NEXT: [[X:%.*]] = alloca i32, align 41086// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 81087// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 81088// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 81089// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 81090// CHECK1-NEXT: store i32 0, ptr [[X]], align 41091// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_Z7runtimePfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])1092// CHECK1-NEXT: ret void1093//1094//1095// CHECK1-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_.omp_outlined1096// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {1097// CHECK1-NEXT: entry:1098// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81099// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81100// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 81101// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 81102// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 81103// CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 81104// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41105// CHECK1-NEXT: [[TMP:%.*]] = alloca i8, align 11106// CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 41107// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 41108// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 41109// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41110// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41111// CHECK1-NEXT: [[I:%.*]] = alloca i8, align 11112// CHECK1-NEXT: [[X:%.*]] = alloca i32, align 41113// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81114// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81115// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 81116// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 81117// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 81118// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 81119// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 81120// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 81121// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 81122// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 81123// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 41124// CHECK1-NEXT: store i32 199, ptr [[DOTOMP_UB]], align 41125// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 41126// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41127// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81128// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 41129// CHECK1-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB2]], i32 [[TMP5]], i32 1073741861, i32 0, i32 199, i32 1, i32 1)1130// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]]1131// CHECK1: omp.dispatch.cond:1132// CHECK1-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB2]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])1133// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 01134// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]1135// CHECK1: omp.dispatch.body:1136// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41137// CHECK1-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 41138// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1139// CHECK1: omp.inner.for.cond:1140// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14:![0-9]+]]1141// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP14]]1142// CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]1143// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1144// CHECK1: omp.inner.for.body:1145// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]1146// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 201147// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 11148// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]]1149// CHECK1-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i81150// CHECK1-NEXT: store i8 [[CONV]], ptr [[I]], align 1, !llvm.access.group [[ACC_GRP14]]1151// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]1152// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]1153// CHECK1-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP12]], 201154// CHECK1-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 201155// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL3]]1156// CHECK1-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 11157// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 -10, [[MUL4]]1158// CHECK1-NEXT: store i32 [[ADD5]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP14]]1159// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP14]]1160// CHECK1-NEXT: [[TMP14:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP14]]1161// CHECK1-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP14]] to i641162// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP13]], i64 [[IDXPROM]]1163// CHECK1-NEXT: [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP14]]1164// CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP14]]1165// CHECK1-NEXT: [[TMP17:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP14]]1166// CHECK1-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP17]] to i641167// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds nuw float, ptr [[TMP16]], i64 [[IDXPROM6]]1168// CHECK1-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP14]]1169// CHECK1-NEXT: [[MUL8:%.*]] = fmul float [[TMP15]], [[TMP18]]1170// CHECK1-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP14]]1171// CHECK1-NEXT: [[TMP20:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP14]]1172// CHECK1-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP20]] to i641173// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds nuw float, ptr [[TMP19]], i64 [[IDXPROM9]]1174// CHECK1-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP14]]1175// CHECK1-NEXT: [[MUL11:%.*]] = fmul float [[MUL8]], [[TMP21]]1176// CHECK1-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP14]]1177// CHECK1-NEXT: [[TMP23:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP14]]1178// CHECK1-NEXT: [[IDXPROM12:%.*]] = zext i8 [[TMP23]] to i641179// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds nuw float, ptr [[TMP22]], i64 [[IDXPROM12]]1180// CHECK1-NEXT: store float [[MUL11]], ptr [[ARRAYIDX13]], align 4, !llvm.access.group [[ACC_GRP14]]1181// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1182// CHECK1: omp.body.continue:1183// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1184// CHECK1: omp.inner.for.inc:1185// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]1186// CHECK1-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP24]], 11187// CHECK1-NEXT: store i32 [[ADD14]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]1188// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]1189// CHECK1: omp.inner.for.end:1190// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]1191// CHECK1: omp.dispatch.inc:1192// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]1193// CHECK1: omp.dispatch.end:1194// CHECK1-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB2]], i32 [[TMP5]])1195// CHECK1-NEXT: ret void1196//1197//1198// CHECK1-LABEL: define {{[^@]+}}@_Z3foov1199// CHECK1-SAME: () #[[ATTR3:[0-9]+]] {1200// CHECK1-NEXT: entry:1201// CHECK1-NEXT: call void @_Z8mayThrowv()1202// CHECK1-NEXT: ret i32 01203//1204//1205// CHECK1-LABEL: define {{[^@]+}}@_Z12parallel_forPfi1206// CHECK1-SAME: (ptr noundef [[A:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] {1207// CHECK1-NEXT: entry:1208// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 81209// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 41210// CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 81211// CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 81212// CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 81213// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 81214// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 41215// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 41216// CHECK1-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i641217// CHECK1-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()1218// CHECK1-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 81219// CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 161220// CHECK1-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 81221// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 41222// CHECK1-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 41223// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 81224// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @_Z12parallel_forPfi.omp_outlined, ptr [[A_ADDR]], i64 [[TMP1]], i64 [[TMP4]])1225// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[SAVED_STACK]], align 81226// CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP5]])1227// CHECK1-NEXT: ret void1228//1229//1230// CHECK1-LABEL: define {{[^@]+}}@_Z12parallel_forPfi.omp_outlined1231// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[N:%.*]]) #[[ATTR1]] personality ptr @__gxx_personality_v0 {1232// CHECK1-NEXT: entry:1233// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81234// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81235// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 81236// CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 81237// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 81238// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41239// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 41240// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 41241// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 41242// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41243// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41244// CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 81245// CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 81246// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 41247// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81248// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81249// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 81250// CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 81251// CHECK1-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 81252// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 81253// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 81254// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 41255// CHECK1-NEXT: store i32 16908288, ptr [[DOTOMP_UB]], align 41256// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 41257// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41258// CHECK1-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()1259// CHECK1-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 81260// CHECK1-NEXT: [[VLA1:%.*]] = alloca float, i64 [[TMP1]], align 161261// CHECK1-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 81262// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81263// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 41264// CHECK1-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5)1265// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]]1266// CHECK1: omp.dispatch.cond:1267// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41268// CHECK1-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP5]], 169082881269// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1270// CHECK1: cond.true:1271// CHECK1-NEXT: br label [[COND_END:%.*]]1272// CHECK1: cond.false:1273// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41274// CHECK1-NEXT: br label [[COND_END]]1275// CHECK1: cond.end:1276// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]1277// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 41278// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41279// CHECK1-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 41280// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41281// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41282// CHECK1-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP8]], [[TMP9]]1283// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_CLEANUP:%.*]]1284// CHECK1: omp.dispatch.cleanup:1285// CHECK1-NEXT: br label [[OMP_DISPATCH_END:%.*]]1286// CHECK1: omp.dispatch.body:1287// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1288// CHECK1: omp.inner.for.cond:1289// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41290// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41291// CHECK1-NEXT: [[CMP3:%.*]] = icmp ule i32 [[TMP10]], [[TMP11]]1292// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]1293// CHECK1: omp.inner.for.cond.cleanup:1294// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]1295// CHECK1: omp.inner.for.body:1296// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41297// CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP12]], 1271298// CHECK1-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]1299// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 41300// CHECK1-NEXT: [[CALL:%.*]] = invoke noundef i32 @_Z3foov()1301// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]]1302// CHECK1: invoke.cont:1303// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[CALL]] to float1304// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 41305// CHECK1-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP13]] to i641306// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[VLA1]], i64 [[IDXPROM]]1307// CHECK1-NEXT: [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 41308// CHECK1-NEXT: [[ADD4:%.*]] = fadd float [[CONV]], [[TMP14]]1309// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[N_ADDR]], align 41310// CHECK1-NEXT: [[CONV5:%.*]] = sitofp i32 [[TMP15]] to float1311// CHECK1-NEXT: [[ADD6:%.*]] = fadd float [[ADD4]], [[CONV5]]1312// CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP0]], align 81313// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 41314// CHECK1-NEXT: [[IDXPROM7:%.*]] = zext i32 [[TMP17]] to i641315// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds nuw float, ptr [[TMP16]], i64 [[IDXPROM7]]1316// CHECK1-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX8]], align 41317// CHECK1-NEXT: [[ADD9:%.*]] = fadd float [[TMP18]], [[ADD6]]1318// CHECK1-NEXT: store float [[ADD9]], ptr [[ARRAYIDX8]], align 41319// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1320// CHECK1: omp.body.continue:1321// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1322// CHECK1: omp.inner.for.inc:1323// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41324// CHECK1-NEXT: [[ADD10:%.*]] = add i32 [[TMP19]], 11325// CHECK1-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 41326// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]1327// CHECK1: omp.inner.for.end:1328// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]1329// CHECK1: omp.dispatch.inc:1330// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41331// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 41332// CHECK1-NEXT: [[ADD11:%.*]] = add i32 [[TMP20]], [[TMP21]]1333// CHECK1-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_LB]], align 41334// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41335// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 41336// CHECK1-NEXT: [[ADD12:%.*]] = add i32 [[TMP22]], [[TMP23]]1337// CHECK1-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_UB]], align 41338// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]1339// CHECK1: omp.dispatch.end:1340// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP4]])1341// CHECK1-NEXT: [[TMP24:%.*]] = load ptr, ptr [[SAVED_STACK]], align 81342// CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP24]])1343// CHECK1-NEXT: ret void1344// CHECK1: terminate.lpad:1345// CHECK1-NEXT: [[TMP25:%.*]] = landingpad { ptr, i32 }1346// CHECK1-NEXT: catch ptr null1347// CHECK1-NEXT: [[TMP26:%.*]] = extractvalue { ptr, i32 } [[TMP25]], 01348// CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP26]]) #[[ATTR7:[0-9]+]]1349// CHECK1-NEXT: unreachable1350//1351//1352// CHECK1-LABEL: define {{[^@]+}}@__clang_call_terminate1353// CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR6:[0-9]+]] comdat {1354// CHECK1-NEXT: [[TMP2:%.*]] = call ptr @__cxa_begin_catch(ptr [[TMP0]]) #[[ATTR2:[0-9]+]]1355// CHECK1-NEXT: call void @_ZSt9terminatev() #[[ATTR7]]1356// CHECK1-NEXT: unreachable1357//1358//1359// CHECK2-LABEL: define {{[^@]+}}@_Z17with_var_schedulev1360// CHECK2-SAME: () #[[ATTR0:[0-9]+]] {1361// CHECK2-NEXT: entry:1362// CHECK2-NEXT: [[A:%.*]] = alloca double, align 81363// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 11364// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 81365// CHECK2-NEXT: store double 5.000000e+00, ptr [[A]], align 81366// CHECK2-NEXT: [[TMP0:%.*]] = load double, ptr [[A]], align 81367// CHECK2-NEXT: [[CONV:%.*]] = fptosi double [[TMP0]] to i81368// CHECK2-NEXT: store i8 [[CONV]], ptr [[DOTCAPTURE_EXPR_]], align 11369// CHECK2-NEXT: [[TMP1:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 11370// CHECK2-NEXT: store i8 [[TMP1]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 11371// CHECK2-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 81372// CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 1, ptr @_Z17with_var_schedulev.omp_outlined, i64 [[TMP2]])1373// CHECK2-NEXT: ret void1374//1375//1376// CHECK2-LABEL: define {{[^@]+}}@_Z17with_var_schedulev.omp_outlined1377// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] {1378// CHECK2-NEXT: entry:1379// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81380// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81381// CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 81382// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 81383// CHECK2-NEXT: [[TMP:%.*]] = alloca i64, align 81384// CHECK2-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca double, align 81385// CHECK2-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 81386// CHECK2-NEXT: [[I:%.*]] = alloca i64, align 81387// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 81388// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 81389// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 81390// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41391// CHECK2-NEXT: [[A:%.*]] = alloca double, align 81392// CHECK2-NEXT: [[I4:%.*]] = alloca i64, align 81393// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81394// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81395// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 81396// CHECK2-NEXT: [[TMP0:%.*]] = load double, ptr undef, align 81397// CHECK2-NEXT: [[ADD:%.*]] = fadd double 2.000000e+00, [[TMP0]]1398// CHECK2-NEXT: store double [[ADD]], ptr [[DOTCAPTURE_EXPR_1]], align 81399// CHECK2-NEXT: [[TMP1:%.*]] = load double, ptr [[DOTCAPTURE_EXPR_1]], align 81400// CHECK2-NEXT: [[SUB:%.*]] = fsub double [[TMP1]], 1.000000e+001401// CHECK2-NEXT: [[DIV:%.*]] = fdiv double [[SUB]], 1.000000e+001402// CHECK2-NEXT: [[CONV:%.*]] = fptoui double [[DIV]] to i641403// CHECK2-NEXT: [[SUB3:%.*]] = sub i64 [[CONV]], 11404// CHECK2-NEXT: store i64 [[SUB3]], ptr [[DOTCAPTURE_EXPR_2]], align 81405// CHECK2-NEXT: store i64 1, ptr [[I]], align 81406// CHECK2-NEXT: [[TMP2:%.*]] = load double, ptr [[DOTCAPTURE_EXPR_1]], align 81407// CHECK2-NEXT: [[CMP:%.*]] = fcmp olt double 1.000000e+00, [[TMP2]]1408// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]1409// CHECK2: omp.precond.then:1410// CHECK2-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 81411// CHECK2-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 81412// CHECK2-NEXT: store i64 [[TMP3]], ptr [[DOTOMP_UB]], align 81413// CHECK2-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 81414// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41415// CHECK2-NEXT: [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 11416// CHECK2-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i641417// CHECK2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81418// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 41419// CHECK2-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 [[CONV5]])1420// CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]]1421// CHECK2: omp.dispatch.cond:1422// CHECK2-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 81423// CHECK2-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 81424// CHECK2-NEXT: [[CMP6:%.*]] = icmp ugt i64 [[TMP7]], [[TMP8]]1425// CHECK2-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1426// CHECK2: cond.true:1427// CHECK2-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 81428// CHECK2-NEXT: br label [[COND_END:%.*]]1429// CHECK2: cond.false:1430// CHECK2-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 81431// CHECK2-NEXT: br label [[COND_END]]1432// CHECK2: cond.end:1433// CHECK2-NEXT: [[COND:%.*]] = phi i64 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]1434// CHECK2-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 81435// CHECK2-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_LB]], align 81436// CHECK2-NEXT: store i64 [[TMP11]], ptr [[DOTOMP_IV]], align 81437// CHECK2-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 81438// CHECK2-NEXT: [[TMP13:%.*]] = load i64, ptr [[DOTOMP_UB]], align 81439// CHECK2-NEXT: [[ADD7:%.*]] = add i64 [[TMP13]], 11440// CHECK2-NEXT: [[CMP8:%.*]] = icmp ult i64 [[TMP12]], [[ADD7]]1441// CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]1442// CHECK2: omp.dispatch.body:1443// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1444// CHECK2: omp.inner.for.cond:1445// CHECK2-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 81446// CHECK2-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_UB]], align 81447// CHECK2-NEXT: [[ADD9:%.*]] = add i64 [[TMP15]], 11448// CHECK2-NEXT: [[CMP10:%.*]] = icmp ult i64 [[TMP14]], [[ADD9]]1449// CHECK2-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1450// CHECK2: omp.inner.for.body:1451// CHECK2-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 81452// CHECK2-NEXT: [[MUL:%.*]] = mul i64 [[TMP16]], 11453// CHECK2-NEXT: [[ADD11:%.*]] = add i64 1, [[MUL]]1454// CHECK2-NEXT: store i64 [[ADD11]], ptr [[I4]], align 81455// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1456// CHECK2: omp.body.continue:1457// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1458// CHECK2: omp.inner.for.inc:1459// CHECK2-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 81460// CHECK2-NEXT: [[ADD12:%.*]] = add i64 [[TMP17]], 11461// CHECK2-NEXT: store i64 [[ADD12]], ptr [[DOTOMP_IV]], align 81462// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]1463// CHECK2: omp.inner.for.end:1464// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]1465// CHECK2: omp.dispatch.inc:1466// CHECK2-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTOMP_LB]], align 81467// CHECK2-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_STRIDE]], align 81468// CHECK2-NEXT: [[ADD13:%.*]] = add i64 [[TMP18]], [[TMP19]]1469// CHECK2-NEXT: store i64 [[ADD13]], ptr [[DOTOMP_LB]], align 81470// CHECK2-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_UB]], align 81471// CHECK2-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_STRIDE]], align 81472// CHECK2-NEXT: [[ADD14:%.*]] = add i64 [[TMP20]], [[TMP21]]1473// CHECK2-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_UB]], align 81474// CHECK2-NEXT: br label [[OMP_DISPATCH_COND]]1475// CHECK2: omp.dispatch.end:1476// CHECK2-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81477// CHECK2-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 41478// CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP23]])1479// CHECK2-NEXT: br label [[OMP_PRECOND_END]]1480// CHECK2: omp.precond.end:1481// CHECK2-NEXT: ret void1482//1483//1484// CHECK2-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_1485// CHECK2-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {1486// CHECK2-NEXT: entry:1487// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 81488// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 81489// CHECK2-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 81490// CHECK2-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 81491// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 81492// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 81493// CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 81494// CHECK2-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 81495// CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_Z23without_schedule_clausePfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])1496// CHECK2-NEXT: ret void1497//1498//1499// CHECK2-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_.omp_outlined1500// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {1501// CHECK2-NEXT: entry:1502// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81503// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81504// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 81505// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 81506// CHECK2-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 81507// CHECK2-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 81508// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41509// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 41510// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 41511// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 41512// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41513// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41514// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 41515// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81516// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81517// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 81518// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 81519// CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 81520// CHECK2-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 81521// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 81522// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 81523// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 81524// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 81525// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 41526// CHECK2-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 41527// CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 41528// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41529// CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81530// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 41531// CHECK2-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1532// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41533// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 45714231534// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1535// CHECK2: cond.true:1536// CHECK2-NEXT: br label [[COND_END:%.*]]1537// CHECK2: cond.false:1538// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41539// CHECK2-NEXT: br label [[COND_END]]1540// CHECK2: cond.end:1541// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]1542// CHECK2-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 41543// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41544// CHECK2-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 41545// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1546// CHECK2: omp.inner.for.cond:1547// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41548// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41549// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]1550// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1551// CHECK2: omp.inner.for.body:1552// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41553// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 71554// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]1555// CHECK2-NEXT: store i32 [[ADD]], ptr [[I]], align 41556// CHECK2-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 81557// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 41558// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i641559// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[IDXPROM]]1560// CHECK2-NEXT: [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 41561// CHECK2-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP2]], align 81562// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 41563// CHECK2-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i641564// CHECK2-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[IDXPROM2]]1565// CHECK2-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX3]], align 41566// CHECK2-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]]1567// CHECK2-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP3]], align 81568// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 41569// CHECK2-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i641570// CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[IDXPROM5]]1571// CHECK2-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX6]], align 41572// CHECK2-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]]1573// CHECK2-NEXT: [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 81574// CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[I]], align 41575// CHECK2-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i641576// CHECK2-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i64 [[IDXPROM8]]1577// CHECK2-NEXT: store float [[MUL7]], ptr [[ARRAYIDX9]], align 41578// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1579// CHECK2: omp.body.continue:1580// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1581// CHECK2: omp.inner.for.inc:1582// CHECK2-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41583// CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP23]], 11584// CHECK2-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 41585// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]1586// CHECK2: omp.inner.for.end:1587// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]1588// CHECK2: omp.loop.exit:1589// CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])1590// CHECK2-NEXT: ret void1591//1592//1593// CHECK2-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_1594// CHECK2-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {1595// CHECK2-NEXT: entry:1596// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 81597// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 81598// CHECK2-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 81599// CHECK2-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 81600// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 81601// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 81602// CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 81603// CHECK2-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 81604// CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_Z18static_not_chunkedPfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])1605// CHECK2-NEXT: ret void1606//1607//1608// CHECK2-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_.omp_outlined1609// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {1610// CHECK2-NEXT: entry:1611// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81612// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81613// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 81614// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 81615// CHECK2-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 81616// CHECK2-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 81617// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41618// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 41619// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 41620// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 41621// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41622// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41623// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 41624// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81625// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81626// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 81627// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 81628// CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 81629// CHECK2-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 81630// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 81631// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 81632// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 81633// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 81634// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 41635// CHECK2-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 41636// CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 41637// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41638// CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81639// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 41640// CHECK2-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1641// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41642// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 45714231643// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1644// CHECK2: cond.true:1645// CHECK2-NEXT: br label [[COND_END:%.*]]1646// CHECK2: cond.false:1647// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41648// CHECK2-NEXT: br label [[COND_END]]1649// CHECK2: cond.end:1650// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]1651// CHECK2-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 41652// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41653// CHECK2-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 41654// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1655// CHECK2: omp.inner.for.cond:1656// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41657// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41658// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]1659// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1660// CHECK2: omp.inner.for.body:1661// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41662// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 71663// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]1664// CHECK2-NEXT: store i32 [[SUB]], ptr [[I]], align 41665// CHECK2-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 81666// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 41667// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i641668// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[IDXPROM]]1669// CHECK2-NEXT: [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 41670// CHECK2-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP2]], align 81671// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 41672// CHECK2-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i641673// CHECK2-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[IDXPROM2]]1674// CHECK2-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX3]], align 41675// CHECK2-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]]1676// CHECK2-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP3]], align 81677// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 41678// CHECK2-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i641679// CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[IDXPROM5]]1680// CHECK2-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX6]], align 41681// CHECK2-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]]1682// CHECK2-NEXT: [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 81683// CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[I]], align 41684// CHECK2-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i641685// CHECK2-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i64 [[IDXPROM8]]1686// CHECK2-NEXT: store float [[MUL7]], ptr [[ARRAYIDX9]], align 41687// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1688// CHECK2: omp.body.continue:1689// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1690// CHECK2: omp.inner.for.inc:1691// CHECK2-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41692// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 11693// CHECK2-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 41694// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]1695// CHECK2: omp.inner.for.end:1696// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]1697// CHECK2: omp.loop.exit:1698// CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])1699// CHECK2-NEXT: ret void1700//1701//1702// CHECK2-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_1703// CHECK2-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {1704// CHECK2-NEXT: entry:1705// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 81706// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 81707// CHECK2-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 81708// CHECK2-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 81709// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 81710// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 81711// CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 81712// CHECK2-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 81713// CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_Z14static_chunkedPfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])1714// CHECK2-NEXT: ret void1715//1716//1717// CHECK2-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_.omp_outlined1718// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {1719// CHECK2-NEXT: entry:1720// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81721// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81722// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 81723// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 81724// CHECK2-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 81725// CHECK2-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 81726// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41727// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 41728// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 41729// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 41730// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41731// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41732// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 41733// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81734// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81735// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 81736// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 81737// CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 81738// CHECK2-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 81739// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 81740// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 81741// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 81742// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 81743// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 41744// CHECK2-NEXT: store i32 16908288, ptr [[DOTOMP_UB]], align 41745// CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 41746// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41747// CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81748// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 41749// CHECK2-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP5]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5)1750// CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]]1751// CHECK2: omp.dispatch.cond:1752// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41753// CHECK2-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 169082881754// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1755// CHECK2: cond.true:1756// CHECK2-NEXT: br label [[COND_END:%.*]]1757// CHECK2: cond.false:1758// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41759// CHECK2-NEXT: br label [[COND_END]]1760// CHECK2: cond.end:1761// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]1762// CHECK2-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 41763// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41764// CHECK2-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 41765// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41766// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41767// CHECK2-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]1768// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]1769// CHECK2: omp.dispatch.body:1770// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1771// CHECK2: omp.inner.for.cond:1772// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41773// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41774// CHECK2-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]1775// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1776// CHECK2: omp.inner.for.body:1777// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41778// CHECK2-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 1271779// CHECK2-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]1780// CHECK2-NEXT: store i32 [[ADD]], ptr [[I]], align 41781// CHECK2-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP1]], align 81782// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 41783// CHECK2-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i641784// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP14]], i64 [[IDXPROM]]1785// CHECK2-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 41786// CHECK2-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP2]], align 81787// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 41788// CHECK2-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i641789// CHECK2-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw float, ptr [[TMP17]], i64 [[IDXPROM3]]1790// CHECK2-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 41791// CHECK2-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]1792// CHECK2-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP3]], align 81793// CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 41794// CHECK2-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i641795// CHECK2-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds nuw float, ptr [[TMP20]], i64 [[IDXPROM6]]1796// CHECK2-NEXT: [[TMP22:%.*]] = load float, ptr [[ARRAYIDX7]], align 41797// CHECK2-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]1798// CHECK2-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP0]], align 81799// CHECK2-NEXT: [[TMP24:%.*]] = load i32, ptr [[I]], align 41800// CHECK2-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i641801// CHECK2-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds nuw float, ptr [[TMP23]], i64 [[IDXPROM9]]1802// CHECK2-NEXT: store float [[MUL8]], ptr [[ARRAYIDX10]], align 41803// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1804// CHECK2: omp.body.continue:1805// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1806// CHECK2: omp.inner.for.inc:1807// CHECK2-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41808// CHECK2-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 11809// CHECK2-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 41810// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]1811// CHECK2: omp.inner.for.end:1812// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]1813// CHECK2: omp.dispatch.inc:1814// CHECK2-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41815// CHECK2-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 41816// CHECK2-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]1817// CHECK2-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_LB]], align 41818// CHECK2-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41819// CHECK2-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 41820// CHECK2-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]]1821// CHECK2-NEXT: store i32 [[ADD13]], ptr [[DOTOMP_UB]], align 41822// CHECK2-NEXT: br label [[OMP_DISPATCH_COND]]1823// CHECK2: omp.dispatch.end:1824// CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])1825// CHECK2-NEXT: ret void1826//1827//1828// CHECK2-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_1829// CHECK2-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {1830// CHECK2-NEXT: entry:1831// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 81832// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 81833// CHECK2-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 81834// CHECK2-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 81835// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 81836// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 81837// CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 81838// CHECK2-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 81839// CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_Z8dynamic1PfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])1840// CHECK2-NEXT: ret void1841//1842//1843// CHECK2-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_.omp_outlined1844// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {1845// CHECK2-NEXT: entry:1846// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81847// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81848// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 81849// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 81850// CHECK2-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 81851// CHECK2-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 81852// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 81853// CHECK2-NEXT: [[TMP:%.*]] = alloca i64, align 81854// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 81855// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 81856// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 81857// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41858// CHECK2-NEXT: [[I:%.*]] = alloca i64, align 81859// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81860// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81861// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 81862// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 81863// CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 81864// CHECK2-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 81865// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 81866// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 81867// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 81868// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 81869// CHECK2-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 81870// CHECK2-NEXT: store i64 16908287, ptr [[DOTOMP_UB]], align 81871// CHECK2-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 81872// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41873// CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81874// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 41875// CHECK2-NEXT: call void @__kmpc_dispatch_init_8u(ptr @[[GLOB2]], i32 [[TMP5]], i32 35, i64 0, i64 16908287, i64 1, i64 1)1876// CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]]1877// CHECK2: omp.dispatch.cond:1878// CHECK2-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8u(ptr @[[GLOB2]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])1879// CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 01880// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]1881// CHECK2: omp.dispatch.body:1882// CHECK2-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_LB]], align 81883// CHECK2-NEXT: store i64 [[TMP7]], ptr [[DOTOMP_IV]], align 81884// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1885// CHECK2: omp.inner.for.cond:1886// CHECK2-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5:![0-9]+]]1887// CHECK2-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP5]]1888// CHECK2-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 11889// CHECK2-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]]1890// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1891// CHECK2: omp.inner.for.body:1892// CHECK2-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]]1893// CHECK2-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 1271894// CHECK2-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]]1895// CHECK2-NEXT: store i64 [[ADD1]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP5]]1896// CHECK2-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP5]]1897// CHECK2-NEXT: [[TMP12:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP5]]1898// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP11]], i64 [[TMP12]]1899// CHECK2-NEXT: [[TMP13:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]]1900// CHECK2-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP5]]1901// CHECK2-NEXT: [[TMP15:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP5]]1902// CHECK2-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw float, ptr [[TMP14]], i64 [[TMP15]]1903// CHECK2-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP5]]1904// CHECK2-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]]1905// CHECK2-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP5]]1906// CHECK2-NEXT: [[TMP18:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP5]]1907// CHECK2-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw float, ptr [[TMP17]], i64 [[TMP18]]1908// CHECK2-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP5]]1909// CHECK2-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]]1910// CHECK2-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP5]]1911// CHECK2-NEXT: [[TMP21:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP5]]1912// CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds nuw float, ptr [[TMP20]], i64 [[TMP21]]1913// CHECK2-NEXT: store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP5]]1914// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1915// CHECK2: omp.body.continue:1916// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1917// CHECK2: omp.inner.for.inc:1918// CHECK2-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]]1919// CHECK2-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 11920// CHECK2-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]]1921// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]1922// CHECK2: omp.inner.for.end:1923// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]1924// CHECK2: omp.dispatch.inc:1925// CHECK2-NEXT: br label [[OMP_DISPATCH_COND]]1926// CHECK2: omp.dispatch.end:1927// CHECK2-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB2]], i32 [[TMP5]])1928// CHECK2-NEXT: ret void1929//1930//1931// CHECK2-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_1932// CHECK2-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {1933// CHECK2-NEXT: entry:1934// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 81935// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 81936// CHECK2-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 81937// CHECK2-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 81938// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 81939// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 81940// CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 81941// CHECK2-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 81942// CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_Z7guided7PfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])1943// CHECK2-NEXT: ret void1944//1945//1946// CHECK2-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_.omp_outlined1947// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {1948// CHECK2-NEXT: entry:1949// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81950// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81951// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 81952// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 81953// CHECK2-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 81954// CHECK2-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 81955// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 81956// CHECK2-NEXT: [[TMP:%.*]] = alloca i64, align 81957// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 81958// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 81959// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 81960// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41961// CHECK2-NEXT: [[I:%.*]] = alloca i64, align 81962// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81963// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81964// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 81965// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 81966// CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 81967// CHECK2-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 81968// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 81969// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 81970// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 81971// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 81972// CHECK2-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 81973// CHECK2-NEXT: store i64 16908287, ptr [[DOTOMP_UB]], align 81974// CHECK2-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 81975// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41976// CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81977// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 41978// CHECK2-NEXT: call void @__kmpc_dispatch_init_8u(ptr @[[GLOB2]], i32 [[TMP5]], i32 36, i64 0, i64 16908287, i64 1, i64 7)1979// CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]]1980// CHECK2: omp.dispatch.cond:1981// CHECK2-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8u(ptr @[[GLOB2]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])1982// CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 01983// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]1984// CHECK2: omp.dispatch.body:1985// CHECK2-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_LB]], align 81986// CHECK2-NEXT: store i64 [[TMP7]], ptr [[DOTOMP_IV]], align 81987// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1988// CHECK2: omp.inner.for.cond:1989// CHECK2-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP8:![0-9]+]]1990// CHECK2-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP8]]1991// CHECK2-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 11992// CHECK2-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]]1993// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1994// CHECK2: omp.inner.for.body:1995// CHECK2-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP8]]1996// CHECK2-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 1271997// CHECK2-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]]1998// CHECK2-NEXT: store i64 [[ADD1]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP8]]1999// CHECK2-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP8]]2000// CHECK2-NEXT: [[TMP12:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP8]]2001// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP11]], i64 [[TMP12]]2002// CHECK2-NEXT: [[TMP13:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP8]]2003// CHECK2-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP8]]2004// CHECK2-NEXT: [[TMP15:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP8]]2005// CHECK2-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw float, ptr [[TMP14]], i64 [[TMP15]]2006// CHECK2-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP8]]2007// CHECK2-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]]2008// CHECK2-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP8]]2009// CHECK2-NEXT: [[TMP18:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP8]]2010// CHECK2-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw float, ptr [[TMP17]], i64 [[TMP18]]2011// CHECK2-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP8]]2012// CHECK2-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]]2013// CHECK2-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP8]]2014// CHECK2-NEXT: [[TMP21:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP8]]2015// CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds nuw float, ptr [[TMP20]], i64 [[TMP21]]2016// CHECK2-NEXT: store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP8]]2017// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]2018// CHECK2: omp.body.continue:2019// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]2020// CHECK2: omp.inner.for.inc:2021// CHECK2-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP8]]2022// CHECK2-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 12023// CHECK2-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP8]]2024// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]2025// CHECK2: omp.inner.for.end:2026// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]2027// CHECK2: omp.dispatch.inc:2028// CHECK2-NEXT: br label [[OMP_DISPATCH_COND]]2029// CHECK2: omp.dispatch.end:2030// CHECK2-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB2]], i32 [[TMP5]])2031// CHECK2-NEXT: ret void2032//2033//2034// CHECK2-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_2035// CHECK2-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {2036// CHECK2-NEXT: entry:2037// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 82038// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 82039// CHECK2-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 82040// CHECK2-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 82041// CHECK2-NEXT: [[X:%.*]] = alloca i32, align 42042// CHECK2-NEXT: [[Y:%.*]] = alloca i32, align 42043// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 82044// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 82045// CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 82046// CHECK2-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 82047// CHECK2-NEXT: store i32 0, ptr [[X]], align 42048// CHECK2-NEXT: store i32 0, ptr [[Y]], align 42049// CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @_Z9test_autoPfS_S_S_.omp_outlined, ptr [[Y]], ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])2050// CHECK2-NEXT: ret void2051//2052//2053// CHECK2-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_.omp_outlined2054// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[Y:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {2055// CHECK2-NEXT: entry:2056// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 82057// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 82058// CHECK2-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 82059// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 82060// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 82061// CHECK2-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 82062// CHECK2-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 82063// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 82064// CHECK2-NEXT: [[TMP:%.*]] = alloca i8, align 12065// CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 42066// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 12067// CHECK2-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 82068// CHECK2-NEXT: [[I:%.*]] = alloca i8, align 12069// CHECK2-NEXT: [[X:%.*]] = alloca i32, align 42070// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 82071// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 82072// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 82073// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42074// CHECK2-NEXT: [[I7:%.*]] = alloca i8, align 12075// CHECK2-NEXT: [[X8:%.*]] = alloca i32, align 42076// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 82077// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 82078// CHECK2-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 82079// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 82080// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 82081// CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 82082// CHECK2-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 82083// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 82084// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 82085// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 82086// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 82087// CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[D_ADDR]], align 82088// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 42089// CHECK2-NEXT: [[CONV:%.*]] = trunc i32 [[TMP5]] to i82090// CHECK2-NEXT: store i8 [[CONV]], ptr [[DOTCAPTURE_EXPR_]], align 12091// CHECK2-NEXT: [[TMP6:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 12092// CHECK2-NEXT: [[CONV3:%.*]] = sext i8 [[TMP6]] to i322093// CHECK2-NEXT: [[SUB:%.*]] = sub i32 57, [[CONV3]]2094// CHECK2-NEXT: [[ADD:%.*]] = add i32 [[SUB]], 12095// CHECK2-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 12096// CHECK2-NEXT: [[CONV4:%.*]] = zext i32 [[DIV]] to i642097// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV4]], 112098// CHECK2-NEXT: [[SUB5:%.*]] = sub nsw i64 [[MUL]], 12099// CHECK2-NEXT: store i64 [[SUB5]], ptr [[DOTCAPTURE_EXPR_2]], align 82100// CHECK2-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 12101// CHECK2-NEXT: store i8 [[TMP7]], ptr [[I]], align 12102// CHECK2-NEXT: store i32 11, ptr [[X]], align 42103// CHECK2-NEXT: [[TMP8:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 12104// CHECK2-NEXT: [[CONV6:%.*]] = sext i8 [[TMP8]] to i322105// CHECK2-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV6]], 572106// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]2107// CHECK2: omp.precond.then:2108// CHECK2-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 82109// CHECK2-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 82110// CHECK2-NEXT: store i64 [[TMP9]], ptr [[DOTOMP_UB]], align 82111// CHECK2-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 82112// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 42113// CHECK2-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 82114// CHECK2-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 82115// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 42116// CHECK2-NEXT: call void @__kmpc_dispatch_init_8(ptr @[[GLOB2]], i32 [[TMP12]], i32 38, i64 0, i64 [[TMP10]], i64 1, i64 1)2117// CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]]2118// CHECK2: omp.dispatch.cond:2119// CHECK2-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 82120// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 42121// CHECK2-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_dispatch_next_8(ptr @[[GLOB2]], i32 [[TMP14]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])2122// CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 02123// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]2124// CHECK2: omp.dispatch.body:2125// CHECK2-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_LB]], align 82126// CHECK2-NEXT: store i64 [[TMP16]], ptr [[DOTOMP_IV]], align 82127// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]2128// CHECK2: omp.inner.for.cond:2129// CHECK2-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11:![0-9]+]]2130// CHECK2-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP11]]2131// CHECK2-NEXT: [[CMP9:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]]2132// CHECK2-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2133// CHECK2: omp.inner.for.body:2134// CHECK2-NEXT: [[TMP19:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP11]]2135// CHECK2-NEXT: [[CONV10:%.*]] = sext i8 [[TMP19]] to i642136// CHECK2-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11]]2137// CHECK2-NEXT: [[DIV11:%.*]] = sdiv i64 [[TMP20]], 112138// CHECK2-NEXT: [[MUL12:%.*]] = mul nsw i64 [[DIV11]], 12139// CHECK2-NEXT: [[ADD13:%.*]] = add nsw i64 [[CONV10]], [[MUL12]]2140// CHECK2-NEXT: [[CONV14:%.*]] = trunc i64 [[ADD13]] to i82141// CHECK2-NEXT: store i8 [[CONV14]], ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP11]]2142// CHECK2-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11]]2143// CHECK2-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11]]2144// CHECK2-NEXT: [[DIV15:%.*]] = sdiv i64 [[TMP22]], 112145// CHECK2-NEXT: [[MUL16:%.*]] = mul nsw i64 [[DIV15]], 112146// CHECK2-NEXT: [[SUB17:%.*]] = sub nsw i64 [[TMP21]], [[MUL16]]2147// CHECK2-NEXT: [[MUL18:%.*]] = mul nsw i64 [[SUB17]], 12148// CHECK2-NEXT: [[SUB19:%.*]] = sub nsw i64 11, [[MUL18]]2149// CHECK2-NEXT: [[CONV20:%.*]] = trunc i64 [[SUB19]] to i322150// CHECK2-NEXT: store i32 [[CONV20]], ptr [[X8]], align 4, !llvm.access.group [[ACC_GRP11]]2151// CHECK2-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP11]]2152// CHECK2-NEXT: [[TMP24:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP11]]2153// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP24]] to i642154// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i64 [[IDXPROM]]2155// CHECK2-NEXT: [[TMP25:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP11]]2156// CHECK2-NEXT: [[TMP26:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP11]]2157// CHECK2-NEXT: [[TMP27:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP11]]2158// CHECK2-NEXT: [[IDXPROM21:%.*]] = sext i8 [[TMP27]] to i642159// CHECK2-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds float, ptr [[TMP26]], i64 [[IDXPROM21]]2160// CHECK2-NEXT: [[TMP28:%.*]] = load float, ptr [[ARRAYIDX22]], align 4, !llvm.access.group [[ACC_GRP11]]2161// CHECK2-NEXT: [[MUL23:%.*]] = fmul float [[TMP25]], [[TMP28]]2162// CHECK2-NEXT: [[TMP29:%.*]] = load ptr, ptr [[TMP4]], align 8, !llvm.access.group [[ACC_GRP11]]2163// CHECK2-NEXT: [[TMP30:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP11]]2164// CHECK2-NEXT: [[IDXPROM24:%.*]] = sext i8 [[TMP30]] to i642165// CHECK2-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds float, ptr [[TMP29]], i64 [[IDXPROM24]]2166// CHECK2-NEXT: [[TMP31:%.*]] = load float, ptr [[ARRAYIDX25]], align 4, !llvm.access.group [[ACC_GRP11]]2167// CHECK2-NEXT: [[MUL26:%.*]] = fmul float [[MUL23]], [[TMP31]]2168// CHECK2-NEXT: [[TMP32:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP11]]2169// CHECK2-NEXT: [[TMP33:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP11]]2170// CHECK2-NEXT: [[IDXPROM27:%.*]] = sext i8 [[TMP33]] to i642171// CHECK2-NEXT: [[ARRAYIDX28:%.*]] = getelementptr inbounds float, ptr [[TMP32]], i64 [[IDXPROM27]]2172// CHECK2-NEXT: store float [[MUL26]], ptr [[ARRAYIDX28]], align 4, !llvm.access.group [[ACC_GRP11]]2173// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]2174// CHECK2: omp.body.continue:2175// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]2176// CHECK2: omp.inner.for.inc:2177// CHECK2-NEXT: [[TMP34:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11]]2178// CHECK2-NEXT: [[ADD29:%.*]] = add nsw i64 [[TMP34]], 12179// CHECK2-NEXT: store i64 [[ADD29]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11]]2180// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]2181// CHECK2: omp.inner.for.end:2182// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]2183// CHECK2: omp.dispatch.inc:2184// CHECK2-NEXT: br label [[OMP_DISPATCH_COND]]2185// CHECK2: omp.dispatch.end:2186// CHECK2-NEXT: [[TMP35:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 82187// CHECK2-NEXT: [[TMP36:%.*]] = load i32, ptr [[TMP35]], align 42188// CHECK2-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB2]], i32 [[TMP36]])2189// CHECK2-NEXT: br label [[OMP_PRECOND_END]]2190// CHECK2: omp.precond.end:2191// CHECK2-NEXT: ret void2192//2193//2194// CHECK2-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_2195// CHECK2-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {2196// CHECK2-NEXT: entry:2197// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 82198// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 82199// CHECK2-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 82200// CHECK2-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 82201// CHECK2-NEXT: [[X:%.*]] = alloca i32, align 42202// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 82203// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 82204// CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 82205// CHECK2-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 82206// CHECK2-NEXT: store i32 0, ptr [[X]], align 42207// CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_Z7runtimePfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])2208// CHECK2-NEXT: ret void2209//2210//2211// CHECK2-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_.omp_outlined2212// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {2213// CHECK2-NEXT: entry:2214// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 82215// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 82216// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 82217// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 82218// CHECK2-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 82219// CHECK2-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 82220// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 42221// CHECK2-NEXT: [[TMP:%.*]] = alloca i8, align 12222// CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 42223// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 42224// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 42225// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42226// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42227// CHECK2-NEXT: [[I:%.*]] = alloca i8, align 12228// CHECK2-NEXT: [[X:%.*]] = alloca i32, align 42229// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 82230// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 82231// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 82232// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 82233// CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 82234// CHECK2-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 82235// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 82236// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 82237// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 82238// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 82239// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 42240// CHECK2-NEXT: store i32 199, ptr [[DOTOMP_UB]], align 42241// CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 42242// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 42243// CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 82244// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 42245// CHECK2-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB2]], i32 [[TMP5]], i32 37, i32 0, i32 199, i32 1, i32 1)2246// CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]]2247// CHECK2: omp.dispatch.cond:2248// CHECK2-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB2]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])2249// CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 02250// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]2251// CHECK2: omp.dispatch.body:2252// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42253// CHECK2-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 42254// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]2255// CHECK2: omp.inner.for.cond:2256// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14:![0-9]+]]2257// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP14]]2258// CHECK2-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]2259// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2260// CHECK2: omp.inner.for.body:2261// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]2262// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 202263// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 12264// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]]2265// CHECK2-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i82266// CHECK2-NEXT: store i8 [[CONV]], ptr [[I]], align 1, !llvm.access.group [[ACC_GRP14]]2267// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]2268// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]2269// CHECK2-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP12]], 202270// CHECK2-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 202271// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL3]]2272// CHECK2-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 12273// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 -10, [[MUL4]]2274// CHECK2-NEXT: store i32 [[ADD5]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP14]]2275// CHECK2-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP14]]2276// CHECK2-NEXT: [[TMP14:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP14]]2277// CHECK2-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP14]] to i642278// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP13]], i64 [[IDXPROM]]2279// CHECK2-NEXT: [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP14]]2280// CHECK2-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP14]]2281// CHECK2-NEXT: [[TMP17:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP14]]2282// CHECK2-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP17]] to i642283// CHECK2-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds nuw float, ptr [[TMP16]], i64 [[IDXPROM6]]2284// CHECK2-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP14]]2285// CHECK2-NEXT: [[MUL8:%.*]] = fmul float [[TMP15]], [[TMP18]]2286// CHECK2-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP14]]2287// CHECK2-NEXT: [[TMP20:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP14]]2288// CHECK2-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP20]] to i642289// CHECK2-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds nuw float, ptr [[TMP19]], i64 [[IDXPROM9]]2290// CHECK2-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP14]]2291// CHECK2-NEXT: [[MUL11:%.*]] = fmul float [[MUL8]], [[TMP21]]2292// CHECK2-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP14]]2293// CHECK2-NEXT: [[TMP23:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP14]]2294// CHECK2-NEXT: [[IDXPROM12:%.*]] = zext i8 [[TMP23]] to i642295// CHECK2-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds nuw float, ptr [[TMP22]], i64 [[IDXPROM12]]2296// CHECK2-NEXT: store float [[MUL11]], ptr [[ARRAYIDX13]], align 4, !llvm.access.group [[ACC_GRP14]]2297// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]2298// CHECK2: omp.body.continue:2299// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]2300// CHECK2: omp.inner.for.inc:2301// CHECK2-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]2302// CHECK2-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP24]], 12303// CHECK2-NEXT: store i32 [[ADD14]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]2304// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]2305// CHECK2: omp.inner.for.end:2306// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]2307// CHECK2: omp.dispatch.inc:2308// CHECK2-NEXT: br label [[OMP_DISPATCH_COND]]2309// CHECK2: omp.dispatch.end:2310// CHECK2-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB2]], i32 [[TMP5]])2311// CHECK2-NEXT: ret void2312//2313//2314// CHECK2-LABEL: define {{[^@]+}}@_Z3foov2315// CHECK2-SAME: () #[[ATTR3:[0-9]+]] {2316// CHECK2-NEXT: entry:2317// CHECK2-NEXT: call void @_Z8mayThrowv()2318// CHECK2-NEXT: ret i32 02319//2320//2321// CHECK2-LABEL: define {{[^@]+}}@_Z12parallel_forPfi2322// CHECK2-SAME: (ptr noundef [[A:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] {2323// CHECK2-NEXT: entry:2324// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 82325// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 42326// CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 82327// CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 82328// CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i64, align 82329// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 82330// CHECK2-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 42331// CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 42332// CHECK2-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i642333// CHECK2-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()2334// CHECK2-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 82335// CHECK2-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 162336// CHECK2-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 82337// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 42338// CHECK2-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 42339// CHECK2-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 82340// CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @_Z12parallel_forPfi.omp_outlined, ptr [[A_ADDR]], i64 [[TMP1]], i64 [[TMP4]])2341// CHECK2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[SAVED_STACK]], align 82342// CHECK2-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP5]])2343// CHECK2-NEXT: ret void2344//2345//2346// CHECK2-LABEL: define {{[^@]+}}@_Z12parallel_forPfi.omp_outlined2347// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[N:%.*]]) #[[ATTR1]] personality ptr @__gxx_personality_v0 {2348// CHECK2-NEXT: entry:2349// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 82350// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 82351// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 82352// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 82353// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 82354// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 42355// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 42356// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 42357// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 42358// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42359// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42360// CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 82361// CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 82362// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 42363// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 82364// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 82365// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 82366// CHECK2-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 82367// CHECK2-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 82368// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 82369// CHECK2-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 82370// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 42371// CHECK2-NEXT: store i32 16908288, ptr [[DOTOMP_UB]], align 42372// CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 42373// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 42374// CHECK2-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()2375// CHECK2-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 82376// CHECK2-NEXT: [[VLA1:%.*]] = alloca float, i64 [[TMP1]], align 162377// CHECK2-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 82378// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 82379// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 42380// CHECK2-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5)2381// CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]]2382// CHECK2: omp.dispatch.cond:2383// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42384// CHECK2-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP5]], 169082882385// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2386// CHECK2: cond.true:2387// CHECK2-NEXT: br label [[COND_END:%.*]]2388// CHECK2: cond.false:2389// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42390// CHECK2-NEXT: br label [[COND_END]]2391// CHECK2: cond.end:2392// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]2393// CHECK2-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 42394// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42395// CHECK2-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 42396// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42397// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42398// CHECK2-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP8]], [[TMP9]]2399// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_CLEANUP:%.*]]2400// CHECK2: omp.dispatch.cleanup:2401// CHECK2-NEXT: br label [[OMP_DISPATCH_END:%.*]]2402// CHECK2: omp.dispatch.body:2403// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]2404// CHECK2: omp.inner.for.cond:2405// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42406// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42407// CHECK2-NEXT: [[CMP3:%.*]] = icmp ule i32 [[TMP10]], [[TMP11]]2408// CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]2409// CHECK2: omp.inner.for.cond.cleanup:2410// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]2411// CHECK2: omp.inner.for.body:2412// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42413// CHECK2-NEXT: [[MUL:%.*]] = mul i32 [[TMP12]], 1272414// CHECK2-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]2415// CHECK2-NEXT: store i32 [[ADD]], ptr [[I]], align 42416// CHECK2-NEXT: [[CALL:%.*]] = invoke noundef i32 @_Z3foov()2417// CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]]2418// CHECK2: invoke.cont:2419// CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[CALL]] to float2420// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 42421// CHECK2-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP13]] to i642422// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[VLA1]], i64 [[IDXPROM]]2423// CHECK2-NEXT: [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 42424// CHECK2-NEXT: [[ADD4:%.*]] = fadd float [[CONV]], [[TMP14]]2425// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[N_ADDR]], align 42426// CHECK2-NEXT: [[CONV5:%.*]] = sitofp i32 [[TMP15]] to float2427// CHECK2-NEXT: [[ADD6:%.*]] = fadd float [[ADD4]], [[CONV5]]2428// CHECK2-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP0]], align 82429// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 42430// CHECK2-NEXT: [[IDXPROM7:%.*]] = zext i32 [[TMP17]] to i642431// CHECK2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds nuw float, ptr [[TMP16]], i64 [[IDXPROM7]]2432// CHECK2-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX8]], align 42433// CHECK2-NEXT: [[ADD9:%.*]] = fadd float [[TMP18]], [[ADD6]]2434// CHECK2-NEXT: store float [[ADD9]], ptr [[ARRAYIDX8]], align 42435// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]2436// CHECK2: omp.body.continue:2437// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]2438// CHECK2: omp.inner.for.inc:2439// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42440// CHECK2-NEXT: [[ADD10:%.*]] = add i32 [[TMP19]], 12441// CHECK2-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 42442// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]2443// CHECK2: omp.inner.for.end:2444// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]2445// CHECK2: omp.dispatch.inc:2446// CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42447// CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 42448// CHECK2-NEXT: [[ADD11:%.*]] = add i32 [[TMP20]], [[TMP21]]2449// CHECK2-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_LB]], align 42450// CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42451// CHECK2-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 42452// CHECK2-NEXT: [[ADD12:%.*]] = add i32 [[TMP22]], [[TMP23]]2453// CHECK2-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_UB]], align 42454// CHECK2-NEXT: br label [[OMP_DISPATCH_COND]]2455// CHECK2: omp.dispatch.end:2456// CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP4]])2457// CHECK2-NEXT: [[TMP24:%.*]] = load ptr, ptr [[SAVED_STACK]], align 82458// CHECK2-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP24]])2459// CHECK2-NEXT: ret void2460// CHECK2: terminate.lpad:2461// CHECK2-NEXT: [[TMP25:%.*]] = landingpad { ptr, i32 }2462// CHECK2-NEXT: catch ptr null2463// CHECK2-NEXT: [[TMP26:%.*]] = extractvalue { ptr, i32 } [[TMP25]], 02464// CHECK2-NEXT: call void @__clang_call_terminate(ptr [[TMP26]]) #[[ATTR7:[0-9]+]]2465// CHECK2-NEXT: unreachable2466//2467//2468// CHECK2-LABEL: define {{[^@]+}}@__clang_call_terminate2469// CHECK2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR6:[0-9]+]] comdat {2470// CHECK2-NEXT: [[TMP2:%.*]] = call ptr @__cxa_begin_catch(ptr [[TMP0]]) #[[ATTR2:[0-9]+]]2471// CHECK2-NEXT: call void @_ZSt9terminatev() #[[ATTR7]]2472// CHECK2-NEXT: unreachable2473//2474//2475// CHECK5-LABEL: define {{[^@]+}}@_Z17with_var_schedulev2476// CHECK5-SAME: () #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] {2477// CHECK5-NEXT: entry:2478// CHECK5-NEXT: [[A:%.*]] = alloca double, align 82479// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 12480// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 82481// CHECK5-NEXT: store double 5.000000e+00, ptr [[A]], align 8, !dbg [[DBG10:![0-9]+]]2482// CHECK5-NEXT: [[TMP0:%.*]] = load double, ptr [[A]], align 8, !dbg [[DBG11:![0-9]+]]2483// CHECK5-NEXT: [[CONV:%.*]] = fptosi double [[TMP0]] to i8, !dbg [[DBG11]]2484// CHECK5-NEXT: store i8 [[CONV]], ptr [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG11]]2485// CHECK5-NEXT: [[TMP1:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG11]]2486// CHECK5-NEXT: store i8 [[TMP1]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1, !dbg [[DBG11]]2487// CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8, !dbg [[DBG11]]2488// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4:[0-9]+]], i32 1, ptr @_Z17with_var_schedulev.omp_outlined, i64 [[TMP2]]), !dbg [[DBG11]]2489// CHECK5-NEXT: ret void, !dbg [[DBG12:![0-9]+]]2490//2491//2492// CHECK5-LABEL: define {{[^@]+}}@_Z17with_var_schedulev.omp_outlined2493// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] !dbg [[DBG13:![0-9]+]] {2494// CHECK5-NEXT: entry:2495// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 82496// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 82497// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 82498// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 82499// CHECK5-NEXT: [[TMP:%.*]] = alloca i64, align 82500// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca double, align 82501// CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 82502// CHECK5-NEXT: [[I:%.*]] = alloca i64, align 82503// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 82504// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 82505// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 82506// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42507// CHECK5-NEXT: [[A:%.*]] = alloca double, align 82508// CHECK5-NEXT: [[I4:%.*]] = alloca i64, align 82509// CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 82510// CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 82511// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 82512// CHECK5-NEXT: [[TMP0:%.*]] = load double, ptr undef, align 8, !dbg [[DBG14:![0-9]+]]2513// CHECK5-NEXT: [[ADD:%.*]] = fadd double 2.000000e+00, [[TMP0]], !dbg [[DBG14]]2514// CHECK5-NEXT: store double [[ADD]], ptr [[DOTCAPTURE_EXPR_1]], align 8, !dbg [[DBG14]]2515// CHECK5-NEXT: [[TMP1:%.*]] = load double, ptr [[DOTCAPTURE_EXPR_1]], align 8, !dbg [[DBG14]]2516// CHECK5-NEXT: [[SUB:%.*]] = fsub double [[TMP1]], 1.000000e+00, !dbg [[DBG14]]2517// CHECK5-NEXT: [[DIV:%.*]] = fdiv double [[SUB]], 1.000000e+00, !dbg [[DBG14]]2518// CHECK5-NEXT: [[CONV:%.*]] = fptoui double [[DIV]] to i64, !dbg [[DBG14]]2519// CHECK5-NEXT: [[SUB3:%.*]] = sub i64 [[CONV]], 1, !dbg [[DBG14]]2520// CHECK5-NEXT: store i64 [[SUB3]], ptr [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG14]]2521// CHECK5-NEXT: store i64 1, ptr [[I]], align 8, !dbg [[DBG14]]2522// CHECK5-NEXT: [[TMP2:%.*]] = load double, ptr [[DOTCAPTURE_EXPR_1]], align 8, !dbg [[DBG14]]2523// CHECK5-NEXT: [[CMP:%.*]] = fcmp olt double 1.000000e+00, [[TMP2]], !dbg [[DBG14]]2524// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]], !dbg [[DBG15:![0-9]+]]2525// CHECK5: omp.precond.then:2526// CHECK5-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8, !dbg [[DBG14]]2527// CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG14]]2528// CHECK5-NEXT: store i64 [[TMP3]], ptr [[DOTOMP_UB]], align 8, !dbg [[DBG14]]2529// CHECK5-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8, !dbg [[DBG14]]2530// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG14]]2531// CHECK5-NEXT: [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1, !dbg [[DBG15]]2532// CHECK5-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i64, !dbg [[DBG15]]2533// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG15]]2534// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG15]]2535// CHECK5-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 [[CONV5]]), !dbg [[DBG15]]2536// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG15]]2537// CHECK5: omp.dispatch.cond:2538// CHECK5-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !dbg [[DBG14]]2539// CHECK5-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG14]]2540// CHECK5-NEXT: [[CMP6:%.*]] = icmp ugt i64 [[TMP7]], [[TMP8]], !dbg [[DBG14]]2541// CHECK5-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG14]]2542// CHECK5: cond.true:2543// CHECK5-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG14]]2544// CHECK5-NEXT: br label [[COND_END:%.*]], !dbg [[DBG14]]2545// CHECK5: cond.false:2546// CHECK5-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !dbg [[DBG14]]2547// CHECK5-NEXT: br label [[COND_END]], !dbg [[DBG14]]2548// CHECK5: cond.end:2549// CHECK5-NEXT: [[COND:%.*]] = phi i64 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ], !dbg [[DBG14]]2550// CHECK5-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8, !dbg [[DBG14]]2551// CHECK5-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8, !dbg [[DBG14]]2552// CHECK5-NEXT: store i64 [[TMP11]], ptr [[DOTOMP_IV]], align 8, !dbg [[DBG14]]2553// CHECK5-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG14]]2554// CHECK5-NEXT: [[TMP13:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !dbg [[DBG14]]2555// CHECK5-NEXT: [[ADD7:%.*]] = add i64 [[TMP13]], 1, !dbg [[DBG14]]2556// CHECK5-NEXT: [[CMP8:%.*]] = icmp ult i64 [[TMP12]], [[ADD7]], !dbg [[DBG14]]2557// CHECK5-NEXT: br i1 [[CMP8]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG15]]2558// CHECK5: omp.dispatch.body:2559// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG15]]2560// CHECK5: omp.inner.for.cond:2561// CHECK5-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG14]]2562// CHECK5-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !dbg [[DBG14]]2563// CHECK5-NEXT: [[ADD9:%.*]] = add i64 [[TMP15]], 1, !dbg [[DBG14]]2564// CHECK5-NEXT: [[CMP10:%.*]] = icmp ult i64 [[TMP14]], [[ADD9]], !dbg [[DBG14]]2565// CHECK5-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG15]]2566// CHECK5: omp.inner.for.body:2567// CHECK5-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG14]]2568// CHECK5-NEXT: [[MUL:%.*]] = mul i64 [[TMP16]], 1, !dbg [[DBG14]]2569// CHECK5-NEXT: [[ADD11:%.*]] = add i64 1, [[MUL]], !dbg [[DBG14]]2570// CHECK5-NEXT: store i64 [[ADD11]], ptr [[I4]], align 8, !dbg [[DBG14]]2571// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG16:![0-9]+]]2572// CHECK5: omp.body.continue:2573// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG15]]2574// CHECK5: omp.inner.for.inc:2575// CHECK5-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG14]]2576// CHECK5-NEXT: [[ADD12:%.*]] = add i64 [[TMP17]], 1, !dbg [[DBG14]]2577// CHECK5-NEXT: store i64 [[ADD12]], ptr [[DOTOMP_IV]], align 8, !dbg [[DBG14]]2578// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG15]], !llvm.loop [[LOOP17:![0-9]+]]2579// CHECK5: omp.inner.for.end:2580// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG15]]2581// CHECK5: omp.dispatch.inc:2582// CHECK5-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8, !dbg [[DBG14]]2583// CHECK5-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_STRIDE]], align 8, !dbg [[DBG14]]2584// CHECK5-NEXT: [[ADD13:%.*]] = add i64 [[TMP18]], [[TMP19]], !dbg [[DBG14]]2585// CHECK5-NEXT: store i64 [[ADD13]], ptr [[DOTOMP_LB]], align 8, !dbg [[DBG14]]2586// CHECK5-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !dbg [[DBG14]]2587// CHECK5-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_STRIDE]], align 8, !dbg [[DBG14]]2588// CHECK5-NEXT: [[ADD14:%.*]] = add i64 [[TMP20]], [[TMP21]], !dbg [[DBG14]]2589// CHECK5-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_UB]], align 8, !dbg [[DBG14]]2590// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG15]], !llvm.loop [[LOOP18:![0-9]+]]2591// CHECK5: omp.dispatch.end:2592// CHECK5-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG15]]2593// CHECK5-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4, !dbg [[DBG15]]2594// CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3:[0-9]+]], i32 [[TMP23]]), !dbg [[DBG15]]2595// CHECK5-NEXT: br label [[OMP_PRECOND_END]], !dbg [[DBG15]]2596// CHECK5: omp.precond.end:2597// CHECK5-NEXT: ret void, !dbg [[DBG16]]2598//2599//2600// CHECK5-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_2601// CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] !dbg [[DBG21:![0-9]+]] {2602// CHECK5-NEXT: entry:2603// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 82604// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 82605// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 82606// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 82607// CHECK5-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 82608// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 82609// CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 82610// CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 82611// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB9:[0-9]+]], i32 4, ptr @_Z23without_schedule_clausePfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]), !dbg [[DBG22:![0-9]+]]2612// CHECK5-NEXT: ret void, !dbg [[DBG23:![0-9]+]]2613//2614//2615// CHECK5-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_.omp_outlined2616// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG24:![0-9]+]] {2617// CHECK5-NEXT: entry:2618// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 82619// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 82620// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 82621// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 82622// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 82623// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 82624// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 42625// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 42626// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 42627// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 42628// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42629// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42630// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 42631// CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 82632// CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 82633// CHECK5-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 82634// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 82635// CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 82636// CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 82637// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG25:![0-9]+]]2638// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG25]]2639// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG25]]2640// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !dbg [[DBG25]]2641// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG26:![0-9]+]]2642// CHECK5-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG26]]2643// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG26]]2644// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG26]]2645// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG25]]2646// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4, !dbg [[DBG25]]2647// CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB6:[0-9]+]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG25]]2648// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG26]]2649// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423, !dbg [[DBG26]]2650// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG26]]2651// CHECK5: cond.true:2652// CHECK5-NEXT: br label [[COND_END:%.*]], !dbg [[DBG26]]2653// CHECK5: cond.false:2654// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG26]]2655// CHECK5-NEXT: br label [[COND_END]], !dbg [[DBG26]]2656// CHECK5: cond.end:2657// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ], !dbg [[DBG26]]2658// CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG26]]2659// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG26]]2660// CHECK5-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG26]]2661// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG25]]2662// CHECK5: omp.inner.for.cond:2663// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG26]]2664// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG26]]2665// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]], !dbg [[DBG26]]2666// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG25]]2667// CHECK5: omp.inner.for.body:2668// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG26]]2669// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7, !dbg [[DBG26]]2670// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]], !dbg [[DBG26]]2671// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !dbg [[DBG26]]2672// CHECK5-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 8, !dbg [[DBG27:![0-9]+]]2673// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG27]]2674// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64, !dbg [[DBG27]]2675// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[IDXPROM]], !dbg [[DBG27]]2676// CHECK5-NEXT: [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !dbg [[DBG27]]2677// CHECK5-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP2]], align 8, !dbg [[DBG27]]2678// CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG27]]2679// CHECK5-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64, !dbg [[DBG27]]2680// CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[IDXPROM2]], !dbg [[DBG27]]2681// CHECK5-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !dbg [[DBG27]]2682// CHECK5-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]], !dbg [[DBG27]]2683// CHECK5-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP3]], align 8, !dbg [[DBG27]]2684// CHECK5-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG27]]2685// CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64, !dbg [[DBG27]]2686// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[IDXPROM5]], !dbg [[DBG27]]2687// CHECK5-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX6]], align 4, !dbg [[DBG27]]2688// CHECK5-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]], !dbg [[DBG27]]2689// CHECK5-NEXT: [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 8, !dbg [[DBG27]]2690// CHECK5-NEXT: [[TMP22:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG27]]2691// CHECK5-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64, !dbg [[DBG27]]2692// CHECK5-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i64 [[IDXPROM8]], !dbg [[DBG27]]2693// CHECK5-NEXT: store float [[MUL7]], ptr [[ARRAYIDX9]], align 4, !dbg [[DBG27]]2694// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG28:![0-9]+]]2695// CHECK5: omp.body.continue:2696// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG25]]2697// CHECK5: omp.inner.for.inc:2698// CHECK5-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG26]]2699// CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP23]], 1, !dbg [[DBG26]]2700// CHECK5-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG26]]2701// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG25]], !llvm.loop [[LOOP29:![0-9]+]]2702// CHECK5: omp.inner.for.end:2703// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]], !dbg [[DBG25]]2704// CHECK5: omp.loop.exit:2705// CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB8:[0-9]+]], i32 [[TMP5]]), !dbg [[DBG25]]2706// CHECK5-NEXT: ret void, !dbg [[DBG28]]2707//2708//2709// CHECK5-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_2710// CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] !dbg [[DBG30:![0-9]+]] {2711// CHECK5-NEXT: entry:2712// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 82713// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 82714// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 82715// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 82716// CHECK5-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 82717// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 82718// CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 82719// CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 82720// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB14:[0-9]+]], i32 4, ptr @_Z18static_not_chunkedPfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]), !dbg [[DBG31:![0-9]+]]2721// CHECK5-NEXT: ret void, !dbg [[DBG32:![0-9]+]]2722//2723//2724// CHECK5-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_.omp_outlined2725// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG33:![0-9]+]] {2726// CHECK5-NEXT: entry:2727// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 82728// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 82729// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 82730// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 82731// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 82732// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 82733// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 42734// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 42735// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 42736// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 42737// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42738// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42739// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 42740// CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 82741// CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 82742// CHECK5-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 82743// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 82744// CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 82745// CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 82746// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG34:![0-9]+]]2747// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG34]]2748// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG34]]2749// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !dbg [[DBG34]]2750// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG35:![0-9]+]]2751// CHECK5-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG35]]2752// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG35]]2753// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG35]]2754// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG34]]2755// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4, !dbg [[DBG34]]2756// CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB11:[0-9]+]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG34]]2757// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG35]]2758// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423, !dbg [[DBG35]]2759// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG35]]2760// CHECK5: cond.true:2761// CHECK5-NEXT: br label [[COND_END:%.*]], !dbg [[DBG35]]2762// CHECK5: cond.false:2763// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG35]]2764// CHECK5-NEXT: br label [[COND_END]], !dbg [[DBG35]]2765// CHECK5: cond.end:2766// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ], !dbg [[DBG35]]2767// CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG35]]2768// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG35]]2769// CHECK5-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG35]]2770// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG34]]2771// CHECK5: omp.inner.for.cond:2772// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG35]]2773// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG35]]2774// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]], !dbg [[DBG35]]2775// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG34]]2776// CHECK5: omp.inner.for.body:2777// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG35]]2778// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7, !dbg [[DBG35]]2779// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]], !dbg [[DBG35]]2780// CHECK5-NEXT: store i32 [[SUB]], ptr [[I]], align 4, !dbg [[DBG35]]2781// CHECK5-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 8, !dbg [[DBG36:![0-9]+]]2782// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG36]]2783// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64, !dbg [[DBG36]]2784// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[IDXPROM]], !dbg [[DBG36]]2785// CHECK5-NEXT: [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !dbg [[DBG36]]2786// CHECK5-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP2]], align 8, !dbg [[DBG36]]2787// CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG36]]2788// CHECK5-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64, !dbg [[DBG36]]2789// CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[IDXPROM2]], !dbg [[DBG36]]2790// CHECK5-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !dbg [[DBG36]]2791// CHECK5-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]], !dbg [[DBG36]]2792// CHECK5-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP3]], align 8, !dbg [[DBG36]]2793// CHECK5-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG36]]2794// CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64, !dbg [[DBG36]]2795// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[IDXPROM5]], !dbg [[DBG36]]2796// CHECK5-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX6]], align 4, !dbg [[DBG36]]2797// CHECK5-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]], !dbg [[DBG36]]2798// CHECK5-NEXT: [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 8, !dbg [[DBG36]]2799// CHECK5-NEXT: [[TMP22:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG36]]2800// CHECK5-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64, !dbg [[DBG36]]2801// CHECK5-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i64 [[IDXPROM8]], !dbg [[DBG36]]2802// CHECK5-NEXT: store float [[MUL7]], ptr [[ARRAYIDX9]], align 4, !dbg [[DBG36]]2803// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG37:![0-9]+]]2804// CHECK5: omp.body.continue:2805// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG34]]2806// CHECK5: omp.inner.for.inc:2807// CHECK5-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG35]]2808// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1, !dbg [[DBG35]]2809// CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG35]]2810// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG34]], !llvm.loop [[LOOP38:![0-9]+]]2811// CHECK5: omp.inner.for.end:2812// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]], !dbg [[DBG34]]2813// CHECK5: omp.loop.exit:2814// CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB13:[0-9]+]], i32 [[TMP5]]), !dbg [[DBG34]]2815// CHECK5-NEXT: ret void, !dbg [[DBG37]]2816//2817//2818// CHECK5-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_2819// CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] !dbg [[DBG39:![0-9]+]] {2820// CHECK5-NEXT: entry:2821// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 82822// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 82823// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 82824// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 82825// CHECK5-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 82826// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 82827// CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 82828// CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 82829// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB19:[0-9]+]], i32 4, ptr @_Z14static_chunkedPfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]), !dbg [[DBG40:![0-9]+]]2830// CHECK5-NEXT: ret void, !dbg [[DBG41:![0-9]+]]2831//2832//2833// CHECK5-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_.omp_outlined2834// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG42:![0-9]+]] {2835// CHECK5-NEXT: entry:2836// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 82837// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 82838// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 82839// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 82840// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 82841// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 82842// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 42843// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 42844// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 42845// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 42846// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42847// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42848// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 42849// CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 82850// CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 82851// CHECK5-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 82852// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 82853// CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 82854// CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 82855// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG43:![0-9]+]]2856// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG43]]2857// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG43]]2858// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !dbg [[DBG43]]2859// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG44:![0-9]+]]2860// CHECK5-NEXT: store i32 16908288, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG44]]2861// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG44]]2862// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG44]]2863// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG43]]2864// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4, !dbg [[DBG43]]2865// CHECK5-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB16:[0-9]+]], i32 [[TMP5]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5), !dbg [[DBG43]]2866// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG43]]2867// CHECK5: omp.dispatch.cond:2868// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG44]]2869// CHECK5-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288, !dbg [[DBG44]]2870// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG44]]2871// CHECK5: cond.true:2872// CHECK5-NEXT: br label [[COND_END:%.*]], !dbg [[DBG44]]2873// CHECK5: cond.false:2874// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG44]]2875// CHECK5-NEXT: br label [[COND_END]], !dbg [[DBG44]]2876// CHECK5: cond.end:2877// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ], !dbg [[DBG44]]2878// CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG44]]2879// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG44]]2880// CHECK5-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG44]]2881// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG44]]2882// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG44]]2883// CHECK5-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]], !dbg [[DBG44]]2884// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG43]]2885// CHECK5: omp.dispatch.body:2886// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG43]]2887// CHECK5: omp.inner.for.cond:2888// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG44]]2889// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG44]]2890// CHECK5-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]], !dbg [[DBG44]]2891// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG43]]2892// CHECK5: omp.inner.for.body:2893// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG44]]2894// CHECK5-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127, !dbg [[DBG44]]2895// CHECK5-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]], !dbg [[DBG44]]2896// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !dbg [[DBG44]]2897// CHECK5-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP1]], align 8, !dbg [[DBG45:![0-9]+]]2898// CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG45]]2899// CHECK5-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64, !dbg [[DBG45]]2900// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP14]], i64 [[IDXPROM]], !dbg [[DBG45]]2901// CHECK5-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !dbg [[DBG45]]2902// CHECK5-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP2]], align 8, !dbg [[DBG45]]2903// CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG45]]2904// CHECK5-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64, !dbg [[DBG45]]2905// CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw float, ptr [[TMP17]], i64 [[IDXPROM3]], !dbg [[DBG45]]2906// CHECK5-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !dbg [[DBG45]]2907// CHECK5-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]], !dbg [[DBG45]]2908// CHECK5-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP3]], align 8, !dbg [[DBG45]]2909// CHECK5-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG45]]2910// CHECK5-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64, !dbg [[DBG45]]2911// CHECK5-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds nuw float, ptr [[TMP20]], i64 [[IDXPROM6]], !dbg [[DBG45]]2912// CHECK5-NEXT: [[TMP22:%.*]] = load float, ptr [[ARRAYIDX7]], align 4, !dbg [[DBG45]]2913// CHECK5-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]], !dbg [[DBG45]]2914// CHECK5-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP0]], align 8, !dbg [[DBG45]]2915// CHECK5-NEXT: [[TMP24:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG45]]2916// CHECK5-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64, !dbg [[DBG45]]2917// CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds nuw float, ptr [[TMP23]], i64 [[IDXPROM9]], !dbg [[DBG45]]2918// CHECK5-NEXT: store float [[MUL8]], ptr [[ARRAYIDX10]], align 4, !dbg [[DBG45]]2919// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG46:![0-9]+]]2920// CHECK5: omp.body.continue:2921// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG43]]2922// CHECK5: omp.inner.for.inc:2923// CHECK5-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG44]]2924// CHECK5-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1, !dbg [[DBG44]]2925// CHECK5-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG44]]2926// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG43]], !llvm.loop [[LOOP47:![0-9]+]]2927// CHECK5: omp.inner.for.end:2928// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG43]]2929// CHECK5: omp.dispatch.inc:2930// CHECK5-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG44]]2931// CHECK5-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG44]]2932// CHECK5-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]], !dbg [[DBG44]]2933// CHECK5-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_LB]], align 4, !dbg [[DBG44]]2934// CHECK5-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG44]]2935// CHECK5-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG44]]2936// CHECK5-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]], !dbg [[DBG44]]2937// CHECK5-NEXT: store i32 [[ADD13]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG44]]2938// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG43]], !llvm.loop [[LOOP48:![0-9]+]]2939// CHECK5: omp.dispatch.end:2940// CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB18:[0-9]+]], i32 [[TMP5]]), !dbg [[DBG43]]2941// CHECK5-NEXT: ret void, !dbg [[DBG46]]2942//2943//2944// CHECK5-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_2945// CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] !dbg [[DBG49:![0-9]+]] {2946// CHECK5-NEXT: entry:2947// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 82948// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 82949// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 82950// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 82951// CHECK5-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 82952// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 82953// CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 82954// CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 82955// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB21:[0-9]+]], i32 4, ptr @_Z8dynamic1PfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]), !dbg [[DBG50:![0-9]+]]2956// CHECK5-NEXT: ret void, !dbg [[DBG51:![0-9]+]]2957//2958//2959// CHECK5-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_.omp_outlined2960// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG52:![0-9]+]] {2961// CHECK5-NEXT: entry:2962// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 82963// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 82964// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 82965// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 82966// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 82967// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 82968// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 82969// CHECK5-NEXT: [[TMP:%.*]] = alloca i64, align 82970// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 82971// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 82972// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 82973// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42974// CHECK5-NEXT: [[I:%.*]] = alloca i64, align 82975// CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 82976// CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 82977// CHECK5-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 82978// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 82979// CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 82980// CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 82981// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG53:![0-9]+]]2982// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG53]]2983// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG53]]2984// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !dbg [[DBG53]]2985// CHECK5-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8, !dbg [[DBG54:![0-9]+]]2986// CHECK5-NEXT: store i64 16908287, ptr [[DOTOMP_UB]], align 8, !dbg [[DBG54]]2987// CHECK5-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8, !dbg [[DBG54]]2988// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG54]]2989// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG53]]2990// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4, !dbg [[DBG53]]2991// CHECK5-NEXT: call void @__kmpc_dispatch_init_8u(ptr @[[GLOB21]], i32 [[TMP5]], i32 1073741859, i64 0, i64 16908287, i64 1, i64 1), !dbg [[DBG53]]2992// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG53]]2993// CHECK5: omp.dispatch.cond:2994// CHECK5-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8u(ptr @[[GLOB21]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]]), !dbg [[DBG53]]2995// CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0, !dbg [[DBG53]]2996// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG53]]2997// CHECK5: omp.dispatch.body:2998// CHECK5-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8, !dbg [[DBG54]]2999// CHECK5-NEXT: store i64 [[TMP7]], ptr [[DOTOMP_IV]], align 8, !dbg [[DBG54]]3000// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG53]]3001// CHECK5: omp.inner.for.cond:3002// CHECK5-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG54]], !llvm.access.group [[ACC_GRP55:![0-9]+]]3003// CHECK5-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !dbg [[DBG54]], !llvm.access.group [[ACC_GRP55]]3004// CHECK5-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1, !dbg [[DBG54]]3005// CHECK5-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]], !dbg [[DBG54]]3006// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG53]]3007// CHECK5: omp.inner.for.body:3008// CHECK5-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG54]], !llvm.access.group [[ACC_GRP55]]3009// CHECK5-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127, !dbg [[DBG54]]3010// CHECK5-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]], !dbg [[DBG54]]3011// CHECK5-NEXT: store i64 [[ADD1]], ptr [[I]], align 8, !dbg [[DBG54]], !llvm.access.group [[ACC_GRP55]]3012// CHECK5-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP1]], align 8, !dbg [[DBG56:![0-9]+]], !llvm.access.group [[ACC_GRP55]]3013// CHECK5-NEXT: [[TMP12:%.*]] = load i64, ptr [[I]], align 8, !dbg [[DBG56]], !llvm.access.group [[ACC_GRP55]]3014// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP11]], i64 [[TMP12]], !dbg [[DBG56]]3015// CHECK5-NEXT: [[TMP13:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !dbg [[DBG56]], !llvm.access.group [[ACC_GRP55]]3016// CHECK5-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP2]], align 8, !dbg [[DBG56]], !llvm.access.group [[ACC_GRP55]]3017// CHECK5-NEXT: [[TMP15:%.*]] = load i64, ptr [[I]], align 8, !dbg [[DBG56]], !llvm.access.group [[ACC_GRP55]]3018// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw float, ptr [[TMP14]], i64 [[TMP15]], !dbg [[DBG56]]3019// CHECK5-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !dbg [[DBG56]], !llvm.access.group [[ACC_GRP55]]3020// CHECK5-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]], !dbg [[DBG56]]3021// CHECK5-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP3]], align 8, !dbg [[DBG56]], !llvm.access.group [[ACC_GRP55]]3022// CHECK5-NEXT: [[TMP18:%.*]] = load i64, ptr [[I]], align 8, !dbg [[DBG56]], !llvm.access.group [[ACC_GRP55]]3023// CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw float, ptr [[TMP17]], i64 [[TMP18]], !dbg [[DBG56]]3024// CHECK5-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !dbg [[DBG56]], !llvm.access.group [[ACC_GRP55]]3025// CHECK5-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]], !dbg [[DBG56]]3026// CHECK5-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP0]], align 8, !dbg [[DBG56]], !llvm.access.group [[ACC_GRP55]]3027// CHECK5-NEXT: [[TMP21:%.*]] = load i64, ptr [[I]], align 8, !dbg [[DBG56]], !llvm.access.group [[ACC_GRP55]]3028// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds nuw float, ptr [[TMP20]], i64 [[TMP21]], !dbg [[DBG56]]3029// CHECK5-NEXT: store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !dbg [[DBG56]], !llvm.access.group [[ACC_GRP55]]3030// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG57:![0-9]+]]3031// CHECK5: omp.body.continue:3032// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG53]]3033// CHECK5: omp.inner.for.inc:3034// CHECK5-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG54]], !llvm.access.group [[ACC_GRP55]]3035// CHECK5-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1, !dbg [[DBG54]]3036// CHECK5-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !dbg [[DBG54]], !llvm.access.group [[ACC_GRP55]]3037// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG53]], !llvm.loop [[LOOP58:![0-9]+]]3038// CHECK5: omp.inner.for.end:3039// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG53]]3040// CHECK5: omp.dispatch.inc:3041// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG53]], !llvm.loop [[LOOP60:![0-9]+]]3042// CHECK5: omp.dispatch.end:3043// CHECK5-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB21]], i32 [[TMP5]]), !dbg [[DBG53]]3044// CHECK5-NEXT: ret void, !dbg [[DBG57]]3045//3046//3047// CHECK5-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_3048// CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] !dbg [[DBG61:![0-9]+]] {3049// CHECK5-NEXT: entry:3050// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 83051// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 83052// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 83053// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 83054// CHECK5-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 83055// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 83056// CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 83057// CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 83058// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB23:[0-9]+]], i32 4, ptr @_Z7guided7PfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]), !dbg [[DBG62:![0-9]+]]3059// CHECK5-NEXT: ret void, !dbg [[DBG63:![0-9]+]]3060//3061//3062// CHECK5-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_.omp_outlined3063// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG64:![0-9]+]] {3064// CHECK5-NEXT: entry:3065// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 83066// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 83067// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 83068// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 83069// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 83070// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 83071// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 83072// CHECK5-NEXT: [[TMP:%.*]] = alloca i64, align 83073// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 83074// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 83075// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 83076// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 43077// CHECK5-NEXT: [[I:%.*]] = alloca i64, align 83078// CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 83079// CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 83080// CHECK5-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 83081// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 83082// CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 83083// CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 83084// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG65:![0-9]+]]3085// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG65]]3086// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG65]]3087// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !dbg [[DBG65]]3088// CHECK5-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8, !dbg [[DBG66:![0-9]+]]3089// CHECK5-NEXT: store i64 16908287, ptr [[DOTOMP_UB]], align 8, !dbg [[DBG66]]3090// CHECK5-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8, !dbg [[DBG66]]3091// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG66]]3092// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG65]]3093// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4, !dbg [[DBG65]]3094// CHECK5-NEXT: call void @__kmpc_dispatch_init_8u(ptr @[[GLOB23]], i32 [[TMP5]], i32 1073741860, i64 0, i64 16908287, i64 1, i64 7), !dbg [[DBG65]]3095// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG65]]3096// CHECK5: omp.dispatch.cond:3097// CHECK5-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8u(ptr @[[GLOB23]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]]), !dbg [[DBG65]]3098// CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0, !dbg [[DBG65]]3099// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG65]]3100// CHECK5: omp.dispatch.body:3101// CHECK5-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8, !dbg [[DBG66]]3102// CHECK5-NEXT: store i64 [[TMP7]], ptr [[DOTOMP_IV]], align 8, !dbg [[DBG66]]3103// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG65]]3104// CHECK5: omp.inner.for.cond:3105// CHECK5-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG66]], !llvm.access.group [[ACC_GRP67:![0-9]+]]3106// CHECK5-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !dbg [[DBG66]], !llvm.access.group [[ACC_GRP67]]3107// CHECK5-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1, !dbg [[DBG66]]3108// CHECK5-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]], !dbg [[DBG66]]3109// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG65]]3110// CHECK5: omp.inner.for.body:3111// CHECK5-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG66]], !llvm.access.group [[ACC_GRP67]]3112// CHECK5-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127, !dbg [[DBG66]]3113// CHECK5-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]], !dbg [[DBG66]]3114// CHECK5-NEXT: store i64 [[ADD1]], ptr [[I]], align 8, !dbg [[DBG66]], !llvm.access.group [[ACC_GRP67]]3115// CHECK5-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP1]], align 8, !dbg [[DBG68:![0-9]+]], !llvm.access.group [[ACC_GRP67]]3116// CHECK5-NEXT: [[TMP12:%.*]] = load i64, ptr [[I]], align 8, !dbg [[DBG68]], !llvm.access.group [[ACC_GRP67]]3117// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP11]], i64 [[TMP12]], !dbg [[DBG68]]3118// CHECK5-NEXT: [[TMP13:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !dbg [[DBG68]], !llvm.access.group [[ACC_GRP67]]3119// CHECK5-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP2]], align 8, !dbg [[DBG68]], !llvm.access.group [[ACC_GRP67]]3120// CHECK5-NEXT: [[TMP15:%.*]] = load i64, ptr [[I]], align 8, !dbg [[DBG68]], !llvm.access.group [[ACC_GRP67]]3121// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw float, ptr [[TMP14]], i64 [[TMP15]], !dbg [[DBG68]]3122// CHECK5-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !dbg [[DBG68]], !llvm.access.group [[ACC_GRP67]]3123// CHECK5-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]], !dbg [[DBG68]]3124// CHECK5-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP3]], align 8, !dbg [[DBG68]], !llvm.access.group [[ACC_GRP67]]3125// CHECK5-NEXT: [[TMP18:%.*]] = load i64, ptr [[I]], align 8, !dbg [[DBG68]], !llvm.access.group [[ACC_GRP67]]3126// CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw float, ptr [[TMP17]], i64 [[TMP18]], !dbg [[DBG68]]3127// CHECK5-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !dbg [[DBG68]], !llvm.access.group [[ACC_GRP67]]3128// CHECK5-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]], !dbg [[DBG68]]3129// CHECK5-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP0]], align 8, !dbg [[DBG68]], !llvm.access.group [[ACC_GRP67]]3130// CHECK5-NEXT: [[TMP21:%.*]] = load i64, ptr [[I]], align 8, !dbg [[DBG68]], !llvm.access.group [[ACC_GRP67]]3131// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds nuw float, ptr [[TMP20]], i64 [[TMP21]], !dbg [[DBG68]]3132// CHECK5-NEXT: store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !dbg [[DBG68]], !llvm.access.group [[ACC_GRP67]]3133// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG69:![0-9]+]]3134// CHECK5: omp.body.continue:3135// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG65]]3136// CHECK5: omp.inner.for.inc:3137// CHECK5-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG66]], !llvm.access.group [[ACC_GRP67]]3138// CHECK5-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1, !dbg [[DBG66]]3139// CHECK5-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !dbg [[DBG66]], !llvm.access.group [[ACC_GRP67]]3140// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG65]], !llvm.loop [[LOOP70:![0-9]+]]3141// CHECK5: omp.inner.for.end:3142// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG65]]3143// CHECK5: omp.dispatch.inc:3144// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG65]], !llvm.loop [[LOOP72:![0-9]+]]3145// CHECK5: omp.dispatch.end:3146// CHECK5-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB23]], i32 [[TMP5]]), !dbg [[DBG65]]3147// CHECK5-NEXT: ret void, !dbg [[DBG69]]3148//3149//3150// CHECK5-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_3151// CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] !dbg [[DBG73:![0-9]+]] {3152// CHECK5-NEXT: entry:3153// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 83154// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 83155// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 83156// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 83157// CHECK5-NEXT: [[X:%.*]] = alloca i32, align 43158// CHECK5-NEXT: [[Y:%.*]] = alloca i32, align 43159// CHECK5-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 83160// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 83161// CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 83162// CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 83163// CHECK5-NEXT: store i32 0, ptr [[X]], align 4, !dbg [[DBG74:![0-9]+]]3164// CHECK5-NEXT: store i32 0, ptr [[Y]], align 4, !dbg [[DBG75:![0-9]+]]3165// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB25:[0-9]+]], i32 5, ptr @_Z9test_autoPfS_S_S_.omp_outlined, ptr [[Y]], ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]), !dbg [[DBG76:![0-9]+]]3166// CHECK5-NEXT: ret void, !dbg [[DBG77:![0-9]+]]3167//3168//3169// CHECK5-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_.omp_outlined3170// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[Y:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG78:![0-9]+]] {3171// CHECK5-NEXT: entry:3172// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 83173// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 83174// CHECK5-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 83175// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 83176// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 83177// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 83178// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 83179// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 83180// CHECK5-NEXT: [[TMP:%.*]] = alloca i8, align 13181// CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 43182// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 13183// CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 83184// CHECK5-NEXT: [[I:%.*]] = alloca i8, align 13185// CHECK5-NEXT: [[X:%.*]] = alloca i32, align 43186// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 83187// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 83188// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 83189// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 43190// CHECK5-NEXT: [[I7:%.*]] = alloca i8, align 13191// CHECK5-NEXT: [[X8:%.*]] = alloca i32, align 43192// CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 83193// CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 83194// CHECK5-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 83195// CHECK5-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 83196// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 83197// CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 83198// CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 83199// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 8, !dbg [[DBG79:![0-9]+]]3200// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG79]]3201// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG79]]3202// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG79]]3203// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !dbg [[DBG79]]3204// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4, !dbg [[DBG80:![0-9]+]]3205// CHECK5-NEXT: [[CONV:%.*]] = trunc i32 [[TMP5]] to i8, !dbg [[DBG80]]3206// CHECK5-NEXT: store i8 [[CONV]], ptr [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG80]]3207// CHECK5-NEXT: [[TMP6:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG80]]3208// CHECK5-NEXT: [[CONV3:%.*]] = sext i8 [[TMP6]] to i32, !dbg [[DBG80]]3209// CHECK5-NEXT: [[SUB:%.*]] = sub i32 57, [[CONV3]], !dbg [[DBG80]]3210// CHECK5-NEXT: [[ADD:%.*]] = add i32 [[SUB]], 1, !dbg [[DBG80]]3211// CHECK5-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1, !dbg [[DBG80]]3212// CHECK5-NEXT: [[CONV4:%.*]] = zext i32 [[DIV]] to i64, !dbg [[DBG80]]3213// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11, !dbg [[DBG81:![0-9]+]]3214// CHECK5-NEXT: [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1, !dbg [[DBG81]]3215// CHECK5-NEXT: store i64 [[SUB5]], ptr [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG80]]3216// CHECK5-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG80]]3217// CHECK5-NEXT: store i8 [[TMP7]], ptr [[I]], align 1, !dbg [[DBG80]]3218// CHECK5-NEXT: store i32 11, ptr [[X]], align 4, !dbg [[DBG81]]3219// CHECK5-NEXT: [[TMP8:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG80]]3220// CHECK5-NEXT: [[CONV6:%.*]] = sext i8 [[TMP8]] to i32, !dbg [[DBG80]]3221// CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV6]], 57, !dbg [[DBG80]]3222// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]], !dbg [[DBG79]]3223// CHECK5: omp.precond.then:3224// CHECK5-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8, !dbg [[DBG80]]3225// CHECK5-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG81]]3226// CHECK5-NEXT: store i64 [[TMP9]], ptr [[DOTOMP_UB]], align 8, !dbg [[DBG80]]3227// CHECK5-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8, !dbg [[DBG80]]3228// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG80]]3229// CHECK5-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG81]]3230// CHECK5-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG79]]3231// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4, !dbg [[DBG79]]3232// CHECK5-NEXT: call void @__kmpc_dispatch_init_8(ptr @[[GLOB25]], i32 [[TMP12]], i32 1073741862, i64 0, i64 [[TMP10]], i64 1, i64 1), !dbg [[DBG79]]3233// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG79]]3234// CHECK5: omp.dispatch.cond:3235// CHECK5-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG79]]3236// CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4, !dbg [[DBG79]]3237// CHECK5-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_dispatch_next_8(ptr @[[GLOB25]], i32 [[TMP14]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]]), !dbg [[DBG79]]3238// CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0, !dbg [[DBG79]]3239// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG79]]3240// CHECK5: omp.dispatch.body:3241// CHECK5-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8, !dbg [[DBG80]]3242// CHECK5-NEXT: store i64 [[TMP16]], ptr [[DOTOMP_IV]], align 8, !dbg [[DBG80]]3243// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG79]]3244// CHECK5: omp.inner.for.cond:3245// CHECK5-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG80]], !llvm.access.group [[ACC_GRP82:![0-9]+]]3246// CHECK5-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !dbg [[DBG80]], !llvm.access.group [[ACC_GRP82]]3247// CHECK5-NEXT: [[CMP9:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]], !dbg [[DBG80]]3248// CHECK5-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG79]]3249// CHECK5: omp.inner.for.body:3250// CHECK5-NEXT: [[TMP19:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG80]], !llvm.access.group [[ACC_GRP82]]3251// CHECK5-NEXT: [[CONV10:%.*]] = sext i8 [[TMP19]] to i64, !dbg [[DBG80]]3252// CHECK5-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG80]], !llvm.access.group [[ACC_GRP82]]3253// CHECK5-NEXT: [[DIV11:%.*]] = sdiv i64 [[TMP20]], 11, !dbg [[DBG80]]3254// CHECK5-NEXT: [[MUL12:%.*]] = mul nsw i64 [[DIV11]], 1, !dbg [[DBG80]]3255// CHECK5-NEXT: [[ADD13:%.*]] = add nsw i64 [[CONV10]], [[MUL12]], !dbg [[DBG80]]3256// CHECK5-NEXT: [[CONV14:%.*]] = trunc i64 [[ADD13]] to i8, !dbg [[DBG80]]3257// CHECK5-NEXT: store i8 [[CONV14]], ptr [[I7]], align 1, !dbg [[DBG80]], !llvm.access.group [[ACC_GRP82]]3258// CHECK5-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG80]], !llvm.access.group [[ACC_GRP82]]3259// CHECK5-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG80]], !llvm.access.group [[ACC_GRP82]]3260// CHECK5-NEXT: [[DIV15:%.*]] = sdiv i64 [[TMP22]], 11, !dbg [[DBG80]]3261// CHECK5-NEXT: [[MUL16:%.*]] = mul nsw i64 [[DIV15]], 11, !dbg [[DBG80]]3262// CHECK5-NEXT: [[SUB17:%.*]] = sub nsw i64 [[TMP21]], [[MUL16]], !dbg [[DBG80]]3263// CHECK5-NEXT: [[MUL18:%.*]] = mul nsw i64 [[SUB17]], 1, !dbg [[DBG81]]3264// CHECK5-NEXT: [[SUB19:%.*]] = sub nsw i64 11, [[MUL18]], !dbg [[DBG81]]3265// CHECK5-NEXT: [[CONV20:%.*]] = trunc i64 [[SUB19]] to i32, !dbg [[DBG81]]3266// CHECK5-NEXT: store i32 [[CONV20]], ptr [[X8]], align 4, !dbg [[DBG81]], !llvm.access.group [[ACC_GRP82]]3267// CHECK5-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP2]], align 8, !dbg [[DBG83:![0-9]+]], !llvm.access.group [[ACC_GRP82]]3268// CHECK5-NEXT: [[TMP24:%.*]] = load i8, ptr [[I7]], align 1, !dbg [[DBG83]], !llvm.access.group [[ACC_GRP82]]3269// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP24]] to i64, !dbg [[DBG83]]3270// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i64 [[IDXPROM]], !dbg [[DBG83]]3271// CHECK5-NEXT: [[TMP25:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !dbg [[DBG83]], !llvm.access.group [[ACC_GRP82]]3272// CHECK5-NEXT: [[TMP26:%.*]] = load ptr, ptr [[TMP3]], align 8, !dbg [[DBG83]], !llvm.access.group [[ACC_GRP82]]3273// CHECK5-NEXT: [[TMP27:%.*]] = load i8, ptr [[I7]], align 1, !dbg [[DBG83]], !llvm.access.group [[ACC_GRP82]]3274// CHECK5-NEXT: [[IDXPROM21:%.*]] = sext i8 [[TMP27]] to i64, !dbg [[DBG83]]3275// CHECK5-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds float, ptr [[TMP26]], i64 [[IDXPROM21]], !dbg [[DBG83]]3276// CHECK5-NEXT: [[TMP28:%.*]] = load float, ptr [[ARRAYIDX22]], align 4, !dbg [[DBG83]], !llvm.access.group [[ACC_GRP82]]3277// CHECK5-NEXT: [[MUL23:%.*]] = fmul float [[TMP25]], [[TMP28]], !dbg [[DBG83]]3278// CHECK5-NEXT: [[TMP29:%.*]] = load ptr, ptr [[TMP4]], align 8, !dbg [[DBG83]], !llvm.access.group [[ACC_GRP82]]3279// CHECK5-NEXT: [[TMP30:%.*]] = load i8, ptr [[I7]], align 1, !dbg [[DBG83]], !llvm.access.group [[ACC_GRP82]]3280// CHECK5-NEXT: [[IDXPROM24:%.*]] = sext i8 [[TMP30]] to i64, !dbg [[DBG83]]3281// CHECK5-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds float, ptr [[TMP29]], i64 [[IDXPROM24]], !dbg [[DBG83]]3282// CHECK5-NEXT: [[TMP31:%.*]] = load float, ptr [[ARRAYIDX25]], align 4, !dbg [[DBG83]], !llvm.access.group [[ACC_GRP82]]3283// CHECK5-NEXT: [[MUL26:%.*]] = fmul float [[MUL23]], [[TMP31]], !dbg [[DBG83]]3284// CHECK5-NEXT: [[TMP32:%.*]] = load ptr, ptr [[TMP1]], align 8, !dbg [[DBG83]], !llvm.access.group [[ACC_GRP82]]3285// CHECK5-NEXT: [[TMP33:%.*]] = load i8, ptr [[I7]], align 1, !dbg [[DBG83]], !llvm.access.group [[ACC_GRP82]]3286// CHECK5-NEXT: [[IDXPROM27:%.*]] = sext i8 [[TMP33]] to i64, !dbg [[DBG83]]3287// CHECK5-NEXT: [[ARRAYIDX28:%.*]] = getelementptr inbounds float, ptr [[TMP32]], i64 [[IDXPROM27]], !dbg [[DBG83]]3288// CHECK5-NEXT: store float [[MUL26]], ptr [[ARRAYIDX28]], align 4, !dbg [[DBG83]], !llvm.access.group [[ACC_GRP82]]3289// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG84:![0-9]+]]3290// CHECK5: omp.body.continue:3291// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG79]]3292// CHECK5: omp.inner.for.inc:3293// CHECK5-NEXT: [[TMP34:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG80]], !llvm.access.group [[ACC_GRP82]]3294// CHECK5-NEXT: [[ADD29:%.*]] = add nsw i64 [[TMP34]], 1, !dbg [[DBG80]]3295// CHECK5-NEXT: store i64 [[ADD29]], ptr [[DOTOMP_IV]], align 8, !dbg [[DBG80]], !llvm.access.group [[ACC_GRP82]]3296// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG79]], !llvm.loop [[LOOP85:![0-9]+]]3297// CHECK5: omp.inner.for.end:3298// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG79]]3299// CHECK5: omp.dispatch.inc:3300// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG79]], !llvm.loop [[LOOP87:![0-9]+]]3301// CHECK5: omp.dispatch.end:3302// CHECK5-NEXT: [[TMP35:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG79]]3303// CHECK5-NEXT: [[TMP36:%.*]] = load i32, ptr [[TMP35]], align 4, !dbg [[DBG79]]3304// CHECK5-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB25]], i32 [[TMP36]]), !dbg [[DBG79]]3305// CHECK5-NEXT: br label [[OMP_PRECOND_END]], !dbg [[DBG79]]3306// CHECK5: omp.precond.end:3307// CHECK5-NEXT: ret void, !dbg [[DBG84]]3308//3309//3310// CHECK5-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_3311// CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] !dbg [[DBG88:![0-9]+]] {3312// CHECK5-NEXT: entry:3313// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 83314// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 83315// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 83316// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 83317// CHECK5-NEXT: [[X:%.*]] = alloca i32, align 43318// CHECK5-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 83319// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 83320// CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 83321// CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 83322// CHECK5-NEXT: store i32 0, ptr [[X]], align 4, !dbg [[DBG89:![0-9]+]]3323// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB27:[0-9]+]], i32 4, ptr @_Z7runtimePfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]), !dbg [[DBG90:![0-9]+]]3324// CHECK5-NEXT: ret void, !dbg [[DBG91:![0-9]+]]3325//3326//3327// CHECK5-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_.omp_outlined3328// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG92:![0-9]+]] {3329// CHECK5-NEXT: entry:3330// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 83331// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 83332// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 83333// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 83334// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 83335// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 83336// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 43337// CHECK5-NEXT: [[TMP:%.*]] = alloca i8, align 13338// CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 43339// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 43340// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 43341// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 43342// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 43343// CHECK5-NEXT: [[I:%.*]] = alloca i8, align 13344// CHECK5-NEXT: [[X:%.*]] = alloca i32, align 43345// CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 83346// CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 83347// CHECK5-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 83348// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 83349// CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 83350// CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 83351// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG93:![0-9]+]]3352// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG93]]3353// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG93]]3354// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !dbg [[DBG93]]3355// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG94:![0-9]+]]3356// CHECK5-NEXT: store i32 199, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG94]]3357// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG94]]3358// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG94]]3359// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG93]]3360// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4, !dbg [[DBG93]]3361// CHECK5-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB27]], i32 [[TMP5]], i32 1073741861, i32 0, i32 199, i32 1, i32 1), !dbg [[DBG93]]3362// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG93]]3363// CHECK5: omp.dispatch.cond:3364// CHECK5-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB27]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]]), !dbg [[DBG93]]3365// CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0, !dbg [[DBG93]]3366// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG93]]3367// CHECK5: omp.dispatch.body:3368// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG94]]3369// CHECK5-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG94]]3370// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG93]]3371// CHECK5: omp.inner.for.cond:3372// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG94]], !llvm.access.group [[ACC_GRP95:![0-9]+]]3373// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG94]], !llvm.access.group [[ACC_GRP95]]3374// CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]], !dbg [[DBG94]]3375// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG93]]3376// CHECK5: omp.inner.for.body:3377// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG94]], !llvm.access.group [[ACC_GRP95]]3378// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 20, !dbg [[DBG94]]3379// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1, !dbg [[DBG94]]3380// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]], !dbg [[DBG94]]3381// CHECK5-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8, !dbg [[DBG94]]3382// CHECK5-NEXT: store i8 [[CONV]], ptr [[I]], align 1, !dbg [[DBG94]], !llvm.access.group [[ACC_GRP95]]3383// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG94]], !llvm.access.group [[ACC_GRP95]]3384// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG94]], !llvm.access.group [[ACC_GRP95]]3385// CHECK5-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP12]], 20, !dbg [[DBG94]]3386// CHECK5-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 20, !dbg [[DBG94]]3387// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL3]], !dbg [[DBG94]]3388// CHECK5-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1, !dbg [[DBG96:![0-9]+]]3389// CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 -10, [[MUL4]], !dbg [[DBG96]]3390// CHECK5-NEXT: store i32 [[ADD5]], ptr [[X]], align 4, !dbg [[DBG96]], !llvm.access.group [[ACC_GRP95]]3391// CHECK5-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 8, !dbg [[DBG97:![0-9]+]], !llvm.access.group [[ACC_GRP95]]3392// CHECK5-NEXT: [[TMP14:%.*]] = load i8, ptr [[I]], align 1, !dbg [[DBG97]], !llvm.access.group [[ACC_GRP95]]3393// CHECK5-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP14]] to i64, !dbg [[DBG97]]3394// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP13]], i64 [[IDXPROM]], !dbg [[DBG97]]3395// CHECK5-NEXT: [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !dbg [[DBG97]], !llvm.access.group [[ACC_GRP95]]3396// CHECK5-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 8, !dbg [[DBG97]], !llvm.access.group [[ACC_GRP95]]3397// CHECK5-NEXT: [[TMP17:%.*]] = load i8, ptr [[I]], align 1, !dbg [[DBG97]], !llvm.access.group [[ACC_GRP95]]3398// CHECK5-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP17]] to i64, !dbg [[DBG97]]3399// CHECK5-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds nuw float, ptr [[TMP16]], i64 [[IDXPROM6]], !dbg [[DBG97]]3400// CHECK5-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX7]], align 4, !dbg [[DBG97]], !llvm.access.group [[ACC_GRP95]]3401// CHECK5-NEXT: [[MUL8:%.*]] = fmul float [[TMP15]], [[TMP18]], !dbg [[DBG97]]3402// CHECK5-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 8, !dbg [[DBG97]], !llvm.access.group [[ACC_GRP95]]3403// CHECK5-NEXT: [[TMP20:%.*]] = load i8, ptr [[I]], align 1, !dbg [[DBG97]], !llvm.access.group [[ACC_GRP95]]3404// CHECK5-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP20]] to i64, !dbg [[DBG97]]3405// CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds nuw float, ptr [[TMP19]], i64 [[IDXPROM9]], !dbg [[DBG97]]3406// CHECK5-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !dbg [[DBG97]], !llvm.access.group [[ACC_GRP95]]3407// CHECK5-NEXT: [[MUL11:%.*]] = fmul float [[MUL8]], [[TMP21]], !dbg [[DBG97]]3408// CHECK5-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 8, !dbg [[DBG97]], !llvm.access.group [[ACC_GRP95]]3409// CHECK5-NEXT: [[TMP23:%.*]] = load i8, ptr [[I]], align 1, !dbg [[DBG97]], !llvm.access.group [[ACC_GRP95]]3410// CHECK5-NEXT: [[IDXPROM12:%.*]] = zext i8 [[TMP23]] to i64, !dbg [[DBG97]]3411// CHECK5-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds nuw float, ptr [[TMP22]], i64 [[IDXPROM12]], !dbg [[DBG97]]3412// CHECK5-NEXT: store float [[MUL11]], ptr [[ARRAYIDX13]], align 4, !dbg [[DBG97]], !llvm.access.group [[ACC_GRP95]]3413// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG98:![0-9]+]]3414// CHECK5: omp.body.continue:3415// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG93]]3416// CHECK5: omp.inner.for.inc:3417// CHECK5-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG94]], !llvm.access.group [[ACC_GRP95]]3418// CHECK5-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP24]], 1, !dbg [[DBG94]]3419// CHECK5-NEXT: store i32 [[ADD14]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG94]], !llvm.access.group [[ACC_GRP95]]3420// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG93]], !llvm.loop [[LOOP99:![0-9]+]]3421// CHECK5: omp.inner.for.end:3422// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG93]]3423// CHECK5: omp.dispatch.inc:3424// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG93]], !llvm.loop [[LOOP101:![0-9]+]]3425// CHECK5: omp.dispatch.end:3426// CHECK5-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB27]], i32 [[TMP5]]), !dbg [[DBG93]]3427// CHECK5-NEXT: ret void, !dbg [[DBG98]]3428//3429//3430// CHECK5-LABEL: define {{[^@]+}}@_Z3foov3431// CHECK5-SAME: () #[[ATTR3:[0-9]+]] !dbg [[DBG102:![0-9]+]] {3432// CHECK5-NEXT: entry:3433// CHECK5-NEXT: call void @_Z8mayThrowv(), !dbg [[DBG103:![0-9]+]]3434// CHECK5-NEXT: ret i32 0, !dbg [[DBG103]]3435//3436//3437// CHECK5-LABEL: define {{[^@]+}}@_Z12parallel_forPfi3438// CHECK5-SAME: (ptr noundef [[A:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] !dbg [[DBG104:![0-9]+]] {3439// CHECK5-NEXT: entry:3440// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 83441// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 43442// CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 83443// CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 83444// CHECK5-NEXT: [[N_CASTED:%.*]] = alloca i64, align 83445// CHECK5-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 83446// CHECK5-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 43447// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4, !dbg [[DBG105:![0-9]+]]3448// CHECK5-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64, !dbg [[DBG105]]3449// CHECK5-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0(), !dbg [[DBG105]]3450// CHECK5-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8, !dbg [[DBG105]]3451// CHECK5-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 16, !dbg [[DBG105]]3452// CHECK5-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8, !dbg [[DBG105]]3453// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4, !dbg [[DBG106:![0-9]+]]3454// CHECK5-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4, !dbg [[DBG106]]3455// CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8, !dbg [[DBG106]]3456// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB32:[0-9]+]], i32 3, ptr @_Z12parallel_forPfi.omp_outlined, ptr [[A_ADDR]], i64 [[TMP1]], i64 [[TMP4]]), !dbg [[DBG106]]3457// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8, !dbg [[DBG107:![0-9]+]]3458// CHECK5-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP5]]), !dbg [[DBG107]]3459// CHECK5-NEXT: ret void, !dbg [[DBG107]]3460//3461//3462// CHECK5-LABEL: define {{[^@]+}}@_Z12parallel_forPfi.omp_outlined3463// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[N:%.*]]) #[[ATTR1]] personality ptr @__gxx_personality_v0 !dbg [[DBG108:![0-9]+]] {3464// CHECK5-NEXT: entry:3465// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 83466// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 83467// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 83468// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 83469// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 83470// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 43471// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 43472// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 43473// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 43474// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 43475// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 43476// CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 83477// CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 83478// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 43479// CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 83480// CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 83481// CHECK5-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 83482// CHECK5-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 83483// CHECK5-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 83484// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG109:![0-9]+]]3485// CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8, !dbg [[DBG109]]3486// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG110:![0-9]+]]3487// CHECK5-NEXT: store i32 16908288, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG110]]3488// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG110]]3489// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG110]]3490// CHECK5-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0(), !dbg [[DBG109]]3491// CHECK5-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8, !dbg [[DBG109]]3492// CHECK5-NEXT: [[VLA1:%.*]] = alloca float, i64 [[TMP1]], align 16, !dbg [[DBG109]]3493// CHECK5-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8, !dbg [[DBG109]]3494// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG109]]3495// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4, !dbg [[DBG109]]3496// CHECK5-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB29:[0-9]+]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5), !dbg [[DBG109]]3497// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG109]]3498// CHECK5: omp.dispatch.cond:3499// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG110]]3500// CHECK5-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP5]], 16908288, !dbg [[DBG110]]3501// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG110]]3502// CHECK5: cond.true:3503// CHECK5-NEXT: br label [[COND_END:%.*]], !dbg [[DBG110]]3504// CHECK5: cond.false:3505// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG110]]3506// CHECK5-NEXT: br label [[COND_END]], !dbg [[DBG110]]3507// CHECK5: cond.end:3508// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ], !dbg [[DBG110]]3509// CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG110]]3510// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG110]]3511// CHECK5-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG110]]3512// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG110]]3513// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG110]]3514// CHECK5-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP8]], [[TMP9]], !dbg [[DBG110]]3515// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_CLEANUP:%.*]], !dbg [[DBG109]]3516// CHECK5: omp.dispatch.cleanup:3517// CHECK5-NEXT: br label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG109]]3518// CHECK5: omp.dispatch.body:3519// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG109]]3520// CHECK5: omp.inner.for.cond:3521// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG110]]3522// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG110]]3523// CHECK5-NEXT: [[CMP3:%.*]] = icmp ule i32 [[TMP10]], [[TMP11]], !dbg [[DBG110]]3524// CHECK5-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]], !dbg [[DBG109]]3525// CHECK5: omp.inner.for.cond.cleanup:3526// CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG109]]3527// CHECK5: omp.inner.for.body:3528// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG110]]3529// CHECK5-NEXT: [[MUL:%.*]] = mul i32 [[TMP12]], 127, !dbg [[DBG110]]3530// CHECK5-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]], !dbg [[DBG110]]3531// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !dbg [[DBG110]]3532// CHECK5-NEXT: [[CALL:%.*]] = invoke noundef i32 @_Z3foov()3533// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG111:![0-9]+]]3534// CHECK5: invoke.cont:3535// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[CALL]] to float, !dbg [[DBG111]]3536// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG111]]3537// CHECK5-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP13]] to i64, !dbg [[DBG111]]3538// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[VLA1]], i64 [[IDXPROM]], !dbg [[DBG111]]3539// CHECK5-NEXT: [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !dbg [[DBG111]]3540// CHECK5-NEXT: [[ADD4:%.*]] = fadd float [[CONV]], [[TMP14]], !dbg [[DBG111]]3541// CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[N_ADDR]], align 4, !dbg [[DBG111]]3542// CHECK5-NEXT: [[CONV5:%.*]] = sitofp i32 [[TMP15]] to float, !dbg [[DBG111]]3543// CHECK5-NEXT: [[ADD6:%.*]] = fadd float [[ADD4]], [[CONV5]], !dbg [[DBG111]]3544// CHECK5-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP0]], align 8, !dbg [[DBG111]]3545// CHECK5-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG111]]3546// CHECK5-NEXT: [[IDXPROM7:%.*]] = zext i32 [[TMP17]] to i64, !dbg [[DBG111]]3547// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds nuw float, ptr [[TMP16]], i64 [[IDXPROM7]], !dbg [[DBG111]]3548// CHECK5-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX8]], align 4, !dbg [[DBG111]]3549// CHECK5-NEXT: [[ADD9:%.*]] = fadd float [[TMP18]], [[ADD6]], !dbg [[DBG111]]3550// CHECK5-NEXT: store float [[ADD9]], ptr [[ARRAYIDX8]], align 4, !dbg [[DBG111]]3551// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG111]]3552// CHECK5: omp.body.continue:3553// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG109]]3554// CHECK5: omp.inner.for.inc:3555// CHECK5-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG110]]3556// CHECK5-NEXT: [[ADD10:%.*]] = add i32 [[TMP19]], 1, !dbg [[DBG110]]3557// CHECK5-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG110]]3558// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG109]], !llvm.loop [[LOOP112:![0-9]+]]3559// CHECK5: omp.inner.for.end:3560// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG109]]3561// CHECK5: omp.dispatch.inc:3562// CHECK5-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG110]]3563// CHECK5-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG110]]3564// CHECK5-NEXT: [[ADD11:%.*]] = add i32 [[TMP20]], [[TMP21]], !dbg [[DBG110]]3565// CHECK5-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_LB]], align 4, !dbg [[DBG110]]3566// CHECK5-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG110]]3567// CHECK5-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG110]]3568// CHECK5-NEXT: [[ADD12:%.*]] = add i32 [[TMP22]], [[TMP23]], !dbg [[DBG110]]3569// CHECK5-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG110]]3570// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG109]], !llvm.loop [[LOOP113:![0-9]+]]3571// CHECK5: omp.dispatch.end:3572// CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB31:[0-9]+]], i32 [[TMP4]]), !dbg [[DBG109]]3573// CHECK5-NEXT: [[TMP24:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8, !dbg [[DBG109]]3574// CHECK5-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP24]]), !dbg [[DBG109]]3575// CHECK5-NEXT: ret void, !dbg [[DBG111]]3576// CHECK5: terminate.lpad:3577// CHECK5-NEXT: [[TMP25:%.*]] = landingpad { ptr, i32 }3578// CHECK5-NEXT: catch ptr null, !dbg [[DBG111]]3579// CHECK5-NEXT: [[TMP26:%.*]] = extractvalue { ptr, i32 } [[TMP25]], 0, !dbg [[DBG111]]3580// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP26]]) #[[ATTR7:[0-9]+]], !dbg [[DBG111]]3581// CHECK5-NEXT: unreachable, !dbg [[DBG111]]3582//3583//3584// CHECK5-LABEL: define {{[^@]+}}@__clang_call_terminate3585// CHECK5-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR6:[0-9]+]] {3586// CHECK5-NEXT: [[TMP2:%.*]] = call ptr @__cxa_begin_catch(ptr [[TMP0]]) #[[ATTR2:[0-9]+]]3587// CHECK5-NEXT: call void @_ZSt9terminatev() #[[ATTR7]]3588// CHECK5-NEXT: unreachable3589//3590//3591// CHECK6-LABEL: define {{[^@]+}}@_Z17with_var_schedulev3592// CHECK6-SAME: () #[[ATTR0:[0-9]+]] {3593// CHECK6-NEXT: entry:3594// CHECK6-NEXT: [[A:%.*]] = alloca double, align 83595// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 13596// CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 83597// CHECK6-NEXT: store double 5.000000e+00, ptr [[A]], align 83598// CHECK6-NEXT: [[TMP0:%.*]] = load double, ptr [[A]], align 83599// CHECK6-NEXT: [[CONV:%.*]] = fptosi double [[TMP0]] to i83600// CHECK6-NEXT: store i8 [[CONV]], ptr [[DOTCAPTURE_EXPR_]], align 13601// CHECK6-NEXT: [[TMP1:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 13602// CHECK6-NEXT: store i8 [[TMP1]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 13603// CHECK6-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 83604// CHECK6-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 1, ptr @_Z17with_var_schedulev.omp_outlined, i64 [[TMP2]])3605// CHECK6-NEXT: ret void3606//3607//3608// CHECK6-LABEL: define {{[^@]+}}@_Z17with_var_schedulev.omp_outlined3609// CHECK6-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] {3610// CHECK6-NEXT: entry:3611// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 83612// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 83613// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 83614// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 83615// CHECK6-NEXT: [[TMP:%.*]] = alloca i64, align 83616// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca double, align 83617// CHECK6-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 83618// CHECK6-NEXT: [[I:%.*]] = alloca i64, align 83619// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 83620// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 83621// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 83622// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 43623// CHECK6-NEXT: [[A:%.*]] = alloca double, align 83624// CHECK6-NEXT: [[I4:%.*]] = alloca i64, align 83625// CHECK6-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 83626// CHECK6-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 83627// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 83628// CHECK6-NEXT: [[TMP0:%.*]] = load double, ptr undef, align 83629// CHECK6-NEXT: [[ADD:%.*]] = fadd double 2.000000e+00, [[TMP0]]3630// CHECK6-NEXT: store double [[ADD]], ptr [[DOTCAPTURE_EXPR_1]], align 83631// CHECK6-NEXT: [[TMP1:%.*]] = load double, ptr [[DOTCAPTURE_EXPR_1]], align 83632// CHECK6-NEXT: [[SUB:%.*]] = fsub double [[TMP1]], 1.000000e+003633// CHECK6-NEXT: [[DIV:%.*]] = fdiv double [[SUB]], 1.000000e+003634// CHECK6-NEXT: [[CONV:%.*]] = fptoui double [[DIV]] to i643635// CHECK6-NEXT: [[SUB3:%.*]] = sub i64 [[CONV]], 13636// CHECK6-NEXT: store i64 [[SUB3]], ptr [[DOTCAPTURE_EXPR_2]], align 83637// CHECK6-NEXT: store i64 1, ptr [[I]], align 83638// CHECK6-NEXT: [[TMP2:%.*]] = load double, ptr [[DOTCAPTURE_EXPR_1]], align 83639// CHECK6-NEXT: [[CMP:%.*]] = fcmp olt double 1.000000e+00, [[TMP2]]3640// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]3641// CHECK6: omp.precond.then:3642// CHECK6-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 83643// CHECK6-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 83644// CHECK6-NEXT: store i64 [[TMP3]], ptr [[DOTOMP_UB]], align 83645// CHECK6-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 83646// CHECK6-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 43647// CHECK6-NEXT: [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 13648// CHECK6-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i643649// CHECK6-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 83650// CHECK6-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 43651// CHECK6-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 [[CONV5]])3652// CHECK6-NEXT: br label [[OMP_DISPATCH_COND:%.*]]3653// CHECK6: omp.dispatch.cond:3654// CHECK6-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 83655// CHECK6-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 83656// CHECK6-NEXT: [[CMP6:%.*]] = icmp ugt i64 [[TMP7]], [[TMP8]]3657// CHECK6-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]3658// CHECK6: cond.true:3659// CHECK6-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 83660// CHECK6-NEXT: br label [[COND_END:%.*]]3661// CHECK6: cond.false:3662// CHECK6-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 83663// CHECK6-NEXT: br label [[COND_END]]3664// CHECK6: cond.end:3665// CHECK6-NEXT: [[COND:%.*]] = phi i64 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]3666// CHECK6-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 83667// CHECK6-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_LB]], align 83668// CHECK6-NEXT: store i64 [[TMP11]], ptr [[DOTOMP_IV]], align 83669// CHECK6-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 83670// CHECK6-NEXT: [[TMP13:%.*]] = load i64, ptr [[DOTOMP_UB]], align 83671// CHECK6-NEXT: [[ADD7:%.*]] = add i64 [[TMP13]], 13672// CHECK6-NEXT: [[CMP8:%.*]] = icmp ult i64 [[TMP12]], [[ADD7]]3673// CHECK6-NEXT: br i1 [[CMP8]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]3674// CHECK6: omp.dispatch.body:3675// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]3676// CHECK6: omp.inner.for.cond:3677// CHECK6-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 83678// CHECK6-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_UB]], align 83679// CHECK6-NEXT: [[ADD9:%.*]] = add i64 [[TMP15]], 13680// CHECK6-NEXT: [[CMP10:%.*]] = icmp ult i64 [[TMP14]], [[ADD9]]3681// CHECK6-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]3682// CHECK6: omp.inner.for.body:3683// CHECK6-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 83684// CHECK6-NEXT: [[MUL:%.*]] = mul i64 [[TMP16]], 13685// CHECK6-NEXT: [[ADD11:%.*]] = add i64 1, [[MUL]]3686// CHECK6-NEXT: store i64 [[ADD11]], ptr [[I4]], align 83687// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]3688// CHECK6: omp.body.continue:3689// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]3690// CHECK6: omp.inner.for.inc:3691// CHECK6-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 83692// CHECK6-NEXT: [[ADD12:%.*]] = add i64 [[TMP17]], 13693// CHECK6-NEXT: store i64 [[ADD12]], ptr [[DOTOMP_IV]], align 83694// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]]3695// CHECK6: omp.inner.for.end:3696// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]]3697// CHECK6: omp.dispatch.inc:3698// CHECK6-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTOMP_LB]], align 83699// CHECK6-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_STRIDE]], align 83700// CHECK6-NEXT: [[ADD13:%.*]] = add i64 [[TMP18]], [[TMP19]]3701// CHECK6-NEXT: store i64 [[ADD13]], ptr [[DOTOMP_LB]], align 83702// CHECK6-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_UB]], align 83703// CHECK6-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_STRIDE]], align 83704// CHECK6-NEXT: [[ADD14:%.*]] = add i64 [[TMP20]], [[TMP21]]3705// CHECK6-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_UB]], align 83706// CHECK6-NEXT: br label [[OMP_DISPATCH_COND]]3707// CHECK6: omp.dispatch.end:3708// CHECK6-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 83709// CHECK6-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 43710// CHECK6-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP23]])3711// CHECK6-NEXT: br label [[OMP_PRECOND_END]]3712// CHECK6: omp.precond.end:3713// CHECK6-NEXT: ret void3714//3715//3716// CHECK6-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_3717// CHECK6-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {3718// CHECK6-NEXT: entry:3719// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 83720// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 83721// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 83722// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 83723// CHECK6-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 83724// CHECK6-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 83725// CHECK6-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 83726// CHECK6-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 83727// CHECK6-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_Z23without_schedule_clausePfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])3728// CHECK6-NEXT: ret void3729//3730//3731// CHECK6-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_.omp_outlined3732// CHECK6-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {3733// CHECK6-NEXT: entry:3734// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 83735// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 83736// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 83737// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 83738// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 83739// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 83740// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 43741// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 43742// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 43743// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 43744// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 43745// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 43746// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 43747// CHECK6-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 83748// CHECK6-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 83749// CHECK6-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 83750// CHECK6-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 83751// CHECK6-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 83752// CHECK6-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 83753// CHECK6-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 83754// CHECK6-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 83755// CHECK6-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 83756// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 83757// CHECK6-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 43758// CHECK6-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 43759// CHECK6-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 43760// CHECK6-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 43761// CHECK6-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 83762// CHECK6-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 43763// CHECK6-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)3764// CHECK6-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43765// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 45714233766// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]3767// CHECK6: cond.true:3768// CHECK6-NEXT: br label [[COND_END:%.*]]3769// CHECK6: cond.false:3770// CHECK6-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43771// CHECK6-NEXT: br label [[COND_END]]3772// CHECK6: cond.end:3773// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]3774// CHECK6-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 43775// CHECK6-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 43776// CHECK6-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 43777// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]3778// CHECK6: omp.inner.for.cond:3779// CHECK6-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43780// CHECK6-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43781// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]3782// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]3783// CHECK6: omp.inner.for.body:3784// CHECK6-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43785// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 73786// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]3787// CHECK6-NEXT: store i32 [[ADD]], ptr [[I]], align 43788// CHECK6-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 83789// CHECK6-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 43790// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i643791// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[IDXPROM]]3792// CHECK6-NEXT: [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 43793// CHECK6-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP2]], align 83794// CHECK6-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 43795// CHECK6-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i643796// CHECK6-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[IDXPROM2]]3797// CHECK6-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX3]], align 43798// CHECK6-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]]3799// CHECK6-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP3]], align 83800// CHECK6-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 43801// CHECK6-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i643802// CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[IDXPROM5]]3803// CHECK6-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX6]], align 43804// CHECK6-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]]3805// CHECK6-NEXT: [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 83806// CHECK6-NEXT: [[TMP22:%.*]] = load i32, ptr [[I]], align 43807// CHECK6-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i643808// CHECK6-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i64 [[IDXPROM8]]3809// CHECK6-NEXT: store float [[MUL7]], ptr [[ARRAYIDX9]], align 43810// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]3811// CHECK6: omp.body.continue:3812// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]3813// CHECK6: omp.inner.for.inc:3814// CHECK6-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43815// CHECK6-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP23]], 13816// CHECK6-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 43817// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]]3818// CHECK6: omp.inner.for.end:3819// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]3820// CHECK6: omp.loop.exit:3821// CHECK6-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])3822// CHECK6-NEXT: ret void3823//3824//3825// CHECK6-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_3826// CHECK6-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {3827// CHECK6-NEXT: entry:3828// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 83829// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 83830// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 83831// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 83832// CHECK6-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 83833// CHECK6-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 83834// CHECK6-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 83835// CHECK6-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 83836// CHECK6-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_Z18static_not_chunkedPfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])3837// CHECK6-NEXT: ret void3838//3839//3840// CHECK6-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_.omp_outlined3841// CHECK6-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {3842// CHECK6-NEXT: entry:3843// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 83844// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 83845// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 83846// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 83847// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 83848// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 83849// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 43850// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 43851// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 43852// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 43853// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 43854// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 43855// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 43856// CHECK6-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 83857// CHECK6-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 83858// CHECK6-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 83859// CHECK6-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 83860// CHECK6-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 83861// CHECK6-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 83862// CHECK6-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 83863// CHECK6-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 83864// CHECK6-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 83865// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 83866// CHECK6-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 43867// CHECK6-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 43868// CHECK6-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 43869// CHECK6-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 43870// CHECK6-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 83871// CHECK6-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 43872// CHECK6-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)3873// CHECK6-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43874// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 45714233875// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]3876// CHECK6: cond.true:3877// CHECK6-NEXT: br label [[COND_END:%.*]]3878// CHECK6: cond.false:3879// CHECK6-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43880// CHECK6-NEXT: br label [[COND_END]]3881// CHECK6: cond.end:3882// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]3883// CHECK6-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 43884// CHECK6-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 43885// CHECK6-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 43886// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]3887// CHECK6: omp.inner.for.cond:3888// CHECK6-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43889// CHECK6-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43890// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]3891// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]3892// CHECK6: omp.inner.for.body:3893// CHECK6-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43894// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 73895// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]3896// CHECK6-NEXT: store i32 [[SUB]], ptr [[I]], align 43897// CHECK6-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 83898// CHECK6-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 43899// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i643900// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[IDXPROM]]3901// CHECK6-NEXT: [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 43902// CHECK6-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP2]], align 83903// CHECK6-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 43904// CHECK6-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i643905// CHECK6-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[IDXPROM2]]3906// CHECK6-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX3]], align 43907// CHECK6-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]]3908// CHECK6-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP3]], align 83909// CHECK6-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 43910// CHECK6-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i643911// CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[IDXPROM5]]3912// CHECK6-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX6]], align 43913// CHECK6-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]]3914// CHECK6-NEXT: [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 83915// CHECK6-NEXT: [[TMP22:%.*]] = load i32, ptr [[I]], align 43916// CHECK6-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i643917// CHECK6-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i64 [[IDXPROM8]]3918// CHECK6-NEXT: store float [[MUL7]], ptr [[ARRAYIDX9]], align 43919// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]3920// CHECK6: omp.body.continue:3921// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]3922// CHECK6: omp.inner.for.inc:3923// CHECK6-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43924// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 13925// CHECK6-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 43926// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]]3927// CHECK6: omp.inner.for.end:3928// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]3929// CHECK6: omp.loop.exit:3930// CHECK6-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])3931// CHECK6-NEXT: ret void3932//3933//3934// CHECK6-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_3935// CHECK6-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {3936// CHECK6-NEXT: entry:3937// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 83938// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 83939// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 83940// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 83941// CHECK6-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 83942// CHECK6-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 83943// CHECK6-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 83944// CHECK6-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 83945// CHECK6-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_Z14static_chunkedPfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])3946// CHECK6-NEXT: ret void3947//3948//3949// CHECK6-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_.omp_outlined3950// CHECK6-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {3951// CHECK6-NEXT: entry:3952// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 83953// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 83954// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 83955// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 83956// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 83957// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 83958// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 43959// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 43960// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 43961// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 43962// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 43963// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 43964// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 43965// CHECK6-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 83966// CHECK6-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 83967// CHECK6-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 83968// CHECK6-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 83969// CHECK6-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 83970// CHECK6-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 83971// CHECK6-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 83972// CHECK6-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 83973// CHECK6-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 83974// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 83975// CHECK6-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 43976// CHECK6-NEXT: store i32 16908288, ptr [[DOTOMP_UB]], align 43977// CHECK6-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 43978// CHECK6-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 43979// CHECK6-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 83980// CHECK6-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 43981// CHECK6-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP5]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5)3982// CHECK6-NEXT: br label [[OMP_DISPATCH_COND:%.*]]3983// CHECK6: omp.dispatch.cond:3984// CHECK6-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43985// CHECK6-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 169082883986// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]3987// CHECK6: cond.true:3988// CHECK6-NEXT: br label [[COND_END:%.*]]3989// CHECK6: cond.false:3990// CHECK6-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43991// CHECK6-NEXT: br label [[COND_END]]3992// CHECK6: cond.end:3993// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]3994// CHECK6-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 43995// CHECK6-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 43996// CHECK6-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 43997// CHECK6-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43998// CHECK6-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43999// CHECK6-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]4000// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]4001// CHECK6: omp.dispatch.body:4002// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]4003// CHECK6: omp.inner.for.cond:4004// CHECK6-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44005// CHECK6-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44006// CHECK6-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]4007// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]4008// CHECK6: omp.inner.for.body:4009// CHECK6-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44010// CHECK6-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 1274011// CHECK6-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]4012// CHECK6-NEXT: store i32 [[ADD]], ptr [[I]], align 44013// CHECK6-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP1]], align 84014// CHECK6-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 44015// CHECK6-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i644016// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP14]], i64 [[IDXPROM]]4017// CHECK6-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 44018// CHECK6-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP2]], align 84019// CHECK6-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 44020// CHECK6-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i644021// CHECK6-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw float, ptr [[TMP17]], i64 [[IDXPROM3]]4022// CHECK6-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 44023// CHECK6-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]4024// CHECK6-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP3]], align 84025// CHECK6-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 44026// CHECK6-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i644027// CHECK6-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds nuw float, ptr [[TMP20]], i64 [[IDXPROM6]]4028// CHECK6-NEXT: [[TMP22:%.*]] = load float, ptr [[ARRAYIDX7]], align 44029// CHECK6-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]4030// CHECK6-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP0]], align 84031// CHECK6-NEXT: [[TMP24:%.*]] = load i32, ptr [[I]], align 44032// CHECK6-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i644033// CHECK6-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds nuw float, ptr [[TMP23]], i64 [[IDXPROM9]]4034// CHECK6-NEXT: store float [[MUL8]], ptr [[ARRAYIDX10]], align 44035// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]4036// CHECK6: omp.body.continue:4037// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]4038// CHECK6: omp.inner.for.inc:4039// CHECK6-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44040// CHECK6-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 14041// CHECK6-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 44042// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]]4043// CHECK6: omp.inner.for.end:4044// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]]4045// CHECK6: omp.dispatch.inc:4046// CHECK6-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB]], align 44047// CHECK6-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 44048// CHECK6-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]4049// CHECK6-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_LB]], align 44050// CHECK6-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44051// CHECK6-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 44052// CHECK6-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]]4053// CHECK6-NEXT: store i32 [[ADD13]], ptr [[DOTOMP_UB]], align 44054// CHECK6-NEXT: br label [[OMP_DISPATCH_COND]]4055// CHECK6: omp.dispatch.end:4056// CHECK6-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])4057// CHECK6-NEXT: ret void4058//4059//4060// CHECK6-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_4061// CHECK6-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {4062// CHECK6-NEXT: entry:4063// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 84064// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 84065// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 84066// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 84067// CHECK6-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 84068// CHECK6-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 84069// CHECK6-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 84070// CHECK6-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 84071// CHECK6-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_Z8dynamic1PfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])4072// CHECK6-NEXT: ret void4073//4074//4075// CHECK6-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_.omp_outlined4076// CHECK6-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {4077// CHECK6-NEXT: entry:4078// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 84079// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 84080// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 84081// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 84082// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 84083// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 84084// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 84085// CHECK6-NEXT: [[TMP:%.*]] = alloca i64, align 84086// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 84087// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 84088// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 84089// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 44090// CHECK6-NEXT: [[I:%.*]] = alloca i64, align 84091// CHECK6-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 84092// CHECK6-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 84093// CHECK6-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 84094// CHECK6-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 84095// CHECK6-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 84096// CHECK6-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 84097// CHECK6-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 84098// CHECK6-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 84099// CHECK6-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 84100// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 84101// CHECK6-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 84102// CHECK6-NEXT: store i64 16908287, ptr [[DOTOMP_UB]], align 84103// CHECK6-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 84104// CHECK6-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 44105// CHECK6-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 84106// CHECK6-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 44107// CHECK6-NEXT: call void @__kmpc_dispatch_init_8u(ptr @[[GLOB2]], i32 [[TMP5]], i32 1073741859, i64 0, i64 16908287, i64 1, i64 1)4108// CHECK6-NEXT: br label [[OMP_DISPATCH_COND:%.*]]4109// CHECK6: omp.dispatch.cond:4110// CHECK6-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8u(ptr @[[GLOB2]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])4111// CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 04112// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]4113// CHECK6: omp.dispatch.body:4114// CHECK6-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_LB]], align 84115// CHECK6-NEXT: store i64 [[TMP7]], ptr [[DOTOMP_IV]], align 84116// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]4117// CHECK6: omp.inner.for.cond:4118// CHECK6-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5:![0-9]+]]4119// CHECK6-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP5]]4120// CHECK6-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 14121// CHECK6-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]]4122// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]4123// CHECK6: omp.inner.for.body:4124// CHECK6-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]]4125// CHECK6-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 1274126// CHECK6-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]]4127// CHECK6-NEXT: store i64 [[ADD1]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP5]]4128// CHECK6-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP5]]4129// CHECK6-NEXT: [[TMP12:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP5]]4130// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP11]], i64 [[TMP12]]4131// CHECK6-NEXT: [[TMP13:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]]4132// CHECK6-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP5]]4133// CHECK6-NEXT: [[TMP15:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP5]]4134// CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw float, ptr [[TMP14]], i64 [[TMP15]]4135// CHECK6-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP5]]4136// CHECK6-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]]4137// CHECK6-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP5]]4138// CHECK6-NEXT: [[TMP18:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP5]]4139// CHECK6-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw float, ptr [[TMP17]], i64 [[TMP18]]4140// CHECK6-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP5]]4141// CHECK6-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]]4142// CHECK6-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP5]]4143// CHECK6-NEXT: [[TMP21:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP5]]4144// CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds nuw float, ptr [[TMP20]], i64 [[TMP21]]4145// CHECK6-NEXT: store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP5]]4146// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]4147// CHECK6: omp.body.continue:4148// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]4149// CHECK6: omp.inner.for.inc:4150// CHECK6-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]]4151// CHECK6-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 14152// CHECK6-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]]4153// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]4154// CHECK6: omp.inner.for.end:4155// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]]4156// CHECK6: omp.dispatch.inc:4157// CHECK6-NEXT: br label [[OMP_DISPATCH_COND]]4158// CHECK6: omp.dispatch.end:4159// CHECK6-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB2]], i32 [[TMP5]])4160// CHECK6-NEXT: ret void4161//4162//4163// CHECK6-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_4164// CHECK6-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {4165// CHECK6-NEXT: entry:4166// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 84167// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 84168// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 84169// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 84170// CHECK6-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 84171// CHECK6-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 84172// CHECK6-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 84173// CHECK6-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 84174// CHECK6-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_Z7guided7PfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])4175// CHECK6-NEXT: ret void4176//4177//4178// CHECK6-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_.omp_outlined4179// CHECK6-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {4180// CHECK6-NEXT: entry:4181// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 84182// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 84183// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 84184// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 84185// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 84186// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 84187// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 84188// CHECK6-NEXT: [[TMP:%.*]] = alloca i64, align 84189// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 84190// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 84191// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 84192// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 44193// CHECK6-NEXT: [[I:%.*]] = alloca i64, align 84194// CHECK6-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 84195// CHECK6-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 84196// CHECK6-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 84197// CHECK6-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 84198// CHECK6-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 84199// CHECK6-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 84200// CHECK6-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 84201// CHECK6-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 84202// CHECK6-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 84203// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 84204// CHECK6-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 84205// CHECK6-NEXT: store i64 16908287, ptr [[DOTOMP_UB]], align 84206// CHECK6-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 84207// CHECK6-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 44208// CHECK6-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 84209// CHECK6-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 44210// CHECK6-NEXT: call void @__kmpc_dispatch_init_8u(ptr @[[GLOB2]], i32 [[TMP5]], i32 1073741860, i64 0, i64 16908287, i64 1, i64 7)4211// CHECK6-NEXT: br label [[OMP_DISPATCH_COND:%.*]]4212// CHECK6: omp.dispatch.cond:4213// CHECK6-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8u(ptr @[[GLOB2]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])4214// CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 04215// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]4216// CHECK6: omp.dispatch.body:4217// CHECK6-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_LB]], align 84218// CHECK6-NEXT: store i64 [[TMP7]], ptr [[DOTOMP_IV]], align 84219// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]4220// CHECK6: omp.inner.for.cond:4221// CHECK6-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP8:![0-9]+]]4222// CHECK6-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP8]]4223// CHECK6-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 14224// CHECK6-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]]4225// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]4226// CHECK6: omp.inner.for.body:4227// CHECK6-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP8]]4228// CHECK6-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 1274229// CHECK6-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]]4230// CHECK6-NEXT: store i64 [[ADD1]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP8]]4231// CHECK6-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP8]]4232// CHECK6-NEXT: [[TMP12:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP8]]4233// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP11]], i64 [[TMP12]]4234// CHECK6-NEXT: [[TMP13:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP8]]4235// CHECK6-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP8]]4236// CHECK6-NEXT: [[TMP15:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP8]]4237// CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw float, ptr [[TMP14]], i64 [[TMP15]]4238// CHECK6-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP8]]4239// CHECK6-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]]4240// CHECK6-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP8]]4241// CHECK6-NEXT: [[TMP18:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP8]]4242// CHECK6-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw float, ptr [[TMP17]], i64 [[TMP18]]4243// CHECK6-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP8]]4244// CHECK6-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]]4245// CHECK6-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP8]]4246// CHECK6-NEXT: [[TMP21:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP8]]4247// CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds nuw float, ptr [[TMP20]], i64 [[TMP21]]4248// CHECK6-NEXT: store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP8]]4249// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]4250// CHECK6: omp.body.continue:4251// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]4252// CHECK6: omp.inner.for.inc:4253// CHECK6-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP8]]4254// CHECK6-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 14255// CHECK6-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP8]]4256// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]4257// CHECK6: omp.inner.for.end:4258// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]]4259// CHECK6: omp.dispatch.inc:4260// CHECK6-NEXT: br label [[OMP_DISPATCH_COND]]4261// CHECK6: omp.dispatch.end:4262// CHECK6-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB2]], i32 [[TMP5]])4263// CHECK6-NEXT: ret void4264//4265//4266// CHECK6-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_4267// CHECK6-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {4268// CHECK6-NEXT: entry:4269// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 84270// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 84271// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 84272// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 84273// CHECK6-NEXT: [[X:%.*]] = alloca i32, align 44274// CHECK6-NEXT: [[Y:%.*]] = alloca i32, align 44275// CHECK6-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 84276// CHECK6-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 84277// CHECK6-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 84278// CHECK6-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 84279// CHECK6-NEXT: store i32 0, ptr [[X]], align 44280// CHECK6-NEXT: store i32 0, ptr [[Y]], align 44281// CHECK6-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @_Z9test_autoPfS_S_S_.omp_outlined, ptr [[Y]], ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])4282// CHECK6-NEXT: ret void4283//4284//4285// CHECK6-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_.omp_outlined4286// CHECK6-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[Y:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {4287// CHECK6-NEXT: entry:4288// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 84289// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 84290// CHECK6-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 84291// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 84292// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 84293// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 84294// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 84295// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 84296// CHECK6-NEXT: [[TMP:%.*]] = alloca i8, align 14297// CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 44298// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 14299// CHECK6-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 84300// CHECK6-NEXT: [[I:%.*]] = alloca i8, align 14301// CHECK6-NEXT: [[X:%.*]] = alloca i32, align 44302// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 84303// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 84304// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 84305// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 44306// CHECK6-NEXT: [[I7:%.*]] = alloca i8, align 14307// CHECK6-NEXT: [[X8:%.*]] = alloca i32, align 44308// CHECK6-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 84309// CHECK6-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 84310// CHECK6-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 84311// CHECK6-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 84312// CHECK6-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 84313// CHECK6-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 84314// CHECK6-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 84315// CHECK6-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 84316// CHECK6-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 84317// CHECK6-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 84318// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 84319// CHECK6-NEXT: [[TMP4:%.*]] = load ptr, ptr [[D_ADDR]], align 84320// CHECK6-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 44321// CHECK6-NEXT: [[CONV:%.*]] = trunc i32 [[TMP5]] to i84322// CHECK6-NEXT: store i8 [[CONV]], ptr [[DOTCAPTURE_EXPR_]], align 14323// CHECK6-NEXT: [[TMP6:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 14324// CHECK6-NEXT: [[CONV3:%.*]] = sext i8 [[TMP6]] to i324325// CHECK6-NEXT: [[SUB:%.*]] = sub i32 57, [[CONV3]]4326// CHECK6-NEXT: [[ADD:%.*]] = add i32 [[SUB]], 14327// CHECK6-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 14328// CHECK6-NEXT: [[CONV4:%.*]] = zext i32 [[DIV]] to i644329// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV4]], 114330// CHECK6-NEXT: [[SUB5:%.*]] = sub nsw i64 [[MUL]], 14331// CHECK6-NEXT: store i64 [[SUB5]], ptr [[DOTCAPTURE_EXPR_2]], align 84332// CHECK6-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 14333// CHECK6-NEXT: store i8 [[TMP7]], ptr [[I]], align 14334// CHECK6-NEXT: store i32 11, ptr [[X]], align 44335// CHECK6-NEXT: [[TMP8:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 14336// CHECK6-NEXT: [[CONV6:%.*]] = sext i8 [[TMP8]] to i324337// CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV6]], 574338// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]4339// CHECK6: omp.precond.then:4340// CHECK6-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 84341// CHECK6-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 84342// CHECK6-NEXT: store i64 [[TMP9]], ptr [[DOTOMP_UB]], align 84343// CHECK6-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 84344// CHECK6-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 44345// CHECK6-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 84346// CHECK6-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 84347// CHECK6-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 44348// CHECK6-NEXT: call void @__kmpc_dispatch_init_8(ptr @[[GLOB2]], i32 [[TMP12]], i32 1073741862, i64 0, i64 [[TMP10]], i64 1, i64 1)4349// CHECK6-NEXT: br label [[OMP_DISPATCH_COND:%.*]]4350// CHECK6: omp.dispatch.cond:4351// CHECK6-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 84352// CHECK6-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 44353// CHECK6-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_dispatch_next_8(ptr @[[GLOB2]], i32 [[TMP14]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])4354// CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 04355// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]4356// CHECK6: omp.dispatch.body:4357// CHECK6-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_LB]], align 84358// CHECK6-NEXT: store i64 [[TMP16]], ptr [[DOTOMP_IV]], align 84359// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]4360// CHECK6: omp.inner.for.cond:4361// CHECK6-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11:![0-9]+]]4362// CHECK6-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP11]]4363// CHECK6-NEXT: [[CMP9:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]]4364// CHECK6-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]4365// CHECK6: omp.inner.for.body:4366// CHECK6-NEXT: [[TMP19:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP11]]4367// CHECK6-NEXT: [[CONV10:%.*]] = sext i8 [[TMP19]] to i644368// CHECK6-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11]]4369// CHECK6-NEXT: [[DIV11:%.*]] = sdiv i64 [[TMP20]], 114370// CHECK6-NEXT: [[MUL12:%.*]] = mul nsw i64 [[DIV11]], 14371// CHECK6-NEXT: [[ADD13:%.*]] = add nsw i64 [[CONV10]], [[MUL12]]4372// CHECK6-NEXT: [[CONV14:%.*]] = trunc i64 [[ADD13]] to i84373// CHECK6-NEXT: store i8 [[CONV14]], ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP11]]4374// CHECK6-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11]]4375// CHECK6-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11]]4376// CHECK6-NEXT: [[DIV15:%.*]] = sdiv i64 [[TMP22]], 114377// CHECK6-NEXT: [[MUL16:%.*]] = mul nsw i64 [[DIV15]], 114378// CHECK6-NEXT: [[SUB17:%.*]] = sub nsw i64 [[TMP21]], [[MUL16]]4379// CHECK6-NEXT: [[MUL18:%.*]] = mul nsw i64 [[SUB17]], 14380// CHECK6-NEXT: [[SUB19:%.*]] = sub nsw i64 11, [[MUL18]]4381// CHECK6-NEXT: [[CONV20:%.*]] = trunc i64 [[SUB19]] to i324382// CHECK6-NEXT: store i32 [[CONV20]], ptr [[X8]], align 4, !llvm.access.group [[ACC_GRP11]]4383// CHECK6-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP11]]4384// CHECK6-NEXT: [[TMP24:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP11]]4385// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP24]] to i644386// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i64 [[IDXPROM]]4387// CHECK6-NEXT: [[TMP25:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP11]]4388// CHECK6-NEXT: [[TMP26:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP11]]4389// CHECK6-NEXT: [[TMP27:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP11]]4390// CHECK6-NEXT: [[IDXPROM21:%.*]] = sext i8 [[TMP27]] to i644391// CHECK6-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds float, ptr [[TMP26]], i64 [[IDXPROM21]]4392// CHECK6-NEXT: [[TMP28:%.*]] = load float, ptr [[ARRAYIDX22]], align 4, !llvm.access.group [[ACC_GRP11]]4393// CHECK6-NEXT: [[MUL23:%.*]] = fmul float [[TMP25]], [[TMP28]]4394// CHECK6-NEXT: [[TMP29:%.*]] = load ptr, ptr [[TMP4]], align 8, !llvm.access.group [[ACC_GRP11]]4395// CHECK6-NEXT: [[TMP30:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP11]]4396// CHECK6-NEXT: [[IDXPROM24:%.*]] = sext i8 [[TMP30]] to i644397// CHECK6-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds float, ptr [[TMP29]], i64 [[IDXPROM24]]4398// CHECK6-NEXT: [[TMP31:%.*]] = load float, ptr [[ARRAYIDX25]], align 4, !llvm.access.group [[ACC_GRP11]]4399// CHECK6-NEXT: [[MUL26:%.*]] = fmul float [[MUL23]], [[TMP31]]4400// CHECK6-NEXT: [[TMP32:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP11]]4401// CHECK6-NEXT: [[TMP33:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP11]]4402// CHECK6-NEXT: [[IDXPROM27:%.*]] = sext i8 [[TMP33]] to i644403// CHECK6-NEXT: [[ARRAYIDX28:%.*]] = getelementptr inbounds float, ptr [[TMP32]], i64 [[IDXPROM27]]4404// CHECK6-NEXT: store float [[MUL26]], ptr [[ARRAYIDX28]], align 4, !llvm.access.group [[ACC_GRP11]]4405// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]4406// CHECK6: omp.body.continue:4407// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]4408// CHECK6: omp.inner.for.inc:4409// CHECK6-NEXT: [[TMP34:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11]]4410// CHECK6-NEXT: [[ADD29:%.*]] = add nsw i64 [[TMP34]], 14411// CHECK6-NEXT: store i64 [[ADD29]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11]]4412// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]4413// CHECK6: omp.inner.for.end:4414// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]]4415// CHECK6: omp.dispatch.inc:4416// CHECK6-NEXT: br label [[OMP_DISPATCH_COND]]4417// CHECK6: omp.dispatch.end:4418// CHECK6-NEXT: [[TMP35:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 84419// CHECK6-NEXT: [[TMP36:%.*]] = load i32, ptr [[TMP35]], align 44420// CHECK6-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB2]], i32 [[TMP36]])4421// CHECK6-NEXT: br label [[OMP_PRECOND_END]]4422// CHECK6: omp.precond.end:4423// CHECK6-NEXT: ret void4424//4425//4426// CHECK6-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_4427// CHECK6-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {4428// CHECK6-NEXT: entry:4429// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 84430// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 84431// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 84432// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 84433// CHECK6-NEXT: [[X:%.*]] = alloca i32, align 44434// CHECK6-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 84435// CHECK6-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 84436// CHECK6-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 84437// CHECK6-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 84438// CHECK6-NEXT: store i32 0, ptr [[X]], align 44439// CHECK6-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_Z7runtimePfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])4440// CHECK6-NEXT: ret void4441//4442//4443// CHECK6-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_.omp_outlined4444// CHECK6-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {4445// CHECK6-NEXT: entry:4446// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 84447// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 84448// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 84449// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 84450// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 84451// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 84452// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 44453// CHECK6-NEXT: [[TMP:%.*]] = alloca i8, align 14454// CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 44455// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 44456// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 44457// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 44458// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 44459// CHECK6-NEXT: [[I:%.*]] = alloca i8, align 14460// CHECK6-NEXT: [[X:%.*]] = alloca i32, align 44461// CHECK6-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 84462// CHECK6-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 84463// CHECK6-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 84464// CHECK6-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 84465// CHECK6-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 84466// CHECK6-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 84467// CHECK6-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 84468// CHECK6-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 84469// CHECK6-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 84470// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 84471// CHECK6-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 44472// CHECK6-NEXT: store i32 199, ptr [[DOTOMP_UB]], align 44473// CHECK6-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 44474// CHECK6-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 44475// CHECK6-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 84476// CHECK6-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 44477// CHECK6-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB2]], i32 [[TMP5]], i32 1073741861, i32 0, i32 199, i32 1, i32 1)4478// CHECK6-NEXT: br label [[OMP_DISPATCH_COND:%.*]]4479// CHECK6: omp.dispatch.cond:4480// CHECK6-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB2]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])4481// CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 04482// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]4483// CHECK6: omp.dispatch.body:4484// CHECK6-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 44485// CHECK6-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 44486// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]4487// CHECK6: omp.inner.for.cond:4488// CHECK6-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14:![0-9]+]]4489// CHECK6-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP14]]4490// CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]4491// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]4492// CHECK6: omp.inner.for.body:4493// CHECK6-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]4494// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 204495// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 14496// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]]4497// CHECK6-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i84498// CHECK6-NEXT: store i8 [[CONV]], ptr [[I]], align 1, !llvm.access.group [[ACC_GRP14]]4499// CHECK6-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]4500// CHECK6-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]4501// CHECK6-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP12]], 204502// CHECK6-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 204503// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL3]]4504// CHECK6-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 14505// CHECK6-NEXT: [[ADD5:%.*]] = add nsw i32 -10, [[MUL4]]4506// CHECK6-NEXT: store i32 [[ADD5]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP14]]4507// CHECK6-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP14]]4508// CHECK6-NEXT: [[TMP14:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP14]]4509// CHECK6-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP14]] to i644510// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP13]], i64 [[IDXPROM]]4511// CHECK6-NEXT: [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP14]]4512// CHECK6-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP14]]4513// CHECK6-NEXT: [[TMP17:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP14]]4514// CHECK6-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP17]] to i644515// CHECK6-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds nuw float, ptr [[TMP16]], i64 [[IDXPROM6]]4516// CHECK6-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP14]]4517// CHECK6-NEXT: [[MUL8:%.*]] = fmul float [[TMP15]], [[TMP18]]4518// CHECK6-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP14]]4519// CHECK6-NEXT: [[TMP20:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP14]]4520// CHECK6-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP20]] to i644521// CHECK6-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds nuw float, ptr [[TMP19]], i64 [[IDXPROM9]]4522// CHECK6-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP14]]4523// CHECK6-NEXT: [[MUL11:%.*]] = fmul float [[MUL8]], [[TMP21]]4524// CHECK6-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP14]]4525// CHECK6-NEXT: [[TMP23:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP14]]4526// CHECK6-NEXT: [[IDXPROM12:%.*]] = zext i8 [[TMP23]] to i644527// CHECK6-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds nuw float, ptr [[TMP22]], i64 [[IDXPROM12]]4528// CHECK6-NEXT: store float [[MUL11]], ptr [[ARRAYIDX13]], align 4, !llvm.access.group [[ACC_GRP14]]4529// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]4530// CHECK6: omp.body.continue:4531// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]4532// CHECK6: omp.inner.for.inc:4533// CHECK6-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]4534// CHECK6-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP24]], 14535// CHECK6-NEXT: store i32 [[ADD14]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]4536// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]4537// CHECK6: omp.inner.for.end:4538// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]]4539// CHECK6: omp.dispatch.inc:4540// CHECK6-NEXT: br label [[OMP_DISPATCH_COND]]4541// CHECK6: omp.dispatch.end:4542// CHECK6-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB2]], i32 [[TMP5]])4543// CHECK6-NEXT: ret void4544//4545//4546// CHECK6-LABEL: define {{[^@]+}}@_Z3foov4547// CHECK6-SAME: () #[[ATTR0]] {4548// CHECK6-NEXT: entry:4549// CHECK6-NEXT: call void @_Z8mayThrowv()4550// CHECK6-NEXT: ret i32 04551//4552//4553// CHECK6-LABEL: define {{[^@]+}}@_Z12parallel_forPfi4554// CHECK6-SAME: (ptr noundef [[A:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] {4555// CHECK6-NEXT: entry:4556// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 84557// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 44558// CHECK6-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 84559// CHECK6-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 84560// CHECK6-NEXT: [[N_CASTED:%.*]] = alloca i64, align 84561// CHECK6-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 84562// CHECK6-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 44563// CHECK6-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 44564// CHECK6-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i644565// CHECK6-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()4566// CHECK6-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 84567// CHECK6-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 164568// CHECK6-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 84569// CHECK6-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 44570// CHECK6-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 44571// CHECK6-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 84572// CHECK6-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @_Z12parallel_forPfi.omp_outlined, ptr [[A_ADDR]], i64 [[TMP1]], i64 [[TMP4]])4573// CHECK6-NEXT: [[TMP5:%.*]] = load ptr, ptr [[SAVED_STACK]], align 84574// CHECK6-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP5]])4575// CHECK6-NEXT: ret void4576//4577//4578// CHECK6-LABEL: define {{[^@]+}}@_Z12parallel_forPfi.omp_outlined4579// CHECK6-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[N:%.*]]) #[[ATTR1]] {4580// CHECK6-NEXT: entry:4581// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 84582// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 84583// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 84584// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 84585// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 84586// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 44587// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 44588// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 44589// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 44590// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 44591// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 44592// CHECK6-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 84593// CHECK6-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 84594// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 44595// CHECK6-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 84596// CHECK6-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 84597// CHECK6-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 84598// CHECK6-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 84599// CHECK6-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 84600// CHECK6-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 84601// CHECK6-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 84602// CHECK6-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 44603// CHECK6-NEXT: store i32 16908288, ptr [[DOTOMP_UB]], align 44604// CHECK6-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 44605// CHECK6-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 44606// CHECK6-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()4607// CHECK6-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 84608// CHECK6-NEXT: [[VLA1:%.*]] = alloca float, i64 [[TMP1]], align 164609// CHECK6-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 84610// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 84611// CHECK6-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 44612// CHECK6-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5)4613// CHECK6-NEXT: br label [[OMP_DISPATCH_COND:%.*]]4614// CHECK6: omp.dispatch.cond:4615// CHECK6-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44616// CHECK6-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP5]], 169082884617// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]4618// CHECK6: cond.true:4619// CHECK6-NEXT: br label [[COND_END:%.*]]4620// CHECK6: cond.false:4621// CHECK6-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44622// CHECK6-NEXT: br label [[COND_END]]4623// CHECK6: cond.end:4624// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]4625// CHECK6-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 44626// CHECK6-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 44627// CHECK6-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 44628// CHECK6-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44629// CHECK6-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44630// CHECK6-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP8]], [[TMP9]]4631// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_CLEANUP:%.*]]4632// CHECK6: omp.dispatch.cleanup:4633// CHECK6-NEXT: br label [[OMP_DISPATCH_END:%.*]]4634// CHECK6: omp.dispatch.body:4635// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]4636// CHECK6: omp.inner.for.cond:4637// CHECK6-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44638// CHECK6-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44639// CHECK6-NEXT: [[CMP3:%.*]] = icmp ule i32 [[TMP10]], [[TMP11]]4640// CHECK6-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]4641// CHECK6: omp.inner.for.cond.cleanup:4642// CHECK6-NEXT: br label [[OMP_INNER_FOR_END:%.*]]4643// CHECK6: omp.inner.for.body:4644// CHECK6-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44645// CHECK6-NEXT: [[MUL:%.*]] = mul i32 [[TMP12]], 1274646// CHECK6-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]4647// CHECK6-NEXT: store i32 [[ADD]], ptr [[I]], align 44648// CHECK6-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3foov()4649// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[CALL]] to float4650// CHECK6-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 44651// CHECK6-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP13]] to i644652// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[VLA1]], i64 [[IDXPROM]]4653// CHECK6-NEXT: [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 44654// CHECK6-NEXT: [[ADD4:%.*]] = fadd float [[CONV]], [[TMP14]]4655// CHECK6-NEXT: [[TMP15:%.*]] = load i32, ptr [[N_ADDR]], align 44656// CHECK6-NEXT: [[CONV5:%.*]] = sitofp i32 [[TMP15]] to float4657// CHECK6-NEXT: [[ADD6:%.*]] = fadd float [[ADD4]], [[CONV5]]4658// CHECK6-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP0]], align 84659// CHECK6-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 44660// CHECK6-NEXT: [[IDXPROM7:%.*]] = zext i32 [[TMP17]] to i644661// CHECK6-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds nuw float, ptr [[TMP16]], i64 [[IDXPROM7]]4662// CHECK6-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX8]], align 44663// CHECK6-NEXT: [[ADD9:%.*]] = fadd float [[TMP18]], [[ADD6]]4664// CHECK6-NEXT: store float [[ADD9]], ptr [[ARRAYIDX8]], align 44665// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]4666// CHECK6: omp.body.continue:4667// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]4668// CHECK6: omp.inner.for.inc:4669// CHECK6-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44670// CHECK6-NEXT: [[ADD10:%.*]] = add i32 [[TMP19]], 14671// CHECK6-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 44672// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]]4673// CHECK6: omp.inner.for.end:4674// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]]4675// CHECK6: omp.dispatch.inc:4676// CHECK6-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_LB]], align 44677// CHECK6-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 44678// CHECK6-NEXT: [[ADD11:%.*]] = add i32 [[TMP20]], [[TMP21]]4679// CHECK6-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_LB]], align 44680// CHECK6-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44681// CHECK6-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 44682// CHECK6-NEXT: [[ADD12:%.*]] = add i32 [[TMP22]], [[TMP23]]4683// CHECK6-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_UB]], align 44684// CHECK6-NEXT: br label [[OMP_DISPATCH_COND]]4685// CHECK6: omp.dispatch.end:4686// CHECK6-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP4]])4687// CHECK6-NEXT: [[TMP24:%.*]] = load ptr, ptr [[SAVED_STACK]], align 84688// CHECK6-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP24]])4689// CHECK6-NEXT: ret void4690//4691//4692// CHECK11-LABEL: define {{[^@]+}}@_Z9incrementv4693// CHECK11-SAME: () #[[ATTR0:[0-9]+]] {4694// CHECK11-NEXT: entry:4695// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 44696// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 44697// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 44698// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 44699// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 44700// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 44701// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 44702// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])4703// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 44704// CHECK11-NEXT: store i32 4, ptr [[DOTOMP_UB]], align 44705// CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 44706// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 44707// CHECK11-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)4708// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44709// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 44710// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]4711// CHECK11: cond.true:4712// CHECK11-NEXT: br label [[COND_END:%.*]]4713// CHECK11: cond.false:4714// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44715// CHECK11-NEXT: br label [[COND_END]]4716// CHECK11: cond.end:4717// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 4, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ]4718// CHECK11-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 44719// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 44720// CHECK11-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 44721// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]4722// CHECK11: omp.inner.for.cond:4723// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44724// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44725// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]4726// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]4727// CHECK11: omp.inner.for.body:4728// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44729// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 14730// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]4731// CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 44732// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]4733// CHECK11: omp.body.continue:4734// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]4735// CHECK11: omp.inner.for.inc:4736// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44737// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP7]], 14738// CHECK11-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 44739// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]4740// CHECK11: omp.inner.for.end:4741// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]4742// CHECK11: omp.loop.exit:4743// CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]])4744// CHECK11-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP0]])4745// CHECK11-NEXT: ret i32 04746//4747//4748// CHECK11-LABEL: define {{[^@]+}}@_Z16decrement_nowaitv4749// CHECK11-SAME: () #[[ATTR0]] {4750// CHECK11-NEXT: entry:4751// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 44752// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 44753// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 44754// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 44755// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 44756// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 44757// CHECK11-NEXT: [[J:%.*]] = alloca i32, align 44758// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])4759// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 44760// CHECK11-NEXT: store i32 4, ptr [[DOTOMP_UB]], align 44761// CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 44762// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 44763// CHECK11-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)4764// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44765// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 44766// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]4767// CHECK11: cond.true:4768// CHECK11-NEXT: br label [[COND_END:%.*]]4769// CHECK11: cond.false:4770// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44771// CHECK11-NEXT: br label [[COND_END]]4772// CHECK11: cond.end:4773// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 4, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ]4774// CHECK11-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 44775// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 44776// CHECK11-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 44777// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]4778// CHECK11: omp.inner.for.cond:4779// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44780// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44781// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]4782// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]4783// CHECK11: omp.inner.for.body:4784// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44785// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 14786// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 5, [[MUL]]4787// CHECK11-NEXT: store i32 [[SUB]], ptr [[J]], align 44788// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]4789// CHECK11: omp.body.continue:4790// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]4791// CHECK11: omp.inner.for.inc:4792// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44793// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], 14794// CHECK11-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 44795// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]4796// CHECK11: omp.inner.for.end:4797// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]4798// CHECK11: omp.loop.exit:4799// CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]])4800// CHECK11-NEXT: ret i32 04801//4802//4803// CHECK11-LABEL: define {{[^@]+}}@_Z16range_for_singlev4804// CHECK11-SAME: () #[[ATTR0]] {4805// CHECK11-NEXT: entry:4806// CHECK11-NEXT: [[ARR:%.*]] = alloca [10 x i32], align 164807// CHECK11-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[ARR]], i8 0, i64 40, i1 false)4808// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @_Z16range_for_singlev.omp_outlined, ptr [[ARR]])4809// CHECK11-NEXT: ret void4810//4811//4812// CHECK11-LABEL: define {{[^@]+}}@_Z16range_for_singlev.omp_outlined4813// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[ARR:%.*]]) #[[ATTR4:[0-9]+]] {4814// CHECK11-NEXT: entry:4815// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 84816// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 84817// CHECK11-NEXT: [[ARR_ADDR:%.*]] = alloca ptr, align 84818// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 84819// CHECK11-NEXT: [[TMP:%.*]] = alloca ptr, align 84820// CHECK11-NEXT: [[__RANGE1:%.*]] = alloca ptr, align 84821// CHECK11-NEXT: [[__END1:%.*]] = alloca ptr, align 84822// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca ptr, align 84823// CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca ptr, align 84824// CHECK11-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 84825// CHECK11-NEXT: [[__BEGIN1:%.*]] = alloca ptr, align 84826// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 84827// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 84828// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 84829// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 44830// CHECK11-NEXT: [[__BEGIN15:%.*]] = alloca ptr, align 84831// CHECK11-NEXT: [[A:%.*]] = alloca ptr, align 84832// CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 84833// CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 84834// CHECK11-NEXT: store ptr [[ARR]], ptr [[ARR_ADDR]], align 84835// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARR_ADDR]], align 84836// CHECK11-NEXT: store ptr [[TMP0]], ptr [[__RANGE1]], align 84837// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE1]], align 84838// CHECK11-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP1]], i64 0, i64 04839// CHECK11-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, ptr [[ARRAYDECAY]], i64 104840// CHECK11-NEXT: store ptr [[ADD_PTR]], ptr [[__END1]], align 84841// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE1]], align 84842// CHECK11-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP2]], i64 0, i64 04843// CHECK11-NEXT: store ptr [[ARRAYDECAY1]], ptr [[DOTCAPTURE_EXPR_]], align 84844// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[__END1]], align 84845// CHECK11-NEXT: store ptr [[TMP3]], ptr [[DOTCAPTURE_EXPR_2]], align 84846// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_2]], align 84847// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 84848// CHECK11-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint ptr [[TMP4]] to i644849// CHECK11-NEXT: [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint ptr [[TMP5]] to i644850// CHECK11-NEXT: [[SUB_PTR_SUB:%.*]] = sub i64 [[SUB_PTR_LHS_CAST]], [[SUB_PTR_RHS_CAST]]4851// CHECK11-NEXT: [[SUB_PTR_DIV:%.*]] = sdiv exact i64 [[SUB_PTR_SUB]], 44852// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i64 [[SUB_PTR_DIV]], 14853// CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 [[SUB]], 14854// CHECK11-NEXT: [[DIV:%.*]] = sdiv i64 [[ADD]], 14855// CHECK11-NEXT: [[SUB4:%.*]] = sub nsw i64 [[DIV]], 14856// CHECK11-NEXT: store i64 [[SUB4]], ptr [[DOTCAPTURE_EXPR_3]], align 84857// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 84858// CHECK11-NEXT: store ptr [[TMP6]], ptr [[__BEGIN1]], align 84859// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 84860// CHECK11-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_2]], align 84861// CHECK11-NEXT: [[CMP:%.*]] = icmp ult ptr [[TMP7]], [[TMP8]]4862// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]4863// CHECK11: omp.precond.then:4864// CHECK11-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 84865// CHECK11-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 84866// CHECK11-NEXT: store i64 [[TMP9]], ptr [[DOTOMP_UB]], align 84867// CHECK11-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 84868// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 44869// CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 84870// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 44871// CHECK11-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP11]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)4872// CHECK11-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_UB]], align 84873// CHECK11-NEXT: [[TMP13:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 84874// CHECK11-NEXT: [[CMP6:%.*]] = icmp sgt i64 [[TMP12]], [[TMP13]]4875// CHECK11-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]4876// CHECK11: cond.true:4877// CHECK11-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 84878// CHECK11-NEXT: br label [[COND_END:%.*]]4879// CHECK11: cond.false:4880// CHECK11-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_UB]], align 84881// CHECK11-NEXT: br label [[COND_END]]4882// CHECK11: cond.end:4883// CHECK11-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ]4884// CHECK11-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 84885// CHECK11-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_LB]], align 84886// CHECK11-NEXT: store i64 [[TMP16]], ptr [[DOTOMP_IV]], align 84887// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]4888// CHECK11: omp.inner.for.cond:4889// CHECK11-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 84890// CHECK11-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTOMP_UB]], align 84891// CHECK11-NEXT: [[CMP7:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]]4892// CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]4893// CHECK11: omp.inner.for.body:4894// CHECK11-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 84895// CHECK11-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_IV]], align 84896// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP20]], 14897// CHECK11-NEXT: [[ADD_PTR8:%.*]] = getelementptr inbounds i32, ptr [[TMP19]], i64 [[MUL]]4898// CHECK11-NEXT: store ptr [[ADD_PTR8]], ptr [[__BEGIN15]], align 84899// CHECK11-NEXT: [[TMP21:%.*]] = load ptr, ptr [[__BEGIN15]], align 84900// CHECK11-NEXT: store ptr [[TMP21]], ptr [[A]], align 84901// CHECK11-NEXT: [[TMP22:%.*]] = load ptr, ptr [[A]], align 84902// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]4903// CHECK11: omp.body.continue:4904// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]4905// CHECK11: omp.inner.for.inc:4906// CHECK11-NEXT: [[TMP23:%.*]] = load i64, ptr [[DOTOMP_IV]], align 84907// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i64 [[TMP23]], 14908// CHECK11-NEXT: store i64 [[ADD9]], ptr [[DOTOMP_IV]], align 84909// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]4910// CHECK11: omp.inner.for.end:4911// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]4912// CHECK11: omp.loop.exit:4913// CHECK11-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 84914// CHECK11-NEXT: [[TMP25:%.*]] = load i32, ptr [[TMP24]], align 44915// CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP25]])4916// CHECK11-NEXT: br label [[OMP_PRECOND_END]]4917// CHECK11: omp.precond.end:4918// CHECK11-NEXT: ret void4919//4920//4921// CHECK11-LABEL: define {{[^@]+}}@_Z19range_for_collapsedv4922// CHECK11-SAME: () #[[ATTR0]] {4923// CHECK11-NEXT: entry:4924// CHECK11-NEXT: [[ARR:%.*]] = alloca [10 x i32], align 164925// CHECK11-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[ARR]], i8 0, i64 40, i1 false)4926// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @_Z19range_for_collapsedv.omp_outlined, ptr [[ARR]])4927// CHECK11-NEXT: ret void4928//4929//4930// CHECK11-LABEL: define {{[^@]+}}@_Z19range_for_collapsedv.omp_outlined4931// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[ARR:%.*]]) #[[ATTR4]] {4932// CHECK11-NEXT: entry:4933// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 84934// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 84935// CHECK11-NEXT: [[ARR_ADDR:%.*]] = alloca ptr, align 84936// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 84937// CHECK11-NEXT: [[TMP:%.*]] = alloca ptr, align 84938// CHECK11-NEXT: [[_TMP1:%.*]] = alloca ptr, align 84939// CHECK11-NEXT: [[__RANGE1:%.*]] = alloca ptr, align 84940// CHECK11-NEXT: [[__END1:%.*]] = alloca ptr, align 84941// CHECK11-NEXT: [[__RANGE2:%.*]] = alloca ptr, align 84942// CHECK11-NEXT: [[__END2:%.*]] = alloca ptr, align 84943// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca ptr, align 84944// CHECK11-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca ptr, align 84945// CHECK11-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca ptr, align 84946// CHECK11-NEXT: [[DOTCAPTURE_EXPR_8:%.*]] = alloca ptr, align 84947// CHECK11-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i64, align 84948// CHECK11-NEXT: [[__BEGIN1:%.*]] = alloca ptr, align 84949// CHECK11-NEXT: [[__BEGIN2:%.*]] = alloca ptr, align 84950// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 84951// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 84952// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 84953// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 44954// CHECK11-NEXT: [[__BEGIN119:%.*]] = alloca ptr, align 84955// CHECK11-NEXT: [[__BEGIN220:%.*]] = alloca ptr, align 84956// CHECK11-NEXT: [[A:%.*]] = alloca ptr, align 84957// CHECK11-NEXT: [[B:%.*]] = alloca i32, align 44958// CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 84959// CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 84960// CHECK11-NEXT: store ptr [[ARR]], ptr [[ARR_ADDR]], align 84961// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARR_ADDR]], align 84962// CHECK11-NEXT: store ptr [[TMP0]], ptr [[__RANGE1]], align 84963// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE1]], align 84964// CHECK11-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP1]], i64 0, i64 04965// CHECK11-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, ptr [[ARRAYDECAY]], i64 104966// CHECK11-NEXT: store ptr [[ADD_PTR]], ptr [[__END1]], align 84967// CHECK11-NEXT: store ptr [[TMP0]], ptr [[__RANGE2]], align 84968// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE2]], align 84969// CHECK11-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP2]], i64 0, i64 04970// CHECK11-NEXT: [[ADD_PTR3:%.*]] = getelementptr inbounds i32, ptr [[ARRAYDECAY2]], i64 104971// CHECK11-NEXT: store ptr [[ADD_PTR3]], ptr [[__END2]], align 84972// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[__RANGE1]], align 84973// CHECK11-NEXT: [[ARRAYDECAY4:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP3]], i64 0, i64 04974// CHECK11-NEXT: store ptr [[ARRAYDECAY4]], ptr [[DOTCAPTURE_EXPR_]], align 84975// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[__END1]], align 84976// CHECK11-NEXT: store ptr [[TMP4]], ptr [[DOTCAPTURE_EXPR_5]], align 84977// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[__RANGE2]], align 84978// CHECK11-NEXT: [[ARRAYDECAY7:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP5]], i64 0, i64 04979// CHECK11-NEXT: store ptr [[ARRAYDECAY7]], ptr [[DOTCAPTURE_EXPR_6]], align 84980// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[__END2]], align 84981// CHECK11-NEXT: store ptr [[TMP6]], ptr [[DOTCAPTURE_EXPR_8]], align 84982// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_5]], align 84983// CHECK11-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 84984// CHECK11-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint ptr [[TMP7]] to i644985// CHECK11-NEXT: [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint ptr [[TMP8]] to i644986// CHECK11-NEXT: [[SUB_PTR_SUB:%.*]] = sub i64 [[SUB_PTR_LHS_CAST]], [[SUB_PTR_RHS_CAST]]4987// CHECK11-NEXT: [[SUB_PTR_DIV:%.*]] = sdiv exact i64 [[SUB_PTR_SUB]], 44988// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i64 [[SUB_PTR_DIV]], 14989// CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 [[SUB]], 14990// CHECK11-NEXT: [[DIV:%.*]] = sdiv i64 [[ADD]], 14991// CHECK11-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_8]], align 84992// CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_6]], align 84993// CHECK11-NEXT: [[SUB_PTR_LHS_CAST10:%.*]] = ptrtoint ptr [[TMP9]] to i644994// CHECK11-NEXT: [[SUB_PTR_RHS_CAST11:%.*]] = ptrtoint ptr [[TMP10]] to i644995// CHECK11-NEXT: [[SUB_PTR_SUB12:%.*]] = sub i64 [[SUB_PTR_LHS_CAST10]], [[SUB_PTR_RHS_CAST11]]4996// CHECK11-NEXT: [[SUB_PTR_DIV13:%.*]] = sdiv exact i64 [[SUB_PTR_SUB12]], 44997// CHECK11-NEXT: [[SUB14:%.*]] = sub nsw i64 [[SUB_PTR_DIV13]], 14998// CHECK11-NEXT: [[ADD15:%.*]] = add nsw i64 [[SUB14]], 14999// CHECK11-NEXT: [[DIV16:%.*]] = sdiv i64 [[ADD15]], 15000// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[DIV]], [[DIV16]]5001// CHECK11-NEXT: [[SUB17:%.*]] = sub nsw i64 [[MUL]], 15002// CHECK11-NEXT: store i64 [[SUB17]], ptr [[DOTCAPTURE_EXPR_9]], align 85003// CHECK11-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 85004// CHECK11-NEXT: store ptr [[TMP11]], ptr [[__BEGIN1]], align 85005// CHECK11-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_6]], align 85006// CHECK11-NEXT: store ptr [[TMP12]], ptr [[__BEGIN2]], align 85007// CHECK11-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 85008// CHECK11-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_5]], align 85009// CHECK11-NEXT: [[CMP:%.*]] = icmp ult ptr [[TMP13]], [[TMP14]]5010// CHECK11-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]5011// CHECK11: land.lhs.true:5012// CHECK11-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_6]], align 85013// CHECK11-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_8]], align 85014// CHECK11-NEXT: [[CMP18:%.*]] = icmp ult ptr [[TMP15]], [[TMP16]]5015// CHECK11-NEXT: br i1 [[CMP18]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]5016// CHECK11: omp.precond.then:5017// CHECK11-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 85018// CHECK11-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_9]], align 85019// CHECK11-NEXT: store i64 [[TMP17]], ptr [[DOTOMP_UB]], align 85020// CHECK11-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 85021// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 45022// CHECK11-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 85023// CHECK11-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 45024// CHECK11-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP19]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)5025// CHECK11-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_UB]], align 85026// CHECK11-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_9]], align 85027// CHECK11-NEXT: [[CMP21:%.*]] = icmp sgt i64 [[TMP20]], [[TMP21]]5028// CHECK11-NEXT: br i1 [[CMP21]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]5029// CHECK11: cond.true:5030// CHECK11-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_9]], align 85031// CHECK11-NEXT: br label [[COND_END:%.*]]5032// CHECK11: cond.false:5033// CHECK11-NEXT: [[TMP23:%.*]] = load i64, ptr [[DOTOMP_UB]], align 85034// CHECK11-NEXT: br label [[COND_END]]5035// CHECK11: cond.end:5036// CHECK11-NEXT: [[COND:%.*]] = phi i64 [ [[TMP22]], [[COND_TRUE]] ], [ [[TMP23]], [[COND_FALSE]] ]5037// CHECK11-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 85038// CHECK11-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_LB]], align 85039// CHECK11-NEXT: store i64 [[TMP24]], ptr [[DOTOMP_IV]], align 85040// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]5041// CHECK11: omp.inner.for.cond:5042// CHECK11-NEXT: [[TMP25:%.*]] = load i64, ptr [[DOTOMP_IV]], align 85043// CHECK11-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTOMP_UB]], align 85044// CHECK11-NEXT: [[CMP22:%.*]] = icmp sle i64 [[TMP25]], [[TMP26]]5045// CHECK11-NEXT: br i1 [[CMP22]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]5046// CHECK11: omp.inner.for.body:5047// CHECK11-NEXT: [[TMP27:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 85048// CHECK11-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTOMP_IV]], align 85049// CHECK11-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_8]], align 85050// CHECK11-NEXT: [[TMP30:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_6]], align 85051// CHECK11-NEXT: [[SUB_PTR_LHS_CAST23:%.*]] = ptrtoint ptr [[TMP29]] to i645052// CHECK11-NEXT: [[SUB_PTR_RHS_CAST24:%.*]] = ptrtoint ptr [[TMP30]] to i645053// CHECK11-NEXT: [[SUB_PTR_SUB25:%.*]] = sub i64 [[SUB_PTR_LHS_CAST23]], [[SUB_PTR_RHS_CAST24]]5054// CHECK11-NEXT: [[SUB_PTR_DIV26:%.*]] = sdiv exact i64 [[SUB_PTR_SUB25]], 45055// CHECK11-NEXT: [[SUB27:%.*]] = sub nsw i64 [[SUB_PTR_DIV26]], 15056// CHECK11-NEXT: [[ADD28:%.*]] = add nsw i64 [[SUB27]], 15057// CHECK11-NEXT: [[DIV29:%.*]] = sdiv i64 [[ADD28]], 15058// CHECK11-NEXT: [[MUL30:%.*]] = mul nsw i64 1, [[DIV29]]5059// CHECK11-NEXT: [[DIV31:%.*]] = sdiv i64 [[TMP28]], [[MUL30]]5060// CHECK11-NEXT: [[MUL32:%.*]] = mul nsw i64 [[DIV31]], 15061// CHECK11-NEXT: [[ADD_PTR33:%.*]] = getelementptr inbounds i32, ptr [[TMP27]], i64 [[MUL32]]5062// CHECK11-NEXT: store ptr [[ADD_PTR33]], ptr [[__BEGIN119]], align 85063// CHECK11-NEXT: [[TMP31:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_6]], align 85064// CHECK11-NEXT: [[TMP32:%.*]] = load i64, ptr [[DOTOMP_IV]], align 85065// CHECK11-NEXT: [[TMP33:%.*]] = load i64, ptr [[DOTOMP_IV]], align 85066// CHECK11-NEXT: [[TMP34:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_8]], align 85067// CHECK11-NEXT: [[TMP35:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_6]], align 85068// CHECK11-NEXT: [[SUB_PTR_LHS_CAST34:%.*]] = ptrtoint ptr [[TMP34]] to i645069// CHECK11-NEXT: [[SUB_PTR_RHS_CAST35:%.*]] = ptrtoint ptr [[TMP35]] to i645070// CHECK11-NEXT: [[SUB_PTR_SUB36:%.*]] = sub i64 [[SUB_PTR_LHS_CAST34]], [[SUB_PTR_RHS_CAST35]]5071// CHECK11-NEXT: [[SUB_PTR_DIV37:%.*]] = sdiv exact i64 [[SUB_PTR_SUB36]], 45072// CHECK11-NEXT: [[SUB38:%.*]] = sub nsw i64 [[SUB_PTR_DIV37]], 15073// CHECK11-NEXT: [[ADD39:%.*]] = add nsw i64 [[SUB38]], 15074// CHECK11-NEXT: [[DIV40:%.*]] = sdiv i64 [[ADD39]], 15075// CHECK11-NEXT: [[MUL41:%.*]] = mul nsw i64 1, [[DIV40]]5076// CHECK11-NEXT: [[DIV42:%.*]] = sdiv i64 [[TMP33]], [[MUL41]]5077// CHECK11-NEXT: [[TMP36:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_8]], align 85078// CHECK11-NEXT: [[TMP37:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_6]], align 85079// CHECK11-NEXT: [[SUB_PTR_LHS_CAST43:%.*]] = ptrtoint ptr [[TMP36]] to i645080// CHECK11-NEXT: [[SUB_PTR_RHS_CAST44:%.*]] = ptrtoint ptr [[TMP37]] to i645081// CHECK11-NEXT: [[SUB_PTR_SUB45:%.*]] = sub i64 [[SUB_PTR_LHS_CAST43]], [[SUB_PTR_RHS_CAST44]]5082// CHECK11-NEXT: [[SUB_PTR_DIV46:%.*]] = sdiv exact i64 [[SUB_PTR_SUB45]], 45083// CHECK11-NEXT: [[SUB47:%.*]] = sub nsw i64 [[SUB_PTR_DIV46]], 15084// CHECK11-NEXT: [[ADD48:%.*]] = add nsw i64 [[SUB47]], 15085// CHECK11-NEXT: [[DIV49:%.*]] = sdiv i64 [[ADD48]], 15086// CHECK11-NEXT: [[MUL50:%.*]] = mul nsw i64 1, [[DIV49]]5087// CHECK11-NEXT: [[MUL51:%.*]] = mul nsw i64 [[DIV42]], [[MUL50]]5088// CHECK11-NEXT: [[SUB52:%.*]] = sub nsw i64 [[TMP32]], [[MUL51]]5089// CHECK11-NEXT: [[MUL53:%.*]] = mul nsw i64 [[SUB52]], 15090// CHECK11-NEXT: [[ADD_PTR54:%.*]] = getelementptr inbounds i32, ptr [[TMP31]], i64 [[MUL53]]5091// CHECK11-NEXT: store ptr [[ADD_PTR54]], ptr [[__BEGIN220]], align 85092// CHECK11-NEXT: [[TMP38:%.*]] = load ptr, ptr [[__BEGIN119]], align 85093// CHECK11-NEXT: store ptr [[TMP38]], ptr [[A]], align 85094// CHECK11-NEXT: [[TMP39:%.*]] = load ptr, ptr [[__BEGIN220]], align 85095// CHECK11-NEXT: [[TMP40:%.*]] = load i32, ptr [[TMP39]], align 45096// CHECK11-NEXT: store i32 [[TMP40]], ptr [[B]], align 45097// CHECK11-NEXT: [[TMP41:%.*]] = load i32, ptr [[B]], align 45098// CHECK11-NEXT: [[TMP42:%.*]] = load ptr, ptr [[A]], align 85099// CHECK11-NEXT: store i32 [[TMP41]], ptr [[TMP42]], align 45100// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]5101// CHECK11: omp.body.continue:5102// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]5103// CHECK11: omp.inner.for.inc:5104// CHECK11-NEXT: [[TMP43:%.*]] = load i64, ptr [[DOTOMP_IV]], align 85105// CHECK11-NEXT: [[ADD55:%.*]] = add nsw i64 [[TMP43]], 15106// CHECK11-NEXT: store i64 [[ADD55]], ptr [[DOTOMP_IV]], align 85107// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]5108// CHECK11: omp.inner.for.end:5109// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]5110// CHECK11: omp.loop.exit:5111// CHECK11-NEXT: [[TMP44:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 85112// CHECK11-NEXT: [[TMP45:%.*]] = load i32, ptr [[TMP44]], align 45113// CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP45]])5114// CHECK11-NEXT: br label [[OMP_PRECOND_END]]5115// CHECK11: omp.precond.end:5116// CHECK11-NEXT: ret void5117//5118