553 lines · cpp
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _2// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s4// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK36// RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK47 8// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"9// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s10// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"11// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"12// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"13// expected-no-diagnostics14#ifndef HEADER15#define HEADER16 17template <class T>18struct S {19 T f;20 S(T a) : f(a) {}21 S() : f() {}22 S<T> &operator=(const S<T> &);23 operator T() { return T(); }24 ~S() {}25};26 27volatile int g = 1212;28float f;29char cnt;30 31template <typename T>32T tmain() {33 S<T> test;34 T *pvar = &test.f;35 T lvar = T();36#pragma omp parallel for linear(pvar, lvar)37 for (int i = 0; i < 2; ++i) {38 ++pvar, ++lvar;39 }40 return T();41}42 43int main() {44#ifdef LAMBDA45 [&]() {46#pragma omp parallel for linear(g:5)47 for (int i = 0; i < 2; ++i) {48 g += 5;49 [&]() {50 g = 2;51 }();52 }53 }();54 return 0;55#elif defined(BLOCKS)56 ^{57#pragma omp parallel for linear(g:5)58 for (int i = 0; i < 2; ++i) {59 g += 5;60 g = 1;61 ^{62 g = 2;63 }();64 }65 }();66 return 0;67#else68 S<float> test;69 float *pvar = &test.f;70 long long lvar = 0;71#pragma omp parallel for linear(pvar, lvar : 3)72 for (int i = 0; i < 2; ++i) {73 pvar += 3, lvar += 3;74 }75 return tmain<int>();76#endif77}78 79 80 81 82// Check for default initialization.83 84 85 86// Check for default initialization.87#endif88 89// CHECK1-LABEL: define {{[^@]+}}@main90// CHECK1-SAME: () #[[ATTR0:[0-9]+]] {91// CHECK1-NEXT: entry:92// CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 493// CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 494// CHECK1-NEXT: [[PVAR:%.*]] = alloca ptr, align 895// CHECK1-NEXT: [[LVAR:%.*]] = alloca i64, align 896// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 497// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])98// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TEST]], i32 0, i32 099// CHECK1-NEXT: store ptr [[F]], ptr [[PVAR]], align 8100// CHECK1-NEXT: store i64 0, ptr [[LVAR]], align 8101// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3:[0-9]+]], i32 2, ptr @main.omp_outlined, ptr [[PVAR]], ptr [[LVAR]])102// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()103// CHECK1-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4104// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4:[0-9]+]]105// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[RETVAL]], align 4106// CHECK1-NEXT: ret i32 [[TMP0]]107//108//109// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev110// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 {111// CHECK1-NEXT: entry:112// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8113// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8114// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8115// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])116// CHECK1-NEXT: ret void117//118//119// CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined120// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[PVAR:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[LVAR:%.*]]) #[[ATTR2:[0-9]+]] {121// CHECK1-NEXT: entry:122// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8123// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8124// CHECK1-NEXT: [[PVAR_ADDR:%.*]] = alloca ptr, align 8125// CHECK1-NEXT: [[LVAR_ADDR:%.*]] = alloca ptr, align 8126// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4127// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4128// CHECK1-NEXT: [[DOTLINEAR_START:%.*]] = alloca ptr, align 8129// CHECK1-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i64, align 8130// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4131// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4132// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4133// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4134// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4135// CHECK1-NEXT: [[PVAR2:%.*]] = alloca ptr, align 8136// CHECK1-NEXT: [[LVAR3:%.*]] = alloca i64, align 8137// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8138// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8139// CHECK1-NEXT: store ptr [[PVAR]], ptr [[PVAR_ADDR]], align 8140// CHECK1-NEXT: store ptr [[LVAR]], ptr [[LVAR_ADDR]], align 8141// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PVAR_ADDR]], align 8142// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[LVAR_ADDR]], align 8143// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP0]], align 8144// CHECK1-NEXT: store ptr [[TMP2]], ptr [[DOTLINEAR_START]], align 8145// CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP1]], align 8146// CHECK1-NEXT: store i64 [[TMP3]], ptr [[DOTLINEAR_START1]], align 8147// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4148// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4149// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4150// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4151// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8152// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4153// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]])154// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)155// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4156// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1157// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]158// CHECK1: cond.true:159// CHECK1-NEXT: br label [[COND_END:%.*]]160// CHECK1: cond.false:161// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4162// CHECK1-NEXT: br label [[COND_END]]163// CHECK1: cond.end:164// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]165// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4166// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4167// CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4168// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]169// CHECK1: omp.inner.for.cond:170// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4171// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4172// CHECK1-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]173// CHECK1-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]174// CHECK1: omp.inner.for.body:175// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4176// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1177// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]178// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4179// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTLINEAR_START]], align 8180// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4181// CHECK1-NEXT: [[MUL5:%.*]] = mul nsw i32 [[TMP13]], 3182// CHECK1-NEXT: [[IDX_EXT:%.*]] = sext i32 [[MUL5]] to i64183// CHECK1-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[IDX_EXT]]184// CHECK1-NEXT: store ptr [[ADD_PTR]], ptr [[PVAR2]], align 8185// CHECK1-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTLINEAR_START1]], align 8186// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4187// CHECK1-NEXT: [[MUL6:%.*]] = mul nsw i32 [[TMP15]], 3188// CHECK1-NEXT: [[CONV:%.*]] = sext i32 [[MUL6]] to i64189// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP14]], [[CONV]]190// CHECK1-NEXT: store i64 [[ADD7]], ptr [[LVAR3]], align 8191// CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[PVAR2]], align 8192// CHECK1-NEXT: [[ADD_PTR8:%.*]] = getelementptr inbounds float, ptr [[TMP16]], i64 3193// CHECK1-NEXT: store ptr [[ADD_PTR8]], ptr [[PVAR2]], align 8194// CHECK1-NEXT: [[TMP17:%.*]] = load i64, ptr [[LVAR3]], align 8195// CHECK1-NEXT: [[ADD9:%.*]] = add nsw i64 [[TMP17]], 3196// CHECK1-NEXT: store i64 [[ADD9]], ptr [[LVAR3]], align 8197// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]198// CHECK1: omp.body.continue:199// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]200// CHECK1: omp.inner.for.inc:201// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4202// CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP18]], 1203// CHECK1-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4204// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]205// CHECK1: omp.inner.for.end:206// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]207// CHECK1: omp.loop.exit:208// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP5]])209// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4210// CHECK1-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0211// CHECK1-NEXT: br i1 [[TMP20]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]212// CHECK1: .omp.linear.pu:213// CHECK1-NEXT: [[TMP21:%.*]] = load ptr, ptr [[PVAR2]], align 8214// CHECK1-NEXT: store ptr [[TMP21]], ptr [[TMP0]], align 8215// CHECK1-NEXT: [[TMP22:%.*]] = load i64, ptr [[LVAR3]], align 8216// CHECK1-NEXT: store i64 [[TMP22]], ptr [[TMP1]], align 8217// CHECK1-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]218// CHECK1: .omp.linear.pu.done:219// CHECK1-NEXT: ret void220//221//222// CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v223// CHECK1-SAME: () #[[ATTR1]] {224// CHECK1-NEXT: entry:225// CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4226// CHECK1-NEXT: [[PVAR:%.*]] = alloca ptr, align 8227// CHECK1-NEXT: [[LVAR:%.*]] = alloca i32, align 4228// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])229// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TEST]], i32 0, i32 0230// CHECK1-NEXT: store ptr [[F]], ptr [[PVAR]], align 8231// CHECK1-NEXT: store i32 0, ptr [[LVAR]], align 4232// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @_Z5tmainIiET_v.omp_outlined, ptr [[PVAR]], ptr [[LVAR]])233// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]234// CHECK1-NEXT: ret i32 0235//236//237// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev238// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {239// CHECK1-NEXT: entry:240// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8241// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8242// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8243// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]244// CHECK1-NEXT: ret void245//246//247// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev248// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {249// CHECK1-NEXT: entry:250// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8251// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8252// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8253// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0254// CHECK1-NEXT: store float 0.000000e+00, ptr [[F]], align 4255// CHECK1-NEXT: ret void256//257//258// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev259// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {260// CHECK1-NEXT: entry:261// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8262// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8263// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8264// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])265// CHECK1-NEXT: ret void266//267//268// CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v.omp_outlined269// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[PVAR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[LVAR:%.*]]) #[[ATTR2]] {270// CHECK1-NEXT: entry:271// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8272// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8273// CHECK1-NEXT: [[PVAR_ADDR:%.*]] = alloca ptr, align 8274// CHECK1-NEXT: [[LVAR_ADDR:%.*]] = alloca ptr, align 8275// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4276// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4277// CHECK1-NEXT: [[DOTLINEAR_START:%.*]] = alloca ptr, align 8278// CHECK1-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4279// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4280// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4281// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4282// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4283// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4284// CHECK1-NEXT: [[PVAR2:%.*]] = alloca ptr, align 8285// CHECK1-NEXT: [[LVAR3:%.*]] = alloca i32, align 4286// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8287// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8288// CHECK1-NEXT: store ptr [[PVAR]], ptr [[PVAR_ADDR]], align 8289// CHECK1-NEXT: store ptr [[LVAR]], ptr [[LVAR_ADDR]], align 8290// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PVAR_ADDR]], align 8291// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[LVAR_ADDR]], align 8292// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP0]], align 8293// CHECK1-NEXT: store ptr [[TMP2]], ptr [[DOTLINEAR_START]], align 8294// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP1]], align 4295// CHECK1-NEXT: store i32 [[TMP3]], ptr [[DOTLINEAR_START1]], align 4296// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4297// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4298// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4299// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4300// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8301// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4302// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB1]], i32 [[TMP5]])303// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)304// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4305// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1306// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]307// CHECK1: cond.true:308// CHECK1-NEXT: br label [[COND_END:%.*]]309// CHECK1: cond.false:310// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4311// CHECK1-NEXT: br label [[COND_END]]312// CHECK1: cond.end:313// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]314// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4315// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4316// CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4317// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]318// CHECK1: omp.inner.for.cond:319// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4320// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4321// CHECK1-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]322// CHECK1-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]323// CHECK1: omp.inner.for.body:324// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4325// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1326// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]327// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4328// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTLINEAR_START]], align 8329// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4330// CHECK1-NEXT: [[MUL5:%.*]] = mul nsw i32 [[TMP13]], 1331// CHECK1-NEXT: [[IDX_EXT:%.*]] = sext i32 [[MUL5]] to i64332// CHECK1-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, ptr [[TMP12]], i64 [[IDX_EXT]]333// CHECK1-NEXT: store ptr [[ADD_PTR]], ptr [[PVAR2]], align 8334// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4335// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4336// CHECK1-NEXT: [[MUL6:%.*]] = mul nsw i32 [[TMP15]], 1337// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP14]], [[MUL6]]338// CHECK1-NEXT: store i32 [[ADD7]], ptr [[LVAR3]], align 4339// CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[PVAR2]], align 8340// CHECK1-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP16]], i32 1341// CHECK1-NEXT: store ptr [[INCDEC_PTR]], ptr [[PVAR2]], align 8342// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[LVAR3]], align 4343// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP17]], 1344// CHECK1-NEXT: store i32 [[INC]], ptr [[LVAR3]], align 4345// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]346// CHECK1: omp.body.continue:347// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]348// CHECK1: omp.inner.for.inc:349// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4350// CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP18]], 1351// CHECK1-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4352// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]353// CHECK1: omp.inner.for.end:354// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]355// CHECK1: omp.loop.exit:356// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP5]])357// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4358// CHECK1-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0359// CHECK1-NEXT: br i1 [[TMP20]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]360// CHECK1: .omp.linear.pu:361// CHECK1-NEXT: [[TMP21:%.*]] = load ptr, ptr [[PVAR2]], align 8362// CHECK1-NEXT: store ptr [[TMP21]], ptr [[TMP0]], align 8363// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[LVAR3]], align 4364// CHECK1-NEXT: store i32 [[TMP22]], ptr [[TMP1]], align 4365// CHECK1-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]366// CHECK1: .omp.linear.pu.done:367// CHECK1-NEXT: ret void368//369//370// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev371// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {372// CHECK1-NEXT: entry:373// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8374// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8375// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8376// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]377// CHECK1-NEXT: ret void378//379//380// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev381// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {382// CHECK1-NEXT: entry:383// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8384// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8385// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8386// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0387// CHECK1-NEXT: store i32 0, ptr [[F]], align 4388// CHECK1-NEXT: ret void389//390//391// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev392// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {393// CHECK1-NEXT: entry:394// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8395// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8396// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8397// CHECK1-NEXT: ret void398//399//400// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev401// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {402// CHECK1-NEXT: entry:403// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8404// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8405// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8406// CHECK1-NEXT: ret void407//408//409// CHECK3-LABEL: define {{[^@]+}}@main410// CHECK3-SAME: () #[[ATTR0:[0-9]+]] {411// CHECK3-NEXT: entry:412// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4413// CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1414// CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4415// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])416// CHECK3-NEXT: ret i32 0417//418//419// CHECK4-LABEL: define {{[^@]+}}@main420// CHECK4-SAME: () #[[ATTR1:[0-9]+]] {421// CHECK4-NEXT: entry:422// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4423// CHECK4-NEXT: store i32 0, ptr [[RETVAL]], align 4424// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr getelementptr inbounds nuw ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr @__block_literal_global, i32 0, i32 3), align 8425// CHECK4-NEXT: call void [[TMP0]](ptr noundef @__block_literal_global)426// CHECK4-NEXT: ret i32 0427//428//429// CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke430// CHECK4-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] {431// CHECK4-NEXT: entry:432// CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8433// CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8434// CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8435// CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8436// CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3:[0-9]+]], i32 1, ptr @__main_block_invoke.omp_outlined, ptr @g)437// CHECK4-NEXT: ret void438//439//440// CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke.omp_outlined441// CHECK4-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[G:%.*]]) #[[ATTR3:[0-9]+]] {442// CHECK4-NEXT: entry:443// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8444// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8445// CHECK4-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 8446// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4447// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4448// CHECK4-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4449// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4450// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4451// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4452// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4453// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4454// CHECK4-NEXT: [[G1:%.*]] = alloca i32, align 4455// CHECK4-NEXT: [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, i32 }>, align 8456// CHECK4-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8457// CHECK4-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8458// CHECK4-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 8459// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 8460// CHECK4-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4461// CHECK4-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START]], align 4462// CHECK4-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4463// CHECK4-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4464// CHECK4-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4465// CHECK4-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4466// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8467// CHECK4-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4468// CHECK4-NEXT: call void @__kmpc_barrier(ptr @[[GLOB1:[0-9]+]], i32 [[TMP3]])469// CHECK4-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)470// CHECK4-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4471// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1472// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]473// CHECK4: cond.true:474// CHECK4-NEXT: br label [[COND_END:%.*]]475// CHECK4: cond.false:476// CHECK4-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4477// CHECK4-NEXT: br label [[COND_END]]478// CHECK4: cond.end:479// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]480// CHECK4-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4481// CHECK4-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4482// CHECK4-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4483// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]484// CHECK4: omp.inner.for.cond:485// CHECK4-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4486// CHECK4-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4487// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]488// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]489// CHECK4: omp.inner.for.body:490// CHECK4-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4491// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1492// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]493// CHECK4-NEXT: store i32 [[ADD]], ptr [[I]], align 4494// CHECK4-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4495// CHECK4-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4496// CHECK4-NEXT: [[MUL3:%.*]] = mul nsw i32 [[TMP11]], 5497// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], [[MUL3]]498// CHECK4-NEXT: store i32 [[ADD4]], ptr [[G1]], align 4499// CHECK4-NEXT: [[TMP12:%.*]] = load i32, ptr [[G1]], align 4500// CHECK4-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP12]], 5501// CHECK4-NEXT: store i32 [[ADD5]], ptr [[G1]], align 4502// CHECK4-NEXT: store i32 1, ptr [[G1]], align 4503// CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 0504// CHECK4-NEXT: store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 8505// CHECK4-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 1506// CHECK4-NEXT: store i32 1073741824, ptr [[BLOCK_FLAGS]], align 8507// CHECK4-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 2508// CHECK4-NEXT: store i32 0, ptr [[BLOCK_RESERVED]], align 4509// CHECK4-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 3510// CHECK4-NEXT: store ptr @g_block_invoke, ptr [[BLOCK_INVOKE]], align 8511// CHECK4-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 4512// CHECK4-NEXT: store ptr @__block_descriptor_tmp.1, ptr [[BLOCK_DESCRIPTOR]], align 8513// CHECK4-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 5514// CHECK4-NEXT: [[TMP13:%.*]] = load volatile i32, ptr [[G1]], align 4515// CHECK4-NEXT: store volatile i32 [[TMP13]], ptr [[BLOCK_CAPTURED]], align 8516// CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3517// CHECK4-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP14]], align 8518// CHECK4-NEXT: call void [[TMP15]](ptr noundef [[BLOCK]])519// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]520// CHECK4: omp.body.continue:521// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]522// CHECK4: omp.inner.for.inc:523// CHECK4-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4524// CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1525// CHECK4-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4526// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]]527// CHECK4: omp.inner.for.end:528// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]529// CHECK4: omp.loop.exit:530// CHECK4-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]])531// CHECK4-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4532// CHECK4-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0533// CHECK4-NEXT: br i1 [[TMP18]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]534// CHECK4: .omp.linear.pu:535// CHECK4-NEXT: [[TMP19:%.*]] = load i32, ptr [[G1]], align 4536// CHECK4-NEXT: store i32 [[TMP19]], ptr [[TMP0]], align 4537// CHECK4-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]538// CHECK4: .omp.linear.pu.done:539// CHECK4-NEXT: ret void540//541//542// CHECK4-LABEL: define {{[^@]+}}@g_block_invoke543// CHECK4-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] {544// CHECK4-NEXT: entry:545// CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8546// CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8547// CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8548// CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8549// CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 5550// CHECK4-NEXT: store i32 2, ptr [[BLOCK_CAPTURE_ADDR]], align 8551// CHECK4-NEXT: ret void552//553