4032 lines · cpp
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _2// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp -fopenmp-version=45 -x c++ -emit-llvm %s -o - -femit-all-decls | FileCheck %s --check-prefix=CHECK13// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s4// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - -femit-all-decls | FileCheck %s --check-prefix=CHECK25// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK36// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s7// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK38 9// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd -fopenmp-version=45 -x c++ -emit-llvm %s -o - -femit-all-decls | FileCheck %s --check-prefix=CHECK510// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s11// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - -femit-all-decls | FileCheck %s --check-prefix=CHECK612// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd -x c++ -emit-llvm %s -o - -femit-all-decls | FileCheck %s --check-prefix=CHECK713// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s14// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - -femit-all-decls | FileCheck %s --check-prefix=CHECK815// expected-no-diagnostics16#ifndef HEADER17#define HEADER18 19int main(int argc, char **argv) {20 21 22 23 24 25#pragma omp parallel master taskloop simd priority(argc) safelen(8)26 for (int i = 0; i < 10; ++i)27 ;28 29 30 31#pragma omp parallel master taskloop simd nogroup grainsize(argc) simdlen(16)32 for (int i = 0; i < 10; ++i)33 ;34 35 36 int i;37#pragma omp parallel master taskloop simd if(argc) shared(argc, argv) collapse(2) num_tasks(argc) lastprivate(i) aligned(argv:8)38 for (i = 0; i < argc; ++i)39 for (int j = argc; j < argv[argc][argc]; ++j)40 ;41}42 43struct S {44 int a;45 S(int c) {46 47#pragma omp parallel master taskloop simd shared(c) num_tasks(4) final(c)48 for (a = 0; a < c; ++a)49 ;50 }51} s(1);52 53 54 55#endif56// CHECK1-LABEL: define {{[^@]+}}@main57// CHECK1-SAME: (i32 noundef [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {58// CHECK1-NEXT: entry:59// CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 460// CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 461// CHECK1-NEXT: [[ARGV_ADDR:%.*]] = alloca ptr, align 862// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 463// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 864// CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 465// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i64, align 866// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 467// CHECK1-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i8, align 168// CHECK1-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 469// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED5:%.*]] = alloca i64, align 870// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED7:%.*]] = alloca i64, align 871// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 472// CHECK1-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 473// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])74// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 475// CHECK1-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 476// CHECK1-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 877// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARGC_ADDR]], align 478// CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 479// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 480// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 481// CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 882// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @main.omp_outlined, i64 [[TMP3]])83// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARGC_ADDR]], align 484// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_1]], align 485// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 486// CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR__CASTED2]], align 487// CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED2]], align 888// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @main.omp_outlined.1, i64 [[TMP6]])89// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARGC_ADDR]], align 490// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 091// CHECK1-NEXT: [[STOREDV:%.*]] = zext i1 [[TOBOOL]] to i892// CHECK1-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_3]], align 193// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[ARGC_ADDR]], align 494// CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTCAPTURE_EXPR_4]], align 495// CHECK1-NEXT: [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_3]], align 196// CHECK1-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP9]] to i197// CHECK1-NEXT: [[STOREDV6:%.*]] = zext i1 [[LOADEDV]] to i898// CHECK1-NEXT: store i8 [[STOREDV6]], ptr [[DOTCAPTURE_EXPR__CASTED5]], align 199// CHECK1-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED5]], align 8100// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4101// CHECK1-NEXT: store i32 [[TMP11]], ptr [[DOTCAPTURE_EXPR__CASTED7]], align 4102// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED7]], align 8103// CHECK1-NEXT: [[TMP13:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_3]], align 1104// CHECK1-NEXT: [[LOADEDV8:%.*]] = trunc i8 [[TMP13]] to i1105// CHECK1-NEXT: br i1 [[LOADEDV8]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]106// CHECK1: omp_if.then:107// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @main.omp_outlined.4, ptr [[I]], ptr [[ARGC_ADDR]], ptr [[ARGV_ADDR]], i64 [[TMP10]], i64 [[TMP12]])108// CHECK1-NEXT: br label [[OMP_IF_END:%.*]]109// CHECK1: omp_if.else:110// CHECK1-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])111// CHECK1-NEXT: store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4112// CHECK1-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4113// CHECK1-NEXT: call void @main.omp_outlined.4(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[I]], ptr [[ARGC_ADDR]], ptr [[ARGV_ADDR]], i64 [[TMP10]], i64 [[TMP12]]) #[[ATTR2:[0-9]+]]114// CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])115// CHECK1-NEXT: br label [[OMP_IF_END]]116// CHECK1: omp_if.end:117// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4118// CHECK1-NEXT: ret i32 [[TMP14]]119//120//121// CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined122// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] {123// CHECK1-NEXT: entry:124// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8125// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8126// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8127// CHECK1-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1128// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4129// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8130// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8131// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8132// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8133// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4134// CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP1]])135// CHECK1-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0136// CHECK1-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]137// CHECK1: omp_if.then:138// CHECK1-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP1]])139// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4140// CHECK1-NEXT: [[TMP5:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP1]], i32 33, i64 80, i64 1, ptr @.omp_task_entry.)141// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP5]], i32 0, i32 0142// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP6]], i32 0, i32 4143// CHECK1-NEXT: store i32 [[TMP4]], ptr [[TMP7]], align 8144// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP6]], i32 0, i32 5145// CHECK1-NEXT: store i64 0, ptr [[TMP8]], align 8146// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP6]], i32 0, i32 6147// CHECK1-NEXT: store i64 9, ptr [[TMP9]], align 8148// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP6]], i32 0, i32 7149// CHECK1-NEXT: store i64 1, ptr [[TMP10]], align 8150// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP6]], i32 0, i32 9151// CHECK1-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP11]], i8 0, i64 8, i1 false)152// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP10]], align 8153// CHECK1-NEXT: call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP1]], ptr [[TMP5]], i32 1, ptr [[TMP8]], ptr [[TMP9]], i64 [[TMP12]], i32 1, i32 0, i64 0, ptr null)154// CHECK1-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP1]])155// CHECK1-NEXT: call void @__kmpc_end_master(ptr @[[GLOB1]], i32 [[TMP1]])156// CHECK1-NEXT: br label [[OMP_IF_END]]157// CHECK1: omp_if.end:158// CHECK1-NEXT: ret void159//160//161// CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry.162// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] {163// CHECK1-NEXT: entry:164// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4165// CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8166// CHECK1-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8167// CHECK1-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8168// CHECK1-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8169// CHECK1-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8170// CHECK1-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8171// CHECK1-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 8172// CHECK1-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4173// CHECK1-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 8174// CHECK1-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8175// CHECK1-NEXT: [[I_I:%.*]] = alloca i32, align 4176// CHECK1-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 4177// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4178// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8179// CHECK1-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4180// CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8181// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4182// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8183// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0184// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2185// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0186// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8187// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5188// CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[TMP8]], align 8189// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6190// CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 8191// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 7192// CHECK1-NEXT: [[TMP13:%.*]] = load i64, ptr [[TMP12]], align 8193// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 8194// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 8195// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9196// CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8197// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])198// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])199// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])200// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])201// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])202// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META14:![0-9]+]]203// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META14]]204// CHECK1-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]]205// CHECK1-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]]206// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META14]]207// CHECK1-NEXT: store i64 [[TMP9]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]]208// CHECK1-NEXT: store i64 [[TMP11]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]]209// CHECK1-NEXT: store i64 [[TMP13]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META14]]210// CHECK1-NEXT: store i32 [[TMP15]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META14]]211// CHECK1-NEXT: store ptr [[TMP17]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META14]]212// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]]213// CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]]214// CHECK1-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]]215// CHECK1-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP19]] to i32216// CHECK1-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]]217// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]218// CHECK1: omp.inner.for.cond.i:219// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]]220// CHECK1-NEXT: [[CONV1_I:%.*]] = sext i32 [[TMP20]] to i64221// CHECK1-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]]222// CHECK1-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV1_I]], [[TMP21]]223// CHECK1-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]]224// CHECK1: omp.inner.for.body.i:225// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]]226// CHECK1-NEXT: store i32 [[TMP22]], ptr [[I_I]], align 4, !noalias [[META14]]227// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]]228// CHECK1-NEXT: [[ADD2_I:%.*]] = add nsw i32 [[TMP23]], 1229// CHECK1-NEXT: store i32 [[ADD2_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]]230// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP15:![0-9]+]]231// CHECK1: .omp_outlined..exit:232// CHECK1-NEXT: ret i32 0233//234//235// CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.1236// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {237// CHECK1-NEXT: entry:238// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8239// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8240// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8241// CHECK1-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_0:%.*]], align 1242// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4243// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8244// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8245// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8246// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8247// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4248// CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP1]])249// CHECK1-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0250// CHECK1-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]251// CHECK1: omp_if.then:252// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4253// CHECK1-NEXT: [[TMP5:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i64 80, i64 1, ptr @.omp_task_entry..3)254// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.*]], ptr [[TMP5]], i32 0, i32 0255// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP6]], i32 0, i32 5256// CHECK1-NEXT: store i64 0, ptr [[TMP7]], align 8257// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP6]], i32 0, i32 6258// CHECK1-NEXT: store i64 9, ptr [[TMP8]], align 8259// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP6]], i32 0, i32 7260// CHECK1-NEXT: store i64 1, ptr [[TMP9]], align 8261// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP6]], i32 0, i32 9262// CHECK1-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP10]], i8 0, i64 8, i1 false)263// CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP9]], align 8264// CHECK1-NEXT: [[TMP12:%.*]] = zext i32 [[TMP4]] to i64265// CHECK1-NEXT: call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP1]], ptr [[TMP5]], i32 1, ptr [[TMP7]], ptr [[TMP8]], i64 [[TMP11]], i32 1, i32 1, i64 [[TMP12]], ptr null)266// CHECK1-NEXT: call void @__kmpc_end_master(ptr @[[GLOB1]], i32 [[TMP1]])267// CHECK1-NEXT: br label [[OMP_IF_END]]268// CHECK1: omp_if.end:269// CHECK1-NEXT: ret void270//271//272// CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..3273// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR4]] {274// CHECK1-NEXT: entry:275// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4276// CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8277// CHECK1-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8278// CHECK1-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8279// CHECK1-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8280// CHECK1-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8281// CHECK1-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8282// CHECK1-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 8283// CHECK1-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4284// CHECK1-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 8285// CHECK1-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8286// CHECK1-NEXT: [[I_I:%.*]] = alloca i32, align 4287// CHECK1-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 4288// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4289// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8290// CHECK1-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4291// CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8292// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4293// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8294// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.*]], ptr [[TMP3]], i32 0, i32 0295// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2296// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0297// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8298// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5299// CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[TMP8]], align 8300// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6301// CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 8302// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 7303// CHECK1-NEXT: [[TMP13:%.*]] = load i64, ptr [[TMP12]], align 8304// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 8305// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 8306// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9307// CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8308// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])309// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])310// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]])311// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META27:![0-9]+]])312// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META29:![0-9]+]])313// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META31:![0-9]+]]314// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META31]]315// CHECK1-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META31]]316// CHECK1-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META31]]317// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META31]]318// CHECK1-NEXT: store i64 [[TMP9]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META31]]319// CHECK1-NEXT: store i64 [[TMP11]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META31]]320// CHECK1-NEXT: store i64 [[TMP13]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META31]]321// CHECK1-NEXT: store i32 [[TMP15]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META31]]322// CHECK1-NEXT: store ptr [[TMP17]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META31]]323// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META31]]324// CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META31]]325// CHECK1-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META31]]326// CHECK1-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP19]] to i32327// CHECK1-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META31]]328// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]329// CHECK1: omp.inner.for.cond.i:330// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META31]], !llvm.access.group [[ACC_GRP32:![0-9]+]]331// CHECK1-NEXT: [[CONV1_I:%.*]] = sext i32 [[TMP20]] to i64332// CHECK1-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META31]], !llvm.access.group [[ACC_GRP32]]333// CHECK1-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV1_I]], [[TMP21]]334// CHECK1-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__2_EXIT:%.*]]335// CHECK1: omp.inner.for.body.i:336// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META31]], !llvm.access.group [[ACC_GRP32]]337// CHECK1-NEXT: store i32 [[TMP22]], ptr [[I_I]], align 4, !noalias [[META31]], !llvm.access.group [[ACC_GRP32]]338// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META31]], !llvm.access.group [[ACC_GRP32]]339// CHECK1-NEXT: [[ADD2_I:%.*]] = add nsw i32 [[TMP23]], 1340// CHECK1-NEXT: store i32 [[ADD2_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META31]], !llvm.access.group [[ACC_GRP32]]341// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP33:![0-9]+]]342// CHECK1: .omp_outlined..2.exit:343// CHECK1-NEXT: ret i32 0344//345//346// CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.4347// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[ARGV:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] {348// CHECK1-NEXT: entry:349// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8350// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8351// CHECK1-NEXT: [[I_ADDR:%.*]] = alloca ptr, align 8352// CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 8353// CHECK1-NEXT: [[ARGV_ADDR:%.*]] = alloca ptr, align 8354// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8355// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8356// CHECK1-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_2:%.*]], align 8357// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4358// CHECK1-NEXT: [[_TMP3:%.*]] = alloca i32, align 4359// CHECK1-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4360// CHECK1-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4361// CHECK1-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i32, align 4362// CHECK1-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i64, align 8363// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8364// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8365// CHECK1-NEXT: store ptr [[I]], ptr [[I_ADDR]], align 8366// CHECK1-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8367// CHECK1-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8368// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8369// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 8370// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8, !nonnull [[META36:![0-9]+]], !align [[META37:![0-9]+]]371// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8, !nonnull [[META36]], !align [[META37]]372// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[ARGV_ADDR]], align 8, !nonnull [[META36]], !align [[META38:![0-9]+]]373// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8374// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4375// CHECK1-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP4]])376// CHECK1-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0377// CHECK1-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]378// CHECK1: omp_if.then:379// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[AGG_CAPTURED]], i32 0, i32 0380// CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP7]], align 8381// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[AGG_CAPTURED]], i32 0, i32 1382// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP8]], align 8383// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[AGG_CAPTURED]], i32 0, i32 2384// CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP9]], align 8385// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4386// CHECK1-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP4]])387// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP1]], align 4388// CHECK1-NEXT: store i32 [[TMP11]], ptr [[DOTCAPTURE_EXPR_4]], align 4389// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP1]], align 4390// CHECK1-NEXT: store i32 [[TMP12]], ptr [[DOTCAPTURE_EXPR_5]], align 4391// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP2]], align 8392// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP1]], align 4393// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64394// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds ptr, ptr [[TMP13]], i64 [[IDXPROM]]395// CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8396// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP1]], align 4397// CHECK1-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP16]] to i64398// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i8, ptr [[TMP15]], i64 [[IDXPROM7]]399// CHECK1-NEXT: [[TMP17:%.*]] = load i8, ptr [[ARRAYIDX8]], align 1400// CHECK1-NEXT: [[CONV:%.*]] = sext i8 [[TMP17]] to i32401// CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTCAPTURE_EXPR_6]], align 4402// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4403// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP18]], 0404// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1405// CHECK1-NEXT: [[CONV10:%.*]] = sext i32 [[DIV]] to i64406// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4407// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4408// CHECK1-NEXT: [[SUB11:%.*]] = sub i32 [[TMP19]], [[TMP20]]409// CHECK1-NEXT: [[SUB12:%.*]] = sub i32 [[SUB11]], 1410// CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB12]], 1411// CHECK1-NEXT: [[DIV13:%.*]] = udiv i32 [[ADD]], 1412// CHECK1-NEXT: [[CONV14:%.*]] = zext i32 [[DIV13]] to i64413// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV10]], [[CONV14]]414// CHECK1-NEXT: [[SUB15:%.*]] = sub nsw i64 [[MUL]], 1415// CHECK1-NEXT: store i64 [[SUB15]], ptr [[DOTCAPTURE_EXPR_9]], align 8416// CHECK1-NEXT: [[TMP21:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP4]], i32 1, i64 88, i64 24, ptr @.omp_task_entry..6)417// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], ptr [[TMP21]], i32 0, i32 0418// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP22]], i32 0, i32 0419// CHECK1-NEXT: [[TMP24:%.*]] = load ptr, ptr [[TMP23]], align 8420// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP24]], ptr align 8 [[AGG_CAPTURED]], i64 24, i1 false)421// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3]], ptr [[TMP21]], i32 0, i32 1422// CHECK1-NEXT: [[TMP26:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1423// CHECK1-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP26]] to i1424// CHECK1-NEXT: [[TMP27:%.*]] = sext i1 [[LOADEDV]] to i32425// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP22]], i32 0, i32 5426// CHECK1-NEXT: store i64 0, ptr [[TMP28]], align 8427// CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP22]], i32 0, i32 6428// CHECK1-NEXT: [[TMP30:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_9]], align 8429// CHECK1-NEXT: store i64 [[TMP30]], ptr [[TMP29]], align 8430// CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP22]], i32 0, i32 7431// CHECK1-NEXT: store i64 1, ptr [[TMP31]], align 8432// CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP22]], i32 0, i32 9433// CHECK1-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP32]], i8 0, i64 8, i1 false)434// CHECK1-NEXT: [[TMP33:%.*]] = load i64, ptr [[TMP31]], align 8435// CHECK1-NEXT: [[TMP34:%.*]] = zext i32 [[TMP10]] to i64436// CHECK1-NEXT: call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP4]], ptr [[TMP21]], i32 [[TMP27]], ptr [[TMP28]], ptr [[TMP29]], i64 [[TMP33]], i32 1, i32 2, i64 [[TMP34]], ptr @.omp_task_dup.)437// CHECK1-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP4]])438// CHECK1-NEXT: call void @__kmpc_end_master(ptr @[[GLOB1]], i32 [[TMP4]])439// CHECK1-NEXT: br label [[OMP_IF_END]]440// CHECK1: omp_if.end:441// CHECK1-NEXT: ret void442//443//444// CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map.445// CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] {446// CHECK1-NEXT: entry:447// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8448// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8449// CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8450// CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8451// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8452// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP2]], i32 0, i32 0453// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR1]], align 8454// CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP4]], align 8455// CHECK1-NEXT: ret void456//457//458// CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..6459// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR4]] {460// CHECK1-NEXT: entry:461// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4462// CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8463// CHECK1-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8464// CHECK1-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8465// CHECK1-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8466// CHECK1-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8467// CHECK1-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8468// CHECK1-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 8469// CHECK1-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4470// CHECK1-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 8471// CHECK1-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8472// CHECK1-NEXT: [[DOTLASTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 8473// CHECK1-NEXT: [[DOTCAPTURE_EXPR__I:%.*]] = alloca i32, align 4474// CHECK1-NEXT: [[DOTCAPTURE_EXPR_2_I:%.*]] = alloca i32, align 4475// CHECK1-NEXT: [[DOTCAPTURE_EXPR_3_I:%.*]] = alloca i32, align 4476// CHECK1-NEXT: [[DOTCAPTURE_EXPR_6_I:%.*]] = alloca i64, align 8477// CHECK1-NEXT: [[I_I:%.*]] = alloca i32, align 4478// CHECK1-NEXT: [[J_I:%.*]] = alloca i32, align 4479// CHECK1-NEXT: [[I14_I:%.*]] = alloca i32, align 4480// CHECK1-NEXT: [[J15_I:%.*]] = alloca i32, align 4481// CHECK1-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i64, align 8482// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4483// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8484// CHECK1-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4485// CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8486// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4487// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8488// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], ptr [[TMP3]], i32 0, i32 0489// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2490// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0491// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8492// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3]], ptr [[TMP3]], i32 0, i32 1493// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5494// CHECK1-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP9]], align 8495// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6496// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP11]], align 8497// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 7498// CHECK1-NEXT: [[TMP14:%.*]] = load i64, ptr [[TMP13]], align 8499// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 8500// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 8501// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9502// CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8503// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META39:![0-9]+]])504// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META42:![0-9]+]])505// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META44:![0-9]+]])506// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META46:![0-9]+]])507// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META48:![0-9]+]])508// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META50:![0-9]+]]509// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META50]]510// CHECK1-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META50]]511// CHECK1-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META50]]512// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META50]]513// CHECK1-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META50]]514// CHECK1-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META50]]515// CHECK1-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META50]]516// CHECK1-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META50]]517// CHECK1-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META50]]518// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META50]]519// CHECK1-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META50]]520// CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META50]]521// CHECK1-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META50]]522// CHECK1-NEXT: call void [[TMP20]](ptr [[TMP21]], ptr [[DOTLASTPRIV_PTR_ADDR_I]]) #[[ATTR2]]523// CHECK1-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP19]], align 8, !nonnull [[META36]], !align [[META37]]524// CHECK1-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias [[META50]]525// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2:%.*]], ptr [[TMP19]], i32 0, i32 1526// CHECK1-NEXT: [[TMP25:%.*]] = load ptr, ptr [[TMP24]], align 8, !nonnull [[META36]], !align [[META37]]527// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4528// CHECK1-NEXT: store i32 [[TMP26]], ptr [[DOTCAPTURE_EXPR__I]], align 4, !noalias [[META50]]529// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[TMP19]], i32 0, i32 1530// CHECK1-NEXT: [[TMP28:%.*]] = load ptr, ptr [[TMP27]], align 8, !nonnull [[META36]], !align [[META37]]531// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[TMP28]], align 4532// CHECK1-NEXT: store i32 [[TMP29]], ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META50]]533// CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[TMP19]], i32 0, i32 2534// CHECK1-NEXT: [[TMP31:%.*]] = load ptr, ptr [[TMP30]], align 8, !nonnull [[META36]], !align [[META38]]535// CHECK1-NEXT: [[TMP32:%.*]] = load ptr, ptr [[TMP31]], align 8536// CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[TMP19]], i32 0, i32 1537// CHECK1-NEXT: [[TMP34:%.*]] = load ptr, ptr [[TMP33]], align 8, !nonnull [[META36]], !align [[META37]]538// CHECK1-NEXT: [[TMP35:%.*]] = load i32, ptr [[TMP34]], align 4539// CHECK1-NEXT: [[IDXPROM_I:%.*]] = sext i32 [[TMP35]] to i64540// CHECK1-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds ptr, ptr [[TMP32]], i64 [[IDXPROM_I]]541// CHECK1-NEXT: [[TMP36:%.*]] = load ptr, ptr [[ARRAYIDX_I]], align 8542// CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[TMP19]], i32 0, i32 1543// CHECK1-NEXT: [[TMP38:%.*]] = load ptr, ptr [[TMP37]], align 8, !nonnull [[META36]], !align [[META37]]544// CHECK1-NEXT: [[TMP39:%.*]] = load i32, ptr [[TMP38]], align 4545// CHECK1-NEXT: [[IDXPROM4_I:%.*]] = sext i32 [[TMP39]] to i64546// CHECK1-NEXT: [[ARRAYIDX5_I:%.*]] = getelementptr inbounds i8, ptr [[TMP36]], i64 [[IDXPROM4_I]]547// CHECK1-NEXT: [[TMP40:%.*]] = load i8, ptr [[ARRAYIDX5_I]], align 1548// CHECK1-NEXT: [[CONV_I:%.*]] = sext i8 [[TMP40]] to i32549// CHECK1-NEXT: store i32 [[CONV_I]], ptr [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias [[META50]]550// CHECK1-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__I]], align 4, !noalias [[META50]]551// CHECK1-NEXT: [[CONV7_I:%.*]] = sext i32 [[TMP41]] to i64552// CHECK1-NEXT: [[TMP42:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias [[META50]]553// CHECK1-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META50]]554// CHECK1-NEXT: [[SUB8_I:%.*]] = sub i32 [[TMP42]], [[TMP43]]555// CHECK1-NEXT: [[SUB9_I:%.*]] = sub i32 [[SUB8_I]], 1556// CHECK1-NEXT: [[CONV11_I:%.*]] = zext i32 [[SUB8_I]] to i64557// CHECK1-NEXT: [[MUL_I:%.*]] = mul nsw i64 [[CONV7_I]], [[CONV11_I]]558// CHECK1-NEXT: [[SUB12_I:%.*]] = sub nsw i64 [[MUL_I]], 1559// CHECK1-NEXT: store i64 [[SUB12_I]], ptr [[DOTCAPTURE_EXPR_6_I]], align 8, !noalias [[META50]]560// CHECK1-NEXT: store i32 0, ptr [[I_I]], align 4, !noalias [[META50]]561// CHECK1-NEXT: [[TMP44:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META50]]562// CHECK1-NEXT: store i32 [[TMP44]], ptr [[J_I]], align 4, !noalias [[META50]]563// CHECK1-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__I]], align 4, !noalias [[META50]]564// CHECK1-NEXT: [[CMP_I:%.*]] = icmp slt i32 0, [[TMP45]]565// CHECK1-NEXT: br i1 [[CMP_I]], label [[LAND_LHS_TRUE_I:%.*]], label [[TASKLOOP_IF_END_I:%.*]]566// CHECK1: land.lhs.true.i:567// CHECK1-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META50]]568// CHECK1-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias [[META50]]569// CHECK1-NEXT: [[CMP13_I:%.*]] = icmp slt i32 [[TMP46]], [[TMP47]]570// CHECK1-NEXT: br i1 [[CMP13_I]], label [[TASKLOOP_IF_THEN_I:%.*]], label [[TASKLOOP_IF_END_I]]571// CHECK1: taskloop.if.then.i:572// CHECK1-NEXT: [[TMP48:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META50]]573// CHECK1-NEXT: store i64 [[TMP48]], ptr [[DOTOMP_IV_I]], align 8, !noalias [[META50]]574// CHECK1-NEXT: [[TMP49:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[TMP19]], i32 0, i32 1575// CHECK1-NEXT: [[TMP50:%.*]] = load ptr, ptr [[TMP49]], align 8, !nonnull [[META36]], !align [[META37]]576// CHECK1-NEXT: [[TMP51:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[TMP19]], i32 0, i32 2577// CHECK1-NEXT: [[TMP52:%.*]] = load ptr, ptr [[TMP51]], align 8, !nonnull [[META36]], !align [[META38]]578// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]579// CHECK1: omp.inner.for.cond.i:580// CHECK1-NEXT: [[TMP53:%.*]] = load i64, ptr [[DOTOMP_IV_I]], align 8, !noalias [[META50]], !llvm.access.group [[ACC_GRP51:![0-9]+]]581// CHECK1-NEXT: [[TMP54:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META50]], !llvm.access.group [[ACC_GRP51]]582// CHECK1-NEXT: [[CMP16_I:%.*]] = icmp ule i64 [[TMP53]], [[TMP54]]583// CHECK1-NEXT: br i1 [[CMP16_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[OMP_INNER_FOR_END_I:%.*]]584// CHECK1: omp.inner.for.body.i:585// CHECK1-NEXT: [[TMP55:%.*]] = load i64, ptr [[DOTOMP_IV_I]], align 8, !noalias [[META50]], !llvm.access.group [[ACC_GRP51]]586// CHECK1-NEXT: [[TMP56:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias [[META50]], !llvm.access.group [[ACC_GRP51]]587// CHECK1-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META50]], !llvm.access.group [[ACC_GRP51]]588// CHECK1-NEXT: [[SUB17_I:%.*]] = sub i32 [[TMP56]], [[TMP57]]589// CHECK1-NEXT: [[SUB18_I:%.*]] = sub i32 [[SUB17_I]], 1590// CHECK1-NEXT: [[CONV22_I:%.*]] = zext i32 [[SUB17_I]] to i64591// CHECK1-NEXT: [[DIV23_I:%.*]] = sdiv i64 [[TMP55]], [[CONV22_I]]592// CHECK1-NEXT: [[CONV26_I:%.*]] = trunc i64 [[DIV23_I]] to i32593// CHECK1-NEXT: store i32 [[CONV26_I]], ptr [[I14_I]], align 4, !noalias [[META50]], !llvm.access.group [[ACC_GRP51]]594// CHECK1-NEXT: [[TMP58:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META50]], !llvm.access.group [[ACC_GRP51]]595// CHECK1-NEXT: [[CONV27_I:%.*]] = sext i32 [[TMP58]] to i64596// CHECK1-NEXT: [[TMP59:%.*]] = load i64, ptr [[DOTOMP_IV_I]], align 8, !noalias [[META50]], !llvm.access.group [[ACC_GRP51]]597// CHECK1-NEXT: [[TMP60:%.*]] = load i64, ptr [[DOTOMP_IV_I]], align 8, !noalias [[META50]], !llvm.access.group [[ACC_GRP51]]598// CHECK1-NEXT: [[TMP61:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias [[META50]], !llvm.access.group [[ACC_GRP51]]599// CHECK1-NEXT: [[TMP62:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META50]], !llvm.access.group [[ACC_GRP51]]600// CHECK1-NEXT: [[SUB28_I:%.*]] = sub i32 [[TMP61]], [[TMP62]]601// CHECK1-NEXT: [[SUB29_I:%.*]] = sub i32 [[SUB28_I]], 1602// CHECK1-NEXT: [[CONV33_I:%.*]] = zext i32 [[SUB28_I]] to i64603// CHECK1-NEXT: [[DIV34_I:%.*]] = sdiv i64 [[TMP60]], [[CONV33_I]]604// CHECK1-NEXT: [[TMP63:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias [[META50]], !llvm.access.group [[ACC_GRP51]]605// CHECK1-NEXT: [[TMP64:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META50]], !llvm.access.group [[ACC_GRP51]]606// CHECK1-NEXT: [[SUB35_I:%.*]] = sub i32 [[TMP63]], [[TMP64]]607// CHECK1-NEXT: [[SUB36_I:%.*]] = sub i32 [[SUB35_I]], 1608// CHECK1-NEXT: [[CONV40_I:%.*]] = zext i32 [[SUB35_I]] to i64609// CHECK1-NEXT: [[MUL41_I:%.*]] = mul nsw i64 [[DIV34_I]], [[CONV40_I]]610// CHECK1-NEXT: [[SUB42_I:%.*]] = sub nsw i64 [[TMP59]], [[MUL41_I]]611// CHECK1-NEXT: [[ADD44_I:%.*]] = add nsw i64 [[CONV27_I]], [[SUB42_I]]612// CHECK1-NEXT: [[CONV45_I:%.*]] = trunc i64 [[ADD44_I]] to i32613// CHECK1-NEXT: store i32 [[CONV45_I]], ptr [[J15_I]], align 4, !noalias [[META50]], !llvm.access.group [[ACC_GRP51]]614// CHECK1-NEXT: [[TMP65:%.*]] = load i64, ptr [[DOTOMP_IV_I]], align 8, !noalias [[META50]], !llvm.access.group [[ACC_GRP51]]615// CHECK1-NEXT: [[ADD46_I:%.*]] = add nsw i64 [[TMP65]], 1616// CHECK1-NEXT: store i64 [[ADD46_I]], ptr [[DOTOMP_IV_I]], align 8, !noalias [[META50]], !llvm.access.group [[ACC_GRP51]]617// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP52:![0-9]+]]618// CHECK1: omp.inner.for.end.i:619// CHECK1-NEXT: br label [[TASKLOOP_IF_END_I]]620// CHECK1: taskloop.if.end.i:621// CHECK1-NEXT: [[TMP66:%.*]] = load i32, ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META50]]622// CHECK1-NEXT: [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0623// CHECK1-NEXT: br i1 [[TMP67]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.*]], label [[DOTOMP_OUTLINED__5_EXIT:%.*]]624// CHECK1: .omp.lastprivate.then.i:625// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__5_EXIT]]626// CHECK1: .omp_outlined..5.exit:627// CHECK1-NEXT: ret i32 0628//629//630// CHECK1-LABEL: define {{[^@]+}}@.omp_task_dup.631// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], i32 noundef [[TMP2:%.*]]) #[[ATTR4]] {632// CHECK1-NEXT: entry:633// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8634// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8635// CHECK1-NEXT: [[DOTADDR2:%.*]] = alloca i32, align 4636// CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8637// CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8638// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTADDR2]], align 4639// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR]], align 8640// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], ptr [[TMP3]], i32 0, i32 0641// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 8642// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTADDR2]], align 4643// CHECK1-NEXT: store i32 [[TMP6]], ptr [[TMP5]], align 8644// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3]], ptr [[TMP3]], i32 0, i32 1645// CHECK1-NEXT: ret void646//647//648// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init649// CHECK1-SAME: () #[[ATTR6]] section "__TEXT,__StaticInit,regular,pure_instructions" {650// CHECK1-NEXT: entry:651// CHECK1-NEXT: call void @_ZN1SC1Ei(ptr noundef nonnull align 4 dereferenceable(4) @s, i32 noundef 1)652// CHECK1-NEXT: ret void653//654//655// CHECK1-LABEL: define {{[^@]+}}@_ZN1SC1Ei656// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] align 2 {657// CHECK1-NEXT: entry:658// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8659// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4660// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8661// CHECK1-NEXT: store i32 [[C]], ptr [[C_ADDR]], align 4662// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8663// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[C_ADDR]], align 4664// CHECK1-NEXT: call void @_ZN1SC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])665// CHECK1-NEXT: ret void666//667//668// CHECK1-LABEL: define {{[^@]+}}@_ZN1SC2Ei669// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR8]] align 2 {670// CHECK1-NEXT: entry:671// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8672// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4673// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1674// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8675// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8676// CHECK1-NEXT: store i32 [[C]], ptr [[C_ADDR]], align 4677// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8678// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[C_ADDR]], align 4679// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0680// CHECK1-NEXT: [[STOREDV:%.*]] = zext i1 [[TOBOOL]] to i8681// CHECK1-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_]], align 1682// CHECK1-NEXT: [[TMP1:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1683// CHECK1-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP1]] to i1684// CHECK1-NEXT: [[STOREDV2:%.*]] = zext i1 [[LOADEDV]] to i8685// CHECK1-NEXT: store i8 [[STOREDV2]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1686// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8687// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 3, ptr @_ZN1SC2Ei.omp_outlined, ptr [[THIS1]], ptr [[C_ADDR]], i64 [[TMP2]])688// CHECK1-NEXT: ret void689//690//691// CHECK1-LABEL: define {{[^@]+}}@_ZN1SC2Ei.omp_outlined692// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {693// CHECK1-NEXT: entry:694// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8695// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8696// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8697// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8698// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8699// CHECK1-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_4:%.*]], align 8700// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4701// CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8702// CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4703// CHECK1-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4704// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8705// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8706// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8707// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8708// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8709// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8710// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META36]], !align [[META37]]711// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8712// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4713// CHECK1-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP3]])714// CHECK1-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0715// CHECK1-NEXT: br i1 [[TMP5]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]716// CHECK1: omp_if.then:717// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_4]], ptr [[AGG_CAPTURED]], i32 0, i32 0718// CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP6]], align 8719// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_4]], ptr [[AGG_CAPTURED]], i32 0, i32 1720// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP7]], align 8721// CHECK1-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP3]])722// CHECK1-NEXT: [[TMP8:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1723// CHECK1-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP8]] to i1724// CHECK1-NEXT: store ptr [[TMP]], ptr [[_TMP1]], align 8725// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP1]], align 4726// CHECK1-NEXT: store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR_2]], align 4727// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4728// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP10]], 0729// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1730// CHECK1-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1731// CHECK1-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_3]], align 4732// CHECK1-NEXT: [[TMP11:%.*]] = select i1 [[LOADEDV]], i32 2, i32 0733// CHECK1-NEXT: [[TMP12:%.*]] = or i32 [[TMP11]], 1734// CHECK1-NEXT: [[TMP13:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP3]], i32 [[TMP12]], i64 80, i64 16, ptr @.omp_task_entry..8)735// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.*]], ptr [[TMP13]], i32 0, i32 0736// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP14]], i32 0, i32 0737// CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8738// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP16]], ptr align 8 [[AGG_CAPTURED]], i64 16, i1 false)739// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP14]], i32 0, i32 5740// CHECK1-NEXT: store i64 0, ptr [[TMP17]], align 8741// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP14]], i32 0, i32 6742// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4743// CHECK1-NEXT: [[CONV:%.*]] = sext i32 [[TMP19]] to i64744// CHECK1-NEXT: store i64 [[CONV]], ptr [[TMP18]], align 8745// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP14]], i32 0, i32 7746// CHECK1-NEXT: store i64 1, ptr [[TMP20]], align 8747// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP14]], i32 0, i32 9748// CHECK1-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP21]], i8 0, i64 8, i1 false)749// CHECK1-NEXT: [[TMP22:%.*]] = load i64, ptr [[TMP20]], align 8750// CHECK1-NEXT: call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP3]], ptr [[TMP13]], i32 1, ptr [[TMP17]], ptr [[TMP18]], i64 [[TMP22]], i32 1, i32 2, i64 4, ptr null)751// CHECK1-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP3]])752// CHECK1-NEXT: call void @__kmpc_end_master(ptr @[[GLOB1]], i32 [[TMP3]])753// CHECK1-NEXT: br label [[OMP_IF_END]]754// CHECK1: omp_if.end:755// CHECK1-NEXT: ret void756//757//758// CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..8759// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR4]] {760// CHECK1-NEXT: entry:761// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4762// CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8763// CHECK1-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8764// CHECK1-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8765// CHECK1-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8766// CHECK1-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8767// CHECK1-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8768// CHECK1-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 8769// CHECK1-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4770// CHECK1-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 8771// CHECK1-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8772// CHECK1-NEXT: [[TMP_I:%.*]] = alloca i32, align 4773// CHECK1-NEXT: [[TMP1_I:%.*]] = alloca ptr, align 8774// CHECK1-NEXT: [[DOTCAPTURE_EXPR__I:%.*]] = alloca i32, align 4775// CHECK1-NEXT: [[DOTCAPTURE_EXPR_2_I:%.*]] = alloca i32, align 4776// CHECK1-NEXT: [[A_I:%.*]] = alloca i32, align 4777// CHECK1-NEXT: [[TMP4_I:%.*]] = alloca ptr, align 8778// CHECK1-NEXT: [[A5_I:%.*]] = alloca i32, align 4779// CHECK1-NEXT: [[TMP6_I:%.*]] = alloca ptr, align 8780// CHECK1-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 4781// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4782// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8783// CHECK1-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4784// CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8785// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4786// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8787// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.*]], ptr [[TMP3]], i32 0, i32 0788// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2789// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0790// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8791// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5792// CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[TMP8]], align 8793// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6794// CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 8795// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 7796// CHECK1-NEXT: [[TMP13:%.*]] = load i64, ptr [[TMP12]], align 8797// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 8798// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 8799// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9800// CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8801// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META54:![0-9]+]])802// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META57:![0-9]+]])803// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META59:![0-9]+]])804// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META61:![0-9]+]])805// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META63:![0-9]+]])806// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META65:![0-9]+]]807// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META65]]808// CHECK1-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META65]]809// CHECK1-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META65]]810// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META65]]811// CHECK1-NEXT: store i64 [[TMP9]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META65]]812// CHECK1-NEXT: store i64 [[TMP11]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META65]]813// CHECK1-NEXT: store i64 [[TMP13]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META65]]814// CHECK1-NEXT: store i32 [[TMP15]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META65]]815// CHECK1-NEXT: store ptr [[TMP17]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META65]]816// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META65]]817// CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META65]]818// CHECK1-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP18]], align 8819// CHECK1-NEXT: store ptr [[TMP_I]], ptr [[TMP1_I]], align 8, !noalias [[META65]]820// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_4:%.*]], ptr [[TMP18]], i32 0, i32 1821// CHECK1-NEXT: [[TMP21:%.*]] = load ptr, ptr [[TMP20]], align 8, !nonnull [[META36]], !align [[META37]]822// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4823// CHECK1-NEXT: store i32 [[TMP22]], ptr [[DOTCAPTURE_EXPR__I]], align 4, !noalias [[META65]]824// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__I]], align 4, !noalias [[META65]]825// CHECK1-NEXT: [[SUB3_I:%.*]] = sub nsw i32 [[TMP23]], 1826// CHECK1-NEXT: store i32 [[SUB3_I]], ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META65]]827// CHECK1-NEXT: store ptr [[A_I]], ptr [[TMP4_I]], align 8, !noalias [[META65]]828// CHECK1-NEXT: [[TMP24:%.*]] = load ptr, ptr [[TMP4_I]], align 8, !noalias [[META65]], !nonnull [[META36]], !align [[META37]]829// CHECK1-NEXT: store i32 0, ptr [[TMP24]], align 4830// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__I]], align 4, !noalias [[META65]]831// CHECK1-NEXT: [[CMP_I:%.*]] = icmp slt i32 0, [[TMP25]]832// CHECK1-NEXT: br i1 [[CMP_I]], label [[TASKLOOP_IF_THEN_I:%.*]], label [[DOTOMP_OUTLINED__7_EXIT:%.*]]833// CHECK1: taskloop.if.then.i:834// CHECK1-NEXT: store ptr [[A5_I]], ptr [[TMP6_I]], align 8, !noalias [[META65]]835// CHECK1-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META65]]836// CHECK1-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP26]] to i32837// CHECK1-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META65]]838// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_4]], ptr [[TMP18]], i32 0, i32 1839// CHECK1-NEXT: [[TMP28:%.*]] = load ptr, ptr [[TMP27]], align 8, !nonnull [[META36]], !align [[META37]]840// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]841// CHECK1: omp.inner.for.cond.i:842// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META65]], !llvm.access.group [[ACC_GRP66:![0-9]+]]843// CHECK1-NEXT: [[CONV7_I:%.*]] = sext i32 [[TMP29]] to i64844// CHECK1-NEXT: [[TMP30:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META65]], !llvm.access.group [[ACC_GRP66]]845// CHECK1-NEXT: [[CMP8_I:%.*]] = icmp ule i64 [[CONV7_I]], [[TMP30]]846// CHECK1-NEXT: br i1 [[CMP8_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[OMP_INNER_FOR_END_I:%.*]]847// CHECK1: omp.inner.for.body.i:848// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META65]], !llvm.access.group [[ACC_GRP66]]849// CHECK1-NEXT: [[TMP32:%.*]] = load ptr, ptr [[TMP6_I]], align 8, !noalias [[META65]], !nonnull [[META36]], !align [[META37]], !llvm.access.group [[ACC_GRP66]]850// CHECK1-NEXT: store i32 [[TMP31]], ptr [[TMP32]], align 4, !llvm.access.group [[ACC_GRP66]]851// CHECK1-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META65]], !llvm.access.group [[ACC_GRP66]]852// CHECK1-NEXT: [[ADD9_I:%.*]] = add nsw i32 [[TMP33]], 1853// CHECK1-NEXT: store i32 [[ADD9_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META65]], !llvm.access.group [[ACC_GRP66]]854// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP67:![0-9]+]]855// CHECK1: omp.inner.for.end.i:856// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__7_EXIT]]857// CHECK1: .omp_outlined..7.exit:858// CHECK1-NEXT: ret i32 0859//860//861// CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_parallel_master_taskloop_simd_codegen.cpp862// CHECK1-SAME: () #[[ATTR6]] section "__TEXT,__StaticInit,regular,pure_instructions" {863// CHECK1-NEXT: entry:864// CHECK1-NEXT: call void @__cxx_global_var_init()865// CHECK1-NEXT: ret void866//867//868// CHECK2-LABEL: define {{[^@]+}}@main869// CHECK2-SAME: (i32 noundef [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {870// CHECK2-NEXT: entry:871// CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4872// CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4873// CHECK2-NEXT: [[ARGV_ADDR:%.*]] = alloca ptr, align 8874// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4875// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8876// CHECK2-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4877// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i64, align 8878// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4879// CHECK2-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i8, align 1880// CHECK2-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4881// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED5:%.*]] = alloca i64, align 8882// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED7:%.*]] = alloca i64, align 8883// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4884// CHECK2-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4885// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])886// CHECK2-NEXT: store i32 0, ptr [[RETVAL]], align 4887// CHECK2-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4888// CHECK2-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8889// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4890// CHECK2-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4891// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4892// CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4893// CHECK2-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8894// CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @main.omp_outlined, i64 [[TMP3]])895// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4896// CHECK2-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_1]], align 4897// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4898// CHECK2-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR__CASTED2]], align 4899// CHECK2-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED2]], align 8900// CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @main.omp_outlined.1, i64 [[TMP6]])901// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4902// CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0903// CHECK2-NEXT: [[STOREDV:%.*]] = zext i1 [[TOBOOL]] to i8904// CHECK2-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_3]], align 1905// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4906// CHECK2-NEXT: store i32 [[TMP8]], ptr [[DOTCAPTURE_EXPR_4]], align 4907// CHECK2-NEXT: [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_3]], align 1908// CHECK2-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP9]] to i1909// CHECK2-NEXT: [[STOREDV6:%.*]] = zext i1 [[LOADEDV]] to i8910// CHECK2-NEXT: store i8 [[STOREDV6]], ptr [[DOTCAPTURE_EXPR__CASTED5]], align 1911// CHECK2-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED5]], align 8912// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4913// CHECK2-NEXT: store i32 [[TMP11]], ptr [[DOTCAPTURE_EXPR__CASTED7]], align 4914// CHECK2-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED7]], align 8915// CHECK2-NEXT: [[TMP13:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_3]], align 1916// CHECK2-NEXT: [[LOADEDV8:%.*]] = trunc i8 [[TMP13]] to i1917// CHECK2-NEXT: br i1 [[LOADEDV8]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]918// CHECK2: omp_if.then:919// CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @main.omp_outlined.4, ptr [[I]], ptr [[ARGC_ADDR]], ptr [[ARGV_ADDR]], i64 [[TMP10]], i64 [[TMP12]])920// CHECK2-NEXT: br label [[OMP_IF_END:%.*]]921// CHECK2: omp_if.else:922// CHECK2-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])923// CHECK2-NEXT: store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4924// CHECK2-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4925// CHECK2-NEXT: call void @main.omp_outlined.4(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[I]], ptr [[ARGC_ADDR]], ptr [[ARGV_ADDR]], i64 [[TMP10]], i64 [[TMP12]]) #[[ATTR2:[0-9]+]]926// CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])927// CHECK2-NEXT: br label [[OMP_IF_END]]928// CHECK2: omp_if.end:929// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4930// CHECK2-NEXT: ret i32 [[TMP14]]931//932//933// CHECK2-LABEL: define {{[^@]+}}@main.omp_outlined934// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] {935// CHECK2-NEXT: entry:936// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8937// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8938// CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8939// CHECK2-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1940// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4941// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8942// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8943// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8944// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8945// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4946// CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP1]])947// CHECK2-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0948// CHECK2-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]949// CHECK2: omp_if.then:950// CHECK2-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP1]])951// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4952// CHECK2-NEXT: [[TMP5:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP1]], i32 33, i64 80, i64 1, ptr @.omp_task_entry.)953// CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP5]], i32 0, i32 0954// CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP6]], i32 0, i32 4955// CHECK2-NEXT: store i32 [[TMP4]], ptr [[TMP7]], align 8956// CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP6]], i32 0, i32 5957// CHECK2-NEXT: store i64 0, ptr [[TMP8]], align 8958// CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP6]], i32 0, i32 6959// CHECK2-NEXT: store i64 9, ptr [[TMP9]], align 8960// CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP6]], i32 0, i32 7961// CHECK2-NEXT: store i64 1, ptr [[TMP10]], align 8962// CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP6]], i32 0, i32 9963// CHECK2-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP11]], i8 0, i64 8, i1 false)964// CHECK2-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP10]], align 8965// CHECK2-NEXT: call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP1]], ptr [[TMP5]], i32 1, ptr [[TMP8]], ptr [[TMP9]], i64 [[TMP12]], i32 1, i32 0, i64 0, ptr null)966// CHECK2-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP1]])967// CHECK2-NEXT: call void @__kmpc_end_master(ptr @[[GLOB1]], i32 [[TMP1]])968// CHECK2-NEXT: br label [[OMP_IF_END]]969// CHECK2: omp_if.end:970// CHECK2-NEXT: ret void971//972//973// CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry.974// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] {975// CHECK2-NEXT: entry:976// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4977// CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8978// CHECK2-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8979// CHECK2-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8980// CHECK2-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8981// CHECK2-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8982// CHECK2-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8983// CHECK2-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 8984// CHECK2-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4985// CHECK2-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 8986// CHECK2-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8987// CHECK2-NEXT: [[I_I:%.*]] = alloca i32, align 4988// CHECK2-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 4989// CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4990// CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8991// CHECK2-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4992// CHECK2-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8993// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4994// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8995// CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0996// CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2997// CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0998// CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8999// CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 51000// CHECK2-NEXT: [[TMP9:%.*]] = load i64, ptr [[TMP8]], align 81001// CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 61002// CHECK2-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 81003// CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 71004// CHECK2-NEXT: [[TMP13:%.*]] = load i64, ptr [[TMP12]], align 81005// CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 81006// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 81007// CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 91008// CHECK2-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 81009// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])1010// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])1011// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])1012// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])1013// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])1014// CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META14:![0-9]+]]1015// CHECK2-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META14]]1016// CHECK2-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]]1017// CHECK2-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]]1018// CHECK2-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META14]]1019// CHECK2-NEXT: store i64 [[TMP9]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]]1020// CHECK2-NEXT: store i64 [[TMP11]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]]1021// CHECK2-NEXT: store i64 [[TMP13]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META14]]1022// CHECK2-NEXT: store i32 [[TMP15]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META14]]1023// CHECK2-NEXT: store ptr [[TMP17]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META14]]1024// CHECK2-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]]1025// CHECK2-NEXT: [[TMP18:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]]1026// CHECK2-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]]1027// CHECK2-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP19]] to i321028// CHECK2-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]]1029// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]1030// CHECK2: omp.inner.for.cond.i:1031// CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]]1032// CHECK2-NEXT: [[CONV1_I:%.*]] = sext i32 [[TMP20]] to i641033// CHECK2-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]]1034// CHECK2-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV1_I]], [[TMP21]]1035// CHECK2-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]]1036// CHECK2: omp.inner.for.body.i:1037// CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]]1038// CHECK2-NEXT: store i32 [[TMP22]], ptr [[I_I]], align 4, !noalias [[META14]]1039// CHECK2-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]]1040// CHECK2-NEXT: [[ADD2_I:%.*]] = add nsw i32 [[TMP23]], 11041// CHECK2-NEXT: store i32 [[ADD2_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]]1042// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP15:![0-9]+]]1043// CHECK2: .omp_outlined..exit:1044// CHECK2-NEXT: ret i32 01045//1046//1047// CHECK2-LABEL: define {{[^@]+}}@main.omp_outlined.11048// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {1049// CHECK2-NEXT: entry:1050// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81051// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81052// CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 81053// CHECK2-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_0:%.*]], align 11054// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 41055// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81056// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81057// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 81058// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81059// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 41060// CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP1]])1061// CHECK2-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 01062// CHECK2-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]1063// CHECK2: omp_if.then:1064// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 41065// CHECK2-NEXT: [[TMP5:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i64 80, i64 1, ptr @.omp_task_entry..3)1066// CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.*]], ptr [[TMP5]], i32 0, i32 01067// CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP6]], i32 0, i32 51068// CHECK2-NEXT: store i64 0, ptr [[TMP7]], align 81069// CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP6]], i32 0, i32 61070// CHECK2-NEXT: store i64 9, ptr [[TMP8]], align 81071// CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP6]], i32 0, i32 71072// CHECK2-NEXT: store i64 1, ptr [[TMP9]], align 81073// CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP6]], i32 0, i32 91074// CHECK2-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP10]], i8 0, i64 8, i1 false)1075// CHECK2-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP9]], align 81076// CHECK2-NEXT: [[TMP12:%.*]] = zext i32 [[TMP4]] to i641077// CHECK2-NEXT: call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP1]], ptr [[TMP5]], i32 1, ptr [[TMP7]], ptr [[TMP8]], i64 [[TMP11]], i32 1, i32 1, i64 [[TMP12]], ptr null)1078// CHECK2-NEXT: call void @__kmpc_end_master(ptr @[[GLOB1]], i32 [[TMP1]])1079// CHECK2-NEXT: br label [[OMP_IF_END]]1080// CHECK2: omp_if.end:1081// CHECK2-NEXT: ret void1082//1083//1084// CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..31085// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR4]] {1086// CHECK2-NEXT: entry:1087// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 41088// CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 81089// CHECK2-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 81090// CHECK2-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 81091// CHECK2-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 81092// CHECK2-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 81093// CHECK2-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 81094// CHECK2-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 81095// CHECK2-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 41096// CHECK2-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 81097// CHECK2-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 81098// CHECK2-NEXT: [[I_I:%.*]] = alloca i32, align 41099// CHECK2-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 41100// CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i32, align 41101// CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 81102// CHECK2-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 41103// CHECK2-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 81104// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 41105// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 81106// CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.*]], ptr [[TMP3]], i32 0, i32 01107// CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 21108// CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 01109// CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 81110// CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 51111// CHECK2-NEXT: [[TMP9:%.*]] = load i64, ptr [[TMP8]], align 81112// CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 61113// CHECK2-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 81114// CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 71115// CHECK2-NEXT: [[TMP13:%.*]] = load i64, ptr [[TMP12]], align 81116// CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 81117// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 81118// CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 91119// CHECK2-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 81120// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])1121// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])1122// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]])1123// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META27:![0-9]+]])1124// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META29:![0-9]+]])1125// CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META31:![0-9]+]]1126// CHECK2-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META31]]1127// CHECK2-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META31]]1128// CHECK2-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META31]]1129// CHECK2-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META31]]1130// CHECK2-NEXT: store i64 [[TMP9]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META31]]1131// CHECK2-NEXT: store i64 [[TMP11]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META31]]1132// CHECK2-NEXT: store i64 [[TMP13]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META31]]1133// CHECK2-NEXT: store i32 [[TMP15]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META31]]1134// CHECK2-NEXT: store ptr [[TMP17]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META31]]1135// CHECK2-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META31]]1136// CHECK2-NEXT: [[TMP18:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META31]]1137// CHECK2-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META31]]1138// CHECK2-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP19]] to i321139// CHECK2-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META31]]1140// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]1141// CHECK2: omp.inner.for.cond.i:1142// CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META31]], !llvm.access.group [[ACC_GRP32:![0-9]+]]1143// CHECK2-NEXT: [[CONV1_I:%.*]] = sext i32 [[TMP20]] to i641144// CHECK2-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META31]], !llvm.access.group [[ACC_GRP32]]1145// CHECK2-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV1_I]], [[TMP21]]1146// CHECK2-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__2_EXIT:%.*]]1147// CHECK2: omp.inner.for.body.i:1148// CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META31]], !llvm.access.group [[ACC_GRP32]]1149// CHECK2-NEXT: store i32 [[TMP22]], ptr [[I_I]], align 4, !noalias [[META31]], !llvm.access.group [[ACC_GRP32]]1150// CHECK2-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META31]], !llvm.access.group [[ACC_GRP32]]1151// CHECK2-NEXT: [[ADD2_I:%.*]] = add nsw i32 [[TMP23]], 11152// CHECK2-NEXT: store i32 [[ADD2_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META31]], !llvm.access.group [[ACC_GRP32]]1153// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP33:![0-9]+]]1154// CHECK2: .omp_outlined..2.exit:1155// CHECK2-NEXT: ret i32 01156//1157//1158// CHECK2-LABEL: define {{[^@]+}}@main.omp_outlined.41159// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[ARGV:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] {1160// CHECK2-NEXT: entry:1161// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81162// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81163// CHECK2-NEXT: [[I_ADDR:%.*]] = alloca ptr, align 81164// CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 81165// CHECK2-NEXT: [[ARGV_ADDR:%.*]] = alloca ptr, align 81166// CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 81167// CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 81168// CHECK2-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_2:%.*]], align 81169// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 41170// CHECK2-NEXT: [[_TMP3:%.*]] = alloca i32, align 41171// CHECK2-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 41172// CHECK2-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 41173// CHECK2-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i32, align 41174// CHECK2-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i64, align 81175// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81176// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81177// CHECK2-NEXT: store ptr [[I]], ptr [[I_ADDR]], align 81178// CHECK2-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 81179// CHECK2-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 81180// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 81181// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 81182// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8, !nonnull [[META36:![0-9]+]], !align [[META37:![0-9]+]]1183// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8, !nonnull [[META36]], !align [[META37]]1184// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[ARGV_ADDR]], align 8, !nonnull [[META36]], !align [[META38:![0-9]+]]1185// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81186// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 41187// CHECK2-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP4]])1188// CHECK2-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 01189// CHECK2-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]1190// CHECK2: omp_if.then:1191// CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[AGG_CAPTURED]], i32 0, i32 01192// CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP7]], align 81193// CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[AGG_CAPTURED]], i32 0, i32 11194// CHECK2-NEXT: store ptr [[TMP1]], ptr [[TMP8]], align 81195// CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[AGG_CAPTURED]], i32 0, i32 21196// CHECK2-NEXT: store ptr [[TMP2]], ptr [[TMP9]], align 81197// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 41198// CHECK2-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP4]])1199// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP1]], align 41200// CHECK2-NEXT: store i32 [[TMP11]], ptr [[DOTCAPTURE_EXPR_4]], align 41201// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP1]], align 41202// CHECK2-NEXT: store i32 [[TMP12]], ptr [[DOTCAPTURE_EXPR_5]], align 41203// CHECK2-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP2]], align 81204// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP1]], align 41205// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i641206// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds ptr, ptr [[TMP13]], i64 [[IDXPROM]]1207// CHECK2-NEXT: [[TMP15:%.*]] = load ptr, ptr [[ARRAYIDX]], align 81208// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP1]], align 41209// CHECK2-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP16]] to i641210// CHECK2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i8, ptr [[TMP15]], i64 [[IDXPROM7]]1211// CHECK2-NEXT: [[TMP17:%.*]] = load i8, ptr [[ARRAYIDX8]], align 11212// CHECK2-NEXT: [[CONV:%.*]] = sext i8 [[TMP17]] to i321213// CHECK2-NEXT: store i32 [[CONV]], ptr [[DOTCAPTURE_EXPR_6]], align 41214// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 41215// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP18]], 01216// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 11217// CHECK2-NEXT: [[CONV10:%.*]] = sext i32 [[DIV]] to i641218// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 41219// CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 41220// CHECK2-NEXT: [[SUB11:%.*]] = sub i32 [[TMP19]], [[TMP20]]1221// CHECK2-NEXT: [[SUB12:%.*]] = sub i32 [[SUB11]], 11222// CHECK2-NEXT: [[ADD:%.*]] = add i32 [[SUB12]], 11223// CHECK2-NEXT: [[DIV13:%.*]] = udiv i32 [[ADD]], 11224// CHECK2-NEXT: [[CONV14:%.*]] = zext i32 [[DIV13]] to i641225// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV10]], [[CONV14]]1226// CHECK2-NEXT: [[SUB15:%.*]] = sub nsw i64 [[MUL]], 11227// CHECK2-NEXT: store i64 [[SUB15]], ptr [[DOTCAPTURE_EXPR_9]], align 81228// CHECK2-NEXT: [[TMP21:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP4]], i32 1, i64 88, i64 24, ptr @.omp_task_entry..6)1229// CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], ptr [[TMP21]], i32 0, i32 01230// CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP22]], i32 0, i32 01231// CHECK2-NEXT: [[TMP24:%.*]] = load ptr, ptr [[TMP23]], align 81232// CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP24]], ptr align 8 [[AGG_CAPTURED]], i64 24, i1 false)1233// CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3]], ptr [[TMP21]], i32 0, i32 11234// CHECK2-NEXT: [[TMP26:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 11235// CHECK2-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP26]] to i11236// CHECK2-NEXT: [[TMP27:%.*]] = sext i1 [[LOADEDV]] to i321237// CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP22]], i32 0, i32 51238// CHECK2-NEXT: store i64 0, ptr [[TMP28]], align 81239// CHECK2-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP22]], i32 0, i32 61240// CHECK2-NEXT: [[TMP30:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_9]], align 81241// CHECK2-NEXT: store i64 [[TMP30]], ptr [[TMP29]], align 81242// CHECK2-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP22]], i32 0, i32 71243// CHECK2-NEXT: store i64 1, ptr [[TMP31]], align 81244// CHECK2-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP22]], i32 0, i32 91245// CHECK2-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP32]], i8 0, i64 8, i1 false)1246// CHECK2-NEXT: [[TMP33:%.*]] = load i64, ptr [[TMP31]], align 81247// CHECK2-NEXT: [[TMP34:%.*]] = zext i32 [[TMP10]] to i641248// CHECK2-NEXT: call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP4]], ptr [[TMP21]], i32 [[TMP27]], ptr [[TMP28]], ptr [[TMP29]], i64 [[TMP33]], i32 1, i32 2, i64 [[TMP34]], ptr @.omp_task_dup.)1249// CHECK2-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP4]])1250// CHECK2-NEXT: call void @__kmpc_end_master(ptr @[[GLOB1]], i32 [[TMP4]])1251// CHECK2-NEXT: br label [[OMP_IF_END]]1252// CHECK2: omp_if.end:1253// CHECK2-NEXT: ret void1254//1255//1256// CHECK2-LABEL: define {{[^@]+}}@.omp_task_privates_map.1257// CHECK2-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] {1258// CHECK2-NEXT: entry:1259// CHECK2-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 81260// CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 81261// CHECK2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 81262// CHECK2-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 81263// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 81264// CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP2]], i32 0, i32 01265// CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR1]], align 81266// CHECK2-NEXT: store ptr [[TMP3]], ptr [[TMP4]], align 81267// CHECK2-NEXT: ret void1268//1269//1270// CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..61271// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR4]] {1272// CHECK2-NEXT: entry:1273// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 41274// CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 81275// CHECK2-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 81276// CHECK2-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 81277// CHECK2-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 81278// CHECK2-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 81279// CHECK2-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 81280// CHECK2-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 81281// CHECK2-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 41282// CHECK2-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 81283// CHECK2-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 81284// CHECK2-NEXT: [[DOTLASTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 81285// CHECK2-NEXT: [[DOTCAPTURE_EXPR__I:%.*]] = alloca i32, align 41286// CHECK2-NEXT: [[DOTCAPTURE_EXPR_2_I:%.*]] = alloca i32, align 41287// CHECK2-NEXT: [[DOTCAPTURE_EXPR_3_I:%.*]] = alloca i32, align 41288// CHECK2-NEXT: [[DOTCAPTURE_EXPR_6_I:%.*]] = alloca i64, align 81289// CHECK2-NEXT: [[I_I:%.*]] = alloca i32, align 41290// CHECK2-NEXT: [[J_I:%.*]] = alloca i32, align 41291// CHECK2-NEXT: [[I14_I:%.*]] = alloca i32, align 41292// CHECK2-NEXT: [[J15_I:%.*]] = alloca i32, align 41293// CHECK2-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i64, align 81294// CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i32, align 41295// CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 81296// CHECK2-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 41297// CHECK2-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 81298// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 41299// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 81300// CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], ptr [[TMP3]], i32 0, i32 01301// CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 21302// CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 01303// CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 81304// CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3]], ptr [[TMP3]], i32 0, i32 11305// CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 51306// CHECK2-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP9]], align 81307// CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 61308// CHECK2-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP11]], align 81309// CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 71310// CHECK2-NEXT: [[TMP14:%.*]] = load i64, ptr [[TMP13]], align 81311// CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 81312// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 81313// CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 91314// CHECK2-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 81315// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META39:![0-9]+]])1316// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META42:![0-9]+]])1317// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META44:![0-9]+]])1318// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META46:![0-9]+]])1319// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META48:![0-9]+]])1320// CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META50:![0-9]+]]1321// CHECK2-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META50]]1322// CHECK2-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META50]]1323// CHECK2-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META50]]1324// CHECK2-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META50]]1325// CHECK2-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META50]]1326// CHECK2-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META50]]1327// CHECK2-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META50]]1328// CHECK2-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META50]]1329// CHECK2-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META50]]1330// CHECK2-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META50]]1331// CHECK2-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META50]]1332// CHECK2-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META50]]1333// CHECK2-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META50]]1334// CHECK2-NEXT: call void [[TMP20]](ptr [[TMP21]], ptr [[DOTLASTPRIV_PTR_ADDR_I]]) #[[ATTR2]]1335// CHECK2-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP19]], align 8, !nonnull [[META36]], !align [[META37]]1336// CHECK2-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias [[META50]]1337// CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2:%.*]], ptr [[TMP19]], i32 0, i32 11338// CHECK2-NEXT: [[TMP25:%.*]] = load ptr, ptr [[TMP24]], align 8, !nonnull [[META36]], !align [[META37]]1339// CHECK2-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 41340// CHECK2-NEXT: store i32 [[TMP26]], ptr [[DOTCAPTURE_EXPR__I]], align 4, !noalias [[META50]]1341// CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[TMP19]], i32 0, i32 11342// CHECK2-NEXT: [[TMP28:%.*]] = load ptr, ptr [[TMP27]], align 8, !nonnull [[META36]], !align [[META37]]1343// CHECK2-NEXT: [[TMP29:%.*]] = load i32, ptr [[TMP28]], align 41344// CHECK2-NEXT: store i32 [[TMP29]], ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META50]]1345// CHECK2-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[TMP19]], i32 0, i32 21346// CHECK2-NEXT: [[TMP31:%.*]] = load ptr, ptr [[TMP30]], align 8, !nonnull [[META36]], !align [[META38]]1347// CHECK2-NEXT: [[TMP32:%.*]] = load ptr, ptr [[TMP31]], align 81348// CHECK2-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[TMP19]], i32 0, i32 11349// CHECK2-NEXT: [[TMP34:%.*]] = load ptr, ptr [[TMP33]], align 8, !nonnull [[META36]], !align [[META37]]1350// CHECK2-NEXT: [[TMP35:%.*]] = load i32, ptr [[TMP34]], align 41351// CHECK2-NEXT: [[IDXPROM_I:%.*]] = sext i32 [[TMP35]] to i641352// CHECK2-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds ptr, ptr [[TMP32]], i64 [[IDXPROM_I]]1353// CHECK2-NEXT: [[TMP36:%.*]] = load ptr, ptr [[ARRAYIDX_I]], align 81354// CHECK2-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[TMP19]], i32 0, i32 11355// CHECK2-NEXT: [[TMP38:%.*]] = load ptr, ptr [[TMP37]], align 8, !nonnull [[META36]], !align [[META37]]1356// CHECK2-NEXT: [[TMP39:%.*]] = load i32, ptr [[TMP38]], align 41357// CHECK2-NEXT: [[IDXPROM4_I:%.*]] = sext i32 [[TMP39]] to i641358// CHECK2-NEXT: [[ARRAYIDX5_I:%.*]] = getelementptr inbounds i8, ptr [[TMP36]], i64 [[IDXPROM4_I]]1359// CHECK2-NEXT: [[TMP40:%.*]] = load i8, ptr [[ARRAYIDX5_I]], align 11360// CHECK2-NEXT: [[CONV_I:%.*]] = sext i8 [[TMP40]] to i321361// CHECK2-NEXT: store i32 [[CONV_I]], ptr [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias [[META50]]1362// CHECK2-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__I]], align 4, !noalias [[META50]]1363// CHECK2-NEXT: [[CONV7_I:%.*]] = sext i32 [[TMP41]] to i641364// CHECK2-NEXT: [[TMP42:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias [[META50]]1365// CHECK2-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META50]]1366// CHECK2-NEXT: [[SUB8_I:%.*]] = sub i32 [[TMP42]], [[TMP43]]1367// CHECK2-NEXT: [[SUB9_I:%.*]] = sub i32 [[SUB8_I]], 11368// CHECK2-NEXT: [[CONV11_I:%.*]] = zext i32 [[SUB8_I]] to i641369// CHECK2-NEXT: [[MUL_I:%.*]] = mul nsw i64 [[CONV7_I]], [[CONV11_I]]1370// CHECK2-NEXT: [[SUB12_I:%.*]] = sub nsw i64 [[MUL_I]], 11371// CHECK2-NEXT: store i64 [[SUB12_I]], ptr [[DOTCAPTURE_EXPR_6_I]], align 8, !noalias [[META50]]1372// CHECK2-NEXT: store i32 0, ptr [[I_I]], align 4, !noalias [[META50]]1373// CHECK2-NEXT: [[TMP44:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META50]]1374// CHECK2-NEXT: store i32 [[TMP44]], ptr [[J_I]], align 4, !noalias [[META50]]1375// CHECK2-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__I]], align 4, !noalias [[META50]]1376// CHECK2-NEXT: [[CMP_I:%.*]] = icmp slt i32 0, [[TMP45]]1377// CHECK2-NEXT: br i1 [[CMP_I]], label [[LAND_LHS_TRUE_I:%.*]], label [[TASKLOOP_IF_END_I:%.*]]1378// CHECK2: land.lhs.true.i:1379// CHECK2-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META50]]1380// CHECK2-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias [[META50]]1381// CHECK2-NEXT: [[CMP13_I:%.*]] = icmp slt i32 [[TMP46]], [[TMP47]]1382// CHECK2-NEXT: br i1 [[CMP13_I]], label [[TASKLOOP_IF_THEN_I:%.*]], label [[TASKLOOP_IF_END_I]]1383// CHECK2: taskloop.if.then.i:1384// CHECK2-NEXT: [[TMP48:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META50]]1385// CHECK2-NEXT: store i64 [[TMP48]], ptr [[DOTOMP_IV_I]], align 8, !noalias [[META50]]1386// CHECK2-NEXT: [[TMP49:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[TMP19]], i32 0, i32 11387// CHECK2-NEXT: [[TMP50:%.*]] = load ptr, ptr [[TMP49]], align 8, !nonnull [[META36]], !align [[META37]]1388// CHECK2-NEXT: [[TMP51:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[TMP19]], i32 0, i32 21389// CHECK2-NEXT: [[TMP52:%.*]] = load ptr, ptr [[TMP51]], align 8, !nonnull [[META36]], !align [[META38]]1390// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]1391// CHECK2: omp.inner.for.cond.i:1392// CHECK2-NEXT: [[TMP53:%.*]] = load i64, ptr [[DOTOMP_IV_I]], align 8, !noalias [[META50]], !llvm.access.group [[ACC_GRP51:![0-9]+]]1393// CHECK2-NEXT: [[TMP54:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META50]], !llvm.access.group [[ACC_GRP51]]1394// CHECK2-NEXT: [[CMP16_I:%.*]] = icmp ule i64 [[TMP53]], [[TMP54]]1395// CHECK2-NEXT: br i1 [[CMP16_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[OMP_INNER_FOR_END_I:%.*]]1396// CHECK2: omp.inner.for.body.i:1397// CHECK2-NEXT: [[TMP55:%.*]] = load i64, ptr [[DOTOMP_IV_I]], align 8, !noalias [[META50]], !llvm.access.group [[ACC_GRP51]]1398// CHECK2-NEXT: [[TMP56:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias [[META50]], !llvm.access.group [[ACC_GRP51]]1399// CHECK2-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META50]], !llvm.access.group [[ACC_GRP51]]1400// CHECK2-NEXT: [[SUB17_I:%.*]] = sub i32 [[TMP56]], [[TMP57]]1401// CHECK2-NEXT: [[SUB18_I:%.*]] = sub i32 [[SUB17_I]], 11402// CHECK2-NEXT: [[CONV22_I:%.*]] = zext i32 [[SUB17_I]] to i641403// CHECK2-NEXT: [[DIV23_I:%.*]] = sdiv i64 [[TMP55]], [[CONV22_I]]1404// CHECK2-NEXT: [[CONV26_I:%.*]] = trunc i64 [[DIV23_I]] to i321405// CHECK2-NEXT: store i32 [[CONV26_I]], ptr [[I14_I]], align 4, !noalias [[META50]], !llvm.access.group [[ACC_GRP51]]1406// CHECK2-NEXT: [[TMP58:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META50]], !llvm.access.group [[ACC_GRP51]]1407// CHECK2-NEXT: [[CONV27_I:%.*]] = sext i32 [[TMP58]] to i641408// CHECK2-NEXT: [[TMP59:%.*]] = load i64, ptr [[DOTOMP_IV_I]], align 8, !noalias [[META50]], !llvm.access.group [[ACC_GRP51]]1409// CHECK2-NEXT: [[TMP60:%.*]] = load i64, ptr [[DOTOMP_IV_I]], align 8, !noalias [[META50]], !llvm.access.group [[ACC_GRP51]]1410// CHECK2-NEXT: [[TMP61:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias [[META50]], !llvm.access.group [[ACC_GRP51]]1411// CHECK2-NEXT: [[TMP62:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META50]], !llvm.access.group [[ACC_GRP51]]1412// CHECK2-NEXT: [[SUB28_I:%.*]] = sub i32 [[TMP61]], [[TMP62]]1413// CHECK2-NEXT: [[SUB29_I:%.*]] = sub i32 [[SUB28_I]], 11414// CHECK2-NEXT: [[CONV33_I:%.*]] = zext i32 [[SUB28_I]] to i641415// CHECK2-NEXT: [[DIV34_I:%.*]] = sdiv i64 [[TMP60]], [[CONV33_I]]1416// CHECK2-NEXT: [[TMP63:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias [[META50]], !llvm.access.group [[ACC_GRP51]]1417// CHECK2-NEXT: [[TMP64:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META50]], !llvm.access.group [[ACC_GRP51]]1418// CHECK2-NEXT: [[SUB35_I:%.*]] = sub i32 [[TMP63]], [[TMP64]]1419// CHECK2-NEXT: [[SUB36_I:%.*]] = sub i32 [[SUB35_I]], 11420// CHECK2-NEXT: [[CONV40_I:%.*]] = zext i32 [[SUB35_I]] to i641421// CHECK2-NEXT: [[MUL41_I:%.*]] = mul nsw i64 [[DIV34_I]], [[CONV40_I]]1422// CHECK2-NEXT: [[SUB42_I:%.*]] = sub nsw i64 [[TMP59]], [[MUL41_I]]1423// CHECK2-NEXT: [[ADD44_I:%.*]] = add nsw i64 [[CONV27_I]], [[SUB42_I]]1424// CHECK2-NEXT: [[CONV45_I:%.*]] = trunc i64 [[ADD44_I]] to i321425// CHECK2-NEXT: store i32 [[CONV45_I]], ptr [[J15_I]], align 4, !noalias [[META50]], !llvm.access.group [[ACC_GRP51]]1426// CHECK2-NEXT: [[TMP65:%.*]] = load i64, ptr [[DOTOMP_IV_I]], align 8, !noalias [[META50]], !llvm.access.group [[ACC_GRP51]]1427// CHECK2-NEXT: [[ADD46_I:%.*]] = add nsw i64 [[TMP65]], 11428// CHECK2-NEXT: store i64 [[ADD46_I]], ptr [[DOTOMP_IV_I]], align 8, !noalias [[META50]], !llvm.access.group [[ACC_GRP51]]1429// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP52:![0-9]+]]1430// CHECK2: omp.inner.for.end.i:1431// CHECK2-NEXT: br label [[TASKLOOP_IF_END_I]]1432// CHECK2: taskloop.if.end.i:1433// CHECK2-NEXT: [[TMP66:%.*]] = load i32, ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META50]]1434// CHECK2-NEXT: [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 01435// CHECK2-NEXT: br i1 [[TMP67]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.*]], label [[DOTOMP_OUTLINED__5_EXIT:%.*]]1436// CHECK2: .omp.lastprivate.then.i:1437// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__5_EXIT]]1438// CHECK2: .omp_outlined..5.exit:1439// CHECK2-NEXT: ret i32 01440//1441//1442// CHECK2-LABEL: define {{[^@]+}}@.omp_task_dup.1443// CHECK2-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], i32 noundef [[TMP2:%.*]]) #[[ATTR4]] {1444// CHECK2-NEXT: entry:1445// CHECK2-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 81446// CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 81447// CHECK2-NEXT: [[DOTADDR2:%.*]] = alloca i32, align 41448// CHECK2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 81449// CHECK2-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 81450// CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTADDR2]], align 41451// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR]], align 81452// CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], ptr [[TMP3]], i32 0, i32 01453// CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 81454// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTADDR2]], align 41455// CHECK2-NEXT: store i32 [[TMP6]], ptr [[TMP5]], align 81456// CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3]], ptr [[TMP3]], i32 0, i32 11457// CHECK2-NEXT: ret void1458//1459//1460// CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init1461// CHECK2-SAME: () #[[ATTR6]] section "__TEXT,__StaticInit,regular,pure_instructions" {1462// CHECK2-NEXT: entry:1463// CHECK2-NEXT: call void @_ZN1SC1Ei(ptr noundef nonnull align 4 dereferenceable(4) @s, i32 noundef 1)1464// CHECK2-NEXT: ret void1465//1466//1467// CHECK2-LABEL: define {{[^@]+}}@_ZN1SC1Ei1468// CHECK2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] align 2 {1469// CHECK2-NEXT: entry:1470// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81471// CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i32, align 41472// CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81473// CHECK2-NEXT: store i32 [[C]], ptr [[C_ADDR]], align 41474// CHECK2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81475// CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[C_ADDR]], align 41476// CHECK2-NEXT: call void @_ZN1SC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])1477// CHECK2-NEXT: ret void1478//1479//1480// CHECK2-LABEL: define {{[^@]+}}@_ZN1SC2Ei1481// CHECK2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR8]] align 2 {1482// CHECK2-NEXT: entry:1483// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81484// CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i32, align 41485// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 11486// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 81487// CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81488// CHECK2-NEXT: store i32 [[C]], ptr [[C_ADDR]], align 41489// CHECK2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81490// CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[C_ADDR]], align 41491// CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 01492// CHECK2-NEXT: [[STOREDV:%.*]] = zext i1 [[TOBOOL]] to i81493// CHECK2-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_]], align 11494// CHECK2-NEXT: [[TMP1:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 11495// CHECK2-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP1]] to i11496// CHECK2-NEXT: [[STOREDV2:%.*]] = zext i1 [[LOADEDV]] to i81497// CHECK2-NEXT: store i8 [[STOREDV2]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 11498// CHECK2-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 81499// CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 3, ptr @_ZN1SC2Ei.omp_outlined, ptr [[THIS1]], ptr [[C_ADDR]], i64 [[TMP2]])1500// CHECK2-NEXT: ret void1501//1502//1503// CHECK2-LABEL: define {{[^@]+}}@_ZN1SC2Ei.omp_outlined1504// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {1505// CHECK2-NEXT: entry:1506// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81507// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81508// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81509// CHECK2-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 81510// CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 81511// CHECK2-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_4:%.*]], align 81512// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 41513// CHECK2-NEXT: [[_TMP1:%.*]] = alloca ptr, align 81514// CHECK2-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 41515// CHECK2-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 41516// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81517// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81518// CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81519// CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 81520// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 81521// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81522// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META36]], !align [[META37]]1523// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81524// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 41525// CHECK2-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP3]])1526// CHECK2-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 01527// CHECK2-NEXT: br i1 [[TMP5]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]1528// CHECK2: omp_if.then:1529// CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_4]], ptr [[AGG_CAPTURED]], i32 0, i32 01530// CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP6]], align 81531// CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_4]], ptr [[AGG_CAPTURED]], i32 0, i32 11532// CHECK2-NEXT: store ptr [[TMP1]], ptr [[TMP7]], align 81533// CHECK2-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP3]])1534// CHECK2-NEXT: [[TMP8:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 11535// CHECK2-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP8]] to i11536// CHECK2-NEXT: store ptr [[TMP]], ptr [[_TMP1]], align 81537// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP1]], align 41538// CHECK2-NEXT: store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR_2]], align 41539// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 41540// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP10]], 01541// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 11542// CHECK2-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 11543// CHECK2-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_3]], align 41544// CHECK2-NEXT: [[TMP11:%.*]] = select i1 [[LOADEDV]], i32 2, i32 01545// CHECK2-NEXT: [[TMP12:%.*]] = or i32 [[TMP11]], 11546// CHECK2-NEXT: [[TMP13:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP3]], i32 [[TMP12]], i64 80, i64 16, ptr @.omp_task_entry..8)1547// CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.*]], ptr [[TMP13]], i32 0, i32 01548// CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP14]], i32 0, i32 01549// CHECK2-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 81550// CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP16]], ptr align 8 [[AGG_CAPTURED]], i64 16, i1 false)1551// CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP14]], i32 0, i32 51552// CHECK2-NEXT: store i64 0, ptr [[TMP17]], align 81553// CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP14]], i32 0, i32 61554// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 41555// CHECK2-NEXT: [[CONV:%.*]] = sext i32 [[TMP19]] to i641556// CHECK2-NEXT: store i64 [[CONV]], ptr [[TMP18]], align 81557// CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP14]], i32 0, i32 71558// CHECK2-NEXT: store i64 1, ptr [[TMP20]], align 81559// CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP14]], i32 0, i32 91560// CHECK2-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP21]], i8 0, i64 8, i1 false)1561// CHECK2-NEXT: [[TMP22:%.*]] = load i64, ptr [[TMP20]], align 81562// CHECK2-NEXT: call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP3]], ptr [[TMP13]], i32 1, ptr [[TMP17]], ptr [[TMP18]], i64 [[TMP22]], i32 1, i32 2, i64 4, ptr null)1563// CHECK2-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP3]])1564// CHECK2-NEXT: call void @__kmpc_end_master(ptr @[[GLOB1]], i32 [[TMP3]])1565// CHECK2-NEXT: br label [[OMP_IF_END]]1566// CHECK2: omp_if.end:1567// CHECK2-NEXT: ret void1568//1569//1570// CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..81571// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR4]] {1572// CHECK2-NEXT: entry:1573// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 41574// CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 81575// CHECK2-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 81576// CHECK2-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 81577// CHECK2-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 81578// CHECK2-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 81579// CHECK2-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 81580// CHECK2-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 81581// CHECK2-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 41582// CHECK2-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 81583// CHECK2-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 81584// CHECK2-NEXT: [[TMP_I:%.*]] = alloca i32, align 41585// CHECK2-NEXT: [[TMP1_I:%.*]] = alloca ptr, align 81586// CHECK2-NEXT: [[DOTCAPTURE_EXPR__I:%.*]] = alloca i32, align 41587// CHECK2-NEXT: [[DOTCAPTURE_EXPR_2_I:%.*]] = alloca i32, align 41588// CHECK2-NEXT: [[A_I:%.*]] = alloca i32, align 41589// CHECK2-NEXT: [[TMP4_I:%.*]] = alloca ptr, align 81590// CHECK2-NEXT: [[A5_I:%.*]] = alloca i32, align 41591// CHECK2-NEXT: [[TMP6_I:%.*]] = alloca ptr, align 81592// CHECK2-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 41593// CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i32, align 41594// CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 81595// CHECK2-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 41596// CHECK2-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 81597// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 41598// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 81599// CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.*]], ptr [[TMP3]], i32 0, i32 01600// CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 21601// CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 01602// CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 81603// CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 51604// CHECK2-NEXT: [[TMP9:%.*]] = load i64, ptr [[TMP8]], align 81605// CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 61606// CHECK2-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 81607// CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 71608// CHECK2-NEXT: [[TMP13:%.*]] = load i64, ptr [[TMP12]], align 81609// CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 81610// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 81611// CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 91612// CHECK2-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 81613// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META54:![0-9]+]])1614// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META57:![0-9]+]])1615// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META59:![0-9]+]])1616// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META61:![0-9]+]])1617// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META63:![0-9]+]])1618// CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META65:![0-9]+]]1619// CHECK2-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META65]]1620// CHECK2-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META65]]1621// CHECK2-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META65]]1622// CHECK2-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META65]]1623// CHECK2-NEXT: store i64 [[TMP9]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META65]]1624// CHECK2-NEXT: store i64 [[TMP11]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META65]]1625// CHECK2-NEXT: store i64 [[TMP13]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META65]]1626// CHECK2-NEXT: store i32 [[TMP15]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META65]]1627// CHECK2-NEXT: store ptr [[TMP17]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META65]]1628// CHECK2-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META65]]1629// CHECK2-NEXT: [[TMP18:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META65]]1630// CHECK2-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP18]], align 81631// CHECK2-NEXT: store ptr [[TMP_I]], ptr [[TMP1_I]], align 8, !noalias [[META65]]1632// CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_4:%.*]], ptr [[TMP18]], i32 0, i32 11633// CHECK2-NEXT: [[TMP21:%.*]] = load ptr, ptr [[TMP20]], align 8, !nonnull [[META36]], !align [[META37]]1634// CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 41635// CHECK2-NEXT: store i32 [[TMP22]], ptr [[DOTCAPTURE_EXPR__I]], align 4, !noalias [[META65]]1636// CHECK2-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__I]], align 4, !noalias [[META65]]1637// CHECK2-NEXT: [[SUB3_I:%.*]] = sub nsw i32 [[TMP23]], 11638// CHECK2-NEXT: store i32 [[SUB3_I]], ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META65]]1639// CHECK2-NEXT: store ptr [[A_I]], ptr [[TMP4_I]], align 8, !noalias [[META65]]1640// CHECK2-NEXT: [[TMP24:%.*]] = load ptr, ptr [[TMP4_I]], align 8, !noalias [[META65]], !nonnull [[META36]], !align [[META37]]1641// CHECK2-NEXT: store i32 0, ptr [[TMP24]], align 41642// CHECK2-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__I]], align 4, !noalias [[META65]]1643// CHECK2-NEXT: [[CMP_I:%.*]] = icmp slt i32 0, [[TMP25]]1644// CHECK2-NEXT: br i1 [[CMP_I]], label [[TASKLOOP_IF_THEN_I:%.*]], label [[DOTOMP_OUTLINED__7_EXIT:%.*]]1645// CHECK2: taskloop.if.then.i:1646// CHECK2-NEXT: store ptr [[A5_I]], ptr [[TMP6_I]], align 8, !noalias [[META65]]1647// CHECK2-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META65]]1648// CHECK2-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP26]] to i321649// CHECK2-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META65]]1650// CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_4]], ptr [[TMP18]], i32 0, i32 11651// CHECK2-NEXT: [[TMP28:%.*]] = load ptr, ptr [[TMP27]], align 8, !nonnull [[META36]], !align [[META37]]1652// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]1653// CHECK2: omp.inner.for.cond.i:1654// CHECK2-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META65]], !llvm.access.group [[ACC_GRP66:![0-9]+]]1655// CHECK2-NEXT: [[CONV7_I:%.*]] = sext i32 [[TMP29]] to i641656// CHECK2-NEXT: [[TMP30:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META65]], !llvm.access.group [[ACC_GRP66]]1657// CHECK2-NEXT: [[CMP8_I:%.*]] = icmp ule i64 [[CONV7_I]], [[TMP30]]1658// CHECK2-NEXT: br i1 [[CMP8_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[OMP_INNER_FOR_END_I:%.*]]1659// CHECK2: omp.inner.for.body.i:1660// CHECK2-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META65]], !llvm.access.group [[ACC_GRP66]]1661// CHECK2-NEXT: [[TMP32:%.*]] = load ptr, ptr [[TMP6_I]], align 8, !noalias [[META65]], !nonnull [[META36]], !align [[META37]], !llvm.access.group [[ACC_GRP66]]1662// CHECK2-NEXT: store i32 [[TMP31]], ptr [[TMP32]], align 4, !llvm.access.group [[ACC_GRP66]]1663// CHECK2-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META65]], !llvm.access.group [[ACC_GRP66]]1664// CHECK2-NEXT: [[ADD9_I:%.*]] = add nsw i32 [[TMP33]], 11665// CHECK2-NEXT: store i32 [[ADD9_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META65]], !llvm.access.group [[ACC_GRP66]]1666// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP67:![0-9]+]]1667// CHECK2: omp.inner.for.end.i:1668// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__7_EXIT]]1669// CHECK2: .omp_outlined..7.exit:1670// CHECK2-NEXT: ret i32 01671//1672//1673// CHECK2-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_parallel_master_taskloop_simd_codegen.cpp1674// CHECK2-SAME: () #[[ATTR6]] section "__TEXT,__StaticInit,regular,pure_instructions" {1675// CHECK2-NEXT: entry:1676// CHECK2-NEXT: call void @__cxx_global_var_init()1677// CHECK2-NEXT: ret void1678//1679//1680// CHECK3-LABEL: define {{[^@]+}}@main1681// CHECK3-SAME: (i32 noundef [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {1682// CHECK3-NEXT: entry:1683// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 41684// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 41685// CHECK3-NEXT: [[ARGV_ADDR:%.*]] = alloca ptr, align 81686// CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 41687// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 81688// CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 41689// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i64, align 81690// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 41691// CHECK3-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i8, align 11692// CHECK3-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 41693// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED5:%.*]] = alloca i64, align 81694// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED7:%.*]] = alloca i64, align 81695// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 41696// CHECK3-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 41697// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])1698// CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 41699// CHECK3-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 41700// CHECK3-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 81701// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARGC_ADDR]], align 41702// CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 41703// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41704// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 41705// CHECK3-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 81706// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @main.omp_outlined, i64 [[TMP3]])1707// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARGC_ADDR]], align 41708// CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_1]], align 41709// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 41710// CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR__CASTED2]], align 41711// CHECK3-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED2]], align 81712// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @main.omp_outlined.1, i64 [[TMP6]])1713// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARGC_ADDR]], align 41714// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 01715// CHECK3-NEXT: [[STOREDV:%.*]] = zext i1 [[TOBOOL]] to i81716// CHECK3-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_3]], align 11717// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[ARGC_ADDR]], align 41718// CHECK3-NEXT: store i32 [[TMP8]], ptr [[DOTCAPTURE_EXPR_4]], align 41719// CHECK3-NEXT: [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_3]], align 11720// CHECK3-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP9]] to i11721// CHECK3-NEXT: [[STOREDV6:%.*]] = zext i1 [[LOADEDV]] to i81722// CHECK3-NEXT: store i8 [[STOREDV6]], ptr [[DOTCAPTURE_EXPR__CASTED5]], align 11723// CHECK3-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED5]], align 81724// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 41725// CHECK3-NEXT: store i32 [[TMP11]], ptr [[DOTCAPTURE_EXPR__CASTED7]], align 41726// CHECK3-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED7]], align 81727// CHECK3-NEXT: [[TMP13:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_3]], align 11728// CHECK3-NEXT: [[LOADEDV8:%.*]] = trunc i8 [[TMP13]] to i11729// CHECK3-NEXT: br i1 [[LOADEDV8]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]1730// CHECK3: omp_if.then:1731// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @main.omp_outlined.4, ptr [[I]], ptr [[ARGC_ADDR]], ptr [[ARGV_ADDR]], i64 [[TMP10]], i64 [[TMP12]])1732// CHECK3-NEXT: br label [[OMP_IF_END:%.*]]1733// CHECK3: omp_if.else:1734// CHECK3-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])1735// CHECK3-NEXT: store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 41736// CHECK3-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 41737// CHECK3-NEXT: call void @main.omp_outlined.4(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[I]], ptr [[ARGC_ADDR]], ptr [[ARGV_ADDR]], i64 [[TMP10]], i64 [[TMP12]]) #[[ATTR2:[0-9]+]]1738// CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])1739// CHECK3-NEXT: br label [[OMP_IF_END]]1740// CHECK3: omp_if.end:1741// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 41742// CHECK3-NEXT: ret i32 [[TMP14]]1743//1744//1745// CHECK3-LABEL: define {{[^@]+}}@main.omp_outlined1746// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] {1747// CHECK3-NEXT: entry:1748// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81749// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81750// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 81751// CHECK3-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 11752// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 41753// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81754// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81755// CHECK3-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 81756// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81757// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 41758// CHECK3-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP1]])1759// CHECK3-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 01760// CHECK3-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]1761// CHECK3: omp_if.then:1762// CHECK3-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP1]])1763// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 41764// CHECK3-NEXT: [[TMP5:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP1]], i32 33, i64 80, i64 1, ptr @.omp_task_entry.)1765// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP5]], i32 0, i32 01766// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP6]], i32 0, i32 41767// CHECK3-NEXT: store i32 [[TMP4]], ptr [[TMP7]], align 81768// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP6]], i32 0, i32 51769// CHECK3-NEXT: store i64 0, ptr [[TMP8]], align 81770// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP6]], i32 0, i32 61771// CHECK3-NEXT: store i64 9, ptr [[TMP9]], align 81772// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP6]], i32 0, i32 71773// CHECK3-NEXT: store i64 1, ptr [[TMP10]], align 81774// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP6]], i32 0, i32 91775// CHECK3-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP11]], i8 0, i64 8, i1 false)1776// CHECK3-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP10]], align 81777// CHECK3-NEXT: call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP1]], ptr [[TMP5]], i32 1, ptr [[TMP8]], ptr [[TMP9]], i64 [[TMP12]], i32 1, i32 0, i64 0, ptr null)1778// CHECK3-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP1]])1779// CHECK3-NEXT: call void @__kmpc_end_master(ptr @[[GLOB1]], i32 [[TMP1]])1780// CHECK3-NEXT: br label [[OMP_IF_END]]1781// CHECK3: omp_if.end:1782// CHECK3-NEXT: ret void1783//1784//1785// CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry.1786// CHECK3-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] {1787// CHECK3-NEXT: entry:1788// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 41789// CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 81790// CHECK3-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 81791// CHECK3-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 81792// CHECK3-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 81793// CHECK3-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 81794// CHECK3-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 81795// CHECK3-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 81796// CHECK3-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 41797// CHECK3-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 81798// CHECK3-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 81799// CHECK3-NEXT: [[I_I:%.*]] = alloca i32, align 41800// CHECK3-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 41801// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i32, align 41802// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 81803// CHECK3-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 41804// CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 81805// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 41806// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 81807// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 01808// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 21809// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 01810// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 81811// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 51812// CHECK3-NEXT: [[TMP9:%.*]] = load i64, ptr [[TMP8]], align 81813// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 61814// CHECK3-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 81815// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 71816// CHECK3-NEXT: [[TMP13:%.*]] = load i64, ptr [[TMP12]], align 81817// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 81818// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 81819// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 91820// CHECK3-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 81821// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])1822// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])1823// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])1824// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])1825// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])1826// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META14:![0-9]+]]1827// CHECK3-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META14]]1828// CHECK3-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]]1829// CHECK3-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]]1830// CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META14]]1831// CHECK3-NEXT: store i64 [[TMP9]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]]1832// CHECK3-NEXT: store i64 [[TMP11]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]]1833// CHECK3-NEXT: store i64 [[TMP13]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META14]]1834// CHECK3-NEXT: store i32 [[TMP15]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META14]]1835// CHECK3-NEXT: store ptr [[TMP17]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META14]]1836// CHECK3-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]]1837// CHECK3-NEXT: [[TMP18:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]]1838// CHECK3-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]]1839// CHECK3-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP19]] to i321840// CHECK3-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]]1841// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]1842// CHECK3: omp.inner.for.cond.i:1843// CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]]1844// CHECK3-NEXT: [[CONV1_I:%.*]] = sext i32 [[TMP20]] to i641845// CHECK3-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]]1846// CHECK3-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV1_I]], [[TMP21]]1847// CHECK3-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]]1848// CHECK3: omp.inner.for.body.i:1849// CHECK3-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]]1850// CHECK3-NEXT: store i32 [[TMP22]], ptr [[I_I]], align 4, !noalias [[META14]]1851// CHECK3-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]]1852// CHECK3-NEXT: [[ADD2_I:%.*]] = add nsw i32 [[TMP23]], 11853// CHECK3-NEXT: store i32 [[ADD2_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]]1854// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP15:![0-9]+]]1855// CHECK3: .omp_outlined..exit:1856// CHECK3-NEXT: ret i32 01857//1858//1859// CHECK3-LABEL: define {{[^@]+}}@main.omp_outlined.11860// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {1861// CHECK3-NEXT: entry:1862// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81863// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81864// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 81865// CHECK3-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_0:%.*]], align 11866// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 41867// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81868// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81869// CHECK3-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 81870// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81871// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 41872// CHECK3-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP1]])1873// CHECK3-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 01874// CHECK3-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]1875// CHECK3: omp_if.then:1876// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 41877// CHECK3-NEXT: [[TMP5:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i64 80, i64 1, ptr @.omp_task_entry..3)1878// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.*]], ptr [[TMP5]], i32 0, i32 01879// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP6]], i32 0, i32 51880// CHECK3-NEXT: store i64 0, ptr [[TMP7]], align 81881// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP6]], i32 0, i32 61882// CHECK3-NEXT: store i64 9, ptr [[TMP8]], align 81883// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP6]], i32 0, i32 71884// CHECK3-NEXT: store i64 1, ptr [[TMP9]], align 81885// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP6]], i32 0, i32 91886// CHECK3-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP10]], i8 0, i64 8, i1 false)1887// CHECK3-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP9]], align 81888// CHECK3-NEXT: [[TMP12:%.*]] = zext i32 [[TMP4]] to i641889// CHECK3-NEXT: call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP1]], ptr [[TMP5]], i32 1, ptr [[TMP7]], ptr [[TMP8]], i64 [[TMP11]], i32 1, i32 1, i64 [[TMP12]], ptr null)1890// CHECK3-NEXT: call void @__kmpc_end_master(ptr @[[GLOB1]], i32 [[TMP1]])1891// CHECK3-NEXT: br label [[OMP_IF_END]]1892// CHECK3: omp_if.end:1893// CHECK3-NEXT: ret void1894//1895//1896// CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry..31897// CHECK3-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR4]] {1898// CHECK3-NEXT: entry:1899// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 41900// CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 81901// CHECK3-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 81902// CHECK3-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 81903// CHECK3-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 81904// CHECK3-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 81905// CHECK3-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 81906// CHECK3-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 81907// CHECK3-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 41908// CHECK3-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 81909// CHECK3-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 81910// CHECK3-NEXT: [[I_I:%.*]] = alloca i32, align 41911// CHECK3-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 41912// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i32, align 41913// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 81914// CHECK3-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 41915// CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 81916// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 41917// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 81918// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.*]], ptr [[TMP3]], i32 0, i32 01919// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 21920// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 01921// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 81922// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 51923// CHECK3-NEXT: [[TMP9:%.*]] = load i64, ptr [[TMP8]], align 81924// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 61925// CHECK3-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 81926// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 71927// CHECK3-NEXT: [[TMP13:%.*]] = load i64, ptr [[TMP12]], align 81928// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 81929// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 81930// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 91931// CHECK3-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 81932// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])1933// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])1934// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]])1935// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META27:![0-9]+]])1936// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META29:![0-9]+]])1937// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META31:![0-9]+]]1938// CHECK3-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META31]]1939// CHECK3-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META31]]1940// CHECK3-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META31]]1941// CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META31]]1942// CHECK3-NEXT: store i64 [[TMP9]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META31]]1943// CHECK3-NEXT: store i64 [[TMP11]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META31]]1944// CHECK3-NEXT: store i64 [[TMP13]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META31]]1945// CHECK3-NEXT: store i32 [[TMP15]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META31]]1946// CHECK3-NEXT: store ptr [[TMP17]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META31]]1947// CHECK3-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META31]]1948// CHECK3-NEXT: [[TMP18:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META31]]1949// CHECK3-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META31]]1950// CHECK3-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP19]] to i321951// CHECK3-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META31]]1952// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]1953// CHECK3: omp.inner.for.cond.i:1954// CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META31]], !llvm.access.group [[ACC_GRP32:![0-9]+]]1955// CHECK3-NEXT: [[CONV1_I:%.*]] = sext i32 [[TMP20]] to i641956// CHECK3-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META31]], !llvm.access.group [[ACC_GRP32]]1957// CHECK3-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV1_I]], [[TMP21]]1958// CHECK3-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__2_EXIT:%.*]]1959// CHECK3: omp.inner.for.body.i:1960// CHECK3-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META31]], !llvm.access.group [[ACC_GRP32]]1961// CHECK3-NEXT: store i32 [[TMP22]], ptr [[I_I]], align 4, !noalias [[META31]], !llvm.access.group [[ACC_GRP32]]1962// CHECK3-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META31]], !llvm.access.group [[ACC_GRP32]]1963// CHECK3-NEXT: [[ADD2_I:%.*]] = add nsw i32 [[TMP23]], 11964// CHECK3-NEXT: store i32 [[ADD2_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META31]], !llvm.access.group [[ACC_GRP32]]1965// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP33:![0-9]+]]1966// CHECK3: .omp_outlined..2.exit:1967// CHECK3-NEXT: ret i32 01968//1969//1970// CHECK3-LABEL: define {{[^@]+}}@main.omp_outlined.41971// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[ARGV:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] {1972// CHECK3-NEXT: entry:1973// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81974// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81975// CHECK3-NEXT: [[I_ADDR:%.*]] = alloca ptr, align 81976// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 81977// CHECK3-NEXT: [[ARGV_ADDR:%.*]] = alloca ptr, align 81978// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 81979// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 81980// CHECK3-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_2:%.*]], align 81981// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 41982// CHECK3-NEXT: [[_TMP3:%.*]] = alloca i32, align 41983// CHECK3-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 41984// CHECK3-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 41985// CHECK3-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i32, align 41986// CHECK3-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i64, align 81987// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81988// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81989// CHECK3-NEXT: store ptr [[I]], ptr [[I_ADDR]], align 81990// CHECK3-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 81991// CHECK3-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 81992// CHECK3-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 81993// CHECK3-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 81994// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8, !nonnull [[META36:![0-9]+]], !align [[META37:![0-9]+]]1995// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8, !nonnull [[META36]], !align [[META37]]1996// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[ARGV_ADDR]], align 8, !nonnull [[META36]], !align [[META38:![0-9]+]]1997// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81998// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 41999// CHECK3-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP4]])2000// CHECK3-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 02001// CHECK3-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]2002// CHECK3: omp_if.then:2003// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[AGG_CAPTURED]], i32 0, i32 02004// CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP7]], align 82005// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[AGG_CAPTURED]], i32 0, i32 12006// CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP8]], align 82007// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[AGG_CAPTURED]], i32 0, i32 22008// CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP9]], align 82009// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[AGG_CAPTURED]], i32 0, i32 32010// CHECK3-NEXT: [[TMP11:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 12011// CHECK3-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP11]] to i12012// CHECK3-NEXT: [[STOREDV:%.*]] = zext i1 [[LOADEDV]] to i82013// CHECK3-NEXT: store i8 [[STOREDV]], ptr [[TMP10]], align 82014// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 42015// CHECK3-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP4]])2016// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP1]], align 42017// CHECK3-NEXT: store i32 [[TMP13]], ptr [[DOTCAPTURE_EXPR_4]], align 42018// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP1]], align 42019// CHECK3-NEXT: store i32 [[TMP14]], ptr [[DOTCAPTURE_EXPR_5]], align 42020// CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP2]], align 82021// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP1]], align 42022// CHECK3-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i642023// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds ptr, ptr [[TMP15]], i64 [[IDXPROM]]2024// CHECK3-NEXT: [[TMP17:%.*]] = load ptr, ptr [[ARRAYIDX]], align 82025// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP1]], align 42026// CHECK3-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP18]] to i642027// CHECK3-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i8, ptr [[TMP17]], i64 [[IDXPROM7]]2028// CHECK3-NEXT: [[TMP19:%.*]] = load i8, ptr [[ARRAYIDX8]], align 12029// CHECK3-NEXT: [[CONV:%.*]] = sext i8 [[TMP19]] to i322030// CHECK3-NEXT: store i32 [[CONV]], ptr [[DOTCAPTURE_EXPR_6]], align 42031// CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 42032// CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP20]], 02033// CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 12034// CHECK3-NEXT: [[CONV10:%.*]] = sext i32 [[DIV]] to i642035// CHECK3-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 42036// CHECK3-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 42037// CHECK3-NEXT: [[SUB11:%.*]] = sub i32 [[TMP21]], [[TMP22]]2038// CHECK3-NEXT: [[SUB12:%.*]] = sub i32 [[SUB11]], 12039// CHECK3-NEXT: [[ADD:%.*]] = add i32 [[SUB12]], 12040// CHECK3-NEXT: [[DIV13:%.*]] = udiv i32 [[ADD]], 12041// CHECK3-NEXT: [[CONV14:%.*]] = zext i32 [[DIV13]] to i642042// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV10]], [[CONV14]]2043// CHECK3-NEXT: [[SUB15:%.*]] = sub nsw i64 [[MUL]], 12044// CHECK3-NEXT: store i64 [[SUB15]], ptr [[DOTCAPTURE_EXPR_9]], align 82045// CHECK3-NEXT: [[TMP23:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP4]], i32 1, i64 88, i64 32, ptr @.omp_task_entry..6)2046// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], ptr [[TMP23]], i32 0, i32 02047// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP24]], i32 0, i32 02048// CHECK3-NEXT: [[TMP26:%.*]] = load ptr, ptr [[TMP25]], align 82049// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP26]], ptr align 8 [[AGG_CAPTURED]], i64 32, i1 false)2050// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3]], ptr [[TMP23]], i32 0, i32 12051// CHECK3-NEXT: [[TMP28:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 12052// CHECK3-NEXT: [[LOADEDV16:%.*]] = trunc i8 [[TMP28]] to i12053// CHECK3-NEXT: [[TMP29:%.*]] = sext i1 [[LOADEDV16]] to i322054// CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP24]], i32 0, i32 52055// CHECK3-NEXT: store i64 0, ptr [[TMP30]], align 82056// CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP24]], i32 0, i32 62057// CHECK3-NEXT: [[TMP32:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_9]], align 82058// CHECK3-NEXT: store i64 [[TMP32]], ptr [[TMP31]], align 82059// CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP24]], i32 0, i32 72060// CHECK3-NEXT: store i64 1, ptr [[TMP33]], align 82061// CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP24]], i32 0, i32 92062// CHECK3-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP34]], i8 0, i64 8, i1 false)2063// CHECK3-NEXT: [[TMP35:%.*]] = load i64, ptr [[TMP33]], align 82064// CHECK3-NEXT: [[TMP36:%.*]] = zext i32 [[TMP12]] to i642065// CHECK3-NEXT: call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP4]], ptr [[TMP23]], i32 [[TMP29]], ptr [[TMP30]], ptr [[TMP31]], i64 [[TMP35]], i32 1, i32 2, i64 [[TMP36]], ptr @.omp_task_dup.)2066// CHECK3-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP4]])2067// CHECK3-NEXT: call void @__kmpc_end_master(ptr @[[GLOB1]], i32 [[TMP4]])2068// CHECK3-NEXT: br label [[OMP_IF_END]]2069// CHECK3: omp_if.end:2070// CHECK3-NEXT: ret void2071//2072//2073// CHECK3-LABEL: define {{[^@]+}}@.omp_task_privates_map.2074// CHECK3-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] {2075// CHECK3-NEXT: entry:2076// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 82077// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 82078// CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 82079// CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 82080// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 82081// CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP2]], i32 0, i32 02082// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR1]], align 82083// CHECK3-NEXT: store ptr [[TMP3]], ptr [[TMP4]], align 82084// CHECK3-NEXT: ret void2085//2086//2087// CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry..62088// CHECK3-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR4]] {2089// CHECK3-NEXT: entry:2090// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 42091// CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 82092// CHECK3-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 82093// CHECK3-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 82094// CHECK3-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 82095// CHECK3-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 82096// CHECK3-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 82097// CHECK3-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 82098// CHECK3-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 42099// CHECK3-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 82100// CHECK3-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 82101// CHECK3-NEXT: [[DOTLASTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 82102// CHECK3-NEXT: [[DOTCAPTURE_EXPR__I:%.*]] = alloca i32, align 42103// CHECK3-NEXT: [[DOTCAPTURE_EXPR_2_I:%.*]] = alloca i32, align 42104// CHECK3-NEXT: [[DOTCAPTURE_EXPR_3_I:%.*]] = alloca i32, align 42105// CHECK3-NEXT: [[DOTCAPTURE_EXPR_6_I:%.*]] = alloca i64, align 82106// CHECK3-NEXT: [[I_I:%.*]] = alloca i32, align 42107// CHECK3-NEXT: [[J_I:%.*]] = alloca i32, align 42108// CHECK3-NEXT: [[I14_I:%.*]] = alloca i32, align 42109// CHECK3-NEXT: [[J15_I:%.*]] = alloca i32, align 42110// CHECK3-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i64, align 82111// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i32, align 42112// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 82113// CHECK3-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 42114// CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 82115// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 42116// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 82117// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], ptr [[TMP3]], i32 0, i32 02118// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 22119// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 02120// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 82121// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3]], ptr [[TMP3]], i32 0, i32 12122// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 52123// CHECK3-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP9]], align 82124// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 62125// CHECK3-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP11]], align 82126// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 72127// CHECK3-NEXT: [[TMP14:%.*]] = load i64, ptr [[TMP13]], align 82128// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 82129// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 82130// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 92131// CHECK3-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 82132// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META39:![0-9]+]])2133// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META42:![0-9]+]])2134// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META44:![0-9]+]])2135// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META46:![0-9]+]])2136// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META48:![0-9]+]])2137// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META50:![0-9]+]]2138// CHECK3-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META50]]2139// CHECK3-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META50]]2140// CHECK3-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META50]]2141// CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META50]]2142// CHECK3-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META50]]2143// CHECK3-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META50]]2144// CHECK3-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META50]]2145// CHECK3-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META50]]2146// CHECK3-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META50]]2147// CHECK3-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META50]]2148// CHECK3-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META50]]2149// CHECK3-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META50]]2150// CHECK3-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META50]]2151// CHECK3-NEXT: call void [[TMP20]](ptr [[TMP21]], ptr [[DOTLASTPRIV_PTR_ADDR_I]]) #[[ATTR2]]2152// CHECK3-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP19]], align 8, !nonnull [[META36]], !align [[META37]]2153// CHECK3-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias [[META50]]2154// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2:%.*]], ptr [[TMP19]], i32 0, i32 12155// CHECK3-NEXT: [[TMP25:%.*]] = load ptr, ptr [[TMP24]], align 8, !nonnull [[META36]], !align [[META37]]2156// CHECK3-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 42157// CHECK3-NEXT: store i32 [[TMP26]], ptr [[DOTCAPTURE_EXPR__I]], align 4, !noalias [[META50]]2158// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[TMP19]], i32 0, i32 12159// CHECK3-NEXT: [[TMP28:%.*]] = load ptr, ptr [[TMP27]], align 8, !nonnull [[META36]], !align [[META37]]2160// CHECK3-NEXT: [[TMP29:%.*]] = load i32, ptr [[TMP28]], align 42161// CHECK3-NEXT: store i32 [[TMP29]], ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META50]]2162// CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[TMP19]], i32 0, i32 22163// CHECK3-NEXT: [[TMP31:%.*]] = load ptr, ptr [[TMP30]], align 8, !nonnull [[META36]], !align [[META38]]2164// CHECK3-NEXT: [[TMP32:%.*]] = load ptr, ptr [[TMP31]], align 82165// CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[TMP19]], i32 0, i32 12166// CHECK3-NEXT: [[TMP34:%.*]] = load ptr, ptr [[TMP33]], align 8, !nonnull [[META36]], !align [[META37]]2167// CHECK3-NEXT: [[TMP35:%.*]] = load i32, ptr [[TMP34]], align 42168// CHECK3-NEXT: [[IDXPROM_I:%.*]] = sext i32 [[TMP35]] to i642169// CHECK3-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds ptr, ptr [[TMP32]], i64 [[IDXPROM_I]]2170// CHECK3-NEXT: [[TMP36:%.*]] = load ptr, ptr [[ARRAYIDX_I]], align 82171// CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[TMP19]], i32 0, i32 12172// CHECK3-NEXT: [[TMP38:%.*]] = load ptr, ptr [[TMP37]], align 8, !nonnull [[META36]], !align [[META37]]2173// CHECK3-NEXT: [[TMP39:%.*]] = load i32, ptr [[TMP38]], align 42174// CHECK3-NEXT: [[IDXPROM4_I:%.*]] = sext i32 [[TMP39]] to i642175// CHECK3-NEXT: [[ARRAYIDX5_I:%.*]] = getelementptr inbounds i8, ptr [[TMP36]], i64 [[IDXPROM4_I]]2176// CHECK3-NEXT: [[TMP40:%.*]] = load i8, ptr [[ARRAYIDX5_I]], align 12177// CHECK3-NEXT: [[CONV_I:%.*]] = sext i8 [[TMP40]] to i322178// CHECK3-NEXT: store i32 [[CONV_I]], ptr [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias [[META50]]2179// CHECK3-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__I]], align 4, !noalias [[META50]]2180// CHECK3-NEXT: [[CONV7_I:%.*]] = sext i32 [[TMP41]] to i642181// CHECK3-NEXT: [[TMP42:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias [[META50]]2182// CHECK3-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META50]]2183// CHECK3-NEXT: [[SUB8_I:%.*]] = sub i32 [[TMP42]], [[TMP43]]2184// CHECK3-NEXT: [[SUB9_I:%.*]] = sub i32 [[SUB8_I]], 12185// CHECK3-NEXT: [[CONV11_I:%.*]] = zext i32 [[SUB8_I]] to i642186// CHECK3-NEXT: [[MUL_I:%.*]] = mul nsw i64 [[CONV7_I]], [[CONV11_I]]2187// CHECK3-NEXT: [[SUB12_I:%.*]] = sub nsw i64 [[MUL_I]], 12188// CHECK3-NEXT: store i64 [[SUB12_I]], ptr [[DOTCAPTURE_EXPR_6_I]], align 8, !noalias [[META50]]2189// CHECK3-NEXT: store i32 0, ptr [[I_I]], align 4, !noalias [[META50]]2190// CHECK3-NEXT: [[TMP44:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META50]]2191// CHECK3-NEXT: store i32 [[TMP44]], ptr [[J_I]], align 4, !noalias [[META50]]2192// CHECK3-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__I]], align 4, !noalias [[META50]]2193// CHECK3-NEXT: [[CMP_I:%.*]] = icmp slt i32 0, [[TMP45]]2194// CHECK3-NEXT: br i1 [[CMP_I]], label [[LAND_LHS_TRUE_I:%.*]], label [[TASKLOOP_IF_END_I:%.*]]2195// CHECK3: land.lhs.true.i:2196// CHECK3-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META50]]2197// CHECK3-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias [[META50]]2198// CHECK3-NEXT: [[CMP13_I:%.*]] = icmp slt i32 [[TMP46]], [[TMP47]]2199// CHECK3-NEXT: br i1 [[CMP13_I]], label [[TASKLOOP_IF_THEN_I:%.*]], label [[TASKLOOP_IF_END_I]]2200// CHECK3: taskloop.if.then.i:2201// CHECK3-NEXT: [[TMP48:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META50]]2202// CHECK3-NEXT: store i64 [[TMP48]], ptr [[DOTOMP_IV_I]], align 8, !noalias [[META50]]2203// CHECK3-NEXT: [[TMP49:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[TMP19]], i32 0, i32 12204// CHECK3-NEXT: [[TMP50:%.*]] = load ptr, ptr [[TMP49]], align 8, !nonnull [[META36]], !align [[META37]]2205// CHECK3-NEXT: [[TMP51:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[TMP19]], i32 0, i32 22206// CHECK3-NEXT: [[TMP52:%.*]] = load ptr, ptr [[TMP51]], align 8, !nonnull [[META36]], !align [[META38]]2207// CHECK3-NEXT: [[TMP53:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[TMP19]], i32 0, i32 32208// CHECK3-NEXT: [[TMP54:%.*]] = load i8, ptr [[TMP53]], align 12209// CHECK3-NEXT: [[LOADEDV_I:%.*]] = trunc i8 [[TMP54]] to i12210// CHECK3-NEXT: br i1 [[LOADEDV_I]], label [[OMP_IF_THEN_I:%.*]], label [[OMP_IF_ELSE_I:%.*]]2211// CHECK3: omp_if.then.i:2212// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]2213// CHECK3: omp.inner.for.cond.i:2214// CHECK3-NEXT: [[TMP55:%.*]] = load i64, ptr [[DOTOMP_IV_I]], align 8, !noalias [[META50]], !llvm.access.group [[ACC_GRP51:![0-9]+]]2215// CHECK3-NEXT: [[TMP56:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META50]], !llvm.access.group [[ACC_GRP51]]2216// CHECK3-NEXT: [[CMP16_I:%.*]] = icmp ule i64 [[TMP55]], [[TMP56]]2217// CHECK3-NEXT: br i1 [[CMP16_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[OMP_INNER_FOR_END_I:%.*]]2218// CHECK3: omp.inner.for.body.i:2219// CHECK3-NEXT: [[TMP57:%.*]] = load i64, ptr [[DOTOMP_IV_I]], align 8, !noalias [[META50]], !llvm.access.group [[ACC_GRP51]]2220// CHECK3-NEXT: [[TMP58:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias [[META50]], !llvm.access.group [[ACC_GRP51]]2221// CHECK3-NEXT: [[TMP59:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META50]], !llvm.access.group [[ACC_GRP51]]2222// CHECK3-NEXT: [[SUB17_I:%.*]] = sub i32 [[TMP58]], [[TMP59]]2223// CHECK3-NEXT: [[SUB18_I:%.*]] = sub i32 [[SUB17_I]], 12224// CHECK3-NEXT: [[CONV22_I:%.*]] = zext i32 [[SUB17_I]] to i642225// CHECK3-NEXT: [[DIV23_I:%.*]] = sdiv i64 [[TMP57]], [[CONV22_I]]2226// CHECK3-NEXT: [[CONV26_I:%.*]] = trunc i64 [[DIV23_I]] to i322227// CHECK3-NEXT: store i32 [[CONV26_I]], ptr [[I14_I]], align 4, !noalias [[META50]], !llvm.access.group [[ACC_GRP51]]2228// CHECK3-NEXT: [[TMP60:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META50]], !llvm.access.group [[ACC_GRP51]]2229// CHECK3-NEXT: [[CONV27_I:%.*]] = sext i32 [[TMP60]] to i642230// CHECK3-NEXT: [[TMP61:%.*]] = load i64, ptr [[DOTOMP_IV_I]], align 8, !noalias [[META50]], !llvm.access.group [[ACC_GRP51]]2231// CHECK3-NEXT: [[TMP62:%.*]] = load i64, ptr [[DOTOMP_IV_I]], align 8, !noalias [[META50]], !llvm.access.group [[ACC_GRP51]]2232// CHECK3-NEXT: [[TMP63:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias [[META50]], !llvm.access.group [[ACC_GRP51]]2233// CHECK3-NEXT: [[TMP64:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META50]], !llvm.access.group [[ACC_GRP51]]2234// CHECK3-NEXT: [[SUB28_I:%.*]] = sub i32 [[TMP63]], [[TMP64]]2235// CHECK3-NEXT: [[SUB29_I:%.*]] = sub i32 [[SUB28_I]], 12236// CHECK3-NEXT: [[CONV33_I:%.*]] = zext i32 [[SUB28_I]] to i642237// CHECK3-NEXT: [[DIV34_I:%.*]] = sdiv i64 [[TMP62]], [[CONV33_I]]2238// CHECK3-NEXT: [[TMP65:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias [[META50]], !llvm.access.group [[ACC_GRP51]]2239// CHECK3-NEXT: [[TMP66:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META50]], !llvm.access.group [[ACC_GRP51]]2240// CHECK3-NEXT: [[SUB35_I:%.*]] = sub i32 [[TMP65]], [[TMP66]]2241// CHECK3-NEXT: [[SUB36_I:%.*]] = sub i32 [[SUB35_I]], 12242// CHECK3-NEXT: [[CONV40_I:%.*]] = zext i32 [[SUB35_I]] to i642243// CHECK3-NEXT: [[MUL41_I:%.*]] = mul nsw i64 [[DIV34_I]], [[CONV40_I]]2244// CHECK3-NEXT: [[SUB42_I:%.*]] = sub nsw i64 [[TMP61]], [[MUL41_I]]2245// CHECK3-NEXT: [[ADD44_I:%.*]] = add nsw i64 [[CONV27_I]], [[SUB42_I]]2246// CHECK3-NEXT: [[CONV45_I:%.*]] = trunc i64 [[ADD44_I]] to i322247// CHECK3-NEXT: store i32 [[CONV45_I]], ptr [[J15_I]], align 4, !noalias [[META50]], !llvm.access.group [[ACC_GRP51]]2248// CHECK3-NEXT: [[TMP67:%.*]] = load i64, ptr [[DOTOMP_IV_I]], align 8, !noalias [[META50]], !llvm.access.group [[ACC_GRP51]]2249// CHECK3-NEXT: [[ADD46_I:%.*]] = add nsw i64 [[TMP67]], 12250// CHECK3-NEXT: store i64 [[ADD46_I]], ptr [[DOTOMP_IV_I]], align 8, !noalias [[META50]], !llvm.access.group [[ACC_GRP51]]2251// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP52:![0-9]+]]2252// CHECK3: omp.inner.for.end.i:2253// CHECK3-NEXT: br label [[OMP_IF_END_I:%.*]]2254// CHECK3: omp_if.else.i:2255// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND47_I:%.*]]2256// CHECK3: omp.inner.for.cond47.i:2257// CHECK3-NEXT: [[TMP68:%.*]] = load i64, ptr [[DOTOMP_IV_I]], align 8, !noalias [[META50]]2258// CHECK3-NEXT: [[TMP69:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META50]]2259// CHECK3-NEXT: [[CMP48_I:%.*]] = icmp ule i64 [[TMP68]], [[TMP69]]2260// CHECK3-NEXT: br i1 [[CMP48_I]], label [[OMP_INNER_FOR_BODY49_I:%.*]], label [[OMP_INNER_FOR_END82_I:%.*]]2261// CHECK3: omp.inner.for.body49.i:2262// CHECK3-NEXT: [[TMP70:%.*]] = load i64, ptr [[DOTOMP_IV_I]], align 8, !noalias [[META50]]2263// CHECK3-NEXT: [[TMP71:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias [[META50]]2264// CHECK3-NEXT: [[TMP72:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META50]]2265// CHECK3-NEXT: [[SUB50_I:%.*]] = sub i32 [[TMP71]], [[TMP72]]2266// CHECK3-NEXT: [[SUB51_I:%.*]] = sub i32 [[SUB50_I]], 12267// CHECK3-NEXT: [[CONV55_I:%.*]] = zext i32 [[SUB50_I]] to i642268// CHECK3-NEXT: [[DIV56_I:%.*]] = sdiv i64 [[TMP70]], [[CONV55_I]]2269// CHECK3-NEXT: [[CONV59_I:%.*]] = trunc i64 [[DIV56_I]] to i322270// CHECK3-NEXT: store i32 [[CONV59_I]], ptr [[I14_I]], align 4, !noalias [[META50]]2271// CHECK3-NEXT: [[TMP73:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META50]]2272// CHECK3-NEXT: [[CONV60_I:%.*]] = sext i32 [[TMP73]] to i642273// CHECK3-NEXT: [[TMP74:%.*]] = load i64, ptr [[DOTOMP_IV_I]], align 8, !noalias [[META50]]2274// CHECK3-NEXT: [[TMP75:%.*]] = load i64, ptr [[DOTOMP_IV_I]], align 8, !noalias [[META50]]2275// CHECK3-NEXT: [[TMP76:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias [[META50]]2276// CHECK3-NEXT: [[TMP77:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META50]]2277// CHECK3-NEXT: [[SUB61_I:%.*]] = sub i32 [[TMP76]], [[TMP77]]2278// CHECK3-NEXT: [[SUB62_I:%.*]] = sub i32 [[SUB61_I]], 12279// CHECK3-NEXT: [[CONV66_I:%.*]] = zext i32 [[SUB61_I]] to i642280// CHECK3-NEXT: [[DIV67_I:%.*]] = sdiv i64 [[TMP75]], [[CONV66_I]]2281// CHECK3-NEXT: [[TMP78:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias [[META50]]2282// CHECK3-NEXT: [[TMP79:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META50]]2283// CHECK3-NEXT: [[SUB68_I:%.*]] = sub i32 [[TMP78]], [[TMP79]]2284// CHECK3-NEXT: [[SUB69_I:%.*]] = sub i32 [[SUB68_I]], 12285// CHECK3-NEXT: [[CONV73_I:%.*]] = zext i32 [[SUB68_I]] to i642286// CHECK3-NEXT: [[MUL74_I:%.*]] = mul nsw i64 [[DIV67_I]], [[CONV73_I]]2287// CHECK3-NEXT: [[SUB75_I:%.*]] = sub nsw i64 [[TMP74]], [[MUL74_I]]2288// CHECK3-NEXT: [[ADD77_I:%.*]] = add nsw i64 [[CONV60_I]], [[SUB75_I]]2289// CHECK3-NEXT: [[CONV78_I:%.*]] = trunc i64 [[ADD77_I]] to i322290// CHECK3-NEXT: store i32 [[CONV78_I]], ptr [[J15_I]], align 4, !noalias [[META50]]2291// CHECK3-NEXT: [[TMP80:%.*]] = load i64, ptr [[DOTOMP_IV_I]], align 8, !noalias [[META50]]2292// CHECK3-NEXT: [[ADD81_I:%.*]] = add nsw i64 [[TMP80]], 12293// CHECK3-NEXT: store i64 [[ADD81_I]], ptr [[DOTOMP_IV_I]], align 8, !noalias [[META50]]2294// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND47_I]], !llvm.loop [[LOOP54:![0-9]+]]2295// CHECK3: omp.inner.for.end82.i:2296// CHECK3-NEXT: br label [[OMP_IF_END_I]]2297// CHECK3: omp_if.end.i:2298// CHECK3-NEXT: br label [[TASKLOOP_IF_END_I]]2299// CHECK3: taskloop.if.end.i:2300// CHECK3-NEXT: [[TMP81:%.*]] = load i32, ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META50]]2301// CHECK3-NEXT: [[TMP82:%.*]] = icmp ne i32 [[TMP81]], 02302// CHECK3-NEXT: br i1 [[TMP82]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.*]], label [[DOTOMP_OUTLINED__5_EXIT:%.*]]2303// CHECK3: .omp.lastprivate.then.i:2304// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__5_EXIT]]2305// CHECK3: .omp_outlined..5.exit:2306// CHECK3-NEXT: ret i32 02307//2308//2309// CHECK3-LABEL: define {{[^@]+}}@.omp_task_dup.2310// CHECK3-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], i32 noundef [[TMP2:%.*]]) #[[ATTR4]] {2311// CHECK3-NEXT: entry:2312// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 82313// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 82314// CHECK3-NEXT: [[DOTADDR2:%.*]] = alloca i32, align 42315// CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 82316// CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 82317// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTADDR2]], align 42318// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR]], align 82319// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], ptr [[TMP3]], i32 0, i32 02320// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 82321// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTADDR2]], align 42322// CHECK3-NEXT: store i32 [[TMP6]], ptr [[TMP5]], align 82323// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3]], ptr [[TMP3]], i32 0, i32 12324// CHECK3-NEXT: ret void2325//2326//2327// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init2328// CHECK3-SAME: () #[[ATTR6]] section "__TEXT,__StaticInit,regular,pure_instructions" {2329// CHECK3-NEXT: entry:2330// CHECK3-NEXT: call void @_ZN1SC1Ei(ptr noundef nonnull align 4 dereferenceable(4) @s, i32 noundef 1)2331// CHECK3-NEXT: ret void2332//2333//2334// CHECK3-LABEL: define {{[^@]+}}@_ZN1SC1Ei2335// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] align 2 {2336// CHECK3-NEXT: entry:2337// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82338// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i32, align 42339// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82340// CHECK3-NEXT: store i32 [[C]], ptr [[C_ADDR]], align 42341// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82342// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[C_ADDR]], align 42343// CHECK3-NEXT: call void @_ZN1SC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])2344// CHECK3-NEXT: ret void2345//2346//2347// CHECK3-LABEL: define {{[^@]+}}@_ZN1SC2Ei2348// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR8]] align 2 {2349// CHECK3-NEXT: entry:2350// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82351// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i32, align 42352// CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 12353// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 82354// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82355// CHECK3-NEXT: store i32 [[C]], ptr [[C_ADDR]], align 42356// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82357// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[C_ADDR]], align 42358// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 02359// CHECK3-NEXT: [[STOREDV:%.*]] = zext i1 [[TOBOOL]] to i82360// CHECK3-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_]], align 12361// CHECK3-NEXT: [[TMP1:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 12362// CHECK3-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP1]] to i12363// CHECK3-NEXT: [[STOREDV2:%.*]] = zext i1 [[LOADEDV]] to i82364// CHECK3-NEXT: store i8 [[STOREDV2]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 12365// CHECK3-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 82366// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 3, ptr @_ZN1SC2Ei.omp_outlined, ptr [[THIS1]], ptr [[C_ADDR]], i64 [[TMP2]])2367// CHECK3-NEXT: ret void2368//2369//2370// CHECK3-LABEL: define {{[^@]+}}@_ZN1SC2Ei.omp_outlined2371// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {2372// CHECK3-NEXT: entry:2373// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 82374// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 82375// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82376// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 82377// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 82378// CHECK3-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_4:%.*]], align 82379// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 42380// CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 82381// CHECK3-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 42382// CHECK3-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 42383// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 82384// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 82385// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82386// CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 82387// CHECK3-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 82388// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82389// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META36]], !align [[META37]]2390// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 82391// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 42392// CHECK3-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP3]])2393// CHECK3-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 02394// CHECK3-NEXT: br i1 [[TMP5]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]2395// CHECK3: omp_if.then:2396// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_4]], ptr [[AGG_CAPTURED]], i32 0, i32 02397// CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP6]], align 82398// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_4]], ptr [[AGG_CAPTURED]], i32 0, i32 12399// CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP7]], align 82400// CHECK3-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP3]])2401// CHECK3-NEXT: [[TMP8:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 12402// CHECK3-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP8]] to i12403// CHECK3-NEXT: store ptr [[TMP]], ptr [[_TMP1]], align 82404// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP1]], align 42405// CHECK3-NEXT: store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR_2]], align 42406// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 42407// CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP10]], 02408// CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 12409// CHECK3-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 12410// CHECK3-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_3]], align 42411// CHECK3-NEXT: [[TMP11:%.*]] = select i1 [[LOADEDV]], i32 2, i32 02412// CHECK3-NEXT: [[TMP12:%.*]] = or i32 [[TMP11]], 12413// CHECK3-NEXT: [[TMP13:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP3]], i32 [[TMP12]], i64 80, i64 16, ptr @.omp_task_entry..8)2414// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.*]], ptr [[TMP13]], i32 0, i32 02415// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP14]], i32 0, i32 02416// CHECK3-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 82417// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP16]], ptr align 8 [[AGG_CAPTURED]], i64 16, i1 false)2418// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP14]], i32 0, i32 52419// CHECK3-NEXT: store i64 0, ptr [[TMP17]], align 82420// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP14]], i32 0, i32 62421// CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 42422// CHECK3-NEXT: [[CONV:%.*]] = sext i32 [[TMP19]] to i642423// CHECK3-NEXT: store i64 [[CONV]], ptr [[TMP18]], align 82424// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP14]], i32 0, i32 72425// CHECK3-NEXT: store i64 1, ptr [[TMP20]], align 82426// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP14]], i32 0, i32 92427// CHECK3-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP21]], i8 0, i64 8, i1 false)2428// CHECK3-NEXT: [[TMP22:%.*]] = load i64, ptr [[TMP20]], align 82429// CHECK3-NEXT: call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP3]], ptr [[TMP13]], i32 1, ptr [[TMP17]], ptr [[TMP18]], i64 [[TMP22]], i32 1, i32 2, i64 4, ptr null)2430// CHECK3-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP3]])2431// CHECK3-NEXT: call void @__kmpc_end_master(ptr @[[GLOB1]], i32 [[TMP3]])2432// CHECK3-NEXT: br label [[OMP_IF_END]]2433// CHECK3: omp_if.end:2434// CHECK3-NEXT: ret void2435//2436//2437// CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry..82438// CHECK3-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR4]] {2439// CHECK3-NEXT: entry:2440// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 42441// CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 82442// CHECK3-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 82443// CHECK3-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 82444// CHECK3-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 82445// CHECK3-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 82446// CHECK3-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 82447// CHECK3-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 82448// CHECK3-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 42449// CHECK3-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 82450// CHECK3-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 82451// CHECK3-NEXT: [[TMP_I:%.*]] = alloca i32, align 42452// CHECK3-NEXT: [[TMP1_I:%.*]] = alloca ptr, align 82453// CHECK3-NEXT: [[DOTCAPTURE_EXPR__I:%.*]] = alloca i32, align 42454// CHECK3-NEXT: [[DOTCAPTURE_EXPR_2_I:%.*]] = alloca i32, align 42455// CHECK3-NEXT: [[A_I:%.*]] = alloca i32, align 42456// CHECK3-NEXT: [[TMP4_I:%.*]] = alloca ptr, align 82457// CHECK3-NEXT: [[A5_I:%.*]] = alloca i32, align 42458// CHECK3-NEXT: [[TMP6_I:%.*]] = alloca ptr, align 82459// CHECK3-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 42460// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i32, align 42461// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 82462// CHECK3-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 42463// CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 82464// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 42465// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 82466// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.*]], ptr [[TMP3]], i32 0, i32 02467// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 22468// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 02469// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 82470// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 52471// CHECK3-NEXT: [[TMP9:%.*]] = load i64, ptr [[TMP8]], align 82472// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 62473// CHECK3-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 82474// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 72475// CHECK3-NEXT: [[TMP13:%.*]] = load i64, ptr [[TMP12]], align 82476// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 82477// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 82478// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 92479// CHECK3-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 82480// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META56:![0-9]+]])2481// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META59:![0-9]+]])2482// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META61:![0-9]+]])2483// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META63:![0-9]+]])2484// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META65:![0-9]+]])2485// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META67:![0-9]+]]2486// CHECK3-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META67]]2487// CHECK3-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META67]]2488// CHECK3-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META67]]2489// CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META67]]2490// CHECK3-NEXT: store i64 [[TMP9]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META67]]2491// CHECK3-NEXT: store i64 [[TMP11]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META67]]2492// CHECK3-NEXT: store i64 [[TMP13]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META67]]2493// CHECK3-NEXT: store i32 [[TMP15]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META67]]2494// CHECK3-NEXT: store ptr [[TMP17]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META67]]2495// CHECK3-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META67]]2496// CHECK3-NEXT: [[TMP18:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META67]]2497// CHECK3-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP18]], align 82498// CHECK3-NEXT: store ptr [[TMP_I]], ptr [[TMP1_I]], align 8, !noalias [[META67]]2499// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_4:%.*]], ptr [[TMP18]], i32 0, i32 12500// CHECK3-NEXT: [[TMP21:%.*]] = load ptr, ptr [[TMP20]], align 8, !nonnull [[META36]], !align [[META37]]2501// CHECK3-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 42502// CHECK3-NEXT: store i32 [[TMP22]], ptr [[DOTCAPTURE_EXPR__I]], align 4, !noalias [[META67]]2503// CHECK3-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__I]], align 4, !noalias [[META67]]2504// CHECK3-NEXT: [[SUB3_I:%.*]] = sub nsw i32 [[TMP23]], 12505// CHECK3-NEXT: store i32 [[SUB3_I]], ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META67]]2506// CHECK3-NEXT: store ptr [[A_I]], ptr [[TMP4_I]], align 8, !noalias [[META67]]2507// CHECK3-NEXT: [[TMP24:%.*]] = load ptr, ptr [[TMP4_I]], align 8, !noalias [[META67]], !nonnull [[META36]], !align [[META37]]2508// CHECK3-NEXT: store i32 0, ptr [[TMP24]], align 42509// CHECK3-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__I]], align 4, !noalias [[META67]]2510// CHECK3-NEXT: [[CMP_I:%.*]] = icmp slt i32 0, [[TMP25]]2511// CHECK3-NEXT: br i1 [[CMP_I]], label [[TASKLOOP_IF_THEN_I:%.*]], label [[DOTOMP_OUTLINED__7_EXIT:%.*]]2512// CHECK3: taskloop.if.then.i:2513// CHECK3-NEXT: store ptr [[A5_I]], ptr [[TMP6_I]], align 8, !noalias [[META67]]2514// CHECK3-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META67]]2515// CHECK3-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP26]] to i322516// CHECK3-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META67]]2517// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_4]], ptr [[TMP18]], i32 0, i32 12518// CHECK3-NEXT: [[TMP28:%.*]] = load ptr, ptr [[TMP27]], align 8, !nonnull [[META36]], !align [[META37]]2519// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]2520// CHECK3: omp.inner.for.cond.i:2521// CHECK3-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META67]], !llvm.access.group [[ACC_GRP68:![0-9]+]]2522// CHECK3-NEXT: [[CONV7_I:%.*]] = sext i32 [[TMP29]] to i642523// CHECK3-NEXT: [[TMP30:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META67]], !llvm.access.group [[ACC_GRP68]]2524// CHECK3-NEXT: [[CMP8_I:%.*]] = icmp ule i64 [[CONV7_I]], [[TMP30]]2525// CHECK3-NEXT: br i1 [[CMP8_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[OMP_INNER_FOR_END_I:%.*]]2526// CHECK3: omp.inner.for.body.i:2527// CHECK3-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META67]], !llvm.access.group [[ACC_GRP68]]2528// CHECK3-NEXT: [[TMP32:%.*]] = load ptr, ptr [[TMP6_I]], align 8, !noalias [[META67]], !nonnull [[META36]], !align [[META37]], !llvm.access.group [[ACC_GRP68]]2529// CHECK3-NEXT: store i32 [[TMP31]], ptr [[TMP32]], align 4, !llvm.access.group [[ACC_GRP68]]2530// CHECK3-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META67]], !llvm.access.group [[ACC_GRP68]]2531// CHECK3-NEXT: [[ADD9_I:%.*]] = add nsw i32 [[TMP33]], 12532// CHECK3-NEXT: store i32 [[ADD9_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META67]], !llvm.access.group [[ACC_GRP68]]2533// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP69:![0-9]+]]2534// CHECK3: omp.inner.for.end.i:2535// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__7_EXIT]]2536// CHECK3: .omp_outlined..7.exit:2537// CHECK3-NEXT: ret i32 02538//2539//2540// CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_parallel_master_taskloop_simd_codegen.cpp2541// CHECK3-SAME: () #[[ATTR6]] section "__TEXT,__StaticInit,regular,pure_instructions" {2542// CHECK3-NEXT: entry:2543// CHECK3-NEXT: call void @__cxx_global_var_init()2544// CHECK3-NEXT: ret void2545//2546//2547// CHECK5-LABEL: define {{[^@]+}}@main2548// CHECK5-SAME: (i32 noundef [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {2549// CHECK5-NEXT: entry:2550// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 42551// CHECK5-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 42552// CHECK5-NEXT: [[ARGV_ADDR:%.*]] = alloca ptr, align 82553// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 42554// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 42555// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 82556// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 82557// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 42558// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 42559// CHECK5-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 42560// CHECK5-NEXT: [[_TMP4:%.*]] = alloca i32, align 42561// CHECK5-NEXT: [[DOTOMP_LB5:%.*]] = alloca i64, align 82562// CHECK5-NEXT: [[DOTOMP_UB6:%.*]] = alloca i64, align 82563// CHECK5-NEXT: [[DOTOMP_IV7:%.*]] = alloca i32, align 42564// CHECK5-NEXT: [[I9:%.*]] = alloca i32, align 42565// CHECK5-NEXT: [[I20:%.*]] = alloca i32, align 42566// CHECK5-NEXT: [[DOTCAPTURE_EXPR_21:%.*]] = alloca i8, align 12567// CHECK5-NEXT: [[DOTCAPTURE_EXPR_22:%.*]] = alloca i32, align 42568// CHECK5-NEXT: [[_TMP23:%.*]] = alloca i32, align 42569// CHECK5-NEXT: [[_TMP24:%.*]] = alloca i32, align 42570// CHECK5-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 42571// CHECK5-NEXT: [[DOTCAPTURE_EXPR_26:%.*]] = alloca i32, align 42572// CHECK5-NEXT: [[DOTCAPTURE_EXPR_27:%.*]] = alloca i32, align 42573// CHECK5-NEXT: [[DOTCAPTURE_EXPR_31:%.*]] = alloca i64, align 82574// CHECK5-NEXT: [[DOTOMP_LB40:%.*]] = alloca i64, align 82575// CHECK5-NEXT: [[DOTOMP_UB41:%.*]] = alloca i64, align 82576// CHECK5-NEXT: [[I42:%.*]] = alloca i32, align 42577// CHECK5-NEXT: [[J:%.*]] = alloca i32, align 42578// CHECK5-NEXT: [[DOTOMP_IV45:%.*]] = alloca i64, align 82579// CHECK5-NEXT: [[I46:%.*]] = alloca i32, align 42580// CHECK5-NEXT: [[J47:%.*]] = alloca i32, align 42581// CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 42582// CHECK5-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 42583// CHECK5-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 82584// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARGC_ADDR]], align 42585// CHECK5-NEXT: store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 42586// CHECK5-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 82587// CHECK5-NEXT: store i64 9, ptr [[DOTOMP_UB]], align 82588// CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTOMP_LB]], align 82589// CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i322590// CHECK5-NEXT: store i32 [[CONV]], ptr [[DOTOMP_IV]], align 42591// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]2592// CHECK5: omp.inner.for.cond:2593// CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42594// CHECK5-NEXT: [[CONV1:%.*]] = sext i32 [[TMP2]] to i642595// CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 82596// CHECK5-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV1]], [[TMP3]]2597// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2598// CHECK5: omp.inner.for.body:2599// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42600// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 12601// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]2602// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 42603// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]2604// CHECK5: omp.body.continue:2605// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]2606// CHECK5: omp.inner.for.inc:2607// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42608// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP5]], 12609// CHECK5-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 42610// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]2611// CHECK5: omp.inner.for.end:2612// CHECK5-NEXT: store i32 10, ptr [[I]], align 42613// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARGC_ADDR]], align 42614// CHECK5-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_3]], align 42615// CHECK5-NEXT: store i64 0, ptr [[DOTOMP_LB5]], align 82616// CHECK5-NEXT: store i64 9, ptr [[DOTOMP_UB6]], align 82617// CHECK5-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_LB5]], align 82618// CHECK5-NEXT: [[CONV8:%.*]] = trunc i64 [[TMP7]] to i322619// CHECK5-NEXT: store i32 [[CONV8]], ptr [[DOTOMP_IV7]], align 42620// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND10:%.*]]2621// CHECK5: omp.inner.for.cond10:2622// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]]2623// CHECK5-NEXT: [[CONV11:%.*]] = sext i32 [[TMP8]] to i642624// CHECK5-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB6]], align 8, !llvm.access.group [[ACC_GRP5]]2625// CHECK5-NEXT: [[CMP12:%.*]] = icmp ule i64 [[CONV11]], [[TMP9]]2626// CHECK5-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY13:%.*]], label [[OMP_INNER_FOR_END19:%.*]]2627// CHECK5: omp.inner.for.body13:2628// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 4, !llvm.access.group [[ACC_GRP5]]2629// CHECK5-NEXT: [[MUL14:%.*]] = mul nsw i32 [[TMP10]], 12630// CHECK5-NEXT: [[ADD15:%.*]] = add nsw i32 0, [[MUL14]]2631// CHECK5-NEXT: store i32 [[ADD15]], ptr [[I9]], align 4, !llvm.access.group [[ACC_GRP5]]2632// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]]2633// CHECK5: omp.body.continue16:2634// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]]2635// CHECK5: omp.inner.for.inc17:2636// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 4, !llvm.access.group [[ACC_GRP5]]2637// CHECK5-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP11]], 12638// CHECK5-NEXT: store i32 [[ADD18]], ptr [[DOTOMP_IV7]], align 4, !llvm.access.group [[ACC_GRP5]]2639// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP6:![0-9]+]]2640// CHECK5: omp.inner.for.end19:2641// CHECK5-NEXT: store i32 10, ptr [[I9]], align 42642// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARGC_ADDR]], align 42643// CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP12]], 02644// CHECK5-NEXT: [[STOREDV:%.*]] = zext i1 [[TOBOOL]] to i82645// CHECK5-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_21]], align 12646// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[ARGC_ADDR]], align 42647// CHECK5-NEXT: store i32 [[TMP13]], ptr [[DOTCAPTURE_EXPR_22]], align 42648// CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[ARGC_ADDR]], align 42649// CHECK5-NEXT: store i32 [[TMP14]], ptr [[DOTCAPTURE_EXPR_25]], align 42650// CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[ARGC_ADDR]], align 42651// CHECK5-NEXT: store i32 [[TMP15]], ptr [[DOTCAPTURE_EXPR_26]], align 42652// CHECK5-NEXT: [[TMP16:%.*]] = load ptr, ptr [[ARGV_ADDR]], align 82653// CHECK5-NEXT: [[TMP17:%.*]] = load i32, ptr [[ARGC_ADDR]], align 42654// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i642655// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds ptr, ptr [[TMP16]], i64 [[IDXPROM]]2656// CHECK5-NEXT: [[TMP18:%.*]] = load ptr, ptr [[ARRAYIDX]], align 82657// CHECK5-NEXT: [[TMP19:%.*]] = load i32, ptr [[ARGC_ADDR]], align 42658// CHECK5-NEXT: [[IDXPROM28:%.*]] = sext i32 [[TMP19]] to i642659// CHECK5-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds i8, ptr [[TMP18]], i64 [[IDXPROM28]]2660// CHECK5-NEXT: [[TMP20:%.*]] = load i8, ptr [[ARRAYIDX29]], align 12661// CHECK5-NEXT: [[CONV30:%.*]] = sext i8 [[TMP20]] to i322662// CHECK5-NEXT: store i32 [[CONV30]], ptr [[DOTCAPTURE_EXPR_27]], align 42663// CHECK5-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_25]], align 42664// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP21]], 02665// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 12666// CHECK5-NEXT: [[CONV32:%.*]] = sext i32 [[DIV]] to i642667// CHECK5-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 42668// CHECK5-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 42669// CHECK5-NEXT: [[SUB33:%.*]] = sub i32 [[TMP22]], [[TMP23]]2670// CHECK5-NEXT: [[SUB34:%.*]] = sub i32 [[SUB33]], 12671// CHECK5-NEXT: [[ADD35:%.*]] = add i32 [[SUB34]], 12672// CHECK5-NEXT: [[DIV36:%.*]] = udiv i32 [[ADD35]], 12673// CHECK5-NEXT: [[CONV37:%.*]] = zext i32 [[DIV36]] to i642674// CHECK5-NEXT: [[MUL38:%.*]] = mul nsw i64 [[CONV32]], [[CONV37]]2675// CHECK5-NEXT: [[SUB39:%.*]] = sub nsw i64 [[MUL38]], 12676// CHECK5-NEXT: store i64 [[SUB39]], ptr [[DOTCAPTURE_EXPR_31]], align 82677// CHECK5-NEXT: store i64 0, ptr [[DOTOMP_LB40]], align 82678// CHECK5-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_31]], align 82679// CHECK5-NEXT: store i64 [[TMP24]], ptr [[DOTOMP_UB41]], align 82680// CHECK5-NEXT: store i32 0, ptr [[I42]], align 42681// CHECK5-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 42682// CHECK5-NEXT: store i32 [[TMP25]], ptr [[J]], align 42683// CHECK5-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_25]], align 42684// CHECK5-NEXT: [[CMP43:%.*]] = icmp slt i32 0, [[TMP26]]2685// CHECK5-NEXT: br i1 [[CMP43]], label [[LAND_LHS_TRUE:%.*]], label [[SIMD_IF_END:%.*]]2686// CHECK5: land.lhs.true:2687// CHECK5-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 42688// CHECK5-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 42689// CHECK5-NEXT: [[CMP44:%.*]] = icmp slt i32 [[TMP27]], [[TMP28]]2690// CHECK5-NEXT: br i1 [[CMP44]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END]]2691// CHECK5: simd.if.then:2692// CHECK5-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTOMP_LB40]], align 82693// CHECK5-NEXT: store i64 [[TMP29]], ptr [[DOTOMP_IV45]], align 82694// CHECK5-NEXT: [[TMP30:%.*]] = load ptr, ptr [[ARGV_ADDR]], align 82695// CHECK5-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[TMP30]], i64 8) ]2696// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND48:%.*]]2697// CHECK5: omp.inner.for.cond48:2698// CHECK5-NEXT: [[TMP31:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9:![0-9]+]]2699// CHECK5-NEXT: [[TMP32:%.*]] = load i64, ptr [[DOTOMP_UB41]], align 8, !llvm.access.group [[ACC_GRP9]]2700// CHECK5-NEXT: [[CMP49:%.*]] = icmp ule i64 [[TMP31]], [[TMP32]]2701// CHECK5-NEXT: br i1 [[CMP49]], label [[OMP_INNER_FOR_BODY50:%.*]], label [[OMP_INNER_FOR_END83:%.*]]2702// CHECK5: omp.inner.for.body50:2703// CHECK5-NEXT: [[TMP33:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9]]2704// CHECK5-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 4, !llvm.access.group [[ACC_GRP9]]2705// CHECK5-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4, !llvm.access.group [[ACC_GRP9]]2706// CHECK5-NEXT: [[SUB51:%.*]] = sub i32 [[TMP34]], [[TMP35]]2707// CHECK5-NEXT: [[SUB52:%.*]] = sub i32 [[SUB51]], 12708// CHECK5-NEXT: [[ADD53:%.*]] = add i32 [[SUB52]], 12709// CHECK5-NEXT: [[DIV54:%.*]] = udiv i32 [[ADD53]], 12710// CHECK5-NEXT: [[MUL55:%.*]] = mul i32 1, [[DIV54]]2711// CHECK5-NEXT: [[CONV56:%.*]] = zext i32 [[MUL55]] to i642712// CHECK5-NEXT: [[DIV57:%.*]] = sdiv i64 [[TMP33]], [[CONV56]]2713// CHECK5-NEXT: [[MUL58:%.*]] = mul nsw i64 [[DIV57]], 12714// CHECK5-NEXT: [[ADD59:%.*]] = add nsw i64 0, [[MUL58]]2715// CHECK5-NEXT: [[CONV60:%.*]] = trunc i64 [[ADD59]] to i322716// CHECK5-NEXT: store i32 [[CONV60]], ptr [[I46]], align 4, !llvm.access.group [[ACC_GRP9]]2717// CHECK5-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4, !llvm.access.group [[ACC_GRP9]]2718// CHECK5-NEXT: [[CONV61:%.*]] = sext i32 [[TMP36]] to i642719// CHECK5-NEXT: [[TMP37:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9]]2720// CHECK5-NEXT: [[TMP38:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9]]2721// CHECK5-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 4, !llvm.access.group [[ACC_GRP9]]2722// CHECK5-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4, !llvm.access.group [[ACC_GRP9]]2723// CHECK5-NEXT: [[SUB62:%.*]] = sub i32 [[TMP39]], [[TMP40]]2724// CHECK5-NEXT: [[SUB63:%.*]] = sub i32 [[SUB62]], 12725// CHECK5-NEXT: [[ADD64:%.*]] = add i32 [[SUB63]], 12726// CHECK5-NEXT: [[DIV65:%.*]] = udiv i32 [[ADD64]], 12727// CHECK5-NEXT: [[MUL66:%.*]] = mul i32 1, [[DIV65]]2728// CHECK5-NEXT: [[CONV67:%.*]] = zext i32 [[MUL66]] to i642729// CHECK5-NEXT: [[DIV68:%.*]] = sdiv i64 [[TMP38]], [[CONV67]]2730// CHECK5-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 4, !llvm.access.group [[ACC_GRP9]]2731// CHECK5-NEXT: [[TMP42:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4, !llvm.access.group [[ACC_GRP9]]2732// CHECK5-NEXT: [[SUB69:%.*]] = sub i32 [[TMP41]], [[TMP42]]2733// CHECK5-NEXT: [[SUB70:%.*]] = sub i32 [[SUB69]], 12734// CHECK5-NEXT: [[ADD71:%.*]] = add i32 [[SUB70]], 12735// CHECK5-NEXT: [[DIV72:%.*]] = udiv i32 [[ADD71]], 12736// CHECK5-NEXT: [[MUL73:%.*]] = mul i32 1, [[DIV72]]2737// CHECK5-NEXT: [[CONV74:%.*]] = zext i32 [[MUL73]] to i642738// CHECK5-NEXT: [[MUL75:%.*]] = mul nsw i64 [[DIV68]], [[CONV74]]2739// CHECK5-NEXT: [[SUB76:%.*]] = sub nsw i64 [[TMP37]], [[MUL75]]2740// CHECK5-NEXT: [[MUL77:%.*]] = mul nsw i64 [[SUB76]], 12741// CHECK5-NEXT: [[ADD78:%.*]] = add nsw i64 [[CONV61]], [[MUL77]]2742// CHECK5-NEXT: [[CONV79:%.*]] = trunc i64 [[ADD78]] to i322743// CHECK5-NEXT: store i32 [[CONV79]], ptr [[J47]], align 4, !llvm.access.group [[ACC_GRP9]]2744// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE80:%.*]]2745// CHECK5: omp.body.continue80:2746// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC81:%.*]]2747// CHECK5: omp.inner.for.inc81:2748// CHECK5-NEXT: [[TMP43:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9]]2749// CHECK5-NEXT: [[ADD82:%.*]] = add nsw i64 [[TMP43]], 12750// CHECK5-NEXT: store i64 [[ADD82]], ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9]]2751// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND48]], !llvm.loop [[LOOP10:![0-9]+]]2752// CHECK5: omp.inner.for.end83:2753// CHECK5-NEXT: [[TMP44:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_25]], align 42754// CHECK5-NEXT: [[SUB84:%.*]] = sub nsw i32 [[TMP44]], 02755// CHECK5-NEXT: [[DIV85:%.*]] = sdiv i32 [[SUB84]], 12756// CHECK5-NEXT: [[MUL86:%.*]] = mul nsw i32 [[DIV85]], 12757// CHECK5-NEXT: [[ADD87:%.*]] = add nsw i32 0, [[MUL86]]2758// CHECK5-NEXT: store i32 [[ADD87]], ptr [[I20]], align 42759// CHECK5-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 42760// CHECK5-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 42761// CHECK5-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 42762// CHECK5-NEXT: [[SUB88:%.*]] = sub i32 [[TMP46]], [[TMP47]]2763// CHECK5-NEXT: [[SUB89:%.*]] = sub i32 [[SUB88]], 12764// CHECK5-NEXT: [[ADD90:%.*]] = add i32 [[SUB89]], 12765// CHECK5-NEXT: [[DIV91:%.*]] = udiv i32 [[ADD90]], 12766// CHECK5-NEXT: [[MUL92:%.*]] = mul i32 [[DIV91]], 12767// CHECK5-NEXT: [[ADD93:%.*]] = add i32 [[TMP45]], [[MUL92]]2768// CHECK5-NEXT: store i32 [[ADD93]], ptr [[J47]], align 42769// CHECK5-NEXT: br label [[SIMD_IF_END]]2770// CHECK5: simd.if.end:2771// CHECK5-NEXT: [[TMP48:%.*]] = load i32, ptr [[RETVAL]], align 42772// CHECK5-NEXT: ret i32 [[TMP48]]2773//2774//2775// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init2776// CHECK5-SAME: () #[[ATTR2:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" {2777// CHECK5-NEXT: entry:2778// CHECK5-NEXT: call void @_ZN1SC1Ei(ptr noundef nonnull align 4 dereferenceable(4) @s, i32 noundef 1)2779// CHECK5-NEXT: ret void2780//2781//2782// CHECK5-LABEL: define {{[^@]+}}@_ZN1SC1Ei2783// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR3:[0-9]+]] align 2 {2784// CHECK5-NEXT: entry:2785// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82786// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i32, align 42787// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82788// CHECK5-NEXT: store i32 [[C]], ptr [[C_ADDR]], align 42789// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82790// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[C_ADDR]], align 42791// CHECK5-NEXT: call void @_ZN1SC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])2792// CHECK5-NEXT: ret void2793//2794//2795// CHECK5-LABEL: define {{[^@]+}}@_ZN1SC2Ei2796// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR3]] align 2 {2797// CHECK5-NEXT: entry:2798// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82799// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i32, align 42800// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 12801// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 42802// CHECK5-NEXT: [[_TMP2:%.*]] = alloca ptr, align 82803// CHECK5-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 42804// CHECK5-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 42805// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 82806// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 82807// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 42808// CHECK5-NEXT: [[_TMP6:%.*]] = alloca ptr, align 82809// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 42810// CHECK5-NEXT: [[A8:%.*]] = alloca i32, align 42811// CHECK5-NEXT: [[_TMP9:%.*]] = alloca ptr, align 82812// CHECK5-NEXT: [[_TMP14:%.*]] = alloca ptr, align 82813// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82814// CHECK5-NEXT: store i32 [[C]], ptr [[C_ADDR]], align 42815// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82816// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[C_ADDR]], align 42817// CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 02818// CHECK5-NEXT: [[STOREDV:%.*]] = zext i1 [[TOBOOL]] to i82819// CHECK5-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_]], align 12820// CHECK5-NEXT: store ptr [[TMP]], ptr [[_TMP2]], align 82821// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[C_ADDR]], align 42822// CHECK5-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_3]], align 42823// CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 42824// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 02825// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 12826// CHECK5-NEXT: [[SUB5:%.*]] = sub nsw i32 [[DIV]], 12827// CHECK5-NEXT: store i32 [[SUB5]], ptr [[DOTCAPTURE_EXPR_4]], align 42828// CHECK5-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 82829// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 42830// CHECK5-NEXT: [[CONV:%.*]] = sext i32 [[TMP3]] to i642831// CHECK5-NEXT: store i64 [[CONV]], ptr [[DOTOMP_UB]], align 82832// CHECK5-NEXT: store ptr [[A]], ptr [[_TMP6]], align 82833// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP6]], align 8, !nonnull [[META12:![0-9]+]], !align [[META13:![0-9]+]]2834// CHECK5-NEXT: store i32 0, ptr [[TMP4]], align 42835// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 42836// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]2837// CHECK5-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]2838// CHECK5: simd.if.then:2839// CHECK5-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 82840// CHECK5-NEXT: [[CONV7:%.*]] = trunc i64 [[TMP6]] to i322841// CHECK5-NEXT: store i32 [[CONV7]], ptr [[DOTOMP_IV]], align 42842// CHECK5-NEXT: store ptr [[A8]], ptr [[_TMP9]], align 82843// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]2844// CHECK5: omp.inner.for.cond:2845// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14:![0-9]+]]2846// CHECK5-NEXT: [[CONV10:%.*]] = sext i32 [[TMP7]] to i642847// CHECK5-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP14]]2848// CHECK5-NEXT: [[CMP11:%.*]] = icmp ule i64 [[CONV10]], [[TMP8]]2849// CHECK5-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2850// CHECK5: omp.inner.for.body:2851// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]2852// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 12853// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]2854// CHECK5-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP9]], align 8, !nonnull [[META12]], !align [[META13]], !llvm.access.group [[ACC_GRP14]]2855// CHECK5-NEXT: store i32 [[ADD]], ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP14]]2856// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]2857// CHECK5: omp.body.continue:2858// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]2859// CHECK5: omp.inner.for.inc:2860// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]2861// CHECK5-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP11]], 12862// CHECK5-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]2863// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]2864// CHECK5: omp.inner.for.end:2865// CHECK5-NEXT: [[A13:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 02866// CHECK5-NEXT: store ptr [[A13]], ptr [[_TMP14]], align 82867// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 42868// CHECK5-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP12]], 02869// CHECK5-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 12870// CHECK5-NEXT: [[MUL17:%.*]] = mul nsw i32 [[DIV16]], 12871// CHECK5-NEXT: [[ADD18:%.*]] = add nsw i32 0, [[MUL17]]2872// CHECK5-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP14]], align 8, !nonnull [[META12]], !align [[META13]]2873// CHECK5-NEXT: store i32 [[ADD18]], ptr [[TMP13]], align 42874// CHECK5-NEXT: br label [[SIMD_IF_END]]2875// CHECK5: simd.if.end:2876// CHECK5-NEXT: ret void2877//2878//2879// CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_parallel_master_taskloop_simd_codegen.cpp2880// CHECK5-SAME: () #[[ATTR2]] section "__TEXT,__StaticInit,regular,pure_instructions" {2881// CHECK5-NEXT: entry:2882// CHECK5-NEXT: call void @__cxx_global_var_init()2883// CHECK5-NEXT: ret void2884//2885//2886// CHECK6-LABEL: define {{[^@]+}}@main2887// CHECK6-SAME: (i32 noundef [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {2888// CHECK6-NEXT: entry:2889// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 42890// CHECK6-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 42891// CHECK6-NEXT: [[ARGV_ADDR:%.*]] = alloca ptr, align 82892// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 42893// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 42894// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 82895// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 82896// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 42897// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 42898// CHECK6-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 42899// CHECK6-NEXT: [[_TMP4:%.*]] = alloca i32, align 42900// CHECK6-NEXT: [[DOTOMP_LB5:%.*]] = alloca i64, align 82901// CHECK6-NEXT: [[DOTOMP_UB6:%.*]] = alloca i64, align 82902// CHECK6-NEXT: [[DOTOMP_IV7:%.*]] = alloca i32, align 42903// CHECK6-NEXT: [[I9:%.*]] = alloca i32, align 42904// CHECK6-NEXT: [[I20:%.*]] = alloca i32, align 42905// CHECK6-NEXT: [[DOTCAPTURE_EXPR_21:%.*]] = alloca i8, align 12906// CHECK6-NEXT: [[DOTCAPTURE_EXPR_22:%.*]] = alloca i32, align 42907// CHECK6-NEXT: [[_TMP23:%.*]] = alloca i32, align 42908// CHECK6-NEXT: [[_TMP24:%.*]] = alloca i32, align 42909// CHECK6-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 42910// CHECK6-NEXT: [[DOTCAPTURE_EXPR_26:%.*]] = alloca i32, align 42911// CHECK6-NEXT: [[DOTCAPTURE_EXPR_27:%.*]] = alloca i32, align 42912// CHECK6-NEXT: [[DOTCAPTURE_EXPR_31:%.*]] = alloca i64, align 82913// CHECK6-NEXT: [[DOTOMP_LB40:%.*]] = alloca i64, align 82914// CHECK6-NEXT: [[DOTOMP_UB41:%.*]] = alloca i64, align 82915// CHECK6-NEXT: [[I42:%.*]] = alloca i32, align 42916// CHECK6-NEXT: [[J:%.*]] = alloca i32, align 42917// CHECK6-NEXT: [[DOTOMP_IV45:%.*]] = alloca i64, align 82918// CHECK6-NEXT: [[I46:%.*]] = alloca i32, align 42919// CHECK6-NEXT: [[J47:%.*]] = alloca i32, align 42920// CHECK6-NEXT: store i32 0, ptr [[RETVAL]], align 42921// CHECK6-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 42922// CHECK6-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 82923// CHECK6-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARGC_ADDR]], align 42924// CHECK6-NEXT: store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 42925// CHECK6-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 82926// CHECK6-NEXT: store i64 9, ptr [[DOTOMP_UB]], align 82927// CHECK6-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTOMP_LB]], align 82928// CHECK6-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i322929// CHECK6-NEXT: store i32 [[CONV]], ptr [[DOTOMP_IV]], align 42930// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]2931// CHECK6: omp.inner.for.cond:2932// CHECK6-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42933// CHECK6-NEXT: [[CONV1:%.*]] = sext i32 [[TMP2]] to i642934// CHECK6-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 82935// CHECK6-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV1]], [[TMP3]]2936// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2937// CHECK6: omp.inner.for.body:2938// CHECK6-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42939// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 12940// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]2941// CHECK6-NEXT: store i32 [[ADD]], ptr [[I]], align 42942// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]2943// CHECK6: omp.body.continue:2944// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]2945// CHECK6: omp.inner.for.inc:2946// CHECK6-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42947// CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP5]], 12948// CHECK6-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 42949// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]2950// CHECK6: omp.inner.for.end:2951// CHECK6-NEXT: store i32 10, ptr [[I]], align 42952// CHECK6-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARGC_ADDR]], align 42953// CHECK6-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_3]], align 42954// CHECK6-NEXT: store i64 0, ptr [[DOTOMP_LB5]], align 82955// CHECK6-NEXT: store i64 9, ptr [[DOTOMP_UB6]], align 82956// CHECK6-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_LB5]], align 82957// CHECK6-NEXT: [[CONV8:%.*]] = trunc i64 [[TMP7]] to i322958// CHECK6-NEXT: store i32 [[CONV8]], ptr [[DOTOMP_IV7]], align 42959// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND10:%.*]]2960// CHECK6: omp.inner.for.cond10:2961// CHECK6-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]]2962// CHECK6-NEXT: [[CONV11:%.*]] = sext i32 [[TMP8]] to i642963// CHECK6-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB6]], align 8, !llvm.access.group [[ACC_GRP5]]2964// CHECK6-NEXT: [[CMP12:%.*]] = icmp ule i64 [[CONV11]], [[TMP9]]2965// CHECK6-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY13:%.*]], label [[OMP_INNER_FOR_END19:%.*]]2966// CHECK6: omp.inner.for.body13:2967// CHECK6-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 4, !llvm.access.group [[ACC_GRP5]]2968// CHECK6-NEXT: [[MUL14:%.*]] = mul nsw i32 [[TMP10]], 12969// CHECK6-NEXT: [[ADD15:%.*]] = add nsw i32 0, [[MUL14]]2970// CHECK6-NEXT: store i32 [[ADD15]], ptr [[I9]], align 4, !llvm.access.group [[ACC_GRP5]]2971// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]]2972// CHECK6: omp.body.continue16:2973// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]]2974// CHECK6: omp.inner.for.inc17:2975// CHECK6-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 4, !llvm.access.group [[ACC_GRP5]]2976// CHECK6-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP11]], 12977// CHECK6-NEXT: store i32 [[ADD18]], ptr [[DOTOMP_IV7]], align 4, !llvm.access.group [[ACC_GRP5]]2978// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP6:![0-9]+]]2979// CHECK6: omp.inner.for.end19:2980// CHECK6-NEXT: store i32 10, ptr [[I9]], align 42981// CHECK6-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARGC_ADDR]], align 42982// CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP12]], 02983// CHECK6-NEXT: [[STOREDV:%.*]] = zext i1 [[TOBOOL]] to i82984// CHECK6-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_21]], align 12985// CHECK6-NEXT: [[TMP13:%.*]] = load i32, ptr [[ARGC_ADDR]], align 42986// CHECK6-NEXT: store i32 [[TMP13]], ptr [[DOTCAPTURE_EXPR_22]], align 42987// CHECK6-NEXT: [[TMP14:%.*]] = load i32, ptr [[ARGC_ADDR]], align 42988// CHECK6-NEXT: store i32 [[TMP14]], ptr [[DOTCAPTURE_EXPR_25]], align 42989// CHECK6-NEXT: [[TMP15:%.*]] = load i32, ptr [[ARGC_ADDR]], align 42990// CHECK6-NEXT: store i32 [[TMP15]], ptr [[DOTCAPTURE_EXPR_26]], align 42991// CHECK6-NEXT: [[TMP16:%.*]] = load ptr, ptr [[ARGV_ADDR]], align 82992// CHECK6-NEXT: [[TMP17:%.*]] = load i32, ptr [[ARGC_ADDR]], align 42993// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i642994// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds ptr, ptr [[TMP16]], i64 [[IDXPROM]]2995// CHECK6-NEXT: [[TMP18:%.*]] = load ptr, ptr [[ARRAYIDX]], align 82996// CHECK6-NEXT: [[TMP19:%.*]] = load i32, ptr [[ARGC_ADDR]], align 42997// CHECK6-NEXT: [[IDXPROM28:%.*]] = sext i32 [[TMP19]] to i642998// CHECK6-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds i8, ptr [[TMP18]], i64 [[IDXPROM28]]2999// CHECK6-NEXT: [[TMP20:%.*]] = load i8, ptr [[ARRAYIDX29]], align 13000// CHECK6-NEXT: [[CONV30:%.*]] = sext i8 [[TMP20]] to i323001// CHECK6-NEXT: store i32 [[CONV30]], ptr [[DOTCAPTURE_EXPR_27]], align 43002// CHECK6-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_25]], align 43003// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP21]], 03004// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 13005// CHECK6-NEXT: [[CONV32:%.*]] = sext i32 [[DIV]] to i643006// CHECK6-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 43007// CHECK6-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 43008// CHECK6-NEXT: [[SUB33:%.*]] = sub i32 [[TMP22]], [[TMP23]]3009// CHECK6-NEXT: [[SUB34:%.*]] = sub i32 [[SUB33]], 13010// CHECK6-NEXT: [[ADD35:%.*]] = add i32 [[SUB34]], 13011// CHECK6-NEXT: [[DIV36:%.*]] = udiv i32 [[ADD35]], 13012// CHECK6-NEXT: [[CONV37:%.*]] = zext i32 [[DIV36]] to i643013// CHECK6-NEXT: [[MUL38:%.*]] = mul nsw i64 [[CONV32]], [[CONV37]]3014// CHECK6-NEXT: [[SUB39:%.*]] = sub nsw i64 [[MUL38]], 13015// CHECK6-NEXT: store i64 [[SUB39]], ptr [[DOTCAPTURE_EXPR_31]], align 83016// CHECK6-NEXT: store i64 0, ptr [[DOTOMP_LB40]], align 83017// CHECK6-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_31]], align 83018// CHECK6-NEXT: store i64 [[TMP24]], ptr [[DOTOMP_UB41]], align 83019// CHECK6-NEXT: store i32 0, ptr [[I42]], align 43020// CHECK6-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 43021// CHECK6-NEXT: store i32 [[TMP25]], ptr [[J]], align 43022// CHECK6-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_25]], align 43023// CHECK6-NEXT: [[CMP43:%.*]] = icmp slt i32 0, [[TMP26]]3024// CHECK6-NEXT: br i1 [[CMP43]], label [[LAND_LHS_TRUE:%.*]], label [[SIMD_IF_END:%.*]]3025// CHECK6: land.lhs.true:3026// CHECK6-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 43027// CHECK6-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 43028// CHECK6-NEXT: [[CMP44:%.*]] = icmp slt i32 [[TMP27]], [[TMP28]]3029// CHECK6-NEXT: br i1 [[CMP44]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END]]3030// CHECK6: simd.if.then:3031// CHECK6-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTOMP_LB40]], align 83032// CHECK6-NEXT: store i64 [[TMP29]], ptr [[DOTOMP_IV45]], align 83033// CHECK6-NEXT: [[TMP30:%.*]] = load ptr, ptr [[ARGV_ADDR]], align 83034// CHECK6-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[TMP30]], i64 8) ]3035// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND48:%.*]]3036// CHECK6: omp.inner.for.cond48:3037// CHECK6-NEXT: [[TMP31:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9:![0-9]+]]3038// CHECK6-NEXT: [[TMP32:%.*]] = load i64, ptr [[DOTOMP_UB41]], align 8, !llvm.access.group [[ACC_GRP9]]3039// CHECK6-NEXT: [[CMP49:%.*]] = icmp ule i64 [[TMP31]], [[TMP32]]3040// CHECK6-NEXT: br i1 [[CMP49]], label [[OMP_INNER_FOR_BODY50:%.*]], label [[OMP_INNER_FOR_END83:%.*]]3041// CHECK6: omp.inner.for.body50:3042// CHECK6-NEXT: [[TMP33:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9]]3043// CHECK6-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 4, !llvm.access.group [[ACC_GRP9]]3044// CHECK6-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4, !llvm.access.group [[ACC_GRP9]]3045// CHECK6-NEXT: [[SUB51:%.*]] = sub i32 [[TMP34]], [[TMP35]]3046// CHECK6-NEXT: [[SUB52:%.*]] = sub i32 [[SUB51]], 13047// CHECK6-NEXT: [[ADD53:%.*]] = add i32 [[SUB52]], 13048// CHECK6-NEXT: [[DIV54:%.*]] = udiv i32 [[ADD53]], 13049// CHECK6-NEXT: [[MUL55:%.*]] = mul i32 1, [[DIV54]]3050// CHECK6-NEXT: [[CONV56:%.*]] = zext i32 [[MUL55]] to i643051// CHECK6-NEXT: [[DIV57:%.*]] = sdiv i64 [[TMP33]], [[CONV56]]3052// CHECK6-NEXT: [[MUL58:%.*]] = mul nsw i64 [[DIV57]], 13053// CHECK6-NEXT: [[ADD59:%.*]] = add nsw i64 0, [[MUL58]]3054// CHECK6-NEXT: [[CONV60:%.*]] = trunc i64 [[ADD59]] to i323055// CHECK6-NEXT: store i32 [[CONV60]], ptr [[I46]], align 4, !llvm.access.group [[ACC_GRP9]]3056// CHECK6-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4, !llvm.access.group [[ACC_GRP9]]3057// CHECK6-NEXT: [[CONV61:%.*]] = sext i32 [[TMP36]] to i643058// CHECK6-NEXT: [[TMP37:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9]]3059// CHECK6-NEXT: [[TMP38:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9]]3060// CHECK6-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 4, !llvm.access.group [[ACC_GRP9]]3061// CHECK6-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4, !llvm.access.group [[ACC_GRP9]]3062// CHECK6-NEXT: [[SUB62:%.*]] = sub i32 [[TMP39]], [[TMP40]]3063// CHECK6-NEXT: [[SUB63:%.*]] = sub i32 [[SUB62]], 13064// CHECK6-NEXT: [[ADD64:%.*]] = add i32 [[SUB63]], 13065// CHECK6-NEXT: [[DIV65:%.*]] = udiv i32 [[ADD64]], 13066// CHECK6-NEXT: [[MUL66:%.*]] = mul i32 1, [[DIV65]]3067// CHECK6-NEXT: [[CONV67:%.*]] = zext i32 [[MUL66]] to i643068// CHECK6-NEXT: [[DIV68:%.*]] = sdiv i64 [[TMP38]], [[CONV67]]3069// CHECK6-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 4, !llvm.access.group [[ACC_GRP9]]3070// CHECK6-NEXT: [[TMP42:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4, !llvm.access.group [[ACC_GRP9]]3071// CHECK6-NEXT: [[SUB69:%.*]] = sub i32 [[TMP41]], [[TMP42]]3072// CHECK6-NEXT: [[SUB70:%.*]] = sub i32 [[SUB69]], 13073// CHECK6-NEXT: [[ADD71:%.*]] = add i32 [[SUB70]], 13074// CHECK6-NEXT: [[DIV72:%.*]] = udiv i32 [[ADD71]], 13075// CHECK6-NEXT: [[MUL73:%.*]] = mul i32 1, [[DIV72]]3076// CHECK6-NEXT: [[CONV74:%.*]] = zext i32 [[MUL73]] to i643077// CHECK6-NEXT: [[MUL75:%.*]] = mul nsw i64 [[DIV68]], [[CONV74]]3078// CHECK6-NEXT: [[SUB76:%.*]] = sub nsw i64 [[TMP37]], [[MUL75]]3079// CHECK6-NEXT: [[MUL77:%.*]] = mul nsw i64 [[SUB76]], 13080// CHECK6-NEXT: [[ADD78:%.*]] = add nsw i64 [[CONV61]], [[MUL77]]3081// CHECK6-NEXT: [[CONV79:%.*]] = trunc i64 [[ADD78]] to i323082// CHECK6-NEXT: store i32 [[CONV79]], ptr [[J47]], align 4, !llvm.access.group [[ACC_GRP9]]3083// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE80:%.*]]3084// CHECK6: omp.body.continue80:3085// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC81:%.*]]3086// CHECK6: omp.inner.for.inc81:3087// CHECK6-NEXT: [[TMP43:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9]]3088// CHECK6-NEXT: [[ADD82:%.*]] = add nsw i64 [[TMP43]], 13089// CHECK6-NEXT: store i64 [[ADD82]], ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9]]3090// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND48]], !llvm.loop [[LOOP10:![0-9]+]]3091// CHECK6: omp.inner.for.end83:3092// CHECK6-NEXT: [[TMP44:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_25]], align 43093// CHECK6-NEXT: [[SUB84:%.*]] = sub nsw i32 [[TMP44]], 03094// CHECK6-NEXT: [[DIV85:%.*]] = sdiv i32 [[SUB84]], 13095// CHECK6-NEXT: [[MUL86:%.*]] = mul nsw i32 [[DIV85]], 13096// CHECK6-NEXT: [[ADD87:%.*]] = add nsw i32 0, [[MUL86]]3097// CHECK6-NEXT: store i32 [[ADD87]], ptr [[I20]], align 43098// CHECK6-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 43099// CHECK6-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 43100// CHECK6-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 43101// CHECK6-NEXT: [[SUB88:%.*]] = sub i32 [[TMP46]], [[TMP47]]3102// CHECK6-NEXT: [[SUB89:%.*]] = sub i32 [[SUB88]], 13103// CHECK6-NEXT: [[ADD90:%.*]] = add i32 [[SUB89]], 13104// CHECK6-NEXT: [[DIV91:%.*]] = udiv i32 [[ADD90]], 13105// CHECK6-NEXT: [[MUL92:%.*]] = mul i32 [[DIV91]], 13106// CHECK6-NEXT: [[ADD93:%.*]] = add i32 [[TMP45]], [[MUL92]]3107// CHECK6-NEXT: store i32 [[ADD93]], ptr [[J47]], align 43108// CHECK6-NEXT: br label [[SIMD_IF_END]]3109// CHECK6: simd.if.end:3110// CHECK6-NEXT: [[TMP48:%.*]] = load i32, ptr [[RETVAL]], align 43111// CHECK6-NEXT: ret i32 [[TMP48]]3112//3113//3114// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init3115// CHECK6-SAME: () #[[ATTR2:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" {3116// CHECK6-NEXT: entry:3117// CHECK6-NEXT: call void @_ZN1SC1Ei(ptr noundef nonnull align 4 dereferenceable(4) @s, i32 noundef 1)3118// CHECK6-NEXT: ret void3119//3120//3121// CHECK6-LABEL: define {{[^@]+}}@_ZN1SC1Ei3122// CHECK6-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR3:[0-9]+]] align 2 {3123// CHECK6-NEXT: entry:3124// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 83125// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca i32, align 43126// CHECK6-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 83127// CHECK6-NEXT: store i32 [[C]], ptr [[C_ADDR]], align 43128// CHECK6-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 83129// CHECK6-NEXT: [[TMP0:%.*]] = load i32, ptr [[C_ADDR]], align 43130// CHECK6-NEXT: call void @_ZN1SC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])3131// CHECK6-NEXT: ret void3132//3133//3134// CHECK6-LABEL: define {{[^@]+}}@_ZN1SC2Ei3135// CHECK6-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR3]] align 2 {3136// CHECK6-NEXT: entry:3137// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 83138// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca i32, align 43139// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 13140// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 43141// CHECK6-NEXT: [[_TMP2:%.*]] = alloca ptr, align 83142// CHECK6-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 43143// CHECK6-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 43144// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 83145// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 83146// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 43147// CHECK6-NEXT: [[_TMP6:%.*]] = alloca ptr, align 83148// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 43149// CHECK6-NEXT: [[A8:%.*]] = alloca i32, align 43150// CHECK6-NEXT: [[_TMP9:%.*]] = alloca ptr, align 83151// CHECK6-NEXT: [[_TMP14:%.*]] = alloca ptr, align 83152// CHECK6-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 83153// CHECK6-NEXT: store i32 [[C]], ptr [[C_ADDR]], align 43154// CHECK6-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 83155// CHECK6-NEXT: [[TMP0:%.*]] = load i32, ptr [[C_ADDR]], align 43156// CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 03157// CHECK6-NEXT: [[STOREDV:%.*]] = zext i1 [[TOBOOL]] to i83158// CHECK6-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_]], align 13159// CHECK6-NEXT: store ptr [[TMP]], ptr [[_TMP2]], align 83160// CHECK6-NEXT: [[TMP1:%.*]] = load i32, ptr [[C_ADDR]], align 43161// CHECK6-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_3]], align 43162// CHECK6-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 43163// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 03164// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 13165// CHECK6-NEXT: [[SUB5:%.*]] = sub nsw i32 [[DIV]], 13166// CHECK6-NEXT: store i32 [[SUB5]], ptr [[DOTCAPTURE_EXPR_4]], align 43167// CHECK6-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 83168// CHECK6-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 43169// CHECK6-NEXT: [[CONV:%.*]] = sext i32 [[TMP3]] to i643170// CHECK6-NEXT: store i64 [[CONV]], ptr [[DOTOMP_UB]], align 83171// CHECK6-NEXT: store ptr [[A]], ptr [[_TMP6]], align 83172// CHECK6-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP6]], align 8, !nonnull [[META12:![0-9]+]], !align [[META13:![0-9]+]]3173// CHECK6-NEXT: store i32 0, ptr [[TMP4]], align 43174// CHECK6-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 43175// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]3176// CHECK6-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]3177// CHECK6: simd.if.then:3178// CHECK6-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 83179// CHECK6-NEXT: [[CONV7:%.*]] = trunc i64 [[TMP6]] to i323180// CHECK6-NEXT: store i32 [[CONV7]], ptr [[DOTOMP_IV]], align 43181// CHECK6-NEXT: store ptr [[A8]], ptr [[_TMP9]], align 83182// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]3183// CHECK6: omp.inner.for.cond:3184// CHECK6-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14:![0-9]+]]3185// CHECK6-NEXT: [[CONV10:%.*]] = sext i32 [[TMP7]] to i643186// CHECK6-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP14]]3187// CHECK6-NEXT: [[CMP11:%.*]] = icmp ule i64 [[CONV10]], [[TMP8]]3188// CHECK6-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]3189// CHECK6: omp.inner.for.body:3190// CHECK6-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]3191// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 13192// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]3193// CHECK6-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP9]], align 8, !nonnull [[META12]], !align [[META13]], !llvm.access.group [[ACC_GRP14]]3194// CHECK6-NEXT: store i32 [[ADD]], ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP14]]3195// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]3196// CHECK6: omp.body.continue:3197// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]3198// CHECK6: omp.inner.for.inc:3199// CHECK6-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]3200// CHECK6-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP11]], 13201// CHECK6-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]3202// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]3203// CHECK6: omp.inner.for.end:3204// CHECK6-NEXT: [[A13:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 03205// CHECK6-NEXT: store ptr [[A13]], ptr [[_TMP14]], align 83206// CHECK6-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 43207// CHECK6-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP12]], 03208// CHECK6-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 13209// CHECK6-NEXT: [[MUL17:%.*]] = mul nsw i32 [[DIV16]], 13210// CHECK6-NEXT: [[ADD18:%.*]] = add nsw i32 0, [[MUL17]]3211// CHECK6-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP14]], align 8, !nonnull [[META12]], !align [[META13]]3212// CHECK6-NEXT: store i32 [[ADD18]], ptr [[TMP13]], align 43213// CHECK6-NEXT: br label [[SIMD_IF_END]]3214// CHECK6: simd.if.end:3215// CHECK6-NEXT: ret void3216//3217//3218// CHECK6-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_parallel_master_taskloop_simd_codegen.cpp3219// CHECK6-SAME: () #[[ATTR2]] section "__TEXT,__StaticInit,regular,pure_instructions" {3220// CHECK6-NEXT: entry:3221// CHECK6-NEXT: call void @__cxx_global_var_init()3222// CHECK6-NEXT: ret void3223//3224//3225// CHECK7-LABEL: define {{[^@]+}}@main3226// CHECK7-SAME: (i32 noundef [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {3227// CHECK7-NEXT: entry:3228// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 43229// CHECK7-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 43230// CHECK7-NEXT: [[ARGV_ADDR:%.*]] = alloca ptr, align 83231// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 43232// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 43233// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 83234// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 83235// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 43236// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 43237// CHECK7-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 43238// CHECK7-NEXT: [[_TMP4:%.*]] = alloca i32, align 43239// CHECK7-NEXT: [[DOTOMP_LB5:%.*]] = alloca i64, align 83240// CHECK7-NEXT: [[DOTOMP_UB6:%.*]] = alloca i64, align 83241// CHECK7-NEXT: [[DOTOMP_IV7:%.*]] = alloca i32, align 43242// CHECK7-NEXT: [[I9:%.*]] = alloca i32, align 43243// CHECK7-NEXT: [[I20:%.*]] = alloca i32, align 43244// CHECK7-NEXT: [[DOTCAPTURE_EXPR_21:%.*]] = alloca i8, align 13245// CHECK7-NEXT: [[DOTCAPTURE_EXPR_22:%.*]] = alloca i32, align 43246// CHECK7-NEXT: [[_TMP23:%.*]] = alloca i32, align 43247// CHECK7-NEXT: [[_TMP24:%.*]] = alloca i32, align 43248// CHECK7-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 43249// CHECK7-NEXT: [[DOTCAPTURE_EXPR_26:%.*]] = alloca i32, align 43250// CHECK7-NEXT: [[DOTCAPTURE_EXPR_27:%.*]] = alloca i32, align 43251// CHECK7-NEXT: [[DOTCAPTURE_EXPR_31:%.*]] = alloca i64, align 83252// CHECK7-NEXT: [[DOTOMP_LB40:%.*]] = alloca i64, align 83253// CHECK7-NEXT: [[DOTOMP_UB41:%.*]] = alloca i64, align 83254// CHECK7-NEXT: [[I42:%.*]] = alloca i32, align 43255// CHECK7-NEXT: [[J:%.*]] = alloca i32, align 43256// CHECK7-NEXT: [[DOTOMP_IV45:%.*]] = alloca i64, align 83257// CHECK7-NEXT: [[I46:%.*]] = alloca i32, align 43258// CHECK7-NEXT: [[J47:%.*]] = alloca i32, align 43259// CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 43260// CHECK7-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 43261// CHECK7-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 83262// CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARGC_ADDR]], align 43263// CHECK7-NEXT: store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 43264// CHECK7-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 83265// CHECK7-NEXT: store i64 9, ptr [[DOTOMP_UB]], align 83266// CHECK7-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTOMP_LB]], align 83267// CHECK7-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i323268// CHECK7-NEXT: store i32 [[CONV]], ptr [[DOTOMP_IV]], align 43269// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]3270// CHECK7: omp.inner.for.cond:3271// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43272// CHECK7-NEXT: [[CONV1:%.*]] = sext i32 [[TMP2]] to i643273// CHECK7-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 83274// CHECK7-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV1]], [[TMP3]]3275// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]3276// CHECK7: omp.inner.for.body:3277// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43278// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 13279// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]3280// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 43281// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]3282// CHECK7: omp.body.continue:3283// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]3284// CHECK7: omp.inner.for.inc:3285// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43286// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP5]], 13287// CHECK7-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 43288// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]3289// CHECK7: omp.inner.for.end:3290// CHECK7-NEXT: store i32 10, ptr [[I]], align 43291// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARGC_ADDR]], align 43292// CHECK7-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_3]], align 43293// CHECK7-NEXT: store i64 0, ptr [[DOTOMP_LB5]], align 83294// CHECK7-NEXT: store i64 9, ptr [[DOTOMP_UB6]], align 83295// CHECK7-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_LB5]], align 83296// CHECK7-NEXT: [[CONV8:%.*]] = trunc i64 [[TMP7]] to i323297// CHECK7-NEXT: store i32 [[CONV8]], ptr [[DOTOMP_IV7]], align 43298// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND10:%.*]]3299// CHECK7: omp.inner.for.cond10:3300// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]]3301// CHECK7-NEXT: [[CONV11:%.*]] = sext i32 [[TMP8]] to i643302// CHECK7-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB6]], align 8, !llvm.access.group [[ACC_GRP5]]3303// CHECK7-NEXT: [[CMP12:%.*]] = icmp ule i64 [[CONV11]], [[TMP9]]3304// CHECK7-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY13:%.*]], label [[OMP_INNER_FOR_END19:%.*]]3305// CHECK7: omp.inner.for.body13:3306// CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 4, !llvm.access.group [[ACC_GRP5]]3307// CHECK7-NEXT: [[MUL14:%.*]] = mul nsw i32 [[TMP10]], 13308// CHECK7-NEXT: [[ADD15:%.*]] = add nsw i32 0, [[MUL14]]3309// CHECK7-NEXT: store i32 [[ADD15]], ptr [[I9]], align 4, !llvm.access.group [[ACC_GRP5]]3310// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]]3311// CHECK7: omp.body.continue16:3312// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]]3313// CHECK7: omp.inner.for.inc17:3314// CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 4, !llvm.access.group [[ACC_GRP5]]3315// CHECK7-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP11]], 13316// CHECK7-NEXT: store i32 [[ADD18]], ptr [[DOTOMP_IV7]], align 4, !llvm.access.group [[ACC_GRP5]]3317// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP6:![0-9]+]]3318// CHECK7: omp.inner.for.end19:3319// CHECK7-NEXT: store i32 10, ptr [[I9]], align 43320// CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARGC_ADDR]], align 43321// CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP12]], 03322// CHECK7-NEXT: [[STOREDV:%.*]] = zext i1 [[TOBOOL]] to i83323// CHECK7-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_21]], align 13324// CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[ARGC_ADDR]], align 43325// CHECK7-NEXT: store i32 [[TMP13]], ptr [[DOTCAPTURE_EXPR_22]], align 43326// CHECK7-NEXT: [[TMP14:%.*]] = load i32, ptr [[ARGC_ADDR]], align 43327// CHECK7-NEXT: store i32 [[TMP14]], ptr [[DOTCAPTURE_EXPR_25]], align 43328// CHECK7-NEXT: [[TMP15:%.*]] = load i32, ptr [[ARGC_ADDR]], align 43329// CHECK7-NEXT: store i32 [[TMP15]], ptr [[DOTCAPTURE_EXPR_26]], align 43330// CHECK7-NEXT: [[TMP16:%.*]] = load ptr, ptr [[ARGV_ADDR]], align 83331// CHECK7-NEXT: [[TMP17:%.*]] = load i32, ptr [[ARGC_ADDR]], align 43332// CHECK7-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i643333// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds ptr, ptr [[TMP16]], i64 [[IDXPROM]]3334// CHECK7-NEXT: [[TMP18:%.*]] = load ptr, ptr [[ARRAYIDX]], align 83335// CHECK7-NEXT: [[TMP19:%.*]] = load i32, ptr [[ARGC_ADDR]], align 43336// CHECK7-NEXT: [[IDXPROM28:%.*]] = sext i32 [[TMP19]] to i643337// CHECK7-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds i8, ptr [[TMP18]], i64 [[IDXPROM28]]3338// CHECK7-NEXT: [[TMP20:%.*]] = load i8, ptr [[ARRAYIDX29]], align 13339// CHECK7-NEXT: [[CONV30:%.*]] = sext i8 [[TMP20]] to i323340// CHECK7-NEXT: store i32 [[CONV30]], ptr [[DOTCAPTURE_EXPR_27]], align 43341// CHECK7-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_25]], align 43342// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP21]], 03343// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 13344// CHECK7-NEXT: [[CONV32:%.*]] = sext i32 [[DIV]] to i643345// CHECK7-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 43346// CHECK7-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 43347// CHECK7-NEXT: [[SUB33:%.*]] = sub i32 [[TMP22]], [[TMP23]]3348// CHECK7-NEXT: [[SUB34:%.*]] = sub i32 [[SUB33]], 13349// CHECK7-NEXT: [[ADD35:%.*]] = add i32 [[SUB34]], 13350// CHECK7-NEXT: [[DIV36:%.*]] = udiv i32 [[ADD35]], 13351// CHECK7-NEXT: [[CONV37:%.*]] = zext i32 [[DIV36]] to i643352// CHECK7-NEXT: [[MUL38:%.*]] = mul nsw i64 [[CONV32]], [[CONV37]]3353// CHECK7-NEXT: [[SUB39:%.*]] = sub nsw i64 [[MUL38]], 13354// CHECK7-NEXT: store i64 [[SUB39]], ptr [[DOTCAPTURE_EXPR_31]], align 83355// CHECK7-NEXT: store i64 0, ptr [[DOTOMP_LB40]], align 83356// CHECK7-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_31]], align 83357// CHECK7-NEXT: store i64 [[TMP24]], ptr [[DOTOMP_UB41]], align 83358// CHECK7-NEXT: store i32 0, ptr [[I42]], align 43359// CHECK7-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 43360// CHECK7-NEXT: store i32 [[TMP25]], ptr [[J]], align 43361// CHECK7-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_25]], align 43362// CHECK7-NEXT: [[CMP43:%.*]] = icmp slt i32 0, [[TMP26]]3363// CHECK7-NEXT: br i1 [[CMP43]], label [[LAND_LHS_TRUE:%.*]], label [[SIMD_IF_END:%.*]]3364// CHECK7: land.lhs.true:3365// CHECK7-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 43366// CHECK7-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 43367// CHECK7-NEXT: [[CMP44:%.*]] = icmp slt i32 [[TMP27]], [[TMP28]]3368// CHECK7-NEXT: br i1 [[CMP44]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END]]3369// CHECK7: simd.if.then:3370// CHECK7-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTOMP_LB40]], align 83371// CHECK7-NEXT: store i64 [[TMP29]], ptr [[DOTOMP_IV45]], align 83372// CHECK7-NEXT: [[TMP30:%.*]] = load ptr, ptr [[ARGV_ADDR]], align 83373// CHECK7-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[TMP30]], i64 8) ]3374// CHECK7-NEXT: [[TMP31:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_21]], align 13375// CHECK7-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP31]] to i13376// CHECK7-NEXT: br i1 [[LOADEDV]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]3377// CHECK7: omp_if.then:3378// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND48:%.*]]3379// CHECK7: omp.inner.for.cond48:3380// CHECK7-NEXT: [[TMP32:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9:![0-9]+]]3381// CHECK7-NEXT: [[TMP33:%.*]] = load i64, ptr [[DOTOMP_UB41]], align 8, !llvm.access.group [[ACC_GRP9]]3382// CHECK7-NEXT: [[CMP49:%.*]] = icmp ule i64 [[TMP32]], [[TMP33]]3383// CHECK7-NEXT: br i1 [[CMP49]], label [[OMP_INNER_FOR_BODY50:%.*]], label [[OMP_INNER_FOR_END83:%.*]]3384// CHECK7: omp.inner.for.body50:3385// CHECK7-NEXT: [[TMP34:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9]]3386// CHECK7-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 4, !llvm.access.group [[ACC_GRP9]]3387// CHECK7-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4, !llvm.access.group [[ACC_GRP9]]3388// CHECK7-NEXT: [[SUB51:%.*]] = sub i32 [[TMP35]], [[TMP36]]3389// CHECK7-NEXT: [[SUB52:%.*]] = sub i32 [[SUB51]], 13390// CHECK7-NEXT: [[ADD53:%.*]] = add i32 [[SUB52]], 13391// CHECK7-NEXT: [[DIV54:%.*]] = udiv i32 [[ADD53]], 13392// CHECK7-NEXT: [[MUL55:%.*]] = mul i32 1, [[DIV54]]3393// CHECK7-NEXT: [[CONV56:%.*]] = zext i32 [[MUL55]] to i643394// CHECK7-NEXT: [[DIV57:%.*]] = sdiv i64 [[TMP34]], [[CONV56]]3395// CHECK7-NEXT: [[MUL58:%.*]] = mul nsw i64 [[DIV57]], 13396// CHECK7-NEXT: [[ADD59:%.*]] = add nsw i64 0, [[MUL58]]3397// CHECK7-NEXT: [[CONV60:%.*]] = trunc i64 [[ADD59]] to i323398// CHECK7-NEXT: store i32 [[CONV60]], ptr [[I46]], align 4, !llvm.access.group [[ACC_GRP9]]3399// CHECK7-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4, !llvm.access.group [[ACC_GRP9]]3400// CHECK7-NEXT: [[CONV61:%.*]] = sext i32 [[TMP37]] to i643401// CHECK7-NEXT: [[TMP38:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9]]3402// CHECK7-NEXT: [[TMP39:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9]]3403// CHECK7-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 4, !llvm.access.group [[ACC_GRP9]]3404// CHECK7-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4, !llvm.access.group [[ACC_GRP9]]3405// CHECK7-NEXT: [[SUB62:%.*]] = sub i32 [[TMP40]], [[TMP41]]3406// CHECK7-NEXT: [[SUB63:%.*]] = sub i32 [[SUB62]], 13407// CHECK7-NEXT: [[ADD64:%.*]] = add i32 [[SUB63]], 13408// CHECK7-NEXT: [[DIV65:%.*]] = udiv i32 [[ADD64]], 13409// CHECK7-NEXT: [[MUL66:%.*]] = mul i32 1, [[DIV65]]3410// CHECK7-NEXT: [[CONV67:%.*]] = zext i32 [[MUL66]] to i643411// CHECK7-NEXT: [[DIV68:%.*]] = sdiv i64 [[TMP39]], [[CONV67]]3412// CHECK7-NEXT: [[TMP42:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 4, !llvm.access.group [[ACC_GRP9]]3413// CHECK7-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4, !llvm.access.group [[ACC_GRP9]]3414// CHECK7-NEXT: [[SUB69:%.*]] = sub i32 [[TMP42]], [[TMP43]]3415// CHECK7-NEXT: [[SUB70:%.*]] = sub i32 [[SUB69]], 13416// CHECK7-NEXT: [[ADD71:%.*]] = add i32 [[SUB70]], 13417// CHECK7-NEXT: [[DIV72:%.*]] = udiv i32 [[ADD71]], 13418// CHECK7-NEXT: [[MUL73:%.*]] = mul i32 1, [[DIV72]]3419// CHECK7-NEXT: [[CONV74:%.*]] = zext i32 [[MUL73]] to i643420// CHECK7-NEXT: [[MUL75:%.*]] = mul nsw i64 [[DIV68]], [[CONV74]]3421// CHECK7-NEXT: [[SUB76:%.*]] = sub nsw i64 [[TMP38]], [[MUL75]]3422// CHECK7-NEXT: [[MUL77:%.*]] = mul nsw i64 [[SUB76]], 13423// CHECK7-NEXT: [[ADD78:%.*]] = add nsw i64 [[CONV61]], [[MUL77]]3424// CHECK7-NEXT: [[CONV79:%.*]] = trunc i64 [[ADD78]] to i323425// CHECK7-NEXT: store i32 [[CONV79]], ptr [[J47]], align 4, !llvm.access.group [[ACC_GRP9]]3426// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE80:%.*]]3427// CHECK7: omp.body.continue80:3428// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC81:%.*]]3429// CHECK7: omp.inner.for.inc81:3430// CHECK7-NEXT: [[TMP44:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9]]3431// CHECK7-NEXT: [[ADD82:%.*]] = add nsw i64 [[TMP44]], 13432// CHECK7-NEXT: store i64 [[ADD82]], ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9]]3433// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND48]], !llvm.loop [[LOOP10:![0-9]+]]3434// CHECK7: omp.inner.for.end83:3435// CHECK7-NEXT: br label [[OMP_IF_END:%.*]]3436// CHECK7: omp_if.else:3437// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND84:%.*]]3438// CHECK7: omp.inner.for.cond84:3439// CHECK7-NEXT: [[TMP45:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 83440// CHECK7-NEXT: [[TMP46:%.*]] = load i64, ptr [[DOTOMP_UB41]], align 83441// CHECK7-NEXT: [[CMP85:%.*]] = icmp ule i64 [[TMP45]], [[TMP46]]3442// CHECK7-NEXT: br i1 [[CMP85]], label [[OMP_INNER_FOR_BODY86:%.*]], label [[OMP_INNER_FOR_END119:%.*]]3443// CHECK7: omp.inner.for.body86:3444// CHECK7-NEXT: [[TMP47:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 83445// CHECK7-NEXT: [[TMP48:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 43446// CHECK7-NEXT: [[TMP49:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 43447// CHECK7-NEXT: [[SUB87:%.*]] = sub i32 [[TMP48]], [[TMP49]]3448// CHECK7-NEXT: [[SUB88:%.*]] = sub i32 [[SUB87]], 13449// CHECK7-NEXT: [[ADD89:%.*]] = add i32 [[SUB88]], 13450// CHECK7-NEXT: [[DIV90:%.*]] = udiv i32 [[ADD89]], 13451// CHECK7-NEXT: [[MUL91:%.*]] = mul i32 1, [[DIV90]]3452// CHECK7-NEXT: [[CONV92:%.*]] = zext i32 [[MUL91]] to i643453// CHECK7-NEXT: [[DIV93:%.*]] = sdiv i64 [[TMP47]], [[CONV92]]3454// CHECK7-NEXT: [[MUL94:%.*]] = mul nsw i64 [[DIV93]], 13455// CHECK7-NEXT: [[ADD95:%.*]] = add nsw i64 0, [[MUL94]]3456// CHECK7-NEXT: [[CONV96:%.*]] = trunc i64 [[ADD95]] to i323457// CHECK7-NEXT: store i32 [[CONV96]], ptr [[I46]], align 43458// CHECK7-NEXT: [[TMP50:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 43459// CHECK7-NEXT: [[CONV97:%.*]] = sext i32 [[TMP50]] to i643460// CHECK7-NEXT: [[TMP51:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 83461// CHECK7-NEXT: [[TMP52:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 83462// CHECK7-NEXT: [[TMP53:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 43463// CHECK7-NEXT: [[TMP54:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 43464// CHECK7-NEXT: [[SUB98:%.*]] = sub i32 [[TMP53]], [[TMP54]]3465// CHECK7-NEXT: [[SUB99:%.*]] = sub i32 [[SUB98]], 13466// CHECK7-NEXT: [[ADD100:%.*]] = add i32 [[SUB99]], 13467// CHECK7-NEXT: [[DIV101:%.*]] = udiv i32 [[ADD100]], 13468// CHECK7-NEXT: [[MUL102:%.*]] = mul i32 1, [[DIV101]]3469// CHECK7-NEXT: [[CONV103:%.*]] = zext i32 [[MUL102]] to i643470// CHECK7-NEXT: [[DIV104:%.*]] = sdiv i64 [[TMP52]], [[CONV103]]3471// CHECK7-NEXT: [[TMP55:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 43472// CHECK7-NEXT: [[TMP56:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 43473// CHECK7-NEXT: [[SUB105:%.*]] = sub i32 [[TMP55]], [[TMP56]]3474// CHECK7-NEXT: [[SUB106:%.*]] = sub i32 [[SUB105]], 13475// CHECK7-NEXT: [[ADD107:%.*]] = add i32 [[SUB106]], 13476// CHECK7-NEXT: [[DIV108:%.*]] = udiv i32 [[ADD107]], 13477// CHECK7-NEXT: [[MUL109:%.*]] = mul i32 1, [[DIV108]]3478// CHECK7-NEXT: [[CONV110:%.*]] = zext i32 [[MUL109]] to i643479// CHECK7-NEXT: [[MUL111:%.*]] = mul nsw i64 [[DIV104]], [[CONV110]]3480// CHECK7-NEXT: [[SUB112:%.*]] = sub nsw i64 [[TMP51]], [[MUL111]]3481// CHECK7-NEXT: [[MUL113:%.*]] = mul nsw i64 [[SUB112]], 13482// CHECK7-NEXT: [[ADD114:%.*]] = add nsw i64 [[CONV97]], [[MUL113]]3483// CHECK7-NEXT: [[CONV115:%.*]] = trunc i64 [[ADD114]] to i323484// CHECK7-NEXT: store i32 [[CONV115]], ptr [[J47]], align 43485// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE116:%.*]]3486// CHECK7: omp.body.continue116:3487// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC117:%.*]]3488// CHECK7: omp.inner.for.inc117:3489// CHECK7-NEXT: [[TMP57:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 83490// CHECK7-NEXT: [[ADD118:%.*]] = add nsw i64 [[TMP57]], 13491// CHECK7-NEXT: store i64 [[ADD118]], ptr [[DOTOMP_IV45]], align 83492// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND84]], !llvm.loop [[LOOP12:![0-9]+]]3493// CHECK7: omp.inner.for.end119:3494// CHECK7-NEXT: br label [[OMP_IF_END]]3495// CHECK7: omp_if.end:3496// CHECK7-NEXT: [[TMP58:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_25]], align 43497// CHECK7-NEXT: [[SUB120:%.*]] = sub nsw i32 [[TMP58]], 03498// CHECK7-NEXT: [[DIV121:%.*]] = sdiv i32 [[SUB120]], 13499// CHECK7-NEXT: [[MUL122:%.*]] = mul nsw i32 [[DIV121]], 13500// CHECK7-NEXT: [[ADD123:%.*]] = add nsw i32 0, [[MUL122]]3501// CHECK7-NEXT: store i32 [[ADD123]], ptr [[I20]], align 43502// CHECK7-NEXT: [[TMP59:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 43503// CHECK7-NEXT: [[TMP60:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 43504// CHECK7-NEXT: [[TMP61:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 43505// CHECK7-NEXT: [[SUB124:%.*]] = sub i32 [[TMP60]], [[TMP61]]3506// CHECK7-NEXT: [[SUB125:%.*]] = sub i32 [[SUB124]], 13507// CHECK7-NEXT: [[ADD126:%.*]] = add i32 [[SUB125]], 13508// CHECK7-NEXT: [[DIV127:%.*]] = udiv i32 [[ADD126]], 13509// CHECK7-NEXT: [[MUL128:%.*]] = mul i32 [[DIV127]], 13510// CHECK7-NEXT: [[ADD129:%.*]] = add i32 [[TMP59]], [[MUL128]]3511// CHECK7-NEXT: store i32 [[ADD129]], ptr [[J47]], align 43512// CHECK7-NEXT: br label [[SIMD_IF_END]]3513// CHECK7: simd.if.end:3514// CHECK7-NEXT: [[TMP62:%.*]] = load i32, ptr [[RETVAL]], align 43515// CHECK7-NEXT: ret i32 [[TMP62]]3516//3517//3518// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init3519// CHECK7-SAME: () #[[ATTR2:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" {3520// CHECK7-NEXT: entry:3521// CHECK7-NEXT: call void @_ZN1SC1Ei(ptr noundef nonnull align 4 dereferenceable(4) @s, i32 noundef 1)3522// CHECK7-NEXT: ret void3523//3524//3525// CHECK7-LABEL: define {{[^@]+}}@_ZN1SC1Ei3526// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR3:[0-9]+]] align 2 {3527// CHECK7-NEXT: entry:3528// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 83529// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i32, align 43530// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 83531// CHECK7-NEXT: store i32 [[C]], ptr [[C_ADDR]], align 43532// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 83533// CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[C_ADDR]], align 43534// CHECK7-NEXT: call void @_ZN1SC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])3535// CHECK7-NEXT: ret void3536//3537//3538// CHECK7-LABEL: define {{[^@]+}}@_ZN1SC2Ei3539// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR3]] align 2 {3540// CHECK7-NEXT: entry:3541// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 83542// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i32, align 43543// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 13544// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 43545// CHECK7-NEXT: [[_TMP2:%.*]] = alloca ptr, align 83546// CHECK7-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 43547// CHECK7-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 43548// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 83549// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 83550// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 43551// CHECK7-NEXT: [[_TMP6:%.*]] = alloca ptr, align 83552// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 43553// CHECK7-NEXT: [[A8:%.*]] = alloca i32, align 43554// CHECK7-NEXT: [[_TMP9:%.*]] = alloca ptr, align 83555// CHECK7-NEXT: [[_TMP14:%.*]] = alloca ptr, align 83556// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 83557// CHECK7-NEXT: store i32 [[C]], ptr [[C_ADDR]], align 43558// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 83559// CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[C_ADDR]], align 43560// CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 03561// CHECK7-NEXT: [[STOREDV:%.*]] = zext i1 [[TOBOOL]] to i83562// CHECK7-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_]], align 13563// CHECK7-NEXT: store ptr [[TMP]], ptr [[_TMP2]], align 83564// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[C_ADDR]], align 43565// CHECK7-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_3]], align 43566// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 43567// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 03568// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 13569// CHECK7-NEXT: [[SUB5:%.*]] = sub nsw i32 [[DIV]], 13570// CHECK7-NEXT: store i32 [[SUB5]], ptr [[DOTCAPTURE_EXPR_4]], align 43571// CHECK7-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 83572// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 43573// CHECK7-NEXT: [[CONV:%.*]] = sext i32 [[TMP3]] to i643574// CHECK7-NEXT: store i64 [[CONV]], ptr [[DOTOMP_UB]], align 83575// CHECK7-NEXT: store ptr [[A]], ptr [[_TMP6]], align 83576// CHECK7-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP6]], align 8, !nonnull [[META14:![0-9]+]], !align [[META15:![0-9]+]]3577// CHECK7-NEXT: store i32 0, ptr [[TMP4]], align 43578// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 43579// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]3580// CHECK7-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]3581// CHECK7: simd.if.then:3582// CHECK7-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 83583// CHECK7-NEXT: [[CONV7:%.*]] = trunc i64 [[TMP6]] to i323584// CHECK7-NEXT: store i32 [[CONV7]], ptr [[DOTOMP_IV]], align 43585// CHECK7-NEXT: store ptr [[A8]], ptr [[_TMP9]], align 83586// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]3587// CHECK7: omp.inner.for.cond:3588// CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16:![0-9]+]]3589// CHECK7-NEXT: [[CONV10:%.*]] = sext i32 [[TMP7]] to i643590// CHECK7-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP16]]3591// CHECK7-NEXT: [[CMP11:%.*]] = icmp ule i64 [[CONV10]], [[TMP8]]3592// CHECK7-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]3593// CHECK7: omp.inner.for.body:3594// CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]]3595// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 13596// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]3597// CHECK7-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP9]], align 8, !nonnull [[META14]], !align [[META15]], !llvm.access.group [[ACC_GRP16]]3598// CHECK7-NEXT: store i32 [[ADD]], ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP16]]3599// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]3600// CHECK7: omp.body.continue:3601// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]3602// CHECK7: omp.inner.for.inc:3603// CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]]3604// CHECK7-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP11]], 13605// CHECK7-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]]3606// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]3607// CHECK7: omp.inner.for.end:3608// CHECK7-NEXT: [[A13:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 03609// CHECK7-NEXT: store ptr [[A13]], ptr [[_TMP14]], align 83610// CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 43611// CHECK7-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP12]], 03612// CHECK7-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 13613// CHECK7-NEXT: [[MUL17:%.*]] = mul nsw i32 [[DIV16]], 13614// CHECK7-NEXT: [[ADD18:%.*]] = add nsw i32 0, [[MUL17]]3615// CHECK7-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP14]], align 8, !nonnull [[META14]], !align [[META15]]3616// CHECK7-NEXT: store i32 [[ADD18]], ptr [[TMP13]], align 43617// CHECK7-NEXT: br label [[SIMD_IF_END]]3618// CHECK7: simd.if.end:3619// CHECK7-NEXT: ret void3620//3621//3622// CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_parallel_master_taskloop_simd_codegen.cpp3623// CHECK7-SAME: () #[[ATTR2]] section "__TEXT,__StaticInit,regular,pure_instructions" {3624// CHECK7-NEXT: entry:3625// CHECK7-NEXT: call void @__cxx_global_var_init()3626// CHECK7-NEXT: ret void3627//3628//3629// CHECK8-LABEL: define {{[^@]+}}@main3630// CHECK8-SAME: (i32 noundef [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {3631// CHECK8-NEXT: entry:3632// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 43633// CHECK8-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 43634// CHECK8-NEXT: [[ARGV_ADDR:%.*]] = alloca ptr, align 83635// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 43636// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 43637// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 83638// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 83639// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 43640// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 43641// CHECK8-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 43642// CHECK8-NEXT: [[_TMP4:%.*]] = alloca i32, align 43643// CHECK8-NEXT: [[DOTOMP_LB5:%.*]] = alloca i64, align 83644// CHECK8-NEXT: [[DOTOMP_UB6:%.*]] = alloca i64, align 83645// CHECK8-NEXT: [[DOTOMP_IV7:%.*]] = alloca i32, align 43646// CHECK8-NEXT: [[I9:%.*]] = alloca i32, align 43647// CHECK8-NEXT: [[I20:%.*]] = alloca i32, align 43648// CHECK8-NEXT: [[DOTCAPTURE_EXPR_21:%.*]] = alloca i8, align 13649// CHECK8-NEXT: [[DOTCAPTURE_EXPR_22:%.*]] = alloca i32, align 43650// CHECK8-NEXT: [[_TMP23:%.*]] = alloca i32, align 43651// CHECK8-NEXT: [[_TMP24:%.*]] = alloca i32, align 43652// CHECK8-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 43653// CHECK8-NEXT: [[DOTCAPTURE_EXPR_26:%.*]] = alloca i32, align 43654// CHECK8-NEXT: [[DOTCAPTURE_EXPR_27:%.*]] = alloca i32, align 43655// CHECK8-NEXT: [[DOTCAPTURE_EXPR_31:%.*]] = alloca i64, align 83656// CHECK8-NEXT: [[DOTOMP_LB40:%.*]] = alloca i64, align 83657// CHECK8-NEXT: [[DOTOMP_UB41:%.*]] = alloca i64, align 83658// CHECK8-NEXT: [[I42:%.*]] = alloca i32, align 43659// CHECK8-NEXT: [[J:%.*]] = alloca i32, align 43660// CHECK8-NEXT: [[DOTOMP_IV45:%.*]] = alloca i64, align 83661// CHECK8-NEXT: [[I46:%.*]] = alloca i32, align 43662// CHECK8-NEXT: [[J47:%.*]] = alloca i32, align 43663// CHECK8-NEXT: store i32 0, ptr [[RETVAL]], align 43664// CHECK8-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 43665// CHECK8-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 83666// CHECK8-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARGC_ADDR]], align 43667// CHECK8-NEXT: store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 43668// CHECK8-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 83669// CHECK8-NEXT: store i64 9, ptr [[DOTOMP_UB]], align 83670// CHECK8-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTOMP_LB]], align 83671// CHECK8-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i323672// CHECK8-NEXT: store i32 [[CONV]], ptr [[DOTOMP_IV]], align 43673// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]3674// CHECK8: omp.inner.for.cond:3675// CHECK8-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43676// CHECK8-NEXT: [[CONV1:%.*]] = sext i32 [[TMP2]] to i643677// CHECK8-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 83678// CHECK8-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV1]], [[TMP3]]3679// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]3680// CHECK8: omp.inner.for.body:3681// CHECK8-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43682// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 13683// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]3684// CHECK8-NEXT: store i32 [[ADD]], ptr [[I]], align 43685// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]3686// CHECK8: omp.body.continue:3687// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]3688// CHECK8: omp.inner.for.inc:3689// CHECK8-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43690// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP5]], 13691// CHECK8-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 43692// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]3693// CHECK8: omp.inner.for.end:3694// CHECK8-NEXT: store i32 10, ptr [[I]], align 43695// CHECK8-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARGC_ADDR]], align 43696// CHECK8-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_3]], align 43697// CHECK8-NEXT: store i64 0, ptr [[DOTOMP_LB5]], align 83698// CHECK8-NEXT: store i64 9, ptr [[DOTOMP_UB6]], align 83699// CHECK8-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_LB5]], align 83700// CHECK8-NEXT: [[CONV8:%.*]] = trunc i64 [[TMP7]] to i323701// CHECK8-NEXT: store i32 [[CONV8]], ptr [[DOTOMP_IV7]], align 43702// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND10:%.*]]3703// CHECK8: omp.inner.for.cond10:3704// CHECK8-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]]3705// CHECK8-NEXT: [[CONV11:%.*]] = sext i32 [[TMP8]] to i643706// CHECK8-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB6]], align 8, !llvm.access.group [[ACC_GRP5]]3707// CHECK8-NEXT: [[CMP12:%.*]] = icmp ule i64 [[CONV11]], [[TMP9]]3708// CHECK8-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY13:%.*]], label [[OMP_INNER_FOR_END19:%.*]]3709// CHECK8: omp.inner.for.body13:3710// CHECK8-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 4, !llvm.access.group [[ACC_GRP5]]3711// CHECK8-NEXT: [[MUL14:%.*]] = mul nsw i32 [[TMP10]], 13712// CHECK8-NEXT: [[ADD15:%.*]] = add nsw i32 0, [[MUL14]]3713// CHECK8-NEXT: store i32 [[ADD15]], ptr [[I9]], align 4, !llvm.access.group [[ACC_GRP5]]3714// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]]3715// CHECK8: omp.body.continue16:3716// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]]3717// CHECK8: omp.inner.for.inc17:3718// CHECK8-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 4, !llvm.access.group [[ACC_GRP5]]3719// CHECK8-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP11]], 13720// CHECK8-NEXT: store i32 [[ADD18]], ptr [[DOTOMP_IV7]], align 4, !llvm.access.group [[ACC_GRP5]]3721// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP6:![0-9]+]]3722// CHECK8: omp.inner.for.end19:3723// CHECK8-NEXT: store i32 10, ptr [[I9]], align 43724// CHECK8-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARGC_ADDR]], align 43725// CHECK8-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP12]], 03726// CHECK8-NEXT: [[STOREDV:%.*]] = zext i1 [[TOBOOL]] to i83727// CHECK8-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_21]], align 13728// CHECK8-NEXT: [[TMP13:%.*]] = load i32, ptr [[ARGC_ADDR]], align 43729// CHECK8-NEXT: store i32 [[TMP13]], ptr [[DOTCAPTURE_EXPR_22]], align 43730// CHECK8-NEXT: [[TMP14:%.*]] = load i32, ptr [[ARGC_ADDR]], align 43731// CHECK8-NEXT: store i32 [[TMP14]], ptr [[DOTCAPTURE_EXPR_25]], align 43732// CHECK8-NEXT: [[TMP15:%.*]] = load i32, ptr [[ARGC_ADDR]], align 43733// CHECK8-NEXT: store i32 [[TMP15]], ptr [[DOTCAPTURE_EXPR_26]], align 43734// CHECK8-NEXT: [[TMP16:%.*]] = load ptr, ptr [[ARGV_ADDR]], align 83735// CHECK8-NEXT: [[TMP17:%.*]] = load i32, ptr [[ARGC_ADDR]], align 43736// CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i643737// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds ptr, ptr [[TMP16]], i64 [[IDXPROM]]3738// CHECK8-NEXT: [[TMP18:%.*]] = load ptr, ptr [[ARRAYIDX]], align 83739// CHECK8-NEXT: [[TMP19:%.*]] = load i32, ptr [[ARGC_ADDR]], align 43740// CHECK8-NEXT: [[IDXPROM28:%.*]] = sext i32 [[TMP19]] to i643741// CHECK8-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds i8, ptr [[TMP18]], i64 [[IDXPROM28]]3742// CHECK8-NEXT: [[TMP20:%.*]] = load i8, ptr [[ARRAYIDX29]], align 13743// CHECK8-NEXT: [[CONV30:%.*]] = sext i8 [[TMP20]] to i323744// CHECK8-NEXT: store i32 [[CONV30]], ptr [[DOTCAPTURE_EXPR_27]], align 43745// CHECK8-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_25]], align 43746// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP21]], 03747// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 13748// CHECK8-NEXT: [[CONV32:%.*]] = sext i32 [[DIV]] to i643749// CHECK8-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 43750// CHECK8-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 43751// CHECK8-NEXT: [[SUB33:%.*]] = sub i32 [[TMP22]], [[TMP23]]3752// CHECK8-NEXT: [[SUB34:%.*]] = sub i32 [[SUB33]], 13753// CHECK8-NEXT: [[ADD35:%.*]] = add i32 [[SUB34]], 13754// CHECK8-NEXT: [[DIV36:%.*]] = udiv i32 [[ADD35]], 13755// CHECK8-NEXT: [[CONV37:%.*]] = zext i32 [[DIV36]] to i643756// CHECK8-NEXT: [[MUL38:%.*]] = mul nsw i64 [[CONV32]], [[CONV37]]3757// CHECK8-NEXT: [[SUB39:%.*]] = sub nsw i64 [[MUL38]], 13758// CHECK8-NEXT: store i64 [[SUB39]], ptr [[DOTCAPTURE_EXPR_31]], align 83759// CHECK8-NEXT: store i64 0, ptr [[DOTOMP_LB40]], align 83760// CHECK8-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_31]], align 83761// CHECK8-NEXT: store i64 [[TMP24]], ptr [[DOTOMP_UB41]], align 83762// CHECK8-NEXT: store i32 0, ptr [[I42]], align 43763// CHECK8-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 43764// CHECK8-NEXT: store i32 [[TMP25]], ptr [[J]], align 43765// CHECK8-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_25]], align 43766// CHECK8-NEXT: [[CMP43:%.*]] = icmp slt i32 0, [[TMP26]]3767// CHECK8-NEXT: br i1 [[CMP43]], label [[LAND_LHS_TRUE:%.*]], label [[SIMD_IF_END:%.*]]3768// CHECK8: land.lhs.true:3769// CHECK8-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 43770// CHECK8-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 43771// CHECK8-NEXT: [[CMP44:%.*]] = icmp slt i32 [[TMP27]], [[TMP28]]3772// CHECK8-NEXT: br i1 [[CMP44]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END]]3773// CHECK8: simd.if.then:3774// CHECK8-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTOMP_LB40]], align 83775// CHECK8-NEXT: store i64 [[TMP29]], ptr [[DOTOMP_IV45]], align 83776// CHECK8-NEXT: [[TMP30:%.*]] = load ptr, ptr [[ARGV_ADDR]], align 83777// CHECK8-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[TMP30]], i64 8) ]3778// CHECK8-NEXT: [[TMP31:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_21]], align 13779// CHECK8-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP31]] to i13780// CHECK8-NEXT: br i1 [[LOADEDV]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]3781// CHECK8: omp_if.then:3782// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND48:%.*]]3783// CHECK8: omp.inner.for.cond48:3784// CHECK8-NEXT: [[TMP32:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9:![0-9]+]]3785// CHECK8-NEXT: [[TMP33:%.*]] = load i64, ptr [[DOTOMP_UB41]], align 8, !llvm.access.group [[ACC_GRP9]]3786// CHECK8-NEXT: [[CMP49:%.*]] = icmp ule i64 [[TMP32]], [[TMP33]]3787// CHECK8-NEXT: br i1 [[CMP49]], label [[OMP_INNER_FOR_BODY50:%.*]], label [[OMP_INNER_FOR_END83:%.*]]3788// CHECK8: omp.inner.for.body50:3789// CHECK8-NEXT: [[TMP34:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9]]3790// CHECK8-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 4, !llvm.access.group [[ACC_GRP9]]3791// CHECK8-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4, !llvm.access.group [[ACC_GRP9]]3792// CHECK8-NEXT: [[SUB51:%.*]] = sub i32 [[TMP35]], [[TMP36]]3793// CHECK8-NEXT: [[SUB52:%.*]] = sub i32 [[SUB51]], 13794// CHECK8-NEXT: [[ADD53:%.*]] = add i32 [[SUB52]], 13795// CHECK8-NEXT: [[DIV54:%.*]] = udiv i32 [[ADD53]], 13796// CHECK8-NEXT: [[MUL55:%.*]] = mul i32 1, [[DIV54]]3797// CHECK8-NEXT: [[CONV56:%.*]] = zext i32 [[MUL55]] to i643798// CHECK8-NEXT: [[DIV57:%.*]] = sdiv i64 [[TMP34]], [[CONV56]]3799// CHECK8-NEXT: [[MUL58:%.*]] = mul nsw i64 [[DIV57]], 13800// CHECK8-NEXT: [[ADD59:%.*]] = add nsw i64 0, [[MUL58]]3801// CHECK8-NEXT: [[CONV60:%.*]] = trunc i64 [[ADD59]] to i323802// CHECK8-NEXT: store i32 [[CONV60]], ptr [[I46]], align 4, !llvm.access.group [[ACC_GRP9]]3803// CHECK8-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4, !llvm.access.group [[ACC_GRP9]]3804// CHECK8-NEXT: [[CONV61:%.*]] = sext i32 [[TMP37]] to i643805// CHECK8-NEXT: [[TMP38:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9]]3806// CHECK8-NEXT: [[TMP39:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9]]3807// CHECK8-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 4, !llvm.access.group [[ACC_GRP9]]3808// CHECK8-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4, !llvm.access.group [[ACC_GRP9]]3809// CHECK8-NEXT: [[SUB62:%.*]] = sub i32 [[TMP40]], [[TMP41]]3810// CHECK8-NEXT: [[SUB63:%.*]] = sub i32 [[SUB62]], 13811// CHECK8-NEXT: [[ADD64:%.*]] = add i32 [[SUB63]], 13812// CHECK8-NEXT: [[DIV65:%.*]] = udiv i32 [[ADD64]], 13813// CHECK8-NEXT: [[MUL66:%.*]] = mul i32 1, [[DIV65]]3814// CHECK8-NEXT: [[CONV67:%.*]] = zext i32 [[MUL66]] to i643815// CHECK8-NEXT: [[DIV68:%.*]] = sdiv i64 [[TMP39]], [[CONV67]]3816// CHECK8-NEXT: [[TMP42:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 4, !llvm.access.group [[ACC_GRP9]]3817// CHECK8-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4, !llvm.access.group [[ACC_GRP9]]3818// CHECK8-NEXT: [[SUB69:%.*]] = sub i32 [[TMP42]], [[TMP43]]3819// CHECK8-NEXT: [[SUB70:%.*]] = sub i32 [[SUB69]], 13820// CHECK8-NEXT: [[ADD71:%.*]] = add i32 [[SUB70]], 13821// CHECK8-NEXT: [[DIV72:%.*]] = udiv i32 [[ADD71]], 13822// CHECK8-NEXT: [[MUL73:%.*]] = mul i32 1, [[DIV72]]3823// CHECK8-NEXT: [[CONV74:%.*]] = zext i32 [[MUL73]] to i643824// CHECK8-NEXT: [[MUL75:%.*]] = mul nsw i64 [[DIV68]], [[CONV74]]3825// CHECK8-NEXT: [[SUB76:%.*]] = sub nsw i64 [[TMP38]], [[MUL75]]3826// CHECK8-NEXT: [[MUL77:%.*]] = mul nsw i64 [[SUB76]], 13827// CHECK8-NEXT: [[ADD78:%.*]] = add nsw i64 [[CONV61]], [[MUL77]]3828// CHECK8-NEXT: [[CONV79:%.*]] = trunc i64 [[ADD78]] to i323829// CHECK8-NEXT: store i32 [[CONV79]], ptr [[J47]], align 4, !llvm.access.group [[ACC_GRP9]]3830// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE80:%.*]]3831// CHECK8: omp.body.continue80:3832// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC81:%.*]]3833// CHECK8: omp.inner.for.inc81:3834// CHECK8-NEXT: [[TMP44:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9]]3835// CHECK8-NEXT: [[ADD82:%.*]] = add nsw i64 [[TMP44]], 13836// CHECK8-NEXT: store i64 [[ADD82]], ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9]]3837// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND48]], !llvm.loop [[LOOP10:![0-9]+]]3838// CHECK8: omp.inner.for.end83:3839// CHECK8-NEXT: br label [[OMP_IF_END:%.*]]3840// CHECK8: omp_if.else:3841// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND84:%.*]]3842// CHECK8: omp.inner.for.cond84:3843// CHECK8-NEXT: [[TMP45:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 83844// CHECK8-NEXT: [[TMP46:%.*]] = load i64, ptr [[DOTOMP_UB41]], align 83845// CHECK8-NEXT: [[CMP85:%.*]] = icmp ule i64 [[TMP45]], [[TMP46]]3846// CHECK8-NEXT: br i1 [[CMP85]], label [[OMP_INNER_FOR_BODY86:%.*]], label [[OMP_INNER_FOR_END119:%.*]]3847// CHECK8: omp.inner.for.body86:3848// CHECK8-NEXT: [[TMP47:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 83849// CHECK8-NEXT: [[TMP48:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 43850// CHECK8-NEXT: [[TMP49:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 43851// CHECK8-NEXT: [[SUB87:%.*]] = sub i32 [[TMP48]], [[TMP49]]3852// CHECK8-NEXT: [[SUB88:%.*]] = sub i32 [[SUB87]], 13853// CHECK8-NEXT: [[ADD89:%.*]] = add i32 [[SUB88]], 13854// CHECK8-NEXT: [[DIV90:%.*]] = udiv i32 [[ADD89]], 13855// CHECK8-NEXT: [[MUL91:%.*]] = mul i32 1, [[DIV90]]3856// CHECK8-NEXT: [[CONV92:%.*]] = zext i32 [[MUL91]] to i643857// CHECK8-NEXT: [[DIV93:%.*]] = sdiv i64 [[TMP47]], [[CONV92]]3858// CHECK8-NEXT: [[MUL94:%.*]] = mul nsw i64 [[DIV93]], 13859// CHECK8-NEXT: [[ADD95:%.*]] = add nsw i64 0, [[MUL94]]3860// CHECK8-NEXT: [[CONV96:%.*]] = trunc i64 [[ADD95]] to i323861// CHECK8-NEXT: store i32 [[CONV96]], ptr [[I46]], align 43862// CHECK8-NEXT: [[TMP50:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 43863// CHECK8-NEXT: [[CONV97:%.*]] = sext i32 [[TMP50]] to i643864// CHECK8-NEXT: [[TMP51:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 83865// CHECK8-NEXT: [[TMP52:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 83866// CHECK8-NEXT: [[TMP53:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 43867// CHECK8-NEXT: [[TMP54:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 43868// CHECK8-NEXT: [[SUB98:%.*]] = sub i32 [[TMP53]], [[TMP54]]3869// CHECK8-NEXT: [[SUB99:%.*]] = sub i32 [[SUB98]], 13870// CHECK8-NEXT: [[ADD100:%.*]] = add i32 [[SUB99]], 13871// CHECK8-NEXT: [[DIV101:%.*]] = udiv i32 [[ADD100]], 13872// CHECK8-NEXT: [[MUL102:%.*]] = mul i32 1, [[DIV101]]3873// CHECK8-NEXT: [[CONV103:%.*]] = zext i32 [[MUL102]] to i643874// CHECK8-NEXT: [[DIV104:%.*]] = sdiv i64 [[TMP52]], [[CONV103]]3875// CHECK8-NEXT: [[TMP55:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 43876// CHECK8-NEXT: [[TMP56:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 43877// CHECK8-NEXT: [[SUB105:%.*]] = sub i32 [[TMP55]], [[TMP56]]3878// CHECK8-NEXT: [[SUB106:%.*]] = sub i32 [[SUB105]], 13879// CHECK8-NEXT: [[ADD107:%.*]] = add i32 [[SUB106]], 13880// CHECK8-NEXT: [[DIV108:%.*]] = udiv i32 [[ADD107]], 13881// CHECK8-NEXT: [[MUL109:%.*]] = mul i32 1, [[DIV108]]3882// CHECK8-NEXT: [[CONV110:%.*]] = zext i32 [[MUL109]] to i643883// CHECK8-NEXT: [[MUL111:%.*]] = mul nsw i64 [[DIV104]], [[CONV110]]3884// CHECK8-NEXT: [[SUB112:%.*]] = sub nsw i64 [[TMP51]], [[MUL111]]3885// CHECK8-NEXT: [[MUL113:%.*]] = mul nsw i64 [[SUB112]], 13886// CHECK8-NEXT: [[ADD114:%.*]] = add nsw i64 [[CONV97]], [[MUL113]]3887// CHECK8-NEXT: [[CONV115:%.*]] = trunc i64 [[ADD114]] to i323888// CHECK8-NEXT: store i32 [[CONV115]], ptr [[J47]], align 43889// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE116:%.*]]3890// CHECK8: omp.body.continue116:3891// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC117:%.*]]3892// CHECK8: omp.inner.for.inc117:3893// CHECK8-NEXT: [[TMP57:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 83894// CHECK8-NEXT: [[ADD118:%.*]] = add nsw i64 [[TMP57]], 13895// CHECK8-NEXT: store i64 [[ADD118]], ptr [[DOTOMP_IV45]], align 83896// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND84]], !llvm.loop [[LOOP12:![0-9]+]]3897// CHECK8: omp.inner.for.end119:3898// CHECK8-NEXT: br label [[OMP_IF_END]]3899// CHECK8: omp_if.end:3900// CHECK8-NEXT: [[TMP58:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_25]], align 43901// CHECK8-NEXT: [[SUB120:%.*]] = sub nsw i32 [[TMP58]], 03902// CHECK8-NEXT: [[DIV121:%.*]] = sdiv i32 [[SUB120]], 13903// CHECK8-NEXT: [[MUL122:%.*]] = mul nsw i32 [[DIV121]], 13904// CHECK8-NEXT: [[ADD123:%.*]] = add nsw i32 0, [[MUL122]]3905// CHECK8-NEXT: store i32 [[ADD123]], ptr [[I20]], align 43906// CHECK8-NEXT: [[TMP59:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 43907// CHECK8-NEXT: [[TMP60:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 43908// CHECK8-NEXT: [[TMP61:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 43909// CHECK8-NEXT: [[SUB124:%.*]] = sub i32 [[TMP60]], [[TMP61]]3910// CHECK8-NEXT: [[SUB125:%.*]] = sub i32 [[SUB124]], 13911// CHECK8-NEXT: [[ADD126:%.*]] = add i32 [[SUB125]], 13912// CHECK8-NEXT: [[DIV127:%.*]] = udiv i32 [[ADD126]], 13913// CHECK8-NEXT: [[MUL128:%.*]] = mul i32 [[DIV127]], 13914// CHECK8-NEXT: [[ADD129:%.*]] = add i32 [[TMP59]], [[MUL128]]3915// CHECK8-NEXT: store i32 [[ADD129]], ptr [[J47]], align 43916// CHECK8-NEXT: br label [[SIMD_IF_END]]3917// CHECK8: simd.if.end:3918// CHECK8-NEXT: [[TMP62:%.*]] = load i32, ptr [[RETVAL]], align 43919// CHECK8-NEXT: ret i32 [[TMP62]]3920//3921//3922// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init3923// CHECK8-SAME: () #[[ATTR2:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" {3924// CHECK8-NEXT: entry:3925// CHECK8-NEXT: call void @_ZN1SC1Ei(ptr noundef nonnull align 4 dereferenceable(4) @s, i32 noundef 1)3926// CHECK8-NEXT: ret void3927//3928//3929// CHECK8-LABEL: define {{[^@]+}}@_ZN1SC1Ei3930// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR3:[0-9]+]] align 2 {3931// CHECK8-NEXT: entry:3932// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 83933// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca i32, align 43934// CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 83935// CHECK8-NEXT: store i32 [[C]], ptr [[C_ADDR]], align 43936// CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 83937// CHECK8-NEXT: [[TMP0:%.*]] = load i32, ptr [[C_ADDR]], align 43938// CHECK8-NEXT: call void @_ZN1SC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])3939// CHECK8-NEXT: ret void3940//3941//3942// CHECK8-LABEL: define {{[^@]+}}@_ZN1SC2Ei3943// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR3]] align 2 {3944// CHECK8-NEXT: entry:3945// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 83946// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca i32, align 43947// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 13948// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 43949// CHECK8-NEXT: [[_TMP2:%.*]] = alloca ptr, align 83950// CHECK8-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 43951// CHECK8-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 43952// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 83953// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 83954// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 43955// CHECK8-NEXT: [[_TMP6:%.*]] = alloca ptr, align 83956// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 43957// CHECK8-NEXT: [[A8:%.*]] = alloca i32, align 43958// CHECK8-NEXT: [[_TMP9:%.*]] = alloca ptr, align 83959// CHECK8-NEXT: [[_TMP14:%.*]] = alloca ptr, align 83960// CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 83961// CHECK8-NEXT: store i32 [[C]], ptr [[C_ADDR]], align 43962// CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 83963// CHECK8-NEXT: [[TMP0:%.*]] = load i32, ptr [[C_ADDR]], align 43964// CHECK8-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 03965// CHECK8-NEXT: [[STOREDV:%.*]] = zext i1 [[TOBOOL]] to i83966// CHECK8-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_]], align 13967// CHECK8-NEXT: store ptr [[TMP]], ptr [[_TMP2]], align 83968// CHECK8-NEXT: [[TMP1:%.*]] = load i32, ptr [[C_ADDR]], align 43969// CHECK8-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_3]], align 43970// CHECK8-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 43971// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 03972// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 13973// CHECK8-NEXT: [[SUB5:%.*]] = sub nsw i32 [[DIV]], 13974// CHECK8-NEXT: store i32 [[SUB5]], ptr [[DOTCAPTURE_EXPR_4]], align 43975// CHECK8-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 83976// CHECK8-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 43977// CHECK8-NEXT: [[CONV:%.*]] = sext i32 [[TMP3]] to i643978// CHECK8-NEXT: store i64 [[CONV]], ptr [[DOTOMP_UB]], align 83979// CHECK8-NEXT: store ptr [[A]], ptr [[_TMP6]], align 83980// CHECK8-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP6]], align 8, !nonnull [[META14:![0-9]+]], !align [[META15:![0-9]+]]3981// CHECK8-NEXT: store i32 0, ptr [[TMP4]], align 43982// CHECK8-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 43983// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]3984// CHECK8-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]3985// CHECK8: simd.if.then:3986// CHECK8-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 83987// CHECK8-NEXT: [[CONV7:%.*]] = trunc i64 [[TMP6]] to i323988// CHECK8-NEXT: store i32 [[CONV7]], ptr [[DOTOMP_IV]], align 43989// CHECK8-NEXT: store ptr [[A8]], ptr [[_TMP9]], align 83990// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]3991// CHECK8: omp.inner.for.cond:3992// CHECK8-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16:![0-9]+]]3993// CHECK8-NEXT: [[CONV10:%.*]] = sext i32 [[TMP7]] to i643994// CHECK8-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP16]]3995// CHECK8-NEXT: [[CMP11:%.*]] = icmp ule i64 [[CONV10]], [[TMP8]]3996// CHECK8-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]3997// CHECK8: omp.inner.for.body:3998// CHECK8-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]]3999// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 14000// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]4001// CHECK8-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP9]], align 8, !nonnull [[META14]], !align [[META15]], !llvm.access.group [[ACC_GRP16]]4002// CHECK8-NEXT: store i32 [[ADD]], ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP16]]4003// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]4004// CHECK8: omp.body.continue:4005// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]4006// CHECK8: omp.inner.for.inc:4007// CHECK8-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]]4008// CHECK8-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP11]], 14009// CHECK8-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]]4010// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]4011// CHECK8: omp.inner.for.end:4012// CHECK8-NEXT: [[A13:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 04013// CHECK8-NEXT: store ptr [[A13]], ptr [[_TMP14]], align 84014// CHECK8-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 44015// CHECK8-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP12]], 04016// CHECK8-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 14017// CHECK8-NEXT: [[MUL17:%.*]] = mul nsw i32 [[DIV16]], 14018// CHECK8-NEXT: [[ADD18:%.*]] = add nsw i32 0, [[MUL17]]4019// CHECK8-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP14]], align 8, !nonnull [[META14]], !align [[META15]]4020// CHECK8-NEXT: store i32 [[ADD18]], ptr [[TMP13]], align 44021// CHECK8-NEXT: br label [[SIMD_IF_END]]4022// CHECK8: simd.if.end:4023// CHECK8-NEXT: ret void4024//4025//4026// CHECK8-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_parallel_master_taskloop_simd_codegen.cpp4027// CHECK8-SAME: () #[[ATTR2]] section "__TEXT,__StaticInit,regular,pure_instructions" {4028// CHECK8-NEXT: entry:4029// CHECK8-NEXT: call void @__cxx_global_var_init()4030// CHECK8-NEXT: ret void4031//4032