918 lines · cpp
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _2// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s4// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK36// RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK47 8// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"9// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s10// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"11// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"12// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"13// expected-no-diagnostics14#ifndef HEADER15#define HEADER16 17enum omp_allocator_handle_t {18 omp_null_allocator = 0,19 omp_default_mem_alloc = 1,20 omp_large_cap_mem_alloc = 2,21 omp_const_mem_alloc = 3,22 omp_high_bw_mem_alloc = 4,23 omp_low_lat_mem_alloc = 5,24 omp_cgroup_mem_alloc = 6,25 omp_pteam_mem_alloc = 7,26 omp_thread_mem_alloc = 8,27 KMP_ALLOCATOR_MAX_HANDLE = __UINTPTR_MAX__28};29 30template <class T>31struct S {32 T f;33 S(T a) : f(a) {}34 S() : f() {}35 operator T() { return T(); }36 ~S() {}37};38 39volatile int g __attribute__((aligned(128))) = 1212;40 41struct SS {42 int a;43 int b : 4;44 int &c;45 SS(int &d) : a(0), b(0), c(d) {46#pragma omp parallel private(a, b, c)47#ifdef LAMBDA48 [&]() {49 ++this->a, --b, (this)->c /= 1;50#pragma omp parallel private(a, b, c)51 ++(this)->a, --b, this->c /= 1;52 }();53#elif defined(BLOCKS)54 ^{55 ++a;56 --this->b;57 (this)->c /= 1;58#pragma omp parallel private(a, b, c)59 ++(this)->a, --b, this->c /= 1;60 }();61#else62 ++this->a, --b, c /= 1;63#endif64 }65};66 67template<typename T>68struct SST {69 T a;70 SST() : a(T()) {71#pragma omp parallel private(a) allocate(omp_large_cap_mem_alloc:a)72#ifdef LAMBDA73 [&]() {74 [&]() {75 ++this->a;76#pragma omp parallel private(a)77 ++(this)->a;78 }();79 }();80#elif defined(BLOCKS)81 ^{82 ^{83 ++a;84#pragma omp parallel private(a)85 ++(this)->a;86 }();87 }();88#else89 ++(this)->a;90#endif91 }92};93 94template <typename T>95T tmain() {96 S<T> test;97 SST<T> sst;98 T t_var __attribute__((aligned(128))) = T();99 T vec[] __attribute__((aligned(128))) = {1, 2};100 S<T> s_arr[] __attribute__((aligned(128))) = {1, 2};101 S<T> var __attribute__((aligned(128))) (3);102#pragma omp parallel private(t_var, vec, s_arr, var)103 {104 vec[0] = t_var;105 s_arr[0] = var;106 }107 return T();108}109 110int main() {111 static int sivar;112 SS ss(sivar);113#ifdef LAMBDA114 [&]() {115#pragma omp parallel private(g, sivar)116 {117 118 119 120 g = 1;121 sivar = 2;122 123 124 [&]() {125 g = 2;126 sivar = 4;127 }();128 }129 }();130 return 0;131#elif defined(BLOCKS)132 ^{133#pragma omp parallel private(g, sivar)134 {135 g = 1;136 sivar = 20;137 ^{138 g = 2;139 sivar = 40;140 }();141 }142 }();143 return 0;144 145 146#else147 S<float> test;148 int t_var = 0;149 int vec[] = {1, 2};150 S<float> s_arr[] = {1, 2};151 S<float> var(3);152#pragma omp parallel private(t_var, vec, s_arr, var, sivar)153 {154 vec[0] = t_var;155 s_arr[0] = var;156 sivar = 3;157 }158 return tmain<int>();159#endif160}161 162 163 164 165 166 167 168#endif169 170// CHECK1-LABEL: define {{[^@]+}}@main171// CHECK1-SAME: () #[[ATTR0:[0-9]+]] {172// CHECK1-NEXT: entry:173// CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4174// CHECK1-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8175// CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4176// CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4177// CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4178// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4179// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4180// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4181// CHECK1-NEXT: call void @_ZN2SSC1ERi(ptr noundef nonnull align 8 dereferenceable(16) [[SS]], ptr noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar)182// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])183// CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4184// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i64 8, i1 false)185// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], float noundef 1.000000e+00)186// CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i64 1187// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00)188// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]], float noundef 3.000000e+00)189// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 0, ptr @main.omp_outlined)190// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()191// CHECK1-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4192// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]]193// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0194// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2195// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]196// CHECK1: arraydestroy.body:197// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP0]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]198// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1199// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]200// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]201// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]202// CHECK1: arraydestroy.done1:203// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]204// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4205// CHECK1-NEXT: ret i32 [[TMP1]]206//207//208// CHECK1-LABEL: define {{[^@]+}}@_ZN2SSC1ERi209// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {210// CHECK1-NEXT: entry:211// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8212// CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8213// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8214// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8215// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8216// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8217// CHECK1-NEXT: call void @_ZN2SSC2ERi(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]])218// CHECK1-NEXT: ret void219//220//221// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev222// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {223// CHECK1-NEXT: entry:224// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8225// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8226// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8227// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])228// CHECK1-NEXT: ret void229//230//231// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef232// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {233// CHECK1-NEXT: entry:234// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8235// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4236// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8237// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4238// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8239// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4240// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])241// CHECK1-NEXT: ret void242//243//244// CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined245// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {246// CHECK1-NEXT: entry:247// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8248// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8249// CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4250// CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4251// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4252// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4253// CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4254// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8255// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8256// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0257// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2258// CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]259// CHECK1: arrayctor.loop:260// CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]261// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])262// CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1263// CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]264// CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]265// CHECK1: arrayctor.cont:266// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])267// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 4268// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0269// CHECK1-NEXT: store i32 [[TMP0]], ptr [[ARRAYIDX]], align 4270// CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0271// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX1]], ptr align 4 [[VAR]], i64 4, i1 false)272// CHECK1-NEXT: store i32 3, ptr [[SIVAR]], align 4273// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]]274// CHECK1-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0275// CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN2]], i64 2276// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]277// CHECK1: arraydestroy.body:278// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]279// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1280// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]281// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]]282// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]]283// CHECK1: arraydestroy.done3:284// CHECK1-NEXT: ret void285//286//287// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev288// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {289// CHECK1-NEXT: entry:290// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8291// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8292// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8293// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]294// CHECK1-NEXT: ret void295//296//297// CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v298// CHECK1-SAME: () #[[ATTR1]] comdat {299// CHECK1-NEXT: entry:300// CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4301// CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4302// CHECK1-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4303// CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 128304// CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128305// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128306// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128307// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])308// CHECK1-NEXT: call void @_ZN3SSTIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[SST]])309// CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 128310// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[VEC]], ptr align 128 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)311// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1)312// CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1313// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)314// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]], i32 noundef 3)315// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @_Z5tmainIiET_v.omp_outlined)316// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4317// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]]318// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0319// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2320// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]321// CHECK1: arraydestroy.body:322// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP0]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]323// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1324// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]325// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]326// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]327// CHECK1: arraydestroy.done1:328// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]329// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4330// CHECK1-NEXT: ret i32 [[TMP1]]331//332//333// CHECK1-LABEL: define {{[^@]+}}@_ZN2SSC2ERi334// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {335// CHECK1-NEXT: entry:336// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8337// CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8338// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8339// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8340// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8341// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0342// CHECK1-NEXT: store i32 0, ptr [[A]], align 8343// CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1344// CHECK1-NEXT: [[BF_LOAD:%.*]] = load i8, ptr [[B]], align 4345// CHECK1-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16346// CHECK1-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0347// CHECK1-NEXT: store i8 [[BF_SET]], ptr [[B]], align 4348// CHECK1-NEXT: [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2349// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8350// CHECK1-NEXT: store ptr [[TMP0]], ptr [[C]], align 8351// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @_ZN2SSC2ERi.omp_outlined, ptr [[THIS1]])352// CHECK1-NEXT: ret void353//354//355// CHECK1-LABEL: define {{[^@]+}}@_ZN2SSC2ERi.omp_outlined356// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]]) #[[ATTR3]] {357// CHECK1-NEXT: entry:358// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8359// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8360// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8361// CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4362// CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8363// CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4364// CHECK1-NEXT: [[C:%.*]] = alloca i32, align 4365// CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8366// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8367// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8368// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8369// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8370// CHECK1-NEXT: store ptr [[A]], ptr [[TMP]], align 8371// CHECK1-NEXT: store ptr [[C]], ptr [[_TMP1]], align 8372// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8373// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4374// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1375// CHECK1-NEXT: store i32 [[INC]], ptr [[TMP1]], align 4376// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[B]], align 4377// CHECK1-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1378// CHECK1-NEXT: store i32 [[DEC]], ptr [[B]], align 4379// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP1]], align 8380// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4381// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1382// CHECK1-NEXT: store i32 [[DIV]], ptr [[TMP4]], align 4383// CHECK1-NEXT: ret void384//385//386// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev387// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {388// CHECK1-NEXT: entry:389// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8390// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8391// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8392// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0393// CHECK1-NEXT: store float 0.000000e+00, ptr [[F]], align 4394// CHECK1-NEXT: ret void395//396//397// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef398// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {399// CHECK1-NEXT: entry:400// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8401// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4402// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8403// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4404// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8405// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0406// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4407// CHECK1-NEXT: store float [[TMP0]], ptr [[F]], align 4408// CHECK1-NEXT: ret void409//410//411// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev412// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {413// CHECK1-NEXT: entry:414// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8415// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8416// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8417// CHECK1-NEXT: ret void418//419//420// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev421// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {422// CHECK1-NEXT: entry:423// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8424// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8425// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8426// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])427// CHECK1-NEXT: ret void428//429//430// CHECK1-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev431// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {432// CHECK1-NEXT: entry:433// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8434// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8435// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8436// CHECK1-NEXT: call void @_ZN3SSTIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])437// CHECK1-NEXT: ret void438//439//440// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei441// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {442// CHECK1-NEXT: entry:443// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8444// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4445// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8446// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4447// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8448// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4449// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])450// CHECK1-NEXT: ret void451//452//453// CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v.omp_outlined454// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {455// CHECK1-NEXT: entry:456// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8457// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8458// CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 128459// CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128460// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128461// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128462// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8463// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8464// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0465// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2466// CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]467// CHECK1: arrayctor.loop:468// CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]469// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])470// CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1471// CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]472// CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]473// CHECK1: arrayctor.cont:474// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])475// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 128476// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0477// CHECK1-NEXT: store i32 [[TMP0]], ptr [[ARRAYIDX]], align 128478// CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0479// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[ARRAYIDX1]], ptr align 128 [[VAR]], i64 4, i1 false)480// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]]481// CHECK1-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0482// CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN2]], i64 2483// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]484// CHECK1: arraydestroy.body:485// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]486// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1487// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]488// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]]489// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]]490// CHECK1: arraydestroy.done3:491// CHECK1-NEXT: ret void492//493//494// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev495// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {496// CHECK1-NEXT: entry:497// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8498// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8499// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8500// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]501// CHECK1-NEXT: ret void502//503//504// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev505// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {506// CHECK1-NEXT: entry:507// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8508// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8509// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8510// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0511// CHECK1-NEXT: store i32 0, ptr [[F]], align 4512// CHECK1-NEXT: ret void513//514//515// CHECK1-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev516// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {517// CHECK1-NEXT: entry:518// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8519// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8520// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8521// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SST:%.*]], ptr [[THIS1]], i32 0, i32 0522// CHECK1-NEXT: store i32 0, ptr [[A]], align 4523// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @_ZN3SSTIiEC2Ev.omp_outlined, ptr [[THIS1]])524// CHECK1-NEXT: ret void525//526//527// CHECK1-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev.omp_outlined528// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]]) #[[ATTR3]] {529// CHECK1-NEXT: entry:530// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8531// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8532// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8533// CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8534// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8535// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8536// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8537// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8538// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8539// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4540// CHECK1-NEXT: [[DOTA__VOID_ADDR:%.*]] = call ptr @__kmpc_alloc(i32 [[TMP2]], i64 4, ptr inttoptr (i64 2 to ptr))541// CHECK1-NEXT: store ptr [[DOTA__VOID_ADDR]], ptr [[TMP]], align 8542// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8543// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4544// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1545// CHECK1-NEXT: store i32 [[INC]], ptr [[TMP3]], align 4546// CHECK1-NEXT: call void @__kmpc_free(i32 [[TMP2]], ptr [[DOTA__VOID_ADDR]], ptr inttoptr (i64 2 to ptr))547// CHECK1-NEXT: ret void548//549//550// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei551// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {552// CHECK1-NEXT: entry:553// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8554// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4555// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8556// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4557// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8558// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0559// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4560// CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4561// CHECK1-NEXT: ret void562//563//564// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev565// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {566// CHECK1-NEXT: entry:567// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8568// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8569// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8570// CHECK1-NEXT: ret void571//572//573// CHECK3-LABEL: define {{[^@]+}}@main574// CHECK3-SAME: () #[[ATTR0:[0-9]+]] {575// CHECK3-NEXT: entry:576// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4577// CHECK3-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8578// CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1579// CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4580// CHECK3-NEXT: call void @_ZN2SSC1ERi(ptr noundef nonnull align 8 dereferenceable(16) [[SS]], ptr noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar)581// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])582// CHECK3-NEXT: ret i32 0583//584//585// CHECK3-LABEL: define {{[^@]+}}@_ZN2SSC1ERi586// CHECK3-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {587// CHECK3-NEXT: entry:588// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8589// CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8590// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8591// CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8592// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8593// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8594// CHECK3-NEXT: call void @_ZN2SSC2ERi(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]])595// CHECK3-NEXT: ret void596//597//598// CHECK3-LABEL: define {{[^@]+}}@_ZN2SSC2ERi599// CHECK3-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {600// CHECK3-NEXT: entry:601// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8602// CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8603// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8604// CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8605// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8606// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0607// CHECK3-NEXT: store i32 0, ptr [[A]], align 8608// CHECK3-NEXT: [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1609// CHECK3-NEXT: [[BF_LOAD:%.*]] = load i8, ptr [[B]], align 4610// CHECK3-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16611// CHECK3-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0612// CHECK3-NEXT: store i8 [[BF_SET]], ptr [[B]], align 4613// CHECK3-NEXT: [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2614// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8615// CHECK3-NEXT: store ptr [[TMP0]], ptr [[C]], align 8616// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 1, ptr @_ZN2SSC2ERi.omp_outlined, ptr [[THIS1]])617// CHECK3-NEXT: ret void618//619//620// CHECK3-LABEL: define {{[^@]+}}@_ZN2SSC2ERi.omp_outlined621// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] {622// CHECK3-NEXT: entry:623// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8624// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8625// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8626// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4627// CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 8628// CHECK3-NEXT: [[B:%.*]] = alloca i32, align 4629// CHECK3-NEXT: [[C:%.*]] = alloca i32, align 4630// CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8631// CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8632// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8633// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8634// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8635// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8636// CHECK3-NEXT: store ptr [[A]], ptr [[TMP]], align 8637// CHECK3-NEXT: store ptr [[C]], ptr [[_TMP1]], align 8638// CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0639// CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP1]], align 8640// CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1641// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8642// CHECK3-NEXT: store ptr [[TMP3]], ptr [[TMP2]], align 8643// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2644// CHECK3-NEXT: store ptr [[B]], ptr [[TMP4]], align 8645// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 3646// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8647// CHECK3-NEXT: store ptr [[TMP6]], ptr [[TMP5]], align 8648// CHECK3-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(32) [[REF_TMP]])649// CHECK3-NEXT: ret void650//651//652// CHECK3-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv653// CHECK3-SAME: (ptr noundef nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR1]] align 2 {654// CHECK3-NEXT: entry:655// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8656// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8657// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8658// CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0:%.*]], ptr [[THIS1]], i32 0, i32 0659// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8660// CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1661// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8662// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4663// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1664// CHECK3-NEXT: store i32 [[INC]], ptr [[TMP3]], align 4665// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 2666// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8667// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4668// CHECK3-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1669// CHECK3-NEXT: store i32 [[DEC]], ptr [[TMP6]], align 4670// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 3671// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8672// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4673// CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1674// CHECK3-NEXT: store i32 [[DIV]], ptr [[TMP9]], align 4675// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined, ptr [[TMP1]])676// CHECK3-NEXT: ret void677//678//679// CHECK3-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined680// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]]) #[[ATTR2]] {681// CHECK3-NEXT: entry:682// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8683// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8684// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8685// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4686// CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 8687// CHECK3-NEXT: [[B:%.*]] = alloca i32, align 4688// CHECK3-NEXT: [[C:%.*]] = alloca i32, align 4689// CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8690// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8691// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8692// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8693// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8694// CHECK3-NEXT: store ptr [[A]], ptr [[TMP]], align 8695// CHECK3-NEXT: store ptr [[C]], ptr [[_TMP1]], align 8696// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8697// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4698// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1699// CHECK3-NEXT: store i32 [[INC]], ptr [[TMP1]], align 4700// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[B]], align 4701// CHECK3-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1702// CHECK3-NEXT: store i32 [[DEC]], ptr [[B]], align 4703// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP1]], align 8704// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4705// CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1706// CHECK3-NEXT: store i32 [[DIV]], ptr [[TMP4]], align 4707// CHECK3-NEXT: ret void708//709//710// CHECK4-LABEL: define {{[^@]+}}@main711// CHECK4-SAME: () #[[ATTR1:[0-9]+]] {712// CHECK4-NEXT: entry:713// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4714// CHECK4-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8715// CHECK4-NEXT: store i32 0, ptr [[RETVAL]], align 4716// CHECK4-NEXT: call void @_ZN2SSC1ERi(ptr noundef nonnull align 8 dereferenceable(16) [[SS]], ptr noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar)717// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr getelementptr inbounds nuw ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr @__block_literal_global, i32 0, i32 3), align 8718// CHECK4-NEXT: call void [[TMP0]](ptr noundef @__block_literal_global)719// CHECK4-NEXT: ret i32 0720//721//722// CHECK4-LABEL: define {{[^@]+}}@_ZN2SSC1ERi723// CHECK4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 {724// CHECK4-NEXT: entry:725// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8726// CHECK4-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8727// CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8728// CHECK4-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8729// CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8730// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8731// CHECK4-NEXT: call void @_ZN2SSC2ERi(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]])732// CHECK4-NEXT: ret void733//734//735// CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke736// CHECK4-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR3:[0-9]+]] {737// CHECK4-NEXT: entry:738// CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8739// CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8740// CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8741// CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8742// CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 0, ptr @__main_block_invoke.omp_outlined)743// CHECK4-NEXT: ret void744//745//746// CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke.omp_outlined747// CHECK4-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4:[0-9]+]] {748// CHECK4-NEXT: entry:749// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8750// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8751// CHECK4-NEXT: [[G:%.*]] = alloca i32, align 128752// CHECK4-NEXT: [[SIVAR:%.*]] = alloca i32, align 4753// CHECK4-NEXT: [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, align 128754// CHECK4-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8755// CHECK4-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8756// CHECK4-NEXT: store i32 1, ptr [[G]], align 128757// CHECK4-NEXT: store i32 20, ptr [[SIVAR]], align 4758// CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 0759// CHECK4-NEXT: store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 128760// CHECK4-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 1761// CHECK4-NEXT: store i32 1073741824, ptr [[BLOCK_FLAGS]], align 8762// CHECK4-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 2763// CHECK4-NEXT: store i32 0, ptr [[BLOCK_RESERVED]], align 4764// CHECK4-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 3765// CHECK4-NEXT: store ptr @g_block_invoke, ptr [[BLOCK_INVOKE]], align 16766// CHECK4-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 4767// CHECK4-NEXT: store ptr @__block_descriptor_tmp.1, ptr [[BLOCK_DESCRIPTOR]], align 8768// CHECK4-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 7769// CHECK4-NEXT: [[TMP0:%.*]] = load volatile i32, ptr [[G]], align 128770// CHECK4-NEXT: store volatile i32 [[TMP0]], ptr [[BLOCK_CAPTURED]], align 128771// CHECK4-NEXT: [[BLOCK_CAPTURED1:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 5772// CHECK4-NEXT: [[TMP1:%.*]] = load i32, ptr [[SIVAR]], align 4773// CHECK4-NEXT: store i32 [[TMP1]], ptr [[BLOCK_CAPTURED1]], align 32774// CHECK4-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3775// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8776// CHECK4-NEXT: call void [[TMP3]](ptr noundef [[BLOCK]])777// CHECK4-NEXT: ret void778//779//780// CHECK4-LABEL: define {{[^@]+}}@g_block_invoke781// CHECK4-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR3]] {782// CHECK4-NEXT: entry:783// CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8784// CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8785// CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8786// CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8787// CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 7788// CHECK4-NEXT: store i32 2, ptr [[BLOCK_CAPTURE_ADDR]], align 128789// CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 5790// CHECK4-NEXT: store i32 40, ptr [[BLOCK_CAPTURE_ADDR1]], align 32791// CHECK4-NEXT: ret void792//793//794// CHECK4-LABEL: define {{[^@]+}}@_ZN2SSC2ERi795// CHECK4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {796// CHECK4-NEXT: entry:797// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8798// CHECK4-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8799// CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8800// CHECK4-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8801// CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8802// CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0803// CHECK4-NEXT: store i32 0, ptr [[A]], align 8804// CHECK4-NEXT: [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1805// CHECK4-NEXT: [[BF_LOAD:%.*]] = load i8, ptr [[B]], align 4806// CHECK4-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16807// CHECK4-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0808// CHECK4-NEXT: store i8 [[BF_SET]], ptr [[B]], align 4809// CHECK4-NEXT: [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2810// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8811// CHECK4-NEXT: store ptr [[TMP0]], ptr [[C]], align 8812// CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @_ZN2SSC2ERi.omp_outlined, ptr [[THIS1]])813// CHECK4-NEXT: ret void814//815//816// CHECK4-LABEL: define {{[^@]+}}@_ZN2SSC2ERi.omp_outlined817// CHECK4-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]]) #[[ATTR4]] {818// CHECK4-NEXT: entry:819// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8820// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8821// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8822// CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4823// CHECK4-NEXT: [[TMP:%.*]] = alloca ptr, align 8824// CHECK4-NEXT: [[B:%.*]] = alloca i32, align 4825// CHECK4-NEXT: [[C:%.*]] = alloca i32, align 4826// CHECK4-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8827// CHECK4-NEXT: [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, align 8828// CHECK4-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8829// CHECK4-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8830// CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8831// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8832// CHECK4-NEXT: store ptr [[A]], ptr [[TMP]], align 8833// CHECK4-NEXT: store ptr [[C]], ptr [[_TMP1]], align 8834// CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 0835// CHECK4-NEXT: store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 8836// CHECK4-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 1837// CHECK4-NEXT: store i32 1073741824, ptr [[BLOCK_FLAGS]], align 8838// CHECK4-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 2839// CHECK4-NEXT: store i32 0, ptr [[BLOCK_RESERVED]], align 4840// CHECK4-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 3841// CHECK4-NEXT: store ptr @g_block_invoke_2, ptr [[BLOCK_INVOKE]], align 8842// CHECK4-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 4843// CHECK4-NEXT: store ptr @__block_descriptor_tmp.2, ptr [[BLOCK_DESCRIPTOR]], align 8844// CHECK4-NEXT: [[BLOCK_CAPTURED_THIS_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 5845// CHECK4-NEXT: store ptr [[TMP0]], ptr [[BLOCK_CAPTURED_THIS_ADDR]], align 8846// CHECK4-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 6847// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8848// CHECK4-NEXT: store ptr [[TMP1]], ptr [[BLOCK_CAPTURED]], align 8849// CHECK4-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 8850// CHECK4-NEXT: [[TMP2:%.*]] = load i32, ptr [[B]], align 4851// CHECK4-NEXT: store i32 [[TMP2]], ptr [[BLOCK_CAPTURED2]], align 8852// CHECK4-NEXT: [[BLOCK_CAPTURED3:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 7853// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[_TMP1]], align 8854// CHECK4-NEXT: store ptr [[TMP3]], ptr [[BLOCK_CAPTURED3]], align 8855// CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3856// CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8857// CHECK4-NEXT: call void [[TMP5]](ptr noundef [[BLOCK]])858// CHECK4-NEXT: ret void859//860//861// CHECK4-LABEL: define {{[^@]+}}@g_block_invoke_2862// CHECK4-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR3]] {863// CHECK4-NEXT: entry:864// CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8865// CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8866// CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8867// CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8868// CHECK4-NEXT: [[BLOCK_CAPTURED_THIS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 5869// CHECK4-NEXT: [[THIS:%.*]] = load ptr, ptr [[BLOCK_CAPTURED_THIS]], align 8870// CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 6871// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR]], align 8872// CHECK4-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4873// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1874// CHECK4-NEXT: store i32 [[INC]], ptr [[TMP0]], align 4875// CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 8876// CHECK4-NEXT: [[TMP2:%.*]] = load i32, ptr [[BLOCK_CAPTURE_ADDR1]], align 8877// CHECK4-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP2]], -1878// CHECK4-NEXT: store i32 [[DEC]], ptr [[BLOCK_CAPTURE_ADDR1]], align 8879// CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 7880// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR2]], align 8881// CHECK4-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4882// CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP4]], 1883// CHECK4-NEXT: store i32 [[DIV]], ptr [[TMP3]], align 4884// CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @g_block_invoke_2.omp_outlined, ptr [[THIS]])885// CHECK4-NEXT: ret void886//887//888// CHECK4-LABEL: define {{[^@]+}}@g_block_invoke_2.omp_outlined889// CHECK4-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]]) #[[ATTR4]] {890// CHECK4-NEXT: entry:891// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8892// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8893// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8894// CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4895// CHECK4-NEXT: [[TMP:%.*]] = alloca ptr, align 8896// CHECK4-NEXT: [[B:%.*]] = alloca i32, align 4897// CHECK4-NEXT: [[C:%.*]] = alloca i32, align 4898// CHECK4-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8899// CHECK4-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8900// CHECK4-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8901// CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8902// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8903// CHECK4-NEXT: store ptr [[A]], ptr [[TMP]], align 8904// CHECK4-NEXT: store ptr [[C]], ptr [[_TMP1]], align 8905// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8906// CHECK4-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4907// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1908// CHECK4-NEXT: store i32 [[INC]], ptr [[TMP1]], align 4909// CHECK4-NEXT: [[TMP3:%.*]] = load i32, ptr [[B]], align 4910// CHECK4-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1911// CHECK4-NEXT: store i32 [[DEC]], ptr [[B]], align 4912// CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP1]], align 8913// CHECK4-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4914// CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1915// CHECK4-NEXT: store i32 [[DIV]], ptr [[TMP4]], align 4916// CHECK4-NEXT: ret void917//918