2268 lines · cpp
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _2// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=52 -fnoopenmp-use-tls -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK13 4// RUN: %clang_cc1 -fopenmp -fopenmp-version=52 -fnoopenmp-use-tls -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s5// RUN: %clang_cc1 -fopenmp -fopenmp-version=52 -fnoopenmp-use-tls -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 7// RUN: %clang_cc1 -fopenmp -fopenmp-version=52 -fnoopenmp-use-tls -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s8// RUN: %clang_cc1 -fopenmp -fopenmp-version=52 -fnoopenmp-use-tls -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK49 10// RUN: %clang_cc1 -verify -Wno-vla -triple x86_64-apple-darwin10 -std=c++11 -fopenmp -fopenmp-version=52 -fnoopenmp-use-tls -fexceptions -fcxx-exceptions -debug-info-kind=line-tables-only -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK511// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=52 -fnoopenmp-use-tls -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK612 13// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=52 -fnoopenmp-use-tls -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"14// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=52 -fnoopenmp-use-tls -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s15// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=52 -fnoopenmp-use-tls -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"16// RUN: %clang_cc1 -verify -Wno-vla -triple x86_64-apple-darwin10 -std=c++11 -fopenmp-simd -fopenmp-version=52 -fnoopenmp-use-tls -fexceptions -fcxx-exceptions -debug-info-kind=line-tables-only -x c++ -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"17// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=52 -fnoopenmp-use-tls -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"18// expected-no-diagnostics19 20typedef void **omp_allocator_handle_t;21extern const omp_allocator_handle_t omp_null_allocator;22extern const omp_allocator_handle_t omp_default_mem_alloc;23extern const omp_allocator_handle_t omp_large_cap_mem_alloc;24extern const omp_allocator_handle_t omp_const_mem_alloc;25extern const omp_allocator_handle_t omp_high_bw_mem_alloc;26extern const omp_allocator_handle_t omp_low_lat_mem_alloc;27extern const omp_allocator_handle_t omp_cgroup_mem_alloc;28extern const omp_allocator_handle_t omp_pteam_mem_alloc;29extern const omp_allocator_handle_t omp_thread_mem_alloc;30 31#ifndef ARRAY32#ifndef HEADER33#define HEADER34 35class TestClass {36public:37 int a;38 TestClass() : a(0) {}39 TestClass(const TestClass &C) : a(C.a) {}40 TestClass &operator=(const TestClass &) { return *this;}41 ~TestClass(){};42};43 44 45TestClass tc;46TestClass tc2[2];47 48void foo() { extern void mayThrow(); mayThrow(); }49 50struct SS {51 int e;52 int a;53 int b : 4;54 int &c;55 SS(int &d) : a(0), b(0), c(d) {56#pragma omp scope private(a, this->b, (this)->c) allocate(omp_default_mem_alloc:b) nowait57 [&]() {58 ++this->a, --b, (this)->c /= 1;59#pragma omp parallel num_threads(b)60#pragma omp scope firstprivate(a, this->b, (this)->c) reduction(+:e)61 ++(this)->a, e+=1, this->c /= 1;62 }();63 }64};65 66template<typename T>67struct SST {68 T a;69 SST() : a(T()) {70#pragma omp target teams71#pragma omp parallel firstprivate(a)72#pragma omp scope private(this->a)73 [&]() {74 [&]() {75 int c;76 ++this->a;77#pragma omp parallel firstprivate(a)78#pragma omp scope private((this)->a) allocate(omp_cgroup_mem_alloc:a)79 ++(this)->a;80 }();81 }();82 }83};84 85int main() {86 char a;87 char a2[2];88 TestClass &c = tc;89 SST<double> sst;90 SS ss(c.a);91 92#pragma omp scope nowait93 a = 2;94#pragma omp scope95 a = 2;96#pragma omp scope firstprivate(a,c, tc) private(a2, tc2)97 foo();98 return a;99}100 101 102void parallel_single() {103#pragma omp parallel104#pragma omp scope105 foo();106}107#endif108#else109struct St {110 int a, b;111 St() : a(0), b(0) {}112 St &operator=(const St &) { return *this; };113 ~St() {}114};115 116void array_func(int n, int a[n], St s[2]) {117 int b,c;118#pragma omp scope nowait firstprivate(b) allocate(omp_high_bw_mem_alloc:c) private(a,s) reduction(*:c)119 ;120}121 122int main() {123 int n;124 int a[10];125 St s[2];126 127 array_func(n, a, s);128 return 0;129}130#endif131// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init132// CHECK1-SAME: () #[[ATTR0:[0-9]+]] {133// CHECK1-NEXT: entry:134// CHECK1-NEXT: call void @_ZN9TestClassC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @tc)135// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN9TestClassD1Ev, ptr @tc, ptr @__dso_handle) #[[ATTR3:[0-9]+]]136// CHECK1-NEXT: ret void137//138//139// CHECK1-LABEL: define {{[^@]+}}@_ZN9TestClassC1Ev140// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {141// CHECK1-NEXT: entry:142// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8143// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8144// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8145// CHECK1-NEXT: call void @_ZN9TestClassC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])146// CHECK1-NEXT: ret void147//148//149// CHECK1-LABEL: define {{[^@]+}}@_ZN9TestClassD1Ev150// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 {151// CHECK1-NEXT: entry:152// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8153// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8154// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8155// CHECK1-NEXT: call void @_ZN9TestClassD2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]]156// CHECK1-NEXT: ret void157//158//159// CHECK1-LABEL: define {{[^@]+}}@_ZN9TestClassC2Ev160// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {161// CHECK1-NEXT: entry:162// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8163// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8164// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8165// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[CLASS_TESTCLASS:%.*]], ptr [[THIS1]], i32 0, i32 0166// CHECK1-NEXT: store i32 0, ptr [[A]], align 4167// CHECK1-NEXT: ret void168//169//170// CHECK1-LABEL: define {{[^@]+}}@_ZN9TestClassD2Ev171// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {172// CHECK1-NEXT: entry:173// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8174// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8175// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8176// CHECK1-NEXT: ret void177//178//179// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1180// CHECK1-SAME: () #[[ATTR0]] personality ptr @__gxx_personality_v0 {181// CHECK1-NEXT: entry:182// CHECK1-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8183// CHECK1-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4184// CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]185// CHECK1: arrayctor.loop:186// CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ @tc2, [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[INVOKE_CONT:%.*]] ]187// CHECK1-NEXT: invoke void @_ZN9TestClassC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])188// CHECK1-NEXT: to label [[INVOKE_CONT]] unwind label [[LPAD:%.*]]189// CHECK1: invoke.cont:190// CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[CLASS_TESTCLASS:%.*]], ptr [[ARRAYCTOR_CUR]], i64 1191// CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], getelementptr inbounds ([[CLASS_TESTCLASS]], ptr @tc2, i64 2)192// CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]193// CHECK1: arrayctor.cont:194// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]]195// CHECK1-NEXT: ret void196// CHECK1: lpad:197// CHECK1-NEXT: [[TMP1:%.*]] = landingpad { ptr, i32 }198// CHECK1-NEXT: cleanup199// CHECK1-NEXT: [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0200// CHECK1-NEXT: store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8201// CHECK1-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1202// CHECK1-NEXT: store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4203// CHECK1-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @tc2, [[ARRAYCTOR_CUR]]204// CHECK1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY:%.*]]205// CHECK1: arraydestroy.body:206// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[ARRAYCTOR_CUR]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]207// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1208// CHECK1-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]209// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @tc2210// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1]], label [[ARRAYDESTROY_BODY]]211// CHECK1: arraydestroy.done1:212// CHECK1-NEXT: br label [[EH_RESUME:%.*]]213// CHECK1: eh.resume:214// CHECK1-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8215// CHECK1-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4216// CHECK1-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0217// CHECK1-NEXT: [[LPAD_VAL2:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1218// CHECK1-NEXT: resume { ptr, i32 } [[LPAD_VAL2]]219//220//221// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor222// CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {223// CHECK1-NEXT: entry:224// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8225// CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8226// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]227// CHECK1: arraydestroy.body:228// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[CLASS_TESTCLASS:%.*]], ptr @tc2, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]229// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1230// CHECK1-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]231// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @tc2232// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]233// CHECK1: arraydestroy.done1:234// CHECK1-NEXT: ret void235//236//237// CHECK1-LABEL: define {{[^@]+}}@_Z3foov238// CHECK1-SAME: () #[[ATTR1]] {239// CHECK1-NEXT: entry:240// CHECK1-NEXT: call void @_Z8mayThrowv()241// CHECK1-NEXT: ret void242//243//244// CHECK1-LABEL: define {{[^@]+}}@main245// CHECK1-SAME: () #[[ATTR5:[0-9]+]] personality ptr @__gxx_personality_v0 {246// CHECK1-NEXT: entry:247// CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4248// CHECK1-NEXT: [[A:%.*]] = alloca i8, align 1249// CHECK1-NEXT: [[A2:%.*]] = alloca [2 x i8], align 1250// CHECK1-NEXT: [[C:%.*]] = alloca ptr, align 8251// CHECK1-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 8252// CHECK1-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8253// CHECK1-NEXT: [[A1:%.*]] = alloca i8, align 1254// CHECK1-NEXT: [[C2:%.*]] = alloca [[CLASS_TESTCLASS:%.*]], align 4255// CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8256// CHECK1-NEXT: [[TC:%.*]] = alloca [[CLASS_TESTCLASS]], align 4257// CHECK1-NEXT: [[A24:%.*]] = alloca [2 x i8], align 1258// CHECK1-NEXT: [[TC2:%.*]] = alloca [2 x %class.TestClass], align 4259// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])260// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4261// CHECK1-NEXT: store ptr @tc, ptr [[C]], align 8262// CHECK1-NEXT: call void @_ZN3SSTIdEC1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[SST]])263// CHECK1-NEXT: call void @_ZN2SSC1ERi(ptr noundef nonnull align 8 dereferenceable(24) [[SS]], ptr noundef nonnull align 4 dereferenceable(4) @tc)264// CHECK1-NEXT: store i8 2, ptr [[A]], align 1265// CHECK1-NEXT: store i8 2, ptr [[A]], align 1266// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB1:[0-9]+]], i32 [[TMP0]])267// CHECK1-NEXT: [[TMP1:%.*]] = load i8, ptr [[A]], align 1268// CHECK1-NEXT: store i8 [[TMP1]], ptr [[A1]], align 1269// CHECK1-NEXT: invoke void @_ZN9TestClassC1ERKS_(ptr noundef nonnull align 4 dereferenceable(4) [[C2]], ptr noundef nonnull align 4 dereferenceable(4) @tc)270// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]]271// CHECK1: invoke.cont:272// CHECK1-NEXT: store ptr [[C2]], ptr [[TMP]], align 8273// CHECK1-NEXT: invoke void @_ZN9TestClassC1ERKS_(ptr noundef nonnull align 4 dereferenceable(4) [[TC]], ptr noundef nonnull align 4 dereferenceable(4) @tc)274// CHECK1-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[TERMINATE_LPAD]]275// CHECK1: invoke.cont3:276// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %class.TestClass], ptr [[TC2]], i32 0, i32 0277// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAY_BEGIN]], i64 2278// CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]279// CHECK1: arrayctor.loop:280// CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[INVOKE_CONT3]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[INVOKE_CONT5:%.*]] ]281// CHECK1-NEXT: invoke void @_ZN9TestClassC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])282// CHECK1-NEXT: to label [[INVOKE_CONT5]] unwind label [[TERMINATE_LPAD]]283// CHECK1: invoke.cont5:284// CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYCTOR_CUR]], i64 1285// CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]286// CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]287// CHECK1: arrayctor.cont:288// CHECK1-NEXT: invoke void @_Z3foov()289// CHECK1-NEXT: to label [[INVOKE_CONT6:%.*]] unwind label [[TERMINATE_LPAD]]290// CHECK1: invoke.cont6:291// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %class.TestClass], ptr [[TC2]], i32 0, i32 0292// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAY_BEGIN7]], i64 2293// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]294// CHECK1: arraydestroy.body:295// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[INVOKE_CONT6]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]296// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1297// CHECK1-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]298// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]299// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]300// CHECK1: arraydestroy.done8:301// CHECK1-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TC]]) #[[ATTR3]]302// CHECK1-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[C2]]) #[[ATTR3]]303// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB1]], i32 [[TMP0]])304// CHECK1-NEXT: [[TMP3:%.*]] = load i8, ptr [[A]], align 1305// CHECK1-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32306// CHECK1-NEXT: ret i32 [[CONV]]307// CHECK1: terminate.lpad:308// CHECK1-NEXT: [[TMP4:%.*]] = landingpad { ptr, i32 }309// CHECK1-NEXT: catch ptr null310// CHECK1-NEXT: [[TMP5:%.*]] = extractvalue { ptr, i32 } [[TMP4]], 0311// CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP5]]) #[[ATTR10:[0-9]+]]312// CHECK1-NEXT: unreachable313//314//315// CHECK1-LABEL: define {{[^@]+}}@_ZN3SSTIdEC1Ev316// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {317// CHECK1-NEXT: entry:318// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8319// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8320// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8321// CHECK1-NEXT: call void @_ZN3SSTIdEC2Ev(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]])322// CHECK1-NEXT: ret void323//324//325// CHECK1-LABEL: define {{[^@]+}}@_ZN2SSC1ERi326// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {327// CHECK1-NEXT: entry:328// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8329// CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8330// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8331// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8332// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8333// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8334// CHECK1-NEXT: call void @_ZN2SSC2ERi(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]])335// CHECK1-NEXT: ret void336//337//338// CHECK1-LABEL: define {{[^@]+}}@_ZN9TestClassC1ERKS_339// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {340// CHECK1-NEXT: entry:341// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8342// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8343// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8344// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8345// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8346// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8347// CHECK1-NEXT: call void @_ZN9TestClassC2ERKS_(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]])348// CHECK1-NEXT: ret void349//350//351// CHECK1-LABEL: define {{[^@]+}}@__clang_call_terminate352// CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR7:[0-9]+]] comdat {353// CHECK1-NEXT: [[TMP2:%.*]] = call ptr @__cxa_begin_catch(ptr [[TMP0]]) #[[ATTR3]]354// CHECK1-NEXT: call void @_ZSt9terminatev() #[[ATTR10]]355// CHECK1-NEXT: unreachable356//357//358//359//360//361//362//363//364//365// CHECK1-LABEL: define {{[^@]+}}@_ZN2SSC2ERi366// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 personality ptr @__gxx_personality_v0 {367// CHECK1-NEXT: entry:368// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8369// CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8370// CHECK1-NEXT: [[A2:%.*]] = alloca i32, align 4371// CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8372// CHECK1-NEXT: [[C3:%.*]] = alloca i32, align 4373// CHECK1-NEXT: [[_TMP4:%.*]] = alloca ptr, align 8374// CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_1:%.*]], align 8375// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])376// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8377// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8378// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8379// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 1380// CHECK1-NEXT: store i32 0, ptr [[A]], align 4381// CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2382// CHECK1-NEXT: [[BF_LOAD:%.*]] = load i8, ptr [[B]], align 8383// CHECK1-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16384// CHECK1-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0385// CHECK1-NEXT: store i8 [[BF_SET]], ptr [[B]], align 8386// CHECK1-NEXT: [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 3387// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[D_ADDR]], align 8388// CHECK1-NEXT: store ptr [[TMP1]], ptr [[C]], align 8389// CHECK1-NEXT: store ptr [[A2]], ptr [[TMP]], align 8390// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr @omp_default_mem_alloc, align 8391// CHECK1-NEXT: [[DOTB__VOID_ADDR:%.*]] = call ptr @__kmpc_alloc(i32 [[TMP0]], i64 4, ptr [[TMP2]])392// CHECK1-NEXT: store ptr [[C3]], ptr [[_TMP4]], align 8393// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 0394// CHECK1-NEXT: store ptr [[THIS1]], ptr [[TMP3]], align 8395// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 1396// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8397// CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 8398// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 2399// CHECK1-NEXT: store ptr [[DOTB__VOID_ADDR]], ptr [[TMP6]], align 8400// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 3401// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP4]], align 8402// CHECK1-NEXT: store ptr [[TMP8]], ptr [[TMP7]], align 8403// CHECK1-NEXT: invoke void @_ZZN2SSC1ERiENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(32) [[REF_TMP]])404// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]]405// CHECK1: invoke.cont:406// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr @omp_default_mem_alloc, align 8407// CHECK1-NEXT: call void @__kmpc_free(i32 [[TMP0]], ptr [[DOTB__VOID_ADDR]], ptr [[TMP9]])408// CHECK1-NEXT: ret void409// CHECK1: terminate.lpad:410// CHECK1-NEXT: [[TMP10:%.*]] = landingpad { ptr, i32 }411// CHECK1-NEXT: catch ptr null412// CHECK1-NEXT: [[TMP11:%.*]] = extractvalue { ptr, i32 } [[TMP10]], 0413// CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP11]]) #[[ATTR10]]414// CHECK1-NEXT: unreachable415//416//417// CHECK1-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv418// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR2]] align 2 {419// CHECK1-NEXT: entry:420// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8421// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])422// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8423// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8424// CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1:%.*]], ptr [[THIS1]], i32 0, i32 0425// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8426// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 1427// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8428// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4429// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1430// CHECK1-NEXT: store i32 [[INC]], ptr [[TMP4]], align 4431// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 2432// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8433// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4434// CHECK1-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP8]], -1435// CHECK1-NEXT: store i32 [[DEC]], ptr [[TMP7]], align 4436// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 3437// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8438// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4439// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP11]], 1440// CHECK1-NEXT: store i32 [[DIV]], ptr [[TMP10]], align 4441// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 2442// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP12]], align 8443// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4444// CHECK1-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP14]])445// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 1446// CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8447// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 2448// CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8449// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 3450// CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8451// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined, ptr [[TMP2]], ptr [[TMP16]], ptr [[TMP18]], ptr [[TMP20]])452// CHECK1-NEXT: ret void453//454//455// CHECK1-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined456// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR8:[0-9]+]] {457// CHECK1-NEXT: entry:458// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8459// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8460// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8461// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8462// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8463// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8464// CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8465// CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8466// CHECK1-NEXT: [[E:%.*]] = alloca ptr, align 8467// CHECK1-NEXT: [[_TMP3:%.*]] = alloca ptr, align 8468// CHECK1-NEXT: [[_TMP4:%.*]] = alloca ptr, align 8469// CHECK1-NEXT: [[_TMP5:%.*]] = alloca ptr, align 8470// CHECK1-NEXT: [[A6:%.*]] = alloca i32, align 4471// CHECK1-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8472// CHECK1-NEXT: [[B8:%.*]] = alloca i32, align 4473// CHECK1-NEXT: [[C9:%.*]] = alloca i32, align 4474// CHECK1-NEXT: [[_TMP10:%.*]] = alloca ptr, align 8475// CHECK1-NEXT: [[E11:%.*]] = alloca i32, align 4476// CHECK1-NEXT: [[_TMP12:%.*]] = alloca ptr, align 8477// CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8478// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8479// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8480// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8481// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8482// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8483// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8484// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8485// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8486// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8487// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8488// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8489// CHECK1-NEXT: store ptr [[TMP3]], ptr [[_TMP1]], align 8490// CHECK1-NEXT: [[E2:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0491// CHECK1-NEXT: store ptr [[E2]], ptr [[E]], align 8492// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8493// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP3]], align 8494// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[E]], align 8495// CHECK1-NEXT: store ptr [[TMP5]], ptr [[_TMP4]], align 8496// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8497// CHECK1-NEXT: store ptr [[TMP6]], ptr [[_TMP5]], align 8498// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP3]], align 8499// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4500// CHECK1-NEXT: store i32 [[TMP8]], ptr [[A6]], align 4501// CHECK1-NEXT: store ptr [[A6]], ptr [[_TMP7]], align 8502// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP2]], align 4503// CHECK1-NEXT: store i32 [[TMP9]], ptr [[B8]], align 4504// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP5]], align 8505// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4506// CHECK1-NEXT: store i32 [[TMP11]], ptr [[C9]], align 4507// CHECK1-NEXT: store ptr [[C9]], ptr [[_TMP10]], align 8508// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP4]], align 8509// CHECK1-NEXT: store i32 0, ptr [[E11]], align 4510// CHECK1-NEXT: store ptr [[E11]], ptr [[_TMP12]], align 8511// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP7]], align 8512// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4513// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1514// CHECK1-NEXT: store i32 [[INC]], ptr [[TMP13]], align 4515// CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP12]], align 8516// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4517// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1518// CHECK1-NEXT: store i32 [[ADD]], ptr [[TMP15]], align 4519// CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP10]], align 8520// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4521// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP18]], 1522// CHECK1-NEXT: store i32 [[DIV]], ptr [[TMP17]], align 4523// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0524// CHECK1-NEXT: store ptr [[E11]], ptr [[TMP19]], align 8525// CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8526// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4527// CHECK1-NEXT: [[TMP22:%.*]] = call i32 @__kmpc_reduce(ptr @[[GLOB3:[0-9]+]], i32 [[TMP21]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var)528// CHECK1-NEXT: switch i32 [[TMP22]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [529// CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]]530// CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]]531// CHECK1-NEXT: ]532// CHECK1: .omp.reduction.case1:533// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP12]], align 4534// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[E11]], align 4535// CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP23]], [[TMP24]]536// CHECK1-NEXT: store i32 [[ADD13]], ptr [[TMP12]], align 4537// CHECK1-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB3]], i32 [[TMP21]], ptr @.gomp_critical_user_.reduction.var)538// CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]539// CHECK1: .omp.reduction.case2:540// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[E11]], align 4541// CHECK1-NEXT: [[TMP26:%.*]] = atomicrmw add ptr [[TMP12]], i32 [[TMP25]] monotonic, align 4542// CHECK1-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB3]], i32 [[TMP21]], ptr @.gomp_critical_user_.reduction.var)543// CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]544// CHECK1: .omp.reduction.default:545// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB1]], i32 [[TMP21]])546// CHECK1-NEXT: ret void547//548//549// CHECK1-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined.omp.reduction.reduction_func550// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR9:[0-9]+]] {551// CHECK1-NEXT: entry:552// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8553// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8554// CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8555// CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8556// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8557// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8558// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0559// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8560// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0561// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8562// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4563// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP5]], align 4564// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]]565// CHECK1-NEXT: store i32 [[ADD]], ptr [[TMP7]], align 4566// CHECK1-NEXT: ret void567//568//569// CHECK1-LABEL: define {{[^@]+}}@_ZN9TestClassC2ERKS_570// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {571// CHECK1-NEXT: entry:572// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8573// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8574// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8575// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8576// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8577// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[CLASS_TESTCLASS:%.*]], ptr [[THIS1]], i32 0, i32 0578// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8579// CHECK1-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[CLASS_TESTCLASS]], ptr [[TMP0]], i32 0, i32 0580// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A2]], align 4581// CHECK1-NEXT: store i32 [[TMP1]], ptr [[A]], align 4582// CHECK1-NEXT: ret void583//584//585// CHECK1-LABEL: define {{[^@]+}}@_Z15parallel_singlev586// CHECK1-SAME: () #[[ATTR2]] {587// CHECK1-NEXT: entry:588// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @_Z15parallel_singlev.omp_outlined)589// CHECK1-NEXT: ret void590//591//592// CHECK1-LABEL: define {{[^@]+}}@_Z15parallel_singlev.omp_outlined593// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR8]] personality ptr @__gxx_personality_v0 {594// CHECK1-NEXT: entry:595// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8596// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8597// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8598// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8599// CHECK1-NEXT: invoke void @_Z3foov()600// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]]601// CHECK1: invoke.cont:602// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8603// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4604// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB1]], i32 [[TMP1]])605// CHECK1-NEXT: ret void606// CHECK1: terminate.lpad:607// CHECK1-NEXT: [[TMP2:%.*]] = landingpad { ptr, i32 }608// CHECK1-NEXT: catch ptr null609// CHECK1-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP2]], 0610// CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP3]]) #[[ATTR10]]611// CHECK1-NEXT: unreachable612//613//614// CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_scope_codegen.cpp615// CHECK1-SAME: () #[[ATTR0]] {616// CHECK1-NEXT: entry:617// CHECK1-NEXT: call void @__cxx_global_var_init()618// CHECK1-NEXT: call void @__cxx_global_var_init.1()619// CHECK1-NEXT: ret void620//621//622//623//624//625//626//627//628//629// CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init630// CHECK4-SAME: () #[[ATTR0:[0-9]+]] {631// CHECK4-NEXT: entry:632// CHECK4-NEXT: call void @_ZN9TestClassC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @tc)633// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN9TestClassD1Ev, ptr @tc, ptr @__dso_handle) #[[ATTR3:[0-9]+]]634// CHECK4-NEXT: ret void635//636//637// CHECK4-LABEL: define {{[^@]+}}@_ZN9TestClassC1Ev638// CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {639// CHECK4-NEXT: entry:640// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8641// CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8642// CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8643// CHECK4-NEXT: call void @_ZN9TestClassC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])644// CHECK4-NEXT: ret void645//646//647// CHECK4-LABEL: define {{[^@]+}}@_ZN9TestClassD1Ev648// CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 {649// CHECK4-NEXT: entry:650// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8651// CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8652// CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8653// CHECK4-NEXT: call void @_ZN9TestClassD2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]]654// CHECK4-NEXT: ret void655//656//657// CHECK4-LABEL: define {{[^@]+}}@_ZN9TestClassC2Ev658// CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {659// CHECK4-NEXT: entry:660// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8661// CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8662// CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8663// CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[CLASS_TESTCLASS:%.*]], ptr [[THIS1]], i32 0, i32 0664// CHECK4-NEXT: store i32 0, ptr [[A]], align 4665// CHECK4-NEXT: ret void666//667//668// CHECK4-LABEL: define {{[^@]+}}@_ZN9TestClassD2Ev669// CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {670// CHECK4-NEXT: entry:671// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8672// CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8673// CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8674// CHECK4-NEXT: ret void675//676//677// CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1678// CHECK4-SAME: () #[[ATTR0]] personality ptr @__gxx_personality_v0 {679// CHECK4-NEXT: entry:680// CHECK4-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8681// CHECK4-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4682// CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]683// CHECK4: arrayctor.loop:684// CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ @tc2, [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[INVOKE_CONT:%.*]] ]685// CHECK4-NEXT: invoke void @_ZN9TestClassC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])686// CHECK4-NEXT: to label [[INVOKE_CONT]] unwind label [[LPAD:%.*]]687// CHECK4: invoke.cont:688// CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[CLASS_TESTCLASS:%.*]], ptr [[ARRAYCTOR_CUR]], i64 1689// CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], getelementptr inbounds ([[CLASS_TESTCLASS]], ptr @tc2, i64 2)690// CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]691// CHECK4: arrayctor.cont:692// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]]693// CHECK4-NEXT: ret void694// CHECK4: lpad:695// CHECK4-NEXT: [[TMP1:%.*]] = landingpad { ptr, i32 }696// CHECK4-NEXT: cleanup697// CHECK4-NEXT: [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0698// CHECK4-NEXT: store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8699// CHECK4-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1700// CHECK4-NEXT: store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4701// CHECK4-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @tc2, [[ARRAYCTOR_CUR]]702// CHECK4-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY:%.*]]703// CHECK4: arraydestroy.body:704// CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[ARRAYCTOR_CUR]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]705// CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1706// CHECK4-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]707// CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @tc2708// CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1]], label [[ARRAYDESTROY_BODY]]709// CHECK4: arraydestroy.done1:710// CHECK4-NEXT: br label [[EH_RESUME:%.*]]711// CHECK4: eh.resume:712// CHECK4-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8713// CHECK4-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4714// CHECK4-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0715// CHECK4-NEXT: [[LPAD_VAL2:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1716// CHECK4-NEXT: resume { ptr, i32 } [[LPAD_VAL2]]717//718//719// CHECK4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor720// CHECK4-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {721// CHECK4-NEXT: entry:722// CHECK4-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8723// CHECK4-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8724// CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]725// CHECK4: arraydestroy.body:726// CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[CLASS_TESTCLASS:%.*]], ptr @tc2, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]727// CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1728// CHECK4-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]729// CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @tc2730// CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]731// CHECK4: arraydestroy.done1:732// CHECK4-NEXT: ret void733//734//735// CHECK4-LABEL: define {{[^@]+}}@_Z3foov736// CHECK4-SAME: () #[[ATTR1]] {737// CHECK4-NEXT: entry:738// CHECK4-NEXT: call void @_Z8mayThrowv()739// CHECK4-NEXT: ret void740//741//742// CHECK4-LABEL: define {{[^@]+}}@main743// CHECK4-SAME: () #[[ATTR5:[0-9]+]] personality ptr @__gxx_personality_v0 {744// CHECK4-NEXT: entry:745// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4746// CHECK4-NEXT: [[A:%.*]] = alloca i8, align 1747// CHECK4-NEXT: [[A2:%.*]] = alloca [2 x i8], align 1748// CHECK4-NEXT: [[C:%.*]] = alloca ptr, align 8749// CHECK4-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 8750// CHECK4-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8751// CHECK4-NEXT: [[A1:%.*]] = alloca i8, align 1752// CHECK4-NEXT: [[C2:%.*]] = alloca [[CLASS_TESTCLASS:%.*]], align 4753// CHECK4-NEXT: [[TMP:%.*]] = alloca ptr, align 8754// CHECK4-NEXT: [[TC:%.*]] = alloca [[CLASS_TESTCLASS]], align 4755// CHECK4-NEXT: [[A24:%.*]] = alloca [2 x i8], align 1756// CHECK4-NEXT: [[TC2:%.*]] = alloca [2 x %class.TestClass], align 4757// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])758// CHECK4-NEXT: store i32 0, ptr [[RETVAL]], align 4759// CHECK4-NEXT: store ptr @tc, ptr [[C]], align 8760// CHECK4-NEXT: call void @_ZN3SSTIdEC1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[SST]])761// CHECK4-NEXT: call void @_ZN2SSC1ERi(ptr noundef nonnull align 8 dereferenceable(24) [[SS]], ptr noundef nonnull align 4 dereferenceable(4) @tc)762// CHECK4-NEXT: store i8 2, ptr [[A]], align 1763// CHECK4-NEXT: store i8 2, ptr [[A]], align 1764// CHECK4-NEXT: call void @__kmpc_barrier(ptr @[[GLOB1:[0-9]+]], i32 [[TMP0]])765// CHECK4-NEXT: [[TMP1:%.*]] = load i8, ptr [[A]], align 1766// CHECK4-NEXT: store i8 [[TMP1]], ptr [[A1]], align 1767// CHECK4-NEXT: invoke void @_ZN9TestClassC1ERKS_(ptr noundef nonnull align 4 dereferenceable(4) [[C2]], ptr noundef nonnull align 4 dereferenceable(4) @tc)768// CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]]769// CHECK4: invoke.cont:770// CHECK4-NEXT: store ptr [[C2]], ptr [[TMP]], align 8771// CHECK4-NEXT: invoke void @_ZN9TestClassC1ERKS_(ptr noundef nonnull align 4 dereferenceable(4) [[TC]], ptr noundef nonnull align 4 dereferenceable(4) @tc)772// CHECK4-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[TERMINATE_LPAD]]773// CHECK4: invoke.cont3:774// CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %class.TestClass], ptr [[TC2]], i32 0, i32 0775// CHECK4-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAY_BEGIN]], i64 2776// CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]777// CHECK4: arrayctor.loop:778// CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[INVOKE_CONT3]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[INVOKE_CONT5:%.*]] ]779// CHECK4-NEXT: invoke void @_ZN9TestClassC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])780// CHECK4-NEXT: to label [[INVOKE_CONT5]] unwind label [[TERMINATE_LPAD]]781// CHECK4: invoke.cont5:782// CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYCTOR_CUR]], i64 1783// CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]784// CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]785// CHECK4: arrayctor.cont:786// CHECK4-NEXT: invoke void @_Z3foov()787// CHECK4-NEXT: to label [[INVOKE_CONT6:%.*]] unwind label [[TERMINATE_LPAD]]788// CHECK4: invoke.cont6:789// CHECK4-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %class.TestClass], ptr [[TC2]], i32 0, i32 0790// CHECK4-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAY_BEGIN7]], i64 2791// CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]792// CHECK4: arraydestroy.body:793// CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[INVOKE_CONT6]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]794// CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1795// CHECK4-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]796// CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]797// CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]798// CHECK4: arraydestroy.done8:799// CHECK4-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TC]]) #[[ATTR3]]800// CHECK4-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[C2]]) #[[ATTR3]]801// CHECK4-NEXT: call void @__kmpc_barrier(ptr @[[GLOB1]], i32 [[TMP0]])802// CHECK4-NEXT: [[TMP3:%.*]] = load i8, ptr [[A]], align 1803// CHECK4-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32804// CHECK4-NEXT: ret i32 [[CONV]]805// CHECK4: terminate.lpad:806// CHECK4-NEXT: [[TMP4:%.*]] = landingpad { ptr, i32 }807// CHECK4-NEXT: catch ptr null808// CHECK4-NEXT: [[TMP5:%.*]] = extractvalue { ptr, i32 } [[TMP4]], 0809// CHECK4-NEXT: call void @__clang_call_terminate(ptr [[TMP5]]) #[[ATTR10:[0-9]+]]810// CHECK4-NEXT: unreachable811//812//813// CHECK4-LABEL: define {{[^@]+}}@_ZN3SSTIdEC1Ev814// CHECK4-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {815// CHECK4-NEXT: entry:816// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8817// CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8818// CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8819// CHECK4-NEXT: call void @_ZN3SSTIdEC2Ev(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]])820// CHECK4-NEXT: ret void821//822//823// CHECK4-LABEL: define {{[^@]+}}@_ZN2SSC1ERi824// CHECK4-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {825// CHECK4-NEXT: entry:826// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8827// CHECK4-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8828// CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8829// CHECK4-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8830// CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8831// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8832// CHECK4-NEXT: call void @_ZN2SSC2ERi(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]])833// CHECK4-NEXT: ret void834//835//836// CHECK4-LABEL: define {{[^@]+}}@_ZN9TestClassC1ERKS_837// CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {838// CHECK4-NEXT: entry:839// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8840// CHECK4-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8841// CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8842// CHECK4-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8843// CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8844// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8845// CHECK4-NEXT: call void @_ZN9TestClassC2ERKS_(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]])846// CHECK4-NEXT: ret void847//848//849// CHECK4-LABEL: define {{[^@]+}}@__clang_call_terminate850// CHECK4-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR7:[0-9]+]] comdat {851// CHECK4-NEXT: [[TMP2:%.*]] = call ptr @__cxa_begin_catch(ptr [[TMP0]]) #[[ATTR3]]852// CHECK4-NEXT: call void @_ZSt9terminatev() #[[ATTR10]]853// CHECK4-NEXT: unreachable854//855//856// CHECK4-LABEL: define {{[^@]+}}@_ZN3SSTIdEC2Ev857// CHECK4-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {858// CHECK4-NEXT: entry:859// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8860// CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8861// CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8862// CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SST:%.*]], ptr [[THIS1]], i32 0, i32 0863// CHECK4-NEXT: store double 0.000000e+00, ptr [[A]], align 8864// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr @omp_cgroup_mem_alloc, align 8865// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr @omp_null_allocator, align 8866// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr @omp_default_mem_alloc, align 8867// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr @omp_large_cap_mem_alloc, align 8868// CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr @omp_const_mem_alloc, align 8869// CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr @omp_high_bw_mem_alloc, align 8870// CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr @omp_low_lat_mem_alloc, align 8871// CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr @omp_pteam_mem_alloc, align 8872// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr @omp_thread_mem_alloc, align 8873// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIdEC1Ev_l70(ptr [[THIS1]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], ptr [[TMP4]], ptr [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], ptr [[TMP8]]) #[[ATTR3]]874// CHECK4-NEXT: ret void875//876//877// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIdEC1Ev_l70878// CHECK4-SAME: (ptr noundef [[THIS:%.*]], ptr noundef [[OMP_CGROUP_MEM_ALLOC:%.*]], ptr noundef [[OMP_NULL_ALLOCATOR:%.*]], ptr noundef [[OMP_DEFAULT_MEM_ALLOC:%.*]], ptr noundef [[OMP_LARGE_CAP_MEM_ALLOC:%.*]], ptr noundef [[OMP_CONST_MEM_ALLOC:%.*]], ptr noundef [[OMP_HIGH_BW_MEM_ALLOC:%.*]], ptr noundef [[OMP_LOW_LAT_MEM_ALLOC:%.*]], ptr noundef [[OMP_PTEAM_MEM_ALLOC:%.*]], ptr noundef [[OMP_THREAD_MEM_ALLOC:%.*]]) #[[ATTR8:[0-9]+]] {879// CHECK4-NEXT: entry:880// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8881// CHECK4-NEXT: [[OMP_CGROUP_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8882// CHECK4-NEXT: [[OMP_NULL_ALLOCATOR_ADDR:%.*]] = alloca ptr, align 8883// CHECK4-NEXT: [[OMP_DEFAULT_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8884// CHECK4-NEXT: [[OMP_LARGE_CAP_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8885// CHECK4-NEXT: [[OMP_CONST_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8886// CHECK4-NEXT: [[OMP_HIGH_BW_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8887// CHECK4-NEXT: [[OMP_LOW_LAT_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8888// CHECK4-NEXT: [[OMP_PTEAM_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8889// CHECK4-NEXT: [[OMP_THREAD_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8890// CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8891// CHECK4-NEXT: store ptr [[OMP_CGROUP_MEM_ALLOC]], ptr [[OMP_CGROUP_MEM_ALLOC_ADDR]], align 8892// CHECK4-NEXT: store ptr [[OMP_NULL_ALLOCATOR]], ptr [[OMP_NULL_ALLOCATOR_ADDR]], align 8893// CHECK4-NEXT: store ptr [[OMP_DEFAULT_MEM_ALLOC]], ptr [[OMP_DEFAULT_MEM_ALLOC_ADDR]], align 8894// CHECK4-NEXT: store ptr [[OMP_LARGE_CAP_MEM_ALLOC]], ptr [[OMP_LARGE_CAP_MEM_ALLOC_ADDR]], align 8895// CHECK4-NEXT: store ptr [[OMP_CONST_MEM_ALLOC]], ptr [[OMP_CONST_MEM_ALLOC_ADDR]], align 8896// CHECK4-NEXT: store ptr [[OMP_HIGH_BW_MEM_ALLOC]], ptr [[OMP_HIGH_BW_MEM_ALLOC_ADDR]], align 8897// CHECK4-NEXT: store ptr [[OMP_LOW_LAT_MEM_ALLOC]], ptr [[OMP_LOW_LAT_MEM_ALLOC_ADDR]], align 8898// CHECK4-NEXT: store ptr [[OMP_PTEAM_MEM_ALLOC]], ptr [[OMP_PTEAM_MEM_ALLOC_ADDR]], align 8899// CHECK4-NEXT: store ptr [[OMP_THREAD_MEM_ALLOC]], ptr [[OMP_THREAD_MEM_ALLOC_ADDR]], align 8900// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8901// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[OMP_CGROUP_MEM_ALLOC_ADDR]], align 8902// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[OMP_NULL_ALLOCATOR_ADDR]], align 8903// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[OMP_DEFAULT_MEM_ALLOC_ADDR]], align 8904// CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[OMP_LARGE_CAP_MEM_ALLOC_ADDR]], align 8905// CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[OMP_CONST_MEM_ALLOC_ADDR]], align 8906// CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr [[OMP_HIGH_BW_MEM_ALLOC_ADDR]], align 8907// CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[OMP_LOW_LAT_MEM_ALLOC_ADDR]], align 8908// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[OMP_PTEAM_MEM_ALLOC_ADDR]], align 8909// CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[OMP_THREAD_MEM_ALLOC_ADDR]], align 8910// CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIdEC1Ev_l70.omp_outlined, ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], ptr [[TMP4]], ptr [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], ptr [[TMP8]], ptr [[TMP9]])911// CHECK4-NEXT: ret void912//913//914// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIdEC1Ev_l70.omp_outlined915// CHECK4-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], ptr noundef [[OMP_CGROUP_MEM_ALLOC:%.*]], ptr noundef [[OMP_NULL_ALLOCATOR:%.*]], ptr noundef [[OMP_DEFAULT_MEM_ALLOC:%.*]], ptr noundef [[OMP_LARGE_CAP_MEM_ALLOC:%.*]], ptr noundef [[OMP_CONST_MEM_ALLOC:%.*]], ptr noundef [[OMP_HIGH_BW_MEM_ALLOC:%.*]], ptr noundef [[OMP_LOW_LAT_MEM_ALLOC:%.*]], ptr noundef [[OMP_PTEAM_MEM_ALLOC:%.*]], ptr noundef [[OMP_THREAD_MEM_ALLOC:%.*]]) #[[ATTR8]] {916// CHECK4-NEXT: entry:917// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8918// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8919// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8920// CHECK4-NEXT: [[OMP_CGROUP_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8921// CHECK4-NEXT: [[OMP_NULL_ALLOCATOR_ADDR:%.*]] = alloca ptr, align 8922// CHECK4-NEXT: [[OMP_DEFAULT_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8923// CHECK4-NEXT: [[OMP_LARGE_CAP_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8924// CHECK4-NEXT: [[OMP_CONST_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8925// CHECK4-NEXT: [[OMP_HIGH_BW_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8926// CHECK4-NEXT: [[OMP_LOW_LAT_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8927// CHECK4-NEXT: [[OMP_PTEAM_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8928// CHECK4-NEXT: [[OMP_THREAD_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8929// CHECK4-NEXT: [[A:%.*]] = alloca ptr, align 8930// CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8931// CHECK4-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8932// CHECK4-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8933// CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8934// CHECK4-NEXT: store ptr [[OMP_CGROUP_MEM_ALLOC]], ptr [[OMP_CGROUP_MEM_ALLOC_ADDR]], align 8935// CHECK4-NEXT: store ptr [[OMP_NULL_ALLOCATOR]], ptr [[OMP_NULL_ALLOCATOR_ADDR]], align 8936// CHECK4-NEXT: store ptr [[OMP_DEFAULT_MEM_ALLOC]], ptr [[OMP_DEFAULT_MEM_ALLOC_ADDR]], align 8937// CHECK4-NEXT: store ptr [[OMP_LARGE_CAP_MEM_ALLOC]], ptr [[OMP_LARGE_CAP_MEM_ALLOC_ADDR]], align 8938// CHECK4-NEXT: store ptr [[OMP_CONST_MEM_ALLOC]], ptr [[OMP_CONST_MEM_ALLOC_ADDR]], align 8939// CHECK4-NEXT: store ptr [[OMP_HIGH_BW_MEM_ALLOC]], ptr [[OMP_HIGH_BW_MEM_ALLOC_ADDR]], align 8940// CHECK4-NEXT: store ptr [[OMP_LOW_LAT_MEM_ALLOC]], ptr [[OMP_LOW_LAT_MEM_ALLOC_ADDR]], align 8941// CHECK4-NEXT: store ptr [[OMP_PTEAM_MEM_ALLOC]], ptr [[OMP_PTEAM_MEM_ALLOC_ADDR]], align 8942// CHECK4-NEXT: store ptr [[OMP_THREAD_MEM_ALLOC]], ptr [[OMP_THREAD_MEM_ALLOC_ADDR]], align 8943// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8944// CHECK4-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_SST:%.*]], ptr [[TMP0]], i32 0, i32 0945// CHECK4-NEXT: store ptr [[A1]], ptr [[A]], align 8946// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A]], align 8947// CHECK4-NEXT: [[TMP2:%.*]] = load double, ptr [[TMP1]], align 8948// CHECK4-NEXT: store double [[TMP2]], ptr [[A_CASTED]], align 8949// CHECK4-NEXT: [[TMP3:%.*]] = load i64, ptr [[A_CASTED]], align 8950// CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 11, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIdEC1Ev_l70.omp_outlined.omp_outlined, ptr [[TMP0]], ptr [[OMP_CGROUP_MEM_ALLOC_ADDR]], ptr [[OMP_NULL_ALLOCATOR_ADDR]], ptr [[OMP_DEFAULT_MEM_ALLOC_ADDR]], ptr [[OMP_LARGE_CAP_MEM_ALLOC_ADDR]], ptr [[OMP_CONST_MEM_ALLOC_ADDR]], ptr [[OMP_HIGH_BW_MEM_ALLOC_ADDR]], ptr [[OMP_LOW_LAT_MEM_ALLOC_ADDR]], ptr [[OMP_PTEAM_MEM_ALLOC_ADDR]], ptr [[OMP_THREAD_MEM_ALLOC_ADDR]], i64 [[TMP3]])951// CHECK4-NEXT: ret void952//953//954// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIdEC1Ev_l70.omp_outlined.omp_outlined955// CHECK4-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_CGROUP_MEM_ALLOC:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_NULL_ALLOCATOR:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_DEFAULT_MEM_ALLOC:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_LARGE_CAP_MEM_ALLOC:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_CONST_MEM_ALLOC:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_HIGH_BW_MEM_ALLOC:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_LOW_LAT_MEM_ALLOC:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_PTEAM_MEM_ALLOC:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_THREAD_MEM_ALLOC:%.*]], i64 noundef [[A:%.*]]) #[[ATTR8]] personality ptr @__gxx_personality_v0 {956// CHECK4-NEXT: entry:957// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8958// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8959// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8960// CHECK4-NEXT: [[OMP_CGROUP_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8961// CHECK4-NEXT: [[OMP_NULL_ALLOCATOR_ADDR:%.*]] = alloca ptr, align 8962// CHECK4-NEXT: [[OMP_DEFAULT_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8963// CHECK4-NEXT: [[OMP_LARGE_CAP_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8964// CHECK4-NEXT: [[OMP_CONST_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8965// CHECK4-NEXT: [[OMP_HIGH_BW_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8966// CHECK4-NEXT: [[OMP_LOW_LAT_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8967// CHECK4-NEXT: [[OMP_PTEAM_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8968// CHECK4-NEXT: [[OMP_THREAD_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8969// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8970// CHECK4-NEXT: [[TMP:%.*]] = alloca ptr, align 8971// CHECK4-NEXT: [[A1:%.*]] = alloca double, align 8972// CHECK4-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8973// CHECK4-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8974// CHECK4-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8975// CHECK4-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8976// CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8977// CHECK4-NEXT: store ptr [[OMP_CGROUP_MEM_ALLOC]], ptr [[OMP_CGROUP_MEM_ALLOC_ADDR]], align 8978// CHECK4-NEXT: store ptr [[OMP_NULL_ALLOCATOR]], ptr [[OMP_NULL_ALLOCATOR_ADDR]], align 8979// CHECK4-NEXT: store ptr [[OMP_DEFAULT_MEM_ALLOC]], ptr [[OMP_DEFAULT_MEM_ALLOC_ADDR]], align 8980// CHECK4-NEXT: store ptr [[OMP_LARGE_CAP_MEM_ALLOC]], ptr [[OMP_LARGE_CAP_MEM_ALLOC_ADDR]], align 8981// CHECK4-NEXT: store ptr [[OMP_CONST_MEM_ALLOC]], ptr [[OMP_CONST_MEM_ALLOC_ADDR]], align 8982// CHECK4-NEXT: store ptr [[OMP_HIGH_BW_MEM_ALLOC]], ptr [[OMP_HIGH_BW_MEM_ALLOC_ADDR]], align 8983// CHECK4-NEXT: store ptr [[OMP_LOW_LAT_MEM_ALLOC]], ptr [[OMP_LOW_LAT_MEM_ALLOC_ADDR]], align 8984// CHECK4-NEXT: store ptr [[OMP_PTEAM_MEM_ALLOC]], ptr [[OMP_PTEAM_MEM_ALLOC_ADDR]], align 8985// CHECK4-NEXT: store ptr [[OMP_THREAD_MEM_ALLOC]], ptr [[OMP_THREAD_MEM_ALLOC_ADDR]], align 8986// CHECK4-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8987// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8988// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[OMP_CGROUP_MEM_ALLOC_ADDR]], align 8989// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[OMP_NULL_ALLOCATOR_ADDR]], align 8990// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[OMP_DEFAULT_MEM_ALLOC_ADDR]], align 8991// CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[OMP_LARGE_CAP_MEM_ALLOC_ADDR]], align 8992// CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[OMP_CONST_MEM_ALLOC_ADDR]], align 8993// CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr [[OMP_HIGH_BW_MEM_ALLOC_ADDR]], align 8994// CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[OMP_LOW_LAT_MEM_ALLOC_ADDR]], align 8995// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[OMP_PTEAM_MEM_ALLOC_ADDR]], align 8996// CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[OMP_THREAD_MEM_ALLOC_ADDR]], align 8997// CHECK4-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8998// CHECK4-NEXT: store ptr [[A1]], ptr [[_TMP2]], align 8999// CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 01000// CHECK4-NEXT: store ptr [[TMP0]], ptr [[TMP10]], align 81001// CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 11002// CHECK4-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 81003// CHECK4-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 81004// CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 21005// CHECK4-NEXT: store ptr [[TMP1]], ptr [[TMP13]], align 81006// CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 31007// CHECK4-NEXT: store ptr [[TMP2]], ptr [[TMP14]], align 81008// CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 41009// CHECK4-NEXT: store ptr [[TMP3]], ptr [[TMP15]], align 81010// CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 51011// CHECK4-NEXT: store ptr [[TMP4]], ptr [[TMP16]], align 81012// CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 61013// CHECK4-NEXT: store ptr [[TMP5]], ptr [[TMP17]], align 81014// CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 71015// CHECK4-NEXT: store ptr [[TMP6]], ptr [[TMP18]], align 81016// CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 81017// CHECK4-NEXT: store ptr [[TMP7]], ptr [[TMP19]], align 81018// CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 91019// CHECK4-NEXT: store ptr [[TMP8]], ptr [[TMP20]], align 81020// CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 101021// CHECK4-NEXT: store ptr [[TMP9]], ptr [[TMP21]], align 81022// CHECK4-NEXT: invoke void @_ZZN3SSTIdEC1EvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(88) [[REF_TMP]])1023// CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]]1024// CHECK4: invoke.cont:1025// CHECK4-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81026// CHECK4-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 41027// CHECK4-NEXT: call void @__kmpc_barrier(ptr @[[GLOB1]], i32 [[TMP23]])1028// CHECK4-NEXT: ret void1029// CHECK4: terminate.lpad:1030// CHECK4-NEXT: [[TMP24:%.*]] = landingpad { ptr, i32 }1031// CHECK4-NEXT: catch ptr null1032// CHECK4-NEXT: [[TMP25:%.*]] = extractvalue { ptr, i32 } [[TMP24]], 01033// CHECK4-NEXT: call void @__clang_call_terminate(ptr [[TMP25]]) #[[ATTR10]]1034// CHECK4-NEXT: unreachable1035//1036//1037// CHECK4-LABEL: define {{[^@]+}}@_ZZN3SSTIdEC1EvENKUlvE_clEv1038// CHECK4-SAME: (ptr noundef nonnull align 8 dereferenceable(88) [[THIS:%.*]]) #[[ATTR1]] align 2 {1039// CHECK4-NEXT: entry:1040// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81041// CHECK4-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 81042// CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81043// CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81044// CHECK4-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON:%.*]], ptr [[THIS1]], i32 0, i32 01045// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 81046// CHECK4-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 01047// CHECK4-NEXT: store ptr [[TMP1]], ptr [[TMP2]], align 81048// CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 11049// CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 11050// CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 81051// CHECK4-NEXT: store ptr [[TMP5]], ptr [[TMP3]], align 81052// CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 21053// CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 21054// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 81055// CHECK4-NEXT: store ptr [[TMP8]], ptr [[TMP6]], align 81056// CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 31057// CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 31058// CHECK4-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 81059// CHECK4-NEXT: store ptr [[TMP11]], ptr [[TMP9]], align 81060// CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 41061// CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 41062// CHECK4-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 81063// CHECK4-NEXT: store ptr [[TMP14]], ptr [[TMP12]], align 81064// CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 51065// CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 51066// CHECK4-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 81067// CHECK4-NEXT: store ptr [[TMP17]], ptr [[TMP15]], align 81068// CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 61069// CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 61070// CHECK4-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 81071// CHECK4-NEXT: store ptr [[TMP20]], ptr [[TMP18]], align 81072// CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 71073// CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 71074// CHECK4-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP22]], align 81075// CHECK4-NEXT: store ptr [[TMP23]], ptr [[TMP21]], align 81076// CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 81077// CHECK4-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 81078// CHECK4-NEXT: [[TMP26:%.*]] = load ptr, ptr [[TMP25]], align 81079// CHECK4-NEXT: store ptr [[TMP26]], ptr [[TMP24]], align 81080// CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 91081// CHECK4-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 91082// CHECK4-NEXT: [[TMP29:%.*]] = load ptr, ptr [[TMP28]], align 81083// CHECK4-NEXT: store ptr [[TMP29]], ptr [[TMP27]], align 81084// CHECK4-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 101085// CHECK4-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 101086// CHECK4-NEXT: [[TMP32:%.*]] = load ptr, ptr [[TMP31]], align 81087// CHECK4-NEXT: store ptr [[TMP32]], ptr [[TMP30]], align 81088// CHECK4-NEXT: call void @_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(88) [[REF_TMP]])1089// CHECK4-NEXT: ret void1090//1091//1092// CHECK4-LABEL: define {{[^@]+}}@_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv1093// CHECK4-SAME: (ptr noundef nonnull align 8 dereferenceable(88) [[THIS:%.*]]) #[[ATTR2]] align 2 {1094// CHECK4-NEXT: entry:1095// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81096// CHECK4-NEXT: [[C:%.*]] = alloca i32, align 41097// CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i64, align 81098// CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81099// CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81100// CHECK4-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0:%.*]], ptr [[THIS1]], i32 0, i32 01101// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 81102// CHECK4-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 11103// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 81104// CHECK4-NEXT: [[TMP4:%.*]] = load double, ptr [[TMP3]], align 81105// CHECK4-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+001106// CHECK4-NEXT: store double [[INC]], ptr [[TMP3]], align 81107// CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 21108// CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 81109// CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 11110// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 81111// CHECK4-NEXT: [[TMP9:%.*]] = load double, ptr [[TMP8]], align 81112// CHECK4-NEXT: store double [[TMP9]], ptr [[A_CASTED]], align 81113// CHECK4-NEXT: [[TMP10:%.*]] = load i64, ptr [[A_CASTED]], align 81114// CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 31115// CHECK4-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 81116// CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 41117// CHECK4-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 81118// CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 51119// CHECK4-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 81120// CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 61121// CHECK4-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 81122// CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 71123// CHECK4-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 81124// CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 81125// CHECK4-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP21]], align 81126// CHECK4-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 91127// CHECK4-NEXT: [[TMP24:%.*]] = load ptr, ptr [[TMP23]], align 81128// CHECK4-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 101129// CHECK4-NEXT: [[TMP26:%.*]] = load ptr, ptr [[TMP25]], align 81130// CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 11, ptr @_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv.omp_outlined, ptr [[TMP1]], ptr [[TMP6]], i64 [[TMP10]], ptr [[TMP12]], ptr [[TMP14]], ptr [[TMP16]], ptr [[TMP18]], ptr [[TMP20]], ptr [[TMP22]], ptr [[TMP24]], ptr [[TMP26]])1131// CHECK4-NEXT: ret void1132//1133//1134// CHECK4-LABEL: define {{[^@]+}}@_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv.omp_outlined1135// CHECK4-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_CGROUP_MEM_ALLOC:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_NULL_ALLOCATOR:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_DEFAULT_MEM_ALLOC:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_LARGE_CAP_MEM_ALLOC:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_CONST_MEM_ALLOC:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_HIGH_BW_MEM_ALLOC:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_LOW_LAT_MEM_ALLOC:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_PTEAM_MEM_ALLOC:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_THREAD_MEM_ALLOC:%.*]]) #[[ATTR8]] {1136// CHECK4-NEXT: entry:1137// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81138// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81139// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81140// CHECK4-NEXT: [[OMP_CGROUP_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 81141// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i64, align 81142// CHECK4-NEXT: [[OMP_NULL_ALLOCATOR_ADDR:%.*]] = alloca ptr, align 81143// CHECK4-NEXT: [[OMP_DEFAULT_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 81144// CHECK4-NEXT: [[OMP_LARGE_CAP_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 81145// CHECK4-NEXT: [[OMP_CONST_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 81146// CHECK4-NEXT: [[OMP_HIGH_BW_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 81147// CHECK4-NEXT: [[OMP_LOW_LAT_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 81148// CHECK4-NEXT: [[OMP_PTEAM_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 81149// CHECK4-NEXT: [[OMP_THREAD_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 81150// CHECK4-NEXT: [[TMP:%.*]] = alloca ptr, align 81151// CHECK4-NEXT: [[_TMP1:%.*]] = alloca ptr, align 81152// CHECK4-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81153// CHECK4-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81154// CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81155// CHECK4-NEXT: store ptr [[OMP_CGROUP_MEM_ALLOC]], ptr [[OMP_CGROUP_MEM_ALLOC_ADDR]], align 81156// CHECK4-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 81157// CHECK4-NEXT: store ptr [[OMP_NULL_ALLOCATOR]], ptr [[OMP_NULL_ALLOCATOR_ADDR]], align 81158// CHECK4-NEXT: store ptr [[OMP_DEFAULT_MEM_ALLOC]], ptr [[OMP_DEFAULT_MEM_ALLOC_ADDR]], align 81159// CHECK4-NEXT: store ptr [[OMP_LARGE_CAP_MEM_ALLOC]], ptr [[OMP_LARGE_CAP_MEM_ALLOC_ADDR]], align 81160// CHECK4-NEXT: store ptr [[OMP_CONST_MEM_ALLOC]], ptr [[OMP_CONST_MEM_ALLOC_ADDR]], align 81161// CHECK4-NEXT: store ptr [[OMP_HIGH_BW_MEM_ALLOC]], ptr [[OMP_HIGH_BW_MEM_ALLOC_ADDR]], align 81162// CHECK4-NEXT: store ptr [[OMP_LOW_LAT_MEM_ALLOC]], ptr [[OMP_LOW_LAT_MEM_ALLOC_ADDR]], align 81163// CHECK4-NEXT: store ptr [[OMP_PTEAM_MEM_ALLOC]], ptr [[OMP_PTEAM_MEM_ALLOC_ADDR]], align 81164// CHECK4-NEXT: store ptr [[OMP_THREAD_MEM_ALLOC]], ptr [[OMP_THREAD_MEM_ALLOC_ADDR]], align 81165// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81166// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[OMP_CGROUP_MEM_ALLOC_ADDR]], align 81167// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[OMP_NULL_ALLOCATOR_ADDR]], align 81168// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[OMP_DEFAULT_MEM_ALLOC_ADDR]], align 81169// CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[OMP_LARGE_CAP_MEM_ALLOC_ADDR]], align 81170// CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[OMP_CONST_MEM_ALLOC_ADDR]], align 81171// CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr [[OMP_HIGH_BW_MEM_ALLOC_ADDR]], align 81172// CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[OMP_LOW_LAT_MEM_ALLOC_ADDR]], align 81173// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[OMP_PTEAM_MEM_ALLOC_ADDR]], align 81174// CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[OMP_THREAD_MEM_ALLOC_ADDR]], align 81175// CHECK4-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 81176// CHECK4-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81177// CHECK4-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 41178// CHECK4-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 81179// CHECK4-NEXT: [[DOTA__VOID_ADDR:%.*]] = call ptr @__kmpc_alloc(i32 [[TMP11]], i64 8, ptr [[TMP12]])1180// CHECK4-NEXT: store ptr [[DOTA__VOID_ADDR]], ptr [[_TMP1]], align 81181// CHECK4-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP1]], align 81182// CHECK4-NEXT: [[TMP14:%.*]] = load double, ptr [[TMP13]], align 81183// CHECK4-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+001184// CHECK4-NEXT: store double [[INC]], ptr [[TMP13]], align 81185// CHECK4-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP1]], align 81186// CHECK4-NEXT: call void @__kmpc_free(i32 [[TMP11]], ptr [[DOTA__VOID_ADDR]], ptr [[TMP15]])1187// CHECK4-NEXT: call void @__kmpc_barrier(ptr @[[GLOB1]], i32 [[TMP11]])1188// CHECK4-NEXT: ret void1189//1190//1191// CHECK4-LABEL: define {{[^@]+}}@_ZN2SSC2ERi1192// CHECK4-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 personality ptr @__gxx_personality_v0 {1193// CHECK4-NEXT: entry:1194// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81195// CHECK4-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 81196// CHECK4-NEXT: [[A2:%.*]] = alloca i32, align 41197// CHECK4-NEXT: [[TMP:%.*]] = alloca ptr, align 81198// CHECK4-NEXT: [[C3:%.*]] = alloca i32, align 41199// CHECK4-NEXT: [[_TMP4:%.*]] = alloca ptr, align 81200// CHECK4-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_1:%.*]], align 81201// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])1202// CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81203// CHECK4-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 81204// CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81205// CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 11206// CHECK4-NEXT: store i32 0, ptr [[A]], align 41207// CHECK4-NEXT: [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 21208// CHECK4-NEXT: [[BF_LOAD:%.*]] = load i8, ptr [[B]], align 81209// CHECK4-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -161210// CHECK4-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 01211// CHECK4-NEXT: store i8 [[BF_SET]], ptr [[B]], align 81212// CHECK4-NEXT: [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 31213// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[D_ADDR]], align 81214// CHECK4-NEXT: store ptr [[TMP1]], ptr [[C]], align 81215// CHECK4-NEXT: store ptr [[A2]], ptr [[TMP]], align 81216// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr @omp_default_mem_alloc, align 81217// CHECK4-NEXT: [[DOTB__VOID_ADDR:%.*]] = call ptr @__kmpc_alloc(i32 [[TMP0]], i64 4, ptr [[TMP2]])1218// CHECK4-NEXT: store ptr [[C3]], ptr [[_TMP4]], align 81219// CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 01220// CHECK4-NEXT: store ptr [[THIS1]], ptr [[TMP3]], align 81221// CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 11222// CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 81223// CHECK4-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 81224// CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 21225// CHECK4-NEXT: store ptr [[DOTB__VOID_ADDR]], ptr [[TMP6]], align 81226// CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 31227// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP4]], align 81228// CHECK4-NEXT: store ptr [[TMP8]], ptr [[TMP7]], align 81229// CHECK4-NEXT: invoke void @_ZZN2SSC1ERiENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(32) [[REF_TMP]])1230// CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]]1231// CHECK4: invoke.cont:1232// CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr @omp_default_mem_alloc, align 81233// CHECK4-NEXT: call void @__kmpc_free(i32 [[TMP0]], ptr [[DOTB__VOID_ADDR]], ptr [[TMP9]])1234// CHECK4-NEXT: ret void1235// CHECK4: terminate.lpad:1236// CHECK4-NEXT: [[TMP10:%.*]] = landingpad { ptr, i32 }1237// CHECK4-NEXT: catch ptr null1238// CHECK4-NEXT: [[TMP11:%.*]] = extractvalue { ptr, i32 } [[TMP10]], 01239// CHECK4-NEXT: call void @__clang_call_terminate(ptr [[TMP11]]) #[[ATTR10]]1240// CHECK4-NEXT: unreachable1241//1242//1243// CHECK4-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv1244// CHECK4-SAME: (ptr noundef nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR2]] align 2 {1245// CHECK4-NEXT: entry:1246// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81247// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])1248// CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81249// CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81250// CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1:%.*]], ptr [[THIS1]], i32 0, i32 01251// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 81252// CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 11253// CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 81254// CHECK4-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 41255// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 11256// CHECK4-NEXT: store i32 [[INC]], ptr [[TMP4]], align 41257// CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 21258// CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 81259// CHECK4-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 41260// CHECK4-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP8]], -11261// CHECK4-NEXT: store i32 [[DEC]], ptr [[TMP7]], align 41262// CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 31263// CHECK4-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 81264// CHECK4-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 41265// CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP11]], 11266// CHECK4-NEXT: store i32 [[DIV]], ptr [[TMP10]], align 41267// CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 21268// CHECK4-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP12]], align 81269// CHECK4-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 41270// CHECK4-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP14]])1271// CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 11272// CHECK4-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 81273// CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 21274// CHECK4-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 81275// CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 31276// CHECK4-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 81277// CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined, ptr [[TMP2]], ptr [[TMP16]], ptr [[TMP18]], ptr [[TMP20]])1278// CHECK4-NEXT: ret void1279//1280//1281// CHECK4-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined1282// CHECK4-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR8]] {1283// CHECK4-NEXT: entry:1284// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81285// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81286// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81287// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 81288// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 81289// CHECK4-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 81290// CHECK4-NEXT: [[TMP:%.*]] = alloca ptr, align 81291// CHECK4-NEXT: [[_TMP1:%.*]] = alloca ptr, align 81292// CHECK4-NEXT: [[E:%.*]] = alloca ptr, align 81293// CHECK4-NEXT: [[_TMP3:%.*]] = alloca ptr, align 81294// CHECK4-NEXT: [[_TMP4:%.*]] = alloca ptr, align 81295// CHECK4-NEXT: [[_TMP5:%.*]] = alloca ptr, align 81296// CHECK4-NEXT: [[A6:%.*]] = alloca i32, align 41297// CHECK4-NEXT: [[_TMP7:%.*]] = alloca ptr, align 81298// CHECK4-NEXT: [[B8:%.*]] = alloca i32, align 41299// CHECK4-NEXT: [[C9:%.*]] = alloca i32, align 41300// CHECK4-NEXT: [[_TMP10:%.*]] = alloca ptr, align 81301// CHECK4-NEXT: [[E11:%.*]] = alloca i32, align 41302// CHECK4-NEXT: [[_TMP12:%.*]] = alloca ptr, align 81303// CHECK4-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 81304// CHECK4-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81305// CHECK4-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81306// CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81307// CHECK4-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 81308// CHECK4-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 81309// CHECK4-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 81310// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81311// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 81312// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 81313// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 81314// CHECK4-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 81315// CHECK4-NEXT: store ptr [[TMP3]], ptr [[_TMP1]], align 81316// CHECK4-NEXT: [[E2:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 01317// CHECK4-NEXT: store ptr [[E2]], ptr [[E]], align 81318// CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 81319// CHECK4-NEXT: store ptr [[TMP4]], ptr [[_TMP3]], align 81320// CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[E]], align 81321// CHECK4-NEXT: store ptr [[TMP5]], ptr [[_TMP4]], align 81322// CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 81323// CHECK4-NEXT: store ptr [[TMP6]], ptr [[_TMP5]], align 81324// CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP3]], align 81325// CHECK4-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 41326// CHECK4-NEXT: store i32 [[TMP8]], ptr [[A6]], align 41327// CHECK4-NEXT: store ptr [[A6]], ptr [[_TMP7]], align 81328// CHECK4-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP2]], align 41329// CHECK4-NEXT: store i32 [[TMP9]], ptr [[B8]], align 41330// CHECK4-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP5]], align 81331// CHECK4-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 41332// CHECK4-NEXT: store i32 [[TMP11]], ptr [[C9]], align 41333// CHECK4-NEXT: store ptr [[C9]], ptr [[_TMP10]], align 81334// CHECK4-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP4]], align 81335// CHECK4-NEXT: store i32 0, ptr [[E11]], align 41336// CHECK4-NEXT: store ptr [[E11]], ptr [[_TMP12]], align 81337// CHECK4-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP7]], align 81338// CHECK4-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 41339// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 11340// CHECK4-NEXT: store i32 [[INC]], ptr [[TMP13]], align 41341// CHECK4-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP12]], align 81342// CHECK4-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 41343// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 11344// CHECK4-NEXT: store i32 [[ADD]], ptr [[TMP15]], align 41345// CHECK4-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP10]], align 81346// CHECK4-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 41347// CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP18]], 11348// CHECK4-NEXT: store i32 [[DIV]], ptr [[TMP17]], align 41349// CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 01350// CHECK4-NEXT: store ptr [[E11]], ptr [[TMP19]], align 81351// CHECK4-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81352// CHECK4-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 41353// CHECK4-NEXT: [[TMP22:%.*]] = call i32 @__kmpc_reduce(ptr @[[GLOB3:[0-9]+]], i32 [[TMP21]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var)1354// CHECK4-NEXT: switch i32 [[TMP22]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [1355// CHECK4-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]]1356// CHECK4-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]]1357// CHECK4-NEXT: ]1358// CHECK4: .omp.reduction.case1:1359// CHECK4-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP12]], align 41360// CHECK4-NEXT: [[TMP24:%.*]] = load i32, ptr [[E11]], align 41361// CHECK4-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP23]], [[TMP24]]1362// CHECK4-NEXT: store i32 [[ADD13]], ptr [[TMP12]], align 41363// CHECK4-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB3]], i32 [[TMP21]], ptr @.gomp_critical_user_.reduction.var)1364// CHECK4-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]1365// CHECK4: .omp.reduction.case2:1366// CHECK4-NEXT: [[TMP25:%.*]] = load i32, ptr [[E11]], align 41367// CHECK4-NEXT: [[TMP26:%.*]] = atomicrmw add ptr [[TMP12]], i32 [[TMP25]] monotonic, align 41368// CHECK4-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB3]], i32 [[TMP21]], ptr @.gomp_critical_user_.reduction.var)1369// CHECK4-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]1370// CHECK4: .omp.reduction.default:1371// CHECK4-NEXT: call void @__kmpc_barrier(ptr @[[GLOB1]], i32 [[TMP21]])1372// CHECK4-NEXT: ret void1373//1374//1375// CHECK4-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined.omp.reduction.reduction_func1376// CHECK4-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR9:[0-9]+]] {1377// CHECK4-NEXT: entry:1378// CHECK4-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 81379// CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 81380// CHECK4-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 81381// CHECK4-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 81382// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 81383// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 81384// CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 01385// CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 81386// CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 01387// CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 81388// CHECK4-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 41389// CHECK4-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP5]], align 41390// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]]1391// CHECK4-NEXT: store i32 [[ADD]], ptr [[TMP7]], align 41392// CHECK4-NEXT: ret void1393//1394//1395// CHECK4-LABEL: define {{[^@]+}}@_ZN9TestClassC2ERKS_1396// CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {1397// CHECK4-NEXT: entry:1398// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81399// CHECK4-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 81400// CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81401// CHECK4-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 81402// CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81403// CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[CLASS_TESTCLASS:%.*]], ptr [[THIS1]], i32 0, i32 01404// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 81405// CHECK4-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[CLASS_TESTCLASS]], ptr [[TMP0]], i32 0, i32 01406// CHECK4-NEXT: [[TMP1:%.*]] = load i32, ptr [[A2]], align 41407// CHECK4-NEXT: store i32 [[TMP1]], ptr [[A]], align 41408// CHECK4-NEXT: ret void1409//1410//1411// CHECK4-LABEL: define {{[^@]+}}@_Z15parallel_singlev1412// CHECK4-SAME: () #[[ATTR2]] {1413// CHECK4-NEXT: entry:1414// CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @_Z15parallel_singlev.omp_outlined)1415// CHECK4-NEXT: ret void1416//1417//1418// CHECK4-LABEL: define {{[^@]+}}@_Z15parallel_singlev.omp_outlined1419// CHECK4-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR8]] personality ptr @__gxx_personality_v0 {1420// CHECK4-NEXT: entry:1421// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81422// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81423// CHECK4-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81424// CHECK4-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81425// CHECK4-NEXT: invoke void @_Z3foov()1426// CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]]1427// CHECK4: invoke.cont:1428// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81429// CHECK4-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 41430// CHECK4-NEXT: call void @__kmpc_barrier(ptr @[[GLOB1]], i32 [[TMP1]])1431// CHECK4-NEXT: ret void1432// CHECK4: terminate.lpad:1433// CHECK4-NEXT: [[TMP2:%.*]] = landingpad { ptr, i32 }1434// CHECK4-NEXT: catch ptr null1435// CHECK4-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP2]], 01436// CHECK4-NEXT: call void @__clang_call_terminate(ptr [[TMP3]]) #[[ATTR10]]1437// CHECK4-NEXT: unreachable1438//1439//1440// CHECK4-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_scope_codegen.cpp1441// CHECK4-SAME: () #[[ATTR0]] {1442// CHECK4-NEXT: entry:1443// CHECK4-NEXT: call void @__cxx_global_var_init()1444// CHECK4-NEXT: call void @__cxx_global_var_init.1()1445// CHECK4-NEXT: ret void1446//1447//1448// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init1449// CHECK5-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" !dbg [[DBG6:![0-9]+]] {1450// CHECK5-NEXT: entry:1451// CHECK5-NEXT: call void @_ZN9TestClassC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @tc), !dbg [[DBG9:![0-9]+]]1452// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN9TestClassD1Ev, ptr @tc, ptr @__dso_handle) #[[ATTR3:[0-9]+]], !dbg [[DBG12:![0-9]+]]1453// CHECK5-NEXT: ret void, !dbg [[DBG9]]1454//1455//1456// CHECK5-LABEL: define {{[^@]+}}@_ZN9TestClassC1Ev1457// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 !dbg [[DBG13:![0-9]+]] {1458// CHECK5-NEXT: entry:1459// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81460// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81461// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81462// CHECK5-NEXT: call void @_ZN9TestClassC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]), !dbg [[DBG14:![0-9]+]]1463// CHECK5-NEXT: ret void, !dbg [[DBG15:![0-9]+]]1464//1465//1466// CHECK5-LABEL: define {{[^@]+}}@_ZN9TestClassD1Ev1467// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] align 2 !dbg [[DBG16:![0-9]+]] {1468// CHECK5-NEXT: entry:1469// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81470// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81471// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81472// CHECK5-NEXT: call void @_ZN9TestClassD2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]], !dbg [[DBG17:![0-9]+]]1473// CHECK5-NEXT: ret void, !dbg [[DBG18:![0-9]+]]1474//1475//1476// CHECK5-LABEL: define {{[^@]+}}@_ZN9TestClassC2Ev1477// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG19:![0-9]+]] {1478// CHECK5-NEXT: entry:1479// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81480// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81481// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81482// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[CLASS_TESTCLASS:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG20:![0-9]+]]1483// CHECK5-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG20]]1484// CHECK5-NEXT: ret void, !dbg [[DBG21:![0-9]+]]1485//1486//1487// CHECK5-LABEL: define {{[^@]+}}@_ZN9TestClassD2Ev1488// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG22:![0-9]+]] {1489// CHECK5-NEXT: entry:1490// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81491// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81492// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81493// CHECK5-NEXT: ret void, !dbg [[DBG23:![0-9]+]]1494//1495//1496// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.11497// CHECK5-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" personality ptr @__gxx_personality_v0 !dbg [[DBG24:![0-9]+]] {1498// CHECK5-NEXT: entry:1499// CHECK5-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 81500// CHECK5-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 41501// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]], !dbg [[DBG25:![0-9]+]]1502// CHECK5: arrayctor.loop:1503// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ @tc2, [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[INVOKE_CONT:%.*]] ], !dbg [[DBG25]]1504// CHECK5-NEXT: invoke void @_ZN9TestClassC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])1505// CHECK5-NEXT: to label [[INVOKE_CONT]] unwind label [[LPAD:%.*]], !dbg [[DBG25]]1506// CHECK5: invoke.cont:1507// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[CLASS_TESTCLASS:%.*]], ptr [[ARRAYCTOR_CUR]], i64 1, !dbg [[DBG25]]1508// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], getelementptr inbounds ([[CLASS_TESTCLASS]], ptr @tc2, i64 2), !dbg [[DBG25]]1509// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]], !dbg [[DBG25]]1510// CHECK5: arrayctor.cont:1511// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG27:![0-9]+]]1512// CHECK5-NEXT: ret void, !dbg [[DBG27]]1513// CHECK5: lpad:1514// CHECK5-NEXT: [[TMP1:%.*]] = landingpad { ptr, i32 }1515// CHECK5-NEXT: cleanup, !dbg [[DBG28:![0-9]+]]1516// CHECK5-NEXT: [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0, !dbg [[DBG28]]1517// CHECK5-NEXT: store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG28]]1518// CHECK5-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1, !dbg [[DBG28]]1519// CHECK5-NEXT: store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG28]]1520// CHECK5-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @tc2, [[ARRAYCTOR_CUR]], !dbg [[DBG25]]1521// CHECK5-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG25]]1522// CHECK5: arraydestroy.body:1523// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[ARRAYCTOR_CUR]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG25]]1524// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG25]]1525// CHECK5-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG25]]1526// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @tc2, !dbg [[DBG25]]1527// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG25]]1528// CHECK5: arraydestroy.done1:1529// CHECK5-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG25]]1530// CHECK5: eh.resume:1531// CHECK5-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG25]]1532// CHECK5-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG25]]1533// CHECK5-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG25]]1534// CHECK5-NEXT: [[LPAD_VAL2:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG25]]1535// CHECK5-NEXT: resume { ptr, i32 } [[LPAD_VAL2]], !dbg [[DBG25]]1536//1537//1538// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor1539// CHECK5-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" !dbg [[DBG29:![0-9]+]] {1540// CHECK5-NEXT: entry:1541// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 81542// CHECK5-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 81543// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG30:![0-9]+]]1544// CHECK5: arraydestroy.body:1545// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[CLASS_TESTCLASS:%.*]], ptr @tc2, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG30]]1546// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG30]]1547// CHECK5-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG30]]1548// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @tc2, !dbg [[DBG30]]1549// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG30]]1550// CHECK5: arraydestroy.done1:1551// CHECK5-NEXT: ret void, !dbg [[DBG30]]1552//1553//1554// CHECK5-LABEL: define {{[^@]+}}@_Z3foov1555// CHECK5-SAME: () #[[ATTR1]] !dbg [[DBG31:![0-9]+]] {1556// CHECK5-NEXT: entry:1557// CHECK5-NEXT: call void @_Z8mayThrowv(), !dbg [[DBG32:![0-9]+]]1558// CHECK5-NEXT: ret void, !dbg [[DBG33:![0-9]+]]1559//1560//1561// CHECK5-LABEL: define {{[^@]+}}@main1562// CHECK5-SAME: () #[[ATTR5:[0-9]+]] personality ptr @__gxx_personality_v0 !dbg [[DBG34:![0-9]+]] {1563// CHECK5-NEXT: entry:1564// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 41565// CHECK5-NEXT: [[A:%.*]] = alloca i8, align 11566// CHECK5-NEXT: [[A2:%.*]] = alloca [2 x i8], align 11567// CHECK5-NEXT: [[C:%.*]] = alloca ptr, align 81568// CHECK5-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 81569// CHECK5-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 81570// CHECK5-NEXT: [[A1:%.*]] = alloca i8, align 11571// CHECK5-NEXT: [[C2:%.*]] = alloca [[CLASS_TESTCLASS:%.*]], align 41572// CHECK5-NEXT: [[TMP:%.*]] = alloca ptr, align 81573// CHECK5-NEXT: [[TC:%.*]] = alloca [[CLASS_TESTCLASS]], align 41574// CHECK5-NEXT: [[A24:%.*]] = alloca [2 x i8], align 11575// CHECK5-NEXT: [[TC2:%.*]] = alloca [2 x %class.TestClass], align 41576// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]), !dbg [[DBG35:![0-9]+]]1577// CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 41578// CHECK5-NEXT: store ptr @tc, ptr [[C]], align 8, !dbg [[DBG36:![0-9]+]]1579// CHECK5-NEXT: call void @_ZN3SSTIdEC1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[SST]]), !dbg [[DBG37:![0-9]+]]1580// CHECK5-NEXT: call void @_ZN2SSC1ERi(ptr noundef nonnull align 8 dereferenceable(24) [[SS]], ptr noundef nonnull align 4 dereferenceable(4) @tc), !dbg [[DBG38:![0-9]+]]1581// CHECK5-NEXT: store i8 2, ptr [[A]], align 1, !dbg [[DBG39:![0-9]+]]1582// CHECK5-NEXT: store i8 2, ptr [[A]], align 1, !dbg [[DBG40:![0-9]+]]1583// CHECK5-NEXT: call void @__kmpc_barrier(ptr @[[GLOB1:[0-9]+]], i32 [[TMP0]]), !dbg [[DBG41:![0-9]+]]1584// CHECK5-NEXT: [[TMP1:%.*]] = load i8, ptr [[A]], align 1, !dbg [[DBG42:![0-9]+]]1585// CHECK5-NEXT: store i8 [[TMP1]], ptr [[A1]], align 1, !dbg [[DBG42]]1586// CHECK5-NEXT: invoke void @_ZN9TestClassC1ERKS_(ptr noundef nonnull align 4 dereferenceable(4) [[C2]], ptr noundef nonnull align 4 dereferenceable(4) @tc)1587// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG43:![0-9]+]]1588// CHECK5: invoke.cont:1589// CHECK5-NEXT: store ptr [[C2]], ptr [[TMP]], align 8, !dbg [[DBG44:![0-9]+]]1590// CHECK5-NEXT: invoke void @_ZN9TestClassC1ERKS_(ptr noundef nonnull align 4 dereferenceable(4) [[TC]], ptr noundef nonnull align 4 dereferenceable(4) @tc)1591// CHECK5-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[TERMINATE_LPAD]], !dbg [[DBG45:![0-9]+]]1592// CHECK5: invoke.cont3:1593// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %class.TestClass], ptr [[TC2]], i32 0, i32 0, !dbg [[DBG46:![0-9]+]]1594// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAY_BEGIN]], i64 2, !dbg [[DBG46]]1595// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]], !dbg [[DBG46]]1596// CHECK5: arrayctor.loop:1597// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[INVOKE_CONT3]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[INVOKE_CONT5:%.*]] ], !dbg [[DBG46]]1598// CHECK5-NEXT: invoke void @_ZN9TestClassC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])1599// CHECK5-NEXT: to label [[INVOKE_CONT5]] unwind label [[TERMINATE_LPAD]], !dbg [[DBG46]]1600// CHECK5: invoke.cont5:1601// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYCTOR_CUR]], i64 1, !dbg [[DBG46]]1602// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]], !dbg [[DBG46]]1603// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]], !dbg [[DBG46]]1604// CHECK5: arrayctor.cont:1605// CHECK5-NEXT: invoke void @_Z3foov()1606// CHECK5-NEXT: to label [[INVOKE_CONT6:%.*]] unwind label [[TERMINATE_LPAD]], !dbg [[DBG47:![0-9]+]]1607// CHECK5: invoke.cont6:1608// CHECK5-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %class.TestClass], ptr [[TC2]], i32 0, i32 0, !dbg [[DBG47]]1609// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAY_BEGIN7]], i64 2, !dbg [[DBG47]]1610// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG47]]1611// CHECK5: arraydestroy.body:1612// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[INVOKE_CONT6]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG47]]1613// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG47]]1614// CHECK5-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG47]]1615// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]], !dbg [[DBG47]]1616// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG47]]1617// CHECK5: arraydestroy.done8:1618// CHECK5-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TC]]) #[[ATTR3]], !dbg [[DBG47]]1619// CHECK5-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[C2]]) #[[ATTR3]], !dbg [[DBG47]]1620// CHECK5-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4:[0-9]+]], i32 [[TMP0]]), !dbg [[DBG48:![0-9]+]]1621// CHECK5-NEXT: [[TMP3:%.*]] = load i8, ptr [[A]], align 1, !dbg [[DBG49:![0-9]+]]1622// CHECK5-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32, !dbg [[DBG49]]1623// CHECK5-NEXT: ret i32 [[CONV]], !dbg [[DBG50:![0-9]+]]1624// CHECK5: terminate.lpad:1625// CHECK5-NEXT: [[TMP4:%.*]] = landingpad { ptr, i32 }1626// CHECK5-NEXT: catch ptr null, !dbg [[DBG43]]1627// CHECK5-NEXT: [[TMP5:%.*]] = extractvalue { ptr, i32 } [[TMP4]], 0, !dbg [[DBG43]]1628// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP5]]) #[[ATTR10:[0-9]+]], !dbg [[DBG43]]1629// CHECK5-NEXT: unreachable, !dbg [[DBG43]]1630//1631//1632// CHECK5-LABEL: define {{[^@]+}}@_ZN3SSTIdEC1Ev1633// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG51:![0-9]+]] {1634// CHECK5-NEXT: entry:1635// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81636// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81637// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81638// CHECK5-NEXT: call void @_ZN3SSTIdEC2Ev(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]]), !dbg [[DBG52:![0-9]+]]1639// CHECK5-NEXT: ret void, !dbg [[DBG53:![0-9]+]]1640//1641//1642// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSC1ERi1643// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG54:![0-9]+]] {1644// CHECK5-NEXT: entry:1645// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81646// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 81647// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81648// CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 81649// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81650// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !dbg [[DBG55:![0-9]+]]1651// CHECK5-NEXT: call void @_ZN2SSC2ERi(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]]), !dbg [[DBG55]]1652// CHECK5-NEXT: ret void, !dbg [[DBG56:![0-9]+]]1653//1654//1655// CHECK5-LABEL: define {{[^@]+}}@_ZN9TestClassC1ERKS_1656// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG57:![0-9]+]] {1657// CHECK5-NEXT: entry:1658// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81659// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 81660// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81661// CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 81662// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81663// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG58:![0-9]+]]1664// CHECK5-NEXT: call void @_ZN9TestClassC2ERKS_(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]]), !dbg [[DBG58]]1665// CHECK5-NEXT: ret void, !dbg [[DBG59:![0-9]+]]1666//1667//1668// CHECK5-LABEL: define {{[^@]+}}@__clang_call_terminate1669// CHECK5-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR7:[0-9]+]] {1670// CHECK5-NEXT: [[TMP2:%.*]] = call ptr @__cxa_begin_catch(ptr [[TMP0]]) #[[ATTR3]]1671// CHECK5-NEXT: call void @_ZSt9terminatev() #[[ATTR10]]1672// CHECK5-NEXT: unreachable1673//1674//1675// CHECK5-LABEL: define {{[^@]+}}@_ZN3SSTIdEC2Ev1676// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG60:![0-9]+]] {1677// CHECK5-NEXT: entry:1678// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81679// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81680// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81681// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SST:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG61:![0-9]+]]1682// CHECK5-NEXT: store double 0.000000e+00, ptr [[A]], align 8, !dbg [[DBG61]]1683// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr @omp_cgroup_mem_alloc, align 8, !dbg [[DBG62:![0-9]+]]1684// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIdEC1Ev_l70(ptr [[THIS1]], ptr [[TMP0]]) #[[ATTR3]], !dbg [[DBG62]]1685// CHECK5-NEXT: ret void, !dbg [[DBG63:![0-9]+]]1686//1687//1688// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIdEC1Ev_l701689// CHECK5-SAME: (ptr noundef [[THIS:%.*]], ptr noundef [[OMP_CGROUP_MEM_ALLOC:%.*]]) #[[ATTR8:[0-9]+]] !dbg [[DBG64:![0-9]+]] {1690// CHECK5-NEXT: entry:1691// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81692// CHECK5-NEXT: [[OMP_CGROUP_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 81693// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81694// CHECK5-NEXT: store ptr [[OMP_CGROUP_MEM_ALLOC]], ptr [[OMP_CGROUP_MEM_ALLOC_ADDR]], align 81695// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !dbg [[DBG65:![0-9]+]]1696// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[OMP_CGROUP_MEM_ALLOC_ADDR]], align 8, !dbg [[DBG65]]1697// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB10:[0-9]+]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIdEC1Ev_l70.omp_outlined, ptr [[TMP0]], ptr [[TMP1]]), !dbg [[DBG65]]1698// CHECK5-NEXT: ret void, !dbg [[DBG66:![0-9]+]]1699//1700//1701// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIdEC1Ev_l70.omp_outlined1702// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], ptr noundef [[OMP_CGROUP_MEM_ALLOC:%.*]]) #[[ATTR8]] !dbg [[DBG67:![0-9]+]] {1703// CHECK5-NEXT: entry:1704// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81705// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81706// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81707// CHECK5-NEXT: [[OMP_CGROUP_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 81708// CHECK5-NEXT: [[A:%.*]] = alloca ptr, align 81709// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 81710// CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81711// CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81712// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81713// CHECK5-NEXT: store ptr [[OMP_CGROUP_MEM_ALLOC]], ptr [[OMP_CGROUP_MEM_ALLOC_ADDR]], align 81714// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !dbg [[DBG68:![0-9]+]]1715// CHECK5-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_SST:%.*]], ptr [[TMP0]], i32 0, i32 0, !dbg [[DBG69:![0-9]+]]1716// CHECK5-NEXT: store ptr [[A1]], ptr [[A]], align 8, !dbg [[DBG69]]1717// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A]], align 8, !dbg [[DBG69]]1718// CHECK5-NEXT: [[TMP2:%.*]] = load double, ptr [[TMP1]], align 8, !dbg [[DBG70:![0-9]+]]1719// CHECK5-NEXT: store double [[TMP2]], ptr [[A_CASTED]], align 8, !dbg [[DBG70]]1720// CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[A_CASTED]], align 8, !dbg [[DBG70]]1721// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB8:[0-9]+]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIdEC1Ev_l70.omp_outlined.omp_outlined, ptr [[TMP0]], ptr [[OMP_CGROUP_MEM_ALLOC_ADDR]], i64 [[TMP3]]), !dbg [[DBG70]]1722// CHECK5-NEXT: ret void, !dbg [[DBG71:![0-9]+]]1723//1724//1725// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIdEC1Ev_l70.omp_outlined.omp_outlined1726// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_CGROUP_MEM_ALLOC:%.*]], i64 noundef [[A:%.*]]) #[[ATTR8]] personality ptr @__gxx_personality_v0 !dbg [[DBG72:![0-9]+]] {1727// CHECK5-NEXT: entry:1728// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81729// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81730// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81731// CHECK5-NEXT: [[OMP_CGROUP_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 81732// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 81733// CHECK5-NEXT: [[TMP:%.*]] = alloca ptr, align 81734// CHECK5-NEXT: [[A1:%.*]] = alloca double, align 81735// CHECK5-NEXT: [[_TMP2:%.*]] = alloca ptr, align 81736// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 81737// CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81738// CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81739// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81740// CHECK5-NEXT: store ptr [[OMP_CGROUP_MEM_ALLOC]], ptr [[OMP_CGROUP_MEM_ALLOC_ADDR]], align 81741// CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 81742// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !dbg [[DBG73:![0-9]+]]1743// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[OMP_CGROUP_MEM_ALLOC_ADDR]], align 8, !dbg [[DBG73]]1744// CHECK5-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8, !dbg [[DBG73]]1745// CHECK5-NEXT: store ptr [[A1]], ptr [[_TMP2]], align 8, !dbg [[DBG74:![0-9]+]]1746// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0, !dbg [[DBG75:![0-9]+]]1747// CHECK5-NEXT: store ptr [[TMP0]], ptr [[TMP2]], align 8, !dbg [[DBG75]]1748// CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1, !dbg [[DBG75]]1749// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG76:![0-9]+]]1750// CHECK5-NEXT: store ptr [[TMP4]], ptr [[TMP3]], align 8, !dbg [[DBG75]]1751// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 2, !dbg [[DBG75]]1752// CHECK5-NEXT: store ptr [[TMP1]], ptr [[TMP5]], align 8, !dbg [[DBG75]]1753// CHECK5-NEXT: invoke void @_ZZN3SSTIdEC1EvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]])1754// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG75]]1755// CHECK5: invoke.cont:1756// CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG77:![0-9]+]]1757// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4, !dbg [[DBG77]]1758// CHECK5-NEXT: call void @__kmpc_barrier(ptr @[[GLOB6:[0-9]+]], i32 [[TMP7]]), !dbg [[DBG77]]1759// CHECK5-NEXT: ret void, !dbg [[DBG77]]1760// CHECK5: terminate.lpad:1761// CHECK5-NEXT: [[TMP8:%.*]] = landingpad { ptr, i32 }1762// CHECK5-NEXT: catch ptr null, !dbg [[DBG75]]1763// CHECK5-NEXT: [[TMP9:%.*]] = extractvalue { ptr, i32 } [[TMP8]], 0, !dbg [[DBG75]]1764// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP9]]) #[[ATTR10]], !dbg [[DBG75]]1765// CHECK5-NEXT: unreachable, !dbg [[DBG75]]1766//1767//1768// CHECK5-LABEL: define {{[^@]+}}@_ZZN3SSTIdEC1EvENKUlvE_clEv1769// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR1]] align 2 !dbg [[DBG78:![0-9]+]] {1770// CHECK5-NEXT: entry:1771// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81772// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 81773// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81774// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81775// CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON:%.*]], ptr [[THIS1]], i32 0, i32 01776// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 81777// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0, !dbg [[DBG79:![0-9]+]]1778// CHECK5-NEXT: store ptr [[TMP1]], ptr [[TMP2]], align 8, !dbg [[DBG79]]1779// CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1, !dbg [[DBG79]]1780// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG80:![0-9]+]]1781// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8, !dbg [[DBG80]]1782// CHECK5-NEXT: store ptr [[TMP5]], ptr [[TMP3]], align 8, !dbg [[DBG79]]1783// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2, !dbg [[DBG79]]1784// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 2, !dbg [[DBG80]]1785// CHECK5-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8, !dbg [[DBG80]]1786// CHECK5-NEXT: store ptr [[TMP8]], ptr [[TMP6]], align 8, !dbg [[DBG79]]1787// CHECK5-NEXT: call void @_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]), !dbg [[DBG79]]1788// CHECK5-NEXT: ret void, !dbg [[DBG81:![0-9]+]]1789//1790//1791// CHECK5-LABEL: define {{[^@]+}}@_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv1792// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2]] align 2 !dbg [[DBG84:![0-9]+]] {1793// CHECK5-NEXT: entry:1794// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81795// CHECK5-NEXT: [[C:%.*]] = alloca i32, align 41796// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 81797// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81798// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81799// CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0:%.*]], ptr [[THIS1]], i32 0, i32 01800// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 81801// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG85:![0-9]+]]1802// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8, !dbg [[DBG85]]1803// CHECK5-NEXT: [[TMP4:%.*]] = load double, ptr [[TMP3]], align 8, !dbg [[DBG86:![0-9]+]]1804// CHECK5-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+00, !dbg [[DBG86]]1805// CHECK5-NEXT: store double [[INC]], ptr [[TMP3]], align 8, !dbg [[DBG86]]1806// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 2, !dbg [[DBG87:![0-9]+]]1807// CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8, !dbg [[DBG87]]1808// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG88:![0-9]+]]1809// CHECK5-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8, !dbg [[DBG88]]1810// CHECK5-NEXT: [[TMP9:%.*]] = load double, ptr [[TMP8]], align 8, !dbg [[DBG89:![0-9]+]]1811// CHECK5-NEXT: store double [[TMP9]], ptr [[A_CASTED]], align 8, !dbg [[DBG89]]1812// CHECK5-NEXT: [[TMP10:%.*]] = load i64, ptr [[A_CASTED]], align 8, !dbg [[DBG89]]1813// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB14:[0-9]+]], i32 3, ptr @_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv.omp_outlined, ptr [[TMP1]], ptr [[TMP6]], i64 [[TMP10]]), !dbg [[DBG89]]1814// CHECK5-NEXT: ret void, !dbg [[DBG90:![0-9]+]]1815//1816//1817// CHECK5-LABEL: define {{[^@]+}}@_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv.omp_outlined1818// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_CGROUP_MEM_ALLOC:%.*]], i64 noundef [[A:%.*]]) #[[ATTR8]] !dbg [[DBG91:![0-9]+]] {1819// CHECK5-NEXT: entry:1820// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81821// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81822// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81823// CHECK5-NEXT: [[OMP_CGROUP_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 81824// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 81825// CHECK5-NEXT: [[TMP:%.*]] = alloca ptr, align 81826// CHECK5-NEXT: [[_TMP1:%.*]] = alloca ptr, align 81827// CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81828// CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81829// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81830// CHECK5-NEXT: store ptr [[OMP_CGROUP_MEM_ALLOC]], ptr [[OMP_CGROUP_MEM_ALLOC_ADDR]], align 81831// CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 81832// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !dbg [[DBG92:![0-9]+]]1833// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[OMP_CGROUP_MEM_ALLOC_ADDR]], align 8, !dbg [[DBG92]]1834// CHECK5-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8, !dbg [[DBG92]]1835// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG93:![0-9]+]]1836// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4, !dbg [[DBG93]]1837// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP1]], align 8, !dbg [[DBG94:![0-9]+]]1838// CHECK5-NEXT: [[DOTA__VOID_ADDR:%.*]] = call ptr @__kmpc_alloc(i32 [[TMP3]], i64 8, ptr [[TMP4]]), !dbg [[DBG93]]1839// CHECK5-NEXT: store ptr [[DOTA__VOID_ADDR]], ptr [[_TMP1]], align 8, !dbg [[DBG93]]1840// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG95:![0-9]+]]1841// CHECK5-NEXT: [[TMP6:%.*]] = load double, ptr [[TMP5]], align 8, !dbg [[DBG96:![0-9]+]]1842// CHECK5-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00, !dbg [[DBG96]]1843// CHECK5-NEXT: store double [[INC]], ptr [[TMP5]], align 8, !dbg [[DBG96]]1844// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP1]], align 8, !dbg [[DBG94]]1845// CHECK5-NEXT: call void @__kmpc_free(i32 [[TMP3]], ptr [[DOTA__VOID_ADDR]], ptr [[TMP7]]), !dbg [[DBG96]]1846// CHECK5-NEXT: call void @__kmpc_barrier(ptr @[[GLOB12:[0-9]+]], i32 [[TMP3]]), !dbg [[DBG97:![0-9]+]]1847// CHECK5-NEXT: ret void, !dbg [[DBG97]]1848//1849//1850// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSC2ERi1851// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2]] align 2 personality ptr @__gxx_personality_v0 !dbg [[DBG98:![0-9]+]] {1852// CHECK5-NEXT: entry:1853// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81854// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 81855// CHECK5-NEXT: [[A2:%.*]] = alloca i32, align 41856// CHECK5-NEXT: [[TMP:%.*]] = alloca ptr, align 81857// CHECK5-NEXT: [[C3:%.*]] = alloca i32, align 41858// CHECK5-NEXT: [[_TMP4:%.*]] = alloca ptr, align 81859// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_1:%.*]], align 81860// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB16:[0-9]+]]), !dbg [[DBG99:![0-9]+]]1861// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81862// CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 81863// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81864// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG100:![0-9]+]]1865// CHECK5-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG100]]1866// CHECK5-NEXT: [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2, !dbg [[DBG101:![0-9]+]]1867// CHECK5-NEXT: [[BF_LOAD:%.*]] = load i8, ptr [[B]], align 8, !dbg [[DBG101]]1868// CHECK5-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16, !dbg [[DBG101]]1869// CHECK5-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0, !dbg [[DBG101]]1870// CHECK5-NEXT: store i8 [[BF_SET]], ptr [[B]], align 8, !dbg [[DBG101]]1871// CHECK5-NEXT: [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 3, !dbg [[DBG102:![0-9]+]]1872// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !dbg [[DBG103:![0-9]+]]1873// CHECK5-NEXT: store ptr [[TMP1]], ptr [[C]], align 8, !dbg [[DBG102]]1874// CHECK5-NEXT: store ptr [[A2]], ptr [[TMP]], align 8, !dbg [[DBG104:![0-9]+]]1875// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr @omp_default_mem_alloc, align 8, !dbg [[DBG105:![0-9]+]]1876// CHECK5-NEXT: [[DOTB__VOID_ADDR:%.*]] = call ptr @__kmpc_alloc(i32 [[TMP0]], i64 4, ptr [[TMP2]]), !dbg [[DBG104]]1877// CHECK5-NEXT: store ptr [[C3]], ptr [[_TMP4]], align 8, !dbg [[DBG104]]1878// CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 0, !dbg [[DBG106:![0-9]+]]1879// CHECK5-NEXT: store ptr [[THIS1]], ptr [[TMP3]], align 8, !dbg [[DBG106]]1880// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 1, !dbg [[DBG106]]1881// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG107:![0-9]+]]1882// CHECK5-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 8, !dbg [[DBG106]]1883// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 2, !dbg [[DBG106]]1884// CHECK5-NEXT: store ptr [[DOTB__VOID_ADDR]], ptr [[TMP6]], align 8, !dbg [[DBG106]]1885// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 3, !dbg [[DBG106]]1886// CHECK5-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP4]], align 8, !dbg [[DBG107]]1887// CHECK5-NEXT: store ptr [[TMP8]], ptr [[TMP7]], align 8, !dbg [[DBG106]]1888// CHECK5-NEXT: invoke void @_ZZN2SSC1ERiENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(32) [[REF_TMP]])1889// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG106]]1890// CHECK5: invoke.cont:1891// CHECK5-NEXT: [[TMP9:%.*]] = load ptr, ptr @omp_default_mem_alloc, align 8, !dbg [[DBG105]]1892// CHECK5-NEXT: call void @__kmpc_free(i32 [[TMP0]], ptr [[DOTB__VOID_ADDR]], ptr [[TMP9]]), !dbg [[DBG106]]1893// CHECK5-NEXT: ret void, !dbg [[DBG108:![0-9]+]]1894// CHECK5: terminate.lpad:1895// CHECK5-NEXT: [[TMP10:%.*]] = landingpad { ptr, i32 }1896// CHECK5-NEXT: catch ptr null, !dbg [[DBG106]]1897// CHECK5-NEXT: [[TMP11:%.*]] = extractvalue { ptr, i32 } [[TMP10]], 0, !dbg [[DBG106]]1898// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP11]]) #[[ATTR10]], !dbg [[DBG106]]1899// CHECK5-NEXT: unreachable, !dbg [[DBG106]]1900//1901//1902// CHECK5-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv1903// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR2]] align 2 !dbg [[DBG109:![0-9]+]] {1904// CHECK5-NEXT: entry:1905// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81906// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB22:[0-9]+]]), !dbg [[DBG110:![0-9]+]]1907// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81908// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81909// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1:%.*]], ptr [[THIS1]], i32 0, i32 01910// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 81911// CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG111:![0-9]+]]1912// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8, !dbg [[DBG111]]1913// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4, !dbg [[DBG112:![0-9]+]]1914// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1, !dbg [[DBG112]]1915// CHECK5-NEXT: store i32 [[INC]], ptr [[TMP4]], align 4, !dbg [[DBG112]]1916// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 2, !dbg [[DBG113:![0-9]+]]1917// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8, !dbg [[DBG113]]1918// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4, !dbg [[DBG114:![0-9]+]]1919// CHECK5-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP8]], -1, !dbg [[DBG114]]1920// CHECK5-NEXT: store i32 [[DEC]], ptr [[TMP7]], align 4, !dbg [[DBG114]]1921// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 3, !dbg [[DBG115:![0-9]+]]1922// CHECK5-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8, !dbg [[DBG115]]1923// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4, !dbg [[DBG116:![0-9]+]]1924// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP11]], 1, !dbg [[DBG116]]1925// CHECK5-NEXT: store i32 [[DIV]], ptr [[TMP10]], align 4, !dbg [[DBG116]]1926// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 2, !dbg [[DBG117:![0-9]+]]1927// CHECK5-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP12]], align 8, !dbg [[DBG117]]1928// CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4, !dbg [[DBG117]]1929// CHECK5-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB22]], i32 [[TMP0]], i32 [[TMP14]]), !dbg [[DBG118:![0-9]+]]1930// CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG119:![0-9]+]]1931// CHECK5-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8, !dbg [[DBG119]]1932// CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 2, !dbg [[DBG120:![0-9]+]]1933// CHECK5-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8, !dbg [[DBG120]]1934// CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 3, !dbg [[DBG121:![0-9]+]]1935// CHECK5-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8, !dbg [[DBG121]]1936// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB24:[0-9]+]], i32 4, ptr @_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined, ptr [[TMP2]], ptr [[TMP16]], ptr [[TMP18]], ptr [[TMP20]]), !dbg [[DBG118]]1937// CHECK5-NEXT: ret void, !dbg [[DBG122:![0-9]+]]1938//1939//1940// CHECK5-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined1941// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR8]] !dbg [[DBG123:![0-9]+]] {1942// CHECK5-NEXT: entry:1943// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81944// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81945// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81946// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 81947// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 81948// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 81949// CHECK5-NEXT: [[TMP:%.*]] = alloca ptr, align 81950// CHECK5-NEXT: [[_TMP1:%.*]] = alloca ptr, align 81951// CHECK5-NEXT: [[E:%.*]] = alloca ptr, align 81952// CHECK5-NEXT: [[_TMP3:%.*]] = alloca ptr, align 81953// CHECK5-NEXT: [[_TMP4:%.*]] = alloca ptr, align 81954// CHECK5-NEXT: [[_TMP5:%.*]] = alloca ptr, align 81955// CHECK5-NEXT: [[A6:%.*]] = alloca i32, align 41956// CHECK5-NEXT: [[_TMP7:%.*]] = alloca ptr, align 81957// CHECK5-NEXT: [[B8:%.*]] = alloca i32, align 41958// CHECK5-NEXT: [[C9:%.*]] = alloca i32, align 41959// CHECK5-NEXT: [[_TMP10:%.*]] = alloca ptr, align 81960// CHECK5-NEXT: [[E11:%.*]] = alloca i32, align 41961// CHECK5-NEXT: [[_TMP12:%.*]] = alloca ptr, align 81962// CHECK5-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 81963// CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81964// CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81965// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81966// CHECK5-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 81967// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 81968// CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 81969// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !dbg [[DBG124:![0-9]+]]1970// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG124]]1971// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG124]]1972// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG124]]1973// CHECK5-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG124]]1974// CHECK5-NEXT: store ptr [[TMP3]], ptr [[_TMP1]], align 8, !dbg [[DBG124]]1975// CHECK5-NEXT: [[E2:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0, !dbg [[DBG125:![0-9]+]]1976// CHECK5-NEXT: store ptr [[E2]], ptr [[E]], align 8, !dbg [[DBG125]]1977// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG126:![0-9]+]]1978// CHECK5-NEXT: store ptr [[TMP4]], ptr [[_TMP3]], align 8, !dbg [[DBG127:![0-9]+]]1979// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[E]], align 8, !dbg [[DBG128:![0-9]+]]1980// CHECK5-NEXT: store ptr [[TMP5]], ptr [[_TMP4]], align 8, !dbg [[DBG127]]1981// CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG129:![0-9]+]]1982// CHECK5-NEXT: store ptr [[TMP6]], ptr [[_TMP5]], align 8, !dbg [[DBG127]]1983// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP3]], align 8, !dbg [[DBG130:![0-9]+]]1984// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4, !dbg [[DBG130]]1985// CHECK5-NEXT: store i32 [[TMP8]], ptr [[A6]], align 4, !dbg [[DBG130]]1986// CHECK5-NEXT: store ptr [[A6]], ptr [[_TMP7]], align 8, !dbg [[DBG127]]1987// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP2]], align 4, !dbg [[DBG131:![0-9]+]]1988// CHECK5-NEXT: store i32 [[TMP9]], ptr [[B8]], align 4, !dbg [[DBG131]]1989// CHECK5-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP5]], align 8, !dbg [[DBG132:![0-9]+]]1990// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4, !dbg [[DBG132]]1991// CHECK5-NEXT: store i32 [[TMP11]], ptr [[C9]], align 4, !dbg [[DBG132]]1992// CHECK5-NEXT: store ptr [[C9]], ptr [[_TMP10]], align 8, !dbg [[DBG127]]1993// CHECK5-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP4]], align 8, !dbg [[DBG125]]1994// CHECK5-NEXT: store i32 0, ptr [[E11]], align 4, !dbg [[DBG125]]1995// CHECK5-NEXT: store ptr [[E11]], ptr [[_TMP12]], align 8, !dbg [[DBG127]]1996// CHECK5-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP7]], align 8, !dbg [[DBG126]]1997// CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4, !dbg [[DBG133:![0-9]+]]1998// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1, !dbg [[DBG133]]1999// CHECK5-NEXT: store i32 [[INC]], ptr [[TMP13]], align 4, !dbg [[DBG133]]2000// CHECK5-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP12]], align 8, !dbg [[DBG128]]2001// CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4, !dbg [[DBG134:![0-9]+]]2002// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1, !dbg [[DBG134]]2003// CHECK5-NEXT: store i32 [[ADD]], ptr [[TMP15]], align 4, !dbg [[DBG134]]2004// CHECK5-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP10]], align 8, !dbg [[DBG129]]2005// CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4, !dbg [[DBG135:![0-9]+]]2006// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP18]], 1, !dbg [[DBG135]]2007// CHECK5-NEXT: store i32 [[DIV]], ptr [[TMP17]], align 4, !dbg [[DBG135]]2008// CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0, !dbg [[DBG133]]2009// CHECK5-NEXT: store ptr [[E11]], ptr [[TMP19]], align 8, !dbg [[DBG133]]2010// CHECK5-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG133]]2011// CHECK5-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4, !dbg [[DBG133]]2012// CHECK5-NEXT: [[TMP22:%.*]] = call i32 @__kmpc_reduce(ptr @[[GLOB18:[0-9]+]], i32 [[TMP21]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var), !dbg [[DBG133]]2013// CHECK5-NEXT: switch i32 [[TMP22]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [2014// CHECK5-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]]2015// CHECK5-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]]2016// CHECK5-NEXT: ], !dbg [[DBG133]]2017// CHECK5: .omp.reduction.case1:2018// CHECK5-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP12]], align 4, !dbg [[DBG125]]2019// CHECK5-NEXT: [[TMP24:%.*]] = load i32, ptr [[E11]], align 4, !dbg [[DBG125]]2020// CHECK5-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP23]], [[TMP24]], !dbg [[DBG136:![0-9]+]]2021// CHECK5-NEXT: store i32 [[ADD13]], ptr [[TMP12]], align 4, !dbg [[DBG136]]2022// CHECK5-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB18]], i32 [[TMP21]], ptr @.gomp_critical_user_.reduction.var), !dbg [[DBG133]]2023// CHECK5-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]], !dbg [[DBG133]]2024// CHECK5: .omp.reduction.case2:2025// CHECK5-NEXT: [[TMP25:%.*]] = load i32, ptr [[E11]], align 4, !dbg [[DBG125]]2026// CHECK5-NEXT: [[TMP26:%.*]] = atomicrmw add ptr [[TMP12]], i32 [[TMP25]] monotonic, align 4, !dbg [[DBG133]]2027// CHECK5-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB18]], i32 [[TMP21]], ptr @.gomp_critical_user_.reduction.var), !dbg [[DBG133]]2028// CHECK5-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]], !dbg [[DBG133]]2029// CHECK5: .omp.reduction.default:2030// CHECK5-NEXT: call void @__kmpc_barrier(ptr @[[GLOB20:[0-9]+]], i32 [[TMP21]]), !dbg [[DBG137:![0-9]+]]2031// CHECK5-NEXT: ret void, !dbg [[DBG137]]2032//2033//2034// CHECK5-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined.omp.reduction.reduction_func2035// CHECK5-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR9:[0-9]+]] !dbg [[DBG138:![0-9]+]] {2036// CHECK5-NEXT: entry:2037// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 82038// CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 82039// CHECK5-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 82040// CHECK5-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 82041// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG139:![0-9]+]]2042// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8, !dbg [[DBG139]]2043// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0, !dbg [[DBG139]]2044// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8, !dbg [[DBG139]]2045// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG139]]2046// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8, !dbg [[DBG139]]2047// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4, !dbg [[DBG140:![0-9]+]]2048// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG140]]2049// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]], !dbg [[DBG141:![0-9]+]]2050// CHECK5-NEXT: store i32 [[ADD]], ptr [[TMP7]], align 4, !dbg [[DBG141]]2051// CHECK5-NEXT: ret void, !dbg [[DBG140]]2052//2053//2054// CHECK5-LABEL: define {{[^@]+}}@_ZN9TestClassC2ERKS_2055// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG142:![0-9]+]] {2056// CHECK5-NEXT: entry:2057// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82058// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 82059// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82060// CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 82061// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82062// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[CLASS_TESTCLASS:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG143:![0-9]+]]2063// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG144:![0-9]+]]2064// CHECK5-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[CLASS_TESTCLASS]], ptr [[TMP0]], i32 0, i32 0, !dbg [[DBG145:![0-9]+]]2065// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[A2]], align 4, !dbg [[DBG145]]2066// CHECK5-NEXT: store i32 [[TMP1]], ptr [[A]], align 4, !dbg [[DBG143]]2067// CHECK5-NEXT: ret void, !dbg [[DBG146:![0-9]+]]2068//2069//2070// CHECK5-LABEL: define {{[^@]+}}@_Z15parallel_singlev2071// CHECK5-SAME: () #[[ATTR2]] !dbg [[DBG147:![0-9]+]] {2072// CHECK5-NEXT: entry:2073// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB28:[0-9]+]], i32 0, ptr @_Z15parallel_singlev.omp_outlined), !dbg [[DBG148:![0-9]+]]2074// CHECK5-NEXT: ret void, !dbg [[DBG149:![0-9]+]]2075//2076//2077// CHECK5-LABEL: define {{[^@]+}}@_Z15parallel_singlev.omp_outlined2078// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR8]] personality ptr @__gxx_personality_v0 !dbg [[DBG150:![0-9]+]] {2079// CHECK5-NEXT: entry:2080// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 82081// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 82082// CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 82083// CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 82084// CHECK5-NEXT: invoke void @_Z3foov()2085// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG151:![0-9]+]]2086// CHECK5: invoke.cont:2087// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG152:![0-9]+]]2088// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4, !dbg [[DBG152]]2089// CHECK5-NEXT: call void @__kmpc_barrier(ptr @[[GLOB26:[0-9]+]], i32 [[TMP1]]), !dbg [[DBG152]]2090// CHECK5-NEXT: ret void, !dbg [[DBG152]]2091// CHECK5: terminate.lpad:2092// CHECK5-NEXT: [[TMP2:%.*]] = landingpad { ptr, i32 }2093// CHECK5-NEXT: catch ptr null, !dbg [[DBG151]]2094// CHECK5-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP2]], 0, !dbg [[DBG151]]2095// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP3]]) #[[ATTR10]], !dbg [[DBG151]]2096// CHECK5-NEXT: unreachable, !dbg [[DBG151]]2097//2098//2099// CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_scope_codegen.cpp2100// CHECK5-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" !dbg [[DBG153:![0-9]+]] {2101// CHECK5-NEXT: entry:2102// CHECK5-NEXT: call void @__cxx_global_var_init(), !dbg [[DBG154:![0-9]+]]2103// CHECK5-NEXT: call void @__cxx_global_var_init.1(), !dbg [[DBG154]]2104// CHECK5-NEXT: ret void2105//2106//2107// CHECK6-LABEL: define {{[^@]+}}@_Z10array_funciPiP2St2108// CHECK6-SAME: (i32 noundef [[N:%.*]], ptr noundef [[A:%.*]], ptr noundef [[S:%.*]]) #[[ATTR0:[0-9]+]] {2109// CHECK6-NEXT: entry:2110// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 42111// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 82112// CHECK6-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 82113// CHECK6-NEXT: [[B:%.*]] = alloca i32, align 42114// CHECK6-NEXT: [[C:%.*]] = alloca i32, align 42115// CHECK6-NEXT: [[B1:%.*]] = alloca i32, align 42116// CHECK6-NEXT: [[A2:%.*]] = alloca ptr, align 82117// CHECK6-NEXT: [[S3:%.*]] = alloca ptr, align 82118// CHECK6-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 82119// CHECK6-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i32, align 42120// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 42121// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])2122// CHECK6-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 42123// CHECK6-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 82124// CHECK6-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 82125// CHECK6-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 42126// CHECK6-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i642127// CHECK6-NEXT: [[TMP3:%.*]] = load i32, ptr [[B]], align 42128// CHECK6-NEXT: store i32 [[TMP3]], ptr [[B1]], align 42129// CHECK6-NEXT: [[TMP4:%.*]] = load ptr, ptr @omp_high_bw_mem_alloc, align 82130// CHECK6-NEXT: [[DOTC__VOID_ADDR:%.*]] = call ptr @__kmpc_alloc(i32 [[TMP0]], i64 4, ptr [[TMP4]])2131// CHECK6-NEXT: store i32 1, ptr [[DOTC__VOID_ADDR]], align 42132// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 02133// CHECK6-NEXT: store ptr [[DOTC__VOID_ADDR]], ptr [[TMP5]], align 82134// CHECK6-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB2:[0-9]+]], i32 [[TMP0]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @_Z10array_funciPiP2St.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var)2135// CHECK6-NEXT: switch i32 [[TMP6]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [2136// CHECK6-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]]2137// CHECK6-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]]2138// CHECK6-NEXT: ]2139// CHECK6: .omp.reduction.case1:2140// CHECK6-NEXT: [[TMP7:%.*]] = load i32, ptr [[C]], align 42141// CHECK6-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTC__VOID_ADDR]], align 42142// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], [[TMP8]]2143// CHECK6-NEXT: store i32 [[MUL]], ptr [[C]], align 42144// CHECK6-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB2]], i32 [[TMP0]], ptr @.gomp_critical_user_.reduction.var)2145// CHECK6-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]2146// CHECK6: .omp.reduction.case2:2147// CHECK6-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTC__VOID_ADDR]], align 42148// CHECK6-NEXT: [[ATOMIC_LOAD:%.*]] = load atomic i32, ptr [[C]] monotonic, align 42149// CHECK6-NEXT: br label [[ATOMIC_CONT:%.*]]2150// CHECK6: atomic_cont:2151// CHECK6-NEXT: [[TMP10:%.*]] = phi i32 [ [[ATOMIC_LOAD]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[TMP15:%.*]], [[ATOMIC_CONT]] ]2152// CHECK6-NEXT: store i32 [[TMP10]], ptr [[TMP]], align 42153// CHECK6-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP]], align 42154// CHECK6-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTC__VOID_ADDR]], align 42155// CHECK6-NEXT: [[MUL4:%.*]] = mul nsw i32 [[TMP11]], [[TMP12]]2156// CHECK6-NEXT: store i32 [[MUL4]], ptr [[ATOMIC_TEMP]], align 42157// CHECK6-NEXT: [[TMP13:%.*]] = load i32, ptr [[ATOMIC_TEMP]], align 42158// CHECK6-NEXT: [[TMP14:%.*]] = cmpxchg ptr [[C]], i32 [[TMP10]], i32 [[TMP13]] monotonic monotonic, align 42159// CHECK6-NEXT: [[TMP15]] = extractvalue { i32, i1 } [[TMP14]], 02160// CHECK6-NEXT: [[TMP16:%.*]] = extractvalue { i32, i1 } [[TMP14]], 12161// CHECK6-NEXT: br i1 [[TMP16]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]]2162// CHECK6: atomic_exit:2163// CHECK6-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]2164// CHECK6: .omp.reduction.default:2165// CHECK6-NEXT: [[TMP17:%.*]] = load ptr, ptr @omp_high_bw_mem_alloc, align 82166// CHECK6-NEXT: call void @__kmpc_free(i32 [[TMP0]], ptr [[DOTC__VOID_ADDR]], ptr [[TMP17]])2167// CHECK6-NEXT: ret void2168//2169//2170// CHECK6-LABEL: define {{[^@]+}}@_Z10array_funciPiP2St.omp.reduction.reduction_func2171// CHECK6-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] {2172// CHECK6-NEXT: entry:2173// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 82174// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 82175// CHECK6-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 82176// CHECK6-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 82177// CHECK6-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 82178// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 82179// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 02180// CHECK6-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 82181// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 02182// CHECK6-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 82183// CHECK6-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 42184// CHECK6-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP5]], align 42185// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], [[TMP9]]2186// CHECK6-NEXT: store i32 [[MUL]], ptr [[TMP7]], align 42187// CHECK6-NEXT: ret void2188//2189//2190// CHECK6-LABEL: define {{[^@]+}}@main2191// CHECK6-SAME: () #[[ATTR4:[0-9]+]] {2192// CHECK6-NEXT: entry:2193// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 42194// CHECK6-NEXT: [[N:%.*]] = alloca i32, align 42195// CHECK6-NEXT: [[A:%.*]] = alloca [10 x i32], align 162196// CHECK6-NEXT: [[S:%.*]] = alloca [2 x %struct.St], align 162197// CHECK6-NEXT: store i32 0, ptr [[RETVAL]], align 42198// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.St], ptr [[S]], i32 0, i32 02199// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[ARRAY_BEGIN]], i64 22200// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]2201// CHECK6: arrayctor.loop:2202// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]2203// CHECK6-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[ARRAYCTOR_CUR]])2204// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_ST]], ptr [[ARRAYCTOR_CUR]], i64 12205// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]2206// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]2207// CHECK6: arrayctor.cont:2208// CHECK6-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 42209// CHECK6-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i64 0, i64 02210// CHECK6-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [2 x %struct.St], ptr [[S]], i64 0, i64 02211// CHECK6-NEXT: call void @_Z10array_funciPiP2St(i32 noundef [[TMP0]], ptr noundef [[ARRAYDECAY]], ptr noundef [[ARRAYDECAY1]])2212// CHECK6-NEXT: store i32 0, ptr [[RETVAL]], align 42213// CHECK6-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.St], ptr [[S]], i32 0, i32 02214// CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[ARRAY_BEGIN2]], i64 22215// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]2216// CHECK6: arraydestroy.body:2217// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]2218// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_ST]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -12219// CHECK6-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR1:[0-9]+]]2220// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]]2221// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]]2222// CHECK6: arraydestroy.done3:2223// CHECK6-NEXT: [[TMP2:%.*]] = load i32, ptr [[RETVAL]], align 42224// CHECK6-NEXT: ret i32 [[TMP2]]2225//2226//2227// CHECK6-LABEL: define {{[^@]+}}@_ZN2StC1Ev2228// CHECK6-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 {2229// CHECK6-NEXT: entry:2230// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82231// CHECK6-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82232// CHECK6-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82233// CHECK6-NEXT: call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]])2234// CHECK6-NEXT: ret void2235//2236//2237// CHECK6-LABEL: define {{[^@]+}}@_ZN2StD1Ev2238// CHECK6-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 {2239// CHECK6-NEXT: entry:2240// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82241// CHECK6-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82242// CHECK6-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82243// CHECK6-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR1]]2244// CHECK6-NEXT: ret void2245//2246//2247// CHECK6-LABEL: define {{[^@]+}}@_ZN2StC2Ev2248// CHECK6-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 {2249// CHECK6-NEXT: entry:2250// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82251// CHECK6-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82252// CHECK6-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82253// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 02254// CHECK6-NEXT: store i32 0, ptr [[A]], align 42255// CHECK6-NEXT: [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 12256// CHECK6-NEXT: store i32 0, ptr [[B]], align 42257// CHECK6-NEXT: ret void2258//2259//2260// CHECK6-LABEL: define {{[^@]+}}@_ZN2StD2Ev2261// CHECK6-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 {2262// CHECK6-NEXT: entry:2263// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82264// CHECK6-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82265// CHECK6-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82266// CHECK6-NEXT: ret void2267//2268