1089 lines · cpp
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _2// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s4// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK36// RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK47 8// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"9// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s10// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"11// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"12// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"13// expected-no-diagnostics14#ifndef HEADER15#define HEADER16 17struct St {18 int a, b;19 St() : a(0), b(0) {}20 St(const St &st) : a(st.a + st.b), b(0) {}21 ~St() {}22};23 24volatile int g = 1212;25 26template <class T>27struct S {28 T f;29 S(T a) : f(a + g) {}30 S() : f(g) {}31 S(const S &s, St t = St()) : f(s.f + t.a) {}32 operator T() { return T(); }33 ~S() {}34};35 36 37template <typename T>38T tmain() {39 S<T> test;40 T t_var = T();41 T vec[] = {1, 2};42 S<T> s_arr[] = {1, 2};43 S<T> var(3);44#pragma omp parallel45#pragma omp sections firstprivate(t_var, vec, s_arr, var)46 {47 vec[0] = t_var;48#pragma omp section49 s_arr[0] = var;50 }51 return T();52}53 54S<float> test;55int t_var = 333;56int vec[] = {1, 2};57S<float> s_arr[] = {1, 2};58S<float> var(3);59 60int main() {61 static int sivar;62#ifdef LAMBDA63 [&]() {64#pragma omp parallel65#pragma omp sections firstprivate(g, sivar)66 {67 // Skip temp vars for loop68 69 70 71 {72 g = 1;73 sivar = 10;74 }75#pragma omp section76 [&]() {77 g = 2;78 sivar = 20;79 }();80 }81 }();82 return 0;83#elif defined(BLOCKS)84 ^{85#pragma omp parallel86#pragma omp sections firstprivate(g, sivar)87 {88 // Skip temp vars for loop89 90 91 92 {93 g = 1;94 sivar = 10;95 }96#pragma omp section97 ^{98 g = 2;99 sivar = 20;100 }();101 }102 }();103 return 0;104#else105#pragma omp sections firstprivate(t_var, vec, s_arr, var, sivar) nowait106 {107 {108 vec[0] = t_var;109 s_arr[0] = var;110 sivar = 31;111 }112 }113 return tmain<int>();114#endif115}116 117 118// firstprivate t_var(t_var)119 120// firstprivate vec(vec)121 122// firstprivate s_arr(s_arr)123 124// firstprivate var(var)125 126// firstprivate isvar127 128 129// ~(firstprivate var), ~(firstprivate s_arr)130 131 132 133// Skip temp vars for loop134 135 136// firstprivate t_var(t_var)137 138// firstprivate vec(vec)139 140// firstprivate s_arr(s_arr)141 142// firstprivate var(var)143 144// No synchronization for initialization.145 146 147// ~(firstprivate var), ~(firstprivate s_arr)148#endif149 150// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init151// CHECK1-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" {152// CHECK1-NEXT: entry:153// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)154// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]155// CHECK1-NEXT: ret void156//157//158// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev159// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 {160// CHECK1-NEXT: entry:161// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8162// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8163// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8164// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])165// CHECK1-NEXT: ret void166//167//168// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev169// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {170// CHECK1-NEXT: entry:171// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8172// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8173// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8174// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]175// CHECK1-NEXT: ret void176//177//178// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev179// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {180// CHECK1-NEXT: entry:181// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8182// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8183// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8184// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0185// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4186// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float187// CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4188// CHECK1-NEXT: ret void189//190//191// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev192// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {193// CHECK1-NEXT: entry:194// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8195// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8196// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8197// CHECK1-NEXT: ret void198//199//200// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1201// CHECK1-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {202// CHECK1-NEXT: entry:203// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)204// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)205// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]206// CHECK1-NEXT: ret void207//208//209// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef210// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {211// CHECK1-NEXT: entry:212// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8213// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4214// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8215// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4216// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8217// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4218// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])219// CHECK1-NEXT: ret void220//221//222// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor223// CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {224// CHECK1-NEXT: entry:225// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8226// CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8227// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]228// CHECK1: arraydestroy.body:229// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]230// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1231// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]232// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr233// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]234// CHECK1: arraydestroy.done1:235// CHECK1-NEXT: ret void236//237//238// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef239// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {240// CHECK1-NEXT: entry:241// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8242// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4243// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8244// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4245// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8246// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0247// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4248// CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4249// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float250// CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]251// CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4252// CHECK1-NEXT: ret void253//254//255// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2256// CHECK1-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {257// CHECK1-NEXT: entry:258// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)259// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]260// CHECK1-NEXT: ret void261//262//263// CHECK1-LABEL: define {{[^@]+}}@main264// CHECK1-SAME: () #[[ATTR3:[0-9]+]] {265// CHECK1-NEXT: entry:266// CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4267// CHECK1-NEXT: [[DOTOMP_SECTIONS_LB_:%.*]] = alloca i32, align 4268// CHECK1-NEXT: [[DOTOMP_SECTIONS_UB_:%.*]] = alloca i32, align 4269// CHECK1-NEXT: [[DOTOMP_SECTIONS_ST_:%.*]] = alloca i32, align 4270// CHECK1-NEXT: [[DOTOMP_SECTIONS_IL_:%.*]] = alloca i32, align 4271// CHECK1-NEXT: [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4272// CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4273// CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4274// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4275// CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4276// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4277// CHECK1-NEXT: [[AGG_TMP2:%.*]] = alloca [[STRUCT_ST]], align 4278// CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4279// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])280// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4281// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_LB_]], align 4282// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_UB_]], align 4283// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_SECTIONS_ST_]], align 4284// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_IL_]], align 4285// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr @t_var, align 4286// CHECK1-NEXT: store i32 [[TMP1]], ptr [[T_VAR]], align 4287// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @vec, i64 8, i1 false)288// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0289// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2290// CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP2]]291// CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]292// CHECK1: omp.arraycpy.body:293// CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ @s_arr, [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]294// CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]295// CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])296// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]])297// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]298// CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1299// CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1300// CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP2]]301// CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]]302// CHECK1: omp.arraycpy.done1:303// CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP2]])304// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]], ptr noundef nonnull align 4 dereferenceable(4) @var, ptr noundef [[AGG_TMP2]])305// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP2]]) #[[ATTR2]]306// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4307// CHECK1-NEXT: store i32 [[TMP3]], ptr [[SIVAR]], align 4308// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_SECTIONS_IL_]], ptr [[DOTOMP_SECTIONS_LB_]], ptr [[DOTOMP_SECTIONS_UB_]], ptr [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1)309// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_UB_]], align 4310// CHECK1-NEXT: [[TMP5:%.*]] = icmp slt i32 [[TMP4]], 0311// CHECK1-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], i32 [[TMP4]], i32 0312// CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_SECTIONS_UB_]], align 4313// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_LB_]], align 4314// CHECK1-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_SECTIONS_IV_]], align 4315// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]316// CHECK1: omp.inner.for.cond:317// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 4318// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_UB_]], align 4319// CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]320// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]321// CHECK1: omp.inner.for.body:322// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 4323// CHECK1-NEXT: switch i32 [[TMP10]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [324// CHECK1-NEXT: i32 0, label [[DOTOMP_SECTIONS_CASE:%.*]]325// CHECK1-NEXT: ]326// CHECK1: .omp.sections.case:327// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[T_VAR]], align 4328// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0329// CHECK1-NEXT: store i32 [[TMP11]], ptr [[ARRAYIDX]], align 4330// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0331// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[VAR]], i64 4, i1 false)332// CHECK1-NEXT: store i32 31, ptr [[SIVAR]], align 4333// CHECK1-NEXT: br label [[DOTOMP_SECTIONS_EXIT]]334// CHECK1: .omp.sections.exit:335// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]336// CHECK1: omp.inner.for.inc:337// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 4338// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1339// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTOMP_SECTIONS_IV_]], align 4340// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]341// CHECK1: omp.inner.for.end:342// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]])343// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]344// CHECK1-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0345// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN4]], i64 2346// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]347// CHECK1: arraydestroy.body:348// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]349// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1350// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]351// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]]352// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]]353// CHECK1: arraydestroy.done5:354// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()355// CHECK1-NEXT: ret i32 [[CALL]]356//357//358// CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev359// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {360// CHECK1-NEXT: entry:361// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8362// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8363// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8364// CHECK1-NEXT: call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]])365// CHECK1-NEXT: ret void366//367//368// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St369// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {370// CHECK1-NEXT: entry:371// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8372// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8373// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8374// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8375// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8376// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8377// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8378// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8379// CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]])380// CHECK1-NEXT: ret void381//382//383// CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev384// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {385// CHECK1-NEXT: entry:386// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8387// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8388// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8389// CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]]390// CHECK1-NEXT: ret void391//392//393// CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v394// CHECK1-SAME: () #[[ATTR1]] {395// CHECK1-NEXT: entry:396// CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4397// CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4398// CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4399// CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4400// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4401// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4402// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])403// CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4404// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)405// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1)406// CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1407// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)408// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]], i32 noundef 3)409// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_Z5tmainIiET_v.omp_outlined, ptr [[T_VAR]], ptr [[VEC]], ptr [[S_ARR]], ptr [[VAR]])410// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4411// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]412// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0413// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2414// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]415// CHECK1: arraydestroy.body:416// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP0]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]417// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1418// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]419// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]420// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]421// CHECK1: arraydestroy.done1:422// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]423// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4424// CHECK1-NEXT: ret i32 [[TMP1]]425//426//427// CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev428// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {429// CHECK1-NEXT: entry:430// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8431// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8432// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8433// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0434// CHECK1-NEXT: store i32 0, ptr [[A]], align 4435// CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1436// CHECK1-NEXT: store i32 0, ptr [[B]], align 4437// CHECK1-NEXT: ret void438//439//440// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St441// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {442// CHECK1-NEXT: entry:443// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8444// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8445// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8446// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8447// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8448// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8449// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8450// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0451// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]]452// CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0453// CHECK1-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4454// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0455// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4456// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float457// CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]458// CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4459// CHECK1-NEXT: ret void460//461//462// CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev463// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {464// CHECK1-NEXT: entry:465// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8466// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8467// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8468// CHECK1-NEXT: ret void469//470//471// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev472// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {473// CHECK1-NEXT: entry:474// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8475// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8476// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8477// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])478// CHECK1-NEXT: ret void479//480//481// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei482// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {483// CHECK1-NEXT: entry:484// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8485// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4486// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8487// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4488// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8489// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4490// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])491// CHECK1-NEXT: ret void492//493//494// CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v.omp_outlined495// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR5:[0-9]+]] {496// CHECK1-NEXT: entry:497// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8498// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8499// CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 8500// CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8501// CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8502// CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8503// CHECK1-NEXT: [[DOTOMP_SECTIONS_LB_:%.*]] = alloca i32, align 4504// CHECK1-NEXT: [[DOTOMP_SECTIONS_UB_:%.*]] = alloca i32, align 4505// CHECK1-NEXT: [[DOTOMP_SECTIONS_ST_:%.*]] = alloca i32, align 4506// CHECK1-NEXT: [[DOTOMP_SECTIONS_IL_:%.*]] = alloca i32, align 4507// CHECK1-NEXT: [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4508// CHECK1-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4509// CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4510// CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4511// CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4512// CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4513// CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4514// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8515// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8516// CHECK1-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8517// CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8518// CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8519// CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8520// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]]521// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META3]], !align [[META4]]522// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]]523// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]]524// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_LB_]], align 4525// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_SECTIONS_UB_]], align 4526// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_SECTIONS_ST_]], align 4527// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_IL_]], align 4528// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP0]], align 4529// CHECK1-NEXT: store i32 [[TMP4]], ptr [[T_VAR1]], align 4530// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC2]], ptr align 4 [[TMP1]], i64 8, i1 false)531// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0532// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2533// CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]]534// CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]535// CHECK1: omp.arraycpy.body:536// CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]537// CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]538// CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])539// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]])540// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]541// CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1542// CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1543// CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]]544// CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]545// CHECK1: omp.arraycpy.done4:546// CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]])547// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP3]], ptr noundef [[AGG_TMP6]])548// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]549// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8550// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4551// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_SECTIONS_IL_]], ptr [[DOTOMP_SECTIONS_LB_]], ptr [[DOTOMP_SECTIONS_UB_]], ptr [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1)552// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_UB_]], align 4553// CHECK1-NEXT: [[TMP9:%.*]] = icmp slt i32 [[TMP8]], 1554// CHECK1-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], i32 [[TMP8]], i32 1555// CHECK1-NEXT: store i32 [[TMP10]], ptr [[DOTOMP_SECTIONS_UB_]], align 4556// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_LB_]], align 4557// CHECK1-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_SECTIONS_IV_]], align 4558// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]559// CHECK1: omp.inner.for.cond:560// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 4561// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_UB_]], align 4562// CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]563// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]564// CHECK1: omp.inner.for.body:565// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 4566// CHECK1-NEXT: switch i32 [[TMP14]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [567// CHECK1-NEXT: i32 0, label [[DOTOMP_SECTIONS_CASE:%.*]]568// CHECK1-NEXT: i32 1, label [[DOTOMP_SECTIONS_CASE7:%.*]]569// CHECK1-NEXT: ]570// CHECK1: .omp.sections.case:571// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR1]], align 4572// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i64 0, i64 0573// CHECK1-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4574// CHECK1-NEXT: br label [[DOTOMP_SECTIONS_EXIT]]575// CHECK1: .omp.sections.case7:576// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i64 0, i64 0577// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[VAR5]], i64 4, i1 false)578// CHECK1-NEXT: br label [[DOTOMP_SECTIONS_EXIT]]579// CHECK1: .omp.sections.exit:580// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]581// CHECK1: omp.inner.for.inc:582// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 4583// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP16]], 1584// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTOMP_SECTIONS_IV_]], align 4585// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]586// CHECK1: omp.inner.for.end:587// CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8588// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4589// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP18]])590// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]591// CHECK1-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0592// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i64 2593// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]594// CHECK1: arraydestroy.body:595// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP19]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]596// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1597// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]598// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]]599// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]]600// CHECK1: arraydestroy.done10:601// CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8602// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4603// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP21]])604// CHECK1-NEXT: ret void605//606//607// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St608// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {609// CHECK1-NEXT: entry:610// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8611// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8612// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8613// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8614// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8615// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8616// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8617// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8618// CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]])619// CHECK1-NEXT: ret void620//621//622// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev623// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {624// CHECK1-NEXT: entry:625// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8626// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8627// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8628// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]629// CHECK1-NEXT: ret void630//631//632// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev633// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {634// CHECK1-NEXT: entry:635// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8636// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8637// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8638// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0639// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4640// CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4641// CHECK1-NEXT: ret void642//643//644// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei645// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {646// CHECK1-NEXT: entry:647// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8648// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4649// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8650// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4651// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8652// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0653// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4654// CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4655// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]656// CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4657// CHECK1-NEXT: ret void658//659//660// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St661// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {662// CHECK1-NEXT: entry:663// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8664// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8665// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8666// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8667// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8668// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8669// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8670// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0671// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8, !nonnull [[META3]], !align [[META4]]672// CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0673// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4674// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0675// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4676// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]677// CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4678// CHECK1-NEXT: ret void679//680//681// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev682// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {683// CHECK1-NEXT: entry:684// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8685// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8686// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8687// CHECK1-NEXT: ret void688//689//690// CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_sections_firstprivate_codegen.cpp691// CHECK1-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {692// CHECK1-NEXT: entry:693// CHECK1-NEXT: call void @__cxx_global_var_init()694// CHECK1-NEXT: call void @__cxx_global_var_init.1()695// CHECK1-NEXT: call void @__cxx_global_var_init.2()696// CHECK1-NEXT: ret void697//698//699// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init700// CHECK3-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" {701// CHECK3-NEXT: entry:702// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)703// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]704// CHECK3-NEXT: ret void705//706//707// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev708// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 {709// CHECK3-NEXT: entry:710// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8711// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8712// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8713// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])714// CHECK3-NEXT: ret void715//716//717// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev718// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {719// CHECK3-NEXT: entry:720// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8721// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8722// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8723// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]724// CHECK3-NEXT: ret void725//726//727// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev728// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {729// CHECK3-NEXT: entry:730// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8731// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8732// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8733// CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0734// CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4735// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float736// CHECK3-NEXT: store float [[CONV]], ptr [[F]], align 4737// CHECK3-NEXT: ret void738//739//740// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev741// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {742// CHECK3-NEXT: entry:743// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8744// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8745// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8746// CHECK3-NEXT: ret void747//748//749// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1750// CHECK3-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {751// CHECK3-NEXT: entry:752// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)753// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)754// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]755// CHECK3-NEXT: ret void756//757//758// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef759// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {760// CHECK3-NEXT: entry:761// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8762// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4763// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8764// CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4765// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8766// CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4767// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])768// CHECK3-NEXT: ret void769//770//771// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor772// CHECK3-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {773// CHECK3-NEXT: entry:774// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8775// CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8776// CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]777// CHECK3: arraydestroy.body:778// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]779// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1780// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]781// CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr782// CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]783// CHECK3: arraydestroy.done1:784// CHECK3-NEXT: ret void785//786//787// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef788// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {789// CHECK3-NEXT: entry:790// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8791// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4792// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8793// CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4794// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8795// CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0796// CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4797// CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4798// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float799// CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]800// CHECK3-NEXT: store float [[ADD]], ptr [[F]], align 4801// CHECK3-NEXT: ret void802//803//804// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2805// CHECK3-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {806// CHECK3-NEXT: entry:807// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)808// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]809// CHECK3-NEXT: ret void810//811//812// CHECK3-LABEL: define {{[^@]+}}@main813// CHECK3-SAME: () #[[ATTR3:[0-9]+]] {814// CHECK3-NEXT: entry:815// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4816// CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8817// CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4818// CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0819// CHECK3-NEXT: store ptr @_ZZ4mainE5sivar, ptr [[TMP0]], align 8820// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(8) [[REF_TMP]])821// CHECK3-NEXT: ret i32 0822//823//824// CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_sections_firstprivate_codegen.cpp825// CHECK3-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {826// CHECK3-NEXT: entry:827// CHECK3-NEXT: call void @__cxx_global_var_init()828// CHECK3-NEXT: call void @__cxx_global_var_init.1()829// CHECK3-NEXT: call void @__cxx_global_var_init.2()830// CHECK3-NEXT: ret void831//832//833// CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init834// CHECK4-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" {835// CHECK4-NEXT: entry:836// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)837// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]838// CHECK4-NEXT: ret void839//840//841// CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev842// CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 {843// CHECK4-NEXT: entry:844// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8845// CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8846// CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8847// CHECK4-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])848// CHECK4-NEXT: ret void849//850//851// CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev852// CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {853// CHECK4-NEXT: entry:854// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8855// CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8856// CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8857// CHECK4-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]858// CHECK4-NEXT: ret void859//860//861// CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev862// CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {863// CHECK4-NEXT: entry:864// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8865// CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8866// CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8867// CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0868// CHECK4-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4869// CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float870// CHECK4-NEXT: store float [[CONV]], ptr [[F]], align 4871// CHECK4-NEXT: ret void872//873//874// CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev875// CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {876// CHECK4-NEXT: entry:877// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8878// CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8879// CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8880// CHECK4-NEXT: ret void881//882//883// CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1884// CHECK4-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {885// CHECK4-NEXT: entry:886// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)887// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)888// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]889// CHECK4-NEXT: ret void890//891//892// CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef893// CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {894// CHECK4-NEXT: entry:895// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8896// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4897// CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8898// CHECK4-NEXT: store float [[A]], ptr [[A_ADDR]], align 4899// CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8900// CHECK4-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4901// CHECK4-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])902// CHECK4-NEXT: ret void903//904//905// CHECK4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor906// CHECK4-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {907// CHECK4-NEXT: entry:908// CHECK4-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8909// CHECK4-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8910// CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]911// CHECK4: arraydestroy.body:912// CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]913// CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1914// CHECK4-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]915// CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr916// CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]917// CHECK4: arraydestroy.done1:918// CHECK4-NEXT: ret void919//920//921// CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef922// CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {923// CHECK4-NEXT: entry:924// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8925// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4926// CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8927// CHECK4-NEXT: store float [[A]], ptr [[A_ADDR]], align 4928// CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8929// CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0930// CHECK4-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4931// CHECK4-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4932// CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float933// CHECK4-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]934// CHECK4-NEXT: store float [[ADD]], ptr [[F]], align 4935// CHECK4-NEXT: ret void936//937//938// CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2939// CHECK4-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {940// CHECK4-NEXT: entry:941// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)942// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]943// CHECK4-NEXT: ret void944//945//946// CHECK4-LABEL: define {{[^@]+}}@main947// CHECK4-SAME: () #[[ATTR3:[0-9]+]] {948// CHECK4-NEXT: entry:949// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4950// CHECK4-NEXT: [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, i32 }>, align 8951// CHECK4-NEXT: store i32 0, ptr [[RETVAL]], align 4952// CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 0953// CHECK4-NEXT: store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 8954// CHECK4-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 1955// CHECK4-NEXT: store i32 1073741824, ptr [[BLOCK_FLAGS]], align 8956// CHECK4-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 2957// CHECK4-NEXT: store i32 0, ptr [[BLOCK_RESERVED]], align 4958// CHECK4-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 3959// CHECK4-NEXT: store ptr @__main_block_invoke, ptr [[BLOCK_INVOKE]], align 8960// CHECK4-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 4961// CHECK4-NEXT: store ptr @__block_descriptor_tmp.3, ptr [[BLOCK_DESCRIPTOR]], align 8962// CHECK4-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 5963// CHECK4-NEXT: [[TMP0:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4964// CHECK4-NEXT: store i32 [[TMP0]], ptr [[BLOCK_CAPTURED]], align 8965// CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3966// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8967// CHECK4-NEXT: call void [[TMP2]](ptr noundef [[BLOCK]])968// CHECK4-NEXT: ret i32 0969//970//971// CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke972// CHECK4-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR4:[0-9]+]] {973// CHECK4-NEXT: entry:974// CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8975// CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8976// CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8977// CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8978// CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3:[0-9]+]], i32 1, ptr @__main_block_invoke.omp_outlined, ptr @_ZZ4mainE5sivar)979// CHECK4-NEXT: ret void980//981//982// CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke.omp_outlined983// CHECK4-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] {984// CHECK4-NEXT: entry:985// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8986// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8987// CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 8988// CHECK4-NEXT: [[DOTOMP_SECTIONS_LB_:%.*]] = alloca i32, align 4989// CHECK4-NEXT: [[DOTOMP_SECTIONS_UB_:%.*]] = alloca i32, align 4990// CHECK4-NEXT: [[DOTOMP_SECTIONS_ST_:%.*]] = alloca i32, align 4991// CHECK4-NEXT: [[DOTOMP_SECTIONS_IL_:%.*]] = alloca i32, align 4992// CHECK4-NEXT: [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4993// CHECK4-NEXT: [[G:%.*]] = alloca i32, align 4994// CHECK4-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4995// CHECK4-NEXT: [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, align 8996// CHECK4-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8997// CHECK4-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8998// CHECK4-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8999// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]]1000// CHECK4-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_LB_]], align 41001// CHECK4-NEXT: store i32 1, ptr [[DOTOMP_SECTIONS_UB_]], align 41002// CHECK4-NEXT: store i32 1, ptr [[DOTOMP_SECTIONS_ST_]], align 41003// CHECK4-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_IL_]], align 41004// CHECK4-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 41005// CHECK4-NEXT: store i32 [[TMP1]], ptr [[G]], align 41006// CHECK4-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP0]], align 41007// CHECK4-NEXT: store i32 [[TMP2]], ptr [[SIVAR1]], align 41008// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81009// CHECK4-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 41010// CHECK4-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP4]], i32 34, ptr [[DOTOMP_SECTIONS_IL_]], ptr [[DOTOMP_SECTIONS_LB_]], ptr [[DOTOMP_SECTIONS_UB_]], ptr [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1)1011// CHECK4-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_UB_]], align 41012// CHECK4-NEXT: [[TMP6:%.*]] = icmp slt i32 [[TMP5]], 11013// CHECK4-NEXT: [[TMP7:%.*]] = select i1 [[TMP6]], i32 [[TMP5]], i32 11014// CHECK4-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_SECTIONS_UB_]], align 41015// CHECK4-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_LB_]], align 41016// CHECK4-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_SECTIONS_IV_]], align 41017// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1018// CHECK4: omp.inner.for.cond:1019// CHECK4-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 41020// CHECK4-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_UB_]], align 41021// CHECK4-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]1022// CHECK4-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1023// CHECK4: omp.inner.for.body:1024// CHECK4-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 41025// CHECK4-NEXT: switch i32 [[TMP11]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [1026// CHECK4-NEXT: i32 0, label [[DOTOMP_SECTIONS_CASE:%.*]]1027// CHECK4-NEXT: i32 1, label [[DOTOMP_SECTIONS_CASE2:%.*]]1028// CHECK4-NEXT: ]1029// CHECK4: .omp.sections.case:1030// CHECK4-NEXT: store i32 1, ptr [[G]], align 41031// CHECK4-NEXT: store i32 10, ptr [[SIVAR1]], align 41032// CHECK4-NEXT: br label [[DOTOMP_SECTIONS_EXIT]]1033// CHECK4: .omp.sections.case2:1034// CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 01035// CHECK4-NEXT: store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 81036// CHECK4-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 11037// CHECK4-NEXT: store i32 1073741824, ptr [[BLOCK_FLAGS]], align 81038// CHECK4-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 21039// CHECK4-NEXT: store i32 0, ptr [[BLOCK_RESERVED]], align 41040// CHECK4-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 31041// CHECK4-NEXT: store ptr @var_block_invoke, ptr [[BLOCK_INVOKE]], align 81042// CHECK4-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 41043// CHECK4-NEXT: store ptr @__block_descriptor_tmp, ptr [[BLOCK_DESCRIPTOR]], align 81044// CHECK4-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 51045// CHECK4-NEXT: [[TMP12:%.*]] = load volatile i32, ptr [[G]], align 41046// CHECK4-NEXT: store volatile i32 [[TMP12]], ptr [[BLOCK_CAPTURED]], align 81047// CHECK4-NEXT: [[BLOCK_CAPTURED3:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 61048// CHECK4-NEXT: [[TMP13:%.*]] = load i32, ptr [[SIVAR1]], align 41049// CHECK4-NEXT: store i32 [[TMP13]], ptr [[BLOCK_CAPTURED3]], align 41050// CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 31051// CHECK4-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP14]], align 81052// CHECK4-NEXT: call void [[TMP15]](ptr noundef [[BLOCK]])1053// CHECK4-NEXT: br label [[DOTOMP_SECTIONS_EXIT]]1054// CHECK4: .omp.sections.exit:1055// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1056// CHECK4: omp.inner.for.inc:1057// CHECK4-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 41058// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP16]], 11059// CHECK4-NEXT: store i32 [[INC]], ptr [[DOTOMP_SECTIONS_IV_]], align 41060// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]]1061// CHECK4: omp.inner.for.end:1062// CHECK4-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP4]])1063// CHECK4-NEXT: call void @__kmpc_barrier(ptr @[[GLOB2:[0-9]+]], i32 [[TMP4]])1064// CHECK4-NEXT: ret void1065//1066//1067// CHECK4-LABEL: define {{[^@]+}}@var_block_invoke1068// CHECK4-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR4]] {1069// CHECK4-NEXT: entry:1070// CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 81071// CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 81072// CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 81073// CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 81074// CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 51075// CHECK4-NEXT: store i32 2, ptr [[BLOCK_CAPTURE_ADDR]], align 81076// CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 61077// CHECK4-NEXT: store i32 20, ptr [[BLOCK_CAPTURE_ADDR1]], align 41078// CHECK4-NEXT: ret void1079//1080//1081// CHECK4-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_sections_firstprivate_codegen.cpp1082// CHECK4-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {1083// CHECK4-NEXT: entry:1084// CHECK4-NEXT: call void @__cxx_global_var_init()1085// CHECK4-NEXT: call void @__cxx_global_var_init.1()1086// CHECK4-NEXT: call void @__cxx_global_var_init.2()1087// CHECK4-NEXT: ret void1088//1089