610 lines · cpp
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _2// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s4// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK36// RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK47 8// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"9// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s10// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"11// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"12// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"13// expected-no-diagnostics14#ifndef HEADER15#define HEADER16 17template <class T>18struct S {19 T f;20 S(T a) : f(a) {}21 S() : f() {}22 operator T() { return T(); }23 ~S() {}24};25 26volatile double g;27 28template <typename T>29T tmain() {30 S<T> test;31 T t_var = T();32 T vec[] = {1, 2};33 S<T> s_arr[] = {1, 2};34 S<T> var(3);35#pragma omp parallel36#pragma omp sections private(t_var, vec, s_arr, s_arr, var, var)37 {38 vec[0] = t_var;39#pragma omp section40 s_arr[0] = var;41 }42 return T();43}44 45int main() {46 static int sivar;47#ifdef LAMBDA48 [&]() {49#pragma omp parallel50#pragma omp sections private(g, sivar)51 {52 {53 g = 1;54 sivar = 11;55 }56#pragma omp section57 [&]() {58 g = 2;59 sivar = 22;60 61 62 }();63 }64 }();65 return 0;66#elif defined(BLOCKS)67 ^{68#pragma omp parallel69#pragma omp sections private(g, sivar)70 {71 {72 g = 1;73 sivar = 111;74 }75#pragma omp section76 ^{77 g = 2;78 sivar = 222;79 }();80 }81 }();82 return 0;83#else84 S<float> test;85 int t_var = 0;86 int vec[] = {1, 2};87 S<float> s_arr[] = {1, 2};88 S<float> var(3);89#pragma omp parallel90#pragma omp sections private(t_var, vec, s_arr, s_arr, var, var, sivar)91 {92 {93 vec[0] = t_var;94 s_arr[0] = var;95 sivar = 2;96 }97 }98 return tmain<int>();99#endif100}101 102 103 104 105#endif106 107// CHECK1-LABEL: define {{[^@]+}}@main108// CHECK1-SAME: () #[[ATTR0:[0-9]+]] {109// CHECK1-NEXT: entry:110// CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4111// CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4112// CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4113// CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4114// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4115// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4116// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4117// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])118// CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4119// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i64 8, i1 false)120// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], float noundef 1.000000e+00)121// CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i64 1122// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00)123// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]], float noundef 3.000000e+00)124// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3:[0-9]+]], i32 0, ptr @main.omp_outlined)125// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()126// CHECK1-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4127// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]]128// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0129// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2130// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]131// CHECK1: arraydestroy.body:132// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP0]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]133// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1134// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]135// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]136// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]137// CHECK1: arraydestroy.done1:138// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]139// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4140// CHECK1-NEXT: ret i32 [[TMP1]]141//142//143// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev144// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {145// CHECK1-NEXT: entry:146// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8147// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8148// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8149// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])150// CHECK1-NEXT: ret void151//152//153// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef154// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {155// CHECK1-NEXT: entry:156// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8157// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4158// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8159// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4160// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8161// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4162// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])163// CHECK1-NEXT: ret void164//165//166// CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined167// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {168// CHECK1-NEXT: entry:169// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8170// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8171// CHECK1-NEXT: [[DOTOMP_SECTIONS_LB_:%.*]] = alloca i32, align 4172// CHECK1-NEXT: [[DOTOMP_SECTIONS_UB_:%.*]] = alloca i32, align 4173// CHECK1-NEXT: [[DOTOMP_SECTIONS_ST_:%.*]] = alloca i32, align 4174// CHECK1-NEXT: [[DOTOMP_SECTIONS_IL_:%.*]] = alloca i32, align 4175// CHECK1-NEXT: [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4176// CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4177// CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4178// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4179// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4180// CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4181// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8182// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8183// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_LB_]], align 4184// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_UB_]], align 4185// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_SECTIONS_ST_]], align 4186// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_IL_]], align 4187// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0188// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2189// CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]190// CHECK1: arrayctor.loop:191// CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]192// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])193// CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1194// CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]195// CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]196// CHECK1: arrayctor.cont:197// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])198// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8199// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4200// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_SECTIONS_IL_]], ptr [[DOTOMP_SECTIONS_LB_]], ptr [[DOTOMP_SECTIONS_UB_]], ptr [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1)201// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_UB_]], align 4202// CHECK1-NEXT: [[TMP3:%.*]] = icmp slt i32 [[TMP2]], 0203// CHECK1-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], i32 [[TMP2]], i32 0204// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_SECTIONS_UB_]], align 4205// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_LB_]], align 4206// CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_SECTIONS_IV_]], align 4207// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]208// CHECK1: omp.inner.for.cond:209// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 4210// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_UB_]], align 4211// CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]212// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]213// CHECK1: omp.inner.for.body:214// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 4215// CHECK1-NEXT: switch i32 [[TMP8]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [216// CHECK1-NEXT: i32 0, label [[DOTOMP_SECTIONS_CASE:%.*]]217// CHECK1-NEXT: ]218// CHECK1: .omp.sections.case:219// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[T_VAR]], align 4220// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0221// CHECK1-NEXT: store i32 [[TMP9]], ptr [[ARRAYIDX]], align 4222// CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0223// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX1]], ptr align 4 [[VAR]], i64 4, i1 false)224// CHECK1-NEXT: store i32 2, ptr [[SIVAR]], align 4225// CHECK1-NEXT: br label [[DOTOMP_SECTIONS_EXIT]]226// CHECK1: .omp.sections.exit:227// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]228// CHECK1: omp.inner.for.inc:229// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 4230// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1231// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTOMP_SECTIONS_IV_]], align 4232// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]233// CHECK1: omp.inner.for.end:234// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8235// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4236// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP12]])237// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]]238// CHECK1-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0239// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN2]], i64 2240// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]241// CHECK1: arraydestroy.body:242// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]243// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1244// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]245// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]]246// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]]247// CHECK1: arraydestroy.done3:248// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8249// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4250// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB2:[0-9]+]], i32 [[TMP15]])251// CHECK1-NEXT: ret void252//253//254// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev255// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {256// CHECK1-NEXT: entry:257// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8258// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8259// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8260// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]261// CHECK1-NEXT: ret void262//263//264// CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v265// CHECK1-SAME: () #[[ATTR1]] comdat {266// CHECK1-NEXT: entry:267// CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4268// CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4269// CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4270// CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4271// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4272// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4273// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])274// CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4275// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)276// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1)277// CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1278// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)279// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]], i32 noundef 3)280// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 0, ptr @_Z5tmainIiET_v.omp_outlined)281// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4282// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]]283// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0284// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2285// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]286// CHECK1: arraydestroy.body:287// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP0]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]288// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1289// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]290// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]291// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]292// CHECK1: arraydestroy.done1:293// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]294// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4295// CHECK1-NEXT: ret i32 [[TMP1]]296//297//298// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev299// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {300// CHECK1-NEXT: entry:301// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8302// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8303// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8304// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0305// CHECK1-NEXT: store float 0.000000e+00, ptr [[F]], align 4306// CHECK1-NEXT: ret void307//308//309// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef310// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {311// CHECK1-NEXT: entry:312// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8313// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4314// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8315// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4316// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8317// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0318// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4319// CHECK1-NEXT: store float [[TMP0]], ptr [[F]], align 4320// CHECK1-NEXT: ret void321//322//323// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev324// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {325// CHECK1-NEXT: entry:326// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8327// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8328// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8329// CHECK1-NEXT: ret void330//331//332// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev333// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {334// CHECK1-NEXT: entry:335// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8336// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8337// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8338// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])339// CHECK1-NEXT: ret void340//341//342// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei343// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {344// CHECK1-NEXT: entry:345// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8346// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4347// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8348// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4349// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8350// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4351// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])352// CHECK1-NEXT: ret void353//354//355// CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v.omp_outlined356// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {357// CHECK1-NEXT: entry:358// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8359// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8360// CHECK1-NEXT: [[DOTOMP_SECTIONS_LB_:%.*]] = alloca i32, align 4361// CHECK1-NEXT: [[DOTOMP_SECTIONS_UB_:%.*]] = alloca i32, align 4362// CHECK1-NEXT: [[DOTOMP_SECTIONS_ST_:%.*]] = alloca i32, align 4363// CHECK1-NEXT: [[DOTOMP_SECTIONS_IL_:%.*]] = alloca i32, align 4364// CHECK1-NEXT: [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4365// CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4366// CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4367// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4368// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4369// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8370// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8371// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_LB_]], align 4372// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_SECTIONS_UB_]], align 4373// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_SECTIONS_ST_]], align 4374// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_IL_]], align 4375// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0376// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2377// CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]378// CHECK1: arrayctor.loop:379// CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]380// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])381// CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1382// CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]383// CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]384// CHECK1: arrayctor.cont:385// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])386// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8387// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4388// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_SECTIONS_IL_]], ptr [[DOTOMP_SECTIONS_LB_]], ptr [[DOTOMP_SECTIONS_UB_]], ptr [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1)389// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_UB_]], align 4390// CHECK1-NEXT: [[TMP3:%.*]] = icmp slt i32 [[TMP2]], 1391// CHECK1-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], i32 [[TMP2]], i32 1392// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_SECTIONS_UB_]], align 4393// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_LB_]], align 4394// CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_SECTIONS_IV_]], align 4395// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]396// CHECK1: omp.inner.for.cond:397// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 4398// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_UB_]], align 4399// CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]400// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]401// CHECK1: omp.inner.for.body:402// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 4403// CHECK1-NEXT: switch i32 [[TMP8]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [404// CHECK1-NEXT: i32 0, label [[DOTOMP_SECTIONS_CASE:%.*]]405// CHECK1-NEXT: i32 1, label [[DOTOMP_SECTIONS_CASE1:%.*]]406// CHECK1-NEXT: ]407// CHECK1: .omp.sections.case:408// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[T_VAR]], align 4409// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0410// CHECK1-NEXT: store i32 [[TMP9]], ptr [[ARRAYIDX]], align 4411// CHECK1-NEXT: br label [[DOTOMP_SECTIONS_EXIT]]412// CHECK1: .omp.sections.case1:413// CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0414// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i64 4, i1 false)415// CHECK1-NEXT: br label [[DOTOMP_SECTIONS_EXIT]]416// CHECK1: .omp.sections.exit:417// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]418// CHECK1: omp.inner.for.inc:419// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 4420// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1421// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTOMP_SECTIONS_IV_]], align 4422// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]423// CHECK1: omp.inner.for.end:424// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8425// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4426// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP12]])427// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]]428// CHECK1-NEXT: [[ARRAY_BEGIN3:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0429// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN3]], i64 2430// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]431// CHECK1: arraydestroy.body:432// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]433// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1434// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]435// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN3]]436// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]]437// CHECK1: arraydestroy.done4:438// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8439// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4440// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB2]], i32 [[TMP15]])441// CHECK1-NEXT: ret void442//443//444// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev445// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {446// CHECK1-NEXT: entry:447// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8448// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8449// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8450// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]451// CHECK1-NEXT: ret void452//453//454// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev455// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {456// CHECK1-NEXT: entry:457// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8458// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8459// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8460// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0461// CHECK1-NEXT: store i32 0, ptr [[F]], align 4462// CHECK1-NEXT: ret void463//464//465// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei466// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {467// CHECK1-NEXT: entry:468// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8469// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4470// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8471// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4472// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8473// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0474// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4475// CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4476// CHECK1-NEXT: ret void477//478//479// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev480// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {481// CHECK1-NEXT: entry:482// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8483// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8484// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8485// CHECK1-NEXT: ret void486//487//488// CHECK3-LABEL: define {{[^@]+}}@main489// CHECK3-SAME: () #[[ATTR0:[0-9]+]] {490// CHECK3-NEXT: entry:491// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4492// CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1493// CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4494// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])495// CHECK3-NEXT: ret i32 0496//497//498// CHECK4-LABEL: define {{[^@]+}}@main499// CHECK4-SAME: () #[[ATTR1:[0-9]+]] {500// CHECK4-NEXT: entry:501// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4502// CHECK4-NEXT: store i32 0, ptr [[RETVAL]], align 4503// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr getelementptr inbounds nuw ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr @__block_literal_global, i32 0, i32 3), align 8504// CHECK4-NEXT: call void [[TMP0]](ptr noundef @__block_literal_global)505// CHECK4-NEXT: ret i32 0506//507//508// CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke509// CHECK4-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] {510// CHECK4-NEXT: entry:511// CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8512// CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8513// CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8514// CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8515// CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3:[0-9]+]], i32 0, ptr @__main_block_invoke.omp_outlined)516// CHECK4-NEXT: ret void517//518//519// CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke.omp_outlined520// CHECK4-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {521// CHECK4-NEXT: entry:522// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8523// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8524// CHECK4-NEXT: [[DOTOMP_SECTIONS_LB_:%.*]] = alloca i32, align 4525// CHECK4-NEXT: [[DOTOMP_SECTIONS_UB_:%.*]] = alloca i32, align 4526// CHECK4-NEXT: [[DOTOMP_SECTIONS_ST_:%.*]] = alloca i32, align 4527// CHECK4-NEXT: [[DOTOMP_SECTIONS_IL_:%.*]] = alloca i32, align 4528// CHECK4-NEXT: [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4529// CHECK4-NEXT: [[G:%.*]] = alloca double, align 8530// CHECK4-NEXT: [[SIVAR:%.*]] = alloca i32, align 4531// CHECK4-NEXT: [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, double, i32 }>, align 8532// CHECK4-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8533// CHECK4-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8534// CHECK4-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_LB_]], align 4535// CHECK4-NEXT: store i32 1, ptr [[DOTOMP_SECTIONS_UB_]], align 4536// CHECK4-NEXT: store i32 1, ptr [[DOTOMP_SECTIONS_ST_]], align 4537// CHECK4-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_IL_]], align 4538// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8539// CHECK4-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4540// CHECK4-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_SECTIONS_IL_]], ptr [[DOTOMP_SECTIONS_LB_]], ptr [[DOTOMP_SECTIONS_UB_]], ptr [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1)541// CHECK4-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_UB_]], align 4542// CHECK4-NEXT: [[TMP3:%.*]] = icmp slt i32 [[TMP2]], 1543// CHECK4-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], i32 [[TMP2]], i32 1544// CHECK4-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_SECTIONS_UB_]], align 4545// CHECK4-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_LB_]], align 4546// CHECK4-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_SECTIONS_IV_]], align 4547// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]548// CHECK4: omp.inner.for.cond:549// CHECK4-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 4550// CHECK4-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_UB_]], align 4551// CHECK4-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]552// CHECK4-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]553// CHECK4: omp.inner.for.body:554// CHECK4-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 4555// CHECK4-NEXT: switch i32 [[TMP8]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [556// CHECK4-NEXT: i32 0, label [[DOTOMP_SECTIONS_CASE:%.*]]557// CHECK4-NEXT: i32 1, label [[DOTOMP_SECTIONS_CASE1:%.*]]558// CHECK4-NEXT: ]559// CHECK4: .omp.sections.case:560// CHECK4-NEXT: store double 1.000000e+00, ptr [[G]], align 8561// CHECK4-NEXT: store i32 111, ptr [[SIVAR]], align 4562// CHECK4-NEXT: br label [[DOTOMP_SECTIONS_EXIT]]563// CHECK4: .omp.sections.case1:564// CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK]], i32 0, i32 0565// CHECK4-NEXT: store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 8566// CHECK4-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK]], i32 0, i32 1567// CHECK4-NEXT: store i32 1073741824, ptr [[BLOCK_FLAGS]], align 8568// CHECK4-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK]], i32 0, i32 2569// CHECK4-NEXT: store i32 0, ptr [[BLOCK_RESERVED]], align 4570// CHECK4-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK]], i32 0, i32 3571// CHECK4-NEXT: store ptr @_block_invoke, ptr [[BLOCK_INVOKE]], align 8572// CHECK4-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK]], i32 0, i32 4573// CHECK4-NEXT: store ptr @__block_descriptor_tmp.1, ptr [[BLOCK_DESCRIPTOR]], align 8574// CHECK4-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK]], i32 0, i32 5575// CHECK4-NEXT: [[TMP9:%.*]] = load volatile double, ptr [[G]], align 8576// CHECK4-NEXT: store volatile double [[TMP9]], ptr [[BLOCK_CAPTURED]], align 8577// CHECK4-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK]], i32 0, i32 6578// CHECK4-NEXT: [[TMP10:%.*]] = load i32, ptr [[SIVAR]], align 4579// CHECK4-NEXT: store i32 [[TMP10]], ptr [[BLOCK_CAPTURED2]], align 8580// CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3581// CHECK4-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8582// CHECK4-NEXT: call void [[TMP12]](ptr noundef [[BLOCK]])583// CHECK4-NEXT: br label [[DOTOMP_SECTIONS_EXIT]]584// CHECK4: .omp.sections.exit:585// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]586// CHECK4: omp.inner.for.inc:587// CHECK4-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 4588// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1589// CHECK4-NEXT: store i32 [[INC]], ptr [[DOTOMP_SECTIONS_IV_]], align 4590// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]]591// CHECK4: omp.inner.for.end:592// CHECK4-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])593// CHECK4-NEXT: call void @__kmpc_barrier(ptr @[[GLOB2:[0-9]+]], i32 [[TMP1]])594// CHECK4-NEXT: ret void595//596//597// CHECK4-LABEL: define {{[^@]+}}@_block_invoke598// CHECK4-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] {599// CHECK4-NEXT: entry:600// CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8601// CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8602// CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8603// CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8604// CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 5605// CHECK4-NEXT: store double 2.000000e+00, ptr [[BLOCK_CAPTURE_ADDR]], align 8606// CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 6607// CHECK4-NEXT: store i32 222, ptr [[BLOCK_CAPTURE_ADDR1]], align 8608// CHECK4-NEXT: ret void609//610