972 lines · cpp
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _2// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s4// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK36// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK47 8// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"9// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s10// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"11// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"12// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"13// expected-no-diagnostics14#ifndef HEADER15#define HEADER16 17struct St {18 int a, b;19 St() : a(0), b(0) {}20 St(const St &st) : a(st.a + st.b), b(0) {}21 ~St() {}22};23 24volatile int g = 1212;25 26template <class T>27struct S {28 T f;29 S(T a) : f(a + g) {}30 S() : f(g) {}31 S(const S &s, St t = St()) : f(s.f + t.a) {}32 operator T() { return T(); }33 ~S() {}34};35 36 37template <typename T>38T tmain() {39 S<T> test;40 T t_var = T();41 T vec[] = {1, 2};42 S<T> s_arr[] = {1, 2};43 S<T> var(3);44#pragma omp parallel45#pragma omp single firstprivate(t_var, vec, s_arr, var)46 {47 vec[0] = t_var;48 s_arr[0] = var;49 }50 return T();51}52 53S<float> test;54int t_var = 333;55int vec[] = {1, 2};56S<float> s_arr[] = {1, 2};57S<float> var(3);58 59int main() {60 static int sivar;61#ifdef LAMBDA62 [&]() {63#pragma omp parallel64#pragma omp single firstprivate(g, sivar)65 {66 g = 1;67 sivar = 17;68 [&]() {69 g = 2;70 sivar = 31;71 }();72 }73 }();74 return 0;75#elif defined(BLOCKS)76 ^{77#pragma omp parallel78#pragma omp single firstprivate(g, sivar)79 {80 g = 1;81 sivar = 37;82 ^{83 g = 2;84 sivar = 31;85 }();86 }87 }();88 return 0;89#else90#pragma omp single firstprivate(t_var, vec, s_arr, var, sivar) nowait91 {92 {93 vec[0] = t_var;94 s_arr[0] = var;95 sivar = 41;96 }97 }98 return tmain<int>();99#endif100}101 102 103// firstprivate t_var(t_var)104 105// firstprivate vec(vec)106 107// firstprivate s_arr(s_arr)108 109// firstprivate var(var)110 111// firstprivate isvar112// CHEC: [[SIVAR_VAL:%.+]] = load i{{[0-9]+}}, iptr [[SIVAR]],113// CHEC: store i{{[0-9]+}} [[SIVAR_VAL]], iptr [[SIVAR_PRIV]],114 115// ~(firstprivate var), ~(firstprivate s_arr)116 117 118 119 120 121 122 123// firstprivate t_var(t_var)124 125// firstprivate vec(vec)126 127// firstprivate s_arr(s_arr)128 129// firstprivate var(var)130 131// ~(firstprivate var), ~(firstprivate s_arr)132 133 134#endif135 136// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init137// CHECK1-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" {138// CHECK1-NEXT: entry:139// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr nonnull align 4 dereferenceable(4) @test)140// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]141// CHECK1-NEXT: ret void142//143//144// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev145// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 {146// CHECK1-NEXT: entry:147// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8148// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8149// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8150// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]])151// CHECK1-NEXT: ret void152//153//154// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev155// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {156// CHECK1-NEXT: entry:157// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8158// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8159// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8160// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]161// CHECK1-NEXT: ret void162//163//164// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev165// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {166// CHECK1-NEXT: entry:167// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8168// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8169// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8170// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0171// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4172// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float173// CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4174// CHECK1-NEXT: ret void175//176//177// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev178// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {179// CHECK1-NEXT: entry:180// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8181// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8182// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8183// CHECK1-NEXT: ret void184//185//186// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1187// CHECK1-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {188// CHECK1-NEXT: entry:189// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) @s_arr, float 1.000000e+00)190// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float 2.000000e+00)191// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]192// CHECK1-NEXT: ret void193//194//195// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef196// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {197// CHECK1-NEXT: entry:198// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8199// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4200// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8201// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4202// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8203// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4204// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])205// CHECK1-NEXT: ret void206//207//208// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor209// CHECK1-SAME: (ptr [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {210// CHECK1-NEXT: entry:211// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8212// CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8213// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]214// CHECK1: arraydestroy.body:215// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]216// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1217// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]218// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr219// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]220// CHECK1: arraydestroy.done1:221// CHECK1-NEXT: ret void222//223//224// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef225// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {226// CHECK1-NEXT: entry:227// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8228// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4229// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8230// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4231// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8232// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0233// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4234// CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4235// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float236// CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]237// CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4238// CHECK1-NEXT: ret void239//240//241// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2242// CHECK1-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {243// CHECK1-NEXT: entry:244// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)245// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]246// CHECK1-NEXT: ret void247//248//249// CHECK1-LABEL: define {{[^@]+}}@main250// CHECK1-SAME: () #[[ATTR3:[0-9]+]] {251// CHECK1-NEXT: entry:252// CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4253// CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4254// CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4255// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4256// CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4257// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4258// CHECK1-NEXT: [[AGG_TMP2:%.*]] = alloca [[STRUCT_ST]], align 4259// CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4260// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])261// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4262// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB1]], i32 [[TMP0]])263// CHECK1-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0264// CHECK1-NEXT: br i1 [[TMP2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]265// CHECK1: omp_if.then:266// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr @t_var, align 4267// CHECK1-NEXT: store i32 [[TMP3]], ptr [[T_VAR]], align 4268// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @vec, i64 8, i1 false)269// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0270// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2271// CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP4]]272// CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]273// CHECK1: omp.arraycpy.body:274// CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ @s_arr, [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]275// CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]276// CHECK1-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]])277// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr [[AGG_TMP]])278// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]279// CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1280// CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1281// CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP4]]282// CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]]283// CHECK1: omp.arraycpy.done1:284// CHECK1-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP2]])285// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR]], ptr nonnull align 4 dereferenceable(4) @var, ptr [[AGG_TMP2]])286// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP2]]) #[[ATTR2]]287// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4288// CHECK1-NEXT: store i32 [[TMP5]], ptr [[SIVAR]], align 4289// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[T_VAR]], align 4290// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0291// CHECK1-NEXT: store i32 [[TMP6]], ptr [[ARRAYIDX]], align 4292// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0293// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[VAR]], i64 4, i1 false)294// CHECK1-NEXT: store i32 41, ptr [[SIVAR]], align 4295// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]296// CHECK1-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0297// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN4]], i64 2298// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]299// CHECK1: arraydestroy.body:300// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP7]], [[OMP_ARRAYCPY_DONE1]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]301// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1302// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]303// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]]304// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]]305// CHECK1: arraydestroy.done5:306// CHECK1-NEXT: call void @__kmpc_end_single(ptr @[[GLOB1]], i32 [[TMP0]])307// CHECK1-NEXT: br label [[OMP_IF_END]]308// CHECK1: omp_if.end:309// CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v()310// CHECK1-NEXT: ret i32 [[CALL]]311//312//313// CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev314// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {315// CHECK1-NEXT: entry:316// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8317// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8318// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8319// CHECK1-NEXT: call void @_ZN2StC2Ev(ptr nonnull align 4 dereferenceable(8) [[THIS1]])320// CHECK1-NEXT: ret void321//322//323// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St324// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {325// CHECK1-NEXT: entry:326// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8327// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8328// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8329// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8330// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8331// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8332// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8333// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8334// CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]], ptr [[T]])335// CHECK1-NEXT: ret void336//337//338// CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev339// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {340// CHECK1-NEXT: entry:341// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8342// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8343// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8344// CHECK1-NEXT: call void @_ZN2StD2Ev(ptr nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]]345// CHECK1-NEXT: ret void346//347//348// CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v349// CHECK1-SAME: () #[[ATTR1]] {350// CHECK1-NEXT: entry:351// CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4352// CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4353// CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4354// CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4355// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4356// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4357// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]])358// CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4359// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)360// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[S_ARR]], i32 1)361// CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1362// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2)363// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[VAR]], i32 3)364// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @_Z5tmainIiET_v.omp_outlined, ptr [[T_VAR]], ptr [[VEC]], ptr [[S_ARR]], ptr [[VAR]])365// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4366// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]367// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0368// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2369// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]370// CHECK1: arraydestroy.body:371// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP0]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]372// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1373// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]374// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]375// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]376// CHECK1: arraydestroy.done1:377// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]378// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4379// CHECK1-NEXT: ret i32 [[TMP1]]380//381//382// CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev383// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {384// CHECK1-NEXT: entry:385// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8386// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8387// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8388// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0389// CHECK1-NEXT: store i32 0, ptr [[A]], align 4390// CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1391// CHECK1-NEXT: store i32 0, ptr [[B]], align 4392// CHECK1-NEXT: ret void393//394//395// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St396// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {397// CHECK1-NEXT: entry:398// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8399// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8400// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8401// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8402// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8403// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8404// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8405// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0406// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]]407// CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0408// CHECK1-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4409// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0410// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4411// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float412// CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]413// CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4414// CHECK1-NEXT: ret void415//416//417// CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev418// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {419// CHECK1-NEXT: entry:420// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8421// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8422// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8423// CHECK1-NEXT: ret void424//425//426// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev427// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {428// CHECK1-NEXT: entry:429// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8430// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8431// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8432// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]])433// CHECK1-NEXT: ret void434//435//436// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei437// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {438// CHECK1-NEXT: entry:439// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8440// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4441// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8442// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4443// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8444// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4445// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]])446// CHECK1-NEXT: ret void447//448//449// CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v.omp_outlined450// CHECK1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR6:[0-9]+]] {451// CHECK1-NEXT: entry:452// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8453// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8454// CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 8455// CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8456// CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8457// CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8458// CHECK1-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4459// CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4460// CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4461// CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4462// CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4463// CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4464// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8465// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8466// CHECK1-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8467// CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8468// CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8469// CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8470// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]]471// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META3]], !align [[META4]]472// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]]473// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]]474// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8475// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4476// CHECK1-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB1]], i32 [[TMP5]])477// CHECK1-NEXT: [[TMP7:%.*]] = icmp ne i32 [[TMP6]], 0478// CHECK1-NEXT: br i1 [[TMP7]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]479// CHECK1: omp_if.then:480// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP0]], align 4481// CHECK1-NEXT: store i32 [[TMP8]], ptr [[T_VAR1]], align 4482// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC2]], ptr align 4 [[TMP1]], i64 8, i1 false)483// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0484// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2485// CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP9]]486// CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]487// CHECK1: omp.arraycpy.body:488// CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]489// CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]490// CHECK1-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]])491// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr [[AGG_TMP]])492// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]493// CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1494// CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1495// CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP9]]496// CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]497// CHECK1: omp.arraycpy.done4:498// CHECK1-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP6]])499// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR5]], ptr nonnull align 4 dereferenceable(4) [[TMP3]], ptr [[AGG_TMP6]])500// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]501// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR1]], align 4502// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i64 0, i64 0503// CHECK1-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4504// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i64 0, i64 0505// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[VAR5]], i64 4, i1 false)506// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]507// CHECK1-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0508// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN8]], i64 2509// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]510// CHECK1: arraydestroy.body:511// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP11]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]512// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1513// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]514// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]]515// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]]516// CHECK1: arraydestroy.done9:517// CHECK1-NEXT: call void @__kmpc_end_single(ptr @[[GLOB1]], i32 [[TMP5]])518// CHECK1-NEXT: br label [[OMP_IF_END]]519// CHECK1: omp_if.end:520// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB2:[0-9]+]], i32 [[TMP5]])521// CHECK1-NEXT: ret void522//523//524// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St525// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {526// CHECK1-NEXT: entry:527// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8528// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8529// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8530// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8531// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8532// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8533// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8534// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8535// CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]], ptr [[T]])536// CHECK1-NEXT: ret void537//538//539// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev540// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {541// CHECK1-NEXT: entry:542// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8543// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8544// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8545// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]546// CHECK1-NEXT: ret void547//548//549// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev550// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {551// CHECK1-NEXT: entry:552// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8553// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8554// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8555// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0556// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4557// CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4558// CHECK1-NEXT: ret void559//560//561// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei562// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {563// CHECK1-NEXT: entry:564// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8565// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4566// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8567// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4568// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8569// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0570// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4571// CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4572// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]573// CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4574// CHECK1-NEXT: ret void575//576//577// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St578// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {579// CHECK1-NEXT: entry:580// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8581// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8582// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8583// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8584// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8585// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8586// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8587// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0588// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8, !nonnull [[META3]], !align [[META4]]589// CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0590// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4591// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0592// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4593// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]594// CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4595// CHECK1-NEXT: ret void596//597//598// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev599// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {600// CHECK1-NEXT: entry:601// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8602// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8603// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8604// CHECK1-NEXT: ret void605//606//607// CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_single_firstprivate_codegen.cpp608// CHECK1-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {609// CHECK1-NEXT: entry:610// CHECK1-NEXT: call void @__cxx_global_var_init()611// CHECK1-NEXT: call void @__cxx_global_var_init.1()612// CHECK1-NEXT: call void @__cxx_global_var_init.2()613// CHECK1-NEXT: ret void614//615//616// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init617// CHECK3-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" {618// CHECK3-NEXT: entry:619// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr nonnull align 4 dereferenceable(4) @test)620// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]621// CHECK3-NEXT: ret void622//623//624// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev625// CHECK3-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 {626// CHECK3-NEXT: entry:627// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8628// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8629// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8630// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]])631// CHECK3-NEXT: ret void632//633//634// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev635// CHECK3-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {636// CHECK3-NEXT: entry:637// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8638// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8639// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8640// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]641// CHECK3-NEXT: ret void642//643//644// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev645// CHECK3-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {646// CHECK3-NEXT: entry:647// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8648// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8649// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8650// CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0651// CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4652// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float653// CHECK3-NEXT: store float [[CONV]], ptr [[F]], align 4654// CHECK3-NEXT: ret void655//656//657// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev658// CHECK3-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {659// CHECK3-NEXT: entry:660// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8661// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8662// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8663// CHECK3-NEXT: ret void664//665//666// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1667// CHECK3-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {668// CHECK3-NEXT: entry:669// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) @s_arr, float 1.000000e+00)670// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float 2.000000e+00)671// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]672// CHECK3-NEXT: ret void673//674//675// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef676// CHECK3-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {677// CHECK3-NEXT: entry:678// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8679// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4680// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8681// CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4682// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8683// CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4684// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(ptr nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])685// CHECK3-NEXT: ret void686//687//688// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor689// CHECK3-SAME: (ptr [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {690// CHECK3-NEXT: entry:691// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8692// CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8693// CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]694// CHECK3: arraydestroy.body:695// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]696// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1697// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]698// CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr699// CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]700// CHECK3: arraydestroy.done1:701// CHECK3-NEXT: ret void702//703//704// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef705// CHECK3-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {706// CHECK3-NEXT: entry:707// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8708// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4709// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8710// CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4711// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8712// CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0713// CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4714// CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4715// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float716// CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]717// CHECK3-NEXT: store float [[ADD]], ptr [[F]], align 4718// CHECK3-NEXT: ret void719//720//721// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2722// CHECK3-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {723// CHECK3-NEXT: entry:724// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)725// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]726// CHECK3-NEXT: ret void727//728//729// CHECK3-LABEL: define {{[^@]+}}@main730// CHECK3-SAME: () #[[ATTR3:[0-9]+]] {731// CHECK3-NEXT: entry:732// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4733// CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8734// CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4735// CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0736// CHECK3-NEXT: store ptr @_ZZ4mainE5sivar, ptr [[TMP0]], align 8737// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr nonnull align 8 dereferenceable(8) [[REF_TMP]])738// CHECK3-NEXT: ret i32 0739//740//741// CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_single_firstprivate_codegen.cpp742// CHECK3-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {743// CHECK3-NEXT: entry:744// CHECK3-NEXT: call void @__cxx_global_var_init()745// CHECK3-NEXT: call void @__cxx_global_var_init.1()746// CHECK3-NEXT: call void @__cxx_global_var_init.2()747// CHECK3-NEXT: ret void748//749//750// CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init751// CHECK4-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" {752// CHECK4-NEXT: entry:753// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(ptr nonnull align 4 dereferenceable(4) @test)754// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]755// CHECK4-NEXT: ret void756//757//758// CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev759// CHECK4-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 {760// CHECK4-NEXT: entry:761// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8762// CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8763// CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8764// CHECK4-NEXT: call void @_ZN1SIfEC2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]])765// CHECK4-NEXT: ret void766//767//768// CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev769// CHECK4-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {770// CHECK4-NEXT: entry:771// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8772// CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8773// CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8774// CHECK4-NEXT: call void @_ZN1SIfED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]775// CHECK4-NEXT: ret void776//777//778// CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev779// CHECK4-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {780// CHECK4-NEXT: entry:781// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8782// CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8783// CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8784// CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0785// CHECK4-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4786// CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float787// CHECK4-NEXT: store float [[CONV]], ptr [[F]], align 4788// CHECK4-NEXT: ret void789//790//791// CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev792// CHECK4-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {793// CHECK4-NEXT: entry:794// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8795// CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8796// CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8797// CHECK4-NEXT: ret void798//799//800// CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1801// CHECK4-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {802// CHECK4-NEXT: entry:803// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) @s_arr, float 1.000000e+00)804// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float 2.000000e+00)805// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]806// CHECK4-NEXT: ret void807//808//809// CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef810// CHECK4-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {811// CHECK4-NEXT: entry:812// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8813// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4814// CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8815// CHECK4-NEXT: store float [[A]], ptr [[A_ADDR]], align 4816// CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8817// CHECK4-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4818// CHECK4-NEXT: call void @_ZN1SIfEC2Ef(ptr nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])819// CHECK4-NEXT: ret void820//821//822// CHECK4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor823// CHECK4-SAME: (ptr [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {824// CHECK4-NEXT: entry:825// CHECK4-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8826// CHECK4-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8827// CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]828// CHECK4: arraydestroy.body:829// CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]830// CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1831// CHECK4-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]832// CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr833// CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]834// CHECK4: arraydestroy.done1:835// CHECK4-NEXT: ret void836//837//838// CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef839// CHECK4-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {840// CHECK4-NEXT: entry:841// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8842// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4843// CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8844// CHECK4-NEXT: store float [[A]], ptr [[A_ADDR]], align 4845// CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8846// CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0847// CHECK4-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4848// CHECK4-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4849// CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float850// CHECK4-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]851// CHECK4-NEXT: store float [[ADD]], ptr [[F]], align 4852// CHECK4-NEXT: ret void853//854//855// CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2856// CHECK4-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {857// CHECK4-NEXT: entry:858// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)859// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]860// CHECK4-NEXT: ret void861//862//863// CHECK4-LABEL: define {{[^@]+}}@main864// CHECK4-SAME: () #[[ATTR3:[0-9]+]] {865// CHECK4-NEXT: entry:866// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4867// CHECK4-NEXT: [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, i32 }>, align 8868// CHECK4-NEXT: store i32 0, ptr [[RETVAL]], align 4869// CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 0870// CHECK4-NEXT: store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 8871// CHECK4-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 1872// CHECK4-NEXT: store i32 1073741824, ptr [[BLOCK_FLAGS]], align 8873// CHECK4-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 2874// CHECK4-NEXT: store i32 0, ptr [[BLOCK_RESERVED]], align 4875// CHECK4-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 3876// CHECK4-NEXT: store ptr @__main_block_invoke, ptr [[BLOCK_INVOKE]], align 8877// CHECK4-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 4878// CHECK4-NEXT: store ptr @__block_descriptor_tmp.3, ptr [[BLOCK_DESCRIPTOR]], align 8879// CHECK4-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 5880// CHECK4-NEXT: [[TMP0:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4881// CHECK4-NEXT: store i32 [[TMP0]], ptr [[BLOCK_CAPTURED]], align 8882// CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3883// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8884// CHECK4-NEXT: call void [[TMP2]](ptr [[BLOCK]])885// CHECK4-NEXT: ret i32 0886//887//888// CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke889// CHECK4-SAME: (ptr [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR4:[0-9]+]] {890// CHECK4-NEXT: entry:891// CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8892// CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8893// CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8894// CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8895// CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 1, ptr @__main_block_invoke.omp_outlined, ptr @_ZZ4mainE5sivar)896// CHECK4-NEXT: ret void897//898//899// CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke.omp_outlined900// CHECK4-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] {901// CHECK4-NEXT: entry:902// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8903// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8904// CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 8905// CHECK4-NEXT: [[G:%.*]] = alloca i32, align 4906// CHECK4-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4907// CHECK4-NEXT: [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, align 8908// CHECK4-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8909// CHECK4-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8910// CHECK4-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8911// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]]912// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8913// CHECK4-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4914// CHECK4-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB1]], i32 [[TMP2]])915// CHECK4-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0916// CHECK4-NEXT: br i1 [[TMP4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]917// CHECK4: omp_if.then:918// CHECK4-NEXT: [[TMP5:%.*]] = load volatile i32, ptr @g, align 4919// CHECK4-NEXT: store i32 [[TMP5]], ptr [[G]], align 4920// CHECK4-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP0]], align 4921// CHECK4-NEXT: store i32 [[TMP6]], ptr [[SIVAR1]], align 4922// CHECK4-NEXT: store i32 1, ptr [[G]], align 4923// CHECK4-NEXT: store i32 37, ptr [[SIVAR1]], align 4924// CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 0925// CHECK4-NEXT: store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 8926// CHECK4-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 1927// CHECK4-NEXT: store i32 1073741824, ptr [[BLOCK_FLAGS]], align 8928// CHECK4-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 2929// CHECK4-NEXT: store i32 0, ptr [[BLOCK_RESERVED]], align 4930// CHECK4-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 3931// CHECK4-NEXT: store ptr @var_block_invoke, ptr [[BLOCK_INVOKE]], align 8932// CHECK4-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 4933// CHECK4-NEXT: store ptr @__block_descriptor_tmp, ptr [[BLOCK_DESCRIPTOR]], align 8934// CHECK4-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 5935// CHECK4-NEXT: [[TMP7:%.*]] = load volatile i32, ptr [[G]], align 4936// CHECK4-NEXT: store volatile i32 [[TMP7]], ptr [[BLOCK_CAPTURED]], align 8937// CHECK4-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 6938// CHECK4-NEXT: [[TMP8:%.*]] = load i32, ptr [[SIVAR1]], align 4939// CHECK4-NEXT: store i32 [[TMP8]], ptr [[BLOCK_CAPTURED2]], align 4940// CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3941// CHECK4-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8942// CHECK4-NEXT: call void [[TMP10]](ptr [[BLOCK]])943// CHECK4-NEXT: call void @__kmpc_end_single(ptr @[[GLOB1]], i32 [[TMP2]])944// CHECK4-NEXT: br label [[OMP_IF_END]]945// CHECK4: omp_if.end:946// CHECK4-NEXT: call void @__kmpc_barrier(ptr @[[GLOB2:[0-9]+]], i32 [[TMP2]])947// CHECK4-NEXT: ret void948//949//950// CHECK4-LABEL: define {{[^@]+}}@var_block_invoke951// CHECK4-SAME: (ptr [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR4]] {952// CHECK4-NEXT: entry:953// CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8954// CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8955// CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8956// CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8957// CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 5958// CHECK4-NEXT: store i32 2, ptr [[BLOCK_CAPTURE_ADDR]], align 8959// CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 6960// CHECK4-NEXT: store i32 31, ptr [[BLOCK_CAPTURE_ADDR1]], align 4961// CHECK4-NEXT: ret void962//963//964// CHECK4-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_single_firstprivate_codegen.cpp965// CHECK4-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {966// CHECK4-NEXT: entry:967// CHECK4-NEXT: call void @__cxx_global_var_init()968// CHECK4-NEXT: call void @__cxx_global_var_init.1()969// CHECK4-NEXT: call void @__cxx_global_var_init.2()970// CHECK4-NEXT: ret void971//972