490 lines · cpp
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _2// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s4// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK36// RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK47 8// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"9// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s10// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"11// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"12// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"13// expected-no-diagnostics14#ifndef HEADER15#define HEADER16 17template <class T>18struct S {19 T f;20 S(T a) : f(a) {}21 S() : f() {}22 operator T() { return T(); }23 ~S() {}24};25 26volatile double g;27 28template <typename T>29T tmain() {30 S<T> test;31 T t_var = T();32 T vec[] = {1, 2};33 S<T> s_arr[] = {1, 2};34 S<T> var(3);35#pragma omp parallel36#pragma omp single private(t_var, vec, s_arr, s_arr, var, var)37 {38 vec[0] = t_var;39 s_arr[0] = var;40 }41 return T();42}43 44int main() {45 static int sivar;46#ifdef LAMBDA47 [&]() {48#pragma omp parallel49#pragma omp single private(g, sivar)50 {51 g = 1;52 sivar = 101;53 [&]() {54 g = 2;55 sivar = 211;56 }();57 }58 }();59 return 0;60#elif defined(BLOCKS)61 ^{62#pragma omp parallel63#pragma omp single private(g, sivar)64 {65 g = 1;66 sivar = 101;67 ^{68 g = 2;69 sivar = 203;70 }();71 }72 }();73 return 0;74#else75 S<float> test;76 int t_var = 0;77 int vec[] = {1, 2};78 S<float> s_arr[] = {1, 2};79 S<float> var(3);80#pragma omp parallel81#pragma omp single private(t_var, vec, s_arr, s_arr, var, var, sivar)82 {83 vec[0] = t_var;84 s_arr[0] = var;85 sivar = 303;86 }87 return tmain<int>();88#endif89}90 91 92#endif93 94// CHECK1-LABEL: define {{[^@]+}}@main95// CHECK1-SAME: () #[[ATTR0:[0-9]+]] {96// CHECK1-NEXT: entry:97// CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 498// CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 499// CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4100// CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4101// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4102// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4103// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4104// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])105// CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4106// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i64 8, i1 false)107// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], float noundef 1.000000e+00)108// CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i64 1109// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00)110// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]], float noundef 3.000000e+00)111// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 0, ptr @main.omp_outlined)112// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()113// CHECK1-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4114// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]]115// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0116// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2117// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]118// CHECK1: arraydestroy.body:119// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP0]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]120// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1121// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]122// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]123// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]124// CHECK1: arraydestroy.done1:125// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]]126// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4127// CHECK1-NEXT: ret i32 [[TMP1]]128//129//130// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev131// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {132// CHECK1-NEXT: entry:133// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8134// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8135// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8136// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])137// CHECK1-NEXT: ret void138//139//140// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef141// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {142// CHECK1-NEXT: entry:143// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8144// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4145// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8146// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4147// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8148// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4149// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])150// CHECK1-NEXT: ret void151//152//153// CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined154// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {155// CHECK1-NEXT: entry:156// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8157// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8158// CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4159// CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4160// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4161// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4162// CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4163// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8164// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8165// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8166// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4167// CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB1]], i32 [[TMP1]])168// CHECK1-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0169// CHECK1-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]170// CHECK1: omp_if.then:171// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0172// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2173// CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]174// CHECK1: arrayctor.loop:175// CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[OMP_IF_THEN]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]176// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])177// CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1178// CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]179// CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]180// CHECK1: arrayctor.cont:181// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])182// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR]], align 4183// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0184// CHECK1-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4185// CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0186// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX1]], ptr align 4 [[VAR]], i64 4, i1 false)187// CHECK1-NEXT: store i32 303, ptr [[SIVAR]], align 4188// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]]189// CHECK1-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0190// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN2]], i64 2191// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]192// CHECK1: arraydestroy.body:193// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]194// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1195// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]196// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]]197// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]]198// CHECK1: arraydestroy.done3:199// CHECK1-NEXT: call void @__kmpc_end_single(ptr @[[GLOB1]], i32 [[TMP1]])200// CHECK1-NEXT: br label [[OMP_IF_END]]201// CHECK1: omp_if.end:202// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB2:[0-9]+]], i32 [[TMP1]])203// CHECK1-NEXT: ret void204//205//206// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev207// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {208// CHECK1-NEXT: entry:209// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8210// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8211// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8212// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]]213// CHECK1-NEXT: ret void214//215//216// CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v217// CHECK1-SAME: () #[[ATTR1]] comdat {218// CHECK1-NEXT: entry:219// CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4220// CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4221// CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4222// CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4223// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4224// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4225// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])226// CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4227// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)228// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1)229// CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1230// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)231// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]], i32 noundef 3)232// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @_Z5tmainIiET_v.omp_outlined)233// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4234// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]]235// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0236// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2237// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]238// CHECK1: arraydestroy.body:239// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP0]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]240// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1241// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]242// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]243// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]244// CHECK1: arraydestroy.done1:245// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]]246// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4247// CHECK1-NEXT: ret i32 [[TMP1]]248//249//250// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev251// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {252// CHECK1-NEXT: entry:253// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8254// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8255// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8256// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0257// CHECK1-NEXT: store float 0.000000e+00, ptr [[F]], align 4258// CHECK1-NEXT: ret void259//260//261// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef262// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {263// CHECK1-NEXT: entry:264// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8265// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4266// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8267// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4268// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8269// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0270// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4271// CHECK1-NEXT: store float [[TMP0]], ptr [[F]], align 4272// CHECK1-NEXT: ret void273//274//275// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev276// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {277// CHECK1-NEXT: entry:278// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8279// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8280// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8281// CHECK1-NEXT: ret void282//283//284// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev285// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {286// CHECK1-NEXT: entry:287// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8288// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8289// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8290// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])291// CHECK1-NEXT: ret void292//293//294// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei295// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {296// CHECK1-NEXT: entry:297// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8298// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4299// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8300// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4301// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8302// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4303// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])304// CHECK1-NEXT: ret void305//306//307// CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v.omp_outlined308// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {309// CHECK1-NEXT: entry:310// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8311// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8312// CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4313// CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4314// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4315// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4316// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8317// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8318// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8319// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4320// CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB1]], i32 [[TMP1]])321// CHECK1-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0322// CHECK1-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]323// CHECK1: omp_if.then:324// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0325// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2326// CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]327// CHECK1: arrayctor.loop:328// CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[OMP_IF_THEN]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]329// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])330// CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1331// CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]332// CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]333// CHECK1: arrayctor.cont:334// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])335// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR]], align 4336// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0337// CHECK1-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4338// CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0339// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX1]], ptr align 4 [[VAR]], i64 4, i1 false)340// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]]341// CHECK1-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0342// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN2]], i64 2343// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]344// CHECK1: arraydestroy.body:345// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]346// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1347// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]348// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]]349// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]]350// CHECK1: arraydestroy.done3:351// CHECK1-NEXT: call void @__kmpc_end_single(ptr @[[GLOB1]], i32 [[TMP1]])352// CHECK1-NEXT: br label [[OMP_IF_END]]353// CHECK1: omp_if.end:354// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB2]], i32 [[TMP1]])355// CHECK1-NEXT: ret void356//357//358// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev359// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {360// CHECK1-NEXT: entry:361// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8362// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8363// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8364// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]]365// CHECK1-NEXT: ret void366//367//368// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev369// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {370// CHECK1-NEXT: entry:371// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8372// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8373// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8374// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0375// CHECK1-NEXT: store i32 0, ptr [[F]], align 4376// CHECK1-NEXT: ret void377//378//379// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei380// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {381// CHECK1-NEXT: entry:382// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8383// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4384// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8385// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4386// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8387// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0388// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4389// CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4390// CHECK1-NEXT: ret void391//392//393// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev394// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {395// CHECK1-NEXT: entry:396// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8397// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8398// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8399// CHECK1-NEXT: ret void400//401//402// CHECK3-LABEL: define {{[^@]+}}@main403// CHECK3-SAME: () #[[ATTR0:[0-9]+]] {404// CHECK3-NEXT: entry:405// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4406// CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1407// CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4408// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])409// CHECK3-NEXT: ret i32 0410//411//412// CHECK4-LABEL: define {{[^@]+}}@main413// CHECK4-SAME: () #[[ATTR1:[0-9]+]] {414// CHECK4-NEXT: entry:415// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4416// CHECK4-NEXT: store i32 0, ptr [[RETVAL]], align 4417// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr getelementptr inbounds nuw ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr @__block_literal_global, i32 0, i32 3), align 8418// CHECK4-NEXT: call void [[TMP0]](ptr noundef @__block_literal_global)419// CHECK4-NEXT: ret i32 0420//421//422// CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke423// CHECK4-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] {424// CHECK4-NEXT: entry:425// CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8426// CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8427// CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8428// CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8429// CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 0, ptr @__main_block_invoke.omp_outlined)430// CHECK4-NEXT: ret void431//432//433// CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke.omp_outlined434// CHECK4-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {435// CHECK4-NEXT: entry:436// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8437// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8438// CHECK4-NEXT: [[G:%.*]] = alloca double, align 8439// CHECK4-NEXT: [[SIVAR:%.*]] = alloca i32, align 4440// CHECK4-NEXT: [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, double, i32 }>, align 8441// CHECK4-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8442// CHECK4-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8443// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8444// CHECK4-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4445// CHECK4-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB1]], i32 [[TMP1]])446// CHECK4-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0447// CHECK4-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]448// CHECK4: omp_if.then:449// CHECK4-NEXT: store double 1.000000e+00, ptr [[G]], align 8450// CHECK4-NEXT: store i32 101, ptr [[SIVAR]], align 4451// CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK]], i32 0, i32 0452// CHECK4-NEXT: store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 8453// CHECK4-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK]], i32 0, i32 1454// CHECK4-NEXT: store i32 1073741824, ptr [[BLOCK_FLAGS]], align 8455// CHECK4-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK]], i32 0, i32 2456// CHECK4-NEXT: store i32 0, ptr [[BLOCK_RESERVED]], align 4457// CHECK4-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK]], i32 0, i32 3458// CHECK4-NEXT: store ptr @_block_invoke, ptr [[BLOCK_INVOKE]], align 8459// CHECK4-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK]], i32 0, i32 4460// CHECK4-NEXT: store ptr @__block_descriptor_tmp.1, ptr [[BLOCK_DESCRIPTOR]], align 8461// CHECK4-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK]], i32 0, i32 5462// CHECK4-NEXT: [[TMP4:%.*]] = load volatile double, ptr [[G]], align 8463// CHECK4-NEXT: store volatile double [[TMP4]], ptr [[BLOCK_CAPTURED]], align 8464// CHECK4-NEXT: [[BLOCK_CAPTURED1:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK]], i32 0, i32 6465// CHECK4-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR]], align 4466// CHECK4-NEXT: store i32 [[TMP5]], ptr [[BLOCK_CAPTURED1]], align 8467// CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3468// CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8469// CHECK4-NEXT: call void [[TMP7]](ptr noundef [[BLOCK]])470// CHECK4-NEXT: call void @__kmpc_end_single(ptr @[[GLOB1]], i32 [[TMP1]])471// CHECK4-NEXT: br label [[OMP_IF_END]]472// CHECK4: omp_if.end:473// CHECK4-NEXT: call void @__kmpc_barrier(ptr @[[GLOB2:[0-9]+]], i32 [[TMP1]])474// CHECK4-NEXT: ret void475//476//477// CHECK4-LABEL: define {{[^@]+}}@_block_invoke478// CHECK4-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] {479// CHECK4-NEXT: entry:480// CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8481// CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8482// CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8483// CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8484// CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 5485// CHECK4-NEXT: store double 2.000000e+00, ptr [[BLOCK_CAPTURE_ADDR]], align 8486// CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 6487// CHECK4-NEXT: store i32 203, ptr [[BLOCK_CAPTURE_ADDR1]], align 8488// CHECK4-NEXT: ret void489//490