2734 lines · cpp
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ --version 42// Check code generation3// RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -fclang-abi-compat=latest\4// RUN: -std=c++20 -fopenmp -fopenmp-version=60 -emit-llvm %s -o - \5// RUN: | FileCheck %s --check-prefix=CHECK16 7// Check same results after serialization round-trip8// RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -fclang-abi-compat=latest\9// RUN: -std=c++20 -fopenmp -fopenmp-version=60 -emit-pch -o %t %s10// RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -fclang-abi-compat=latest\11// RUN: -std=c++20 -fopenmp -fopenmp-version=60 -include-pch %t -emit-llvm %s -o - \12// RUN: | FileCheck %s --check-prefix=CHECK213// expected-no-diagnostics14 15#ifndef HEADER16#define HEADER17 18// placeholder for loop body code.19extern "C" void body(...) {}20 21 22struct S {23 int i;24 S() {25#pragma omp stripe sizes(5)26 for (i = 7; i < 17; i += 3)27 body(i);28 }29} s;30 31extern "C" void foo1(int start, int end, int step) {32 int i;33#pragma omp stripe sizes(5)34 for (i = start; i < end; i += step)35 body(i);36}37 38extern "C" void foo2(int start, int end, int step) {39#pragma omp stripe sizes(5,5)40 for (int i = 7; i < 17; i+=3)41 for (int j = 7; j < 17; j+=3)42 body(i,j);43}44 45extern "C" void foo3() {46#pragma omp for47#pragma omp stripe sizes(5,5)48 for (int i = 7; i < 17; i += 3)49 for (int j = 7; j < 17; j += 3)50 body(i, j);51}52 53extern "C" void foo4() {54#pragma omp for collapse(2)55 for (int k = 7; k < 17; k += 3)56#pragma omp stripe sizes(5,5)57 for (int i = 7; i < 17; i += 3)58 for (int j = 7; j < 17; j += 3)59 body(i, j);60}61 62 63extern "C" void foo5() {64#pragma omp for collapse(3)65#pragma omp stripe sizes(5)66 for (int i = 7; i < 17; i += 3)67 for (int j = 7; j < 17; j += 3)68 body(i, j);69}70 71 72extern "C" void foo6() {73#pragma omp parallel for74#pragma omp stripe sizes(5)75 for (int i = 7; i < 17; i += 3)76 body(i);77}78 79 80template<typename T, T Step, T Stripe>81void foo7(T start, T end) {82#pragma omp stripe sizes(Stripe)83 for (T i = start; i < end; i += Step)84 body(i);85}86 87extern "C" void tfoo7() {88 foo7<int,3,5>(0, 42);89}90 91 92extern "C" void foo8(int a) {93#pragma omp stripe sizes(a)94 for (int i = 7; i < 17; i += 3)95 body(i);96}97 98 99typedef struct { double array[12]; } data_t;100extern "C" void foo9(data_t data) {101#pragma omp stripe sizes(5)102 for (double v : data.array)103 body(v);104}105 106 107extern "C" void foo10(data_t data) {108#pragma omp stripe sizes(5)109 for (double c = 42.0; double v : data.array)110 body(c, v);111}112 113 114#endif /* HEADER */115 116// CHECK1-LABEL: define dso_local void @body(117// CHECK1-SAME: ...) #[[ATTR0:[0-9]+]] {118// CHECK1-NEXT: entry:119// CHECK1-NEXT: ret void120//121//122// CHECK1-LABEL: define internal void @__cxx_global_var_init(123// CHECK1-SAME: ) #[[ATTR1:[0-9]+]] section ".text.startup" {124// CHECK1-NEXT: entry:125// CHECK1-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @s)126// CHECK1-NEXT: ret void127//128//129// CHECK1-LABEL: define linkonce_odr void @_ZN1SC1Ev(130// CHECK1-SAME: ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat align 2 {131// CHECK1-NEXT: entry:132// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8133// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8134// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8135// CHECK1-NEXT: call void @_ZN1SC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])136// CHECK1-NEXT: ret void137//138//139// CHECK1-LABEL: define linkonce_odr void @_ZN1SC2Ev(140// CHECK1-SAME: ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat align 2 {141// CHECK1-NEXT: entry:142// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8143// CHECK1-NEXT: [[I2:%.*]] = alloca ptr, align 8144// CHECK1-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 4145// CHECK1-NEXT: [[DOTSTRIPE_0_IV_I:%.*]] = alloca i32, align 4146// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8147// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8148// CHECK1-NEXT: [[I:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0149// CHECK1-NEXT: store i32 7, ptr [[I]], align 4150// CHECK1-NEXT: [[I3:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[THIS1]], i32 0, i32 0151// CHECK1-NEXT: store ptr [[I3]], ptr [[I2]], align 8152// CHECK1-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV_I]], align 4153// CHECK1-NEXT: br label [[FOR_COND:%.*]]154// CHECK1: for.cond:155// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4156// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 4157// CHECK1-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END12:%.*]]158// CHECK1: for.body:159// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4160// CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTSTRIPE_0_IV_I]], align 4161// CHECK1-NEXT: br label [[FOR_COND4:%.*]]162// CHECK1: for.cond4:163// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 4164// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4165// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 5166// CHECK1-NEXT: [[CMP5:%.*]] = icmp slt i32 4, [[ADD]]167// CHECK1-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]168// CHECK1: cond.true:169// CHECK1-NEXT: br label [[COND_END:%.*]]170// CHECK1: cond.false:171// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4172// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP4]], 5173// CHECK1-NEXT: br label [[COND_END]]174// CHECK1: cond.end:175// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 4, [[COND_TRUE]] ], [ [[ADD6]], [[COND_FALSE]] ]176// CHECK1-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP2]], [[COND]]177// CHECK1-NEXT: br i1 [[CMP7]], label [[FOR_BODY8:%.*]], label [[FOR_END:%.*]]178// CHECK1: for.body8:179// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 4180// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP5]], 3181// CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 7, [[MUL]]182// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[I2]], align 8183// CHECK1-NEXT: store i32 [[ADD9]], ptr [[TMP6]], align 4184// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[I2]], align 8185// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4186// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP8]])187// CHECK1-NEXT: br label [[FOR_INC:%.*]]188// CHECK1: for.inc:189// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 4190// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1191// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTSTRIPE_0_IV_I]], align 4192// CHECK1-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP3:![0-9]+]]193// CHECK1: for.end:194// CHECK1-NEXT: br label [[FOR_INC10:%.*]]195// CHECK1: for.inc10:196// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4197// CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP10]], 5198// CHECK1-NEXT: store i32 [[ADD11]], ptr [[DOTFLOOR_0_IV_I]], align 4199// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]200// CHECK1: for.end12:201// CHECK1-NEXT: ret void202//203//204// CHECK1-LABEL: define dso_local void @foo1(205// CHECK1-SAME: i32 noundef [[START:%.*]], i32 noundef [[END:%.*]], i32 noundef [[STEP:%.*]]) #[[ATTR0]] {206// CHECK1-NEXT: entry:207// CHECK1-NEXT: [[START_ADDR:%.*]] = alloca i32, align 4208// CHECK1-NEXT: [[END_ADDR:%.*]] = alloca i32, align 4209// CHECK1-NEXT: [[STEP_ADDR:%.*]] = alloca i32, align 4210// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4211// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4212// CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4213// CHECK1-NEXT: [[DOTNEW_STEP:%.*]] = alloca i32, align 4214// CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4215// CHECK1-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 4216// CHECK1-NEXT: [[DOTSTRIPE_0_IV_I:%.*]] = alloca i32, align 4217// CHECK1-NEXT: store i32 [[START]], ptr [[START_ADDR]], align 4218// CHECK1-NEXT: store i32 [[END]], ptr [[END_ADDR]], align 4219// CHECK1-NEXT: store i32 [[STEP]], ptr [[STEP_ADDR]], align 4220// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[START_ADDR]], align 4221// CHECK1-NEXT: store i32 [[TMP0]], ptr [[I]], align 4222// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[START_ADDR]], align 4223// CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4224// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[END_ADDR]], align 4225// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_1]], align 4226// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[STEP_ADDR]], align 4227// CHECK1-NEXT: store i32 [[TMP3]], ptr [[DOTNEW_STEP]], align 4228// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4229// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4230// CHECK1-NEXT: [[SUB:%.*]] = sub i32 [[TMP4]], [[TMP5]]231// CHECK1-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1232// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4233// CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], [[TMP6]]234// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4235// CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], [[TMP7]]236// CHECK1-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1237// CHECK1-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4238// CHECK1-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV_I]], align 4239// CHECK1-NEXT: br label [[FOR_COND:%.*]]240// CHECK1: for.cond:241// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4242// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4243// CHECK1-NEXT: [[ADD5:%.*]] = add i32 [[TMP9]], 1244// CHECK1-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP8]], [[ADD5]]245// CHECK1-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END17:%.*]]246// CHECK1: for.body:247// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4248// CHECK1-NEXT: store i32 [[TMP10]], ptr [[DOTSTRIPE_0_IV_I]], align 4249// CHECK1-NEXT: br label [[FOR_COND6:%.*]]250// CHECK1: for.cond6:251// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 4252// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4253// CHECK1-NEXT: [[ADD7:%.*]] = add i32 [[TMP12]], 1254// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4255// CHECK1-NEXT: [[ADD8:%.*]] = add i32 [[TMP13]], 5256// CHECK1-NEXT: [[CMP9:%.*]] = icmp ult i32 [[ADD7]], [[ADD8]]257// CHECK1-NEXT: br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]258// CHECK1: cond.true:259// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4260// CHECK1-NEXT: [[ADD10:%.*]] = add i32 [[TMP14]], 1261// CHECK1-NEXT: br label [[COND_END:%.*]]262// CHECK1: cond.false:263// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4264// CHECK1-NEXT: [[ADD11:%.*]] = add i32 [[TMP15]], 5265// CHECK1-NEXT: br label [[COND_END]]266// CHECK1: cond.end:267// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[ADD10]], [[COND_TRUE]] ], [ [[ADD11]], [[COND_FALSE]] ]268// CHECK1-NEXT: [[CMP12:%.*]] = icmp ult i32 [[TMP11]], [[COND]]269// CHECK1-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END:%.*]]270// CHECK1: for.body13:271// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4272// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 4273// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4274// CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP17]], [[TMP18]]275// CHECK1-NEXT: [[ADD14:%.*]] = add i32 [[TMP16]], [[MUL]]276// CHECK1-NEXT: store i32 [[ADD14]], ptr [[I]], align 4277// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4278// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP19]])279// CHECK1-NEXT: br label [[FOR_INC:%.*]]280// CHECK1: for.inc:281// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 4282// CHECK1-NEXT: [[INC:%.*]] = add i32 [[TMP20]], 1283// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTSTRIPE_0_IV_I]], align 4284// CHECK1-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP6:![0-9]+]]285// CHECK1: for.end:286// CHECK1-NEXT: br label [[FOR_INC15:%.*]]287// CHECK1: for.inc15:288// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4289// CHECK1-NEXT: [[ADD16:%.*]] = add i32 [[TMP21]], 5290// CHECK1-NEXT: store i32 [[ADD16]], ptr [[DOTFLOOR_0_IV_I]], align 4291// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]292// CHECK1: for.end17:293// CHECK1-NEXT: ret void294//295//296// CHECK1-LABEL: define dso_local void @foo2(297// CHECK1-SAME: i32 noundef [[START:%.*]], i32 noundef [[END:%.*]], i32 noundef [[STEP:%.*]]) #[[ATTR0]] {298// CHECK1-NEXT: entry:299// CHECK1-NEXT: [[START_ADDR:%.*]] = alloca i32, align 4300// CHECK1-NEXT: [[END_ADDR:%.*]] = alloca i32, align 4301// CHECK1-NEXT: [[STEP_ADDR:%.*]] = alloca i32, align 4302// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4303// CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4304// CHECK1-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 4305// CHECK1-NEXT: [[DOTFLOOR_1_IV_J:%.*]] = alloca i32, align 4306// CHECK1-NEXT: [[DOTSTRIPE_0_IV_I:%.*]] = alloca i32, align 4307// CHECK1-NEXT: [[DOTSTRIPE_1_IV_J:%.*]] = alloca i32, align 4308// CHECK1-NEXT: store i32 [[START]], ptr [[START_ADDR]], align 4309// CHECK1-NEXT: store i32 [[END]], ptr [[END_ADDR]], align 4310// CHECK1-NEXT: store i32 [[STEP]], ptr [[STEP_ADDR]], align 4311// CHECK1-NEXT: store i32 7, ptr [[I]], align 4312// CHECK1-NEXT: store i32 7, ptr [[J]], align 4313// CHECK1-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV_I]], align 4314// CHECK1-NEXT: br label [[FOR_COND:%.*]]315// CHECK1: for.cond:316// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4317// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 4318// CHECK1-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END30:%.*]]319// CHECK1: for.body:320// CHECK1-NEXT: store i32 0, ptr [[DOTFLOOR_1_IV_J]], align 4321// CHECK1-NEXT: br label [[FOR_COND1:%.*]]322// CHECK1: for.cond1:323// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4324// CHECK1-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 4325// CHECK1-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END27:%.*]]326// CHECK1: for.body3:327// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4328// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTSTRIPE_0_IV_I]], align 4329// CHECK1-NEXT: br label [[FOR_COND4:%.*]]330// CHECK1: for.cond4:331// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 4332// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4333// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], 5334// CHECK1-NEXT: [[CMP5:%.*]] = icmp slt i32 4, [[ADD]]335// CHECK1-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]336// CHECK1: cond.true:337// CHECK1-NEXT: br label [[COND_END:%.*]]338// CHECK1: cond.false:339// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4340// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP5]], 5341// CHECK1-NEXT: br label [[COND_END]]342// CHECK1: cond.end:343// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 4, [[COND_TRUE]] ], [ [[ADD6]], [[COND_FALSE]] ]344// CHECK1-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP3]], [[COND]]345// CHECK1-NEXT: br i1 [[CMP7]], label [[FOR_BODY8:%.*]], label [[FOR_END24:%.*]]346// CHECK1: for.body8:347// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 4348// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 3349// CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 7, [[MUL]]350// CHECK1-NEXT: store i32 [[ADD9]], ptr [[I]], align 4351// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4352// CHECK1-NEXT: store i32 [[TMP7]], ptr [[DOTSTRIPE_1_IV_J]], align 4353// CHECK1-NEXT: br label [[FOR_COND10:%.*]]354// CHECK1: for.cond10:355// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTSTRIPE_1_IV_J]], align 4356// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4357// CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP9]], 5358// CHECK1-NEXT: [[CMP12:%.*]] = icmp slt i32 4, [[ADD11]]359// CHECK1-NEXT: br i1 [[CMP12]], label [[COND_TRUE13:%.*]], label [[COND_FALSE14:%.*]]360// CHECK1: cond.true13:361// CHECK1-NEXT: br label [[COND_END16:%.*]]362// CHECK1: cond.false14:363// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4364// CHECK1-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP10]], 5365// CHECK1-NEXT: br label [[COND_END16]]366// CHECK1: cond.end16:367// CHECK1-NEXT: [[COND17:%.*]] = phi i32 [ 4, [[COND_TRUE13]] ], [ [[ADD15]], [[COND_FALSE14]] ]368// CHECK1-NEXT: [[CMP18:%.*]] = icmp slt i32 [[TMP8]], [[COND17]]369// CHECK1-NEXT: br i1 [[CMP18]], label [[FOR_BODY19:%.*]], label [[FOR_END:%.*]]370// CHECK1: for.body19:371// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTSTRIPE_1_IV_J]], align 4372// CHECK1-NEXT: [[MUL20:%.*]] = mul nsw i32 [[TMP11]], 3373// CHECK1-NEXT: [[ADD21:%.*]] = add nsw i32 7, [[MUL20]]374// CHECK1-NEXT: store i32 [[ADD21]], ptr [[J]], align 4375// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4376// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[J]], align 4377// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP12]], i32 noundef [[TMP13]])378// CHECK1-NEXT: br label [[FOR_INC:%.*]]379// CHECK1: for.inc:380// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTSTRIPE_1_IV_J]], align 4381// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1382// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTSTRIPE_1_IV_J]], align 4383// CHECK1-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP8:![0-9]+]]384// CHECK1: for.end:385// CHECK1-NEXT: br label [[FOR_INC22:%.*]]386// CHECK1: for.inc22:387// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 4388// CHECK1-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP15]], 1389// CHECK1-NEXT: store i32 [[INC23]], ptr [[DOTSTRIPE_0_IV_I]], align 4390// CHECK1-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP9:![0-9]+]]391// CHECK1: for.end24:392// CHECK1-NEXT: br label [[FOR_INC25:%.*]]393// CHECK1: for.inc25:394// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4395// CHECK1-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP16]], 5396// CHECK1-NEXT: store i32 [[ADD26]], ptr [[DOTFLOOR_1_IV_J]], align 4397// CHECK1-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP10:![0-9]+]]398// CHECK1: for.end27:399// CHECK1-NEXT: br label [[FOR_INC28:%.*]]400// CHECK1: for.inc28:401// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4402// CHECK1-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP17]], 5403// CHECK1-NEXT: store i32 [[ADD29]], ptr [[DOTFLOOR_0_IV_I]], align 4404// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]405// CHECK1: for.end30:406// CHECK1-NEXT: ret void407//408//409// CHECK1-LABEL: define dso_local void @foo3(410// CHECK1-SAME: ) #[[ATTR0]] {411// CHECK1-NEXT: entry:412// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4413// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4414// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4415// CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4416// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4417// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4418// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4419// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4420// CHECK1-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 4421// CHECK1-NEXT: [[DOTFLOOR_1_IV_J:%.*]] = alloca i32, align 4422// CHECK1-NEXT: [[DOTSTRIPE_0_IV_I:%.*]] = alloca i32, align 4423// CHECK1-NEXT: [[DOTSTRIPE_1_IV_J:%.*]] = alloca i32, align 4424// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])425// CHECK1-NEXT: store i32 7, ptr [[I]], align 4426// CHECK1-NEXT: store i32 7, ptr [[J]], align 4427// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4428// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_UB]], align 4429// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4430// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4431// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)432// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4433// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 0434// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]435// CHECK1: cond.true:436// CHECK1-NEXT: br label [[COND_END:%.*]]437// CHECK1: cond.false:438// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4439// CHECK1-NEXT: br label [[COND_END]]440// CHECK1: cond.end:441// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 0, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ]442// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4443// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4444// CHECK1-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4445// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]446// CHECK1: omp.inner.for.cond:447// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4448// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4449// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]450// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]451// CHECK1: omp.inner.for.body:452// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4453// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 5454// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]455// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTFLOOR_0_IV_I]], align 4456// CHECK1-NEXT: store i32 0, ptr [[DOTFLOOR_1_IV_J]], align 4457// CHECK1-NEXT: br label [[FOR_COND:%.*]]458// CHECK1: for.cond:459// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4460// CHECK1-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP7]], 4461// CHECK1-NEXT: br i1 [[CMP2]], label [[FOR_BODY:%.*]], label [[FOR_END32:%.*]]462// CHECK1: for.body:463// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4464// CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTSTRIPE_0_IV_I]], align 4465// CHECK1-NEXT: br label [[FOR_COND3:%.*]]466// CHECK1: for.cond3:467// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 4468// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4469// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 5470// CHECK1-NEXT: [[CMP5:%.*]] = icmp slt i32 4, [[ADD4]]471// CHECK1-NEXT: br i1 [[CMP5]], label [[COND_TRUE6:%.*]], label [[COND_FALSE7:%.*]]472// CHECK1: cond.true6:473// CHECK1-NEXT: br label [[COND_END9:%.*]]474// CHECK1: cond.false7:475// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4476// CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP11]], 5477// CHECK1-NEXT: br label [[COND_END9]]478// CHECK1: cond.end9:479// CHECK1-NEXT: [[COND10:%.*]] = phi i32 [ 4, [[COND_TRUE6]] ], [ [[ADD8]], [[COND_FALSE7]] ]480// CHECK1-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP9]], [[COND10]]481// CHECK1-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END29:%.*]]482// CHECK1: for.body12:483// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 4484// CHECK1-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP12]], 3485// CHECK1-NEXT: [[ADD14:%.*]] = add nsw i32 7, [[MUL13]]486// CHECK1-NEXT: store i32 [[ADD14]], ptr [[I]], align 4487// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4488// CHECK1-NEXT: store i32 [[TMP13]], ptr [[DOTSTRIPE_1_IV_J]], align 4489// CHECK1-NEXT: br label [[FOR_COND15:%.*]]490// CHECK1: for.cond15:491// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTSTRIPE_1_IV_J]], align 4492// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4493// CHECK1-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP15]], 5494// CHECK1-NEXT: [[CMP17:%.*]] = icmp slt i32 4, [[ADD16]]495// CHECK1-NEXT: br i1 [[CMP17]], label [[COND_TRUE18:%.*]], label [[COND_FALSE19:%.*]]496// CHECK1: cond.true18:497// CHECK1-NEXT: br label [[COND_END21:%.*]]498// CHECK1: cond.false19:499// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4500// CHECK1-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP16]], 5501// CHECK1-NEXT: br label [[COND_END21]]502// CHECK1: cond.end21:503// CHECK1-NEXT: [[COND22:%.*]] = phi i32 [ 4, [[COND_TRUE18]] ], [ [[ADD20]], [[COND_FALSE19]] ]504// CHECK1-NEXT: [[CMP23:%.*]] = icmp slt i32 [[TMP14]], [[COND22]]505// CHECK1-NEXT: br i1 [[CMP23]], label [[FOR_BODY24:%.*]], label [[FOR_END:%.*]]506// CHECK1: for.body24:507// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTSTRIPE_1_IV_J]], align 4508// CHECK1-NEXT: [[MUL25:%.*]] = mul nsw i32 [[TMP17]], 3509// CHECK1-NEXT: [[ADD26:%.*]] = add nsw i32 7, [[MUL25]]510// CHECK1-NEXT: store i32 [[ADD26]], ptr [[J]], align 4511// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4512// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[J]], align 4513// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP18]], i32 noundef [[TMP19]])514// CHECK1-NEXT: br label [[FOR_INC:%.*]]515// CHECK1: for.inc:516// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTSTRIPE_1_IV_J]], align 4517// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP20]], 1518// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTSTRIPE_1_IV_J]], align 4519// CHECK1-NEXT: br label [[FOR_COND15]], !llvm.loop [[LOOP12:![0-9]+]]520// CHECK1: for.end:521// CHECK1-NEXT: br label [[FOR_INC27:%.*]]522// CHECK1: for.inc27:523// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 4524// CHECK1-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP21]], 1525// CHECK1-NEXT: store i32 [[INC28]], ptr [[DOTSTRIPE_0_IV_I]], align 4526// CHECK1-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP13:![0-9]+]]527// CHECK1: for.end29:528// CHECK1-NEXT: br label [[FOR_INC30:%.*]]529// CHECK1: for.inc30:530// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4531// CHECK1-NEXT: [[ADD31:%.*]] = add nsw i32 [[TMP22]], 5532// CHECK1-NEXT: store i32 [[ADD31]], ptr [[DOTFLOOR_1_IV_J]], align 4533// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]534// CHECK1: for.end32:535// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]536// CHECK1: omp.body.continue:537// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]538// CHECK1: omp.inner.for.inc:539// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4540// CHECK1-NEXT: [[ADD33:%.*]] = add nsw i32 [[TMP23]], 1541// CHECK1-NEXT: store i32 [[ADD33]], ptr [[DOTOMP_IV]], align 4542// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]543// CHECK1: omp.inner.for.end:544// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]545// CHECK1: omp.loop.exit:546// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]])547// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP0]])548// CHECK1-NEXT: ret void549//550//551// CHECK1-LABEL: define dso_local void @foo4(552// CHECK1-SAME: ) #[[ATTR0]] {553// CHECK1-NEXT: entry:554// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4555// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4556// CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4557// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4558// CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4559// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4560// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4561// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4562// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4563// CHECK1-NEXT: [[K:%.*]] = alloca i32, align 4564// CHECK1-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 4565// CHECK1-NEXT: [[DOTFLOOR_1_IV_J:%.*]] = alloca i32, align 4566// CHECK1-NEXT: [[DOTSTRIPE_0_IV_I:%.*]] = alloca i32, align 4567// CHECK1-NEXT: [[DOTSTRIPE_1_IV_J:%.*]] = alloca i32, align 4568// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])569// CHECK1-NEXT: store i32 7, ptr [[I]], align 4570// CHECK1-NEXT: store i32 7, ptr [[J]], align 4571// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4572// CHECK1-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 4573// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4574// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4575// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)576// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4577// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 3578// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]579// CHECK1: cond.true:580// CHECK1-NEXT: br label [[COND_END:%.*]]581// CHECK1: cond.false:582// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4583// CHECK1-NEXT: br label [[COND_END]]584// CHECK1: cond.end:585// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ]586// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4587// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4588// CHECK1-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4589// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]590// CHECK1: omp.inner.for.cond:591// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4592// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4593// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]594// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]595// CHECK1: omp.inner.for.body:596// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4597// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP6]], 1598// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 3599// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 7, [[MUL]]600// CHECK1-NEXT: store i32 [[ADD]], ptr [[K]], align 4601// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4602// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4603// CHECK1-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP8]], 1604// CHECK1-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 1605// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], [[MUL4]]606// CHECK1-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 5607// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]608// CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTFLOOR_0_IV_I]], align 4609// CHECK1-NEXT: store i32 0, ptr [[DOTFLOOR_1_IV_J]], align 4610// CHECK1-NEXT: br label [[FOR_COND:%.*]]611// CHECK1: for.cond:612// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4613// CHECK1-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP9]], 4614// CHECK1-NEXT: br i1 [[CMP7]], label [[FOR_BODY:%.*]], label [[FOR_END37:%.*]]615// CHECK1: for.body:616// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4617// CHECK1-NEXT: store i32 [[TMP10]], ptr [[DOTSTRIPE_0_IV_I]], align 4618// CHECK1-NEXT: br label [[FOR_COND8:%.*]]619// CHECK1: for.cond8:620// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 4621// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4622// CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP12]], 5623// CHECK1-NEXT: [[CMP10:%.*]] = icmp slt i32 4, [[ADD9]]624// CHECK1-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]]625// CHECK1: cond.true11:626// CHECK1-NEXT: br label [[COND_END14:%.*]]627// CHECK1: cond.false12:628// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4629// CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP13]], 5630// CHECK1-NEXT: br label [[COND_END14]]631// CHECK1: cond.end14:632// CHECK1-NEXT: [[COND15:%.*]] = phi i32 [ 4, [[COND_TRUE11]] ], [ [[ADD13]], [[COND_FALSE12]] ]633// CHECK1-NEXT: [[CMP16:%.*]] = icmp slt i32 [[TMP11]], [[COND15]]634// CHECK1-NEXT: br i1 [[CMP16]], label [[FOR_BODY17:%.*]], label [[FOR_END34:%.*]]635// CHECK1: for.body17:636// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 4637// CHECK1-NEXT: [[MUL18:%.*]] = mul nsw i32 [[TMP14]], 3638// CHECK1-NEXT: [[ADD19:%.*]] = add nsw i32 7, [[MUL18]]639// CHECK1-NEXT: store i32 [[ADD19]], ptr [[I]], align 4640// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4641// CHECK1-NEXT: store i32 [[TMP15]], ptr [[DOTSTRIPE_1_IV_J]], align 4642// CHECK1-NEXT: br label [[FOR_COND20:%.*]]643// CHECK1: for.cond20:644// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTSTRIPE_1_IV_J]], align 4645// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4646// CHECK1-NEXT: [[ADD21:%.*]] = add nsw i32 [[TMP17]], 5647// CHECK1-NEXT: [[CMP22:%.*]] = icmp slt i32 4, [[ADD21]]648// CHECK1-NEXT: br i1 [[CMP22]], label [[COND_TRUE23:%.*]], label [[COND_FALSE24:%.*]]649// CHECK1: cond.true23:650// CHECK1-NEXT: br label [[COND_END26:%.*]]651// CHECK1: cond.false24:652// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4653// CHECK1-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP18]], 5654// CHECK1-NEXT: br label [[COND_END26]]655// CHECK1: cond.end26:656// CHECK1-NEXT: [[COND27:%.*]] = phi i32 [ 4, [[COND_TRUE23]] ], [ [[ADD25]], [[COND_FALSE24]] ]657// CHECK1-NEXT: [[CMP28:%.*]] = icmp slt i32 [[TMP16]], [[COND27]]658// CHECK1-NEXT: br i1 [[CMP28]], label [[FOR_BODY29:%.*]], label [[FOR_END:%.*]]659// CHECK1: for.body29:660// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTSTRIPE_1_IV_J]], align 4661// CHECK1-NEXT: [[MUL30:%.*]] = mul nsw i32 [[TMP19]], 3662// CHECK1-NEXT: [[ADD31:%.*]] = add nsw i32 7, [[MUL30]]663// CHECK1-NEXT: store i32 [[ADD31]], ptr [[J]], align 4664// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[I]], align 4665// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[J]], align 4666// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP20]], i32 noundef [[TMP21]])667// CHECK1-NEXT: br label [[FOR_INC:%.*]]668// CHECK1: for.inc:669// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTSTRIPE_1_IV_J]], align 4670// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP22]], 1671// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTSTRIPE_1_IV_J]], align 4672// CHECK1-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP15:![0-9]+]]673// CHECK1: for.end:674// CHECK1-NEXT: br label [[FOR_INC32:%.*]]675// CHECK1: for.inc32:676// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 4677// CHECK1-NEXT: [[INC33:%.*]] = add nsw i32 [[TMP23]], 1678// CHECK1-NEXT: store i32 [[INC33]], ptr [[DOTSTRIPE_0_IV_I]], align 4679// CHECK1-NEXT: br label [[FOR_COND8]], !llvm.loop [[LOOP16:![0-9]+]]680// CHECK1: for.end34:681// CHECK1-NEXT: br label [[FOR_INC35:%.*]]682// CHECK1: for.inc35:683// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4684// CHECK1-NEXT: [[ADD36:%.*]] = add nsw i32 [[TMP24]], 5685// CHECK1-NEXT: store i32 [[ADD36]], ptr [[DOTFLOOR_1_IV_J]], align 4686// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]687// CHECK1: for.end37:688// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]689// CHECK1: omp.body.continue:690// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]691// CHECK1: omp.inner.for.inc:692// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4693// CHECK1-NEXT: [[ADD38:%.*]] = add nsw i32 [[TMP25]], 1694// CHECK1-NEXT: store i32 [[ADD38]], ptr [[DOTOMP_IV]], align 4695// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]696// CHECK1: omp.inner.for.end:697// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]698// CHECK1: omp.loop.exit:699// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]])700// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]])701// CHECK1-NEXT: ret void702//703//704// CHECK1-LABEL: define dso_local void @foo5(705// CHECK1-SAME: ) #[[ATTR0]] {706// CHECK1-NEXT: entry:707// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8708// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4709// CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4710// CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4711// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4712// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4713// CHECK1-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4714// CHECK1-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8715// CHECK1-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 4716// CHECK1-NEXT: [[DOTSTRIPE_0_IV_I:%.*]] = alloca i32, align 4717// CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4718// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8719// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8720// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8721// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4722// CHECK1-NEXT: [[DOTFLOOR_0_IV_I11:%.*]] = alloca i32, align 4723// CHECK1-NEXT: [[DOTSTRIPE_0_IV_I12:%.*]] = alloca i32, align 4724// CHECK1-NEXT: [[J13:%.*]] = alloca i32, align 4725// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])726// CHECK1-NEXT: store i32 7, ptr [[I]], align 4727// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP]], align 4728// CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4729// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP]], align 4730// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 5731// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 4, [[ADD]]732// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]733// CHECK1: cond.true:734// CHECK1-NEXT: br label [[COND_END:%.*]]735// CHECK1: cond.false:736// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP]], align 4737// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 5738// CHECK1-NEXT: br label [[COND_END]]739// CHECK1: cond.end:740// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 4, [[COND_TRUE]] ], [ [[ADD4]], [[COND_FALSE]] ]741// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTCAPTURE_EXPR_3]], align 4742// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4743// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4744// CHECK1-NEXT: [[SUB:%.*]] = sub i32 [[TMP4]], [[TMP5]]745// CHECK1-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1746// CHECK1-NEXT: [[ADD7:%.*]] = add i32 [[SUB6]], 1747// CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD7]], 1748// CHECK1-NEXT: [[CONV:%.*]] = zext i32 [[DIV]] to i64749// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 1, [[CONV]]750// CHECK1-NEXT: [[MUL8:%.*]] = mul nsw i64 [[MUL]], 4751// CHECK1-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL8]], 1752// CHECK1-NEXT: store i64 [[SUB9]], ptr [[DOTCAPTURE_EXPR_5]], align 8753// CHECK1-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV_I]], align 4754// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4755// CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTSTRIPE_0_IV_I]], align 4756// CHECK1-NEXT: store i32 7, ptr [[J]], align 4757// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4758// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4759// CHECK1-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]]760// CHECK1-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]761// CHECK1: omp.precond.then:762// CHECK1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8763// CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8764// CHECK1-NEXT: store i64 [[TMP9]], ptr [[DOTOMP_UB]], align 8765// CHECK1-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8766// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4767// CHECK1-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)768// CHECK1-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8769// CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8770// CHECK1-NEXT: [[CMP14:%.*]] = icmp sgt i64 [[TMP10]], [[TMP11]]771// CHECK1-NEXT: br i1 [[CMP14]], label [[COND_TRUE15:%.*]], label [[COND_FALSE16:%.*]]772// CHECK1: cond.true15:773// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8774// CHECK1-NEXT: br label [[COND_END17:%.*]]775// CHECK1: cond.false16:776// CHECK1-NEXT: [[TMP13:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8777// CHECK1-NEXT: br label [[COND_END17]]778// CHECK1: cond.end17:779// CHECK1-NEXT: [[COND18:%.*]] = phi i64 [ [[TMP12]], [[COND_TRUE15]] ], [ [[TMP13]], [[COND_FALSE16]] ]780// CHECK1-NEXT: store i64 [[COND18]], ptr [[DOTOMP_UB]], align 8781// CHECK1-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8782// CHECK1-NEXT: store i64 [[TMP14]], ptr [[DOTOMP_IV]], align 8783// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]784// CHECK1: omp.inner.for.cond:785// CHECK1-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8786// CHECK1-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8787// CHECK1-NEXT: [[CMP19:%.*]] = icmp sle i64 [[TMP15]], [[TMP16]]788// CHECK1-NEXT: br i1 [[CMP19]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]789// CHECK1: omp.inner.for.body:790// CHECK1-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8791// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4792// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4793// CHECK1-NEXT: [[SUB20:%.*]] = sub i32 [[TMP18]], [[TMP19]]794// CHECK1-NEXT: [[SUB21:%.*]] = sub i32 [[SUB20]], 1795// CHECK1-NEXT: [[ADD22:%.*]] = add i32 [[SUB21]], 1796// CHECK1-NEXT: [[DIV23:%.*]] = udiv i32 [[ADD22]], 1797// CHECK1-NEXT: [[MUL24:%.*]] = mul i32 1, [[DIV23]]798// CHECK1-NEXT: [[MUL25:%.*]] = mul i32 [[MUL24]], 4799// CHECK1-NEXT: [[CONV26:%.*]] = zext i32 [[MUL25]] to i64800// CHECK1-NEXT: [[DIV27:%.*]] = sdiv i64 [[TMP17]], [[CONV26]]801// CHECK1-NEXT: [[MUL28:%.*]] = mul nsw i64 [[DIV27]], 5802// CHECK1-NEXT: [[ADD29:%.*]] = add nsw i64 0, [[MUL28]]803// CHECK1-NEXT: [[CONV30:%.*]] = trunc i64 [[ADD29]] to i32804// CHECK1-NEXT: store i32 [[CONV30]], ptr [[DOTFLOOR_0_IV_I11]], align 4805// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4806// CHECK1-NEXT: [[CONV31:%.*]] = sext i32 [[TMP20]] to i64807// CHECK1-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8808// CHECK1-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8809// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4810// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4811// CHECK1-NEXT: [[SUB32:%.*]] = sub i32 [[TMP23]], [[TMP24]]812// CHECK1-NEXT: [[SUB33:%.*]] = sub i32 [[SUB32]], 1813// CHECK1-NEXT: [[ADD34:%.*]] = add i32 [[SUB33]], 1814// CHECK1-NEXT: [[DIV35:%.*]] = udiv i32 [[ADD34]], 1815// CHECK1-NEXT: [[MUL36:%.*]] = mul i32 1, [[DIV35]]816// CHECK1-NEXT: [[MUL37:%.*]] = mul i32 [[MUL36]], 4817// CHECK1-NEXT: [[CONV38:%.*]] = zext i32 [[MUL37]] to i64818// CHECK1-NEXT: [[DIV39:%.*]] = sdiv i64 [[TMP22]], [[CONV38]]819// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4820// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4821// CHECK1-NEXT: [[SUB40:%.*]] = sub i32 [[TMP25]], [[TMP26]]822// CHECK1-NEXT: [[SUB41:%.*]] = sub i32 [[SUB40]], 1823// CHECK1-NEXT: [[ADD42:%.*]] = add i32 [[SUB41]], 1824// CHECK1-NEXT: [[DIV43:%.*]] = udiv i32 [[ADD42]], 1825// CHECK1-NEXT: [[MUL44:%.*]] = mul i32 1, [[DIV43]]826// CHECK1-NEXT: [[MUL45:%.*]] = mul i32 [[MUL44]], 4827// CHECK1-NEXT: [[CONV46:%.*]] = zext i32 [[MUL45]] to i64828// CHECK1-NEXT: [[MUL47:%.*]] = mul nsw i64 [[DIV39]], [[CONV46]]829// CHECK1-NEXT: [[SUB48:%.*]] = sub nsw i64 [[TMP21]], [[MUL47]]830// CHECK1-NEXT: [[DIV49:%.*]] = sdiv i64 [[SUB48]], 4831// CHECK1-NEXT: [[MUL50:%.*]] = mul nsw i64 [[DIV49]], 1832// CHECK1-NEXT: [[ADD51:%.*]] = add nsw i64 [[CONV31]], [[MUL50]]833// CHECK1-NEXT: [[CONV52:%.*]] = trunc i64 [[ADD51]] to i32834// CHECK1-NEXT: store i32 [[CONV52]], ptr [[DOTSTRIPE_0_IV_I12]], align 4835// CHECK1-NEXT: [[TMP27:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8836// CHECK1-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8837// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4838// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4839// CHECK1-NEXT: [[SUB53:%.*]] = sub i32 [[TMP29]], [[TMP30]]840// CHECK1-NEXT: [[SUB54:%.*]] = sub i32 [[SUB53]], 1841// CHECK1-NEXT: [[ADD55:%.*]] = add i32 [[SUB54]], 1842// CHECK1-NEXT: [[DIV56:%.*]] = udiv i32 [[ADD55]], 1843// CHECK1-NEXT: [[MUL57:%.*]] = mul i32 1, [[DIV56]]844// CHECK1-NEXT: [[MUL58:%.*]] = mul i32 [[MUL57]], 4845// CHECK1-NEXT: [[CONV59:%.*]] = zext i32 [[MUL58]] to i64846// CHECK1-NEXT: [[DIV60:%.*]] = sdiv i64 [[TMP28]], [[CONV59]]847// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4848// CHECK1-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4849// CHECK1-NEXT: [[SUB61:%.*]] = sub i32 [[TMP31]], [[TMP32]]850// CHECK1-NEXT: [[SUB62:%.*]] = sub i32 [[SUB61]], 1851// CHECK1-NEXT: [[ADD63:%.*]] = add i32 [[SUB62]], 1852// CHECK1-NEXT: [[DIV64:%.*]] = udiv i32 [[ADD63]], 1853// CHECK1-NEXT: [[MUL65:%.*]] = mul i32 1, [[DIV64]]854// CHECK1-NEXT: [[MUL66:%.*]] = mul i32 [[MUL65]], 4855// CHECK1-NEXT: [[CONV67:%.*]] = zext i32 [[MUL66]] to i64856// CHECK1-NEXT: [[MUL68:%.*]] = mul nsw i64 [[DIV60]], [[CONV67]]857// CHECK1-NEXT: [[SUB69:%.*]] = sub nsw i64 [[TMP27]], [[MUL68]]858// CHECK1-NEXT: [[TMP33:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8859// CHECK1-NEXT: [[TMP34:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8860// CHECK1-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4861// CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4862// CHECK1-NEXT: [[SUB70:%.*]] = sub i32 [[TMP35]], [[TMP36]]863// CHECK1-NEXT: [[SUB71:%.*]] = sub i32 [[SUB70]], 1864// CHECK1-NEXT: [[ADD72:%.*]] = add i32 [[SUB71]], 1865// CHECK1-NEXT: [[DIV73:%.*]] = udiv i32 [[ADD72]], 1866// CHECK1-NEXT: [[MUL74:%.*]] = mul i32 1, [[DIV73]]867// CHECK1-NEXT: [[MUL75:%.*]] = mul i32 [[MUL74]], 4868// CHECK1-NEXT: [[CONV76:%.*]] = zext i32 [[MUL75]] to i64869// CHECK1-NEXT: [[DIV77:%.*]] = sdiv i64 [[TMP34]], [[CONV76]]870// CHECK1-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4871// CHECK1-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4872// CHECK1-NEXT: [[SUB78:%.*]] = sub i32 [[TMP37]], [[TMP38]]873// CHECK1-NEXT: [[SUB79:%.*]] = sub i32 [[SUB78]], 1874// CHECK1-NEXT: [[ADD80:%.*]] = add i32 [[SUB79]], 1875// CHECK1-NEXT: [[DIV81:%.*]] = udiv i32 [[ADD80]], 1876// CHECK1-NEXT: [[MUL82:%.*]] = mul i32 1, [[DIV81]]877// CHECK1-NEXT: [[MUL83:%.*]] = mul i32 [[MUL82]], 4878// CHECK1-NEXT: [[CONV84:%.*]] = zext i32 [[MUL83]] to i64879// CHECK1-NEXT: [[MUL85:%.*]] = mul nsw i64 [[DIV77]], [[CONV84]]880// CHECK1-NEXT: [[SUB86:%.*]] = sub nsw i64 [[TMP33]], [[MUL85]]881// CHECK1-NEXT: [[DIV87:%.*]] = sdiv i64 [[SUB86]], 4882// CHECK1-NEXT: [[MUL88:%.*]] = mul nsw i64 [[DIV87]], 4883// CHECK1-NEXT: [[SUB89:%.*]] = sub nsw i64 [[SUB69]], [[MUL88]]884// CHECK1-NEXT: [[MUL90:%.*]] = mul nsw i64 [[SUB89]], 3885// CHECK1-NEXT: [[ADD91:%.*]] = add nsw i64 7, [[MUL90]]886// CHECK1-NEXT: [[CONV92:%.*]] = trunc i64 [[ADD91]] to i32887// CHECK1-NEXT: store i32 [[CONV92]], ptr [[J13]], align 4888// CHECK1-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I12]], align 4889// CHECK1-NEXT: [[MUL93:%.*]] = mul nsw i32 [[TMP39]], 3890// CHECK1-NEXT: [[ADD94:%.*]] = add nsw i32 7, [[MUL93]]891// CHECK1-NEXT: store i32 [[ADD94]], ptr [[I]], align 4892// CHECK1-NEXT: [[TMP40:%.*]] = load i32, ptr [[I]], align 4893// CHECK1-NEXT: [[TMP41:%.*]] = load i32, ptr [[J13]], align 4894// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP40]], i32 noundef [[TMP41]])895// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]896// CHECK1: omp.body.continue:897// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]898// CHECK1: omp.inner.for.inc:899// CHECK1-NEXT: [[TMP42:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8900// CHECK1-NEXT: [[ADD95:%.*]] = add nsw i64 [[TMP42]], 1901// CHECK1-NEXT: store i64 [[ADD95]], ptr [[DOTOMP_IV]], align 8902// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]903// CHECK1: omp.inner.for.end:904// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]905// CHECK1: omp.loop.exit:906// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]])907// CHECK1-NEXT: br label [[OMP_PRECOND_END]]908// CHECK1: omp.precond.end:909// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]])910// CHECK1-NEXT: ret void911//912//913// CHECK1-LABEL: define dso_local void @foo6(914// CHECK1-SAME: ) #[[ATTR0]] {915// CHECK1-NEXT: entry:916// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @foo6.omp_outlined)917// CHECK1-NEXT: ret void918//919//920// CHECK1-LABEL: define internal void @foo6.omp_outlined(921// CHECK1-SAME: ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4:[0-9]+]] {922// CHECK1-NEXT: entry:923// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8924// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8925// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4926// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4927// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4928// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4929// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4930// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4931// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4932// CHECK1-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 4933// CHECK1-NEXT: [[DOTSTRIPE_0_IV_I:%.*]] = alloca i32, align 4934// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8935// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8936// CHECK1-NEXT: store i32 7, ptr [[I]], align 4937// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4938// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_UB]], align 4939// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4940// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4941// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8942// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4943// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)944// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4945// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 0946// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]947// CHECK1: cond.true:948// CHECK1-NEXT: br label [[COND_END:%.*]]949// CHECK1: cond.false:950// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4951// CHECK1-NEXT: br label [[COND_END]]952// CHECK1: cond.end:953// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 0, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]954// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4955// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4956// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4957// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]958// CHECK1: omp.inner.for.cond:959// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4960// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4961// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]962// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]963// CHECK1: omp.inner.for.body:964// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4965// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5966// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]967// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTFLOOR_0_IV_I]], align 4968// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4969// CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTSTRIPE_0_IV_I]], align 4970// CHECK1-NEXT: br label [[FOR_COND:%.*]]971// CHECK1: for.cond:972// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 4973// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4974// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 5975// CHECK1-NEXT: [[CMP3:%.*]] = icmp slt i32 4, [[ADD2]]976// CHECK1-NEXT: br i1 [[CMP3]], label [[COND_TRUE4:%.*]], label [[COND_FALSE5:%.*]]977// CHECK1: cond.true4:978// CHECK1-NEXT: br label [[COND_END7:%.*]]979// CHECK1: cond.false5:980// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4981// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 5982// CHECK1-NEXT: br label [[COND_END7]]983// CHECK1: cond.end7:984// CHECK1-NEXT: [[COND8:%.*]] = phi i32 [ 4, [[COND_TRUE4]] ], [ [[ADD6]], [[COND_FALSE5]] ]985// CHECK1-NEXT: [[CMP9:%.*]] = icmp slt i32 [[TMP9]], [[COND8]]986// CHECK1-NEXT: br i1 [[CMP9]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]987// CHECK1: for.body:988// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 4989// CHECK1-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP12]], 3990// CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 7, [[MUL10]]991// CHECK1-NEXT: store i32 [[ADD11]], ptr [[I]], align 4992// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4993// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP13]])994// CHECK1-NEXT: br label [[FOR_INC:%.*]]995// CHECK1: for.inc:996// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 4997// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1998// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTSTRIPE_0_IV_I]], align 4999// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]1000// CHECK1: for.end:1001// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1002// CHECK1: omp.body.continue:1003// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1004// CHECK1: omp.inner.for.inc:1005// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41006// CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP15]], 11007// CHECK1-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 41008// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]1009// CHECK1: omp.inner.for.end:1010// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]1011// CHECK1: omp.loop.exit:1012// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])1013// CHECK1-NEXT: ret void1014//1015//1016// CHECK1-LABEL: define dso_local void @tfoo7(1017// CHECK1-SAME: ) #[[ATTR0]] {1018// CHECK1-NEXT: entry:1019// CHECK1-NEXT: call void @_Z4foo7IiTnT_Li3ETnS0_Li5EEvS0_S0_(i32 noundef 0, i32 noundef 42)1020// CHECK1-NEXT: ret void1021//1022//1023// CHECK1-LABEL: define linkonce_odr void @_Z4foo7IiTnT_Li3ETnS0_Li5EEvS0_S0_(1024// CHECK1-SAME: i32 noundef [[START:%.*]], i32 noundef [[END:%.*]]) #[[ATTR0]] comdat {1025// CHECK1-NEXT: entry:1026// CHECK1-NEXT: [[START_ADDR:%.*]] = alloca i32, align 41027// CHECK1-NEXT: [[END_ADDR:%.*]] = alloca i32, align 41028// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 41029// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 41030// CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 41031// CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 41032// CHECK1-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 41033// CHECK1-NEXT: [[DOTSTRIPE_0_IV_I:%.*]] = alloca i32, align 41034// CHECK1-NEXT: store i32 [[START]], ptr [[START_ADDR]], align 41035// CHECK1-NEXT: store i32 [[END]], ptr [[END_ADDR]], align 41036// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[START_ADDR]], align 41037// CHECK1-NEXT: store i32 [[TMP0]], ptr [[I]], align 41038// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[START_ADDR]], align 41039// CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 41040// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[END_ADDR]], align 41041// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_1]], align 41042// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 41043// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41044// CHECK1-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]1045// CHECK1-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 11046// CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 31047// CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 31048// CHECK1-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 11049// CHECK1-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 41050// CHECK1-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV_I]], align 41051// CHECK1-NEXT: br label [[FOR_COND:%.*]]1052// CHECK1: for.cond:1053// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 41054// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 41055// CHECK1-NEXT: [[ADD5:%.*]] = add i32 [[TMP6]], 11056// CHECK1-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP5]], [[ADD5]]1057// CHECK1-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END17:%.*]]1058// CHECK1: for.body:1059// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 41060// CHECK1-NEXT: store i32 [[TMP7]], ptr [[DOTSTRIPE_0_IV_I]], align 41061// CHECK1-NEXT: br label [[FOR_COND6:%.*]]1062// CHECK1: for.cond6:1063// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 41064// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 41065// CHECK1-NEXT: [[ADD7:%.*]] = add i32 [[TMP9]], 11066// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 41067// CHECK1-NEXT: [[ADD8:%.*]] = add i32 [[TMP10]], 51068// CHECK1-NEXT: [[CMP9:%.*]] = icmp ult i32 [[ADD7]], [[ADD8]]1069// CHECK1-NEXT: br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1070// CHECK1: cond.true:1071// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 41072// CHECK1-NEXT: [[ADD10:%.*]] = add i32 [[TMP11]], 11073// CHECK1-NEXT: br label [[COND_END:%.*]]1074// CHECK1: cond.false:1075// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 41076// CHECK1-NEXT: [[ADD11:%.*]] = add i32 [[TMP12]], 51077// CHECK1-NEXT: br label [[COND_END]]1078// CHECK1: cond.end:1079// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[ADD10]], [[COND_TRUE]] ], [ [[ADD11]], [[COND_FALSE]] ]1080// CHECK1-NEXT: [[CMP12:%.*]] = icmp ult i32 [[TMP8]], [[COND]]1081// CHECK1-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END:%.*]]1082// CHECK1: for.body13:1083// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41084// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 41085// CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP14]], 31086// CHECK1-NEXT: [[ADD14:%.*]] = add i32 [[TMP13]], [[MUL]]1087// CHECK1-NEXT: store i32 [[ADD14]], ptr [[I]], align 41088// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 41089// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP15]])1090// CHECK1-NEXT: br label [[FOR_INC:%.*]]1091// CHECK1: for.inc:1092// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 41093// CHECK1-NEXT: [[INC:%.*]] = add i32 [[TMP16]], 11094// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTSTRIPE_0_IV_I]], align 41095// CHECK1-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP21:![0-9]+]]1096// CHECK1: for.end:1097// CHECK1-NEXT: br label [[FOR_INC15:%.*]]1098// CHECK1: for.inc15:1099// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 41100// CHECK1-NEXT: [[ADD16:%.*]] = add i32 [[TMP17]], 51101// CHECK1-NEXT: store i32 [[ADD16]], ptr [[DOTFLOOR_0_IV_I]], align 41102// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]1103// CHECK1: for.end17:1104// CHECK1-NEXT: ret void1105//1106//1107// CHECK1-LABEL: define dso_local void @foo8(1108// CHECK1-SAME: i32 noundef [[A:%.*]]) #[[ATTR0]] {1109// CHECK1-NEXT: entry:1110// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 41111// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 41112// CHECK1-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 41113// CHECK1-NEXT: [[DOTSTRIPE_0_IV_I:%.*]] = alloca i32, align 41114// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 41115// CHECK1-NEXT: store i32 7, ptr [[I]], align 41116// CHECK1-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV_I]], align 41117// CHECK1-NEXT: br label [[FOR_COND:%.*]]1118// CHECK1: for.cond:1119// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 41120// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 41121// CHECK1-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END24:%.*]]1122// CHECK1: for.body:1123// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 41124// CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTSTRIPE_0_IV_I]], align 41125// CHECK1-NEXT: br label [[FOR_COND1:%.*]]1126// CHECK1: for.cond1:1127// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 41128// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 41129// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 41130// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP4]], 01131// CHECK1-NEXT: br i1 [[CMP2]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1132// CHECK1: cond.true:1133// CHECK1-NEXT: br label [[COND_END:%.*]]1134// CHECK1: cond.false:1135// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[A_ADDR]], align 41136// CHECK1-NEXT: br label [[COND_END]]1137// CHECK1: cond.end:1138// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]1139// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[COND]]1140// CHECK1-NEXT: [[CMP3:%.*]] = icmp slt i32 4, [[ADD]]1141// CHECK1-NEXT: br i1 [[CMP3]], label [[COND_TRUE4:%.*]], label [[COND_FALSE5:%.*]]1142// CHECK1: cond.true4:1143// CHECK1-NEXT: br label [[COND_END12:%.*]]1144// CHECK1: cond.false5:1145// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 41146// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[A_ADDR]], align 41147// CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], 01148// CHECK1-NEXT: br i1 [[CMP6]], label [[COND_TRUE7:%.*]], label [[COND_FALSE8:%.*]]1149// CHECK1: cond.true7:1150// CHECK1-NEXT: br label [[COND_END9:%.*]]1151// CHECK1: cond.false8:1152// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 41153// CHECK1-NEXT: br label [[COND_END9]]1154// CHECK1: cond.end9:1155// CHECK1-NEXT: [[COND10:%.*]] = phi i32 [ 1, [[COND_TRUE7]] ], [ [[TMP8]], [[COND_FALSE8]] ]1156// CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP6]], [[COND10]]1157// CHECK1-NEXT: br label [[COND_END12]]1158// CHECK1: cond.end12:1159// CHECK1-NEXT: [[COND13:%.*]] = phi i32 [ 4, [[COND_TRUE4]] ], [ [[ADD11]], [[COND_END9]] ]1160// CHECK1-NEXT: [[CMP14:%.*]] = icmp slt i32 [[TMP2]], [[COND13]]1161// CHECK1-NEXT: br i1 [[CMP14]], label [[FOR_BODY15:%.*]], label [[FOR_END:%.*]]1162// CHECK1: for.body15:1163// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 41164// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 31165// CHECK1-NEXT: [[ADD16:%.*]] = add nsw i32 7, [[MUL]]1166// CHECK1-NEXT: store i32 [[ADD16]], ptr [[I]], align 41167// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 41168// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP10]])1169// CHECK1-NEXT: br label [[FOR_INC:%.*]]1170// CHECK1: for.inc:1171// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 41172// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 11173// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTSTRIPE_0_IV_I]], align 41174// CHECK1-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP23:![0-9]+]]1175// CHECK1: for.end:1176// CHECK1-NEXT: br label [[FOR_INC17:%.*]]1177// CHECK1: for.inc17:1178// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[A_ADDR]], align 41179// CHECK1-NEXT: [[CMP18:%.*]] = icmp sle i32 [[TMP12]], 01180// CHECK1-NEXT: br i1 [[CMP18]], label [[COND_TRUE19:%.*]], label [[COND_FALSE20:%.*]]1181// CHECK1: cond.true19:1182// CHECK1-NEXT: br label [[COND_END21:%.*]]1183// CHECK1: cond.false20:1184// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[A_ADDR]], align 41185// CHECK1-NEXT: br label [[COND_END21]]1186// CHECK1: cond.end21:1187// CHECK1-NEXT: [[COND22:%.*]] = phi i32 [ 1, [[COND_TRUE19]] ], [ [[TMP13]], [[COND_FALSE20]] ]1188// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 41189// CHECK1-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP14]], [[COND22]]1190// CHECK1-NEXT: store i32 [[ADD23]], ptr [[DOTFLOOR_0_IV_I]], align 41191// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]1192// CHECK1: for.end24:1193// CHECK1-NEXT: ret void1194//1195//1196// CHECK1-LABEL: define dso_local void @foo9(1197// CHECK1-SAME: ptr noundef byval([[STRUCT_DATA_T:%.*]]) align 8 [[DATA:%.*]]) #[[ATTR0]] {1198// CHECK1-NEXT: entry:1199// CHECK1-NEXT: [[__RANGE2:%.*]] = alloca ptr, align 81200// CHECK1-NEXT: [[__END2:%.*]] = alloca ptr, align 81201// CHECK1-NEXT: [[__BEGIN2:%.*]] = alloca ptr, align 81202// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca ptr, align 81203// CHECK1-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca ptr, align 81204// CHECK1-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i64, align 81205// CHECK1-NEXT: [[DOTFLOOR_0_IV___BEGIN2:%.*]] = alloca i64, align 81206// CHECK1-NEXT: [[DOTSTRIPE_0_IV___BEGIN2:%.*]] = alloca i64, align 81207// CHECK1-NEXT: [[V:%.*]] = alloca double, align 81208// CHECK1-NEXT: [[ARRAY:%.*]] = getelementptr inbounds nuw [[STRUCT_DATA_T]], ptr [[DATA]], i32 0, i32 01209// CHECK1-NEXT: store ptr [[ARRAY]], ptr [[__RANGE2]], align 81210// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__RANGE2]], align 81211// CHECK1-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [12 x double], ptr [[TMP0]], i64 0, i64 01212// CHECK1-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY]], i64 121213// CHECK1-NEXT: store ptr [[ADD_PTR]], ptr [[__END2]], align 81214// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE2]], align 81215// CHECK1-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [12 x double], ptr [[TMP1]], i64 0, i64 01216// CHECK1-NEXT: store ptr [[ARRAYDECAY1]], ptr [[__BEGIN2]], align 81217// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE2]], align 81218// CHECK1-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [12 x double], ptr [[TMP2]], i64 0, i64 01219// CHECK1-NEXT: store ptr [[ARRAYDECAY2]], ptr [[DOTCAPTURE_EXPR_]], align 81220// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[__END2]], align 81221// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTCAPTURE_EXPR_3]], align 81222// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_3]], align 81223// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 81224// CHECK1-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint ptr [[TMP4]] to i641225// CHECK1-NEXT: [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint ptr [[TMP5]] to i641226// CHECK1-NEXT: [[SUB_PTR_SUB:%.*]] = sub i64 [[SUB_PTR_LHS_CAST]], [[SUB_PTR_RHS_CAST]]1227// CHECK1-NEXT: [[SUB_PTR_DIV:%.*]] = sdiv exact i64 [[SUB_PTR_SUB]], 81228// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i64 [[SUB_PTR_DIV]], 11229// CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 [[SUB]], 11230// CHECK1-NEXT: [[DIV:%.*]] = sdiv i64 [[ADD]], 11231// CHECK1-NEXT: [[SUB5:%.*]] = sub nsw i64 [[DIV]], 11232// CHECK1-NEXT: store i64 [[SUB5]], ptr [[DOTCAPTURE_EXPR_4]], align 81233// CHECK1-NEXT: store i64 0, ptr [[DOTFLOOR_0_IV___BEGIN2]], align 81234// CHECK1-NEXT: br label [[FOR_COND:%.*]]1235// CHECK1: for.cond:1236// CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTFLOOR_0_IV___BEGIN2]], align 81237// CHECK1-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_4]], align 81238// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP7]], 11239// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP6]], [[ADD6]]1240// CHECK1-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END18:%.*]]1241// CHECK1: for.body:1242// CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTFLOOR_0_IV___BEGIN2]], align 81243// CHECK1-NEXT: store i64 [[TMP8]], ptr [[DOTSTRIPE_0_IV___BEGIN2]], align 81244// CHECK1-NEXT: br label [[FOR_COND7:%.*]]1245// CHECK1: for.cond7:1246// CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTSTRIPE_0_IV___BEGIN2]], align 81247// CHECK1-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_4]], align 81248// CHECK1-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP10]], 11249// CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTFLOOR_0_IV___BEGIN2]], align 81250// CHECK1-NEXT: [[ADD9:%.*]] = add nsw i64 [[TMP11]], 51251// CHECK1-NEXT: [[CMP10:%.*]] = icmp slt i64 [[ADD8]], [[ADD9]]1252// CHECK1-NEXT: br i1 [[CMP10]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1253// CHECK1: cond.true:1254// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_4]], align 81255// CHECK1-NEXT: [[ADD11:%.*]] = add nsw i64 [[TMP12]], 11256// CHECK1-NEXT: br label [[COND_END:%.*]]1257// CHECK1: cond.false:1258// CHECK1-NEXT: [[TMP13:%.*]] = load i64, ptr [[DOTFLOOR_0_IV___BEGIN2]], align 81259// CHECK1-NEXT: [[ADD12:%.*]] = add nsw i64 [[TMP13]], 51260// CHECK1-NEXT: br label [[COND_END]]1261// CHECK1: cond.end:1262// CHECK1-NEXT: [[COND:%.*]] = phi i64 [ [[ADD11]], [[COND_TRUE]] ], [ [[ADD12]], [[COND_FALSE]] ]1263// CHECK1-NEXT: [[CMP13:%.*]] = icmp slt i64 [[TMP9]], [[COND]]1264// CHECK1-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END:%.*]]1265// CHECK1: for.body14:1266// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 81267// CHECK1-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTSTRIPE_0_IV___BEGIN2]], align 81268// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP15]], 11269// CHECK1-NEXT: [[ADD_PTR15:%.*]] = getelementptr inbounds double, ptr [[TMP14]], i64 [[MUL]]1270// CHECK1-NEXT: store ptr [[ADD_PTR15]], ptr [[__BEGIN2]], align 81271// CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[__BEGIN2]], align 81272// CHECK1-NEXT: [[TMP17:%.*]] = load double, ptr [[TMP16]], align 81273// CHECK1-NEXT: store double [[TMP17]], ptr [[V]], align 81274// CHECK1-NEXT: [[TMP18:%.*]] = load double, ptr [[V]], align 81275// CHECK1-NEXT: call void (...) @body(double noundef [[TMP18]])1276// CHECK1-NEXT: br label [[FOR_INC:%.*]]1277// CHECK1: for.inc:1278// CHECK1-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTSTRIPE_0_IV___BEGIN2]], align 81279// CHECK1-NEXT: [[INC:%.*]] = add nsw i64 [[TMP19]], 11280// CHECK1-NEXT: store i64 [[INC]], ptr [[DOTSTRIPE_0_IV___BEGIN2]], align 81281// CHECK1-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP25:![0-9]+]]1282// CHECK1: for.end:1283// CHECK1-NEXT: br label [[FOR_INC16:%.*]]1284// CHECK1: for.inc16:1285// CHECK1-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTFLOOR_0_IV___BEGIN2]], align 81286// CHECK1-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP20]], 51287// CHECK1-NEXT: store i64 [[ADD17]], ptr [[DOTFLOOR_0_IV___BEGIN2]], align 81288// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]1289// CHECK1: for.end18:1290// CHECK1-NEXT: ret void1291//1292//1293// CHECK1-LABEL: define dso_local void @foo10(1294// CHECK1-SAME: ptr noundef byval([[STRUCT_DATA_T:%.*]]) align 8 [[DATA:%.*]]) #[[ATTR0]] {1295// CHECK1-NEXT: entry:1296// CHECK1-NEXT: [[C:%.*]] = alloca double, align 81297// CHECK1-NEXT: [[__RANGE2:%.*]] = alloca ptr, align 81298// CHECK1-NEXT: [[__END2:%.*]] = alloca ptr, align 81299// CHECK1-NEXT: [[__BEGIN2:%.*]] = alloca ptr, align 81300// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca ptr, align 81301// CHECK1-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca ptr, align 81302// CHECK1-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i64, align 81303// CHECK1-NEXT: [[DOTFLOOR_0_IV___BEGIN2:%.*]] = alloca i64, align 81304// CHECK1-NEXT: [[DOTSTRIPE_0_IV___BEGIN2:%.*]] = alloca i64, align 81305// CHECK1-NEXT: [[V:%.*]] = alloca double, align 81306// CHECK1-NEXT: store double 4.200000e+01, ptr [[C]], align 81307// CHECK1-NEXT: [[ARRAY:%.*]] = getelementptr inbounds nuw [[STRUCT_DATA_T]], ptr [[DATA]], i32 0, i32 01308// CHECK1-NEXT: store ptr [[ARRAY]], ptr [[__RANGE2]], align 81309// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__RANGE2]], align 81310// CHECK1-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [12 x double], ptr [[TMP0]], i64 0, i64 01311// CHECK1-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY]], i64 121312// CHECK1-NEXT: store ptr [[ADD_PTR]], ptr [[__END2]], align 81313// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE2]], align 81314// CHECK1-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [12 x double], ptr [[TMP1]], i64 0, i64 01315// CHECK1-NEXT: store ptr [[ARRAYDECAY1]], ptr [[__BEGIN2]], align 81316// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE2]], align 81317// CHECK1-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [12 x double], ptr [[TMP2]], i64 0, i64 01318// CHECK1-NEXT: store ptr [[ARRAYDECAY2]], ptr [[DOTCAPTURE_EXPR_]], align 81319// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[__END2]], align 81320// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTCAPTURE_EXPR_3]], align 81321// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_3]], align 81322// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 81323// CHECK1-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint ptr [[TMP4]] to i641324// CHECK1-NEXT: [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint ptr [[TMP5]] to i641325// CHECK1-NEXT: [[SUB_PTR_SUB:%.*]] = sub i64 [[SUB_PTR_LHS_CAST]], [[SUB_PTR_RHS_CAST]]1326// CHECK1-NEXT: [[SUB_PTR_DIV:%.*]] = sdiv exact i64 [[SUB_PTR_SUB]], 81327// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i64 [[SUB_PTR_DIV]], 11328// CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 [[SUB]], 11329// CHECK1-NEXT: [[DIV:%.*]] = sdiv i64 [[ADD]], 11330// CHECK1-NEXT: [[SUB5:%.*]] = sub nsw i64 [[DIV]], 11331// CHECK1-NEXT: store i64 [[SUB5]], ptr [[DOTCAPTURE_EXPR_4]], align 81332// CHECK1-NEXT: store i64 0, ptr [[DOTFLOOR_0_IV___BEGIN2]], align 81333// CHECK1-NEXT: br label [[FOR_COND:%.*]]1334// CHECK1: for.cond:1335// CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTFLOOR_0_IV___BEGIN2]], align 81336// CHECK1-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_4]], align 81337// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP7]], 11338// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP6]], [[ADD6]]1339// CHECK1-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END18:%.*]]1340// CHECK1: for.body:1341// CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTFLOOR_0_IV___BEGIN2]], align 81342// CHECK1-NEXT: store i64 [[TMP8]], ptr [[DOTSTRIPE_0_IV___BEGIN2]], align 81343// CHECK1-NEXT: br label [[FOR_COND7:%.*]]1344// CHECK1: for.cond7:1345// CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTSTRIPE_0_IV___BEGIN2]], align 81346// CHECK1-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_4]], align 81347// CHECK1-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP10]], 11348// CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTFLOOR_0_IV___BEGIN2]], align 81349// CHECK1-NEXT: [[ADD9:%.*]] = add nsw i64 [[TMP11]], 51350// CHECK1-NEXT: [[CMP10:%.*]] = icmp slt i64 [[ADD8]], [[ADD9]]1351// CHECK1-NEXT: br i1 [[CMP10]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1352// CHECK1: cond.true:1353// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_4]], align 81354// CHECK1-NEXT: [[ADD11:%.*]] = add nsw i64 [[TMP12]], 11355// CHECK1-NEXT: br label [[COND_END:%.*]]1356// CHECK1: cond.false:1357// CHECK1-NEXT: [[TMP13:%.*]] = load i64, ptr [[DOTFLOOR_0_IV___BEGIN2]], align 81358// CHECK1-NEXT: [[ADD12:%.*]] = add nsw i64 [[TMP13]], 51359// CHECK1-NEXT: br label [[COND_END]]1360// CHECK1: cond.end:1361// CHECK1-NEXT: [[COND:%.*]] = phi i64 [ [[ADD11]], [[COND_TRUE]] ], [ [[ADD12]], [[COND_FALSE]] ]1362// CHECK1-NEXT: [[CMP13:%.*]] = icmp slt i64 [[TMP9]], [[COND]]1363// CHECK1-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END:%.*]]1364// CHECK1: for.body14:1365// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 81366// CHECK1-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTSTRIPE_0_IV___BEGIN2]], align 81367// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP15]], 11368// CHECK1-NEXT: [[ADD_PTR15:%.*]] = getelementptr inbounds double, ptr [[TMP14]], i64 [[MUL]]1369// CHECK1-NEXT: store ptr [[ADD_PTR15]], ptr [[__BEGIN2]], align 81370// CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[__BEGIN2]], align 81371// CHECK1-NEXT: [[TMP17:%.*]] = load double, ptr [[TMP16]], align 81372// CHECK1-NEXT: store double [[TMP17]], ptr [[V]], align 81373// CHECK1-NEXT: [[TMP18:%.*]] = load double, ptr [[C]], align 81374// CHECK1-NEXT: [[TMP19:%.*]] = load double, ptr [[V]], align 81375// CHECK1-NEXT: call void (...) @body(double noundef [[TMP18]], double noundef [[TMP19]])1376// CHECK1-NEXT: br label [[FOR_INC:%.*]]1377// CHECK1: for.inc:1378// CHECK1-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTSTRIPE_0_IV___BEGIN2]], align 81379// CHECK1-NEXT: [[INC:%.*]] = add nsw i64 [[TMP20]], 11380// CHECK1-NEXT: store i64 [[INC]], ptr [[DOTSTRIPE_0_IV___BEGIN2]], align 81381// CHECK1-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP27:![0-9]+]]1382// CHECK1: for.end:1383// CHECK1-NEXT: br label [[FOR_INC16:%.*]]1384// CHECK1: for.inc16:1385// CHECK1-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTFLOOR_0_IV___BEGIN2]], align 81386// CHECK1-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP21]], 51387// CHECK1-NEXT: store i64 [[ADD17]], ptr [[DOTFLOOR_0_IV___BEGIN2]], align 81388// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]1389// CHECK1: for.end18:1390// CHECK1-NEXT: ret void1391//1392//1393// CHECK1-LABEL: define internal void @_GLOBAL__sub_I_stripe_codegen.cpp(1394// CHECK1-SAME: ) #[[ATTR1]] section ".text.startup" {1395// CHECK1-NEXT: entry:1396// CHECK1-NEXT: call void @__cxx_global_var_init()1397// CHECK1-NEXT: ret void1398//1399//1400// CHECK2-LABEL: define internal void @__cxx_global_var_init(1401// CHECK2-SAME: ) #[[ATTR0:[0-9]+]] section ".text.startup" {1402// CHECK2-NEXT: entry:1403// CHECK2-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @s)1404// CHECK2-NEXT: ret void1405//1406//1407// CHECK2-LABEL: define linkonce_odr void @_ZN1SC1Ev(1408// CHECK2-SAME: ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {1409// CHECK2-NEXT: entry:1410// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81411// CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81412// CHECK2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81413// CHECK2-NEXT: call void @_ZN1SC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])1414// CHECK2-NEXT: ret void1415//1416//1417// CHECK2-LABEL: define linkonce_odr void @_ZN1SC2Ev(1418// CHECK2-SAME: ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1419// CHECK2-NEXT: entry:1420// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81421// CHECK2-NEXT: [[I2:%.*]] = alloca ptr, align 81422// CHECK2-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 41423// CHECK2-NEXT: [[DOTSTRIPE_0_IV_I:%.*]] = alloca i32, align 41424// CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81425// CHECK2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81426// CHECK2-NEXT: [[I:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 01427// CHECK2-NEXT: store i32 7, ptr [[I]], align 41428// CHECK2-NEXT: [[I3:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[THIS1]], i32 0, i32 01429// CHECK2-NEXT: store ptr [[I3]], ptr [[I2]], align 81430// CHECK2-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV_I]], align 41431// CHECK2-NEXT: br label [[FOR_COND:%.*]]1432// CHECK2: for.cond:1433// CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 41434// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 41435// CHECK2-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END12:%.*]]1436// CHECK2: for.body:1437// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 41438// CHECK2-NEXT: store i32 [[TMP1]], ptr [[DOTSTRIPE_0_IV_I]], align 41439// CHECK2-NEXT: br label [[FOR_COND4:%.*]]1440// CHECK2: for.cond4:1441// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 41442// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 41443// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 51444// CHECK2-NEXT: [[CMP5:%.*]] = icmp slt i32 4, [[ADD]]1445// CHECK2-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1446// CHECK2: cond.true:1447// CHECK2-NEXT: br label [[COND_END:%.*]]1448// CHECK2: cond.false:1449// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 41450// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP4]], 51451// CHECK2-NEXT: br label [[COND_END]]1452// CHECK2: cond.end:1453// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 4, [[COND_TRUE]] ], [ [[ADD6]], [[COND_FALSE]] ]1454// CHECK2-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP2]], [[COND]]1455// CHECK2-NEXT: br i1 [[CMP7]], label [[FOR_BODY8:%.*]], label [[FOR_END:%.*]]1456// CHECK2: for.body8:1457// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 41458// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP5]], 31459// CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 7, [[MUL]]1460// CHECK2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[I2]], align 81461// CHECK2-NEXT: store i32 [[ADD9]], ptr [[TMP6]], align 41462// CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[I2]], align 81463// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 41464// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP8]])1465// CHECK2-NEXT: br label [[FOR_INC:%.*]]1466// CHECK2: for.inc:1467// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 41468// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 11469// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTSTRIPE_0_IV_I]], align 41470// CHECK2-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP3:![0-9]+]]1471// CHECK2: for.end:1472// CHECK2-NEXT: br label [[FOR_INC10:%.*]]1473// CHECK2: for.inc10:1474// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 41475// CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP10]], 51476// CHECK2-NEXT: store i32 [[ADD11]], ptr [[DOTFLOOR_0_IV_I]], align 41477// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]1478// CHECK2: for.end12:1479// CHECK2-NEXT: ret void1480//1481//1482// CHECK2-LABEL: define dso_local void @body(1483// CHECK2-SAME: ...) #[[ATTR1]] {1484// CHECK2-NEXT: entry:1485// CHECK2-NEXT: ret void1486//1487//1488// CHECK2-LABEL: define dso_local void @foo1(1489// CHECK2-SAME: i32 noundef [[START:%.*]], i32 noundef [[END:%.*]], i32 noundef [[STEP:%.*]]) #[[ATTR1]] {1490// CHECK2-NEXT: entry:1491// CHECK2-NEXT: [[START_ADDR:%.*]] = alloca i32, align 41492// CHECK2-NEXT: [[END_ADDR:%.*]] = alloca i32, align 41493// CHECK2-NEXT: [[STEP_ADDR:%.*]] = alloca i32, align 41494// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 41495// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 41496// CHECK2-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 41497// CHECK2-NEXT: [[DOTNEW_STEP:%.*]] = alloca i32, align 41498// CHECK2-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 41499// CHECK2-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 41500// CHECK2-NEXT: [[DOTSTRIPE_0_IV_I:%.*]] = alloca i32, align 41501// CHECK2-NEXT: store i32 [[START]], ptr [[START_ADDR]], align 41502// CHECK2-NEXT: store i32 [[END]], ptr [[END_ADDR]], align 41503// CHECK2-NEXT: store i32 [[STEP]], ptr [[STEP_ADDR]], align 41504// CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[START_ADDR]], align 41505// CHECK2-NEXT: store i32 [[TMP0]], ptr [[I]], align 41506// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[START_ADDR]], align 41507// CHECK2-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 41508// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[END_ADDR]], align 41509// CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_1]], align 41510// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[STEP_ADDR]], align 41511// CHECK2-NEXT: store i32 [[TMP3]], ptr [[DOTNEW_STEP]], align 41512// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 41513// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41514// CHECK2-NEXT: [[SUB:%.*]] = sub i32 [[TMP4]], [[TMP5]]1515// CHECK2-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 11516// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 41517// CHECK2-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], [[TMP6]]1518// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 41519// CHECK2-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], [[TMP7]]1520// CHECK2-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 11521// CHECK2-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 41522// CHECK2-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV_I]], align 41523// CHECK2-NEXT: br label [[FOR_COND:%.*]]1524// CHECK2: for.cond:1525// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 41526// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 41527// CHECK2-NEXT: [[ADD5:%.*]] = add i32 [[TMP9]], 11528// CHECK2-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP8]], [[ADD5]]1529// CHECK2-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END17:%.*]]1530// CHECK2: for.body:1531// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 41532// CHECK2-NEXT: store i32 [[TMP10]], ptr [[DOTSTRIPE_0_IV_I]], align 41533// CHECK2-NEXT: br label [[FOR_COND6:%.*]]1534// CHECK2: for.cond6:1535// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 41536// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 41537// CHECK2-NEXT: [[ADD7:%.*]] = add i32 [[TMP12]], 11538// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 41539// CHECK2-NEXT: [[ADD8:%.*]] = add i32 [[TMP13]], 51540// CHECK2-NEXT: [[CMP9:%.*]] = icmp ult i32 [[ADD7]], [[ADD8]]1541// CHECK2-NEXT: br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1542// CHECK2: cond.true:1543// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 41544// CHECK2-NEXT: [[ADD10:%.*]] = add i32 [[TMP14]], 11545// CHECK2-NEXT: br label [[COND_END:%.*]]1546// CHECK2: cond.false:1547// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 41548// CHECK2-NEXT: [[ADD11:%.*]] = add i32 [[TMP15]], 51549// CHECK2-NEXT: br label [[COND_END]]1550// CHECK2: cond.end:1551// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ [[ADD10]], [[COND_TRUE]] ], [ [[ADD11]], [[COND_FALSE]] ]1552// CHECK2-NEXT: [[CMP12:%.*]] = icmp ult i32 [[TMP11]], [[COND]]1553// CHECK2-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END:%.*]]1554// CHECK2: for.body13:1555// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41556// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 41557// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 41558// CHECK2-NEXT: [[MUL:%.*]] = mul i32 [[TMP17]], [[TMP18]]1559// CHECK2-NEXT: [[ADD14:%.*]] = add i32 [[TMP16]], [[MUL]]1560// CHECK2-NEXT: store i32 [[ADD14]], ptr [[I]], align 41561// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 41562// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP19]])1563// CHECK2-NEXT: br label [[FOR_INC:%.*]]1564// CHECK2: for.inc:1565// CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 41566// CHECK2-NEXT: [[INC:%.*]] = add i32 [[TMP20]], 11567// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTSTRIPE_0_IV_I]], align 41568// CHECK2-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP6:![0-9]+]]1569// CHECK2: for.end:1570// CHECK2-NEXT: br label [[FOR_INC15:%.*]]1571// CHECK2: for.inc15:1572// CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 41573// CHECK2-NEXT: [[ADD16:%.*]] = add i32 [[TMP21]], 51574// CHECK2-NEXT: store i32 [[ADD16]], ptr [[DOTFLOOR_0_IV_I]], align 41575// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]1576// CHECK2: for.end17:1577// CHECK2-NEXT: ret void1578//1579//1580// CHECK2-LABEL: define dso_local void @foo10(1581// CHECK2-SAME: ptr noundef byval([[STRUCT_DATA_T:%.*]]) align 8 [[DATA:%.*]]) #[[ATTR1]] {1582// CHECK2-NEXT: entry:1583// CHECK2-NEXT: [[C:%.*]] = alloca double, align 81584// CHECK2-NEXT: [[__RANGE2:%.*]] = alloca ptr, align 81585// CHECK2-NEXT: [[__END2:%.*]] = alloca ptr, align 81586// CHECK2-NEXT: [[__BEGIN2:%.*]] = alloca ptr, align 81587// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca ptr, align 81588// CHECK2-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca ptr, align 81589// CHECK2-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i64, align 81590// CHECK2-NEXT: [[DOTFLOOR_0_IV___BEGIN2:%.*]] = alloca i64, align 81591// CHECK2-NEXT: [[DOTSTRIPE_0_IV___BEGIN2:%.*]] = alloca i64, align 81592// CHECK2-NEXT: [[V:%.*]] = alloca double, align 81593// CHECK2-NEXT: store double 4.200000e+01, ptr [[C]], align 81594// CHECK2-NEXT: [[ARRAY:%.*]] = getelementptr inbounds nuw [[STRUCT_DATA_T]], ptr [[DATA]], i32 0, i32 01595// CHECK2-NEXT: store ptr [[ARRAY]], ptr [[__RANGE2]], align 81596// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__RANGE2]], align 81597// CHECK2-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [12 x double], ptr [[TMP0]], i64 0, i64 01598// CHECK2-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY]], i64 121599// CHECK2-NEXT: store ptr [[ADD_PTR]], ptr [[__END2]], align 81600// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE2]], align 81601// CHECK2-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [12 x double], ptr [[TMP1]], i64 0, i64 01602// CHECK2-NEXT: store ptr [[ARRAYDECAY1]], ptr [[__BEGIN2]], align 81603// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE2]], align 81604// CHECK2-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [12 x double], ptr [[TMP2]], i64 0, i64 01605// CHECK2-NEXT: store ptr [[ARRAYDECAY2]], ptr [[DOTCAPTURE_EXPR_]], align 81606// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[__END2]], align 81607// CHECK2-NEXT: store ptr [[TMP3]], ptr [[DOTCAPTURE_EXPR_3]], align 81608// CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_3]], align 81609// CHECK2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 81610// CHECK2-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint ptr [[TMP4]] to i641611// CHECK2-NEXT: [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint ptr [[TMP5]] to i641612// CHECK2-NEXT: [[SUB_PTR_SUB:%.*]] = sub i64 [[SUB_PTR_LHS_CAST]], [[SUB_PTR_RHS_CAST]]1613// CHECK2-NEXT: [[SUB_PTR_DIV:%.*]] = sdiv exact i64 [[SUB_PTR_SUB]], 81614// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i64 [[SUB_PTR_DIV]], 11615// CHECK2-NEXT: [[ADD:%.*]] = add nsw i64 [[SUB]], 11616// CHECK2-NEXT: [[DIV:%.*]] = sdiv i64 [[ADD]], 11617// CHECK2-NEXT: [[SUB5:%.*]] = sub nsw i64 [[DIV]], 11618// CHECK2-NEXT: store i64 [[SUB5]], ptr [[DOTCAPTURE_EXPR_4]], align 81619// CHECK2-NEXT: store i64 0, ptr [[DOTFLOOR_0_IV___BEGIN2]], align 81620// CHECK2-NEXT: br label [[FOR_COND:%.*]]1621// CHECK2: for.cond:1622// CHECK2-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTFLOOR_0_IV___BEGIN2]], align 81623// CHECK2-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_4]], align 81624// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP7]], 11625// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP6]], [[ADD6]]1626// CHECK2-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END18:%.*]]1627// CHECK2: for.body:1628// CHECK2-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTFLOOR_0_IV___BEGIN2]], align 81629// CHECK2-NEXT: store i64 [[TMP8]], ptr [[DOTSTRIPE_0_IV___BEGIN2]], align 81630// CHECK2-NEXT: br label [[FOR_COND7:%.*]]1631// CHECK2: for.cond7:1632// CHECK2-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTSTRIPE_0_IV___BEGIN2]], align 81633// CHECK2-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_4]], align 81634// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP10]], 11635// CHECK2-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTFLOOR_0_IV___BEGIN2]], align 81636// CHECK2-NEXT: [[ADD9:%.*]] = add nsw i64 [[TMP11]], 51637// CHECK2-NEXT: [[CMP10:%.*]] = icmp slt i64 [[ADD8]], [[ADD9]]1638// CHECK2-NEXT: br i1 [[CMP10]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1639// CHECK2: cond.true:1640// CHECK2-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_4]], align 81641// CHECK2-NEXT: [[ADD11:%.*]] = add nsw i64 [[TMP12]], 11642// CHECK2-NEXT: br label [[COND_END:%.*]]1643// CHECK2: cond.false:1644// CHECK2-NEXT: [[TMP13:%.*]] = load i64, ptr [[DOTFLOOR_0_IV___BEGIN2]], align 81645// CHECK2-NEXT: [[ADD12:%.*]] = add nsw i64 [[TMP13]], 51646// CHECK2-NEXT: br label [[COND_END]]1647// CHECK2: cond.end:1648// CHECK2-NEXT: [[COND:%.*]] = phi i64 [ [[ADD11]], [[COND_TRUE]] ], [ [[ADD12]], [[COND_FALSE]] ]1649// CHECK2-NEXT: [[CMP13:%.*]] = icmp slt i64 [[TMP9]], [[COND]]1650// CHECK2-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END:%.*]]1651// CHECK2: for.body14:1652// CHECK2-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 81653// CHECK2-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTSTRIPE_0_IV___BEGIN2]], align 81654// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP15]], 11655// CHECK2-NEXT: [[ADD_PTR15:%.*]] = getelementptr inbounds double, ptr [[TMP14]], i64 [[MUL]]1656// CHECK2-NEXT: store ptr [[ADD_PTR15]], ptr [[__BEGIN2]], align 81657// CHECK2-NEXT: [[TMP16:%.*]] = load ptr, ptr [[__BEGIN2]], align 81658// CHECK2-NEXT: [[TMP17:%.*]] = load double, ptr [[TMP16]], align 81659// CHECK2-NEXT: store double [[TMP17]], ptr [[V]], align 81660// CHECK2-NEXT: [[TMP18:%.*]] = load double, ptr [[C]], align 81661// CHECK2-NEXT: [[TMP19:%.*]] = load double, ptr [[V]], align 81662// CHECK2-NEXT: call void (...) @body(double noundef [[TMP18]], double noundef [[TMP19]])1663// CHECK2-NEXT: br label [[FOR_INC:%.*]]1664// CHECK2: for.inc:1665// CHECK2-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTSTRIPE_0_IV___BEGIN2]], align 81666// CHECK2-NEXT: [[INC:%.*]] = add nsw i64 [[TMP20]], 11667// CHECK2-NEXT: store i64 [[INC]], ptr [[DOTSTRIPE_0_IV___BEGIN2]], align 81668// CHECK2-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP8:![0-9]+]]1669// CHECK2: for.end:1670// CHECK2-NEXT: br label [[FOR_INC16:%.*]]1671// CHECK2: for.inc16:1672// CHECK2-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTFLOOR_0_IV___BEGIN2]], align 81673// CHECK2-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP21]], 51674// CHECK2-NEXT: store i64 [[ADD17]], ptr [[DOTFLOOR_0_IV___BEGIN2]], align 81675// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]1676// CHECK2: for.end18:1677// CHECK2-NEXT: ret void1678//1679//1680// CHECK2-LABEL: define dso_local void @foo2(1681// CHECK2-SAME: i32 noundef [[START:%.*]], i32 noundef [[END:%.*]], i32 noundef [[STEP:%.*]]) #[[ATTR1]] {1682// CHECK2-NEXT: entry:1683// CHECK2-NEXT: [[START_ADDR:%.*]] = alloca i32, align 41684// CHECK2-NEXT: [[END_ADDR:%.*]] = alloca i32, align 41685// CHECK2-NEXT: [[STEP_ADDR:%.*]] = alloca i32, align 41686// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 41687// CHECK2-NEXT: [[J:%.*]] = alloca i32, align 41688// CHECK2-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 41689// CHECK2-NEXT: [[DOTFLOOR_1_IV_J:%.*]] = alloca i32, align 41690// CHECK2-NEXT: [[DOTSTRIPE_0_IV_I:%.*]] = alloca i32, align 41691// CHECK2-NEXT: [[DOTSTRIPE_1_IV_J:%.*]] = alloca i32, align 41692// CHECK2-NEXT: store i32 [[START]], ptr [[START_ADDR]], align 41693// CHECK2-NEXT: store i32 [[END]], ptr [[END_ADDR]], align 41694// CHECK2-NEXT: store i32 [[STEP]], ptr [[STEP_ADDR]], align 41695// CHECK2-NEXT: store i32 7, ptr [[I]], align 41696// CHECK2-NEXT: store i32 7, ptr [[J]], align 41697// CHECK2-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV_I]], align 41698// CHECK2-NEXT: br label [[FOR_COND:%.*]]1699// CHECK2: for.cond:1700// CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 41701// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 41702// CHECK2-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END30:%.*]]1703// CHECK2: for.body:1704// CHECK2-NEXT: store i32 0, ptr [[DOTFLOOR_1_IV_J]], align 41705// CHECK2-NEXT: br label [[FOR_COND1:%.*]]1706// CHECK2: for.cond1:1707// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 41708// CHECK2-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 41709// CHECK2-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END27:%.*]]1710// CHECK2: for.body3:1711// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 41712// CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTSTRIPE_0_IV_I]], align 41713// CHECK2-NEXT: br label [[FOR_COND4:%.*]]1714// CHECK2: for.cond4:1715// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 41716// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 41717// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], 51718// CHECK2-NEXT: [[CMP5:%.*]] = icmp slt i32 4, [[ADD]]1719// CHECK2-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1720// CHECK2: cond.true:1721// CHECK2-NEXT: br label [[COND_END:%.*]]1722// CHECK2: cond.false:1723// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 41724// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP5]], 51725// CHECK2-NEXT: br label [[COND_END]]1726// CHECK2: cond.end:1727// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 4, [[COND_TRUE]] ], [ [[ADD6]], [[COND_FALSE]] ]1728// CHECK2-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP3]], [[COND]]1729// CHECK2-NEXT: br i1 [[CMP7]], label [[FOR_BODY8:%.*]], label [[FOR_END24:%.*]]1730// CHECK2: for.body8:1731// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 41732// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 31733// CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 7, [[MUL]]1734// CHECK2-NEXT: store i32 [[ADD9]], ptr [[I]], align 41735// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 41736// CHECK2-NEXT: store i32 [[TMP7]], ptr [[DOTSTRIPE_1_IV_J]], align 41737// CHECK2-NEXT: br label [[FOR_COND10:%.*]]1738// CHECK2: for.cond10:1739// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTSTRIPE_1_IV_J]], align 41740// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 41741// CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP9]], 51742// CHECK2-NEXT: [[CMP12:%.*]] = icmp slt i32 4, [[ADD11]]1743// CHECK2-NEXT: br i1 [[CMP12]], label [[COND_TRUE13:%.*]], label [[COND_FALSE14:%.*]]1744// CHECK2: cond.true13:1745// CHECK2-NEXT: br label [[COND_END16:%.*]]1746// CHECK2: cond.false14:1747// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 41748// CHECK2-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP10]], 51749// CHECK2-NEXT: br label [[COND_END16]]1750// CHECK2: cond.end16:1751// CHECK2-NEXT: [[COND17:%.*]] = phi i32 [ 4, [[COND_TRUE13]] ], [ [[ADD15]], [[COND_FALSE14]] ]1752// CHECK2-NEXT: [[CMP18:%.*]] = icmp slt i32 [[TMP8]], [[COND17]]1753// CHECK2-NEXT: br i1 [[CMP18]], label [[FOR_BODY19:%.*]], label [[FOR_END:%.*]]1754// CHECK2: for.body19:1755// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTSTRIPE_1_IV_J]], align 41756// CHECK2-NEXT: [[MUL20:%.*]] = mul nsw i32 [[TMP11]], 31757// CHECK2-NEXT: [[ADD21:%.*]] = add nsw i32 7, [[MUL20]]1758// CHECK2-NEXT: store i32 [[ADD21]], ptr [[J]], align 41759// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 41760// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[J]], align 41761// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP12]], i32 noundef [[TMP13]])1762// CHECK2-NEXT: br label [[FOR_INC:%.*]]1763// CHECK2: for.inc:1764// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTSTRIPE_1_IV_J]], align 41765// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 11766// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTSTRIPE_1_IV_J]], align 41767// CHECK2-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP10:![0-9]+]]1768// CHECK2: for.end:1769// CHECK2-NEXT: br label [[FOR_INC22:%.*]]1770// CHECK2: for.inc22:1771// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 41772// CHECK2-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP15]], 11773// CHECK2-NEXT: store i32 [[INC23]], ptr [[DOTSTRIPE_0_IV_I]], align 41774// CHECK2-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP11:![0-9]+]]1775// CHECK2: for.end24:1776// CHECK2-NEXT: br label [[FOR_INC25:%.*]]1777// CHECK2: for.inc25:1778// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 41779// CHECK2-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP16]], 51780// CHECK2-NEXT: store i32 [[ADD26]], ptr [[DOTFLOOR_1_IV_J]], align 41781// CHECK2-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP12:![0-9]+]]1782// CHECK2: for.end27:1783// CHECK2-NEXT: br label [[FOR_INC28:%.*]]1784// CHECK2: for.inc28:1785// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 41786// CHECK2-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP17]], 51787// CHECK2-NEXT: store i32 [[ADD29]], ptr [[DOTFLOOR_0_IV_I]], align 41788// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]1789// CHECK2: for.end30:1790// CHECK2-NEXT: ret void1791//1792//1793// CHECK2-LABEL: define dso_local void @foo3(1794// CHECK2-SAME: ) #[[ATTR1]] {1795// CHECK2-NEXT: entry:1796// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41797// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 41798// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 41799// CHECK2-NEXT: [[J:%.*]] = alloca i32, align 41800// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 41801// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 41802// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41803// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41804// CHECK2-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 41805// CHECK2-NEXT: [[DOTFLOOR_1_IV_J:%.*]] = alloca i32, align 41806// CHECK2-NEXT: [[DOTSTRIPE_0_IV_I:%.*]] = alloca i32, align 41807// CHECK2-NEXT: [[DOTSTRIPE_1_IV_J:%.*]] = alloca i32, align 41808// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])1809// CHECK2-NEXT: store i32 7, ptr [[I]], align 41810// CHECK2-NEXT: store i32 7, ptr [[J]], align 41811// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 41812// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_UB]], align 41813// CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 41814// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41815// CHECK2-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1816// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41817// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 01818// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1819// CHECK2: cond.true:1820// CHECK2-NEXT: br label [[COND_END:%.*]]1821// CHECK2: cond.false:1822// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41823// CHECK2-NEXT: br label [[COND_END]]1824// CHECK2: cond.end:1825// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 0, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ]1826// CHECK2-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 41827// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41828// CHECK2-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 41829// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1830// CHECK2: omp.inner.for.cond:1831// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41832// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41833// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]1834// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1835// CHECK2: omp.inner.for.body:1836// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41837// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 51838// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]1839// CHECK2-NEXT: store i32 [[ADD]], ptr [[DOTFLOOR_0_IV_I]], align 41840// CHECK2-NEXT: store i32 0, ptr [[DOTFLOOR_1_IV_J]], align 41841// CHECK2-NEXT: br label [[FOR_COND:%.*]]1842// CHECK2: for.cond:1843// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 41844// CHECK2-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP7]], 41845// CHECK2-NEXT: br i1 [[CMP2]], label [[FOR_BODY:%.*]], label [[FOR_END32:%.*]]1846// CHECK2: for.body:1847// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 41848// CHECK2-NEXT: store i32 [[TMP8]], ptr [[DOTSTRIPE_0_IV_I]], align 41849// CHECK2-NEXT: br label [[FOR_COND3:%.*]]1850// CHECK2: for.cond3:1851// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 41852// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 41853// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 51854// CHECK2-NEXT: [[CMP5:%.*]] = icmp slt i32 4, [[ADD4]]1855// CHECK2-NEXT: br i1 [[CMP5]], label [[COND_TRUE6:%.*]], label [[COND_FALSE7:%.*]]1856// CHECK2: cond.true6:1857// CHECK2-NEXT: br label [[COND_END9:%.*]]1858// CHECK2: cond.false7:1859// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 41860// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP11]], 51861// CHECK2-NEXT: br label [[COND_END9]]1862// CHECK2: cond.end9:1863// CHECK2-NEXT: [[COND10:%.*]] = phi i32 [ 4, [[COND_TRUE6]] ], [ [[ADD8]], [[COND_FALSE7]] ]1864// CHECK2-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP9]], [[COND10]]1865// CHECK2-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END29:%.*]]1866// CHECK2: for.body12:1867// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 41868// CHECK2-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP12]], 31869// CHECK2-NEXT: [[ADD14:%.*]] = add nsw i32 7, [[MUL13]]1870// CHECK2-NEXT: store i32 [[ADD14]], ptr [[I]], align 41871// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 41872// CHECK2-NEXT: store i32 [[TMP13]], ptr [[DOTSTRIPE_1_IV_J]], align 41873// CHECK2-NEXT: br label [[FOR_COND15:%.*]]1874// CHECK2: for.cond15:1875// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTSTRIPE_1_IV_J]], align 41876// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 41877// CHECK2-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP15]], 51878// CHECK2-NEXT: [[CMP17:%.*]] = icmp slt i32 4, [[ADD16]]1879// CHECK2-NEXT: br i1 [[CMP17]], label [[COND_TRUE18:%.*]], label [[COND_FALSE19:%.*]]1880// CHECK2: cond.true18:1881// CHECK2-NEXT: br label [[COND_END21:%.*]]1882// CHECK2: cond.false19:1883// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 41884// CHECK2-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP16]], 51885// CHECK2-NEXT: br label [[COND_END21]]1886// CHECK2: cond.end21:1887// CHECK2-NEXT: [[COND22:%.*]] = phi i32 [ 4, [[COND_TRUE18]] ], [ [[ADD20]], [[COND_FALSE19]] ]1888// CHECK2-NEXT: [[CMP23:%.*]] = icmp slt i32 [[TMP14]], [[COND22]]1889// CHECK2-NEXT: br i1 [[CMP23]], label [[FOR_BODY24:%.*]], label [[FOR_END:%.*]]1890// CHECK2: for.body24:1891// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTSTRIPE_1_IV_J]], align 41892// CHECK2-NEXT: [[MUL25:%.*]] = mul nsw i32 [[TMP17]], 31893// CHECK2-NEXT: [[ADD26:%.*]] = add nsw i32 7, [[MUL25]]1894// CHECK2-NEXT: store i32 [[ADD26]], ptr [[J]], align 41895// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 41896// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[J]], align 41897// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP18]], i32 noundef [[TMP19]])1898// CHECK2-NEXT: br label [[FOR_INC:%.*]]1899// CHECK2: for.inc:1900// CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTSTRIPE_1_IV_J]], align 41901// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP20]], 11902// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTSTRIPE_1_IV_J]], align 41903// CHECK2-NEXT: br label [[FOR_COND15]], !llvm.loop [[LOOP14:![0-9]+]]1904// CHECK2: for.end:1905// CHECK2-NEXT: br label [[FOR_INC27:%.*]]1906// CHECK2: for.inc27:1907// CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 41908// CHECK2-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP21]], 11909// CHECK2-NEXT: store i32 [[INC28]], ptr [[DOTSTRIPE_0_IV_I]], align 41910// CHECK2-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP15:![0-9]+]]1911// CHECK2: for.end29:1912// CHECK2-NEXT: br label [[FOR_INC30:%.*]]1913// CHECK2: for.inc30:1914// CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 41915// CHECK2-NEXT: [[ADD31:%.*]] = add nsw i32 [[TMP22]], 51916// CHECK2-NEXT: store i32 [[ADD31]], ptr [[DOTFLOOR_1_IV_J]], align 41917// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]1918// CHECK2: for.end32:1919// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1920// CHECK2: omp.body.continue:1921// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1922// CHECK2: omp.inner.for.inc:1923// CHECK2-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41924// CHECK2-NEXT: [[ADD33:%.*]] = add nsw i32 [[TMP23]], 11925// CHECK2-NEXT: store i32 [[ADD33]], ptr [[DOTOMP_IV]], align 41926// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]1927// CHECK2: omp.inner.for.end:1928// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]1929// CHECK2: omp.loop.exit:1930// CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]])1931// CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP0]])1932// CHECK2-NEXT: ret void1933//1934//1935// CHECK2-LABEL: define dso_local void @foo4(1936// CHECK2-SAME: ) #[[ATTR1]] {1937// CHECK2-NEXT: entry:1938// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41939// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 41940// CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 41941// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 41942// CHECK2-NEXT: [[J:%.*]] = alloca i32, align 41943// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 41944// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 41945// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41946// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41947// CHECK2-NEXT: [[K:%.*]] = alloca i32, align 41948// CHECK2-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 41949// CHECK2-NEXT: [[DOTFLOOR_1_IV_J:%.*]] = alloca i32, align 41950// CHECK2-NEXT: [[DOTSTRIPE_0_IV_I:%.*]] = alloca i32, align 41951// CHECK2-NEXT: [[DOTSTRIPE_1_IV_J:%.*]] = alloca i32, align 41952// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])1953// CHECK2-NEXT: store i32 7, ptr [[I]], align 41954// CHECK2-NEXT: store i32 7, ptr [[J]], align 41955// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 41956// CHECK2-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 41957// CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 41958// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41959// CHECK2-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1960// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41961// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 31962// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1963// CHECK2: cond.true:1964// CHECK2-NEXT: br label [[COND_END:%.*]]1965// CHECK2: cond.false:1966// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41967// CHECK2-NEXT: br label [[COND_END]]1968// CHECK2: cond.end:1969// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ]1970// CHECK2-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 41971// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41972// CHECK2-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 41973// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1974// CHECK2: omp.inner.for.cond:1975// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41976// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41977// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]1978// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1979// CHECK2: omp.inner.for.body:1980// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41981// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP6]], 11982// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 31983// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 7, [[MUL]]1984// CHECK2-NEXT: store i32 [[ADD]], ptr [[K]], align 41985// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41986// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41987// CHECK2-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP8]], 11988// CHECK2-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 11989// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], [[MUL4]]1990// CHECK2-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 51991// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]1992// CHECK2-NEXT: store i32 [[ADD6]], ptr [[DOTFLOOR_0_IV_I]], align 41993// CHECK2-NEXT: store i32 0, ptr [[DOTFLOOR_1_IV_J]], align 41994// CHECK2-NEXT: br label [[FOR_COND:%.*]]1995// CHECK2: for.cond:1996// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 41997// CHECK2-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP9]], 41998// CHECK2-NEXT: br i1 [[CMP7]], label [[FOR_BODY:%.*]], label [[FOR_END37:%.*]]1999// CHECK2: for.body:2000// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 42001// CHECK2-NEXT: store i32 [[TMP10]], ptr [[DOTSTRIPE_0_IV_I]], align 42002// CHECK2-NEXT: br label [[FOR_COND8:%.*]]2003// CHECK2: for.cond8:2004// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 42005// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 42006// CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP12]], 52007// CHECK2-NEXT: [[CMP10:%.*]] = icmp slt i32 4, [[ADD9]]2008// CHECK2-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]]2009// CHECK2: cond.true11:2010// CHECK2-NEXT: br label [[COND_END14:%.*]]2011// CHECK2: cond.false12:2012// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 42013// CHECK2-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP13]], 52014// CHECK2-NEXT: br label [[COND_END14]]2015// CHECK2: cond.end14:2016// CHECK2-NEXT: [[COND15:%.*]] = phi i32 [ 4, [[COND_TRUE11]] ], [ [[ADD13]], [[COND_FALSE12]] ]2017// CHECK2-NEXT: [[CMP16:%.*]] = icmp slt i32 [[TMP11]], [[COND15]]2018// CHECK2-NEXT: br i1 [[CMP16]], label [[FOR_BODY17:%.*]], label [[FOR_END34:%.*]]2019// CHECK2: for.body17:2020// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 42021// CHECK2-NEXT: [[MUL18:%.*]] = mul nsw i32 [[TMP14]], 32022// CHECK2-NEXT: [[ADD19:%.*]] = add nsw i32 7, [[MUL18]]2023// CHECK2-NEXT: store i32 [[ADD19]], ptr [[I]], align 42024// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 42025// CHECK2-NEXT: store i32 [[TMP15]], ptr [[DOTSTRIPE_1_IV_J]], align 42026// CHECK2-NEXT: br label [[FOR_COND20:%.*]]2027// CHECK2: for.cond20:2028// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTSTRIPE_1_IV_J]], align 42029// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 42030// CHECK2-NEXT: [[ADD21:%.*]] = add nsw i32 [[TMP17]], 52031// CHECK2-NEXT: [[CMP22:%.*]] = icmp slt i32 4, [[ADD21]]2032// CHECK2-NEXT: br i1 [[CMP22]], label [[COND_TRUE23:%.*]], label [[COND_FALSE24:%.*]]2033// CHECK2: cond.true23:2034// CHECK2-NEXT: br label [[COND_END26:%.*]]2035// CHECK2: cond.false24:2036// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 42037// CHECK2-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP18]], 52038// CHECK2-NEXT: br label [[COND_END26]]2039// CHECK2: cond.end26:2040// CHECK2-NEXT: [[COND27:%.*]] = phi i32 [ 4, [[COND_TRUE23]] ], [ [[ADD25]], [[COND_FALSE24]] ]2041// CHECK2-NEXT: [[CMP28:%.*]] = icmp slt i32 [[TMP16]], [[COND27]]2042// CHECK2-NEXT: br i1 [[CMP28]], label [[FOR_BODY29:%.*]], label [[FOR_END:%.*]]2043// CHECK2: for.body29:2044// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTSTRIPE_1_IV_J]], align 42045// CHECK2-NEXT: [[MUL30:%.*]] = mul nsw i32 [[TMP19]], 32046// CHECK2-NEXT: [[ADD31:%.*]] = add nsw i32 7, [[MUL30]]2047// CHECK2-NEXT: store i32 [[ADD31]], ptr [[J]], align 42048// CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[I]], align 42049// CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[J]], align 42050// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP20]], i32 noundef [[TMP21]])2051// CHECK2-NEXT: br label [[FOR_INC:%.*]]2052// CHECK2: for.inc:2053// CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTSTRIPE_1_IV_J]], align 42054// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP22]], 12055// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTSTRIPE_1_IV_J]], align 42056// CHECK2-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP17:![0-9]+]]2057// CHECK2: for.end:2058// CHECK2-NEXT: br label [[FOR_INC32:%.*]]2059// CHECK2: for.inc32:2060// CHECK2-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 42061// CHECK2-NEXT: [[INC33:%.*]] = add nsw i32 [[TMP23]], 12062// CHECK2-NEXT: store i32 [[INC33]], ptr [[DOTSTRIPE_0_IV_I]], align 42063// CHECK2-NEXT: br label [[FOR_COND8]], !llvm.loop [[LOOP18:![0-9]+]]2064// CHECK2: for.end34:2065// CHECK2-NEXT: br label [[FOR_INC35:%.*]]2066// CHECK2: for.inc35:2067// CHECK2-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 42068// CHECK2-NEXT: [[ADD36:%.*]] = add nsw i32 [[TMP24]], 52069// CHECK2-NEXT: store i32 [[ADD36]], ptr [[DOTFLOOR_1_IV_J]], align 42070// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]2071// CHECK2: for.end37:2072// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]2073// CHECK2: omp.body.continue:2074// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]2075// CHECK2: omp.inner.for.inc:2076// CHECK2-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42077// CHECK2-NEXT: [[ADD38:%.*]] = add nsw i32 [[TMP25]], 12078// CHECK2-NEXT: store i32 [[ADD38]], ptr [[DOTOMP_IV]], align 42079// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]2080// CHECK2: omp.inner.for.end:2081// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]2082// CHECK2: omp.loop.exit:2083// CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]])2084// CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]])2085// CHECK2-NEXT: ret void2086//2087//2088// CHECK2-LABEL: define dso_local void @foo5(2089// CHECK2-SAME: ) #[[ATTR1]] {2090// CHECK2-NEXT: entry:2091// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 82092// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 42093// CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 42094// CHECK2-NEXT: [[_TMP2:%.*]] = alloca i32, align 42095// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 42096// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 42097// CHECK2-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 42098// CHECK2-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 82099// CHECK2-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 42100// CHECK2-NEXT: [[DOTSTRIPE_0_IV_I:%.*]] = alloca i32, align 42101// CHECK2-NEXT: [[J:%.*]] = alloca i32, align 42102// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 82103// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 82104// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 82105// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42106// CHECK2-NEXT: [[DOTFLOOR_0_IV_I11:%.*]] = alloca i32, align 42107// CHECK2-NEXT: [[DOTSTRIPE_0_IV_I12:%.*]] = alloca i32, align 42108// CHECK2-NEXT: [[J13:%.*]] = alloca i32, align 42109// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])2110// CHECK2-NEXT: store i32 7, ptr [[I]], align 42111// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP]], align 42112// CHECK2-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 42113// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP]], align 42114// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 52115// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 4, [[ADD]]2116// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2117// CHECK2: cond.true:2118// CHECK2-NEXT: br label [[COND_END:%.*]]2119// CHECK2: cond.false:2120// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP]], align 42121// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 52122// CHECK2-NEXT: br label [[COND_END]]2123// CHECK2: cond.end:2124// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 4, [[COND_TRUE]] ], [ [[ADD4]], [[COND_FALSE]] ]2125// CHECK2-NEXT: store i32 [[COND]], ptr [[DOTCAPTURE_EXPR_3]], align 42126// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 42127// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 42128// CHECK2-NEXT: [[SUB:%.*]] = sub i32 [[TMP4]], [[TMP5]]2129// CHECK2-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 12130// CHECK2-NEXT: [[ADD7:%.*]] = add i32 [[SUB6]], 12131// CHECK2-NEXT: [[DIV:%.*]] = udiv i32 [[ADD7]], 12132// CHECK2-NEXT: [[CONV:%.*]] = zext i32 [[DIV]] to i642133// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i64 1, [[CONV]]2134// CHECK2-NEXT: [[MUL8:%.*]] = mul nsw i64 [[MUL]], 42135// CHECK2-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL8]], 12136// CHECK2-NEXT: store i64 [[SUB9]], ptr [[DOTCAPTURE_EXPR_5]], align 82137// CHECK2-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV_I]], align 42138// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 42139// CHECK2-NEXT: store i32 [[TMP6]], ptr [[DOTSTRIPE_0_IV_I]], align 42140// CHECK2-NEXT: store i32 7, ptr [[J]], align 42141// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 42142// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 42143// CHECK2-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]]2144// CHECK2-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]2145// CHECK2: omp.precond.then:2146// CHECK2-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 82147// CHECK2-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 82148// CHECK2-NEXT: store i64 [[TMP9]], ptr [[DOTOMP_UB]], align 82149// CHECK2-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 82150// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 42151// CHECK2-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)2152// CHECK2-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 82153// CHECK2-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 82154// CHECK2-NEXT: [[CMP14:%.*]] = icmp sgt i64 [[TMP10]], [[TMP11]]2155// CHECK2-NEXT: br i1 [[CMP14]], label [[COND_TRUE15:%.*]], label [[COND_FALSE16:%.*]]2156// CHECK2: cond.true15:2157// CHECK2-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 82158// CHECK2-NEXT: br label [[COND_END17:%.*]]2159// CHECK2: cond.false16:2160// CHECK2-NEXT: [[TMP13:%.*]] = load i64, ptr [[DOTOMP_UB]], align 82161// CHECK2-NEXT: br label [[COND_END17]]2162// CHECK2: cond.end17:2163// CHECK2-NEXT: [[COND18:%.*]] = phi i64 [ [[TMP12]], [[COND_TRUE15]] ], [ [[TMP13]], [[COND_FALSE16]] ]2164// CHECK2-NEXT: store i64 [[COND18]], ptr [[DOTOMP_UB]], align 82165// CHECK2-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_LB]], align 82166// CHECK2-NEXT: store i64 [[TMP14]], ptr [[DOTOMP_IV]], align 82167// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]2168// CHECK2: omp.inner.for.cond:2169// CHECK2-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82170// CHECK2-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_UB]], align 82171// CHECK2-NEXT: [[CMP19:%.*]] = icmp sle i64 [[TMP15]], [[TMP16]]2172// CHECK2-NEXT: br i1 [[CMP19]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2173// CHECK2: omp.inner.for.body:2174// CHECK2-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82175// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 42176// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 42177// CHECK2-NEXT: [[SUB20:%.*]] = sub i32 [[TMP18]], [[TMP19]]2178// CHECK2-NEXT: [[SUB21:%.*]] = sub i32 [[SUB20]], 12179// CHECK2-NEXT: [[ADD22:%.*]] = add i32 [[SUB21]], 12180// CHECK2-NEXT: [[DIV23:%.*]] = udiv i32 [[ADD22]], 12181// CHECK2-NEXT: [[MUL24:%.*]] = mul i32 1, [[DIV23]]2182// CHECK2-NEXT: [[MUL25:%.*]] = mul i32 [[MUL24]], 42183// CHECK2-NEXT: [[CONV26:%.*]] = zext i32 [[MUL25]] to i642184// CHECK2-NEXT: [[DIV27:%.*]] = sdiv i64 [[TMP17]], [[CONV26]]2185// CHECK2-NEXT: [[MUL28:%.*]] = mul nsw i64 [[DIV27]], 52186// CHECK2-NEXT: [[ADD29:%.*]] = add nsw i64 0, [[MUL28]]2187// CHECK2-NEXT: [[CONV30:%.*]] = trunc i64 [[ADD29]] to i322188// CHECK2-NEXT: store i32 [[CONV30]], ptr [[DOTFLOOR_0_IV_I11]], align 42189// CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 42190// CHECK2-NEXT: [[CONV31:%.*]] = sext i32 [[TMP20]] to i642191// CHECK2-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82192// CHECK2-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82193// CHECK2-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 42194// CHECK2-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 42195// CHECK2-NEXT: [[SUB32:%.*]] = sub i32 [[TMP23]], [[TMP24]]2196// CHECK2-NEXT: [[SUB33:%.*]] = sub i32 [[SUB32]], 12197// CHECK2-NEXT: [[ADD34:%.*]] = add i32 [[SUB33]], 12198// CHECK2-NEXT: [[DIV35:%.*]] = udiv i32 [[ADD34]], 12199// CHECK2-NEXT: [[MUL36:%.*]] = mul i32 1, [[DIV35]]2200// CHECK2-NEXT: [[MUL37:%.*]] = mul i32 [[MUL36]], 42201// CHECK2-NEXT: [[CONV38:%.*]] = zext i32 [[MUL37]] to i642202// CHECK2-NEXT: [[DIV39:%.*]] = sdiv i64 [[TMP22]], [[CONV38]]2203// CHECK2-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 42204// CHECK2-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 42205// CHECK2-NEXT: [[SUB40:%.*]] = sub i32 [[TMP25]], [[TMP26]]2206// CHECK2-NEXT: [[SUB41:%.*]] = sub i32 [[SUB40]], 12207// CHECK2-NEXT: [[ADD42:%.*]] = add i32 [[SUB41]], 12208// CHECK2-NEXT: [[DIV43:%.*]] = udiv i32 [[ADD42]], 12209// CHECK2-NEXT: [[MUL44:%.*]] = mul i32 1, [[DIV43]]2210// CHECK2-NEXT: [[MUL45:%.*]] = mul i32 [[MUL44]], 42211// CHECK2-NEXT: [[CONV46:%.*]] = zext i32 [[MUL45]] to i642212// CHECK2-NEXT: [[MUL47:%.*]] = mul nsw i64 [[DIV39]], [[CONV46]]2213// CHECK2-NEXT: [[SUB48:%.*]] = sub nsw i64 [[TMP21]], [[MUL47]]2214// CHECK2-NEXT: [[DIV49:%.*]] = sdiv i64 [[SUB48]], 42215// CHECK2-NEXT: [[MUL50:%.*]] = mul nsw i64 [[DIV49]], 12216// CHECK2-NEXT: [[ADD51:%.*]] = add nsw i64 [[CONV31]], [[MUL50]]2217// CHECK2-NEXT: [[CONV52:%.*]] = trunc i64 [[ADD51]] to i322218// CHECK2-NEXT: store i32 [[CONV52]], ptr [[DOTSTRIPE_0_IV_I12]], align 42219// CHECK2-NEXT: [[TMP27:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82220// CHECK2-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82221// CHECK2-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 42222// CHECK2-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 42223// CHECK2-NEXT: [[SUB53:%.*]] = sub i32 [[TMP29]], [[TMP30]]2224// CHECK2-NEXT: [[SUB54:%.*]] = sub i32 [[SUB53]], 12225// CHECK2-NEXT: [[ADD55:%.*]] = add i32 [[SUB54]], 12226// CHECK2-NEXT: [[DIV56:%.*]] = udiv i32 [[ADD55]], 12227// CHECK2-NEXT: [[MUL57:%.*]] = mul i32 1, [[DIV56]]2228// CHECK2-NEXT: [[MUL58:%.*]] = mul i32 [[MUL57]], 42229// CHECK2-NEXT: [[CONV59:%.*]] = zext i32 [[MUL58]] to i642230// CHECK2-NEXT: [[DIV60:%.*]] = sdiv i64 [[TMP28]], [[CONV59]]2231// CHECK2-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 42232// CHECK2-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 42233// CHECK2-NEXT: [[SUB61:%.*]] = sub i32 [[TMP31]], [[TMP32]]2234// CHECK2-NEXT: [[SUB62:%.*]] = sub i32 [[SUB61]], 12235// CHECK2-NEXT: [[ADD63:%.*]] = add i32 [[SUB62]], 12236// CHECK2-NEXT: [[DIV64:%.*]] = udiv i32 [[ADD63]], 12237// CHECK2-NEXT: [[MUL65:%.*]] = mul i32 1, [[DIV64]]2238// CHECK2-NEXT: [[MUL66:%.*]] = mul i32 [[MUL65]], 42239// CHECK2-NEXT: [[CONV67:%.*]] = zext i32 [[MUL66]] to i642240// CHECK2-NEXT: [[MUL68:%.*]] = mul nsw i64 [[DIV60]], [[CONV67]]2241// CHECK2-NEXT: [[SUB69:%.*]] = sub nsw i64 [[TMP27]], [[MUL68]]2242// CHECK2-NEXT: [[TMP33:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82243// CHECK2-NEXT: [[TMP34:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82244// CHECK2-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 42245// CHECK2-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 42246// CHECK2-NEXT: [[SUB70:%.*]] = sub i32 [[TMP35]], [[TMP36]]2247// CHECK2-NEXT: [[SUB71:%.*]] = sub i32 [[SUB70]], 12248// CHECK2-NEXT: [[ADD72:%.*]] = add i32 [[SUB71]], 12249// CHECK2-NEXT: [[DIV73:%.*]] = udiv i32 [[ADD72]], 12250// CHECK2-NEXT: [[MUL74:%.*]] = mul i32 1, [[DIV73]]2251// CHECK2-NEXT: [[MUL75:%.*]] = mul i32 [[MUL74]], 42252// CHECK2-NEXT: [[CONV76:%.*]] = zext i32 [[MUL75]] to i642253// CHECK2-NEXT: [[DIV77:%.*]] = sdiv i64 [[TMP34]], [[CONV76]]2254// CHECK2-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 42255// CHECK2-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 42256// CHECK2-NEXT: [[SUB78:%.*]] = sub i32 [[TMP37]], [[TMP38]]2257// CHECK2-NEXT: [[SUB79:%.*]] = sub i32 [[SUB78]], 12258// CHECK2-NEXT: [[ADD80:%.*]] = add i32 [[SUB79]], 12259// CHECK2-NEXT: [[DIV81:%.*]] = udiv i32 [[ADD80]], 12260// CHECK2-NEXT: [[MUL82:%.*]] = mul i32 1, [[DIV81]]2261// CHECK2-NEXT: [[MUL83:%.*]] = mul i32 [[MUL82]], 42262// CHECK2-NEXT: [[CONV84:%.*]] = zext i32 [[MUL83]] to i642263// CHECK2-NEXT: [[MUL85:%.*]] = mul nsw i64 [[DIV77]], [[CONV84]]2264// CHECK2-NEXT: [[SUB86:%.*]] = sub nsw i64 [[TMP33]], [[MUL85]]2265// CHECK2-NEXT: [[DIV87:%.*]] = sdiv i64 [[SUB86]], 42266// CHECK2-NEXT: [[MUL88:%.*]] = mul nsw i64 [[DIV87]], 42267// CHECK2-NEXT: [[SUB89:%.*]] = sub nsw i64 [[SUB69]], [[MUL88]]2268// CHECK2-NEXT: [[MUL90:%.*]] = mul nsw i64 [[SUB89]], 32269// CHECK2-NEXT: [[ADD91:%.*]] = add nsw i64 7, [[MUL90]]2270// CHECK2-NEXT: [[CONV92:%.*]] = trunc i64 [[ADD91]] to i322271// CHECK2-NEXT: store i32 [[CONV92]], ptr [[J13]], align 42272// CHECK2-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I12]], align 42273// CHECK2-NEXT: [[MUL93:%.*]] = mul nsw i32 [[TMP39]], 32274// CHECK2-NEXT: [[ADD94:%.*]] = add nsw i32 7, [[MUL93]]2275// CHECK2-NEXT: store i32 [[ADD94]], ptr [[I]], align 42276// CHECK2-NEXT: [[TMP40:%.*]] = load i32, ptr [[I]], align 42277// CHECK2-NEXT: [[TMP41:%.*]] = load i32, ptr [[J13]], align 42278// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP40]], i32 noundef [[TMP41]])2279// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]2280// CHECK2: omp.body.continue:2281// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]2282// CHECK2: omp.inner.for.inc:2283// CHECK2-NEXT: [[TMP42:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82284// CHECK2-NEXT: [[ADD95:%.*]] = add nsw i64 [[TMP42]], 12285// CHECK2-NEXT: store i64 [[ADD95]], ptr [[DOTOMP_IV]], align 82286// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]2287// CHECK2: omp.inner.for.end:2288// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]2289// CHECK2: omp.loop.exit:2290// CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]])2291// CHECK2-NEXT: br label [[OMP_PRECOND_END]]2292// CHECK2: omp.precond.end:2293// CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]])2294// CHECK2-NEXT: ret void2295//2296//2297// CHECK2-LABEL: define dso_local void @foo6(2298// CHECK2-SAME: ) #[[ATTR1]] {2299// CHECK2-NEXT: entry:2300// CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @foo6.omp_outlined)2301// CHECK2-NEXT: ret void2302//2303//2304// CHECK2-LABEL: define internal void @foo6.omp_outlined(2305// CHECK2-SAME: ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4:[0-9]+]] {2306// CHECK2-NEXT: entry:2307// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 82308// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 82309// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 42310// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 42311// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 42312// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 42313// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 42314// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42315// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42316// CHECK2-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 42317// CHECK2-NEXT: [[DOTSTRIPE_0_IV_I:%.*]] = alloca i32, align 42318// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 82319// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 82320// CHECK2-NEXT: store i32 7, ptr [[I]], align 42321// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 42322// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_UB]], align 42323// CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 42324// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 42325// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 82326// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 42327// CHECK2-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)2328// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42329// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 02330// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2331// CHECK2: cond.true:2332// CHECK2-NEXT: br label [[COND_END:%.*]]2333// CHECK2: cond.false:2334// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42335// CHECK2-NEXT: br label [[COND_END]]2336// CHECK2: cond.end:2337// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 0, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]2338// CHECK2-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 42339// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42340// CHECK2-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 42341// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]2342// CHECK2: omp.inner.for.cond:2343// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42344// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42345// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]2346// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2347// CHECK2: omp.inner.for.body:2348// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42349// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 52350// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]2351// CHECK2-NEXT: store i32 [[ADD]], ptr [[DOTFLOOR_0_IV_I]], align 42352// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 42353// CHECK2-NEXT: store i32 [[TMP8]], ptr [[DOTSTRIPE_0_IV_I]], align 42354// CHECK2-NEXT: br label [[FOR_COND:%.*]]2355// CHECK2: for.cond:2356// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 42357// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 42358// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 52359// CHECK2-NEXT: [[CMP3:%.*]] = icmp slt i32 4, [[ADD2]]2360// CHECK2-NEXT: br i1 [[CMP3]], label [[COND_TRUE4:%.*]], label [[COND_FALSE5:%.*]]2361// CHECK2: cond.true4:2362// CHECK2-NEXT: br label [[COND_END7:%.*]]2363// CHECK2: cond.false5:2364// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 42365// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 52366// CHECK2-NEXT: br label [[COND_END7]]2367// CHECK2: cond.end7:2368// CHECK2-NEXT: [[COND8:%.*]] = phi i32 [ 4, [[COND_TRUE4]] ], [ [[ADD6]], [[COND_FALSE5]] ]2369// CHECK2-NEXT: [[CMP9:%.*]] = icmp slt i32 [[TMP9]], [[COND8]]2370// CHECK2-NEXT: br i1 [[CMP9]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]2371// CHECK2: for.body:2372// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 42373// CHECK2-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP12]], 32374// CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 7, [[MUL10]]2375// CHECK2-NEXT: store i32 [[ADD11]], ptr [[I]], align 42376// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 42377// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP13]])2378// CHECK2-NEXT: br label [[FOR_INC:%.*]]2379// CHECK2: for.inc:2380// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 42381// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 12382// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTSTRIPE_0_IV_I]], align 42383// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]2384// CHECK2: for.end:2385// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]2386// CHECK2: omp.body.continue:2387// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]2388// CHECK2: omp.inner.for.inc:2389// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42390// CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP15]], 12391// CHECK2-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 42392// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]2393// CHECK2: omp.inner.for.end:2394// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]2395// CHECK2: omp.loop.exit:2396// CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])2397// CHECK2-NEXT: ret void2398//2399//2400// CHECK2-LABEL: define dso_local void @foo8(2401// CHECK2-SAME: i32 noundef [[A:%.*]]) #[[ATTR1]] {2402// CHECK2-NEXT: entry:2403// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 42404// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 42405// CHECK2-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 42406// CHECK2-NEXT: [[DOTSTRIPE_0_IV_I:%.*]] = alloca i32, align 42407// CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 42408// CHECK2-NEXT: store i32 7, ptr [[I]], align 42409// CHECK2-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV_I]], align 42410// CHECK2-NEXT: br label [[FOR_COND:%.*]]2411// CHECK2: for.cond:2412// CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 42413// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 42414// CHECK2-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END24:%.*]]2415// CHECK2: for.body:2416// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 42417// CHECK2-NEXT: store i32 [[TMP1]], ptr [[DOTSTRIPE_0_IV_I]], align 42418// CHECK2-NEXT: br label [[FOR_COND1:%.*]]2419// CHECK2: for.cond1:2420// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 42421// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 42422// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 42423// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP4]], 02424// CHECK2-NEXT: br i1 [[CMP2]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2425// CHECK2: cond.true:2426// CHECK2-NEXT: br label [[COND_END:%.*]]2427// CHECK2: cond.false:2428// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[A_ADDR]], align 42429// CHECK2-NEXT: br label [[COND_END]]2430// CHECK2: cond.end:2431// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]2432// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[COND]]2433// CHECK2-NEXT: [[CMP3:%.*]] = icmp slt i32 4, [[ADD]]2434// CHECK2-NEXT: br i1 [[CMP3]], label [[COND_TRUE4:%.*]], label [[COND_FALSE5:%.*]]2435// CHECK2: cond.true4:2436// CHECK2-NEXT: br label [[COND_END12:%.*]]2437// CHECK2: cond.false5:2438// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 42439// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[A_ADDR]], align 42440// CHECK2-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], 02441// CHECK2-NEXT: br i1 [[CMP6]], label [[COND_TRUE7:%.*]], label [[COND_FALSE8:%.*]]2442// CHECK2: cond.true7:2443// CHECK2-NEXT: br label [[COND_END9:%.*]]2444// CHECK2: cond.false8:2445// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 42446// CHECK2-NEXT: br label [[COND_END9]]2447// CHECK2: cond.end9:2448// CHECK2-NEXT: [[COND10:%.*]] = phi i32 [ 1, [[COND_TRUE7]] ], [ [[TMP8]], [[COND_FALSE8]] ]2449// CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP6]], [[COND10]]2450// CHECK2-NEXT: br label [[COND_END12]]2451// CHECK2: cond.end12:2452// CHECK2-NEXT: [[COND13:%.*]] = phi i32 [ 4, [[COND_TRUE4]] ], [ [[ADD11]], [[COND_END9]] ]2453// CHECK2-NEXT: [[CMP14:%.*]] = icmp slt i32 [[TMP2]], [[COND13]]2454// CHECK2-NEXT: br i1 [[CMP14]], label [[FOR_BODY15:%.*]], label [[FOR_END:%.*]]2455// CHECK2: for.body15:2456// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 42457// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 32458// CHECK2-NEXT: [[ADD16:%.*]] = add nsw i32 7, [[MUL]]2459// CHECK2-NEXT: store i32 [[ADD16]], ptr [[I]], align 42460// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 42461// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP10]])2462// CHECK2-NEXT: br label [[FOR_INC:%.*]]2463// CHECK2: for.inc:2464// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 42465// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 12466// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTSTRIPE_0_IV_I]], align 42467// CHECK2-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP23:![0-9]+]]2468// CHECK2: for.end:2469// CHECK2-NEXT: br label [[FOR_INC17:%.*]]2470// CHECK2: for.inc17:2471// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[A_ADDR]], align 42472// CHECK2-NEXT: [[CMP18:%.*]] = icmp sle i32 [[TMP12]], 02473// CHECK2-NEXT: br i1 [[CMP18]], label [[COND_TRUE19:%.*]], label [[COND_FALSE20:%.*]]2474// CHECK2: cond.true19:2475// CHECK2-NEXT: br label [[COND_END21:%.*]]2476// CHECK2: cond.false20:2477// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[A_ADDR]], align 42478// CHECK2-NEXT: br label [[COND_END21]]2479// CHECK2: cond.end21:2480// CHECK2-NEXT: [[COND22:%.*]] = phi i32 [ 1, [[COND_TRUE19]] ], [ [[TMP13]], [[COND_FALSE20]] ]2481// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 42482// CHECK2-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP14]], [[COND22]]2483// CHECK2-NEXT: store i32 [[ADD23]], ptr [[DOTFLOOR_0_IV_I]], align 42484// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]2485// CHECK2: for.end24:2486// CHECK2-NEXT: ret void2487//2488//2489// CHECK2-LABEL: define dso_local void @foo9(2490// CHECK2-SAME: ptr noundef byval([[STRUCT_DATA_T:%.*]]) align 8 [[DATA:%.*]]) #[[ATTR1]] {2491// CHECK2-NEXT: entry:2492// CHECK2-NEXT: [[__RANGE2:%.*]] = alloca ptr, align 82493// CHECK2-NEXT: [[__END2:%.*]] = alloca ptr, align 82494// CHECK2-NEXT: [[__BEGIN2:%.*]] = alloca ptr, align 82495// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca ptr, align 82496// CHECK2-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca ptr, align 82497// CHECK2-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i64, align 82498// CHECK2-NEXT: [[DOTFLOOR_0_IV___BEGIN2:%.*]] = alloca i64, align 82499// CHECK2-NEXT: [[DOTSTRIPE_0_IV___BEGIN2:%.*]] = alloca i64, align 82500// CHECK2-NEXT: [[V:%.*]] = alloca double, align 82501// CHECK2-NEXT: [[ARRAY:%.*]] = getelementptr inbounds nuw [[STRUCT_DATA_T]], ptr [[DATA]], i32 0, i32 02502// CHECK2-NEXT: store ptr [[ARRAY]], ptr [[__RANGE2]], align 82503// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__RANGE2]], align 82504// CHECK2-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [12 x double], ptr [[TMP0]], i64 0, i64 02505// CHECK2-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY]], i64 122506// CHECK2-NEXT: store ptr [[ADD_PTR]], ptr [[__END2]], align 82507// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE2]], align 82508// CHECK2-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [12 x double], ptr [[TMP1]], i64 0, i64 02509// CHECK2-NEXT: store ptr [[ARRAYDECAY1]], ptr [[__BEGIN2]], align 82510// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE2]], align 82511// CHECK2-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [12 x double], ptr [[TMP2]], i64 0, i64 02512// CHECK2-NEXT: store ptr [[ARRAYDECAY2]], ptr [[DOTCAPTURE_EXPR_]], align 82513// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[__END2]], align 82514// CHECK2-NEXT: store ptr [[TMP3]], ptr [[DOTCAPTURE_EXPR_3]], align 82515// CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_3]], align 82516// CHECK2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 82517// CHECK2-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint ptr [[TMP4]] to i642518// CHECK2-NEXT: [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint ptr [[TMP5]] to i642519// CHECK2-NEXT: [[SUB_PTR_SUB:%.*]] = sub i64 [[SUB_PTR_LHS_CAST]], [[SUB_PTR_RHS_CAST]]2520// CHECK2-NEXT: [[SUB_PTR_DIV:%.*]] = sdiv exact i64 [[SUB_PTR_SUB]], 82521// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i64 [[SUB_PTR_DIV]], 12522// CHECK2-NEXT: [[ADD:%.*]] = add nsw i64 [[SUB]], 12523// CHECK2-NEXT: [[DIV:%.*]] = sdiv i64 [[ADD]], 12524// CHECK2-NEXT: [[SUB5:%.*]] = sub nsw i64 [[DIV]], 12525// CHECK2-NEXT: store i64 [[SUB5]], ptr [[DOTCAPTURE_EXPR_4]], align 82526// CHECK2-NEXT: store i64 0, ptr [[DOTFLOOR_0_IV___BEGIN2]], align 82527// CHECK2-NEXT: br label [[FOR_COND:%.*]]2528// CHECK2: for.cond:2529// CHECK2-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTFLOOR_0_IV___BEGIN2]], align 82530// CHECK2-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_4]], align 82531// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP7]], 12532// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP6]], [[ADD6]]2533// CHECK2-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END18:%.*]]2534// CHECK2: for.body:2535// CHECK2-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTFLOOR_0_IV___BEGIN2]], align 82536// CHECK2-NEXT: store i64 [[TMP8]], ptr [[DOTSTRIPE_0_IV___BEGIN2]], align 82537// CHECK2-NEXT: br label [[FOR_COND7:%.*]]2538// CHECK2: for.cond7:2539// CHECK2-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTSTRIPE_0_IV___BEGIN2]], align 82540// CHECK2-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_4]], align 82541// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP10]], 12542// CHECK2-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTFLOOR_0_IV___BEGIN2]], align 82543// CHECK2-NEXT: [[ADD9:%.*]] = add nsw i64 [[TMP11]], 52544// CHECK2-NEXT: [[CMP10:%.*]] = icmp slt i64 [[ADD8]], [[ADD9]]2545// CHECK2-NEXT: br i1 [[CMP10]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2546// CHECK2: cond.true:2547// CHECK2-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_4]], align 82548// CHECK2-NEXT: [[ADD11:%.*]] = add nsw i64 [[TMP12]], 12549// CHECK2-NEXT: br label [[COND_END:%.*]]2550// CHECK2: cond.false:2551// CHECK2-NEXT: [[TMP13:%.*]] = load i64, ptr [[DOTFLOOR_0_IV___BEGIN2]], align 82552// CHECK2-NEXT: [[ADD12:%.*]] = add nsw i64 [[TMP13]], 52553// CHECK2-NEXT: br label [[COND_END]]2554// CHECK2: cond.end:2555// CHECK2-NEXT: [[COND:%.*]] = phi i64 [ [[ADD11]], [[COND_TRUE]] ], [ [[ADD12]], [[COND_FALSE]] ]2556// CHECK2-NEXT: [[CMP13:%.*]] = icmp slt i64 [[TMP9]], [[COND]]2557// CHECK2-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END:%.*]]2558// CHECK2: for.body14:2559// CHECK2-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 82560// CHECK2-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTSTRIPE_0_IV___BEGIN2]], align 82561// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP15]], 12562// CHECK2-NEXT: [[ADD_PTR15:%.*]] = getelementptr inbounds double, ptr [[TMP14]], i64 [[MUL]]2563// CHECK2-NEXT: store ptr [[ADD_PTR15]], ptr [[__BEGIN2]], align 82564// CHECK2-NEXT: [[TMP16:%.*]] = load ptr, ptr [[__BEGIN2]], align 82565// CHECK2-NEXT: [[TMP17:%.*]] = load double, ptr [[TMP16]], align 82566// CHECK2-NEXT: store double [[TMP17]], ptr [[V]], align 82567// CHECK2-NEXT: [[TMP18:%.*]] = load double, ptr [[V]], align 82568// CHECK2-NEXT: call void (...) @body(double noundef [[TMP18]])2569// CHECK2-NEXT: br label [[FOR_INC:%.*]]2570// CHECK2: for.inc:2571// CHECK2-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTSTRIPE_0_IV___BEGIN2]], align 82572// CHECK2-NEXT: [[INC:%.*]] = add nsw i64 [[TMP19]], 12573// CHECK2-NEXT: store i64 [[INC]], ptr [[DOTSTRIPE_0_IV___BEGIN2]], align 82574// CHECK2-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP25:![0-9]+]]2575// CHECK2: for.end:2576// CHECK2-NEXT: br label [[FOR_INC16:%.*]]2577// CHECK2: for.inc16:2578// CHECK2-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTFLOOR_0_IV___BEGIN2]], align 82579// CHECK2-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP20]], 52580// CHECK2-NEXT: store i64 [[ADD17]], ptr [[DOTFLOOR_0_IV___BEGIN2]], align 82581// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]2582// CHECK2: for.end18:2583// CHECK2-NEXT: ret void2584//2585//2586// CHECK2-LABEL: define dso_local void @tfoo7(2587// CHECK2-SAME: ) #[[ATTR1]] {2588// CHECK2-NEXT: entry:2589// CHECK2-NEXT: call void @_Z4foo7IiTnT_Li3ETnS0_Li5EEvS0_S0_(i32 noundef 0, i32 noundef 42)2590// CHECK2-NEXT: ret void2591//2592//2593// CHECK2-LABEL: define linkonce_odr void @_Z4foo7IiTnT_Li3ETnS0_Li5EEvS0_S0_(2594// CHECK2-SAME: i32 noundef [[START:%.*]], i32 noundef [[END:%.*]]) #[[ATTR1]] comdat {2595// CHECK2-NEXT: entry:2596// CHECK2-NEXT: [[START_ADDR:%.*]] = alloca i32, align 42597// CHECK2-NEXT: [[END_ADDR:%.*]] = alloca i32, align 42598// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 42599// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 42600// CHECK2-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 42601// CHECK2-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 42602// CHECK2-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 42603// CHECK2-NEXT: [[DOTSTRIPE_0_IV_I:%.*]] = alloca i32, align 42604// CHECK2-NEXT: store i32 [[START]], ptr [[START_ADDR]], align 42605// CHECK2-NEXT: store i32 [[END]], ptr [[END_ADDR]], align 42606// CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[START_ADDR]], align 42607// CHECK2-NEXT: store i32 [[TMP0]], ptr [[I]], align 42608// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[START_ADDR]], align 42609// CHECK2-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 42610// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[END_ADDR]], align 42611// CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_1]], align 42612// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 42613// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 42614// CHECK2-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]2615// CHECK2-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 12616// CHECK2-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 32617// CHECK2-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 32618// CHECK2-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 12619// CHECK2-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 42620// CHECK2-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV_I]], align 42621// CHECK2-NEXT: br label [[FOR_COND:%.*]]2622// CHECK2: for.cond:2623// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 42624// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 42625// CHECK2-NEXT: [[ADD5:%.*]] = add i32 [[TMP6]], 12626// CHECK2-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP5]], [[ADD5]]2627// CHECK2-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END17:%.*]]2628// CHECK2: for.body:2629// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 42630// CHECK2-NEXT: store i32 [[TMP7]], ptr [[DOTSTRIPE_0_IV_I]], align 42631// CHECK2-NEXT: br label [[FOR_COND6:%.*]]2632// CHECK2: for.cond6:2633// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 42634// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 42635// CHECK2-NEXT: [[ADD7:%.*]] = add i32 [[TMP9]], 12636// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 42637// CHECK2-NEXT: [[ADD8:%.*]] = add i32 [[TMP10]], 52638// CHECK2-NEXT: [[CMP9:%.*]] = icmp ult i32 [[ADD7]], [[ADD8]]2639// CHECK2-NEXT: br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2640// CHECK2: cond.true:2641// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 42642// CHECK2-NEXT: [[ADD10:%.*]] = add i32 [[TMP11]], 12643// CHECK2-NEXT: br label [[COND_END:%.*]]2644// CHECK2: cond.false:2645// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 42646// CHECK2-NEXT: [[ADD11:%.*]] = add i32 [[TMP12]], 52647// CHECK2-NEXT: br label [[COND_END]]2648// CHECK2: cond.end:2649// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ [[ADD10]], [[COND_TRUE]] ], [ [[ADD11]], [[COND_FALSE]] ]2650// CHECK2-NEXT: [[CMP12:%.*]] = icmp ult i32 [[TMP8]], [[COND]]2651// CHECK2-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END:%.*]]2652// CHECK2: for.body13:2653// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 42654// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 42655// CHECK2-NEXT: [[MUL:%.*]] = mul i32 [[TMP14]], 32656// CHECK2-NEXT: [[ADD14:%.*]] = add i32 [[TMP13]], [[MUL]]2657// CHECK2-NEXT: store i32 [[ADD14]], ptr [[I]], align 42658// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 42659// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP15]])2660// CHECK2-NEXT: br label [[FOR_INC:%.*]]2661// CHECK2: for.inc:2662// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTSTRIPE_0_IV_I]], align 42663// CHECK2-NEXT: [[INC:%.*]] = add i32 [[TMP16]], 12664// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTSTRIPE_0_IV_I]], align 42665// CHECK2-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP27:![0-9]+]]2666// CHECK2: for.end:2667// CHECK2-NEXT: br label [[FOR_INC15:%.*]]2668// CHECK2: for.inc15:2669// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 42670// CHECK2-NEXT: [[ADD16:%.*]] = add i32 [[TMP17]], 52671// CHECK2-NEXT: store i32 [[ADD16]], ptr [[DOTFLOOR_0_IV_I]], align 42672// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]2673// CHECK2: for.end17:2674// CHECK2-NEXT: ret void2675//2676//2677// CHECK2-LABEL: define internal void @_GLOBAL__sub_I_stripe_codegen.cpp(2678// CHECK2-SAME: ) #[[ATTR0]] section ".text.startup" {2679// CHECK2-NEXT: entry:2680// CHECK2-NEXT: call void @__cxx_global_var_init()2681// CHECK2-NEXT: ret void2682//2683//.2684// CHECK1: [[LOOP3]] = distinct !{[[LOOP3]], [[META4:![0-9]+]]}2685// CHECK1: [[META4]] = !{!"llvm.loop.mustprogress"}2686// CHECK1: [[LOOP5]] = distinct !{[[LOOP5]], [[META4]]}2687// CHECK1: [[LOOP6]] = distinct !{[[LOOP6]], [[META4]]}2688// CHECK1: [[LOOP7]] = distinct !{[[LOOP7]], [[META4]]}2689// CHECK1: [[LOOP8]] = distinct !{[[LOOP8]], [[META4]]}2690// CHECK1: [[LOOP9]] = distinct !{[[LOOP9]], [[META4]]}2691// CHECK1: [[LOOP10]] = distinct !{[[LOOP10]], [[META4]]}2692// CHECK1: [[LOOP11]] = distinct !{[[LOOP11]], [[META4]]}2693// CHECK1: [[LOOP12]] = distinct !{[[LOOP12]], [[META4]]}2694// CHECK1: [[LOOP13]] = distinct !{[[LOOP13]], [[META4]]}2695// CHECK1: [[LOOP14]] = distinct !{[[LOOP14]], [[META4]]}2696// CHECK1: [[LOOP15]] = distinct !{[[LOOP15]], [[META4]]}2697// CHECK1: [[LOOP16]] = distinct !{[[LOOP16]], [[META4]]}2698// CHECK1: [[LOOP17]] = distinct !{[[LOOP17]], [[META4]]}2699// CHECK1: [[LOOP18]] = distinct !{[[LOOP18]], [[META4]]}2700// CHECK1: [[LOOP21]] = distinct !{[[LOOP21]], [[META4]]}2701// CHECK1: [[LOOP22]] = distinct !{[[LOOP22]], [[META4]]}2702// CHECK1: [[LOOP23]] = distinct !{[[LOOP23]], [[META4]]}2703// CHECK1: [[LOOP24]] = distinct !{[[LOOP24]], [[META4]]}2704// CHECK1: [[LOOP25]] = distinct !{[[LOOP25]], [[META4]]}2705// CHECK1: [[LOOP26]] = distinct !{[[LOOP26]], [[META4]]}2706// CHECK1: [[LOOP27]] = distinct !{[[LOOP27]], [[META4]]}2707// CHECK1: [[LOOP28]] = distinct !{[[LOOP28]], [[META4]]}2708//.2709// CHECK2: [[LOOP3]] = distinct !{[[LOOP3]], [[META4:![0-9]+]]}2710// CHECK2: [[META4]] = !{!"llvm.loop.mustprogress"}2711// CHECK2: [[LOOP5]] = distinct !{[[LOOP5]], [[META4]]}2712// CHECK2: [[LOOP6]] = distinct !{[[LOOP6]], [[META4]]}2713// CHECK2: [[LOOP7]] = distinct !{[[LOOP7]], [[META4]]}2714// CHECK2: [[LOOP8]] = distinct !{[[LOOP8]], [[META4]]}2715// CHECK2: [[LOOP9]] = distinct !{[[LOOP9]], [[META4]]}2716// CHECK2: [[LOOP10]] = distinct !{[[LOOP10]], [[META4]]}2717// CHECK2: [[LOOP11]] = distinct !{[[LOOP11]], [[META4]]}2718// CHECK2: [[LOOP12]] = distinct !{[[LOOP12]], [[META4]]}2719// CHECK2: [[LOOP13]] = distinct !{[[LOOP13]], [[META4]]}2720// CHECK2: [[LOOP14]] = distinct !{[[LOOP14]], [[META4]]}2721// CHECK2: [[LOOP15]] = distinct !{[[LOOP15]], [[META4]]}2722// CHECK2: [[LOOP16]] = distinct !{[[LOOP16]], [[META4]]}2723// CHECK2: [[LOOP17]] = distinct !{[[LOOP17]], [[META4]]}2724// CHECK2: [[LOOP18]] = distinct !{[[LOOP18]], [[META4]]}2725// CHECK2: [[LOOP19]] = distinct !{[[LOOP19]], [[META4]]}2726// CHECK2: [[LOOP20]] = distinct !{[[LOOP20]], [[META4]]}2727// CHECK2: [[LOOP23]] = distinct !{[[LOOP23]], [[META4]]}2728// CHECK2: [[LOOP24]] = distinct !{[[LOOP24]], [[META4]]}2729// CHECK2: [[LOOP25]] = distinct !{[[LOOP25]], [[META4]]}2730// CHECK2: [[LOOP26]] = distinct !{[[LOOP26]], [[META4]]}2731// CHECK2: [[LOOP27]] = distinct !{[[LOOP27]], [[META4]]}2732// CHECK2: [[LOOP28]] = distinct !{[[LOOP28]], [[META4]]}2733//.2734