11632 lines · cpp
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _2// Test host codegen.3// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK04// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s5// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK16// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK27// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s8// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK39 10// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s11// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s12// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY01 %s13// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY02 %s14// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s15// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY03 %s16 17// Test target codegen - host bc file has to be created first.18// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc19// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK20// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s21// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK122// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc23// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK224// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s25// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK326 27// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc28// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s29// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s30// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY11 %s31// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc32// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY12 %s33// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s34// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY13 %s35 36// expected-no-diagnostics37#ifndef HEADER38#define HEADER39 40template <typename tx, typename ty>41struct TT {42 tx X;43 ty Y;44};45#pragma omp declare target46int ga = 5;47#pragma omp end declare target48 49 50 51 52int foo(int n, double *ptr) {53 int a = 0;54 short aa = 0;55 float b[10];56 float bn[n];57 double c[5][10];58 double cn[5][n];59 TT<long long, char> d;60 const TT<int, int> e = {n, n};61 int *p __attribute__ ((aligned (64))) = &a;62 63#pragma omp target firstprivate(a, p, ga)64 {65 }66 67 // a is passed by value to tgt_target68 69 70#pragma omp target firstprivate(aa, b, bn, c, cn, d)71 {72 aa += 1;73 b[2] = 1.0;74 bn[3] = 1.0;75 c[1][2] = 1.0;76 cn[1][3] = 1.0;77 d.X = 1;78 d.Y = 1;79 }80 81 82 // firstprivate(aa) --> base_ptr = aa, ptr = aa, size = 2 (short)83 84 // firstprivate(b): base_ptr = &b[0], ptr = &b[0], size = 40 (sizeof(float)*10)85 86 // firstprivate(bn), 2 entries, n and bn: (1) base_ptr = n, ptr = n, size = 8 ; (2) base_ptr = &c[0], ptr = &c[0], size = n*sizeof(float)87 88 // firstprivate(c): base_ptr = &c[0], ptr = &c[0], size = 400 (5*10*sizeof(double))89 90 // firstprivate(cn), 3 entries, 5, n, cn: (1) base_ptr = 5, ptr = 5, size = 8; (2) (1) base_ptr = n, ptr = n, size = 8; (3) base_ptr = &cn[0], ptr = &cn[0], size = 5*n*sizeof(double)91 92 // firstprivate(d): base_ptr = &d, ptr = &d, size = 1693 94 95 // make sure that firstprivate variables are generated in all cases and that we use those instances for operations inside the96 // target region97 98 // firstprivate(aa): a_priv = a_in99 100 // firstprivate(b): memcpy(b_priv,b_in)101 102 103 // firstprivate(bn)104 105 // firstprivate(c)106 107 // firstprivate(cn)108 109 // firstprivate(d)110 111#pragma omp target firstprivate(ptr, e)112 {113 ptr[0] = e.X;114 ptr[0]++;115 }116 117 118 119 120 return a;121}122 123template <typename tx>124tx ftemplate(int n) {125 tx a = 0;126 tx b[10];127 128#pragma omp target firstprivate(a, b)129 {130 a += 1;131 b[2] += 1;132 }133 134 return a;135}136 137static int fstatic(int n) {138 int a = 0;139 char aaa = 0;140 int b[10];141 142#pragma omp target firstprivate(a, aaa, b)143 {144 a += 1;145 aaa += 1;146 b[2] += 1;147 }148 149 return a;150}151 152 153// firstprivate(a): a_priv = a_in154 155// firstprivate(aaa)156 157// firstprivate(b)158 159 160struct S1 {161 double a;162 163 int r1(int n) {164 int b = n + 1;165 short int c[2][n];166 167#pragma omp target firstprivate(b, c)168 {169 this->a = (double)b + 1.5;170 c[1][1] = ++a;171 }172 173 return c[1][1] + (int)b;174 }175 176 // on the host side, we first generate r1, then the static function and the template above177 178 // map(this: this ptr is implicitly captured (not firstprivate matter)179 180 // firstprivate(b): base_ptr = b, ptr = b, size = 4 (pass by-value)181 182 // firstprivate(c), 3 entries: 2, n, c183 184 // only check that we use the map types stored in the global variable185 186 187 188 // firstprivate(b)189 190 191 // firstprivate(c)192 193 // finish194 195 // static host function196 197 // firstprivate(a): by value198 199 // firstprivate(aaa): by value200 201 // firstprivate(b): base_ptr = &b[0], ptr= &b[0]202 203 // only check that the right sizes and map types are used204};205 206int bar(int n, double *ptr) {207 int a = 0;208 a += foo(n, ptr);209 S1 S;210 a += S.r1(n);211 a += fstatic(n);212 a += ftemplate<int>(n);213 214 return a;215}216 217// template host and device218 219 220// firstprivate(a): by value221 222// firstprivate(b): pointer223 224 225 226// firstprivate(a)227 228// firstprivate(b)229 230 231#endif232// CHECK-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg233// CHECK-SAME: () #[[ATTR5:[0-9]+]] {234// CHECK-NEXT: entry:235// CHECK-NEXT: call void @__tgt_register_requires(i64 1)236// CHECK-NEXT: ret void237// CHECK-64-LABEL: define {{[^@]+}}@_Z3fooiPd238// CHECK-64-SAME: (i32 noundef signext [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {239// CHECK-64-NEXT: entry:240// CHECK-64-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4241// CHECK-64-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 8242// CHECK-64-NEXT: [[A:%.*]] = alloca i32, align 4243// CHECK-64-NEXT: [[AA:%.*]] = alloca i16, align 2244// CHECK-64-NEXT: [[B:%.*]] = alloca [10 x float], align 4245// CHECK-64-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8246// CHECK-64-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8247// CHECK-64-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8248// CHECK-64-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8249// CHECK-64-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8250// CHECK-64-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4251// CHECK-64-NEXT: [[P:%.*]] = alloca i32*, align 64252// CHECK-64-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8253// CHECK-64-NEXT: [[GA_CASTED:%.*]] = alloca i64, align 8254// CHECK-64-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8255// CHECK-64-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8256// CHECK-64-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8257// CHECK-64-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8258// CHECK-64-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [9 x i8*], align 8259// CHECK-64-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [9 x i8*], align 8260// CHECK-64-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [9 x i8*], align 8261// CHECK-64-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8262// CHECK-64-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x i8*], align 8263// CHECK-64-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x i8*], align 8264// CHECK-64-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x i8*], align 8265// CHECK-64-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4266// CHECK-64-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 8267// CHECK-64-NEXT: store i32 0, i32* [[A]], align 4268// CHECK-64-NEXT: store i16 0, i16* [[AA]], align 2269// CHECK-64-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4270// CHECK-64-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64271// CHECK-64-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()272// CHECK-64-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8273// CHECK-64-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4274// CHECK-64-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8275// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4276// CHECK-64-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64277// CHECK-64-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]278// CHECK-64-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8279// CHECK-64-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8280// CHECK-64-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 0281// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4282// CHECK-64-NEXT: store i32 [[TMP6]], i32* [[X]], align 4283// CHECK-64-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 1284// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4285// CHECK-64-NEXT: store i32 [[TMP7]], i32* [[Y]], align 4286// CHECK-64-NEXT: store i32* [[A]], i32** [[P]], align 64287// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4288// CHECK-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*289// CHECK-64-NEXT: store i32 [[TMP8]], i32* [[CONV]], align 4290// CHECK-64-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8291// CHECK-64-NEXT: [[TMP10:%.*]] = load i32*, i32** [[P]], align 64292// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, i32* @ga, align 4293// CHECK-64-NEXT: [[CONV2:%.*]] = bitcast i64* [[GA_CASTED]] to i32*294// CHECK-64-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4295// CHECK-64-NEXT: [[TMP12:%.*]] = load i64, i64* [[GA_CASTED]], align 8296// CHECK-64-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0297// CHECK-64-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64*298// CHECK-64-NEXT: store i64 [[TMP9]], i64* [[TMP14]], align 8299// CHECK-64-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0300// CHECK-64-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64*301// CHECK-64-NEXT: store i64 [[TMP9]], i64* [[TMP16]], align 8302// CHECK-64-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0303// CHECK-64-NEXT: store i8* null, i8** [[TMP17]], align 8304// CHECK-64-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1305// CHECK-64-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32**306// CHECK-64-NEXT: store i32* [[TMP10]], i32** [[TMP19]], align 8307// CHECK-64-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1308// CHECK-64-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32**309// CHECK-64-NEXT: store i32* [[TMP10]], i32** [[TMP21]], align 8310// CHECK-64-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1311// CHECK-64-NEXT: store i8* null, i8** [[TMP22]], align 8312// CHECK-64-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2313// CHECK-64-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64*314// CHECK-64-NEXT: store i64 [[TMP12]], i64* [[TMP24]], align 8315// CHECK-64-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2316// CHECK-64-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64*317// CHECK-64-NEXT: store i64 [[TMP12]], i64* [[TMP26]], align 8318// CHECK-64-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2319// CHECK-64-NEXT: store i8* null, i8** [[TMP27]], align 8320// CHECK-64-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0321// CHECK-64-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0322// CHECK-64-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8323// CHECK-64-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0324// CHECK-64-NEXT: store i32 2, i32* [[TMP30]], align 4325// CHECK-64-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1326// CHECK-64-NEXT: store i32 3, i32* [[TMP31]], align 4327// CHECK-64-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2328// CHECK-64-NEXT: store i8** [[TMP28]], i8*** [[TMP32]], align 8329// CHECK-64-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3330// CHECK-64-NEXT: store i8** [[TMP29]], i8*** [[TMP33]], align 8331// CHECK-64-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4332// CHECK-64-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP34]], align 8333// CHECK-64-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5334// CHECK-64-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP35]], align 8335// CHECK-64-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6336// CHECK-64-NEXT: store i8** null, i8*** [[TMP36]], align 8337// CHECK-64-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7338// CHECK-64-NEXT: store i8** null, i8*** [[TMP37]], align 8339// CHECK-64-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8340// CHECK-64-NEXT: store i64 0, i64* [[TMP38]], align 8341// CHECK-64-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9342// CHECK-64-NEXT: store i64 0, i64* [[TMP39]], align 8343// CHECK-64-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10344// CHECK-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP40]], align 4345// CHECK-64-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11346// CHECK-64-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP41]], align 4347// CHECK-64-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12348// CHECK-64-NEXT: store i32 0, i32* [[TMP42]], align 4349// CHECK-64-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])350// CHECK-64-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0351// CHECK-64-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]352// CHECK-64: omp_offload.failed:353// CHECK-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63(i64 [[TMP9]], i32* [[TMP10]], i64 [[TMP12]]) #[[ATTR3:[0-9]+]]354// CHECK-64-NEXT: br label [[OMP_OFFLOAD_CONT]]355// CHECK-64: omp_offload.cont:356// CHECK-64-NEXT: [[TMP45:%.*]] = load i16, i16* [[AA]], align 2357// CHECK-64-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*358// CHECK-64-NEXT: store i16 [[TMP45]], i16* [[CONV3]], align 2359// CHECK-64-NEXT: [[TMP46:%.*]] = load i64, i64* [[AA_CASTED]], align 8360// CHECK-64-NEXT: [[TMP47:%.*]] = mul nuw i64 [[TMP1]], 4361// CHECK-64-NEXT: [[TMP48:%.*]] = mul nuw i64 5, [[TMP4]]362// CHECK-64-NEXT: [[TMP49:%.*]] = mul nuw i64 [[TMP48]], 8363// CHECK-64-NEXT: [[TMP50:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8*364// CHECK-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 bitcast ([9 x i64]* @.offload_sizes.1 to i8*), i64 72, i1 false)365// CHECK-64-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0366// CHECK-64-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i64*367// CHECK-64-NEXT: store i64 [[TMP46]], i64* [[TMP52]], align 8368// CHECK-64-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0369// CHECK-64-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to i64*370// CHECK-64-NEXT: store i64 [[TMP46]], i64* [[TMP54]], align 8371// CHECK-64-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0372// CHECK-64-NEXT: store i8* null, i8** [[TMP55]], align 8373// CHECK-64-NEXT: [[TMP56:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1374// CHECK-64-NEXT: [[TMP57:%.*]] = bitcast i8** [[TMP56]] to [10 x float]**375// CHECK-64-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP57]], align 8376// CHECK-64-NEXT: [[TMP58:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1377// CHECK-64-NEXT: [[TMP59:%.*]] = bitcast i8** [[TMP58]] to [10 x float]**378// CHECK-64-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP59]], align 8379// CHECK-64-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 1380// CHECK-64-NEXT: store i8* null, i8** [[TMP60]], align 8381// CHECK-64-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2382// CHECK-64-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64*383// CHECK-64-NEXT: store i64 [[TMP1]], i64* [[TMP62]], align 8384// CHECK-64-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2385// CHECK-64-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64*386// CHECK-64-NEXT: store i64 [[TMP1]], i64* [[TMP64]], align 8387// CHECK-64-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 2388// CHECK-64-NEXT: store i8* null, i8** [[TMP65]], align 8389// CHECK-64-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 3390// CHECK-64-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to float**391// CHECK-64-NEXT: store float* [[VLA]], float** [[TMP67]], align 8392// CHECK-64-NEXT: [[TMP68:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 3393// CHECK-64-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to float**394// CHECK-64-NEXT: store float* [[VLA]], float** [[TMP69]], align 8395// CHECK-64-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3396// CHECK-64-NEXT: store i64 [[TMP47]], i64* [[TMP70]], align 8397// CHECK-64-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 3398// CHECK-64-NEXT: store i8* null, i8** [[TMP71]], align 8399// CHECK-64-NEXT: [[TMP72:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 4400// CHECK-64-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to [5 x [10 x double]]**401// CHECK-64-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP73]], align 8402// CHECK-64-NEXT: [[TMP74:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 4403// CHECK-64-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to [5 x [10 x double]]**404// CHECK-64-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP75]], align 8405// CHECK-64-NEXT: [[TMP76:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 4406// CHECK-64-NEXT: store i8* null, i8** [[TMP76]], align 8407// CHECK-64-NEXT: [[TMP77:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 5408// CHECK-64-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64*409// CHECK-64-NEXT: store i64 5, i64* [[TMP78]], align 8410// CHECK-64-NEXT: [[TMP79:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 5411// CHECK-64-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i64*412// CHECK-64-NEXT: store i64 5, i64* [[TMP80]], align 8413// CHECK-64-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 5414// CHECK-64-NEXT: store i8* null, i8** [[TMP81]], align 8415// CHECK-64-NEXT: [[TMP82:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 6416// CHECK-64-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64*417// CHECK-64-NEXT: store i64 [[TMP4]], i64* [[TMP83]], align 8418// CHECK-64-NEXT: [[TMP84:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 6419// CHECK-64-NEXT: [[TMP85:%.*]] = bitcast i8** [[TMP84]] to i64*420// CHECK-64-NEXT: store i64 [[TMP4]], i64* [[TMP85]], align 8421// CHECK-64-NEXT: [[TMP86:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 6422// CHECK-64-NEXT: store i8* null, i8** [[TMP86]], align 8423// CHECK-64-NEXT: [[TMP87:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 7424// CHECK-64-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to double**425// CHECK-64-NEXT: store double* [[VLA1]], double** [[TMP88]], align 8426// CHECK-64-NEXT: [[TMP89:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 7427// CHECK-64-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to double**428// CHECK-64-NEXT: store double* [[VLA1]], double** [[TMP90]], align 8429// CHECK-64-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7430// CHECK-64-NEXT: store i64 [[TMP49]], i64* [[TMP91]], align 8431// CHECK-64-NEXT: [[TMP92:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 7432// CHECK-64-NEXT: store i8* null, i8** [[TMP92]], align 8433// CHECK-64-NEXT: [[TMP93:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 8434// CHECK-64-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to %struct.TT**435// CHECK-64-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP94]], align 8436// CHECK-64-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 8437// CHECK-64-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to %struct.TT**438// CHECK-64-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP96]], align 8439// CHECK-64-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 8440// CHECK-64-NEXT: store i8* null, i8** [[TMP97]], align 8441// CHECK-64-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0442// CHECK-64-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0443// CHECK-64-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0444// CHECK-64-NEXT: [[KERNEL_ARGS7:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8445// CHECK-64-NEXT: [[TMP101:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 0446// CHECK-64-NEXT: store i32 2, i32* [[TMP101]], align 4447// CHECK-64-NEXT: [[TMP102:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 1448// CHECK-64-NEXT: store i32 9, i32* [[TMP102]], align 4449// CHECK-64-NEXT: [[TMP103:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 2450// CHECK-64-NEXT: store i8** [[TMP98]], i8*** [[TMP103]], align 8451// CHECK-64-NEXT: [[TMP104:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 3452// CHECK-64-NEXT: store i8** [[TMP99]], i8*** [[TMP104]], align 8453// CHECK-64-NEXT: [[TMP105:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 4454// CHECK-64-NEXT: store i64* [[TMP100]], i64** [[TMP105]], align 8455// CHECK-64-NEXT: [[TMP106:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 5456// CHECK-64-NEXT: store i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.2, i32 0, i32 0), i64** [[TMP106]], align 8457// CHECK-64-NEXT: [[TMP107:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 6458// CHECK-64-NEXT: store i8** null, i8*** [[TMP107]], align 8459// CHECK-64-NEXT: [[TMP108:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 7460// CHECK-64-NEXT: store i8** null, i8*** [[TMP108]], align 8461// CHECK-64-NEXT: [[TMP109:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 8462// CHECK-64-NEXT: store i64 0, i64* [[TMP109]], align 8463// CHECK-64-NEXT: [[TMP110:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 9464// CHECK-64-NEXT: store i64 0, i64* [[TMP110]], align 8465// CHECK-64-NEXT: [[TMP111:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 10466// CHECK-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP111]], align 4467// CHECK-64-NEXT: [[TMP112:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 11468// CHECK-64-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP112]], align 4469// CHECK-64-NEXT: [[TMP113:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 12470// CHECK-64-NEXT: store i32 0, i32* [[TMP113]], align 4471// CHECK-64-NEXT: [[TMP114:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]])472// CHECK-64-NEXT: [[TMP115:%.*]] = icmp ne i32 [[TMP114]], 0473// CHECK-64-NEXT: br i1 [[TMP115]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]]474// CHECK-64: omp_offload.failed8:475// CHECK-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70(i64 [[TMP46]], [10 x float]* [[B]], i64 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP4]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]476// CHECK-64-NEXT: br label [[OMP_OFFLOAD_CONT9]]477// CHECK-64: omp_offload.cont9:478// CHECK-64-NEXT: [[TMP116:%.*]] = load double*, double** [[PTR_ADDR]], align 8479// CHECK-64-NEXT: [[TMP117:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0480// CHECK-64-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to double**481// CHECK-64-NEXT: store double* [[TMP116]], double** [[TMP118]], align 8482// CHECK-64-NEXT: [[TMP119:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0483// CHECK-64-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to double**484// CHECK-64-NEXT: store double* [[TMP116]], double** [[TMP120]], align 8485// CHECK-64-NEXT: [[TMP121:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0486// CHECK-64-NEXT: store i8* null, i8** [[TMP121]], align 8487// CHECK-64-NEXT: [[TMP122:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1488// CHECK-64-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to %struct.TT.0**489// CHECK-64-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[TMP123]], align 8490// CHECK-64-NEXT: [[TMP124:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 1491// CHECK-64-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to %struct.TT.0**492// CHECK-64-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[TMP125]], align 8493// CHECK-64-NEXT: [[TMP126:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1494// CHECK-64-NEXT: store i8* null, i8** [[TMP126]], align 8495// CHECK-64-NEXT: [[TMP127:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0496// CHECK-64-NEXT: [[TMP128:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0497// CHECK-64-NEXT: [[KERNEL_ARGS13:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8498// CHECK-64-NEXT: [[TMP129:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 0499// CHECK-64-NEXT: store i32 2, i32* [[TMP129]], align 4500// CHECK-64-NEXT: [[TMP130:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 1501// CHECK-64-NEXT: store i32 2, i32* [[TMP130]], align 4502// CHECK-64-NEXT: [[TMP131:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 2503// CHECK-64-NEXT: store i8** [[TMP127]], i8*** [[TMP131]], align 8504// CHECK-64-NEXT: [[TMP132:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 3505// CHECK-64-NEXT: store i8** [[TMP128]], i8*** [[TMP132]], align 8506// CHECK-64-NEXT: [[TMP133:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 4507// CHECK-64-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.3, i32 0, i32 0), i64** [[TMP133]], align 8508// CHECK-64-NEXT: [[TMP134:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 5509// CHECK-64-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.4, i32 0, i32 0), i64** [[TMP134]], align 8510// CHECK-64-NEXT: [[TMP135:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 6511// CHECK-64-NEXT: store i8** null, i8*** [[TMP135]], align 8512// CHECK-64-NEXT: [[TMP136:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 7513// CHECK-64-NEXT: store i8** null, i8*** [[TMP136]], align 8514// CHECK-64-NEXT: [[TMP137:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 8515// CHECK-64-NEXT: store i64 0, i64* [[TMP137]], align 8516// CHECK-64-NEXT: [[TMP138:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 9517// CHECK-64-NEXT: store i64 0, i64* [[TMP138]], align 8518// CHECK-64-NEXT: [[TMP139:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 10519// CHECK-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP139]], align 4520// CHECK-64-NEXT: [[TMP140:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 11521// CHECK-64-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP140]], align 4522// CHECK-64-NEXT: [[TMP141:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 12523// CHECK-64-NEXT: store i32 0, i32* [[TMP141]], align 4524// CHECK-64-NEXT: [[TMP142:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]])525// CHECK-64-NEXT: [[TMP143:%.*]] = icmp ne i32 [[TMP142]], 0526// CHECK-64-NEXT: br i1 [[TMP143]], label [[OMP_OFFLOAD_FAILED14:%.*]], label [[OMP_OFFLOAD_CONT15:%.*]]527// CHECK-64: omp_offload.failed14:528// CHECK-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111(double* [[TMP116]], %struct.TT.0* [[E]]) #[[ATTR3]]529// CHECK-64-NEXT: br label [[OMP_OFFLOAD_CONT15]]530// CHECK-64: omp_offload.cont15:531// CHECK-64-NEXT: [[TMP144:%.*]] = load i32, i32* [[A]], align 4532// CHECK-64-NEXT: [[TMP145:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8533// CHECK-64-NEXT: call void @llvm.stackrestore(i8* [[TMP145]])534// CHECK-64-NEXT: ret i32 [[TMP144]]535// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63536// CHECK-64-SAME: (i64 noundef [[A:%.*]], i32* noundef [[P:%.*]], i64 noundef [[GA:%.*]]) #[[ATTR2:[0-9]+]] {537// CHECK-64-NEXT: entry:538// CHECK-64-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8539// CHECK-64-NEXT: [[P_ADDR:%.*]] = alloca i32*, align 8540// CHECK-64-NEXT: [[GA_ADDR:%.*]] = alloca i64, align 8541// CHECK-64-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8542// CHECK-64-NEXT: store i32* [[P]], i32** [[P_ADDR]], align 8543// CHECK-64-NEXT: store i64 [[GA]], i64* [[GA_ADDR]], align 8544// CHECK-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*545// CHECK-64-NEXT: [[CONV1:%.*]] = bitcast i64* [[GA_ADDR]] to i32*546// CHECK-64-NEXT: ret void547// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70548// CHECK-64-SAME: (i64 noundef [[AA:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {549// CHECK-64-NEXT: entry:550// CHECK-64-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8551// CHECK-64-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8552// CHECK-64-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8553// CHECK-64-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8554// CHECK-64-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8555// CHECK-64-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8556// CHECK-64-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8557// CHECK-64-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8558// CHECK-64-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8559// CHECK-64-NEXT: [[B5:%.*]] = alloca [10 x float], align 4560// CHECK-64-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8561// CHECK-64-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8562// CHECK-64-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 8563// CHECK-64-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8564// CHECK-64-NEXT: [[__VLA_EXPR2:%.*]] = alloca i64, align 8565// CHECK-64-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 8566// CHECK-64-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8567// CHECK-64-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8568// CHECK-64-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8569// CHECK-64-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8570// CHECK-64-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8571// CHECK-64-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8572// CHECK-64-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8573// CHECK-64-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8574// CHECK-64-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8575// CHECK-64-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*576// CHECK-64-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8577// CHECK-64-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8578// CHECK-64-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8579// CHECK-64-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8580// CHECK-64-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8581// CHECK-64-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8582// CHECK-64-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8583// CHECK-64-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8584// CHECK-64-NEXT: [[TMP8:%.*]] = bitcast [10 x float]* [[B5]] to i8*585// CHECK-64-NEXT: [[TMP9:%.*]] = bitcast [10 x float]* [[TMP0]] to i8*586// CHECK-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 40, i1 false)587// CHECK-64-NEXT: [[TMP10:%.*]] = call i8* @llvm.stacksave()588// CHECK-64-NEXT: store i8* [[TMP10]], i8** [[SAVED_STACK]], align 8589// CHECK-64-NEXT: [[VLA6:%.*]] = alloca float, i64 [[TMP1]], align 4590// CHECK-64-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8591// CHECK-64-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP1]], 4592// CHECK-64-NEXT: [[TMP12:%.*]] = bitcast float* [[VLA6]] to i8*593// CHECK-64-NEXT: [[TMP13:%.*]] = bitcast float* [[TMP2]] to i8*594// CHECK-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 [[TMP11]], i1 false)595// CHECK-64-NEXT: [[TMP14:%.*]] = bitcast [5 x [10 x double]]* [[C7]] to i8*596// CHECK-64-NEXT: [[TMP15:%.*]] = bitcast [5 x [10 x double]]* [[TMP3]] to i8*597// CHECK-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP14]], i8* align 8 [[TMP15]], i64 400, i1 false)598// CHECK-64-NEXT: [[TMP16:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]]599// CHECK-64-NEXT: [[VLA8:%.*]] = alloca double, i64 [[TMP16]], align 8600// CHECK-64-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8601// CHECK-64-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR2]], align 8602// CHECK-64-NEXT: [[TMP17:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]]603// CHECK-64-NEXT: [[TMP18:%.*]] = mul nuw i64 [[TMP17]], 8604// CHECK-64-NEXT: [[TMP19:%.*]] = bitcast double* [[VLA8]] to i8*605// CHECK-64-NEXT: [[TMP20:%.*]] = bitcast double* [[TMP6]] to i8*606// CHECK-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP19]], i8* align 8 [[TMP20]], i64 [[TMP18]], i1 false)607// CHECK-64-NEXT: [[TMP21:%.*]] = bitcast %struct.TT* [[D9]] to i8*608// CHECK-64-NEXT: [[TMP22:%.*]] = bitcast %struct.TT* [[TMP7]] to i8*609// CHECK-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP21]], i8* align 8 [[TMP22]], i64 16, i1 false)610// CHECK-64-NEXT: [[TMP23:%.*]] = load i16, i16* [[CONV]], align 2611// CHECK-64-NEXT: [[CONV10:%.*]] = sext i16 [[TMP23]] to i32612// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV10]], 1613// CHECK-64-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD]] to i16614// CHECK-64-NEXT: store i16 [[CONV11]], i16* [[CONV]], align 2615// CHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], i64 0, i64 2616// CHECK-64-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4617// CHECK-64-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA6]], i64 3618// CHECK-64-NEXT: store float 1.000000e+00, float* [[ARRAYIDX12]], align 4619// CHECK-64-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], i64 0, i64 1620// CHECK-64-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i64 0, i64 2621// CHECK-64-NEXT: store double 1.000000e+00, double* [[ARRAYIDX14]], align 8622// CHECK-64-NEXT: [[TMP24:%.*]] = mul nsw i64 1, [[TMP5]]623// CHECK-64-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[VLA8]], i64 [[TMP24]]624// CHECK-64-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3625// CHECK-64-NEXT: store double 1.000000e+00, double* [[ARRAYIDX16]], align 8626// CHECK-64-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 0627// CHECK-64-NEXT: store i64 1, i64* [[X]], align 8628// CHECK-64-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 1629// CHECK-64-NEXT: store i8 1, i8* [[Y]], align 8630// CHECK-64-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8631// CHECK-64-NEXT: call void @llvm.stackrestore(i8* [[TMP25]])632// CHECK-64-NEXT: ret void633// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111634// CHECK-64-SAME: (double* noundef [[PTR:%.*]], %struct.TT.0* noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR2]] {635// CHECK-64-NEXT: entry:636// CHECK-64-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 8637// CHECK-64-NEXT: [[E_ADDR:%.*]] = alloca %struct.TT.0*, align 8638// CHECK-64-NEXT: [[E1:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4639// CHECK-64-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 8640// CHECK-64-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[E_ADDR]], align 8641// CHECK-64-NEXT: [[TMP0:%.*]] = load %struct.TT.0*, %struct.TT.0** [[E_ADDR]], align 8642// CHECK-64-NEXT: [[TMP1:%.*]] = bitcast %struct.TT.0* [[E1]] to i8*643// CHECK-64-NEXT: [[TMP2:%.*]] = bitcast %struct.TT.0* [[TMP0]] to i8*644// CHECK-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 8, i1 false)645// CHECK-64-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E1]], i32 0, i32 0646// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, i32* [[X]], align 4647// CHECK-64-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP3]] to double648// CHECK-64-NEXT: [[TMP4:%.*]] = load double*, double** [[PTR_ADDR]], align 8649// CHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP4]], i64 0650// CHECK-64-NEXT: store double [[CONV]], double* [[ARRAYIDX]], align 8651// CHECK-64-NEXT: [[TMP5:%.*]] = load double*, double** [[PTR_ADDR]], align 8652// CHECK-64-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, double* [[TMP5]], i64 0653// CHECK-64-NEXT: [[TMP6:%.*]] = load double, double* [[ARRAYIDX2]], align 8654// CHECK-64-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00655// CHECK-64-NEXT: store double [[INC]], double* [[ARRAYIDX2]], align 8656// CHECK-64-NEXT: ret void657// CHECK-64-LABEL: define {{[^@]+}}@_Z3bariPd658// CHECK-64-SAME: (i32 noundef signext [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0]] {659// CHECK-64-NEXT: entry:660// CHECK-64-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4661// CHECK-64-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 8662// CHECK-64-NEXT: [[A:%.*]] = alloca i32, align 4663// CHECK-64-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8664// CHECK-64-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4665// CHECK-64-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 8666// CHECK-64-NEXT: store i32 0, i32* [[A]], align 4667// CHECK-64-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4668// CHECK-64-NEXT: [[TMP1:%.*]] = load double*, double** [[PTR_ADDR]], align 8669// CHECK-64-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooiPd(i32 noundef signext [[TMP0]], double* noundef [[TMP1]])670// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4671// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]]672// CHECK-64-NEXT: store i32 [[ADD]], i32* [[A]], align 4673// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4674// CHECK-64-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP3]])675// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4676// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]]677// CHECK-64-NEXT: store i32 [[ADD2]], i32* [[A]], align 4678// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4679// CHECK-64-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP5]])680// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4681// CHECK-64-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]]682// CHECK-64-NEXT: store i32 [[ADD4]], i32* [[A]], align 4683// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4684// CHECK-64-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP7]])685// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4686// CHECK-64-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]]687// CHECK-64-NEXT: store i32 [[ADD6]], i32* [[A]], align 4688// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4689// CHECK-64-NEXT: ret i32 [[TMP9]]690// CHECK-64-LABEL: define {{[^@]+}}@_ZN2S12r1Ei691// CHECK-64-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {692// CHECK-64-NEXT: entry:693// CHECK-64-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8694// CHECK-64-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4695// CHECK-64-NEXT: [[B:%.*]] = alloca i32, align 4696// CHECK-64-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8697// CHECK-64-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8698// CHECK-64-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8699// CHECK-64-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8700// CHECK-64-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8701// CHECK-64-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8702// CHECK-64-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8703// CHECK-64-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8704// CHECK-64-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4705// CHECK-64-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8706// CHECK-64-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4707// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1708// CHECK-64-NEXT: store i32 [[ADD]], i32* [[B]], align 4709// CHECK-64-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4710// CHECK-64-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64711// CHECK-64-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()712// CHECK-64-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8713// CHECK-64-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]714// CHECK-64-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2715// CHECK-64-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8716// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4717// CHECK-64-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*718// CHECK-64-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4719// CHECK-64-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8720// CHECK-64-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0721// CHECK-64-NEXT: [[TMP7:%.*]] = mul nuw i64 2, [[TMP2]]722// CHECK-64-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP7]], 2723// CHECK-64-NEXT: [[TMP9:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8*724// CHECK-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP9]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes.5 to i8*), i64 40, i1 false)725// CHECK-64-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0726// CHECK-64-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**727// CHECK-64-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8728// CHECK-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0729// CHECK-64-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**730// CHECK-64-NEXT: store double* [[A]], double** [[TMP13]], align 8731// CHECK-64-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0732// CHECK-64-NEXT: store i8* null, i8** [[TMP14]], align 8733// CHECK-64-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1734// CHECK-64-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64*735// CHECK-64-NEXT: store i64 [[TMP6]], i64* [[TMP16]], align 8736// CHECK-64-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1737// CHECK-64-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*738// CHECK-64-NEXT: store i64 [[TMP6]], i64* [[TMP18]], align 8739// CHECK-64-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1740// CHECK-64-NEXT: store i8* null, i8** [[TMP19]], align 8741// CHECK-64-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2742// CHECK-64-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64*743// CHECK-64-NEXT: store i64 2, i64* [[TMP21]], align 8744// CHECK-64-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2745// CHECK-64-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64*746// CHECK-64-NEXT: store i64 2, i64* [[TMP23]], align 8747// CHECK-64-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2748// CHECK-64-NEXT: store i8* null, i8** [[TMP24]], align 8749// CHECK-64-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3750// CHECK-64-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64*751// CHECK-64-NEXT: store i64 [[TMP2]], i64* [[TMP26]], align 8752// CHECK-64-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3753// CHECK-64-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64*754// CHECK-64-NEXT: store i64 [[TMP2]], i64* [[TMP28]], align 8755// CHECK-64-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3756// CHECK-64-NEXT: store i8* null, i8** [[TMP29]], align 8757// CHECK-64-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4758// CHECK-64-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i16**759// CHECK-64-NEXT: store i16* [[VLA]], i16** [[TMP31]], align 8760// CHECK-64-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4761// CHECK-64-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i16**762// CHECK-64-NEXT: store i16* [[VLA]], i16** [[TMP33]], align 8763// CHECK-64-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4764// CHECK-64-NEXT: store i64 [[TMP8]], i64* [[TMP34]], align 8765// CHECK-64-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4766// CHECK-64-NEXT: store i8* null, i8** [[TMP35]], align 8767// CHECK-64-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0768// CHECK-64-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0769// CHECK-64-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0770// CHECK-64-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8771// CHECK-64-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0772// CHECK-64-NEXT: store i32 2, i32* [[TMP39]], align 4773// CHECK-64-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1774// CHECK-64-NEXT: store i32 5, i32* [[TMP40]], align 4775// CHECK-64-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2776// CHECK-64-NEXT: store i8** [[TMP36]], i8*** [[TMP41]], align 8777// CHECK-64-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3778// CHECK-64-NEXT: store i8** [[TMP37]], i8*** [[TMP42]], align 8779// CHECK-64-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4780// CHECK-64-NEXT: store i64* [[TMP38]], i64** [[TMP43]], align 8781// CHECK-64-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5782// CHECK-64-NEXT: store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.6, i32 0, i32 0), i64** [[TMP44]], align 8783// CHECK-64-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6784// CHECK-64-NEXT: store i8** null, i8*** [[TMP45]], align 8785// CHECK-64-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7786// CHECK-64-NEXT: store i8** null, i8*** [[TMP46]], align 8787// CHECK-64-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8788// CHECK-64-NEXT: store i64 0, i64* [[TMP47]], align 8789// CHECK-64-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9790// CHECK-64-NEXT: store i64 0, i64* [[TMP48]], align 8791// CHECK-64-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10792// CHECK-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP49]], align 4793// CHECK-64-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11794// CHECK-64-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP50]], align 4795// CHECK-64-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12796// CHECK-64-NEXT: store i32 0, i32* [[TMP51]], align 4797// CHECK-64-NEXT: [[TMP52:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])798// CHECK-64-NEXT: [[TMP53:%.*]] = icmp ne i32 [[TMP52]], 0799// CHECK-64-NEXT: br i1 [[TMP53]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]800// CHECK-64: omp_offload.failed:801// CHECK-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]]802// CHECK-64-NEXT: br label [[OMP_OFFLOAD_CONT]]803// CHECK-64: omp_offload.cont:804// CHECK-64-NEXT: [[TMP54:%.*]] = mul nsw i64 1, [[TMP2]]805// CHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP54]]806// CHECK-64-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1807// CHECK-64-NEXT: [[TMP55:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2808// CHECK-64-NEXT: [[CONV3:%.*]] = sext i16 [[TMP55]] to i32809// CHECK-64-NEXT: [[TMP56:%.*]] = load i32, i32* [[B]], align 4810// CHECK-64-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP56]]811// CHECK-64-NEXT: [[TMP57:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8812// CHECK-64-NEXT: call void @llvm.stackrestore(i8* [[TMP57]])813// CHECK-64-NEXT: ret i32 [[ADD4]]814// CHECK-64-LABEL: define {{[^@]+}}@_ZL7fstatici815// CHECK-64-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {816// CHECK-64-NEXT: entry:817// CHECK-64-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4818// CHECK-64-NEXT: [[A:%.*]] = alloca i32, align 4819// CHECK-64-NEXT: [[AAA:%.*]] = alloca i8, align 1820// CHECK-64-NEXT: [[B:%.*]] = alloca [10 x i32], align 4821// CHECK-64-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8822// CHECK-64-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8823// CHECK-64-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8824// CHECK-64-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8825// CHECK-64-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8826// CHECK-64-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4827// CHECK-64-NEXT: store i32 0, i32* [[A]], align 4828// CHECK-64-NEXT: store i8 0, i8* [[AAA]], align 1829// CHECK-64-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4830// CHECK-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*831// CHECK-64-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4832// CHECK-64-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8833// CHECK-64-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1834// CHECK-64-NEXT: [[CONV1:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*835// CHECK-64-NEXT: store i8 [[TMP2]], i8* [[CONV1]], align 1836// CHECK-64-NEXT: [[TMP3:%.*]] = load i64, i64* [[AAA_CASTED]], align 8837// CHECK-64-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0838// CHECK-64-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*839// CHECK-64-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8840// CHECK-64-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0841// CHECK-64-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64*842// CHECK-64-NEXT: store i64 [[TMP1]], i64* [[TMP7]], align 8843// CHECK-64-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0844// CHECK-64-NEXT: store i8* null, i8** [[TMP8]], align 8845// CHECK-64-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1846// CHECK-64-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*847// CHECK-64-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8848// CHECK-64-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1849// CHECK-64-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64*850// CHECK-64-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8851// CHECK-64-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1852// CHECK-64-NEXT: store i8* null, i8** [[TMP13]], align 8853// CHECK-64-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2854// CHECK-64-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [10 x i32]**855// CHECK-64-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP15]], align 8856// CHECK-64-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2857// CHECK-64-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [10 x i32]**858// CHECK-64-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP17]], align 8859// CHECK-64-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2860// CHECK-64-NEXT: store i8* null, i8** [[TMP18]], align 8861// CHECK-64-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0862// CHECK-64-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0863// CHECK-64-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8864// CHECK-64-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0865// CHECK-64-NEXT: store i32 2, i32* [[TMP21]], align 4866// CHECK-64-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1867// CHECK-64-NEXT: store i32 3, i32* [[TMP22]], align 4868// CHECK-64-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2869// CHECK-64-NEXT: store i8** [[TMP19]], i8*** [[TMP23]], align 8870// CHECK-64-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3871// CHECK-64-NEXT: store i8** [[TMP20]], i8*** [[TMP24]], align 8872// CHECK-64-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4873// CHECK-64-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.7, i32 0, i32 0), i64** [[TMP25]], align 8874// CHECK-64-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5875// CHECK-64-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.8, i32 0, i32 0), i64** [[TMP26]], align 8876// CHECK-64-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6877// CHECK-64-NEXT: store i8** null, i8*** [[TMP27]], align 8878// CHECK-64-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7879// CHECK-64-NEXT: store i8** null, i8*** [[TMP28]], align 8880// CHECK-64-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8881// CHECK-64-NEXT: store i64 0, i64* [[TMP29]], align 8882// CHECK-64-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9883// CHECK-64-NEXT: store i64 0, i64* [[TMP30]], align 8884// CHECK-64-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10885// CHECK-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP31]], align 4886// CHECK-64-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11887// CHECK-64-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP32]], align 4888// CHECK-64-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12889// CHECK-64-NEXT: store i32 0, i32* [[TMP33]], align 4890// CHECK-64-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])891// CHECK-64-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0892// CHECK-64-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]893// CHECK-64: omp_offload.failed:894// CHECK-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]895// CHECK-64-NEXT: br label [[OMP_OFFLOAD_CONT]]896// CHECK-64: omp_offload.cont:897// CHECK-64-NEXT: [[TMP36:%.*]] = load i32, i32* [[A]], align 4898// CHECK-64-NEXT: ret i32 [[TMP36]]899// CHECK-64-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i900// CHECK-64-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {901// CHECK-64-NEXT: entry:902// CHECK-64-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4903// CHECK-64-NEXT: [[A:%.*]] = alloca i32, align 4904// CHECK-64-NEXT: [[B:%.*]] = alloca [10 x i32], align 4905// CHECK-64-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8906// CHECK-64-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 8907// CHECK-64-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 8908// CHECK-64-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 8909// CHECK-64-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4910// CHECK-64-NEXT: store i32 0, i32* [[A]], align 4911// CHECK-64-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4912// CHECK-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*913// CHECK-64-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4914// CHECK-64-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8915// CHECK-64-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0916// CHECK-64-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64*917// CHECK-64-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8918// CHECK-64-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0919// CHECK-64-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*920// CHECK-64-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8921// CHECK-64-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0922// CHECK-64-NEXT: store i8* null, i8** [[TMP6]], align 8923// CHECK-64-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1924// CHECK-64-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [10 x i32]**925// CHECK-64-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP8]], align 8926// CHECK-64-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1927// CHECK-64-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]**928// CHECK-64-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP10]], align 8929// CHECK-64-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1930// CHECK-64-NEXT: store i8* null, i8** [[TMP11]], align 8931// CHECK-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0932// CHECK-64-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0933// CHECK-64-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8934// CHECK-64-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0935// CHECK-64-NEXT: store i32 2, i32* [[TMP14]], align 4936// CHECK-64-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1937// CHECK-64-NEXT: store i32 2, i32* [[TMP15]], align 4938// CHECK-64-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2939// CHECK-64-NEXT: store i8** [[TMP12]], i8*** [[TMP16]], align 8940// CHECK-64-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3941// CHECK-64-NEXT: store i8** [[TMP13]], i8*** [[TMP17]], align 8942// CHECK-64-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4943// CHECK-64-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.9, i32 0, i32 0), i64** [[TMP18]], align 8944// CHECK-64-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5945// CHECK-64-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.10, i32 0, i32 0), i64** [[TMP19]], align 8946// CHECK-64-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6947// CHECK-64-NEXT: store i8** null, i8*** [[TMP20]], align 8948// CHECK-64-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7949// CHECK-64-NEXT: store i8** null, i8*** [[TMP21]], align 8950// CHECK-64-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8951// CHECK-64-NEXT: store i64 0, i64* [[TMP22]], align 8952// CHECK-64-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9953// CHECK-64-NEXT: store i64 0, i64* [[TMP23]], align 8954// CHECK-64-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10955// CHECK-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP24]], align 4956// CHECK-64-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11957// CHECK-64-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP25]], align 4958// CHECK-64-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12959// CHECK-64-NEXT: store i32 0, i32* [[TMP26]], align 4960// CHECK-64-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])961// CHECK-64-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0962// CHECK-64-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]963// CHECK-64: omp_offload.failed:964// CHECK-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128(i64 [[TMP1]], [10 x i32]* [[B]]) #[[ATTR3]]965// CHECK-64-NEXT: br label [[OMP_OFFLOAD_CONT]]966// CHECK-64: omp_offload.cont:967// CHECK-64-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4968// CHECK-64-NEXT: ret i32 [[TMP29]]969// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167970// CHECK-64-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {971// CHECK-64-NEXT: entry:972// CHECK-64-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8973// CHECK-64-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8974// CHECK-64-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8975// CHECK-64-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8976// CHECK-64-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8977// CHECK-64-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8978// CHECK-64-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8979// CHECK-64-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8980// CHECK-64-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8981// CHECK-64-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8982// CHECK-64-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8983// CHECK-64-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8984// CHECK-64-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8985// CHECK-64-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8986// CHECK-64-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*987// CHECK-64-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8988// CHECK-64-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8989// CHECK-64-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8990// CHECK-64-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave()991// CHECK-64-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8992// CHECK-64-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]]993// CHECK-64-NEXT: [[VLA3:%.*]] = alloca i16, i64 [[TMP5]], align 2994// CHECK-64-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8995// CHECK-64-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR1]], align 8996// CHECK-64-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]]997// CHECK-64-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], 2998// CHECK-64-NEXT: [[TMP8:%.*]] = bitcast i16* [[VLA3]] to i8*999// CHECK-64-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP3]] to i8*1000// CHECK-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 2 [[TMP8]], i8* align 2 [[TMP9]], i64 [[TMP7]], i1 false)1001// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 41002// CHECK-64-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP10]] to double1003// CHECK-64-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+001004// CHECK-64-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 01005// CHECK-64-NEXT: store double [[ADD]], double* [[A]], align 81006// CHECK-64-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 01007// CHECK-64-NEXT: [[TMP11:%.*]] = load double, double* [[A5]], align 81008// CHECK-64-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+001009// CHECK-64-NEXT: store double [[INC]], double* [[A5]], align 81010// CHECK-64-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i161011// CHECK-64-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP2]]1012// CHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA3]], i64 [[TMP12]]1013// CHECK-64-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 11014// CHECK-64-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 21015// CHECK-64-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 81016// CHECK-64-NEXT: call void @llvm.stackrestore(i8* [[TMP13]])1017// CHECK-64-NEXT: ret void1018// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l1421019// CHECK-64-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {1020// CHECK-64-NEXT: entry:1021// CHECK-64-NEXT: [[A_ADDR:%.*]] = alloca i64, align 81022// CHECK-64-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 81023// CHECK-64-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 81024// CHECK-64-NEXT: [[B2:%.*]] = alloca [10 x i32], align 41025// CHECK-64-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 81026// CHECK-64-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 81027// CHECK-64-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 81028// CHECK-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*1029// CHECK-64-NEXT: [[CONV1:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*1030// CHECK-64-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 81031// CHECK-64-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B2]] to i8*1032// CHECK-64-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*1033// CHECK-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 40, i1 false)1034// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 41035// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 11036// CHECK-64-NEXT: store i32 [[ADD]], i32* [[CONV]], align 41037// CHECK-64-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 11038// CHECK-64-NEXT: [[CONV3:%.*]] = sext i8 [[TMP4]] to i321039// CHECK-64-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 11040// CHECK-64-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i81041// CHECK-64-NEXT: store i8 [[CONV5]], i8* [[CONV1]], align 11042// CHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B2]], i64 0, i64 21043// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 41044// CHECK-64-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP5]], 11045// CHECK-64-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 41046// CHECK-64-NEXT: ret void1047// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l1281048// CHECK-64-SAME: (i64 noundef [[A:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {1049// CHECK-64-NEXT: entry:1050// CHECK-64-NEXT: [[A_ADDR:%.*]] = alloca i64, align 81051// CHECK-64-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 81052// CHECK-64-NEXT: [[B1:%.*]] = alloca [10 x i32], align 41053// CHECK-64-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 81054// CHECK-64-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 81055// CHECK-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*1056// CHECK-64-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 81057// CHECK-64-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8*1058// CHECK-64-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*1059// CHECK-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 40, i1 false)1060// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 41061// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 11062// CHECK-64-NEXT: store i32 [[ADD]], i32* [[CONV]], align 41063// CHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i64 0, i64 21064// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 41065// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], 11066// CHECK-64-NEXT: store i32 [[ADD2]], i32* [[ARRAYIDX]], align 41067// CHECK-64-NEXT: ret void1068// CHECK-64-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg1069// CHECK-64-SAME: () #[[ATTR5:[0-9]+]] {1070// CHECK-64-NEXT: entry:1071// CHECK-64-NEXT: call void @__tgt_register_requires(i64 1)1072// CHECK-64-NEXT: ret void1073// CHECK-32-LABEL: define {{[^@]+}}@_Z3fooiPd1074// CHECK-32-SAME: (i32 noundef [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {1075// CHECK-32-NEXT: entry:1076// CHECK-32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 41077// CHECK-32-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 41078// CHECK-32-NEXT: [[A:%.*]] = alloca i32, align 41079// CHECK-32-NEXT: [[AA:%.*]] = alloca i16, align 21080// CHECK-32-NEXT: [[B:%.*]] = alloca [10 x float], align 41081// CHECK-32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 41082// CHECK-32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 41083// CHECK-32-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 81084// CHECK-32-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 41085// CHECK-32-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 41086// CHECK-32-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 41087// CHECK-32-NEXT: [[P:%.*]] = alloca i32*, align 641088// CHECK-32-NEXT: [[A_CASTED:%.*]] = alloca i32, align 41089// CHECK-32-NEXT: [[GA_CASTED:%.*]] = alloca i32, align 41090// CHECK-32-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 41091// CHECK-32-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 41092// CHECK-32-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 41093// CHECK-32-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 41094// CHECK-32-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [9 x i8*], align 41095// CHECK-32-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [9 x i8*], align 41096// CHECK-32-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [9 x i8*], align 41097// CHECK-32-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 41098// CHECK-32-NEXT: [[DOTOFFLOAD_BASEPTRS8:%.*]] = alloca [2 x i8*], align 41099// CHECK-32-NEXT: [[DOTOFFLOAD_PTRS9:%.*]] = alloca [2 x i8*], align 41100// CHECK-32-NEXT: [[DOTOFFLOAD_MAPPERS10:%.*]] = alloca [2 x i8*], align 41101// CHECK-32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 41102// CHECK-32-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 41103// CHECK-32-NEXT: store i32 0, i32* [[A]], align 41104// CHECK-32-NEXT: store i16 0, i16* [[AA]], align 21105// CHECK-32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 41106// CHECK-32-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave()1107// CHECK-32-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 41108// CHECK-32-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 41109// CHECK-32-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 41110// CHECK-32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 41111// CHECK-32-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]1112// CHECK-32-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 81113// CHECK-32-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 41114// CHECK-32-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 01115// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 41116// CHECK-32-NEXT: store i32 [[TMP4]], i32* [[X]], align 41117// CHECK-32-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 11118// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 41119// CHECK-32-NEXT: store i32 [[TMP5]], i32* [[Y]], align 41120// CHECK-32-NEXT: store i32* [[A]], i32** [[P]], align 641121// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 41122// CHECK-32-NEXT: store i32 [[TMP6]], i32* [[A_CASTED]], align 41123// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, i32* [[A_CASTED]], align 41124// CHECK-32-NEXT: [[TMP8:%.*]] = load i32*, i32** [[P]], align 641125// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, i32* @ga, align 41126// CHECK-32-NEXT: store i32 [[TMP9]], i32* [[GA_CASTED]], align 41127// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, i32* [[GA_CASTED]], align 41128// CHECK-32-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01129// CHECK-32-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32*1130// CHECK-32-NEXT: store i32 [[TMP7]], i32* [[TMP12]], align 41131// CHECK-32-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 01132// CHECK-32-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32*1133// CHECK-32-NEXT: store i32 [[TMP7]], i32* [[TMP14]], align 41134// CHECK-32-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 01135// CHECK-32-NEXT: store i8* null, i8** [[TMP15]], align 41136// CHECK-32-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 11137// CHECK-32-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32**1138// CHECK-32-NEXT: store i32* [[TMP8]], i32** [[TMP17]], align 41139// CHECK-32-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 11140// CHECK-32-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32**1141// CHECK-32-NEXT: store i32* [[TMP8]], i32** [[TMP19]], align 41142// CHECK-32-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 11143// CHECK-32-NEXT: store i8* null, i8** [[TMP20]], align 41144// CHECK-32-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 21145// CHECK-32-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32*1146// CHECK-32-NEXT: store i32 [[TMP10]], i32* [[TMP22]], align 41147// CHECK-32-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 21148// CHECK-32-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32*1149// CHECK-32-NEXT: store i32 [[TMP10]], i32* [[TMP24]], align 41150// CHECK-32-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 21151// CHECK-32-NEXT: store i8* null, i8** [[TMP25]], align 41152// CHECK-32-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01153// CHECK-32-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 01154// CHECK-32-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81155// CHECK-32-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 01156// CHECK-32-NEXT: store i32 2, i32* [[TMP28]], align 41157// CHECK-32-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11158// CHECK-32-NEXT: store i32 3, i32* [[TMP29]], align 41159// CHECK-32-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 21160// CHECK-32-NEXT: store i8** [[TMP26]], i8*** [[TMP30]], align 41161// CHECK-32-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 31162// CHECK-32-NEXT: store i8** [[TMP27]], i8*** [[TMP31]], align 41163// CHECK-32-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 41164// CHECK-32-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP32]], align 41165// CHECK-32-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 51166// CHECK-32-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP33]], align 41167// CHECK-32-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 61168// CHECK-32-NEXT: store i8** null, i8*** [[TMP34]], align 41169// CHECK-32-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 71170// CHECK-32-NEXT: store i8** null, i8*** [[TMP35]], align 41171// CHECK-32-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 81172// CHECK-32-NEXT: store i64 0, i64* [[TMP36]], align 81173// CHECK-32-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 91174// CHECK-32-NEXT: store i64 0, i64* [[TMP37]], align 81175// CHECK-32-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 101176// CHECK-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP38]], align 41177// CHECK-32-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 111178// CHECK-32-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP39]], align 41179// CHECK-32-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 121180// CHECK-32-NEXT: store i32 0, i32* [[TMP40]], align 41181// CHECK-32-NEXT: [[TMP41:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])1182// CHECK-32-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 01183// CHECK-32-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]1184// CHECK-32: omp_offload.failed:1185// CHECK-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63(i32 [[TMP7]], i32* [[TMP8]], i32 [[TMP10]]) #[[ATTR3:[0-9]+]]1186// CHECK-32-NEXT: br label [[OMP_OFFLOAD_CONT]]1187// CHECK-32: omp_offload.cont:1188// CHECK-32-NEXT: [[TMP43:%.*]] = load i16, i16* [[AA]], align 21189// CHECK-32-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*1190// CHECK-32-NEXT: store i16 [[TMP43]], i16* [[CONV]], align 21191// CHECK-32-NEXT: [[TMP44:%.*]] = load i32, i32* [[AA_CASTED]], align 41192// CHECK-32-NEXT: [[TMP45:%.*]] = mul nuw i32 [[TMP0]], 41193// CHECK-32-NEXT: [[TMP46:%.*]] = sext i32 [[TMP45]] to i641194// CHECK-32-NEXT: [[TMP47:%.*]] = mul nuw i32 5, [[TMP2]]1195// CHECK-32-NEXT: [[TMP48:%.*]] = mul nuw i32 [[TMP47]], 81196// CHECK-32-NEXT: [[TMP49:%.*]] = sext i32 [[TMP48]] to i641197// CHECK-32-NEXT: [[TMP50:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8*1198// CHECK-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 bitcast ([9 x i64]* @.offload_sizes.1 to i8*), i32 72, i1 false)1199// CHECK-32-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 01200// CHECK-32-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32*1201// CHECK-32-NEXT: store i32 [[TMP44]], i32* [[TMP52]], align 41202// CHECK-32-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 01203// CHECK-32-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to i32*1204// CHECK-32-NEXT: store i32 [[TMP44]], i32* [[TMP54]], align 41205// CHECK-32-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 01206// CHECK-32-NEXT: store i8* null, i8** [[TMP55]], align 41207// CHECK-32-NEXT: [[TMP56:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 11208// CHECK-32-NEXT: [[TMP57:%.*]] = bitcast i8** [[TMP56]] to [10 x float]**1209// CHECK-32-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP57]], align 41210// CHECK-32-NEXT: [[TMP58:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 11211// CHECK-32-NEXT: [[TMP59:%.*]] = bitcast i8** [[TMP58]] to [10 x float]**1212// CHECK-32-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP59]], align 41213// CHECK-32-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 11214// CHECK-32-NEXT: store i8* null, i8** [[TMP60]], align 41215// CHECK-32-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 21216// CHECK-32-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32*1217// CHECK-32-NEXT: store i32 [[TMP0]], i32* [[TMP62]], align 41218// CHECK-32-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 21219// CHECK-32-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i32*1220// CHECK-32-NEXT: store i32 [[TMP0]], i32* [[TMP64]], align 41221// CHECK-32-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 21222// CHECK-32-NEXT: store i8* null, i8** [[TMP65]], align 41223// CHECK-32-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 31224// CHECK-32-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to float**1225// CHECK-32-NEXT: store float* [[VLA]], float** [[TMP67]], align 41226// CHECK-32-NEXT: [[TMP68:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 31227// CHECK-32-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to float**1228// CHECK-32-NEXT: store float* [[VLA]], float** [[TMP69]], align 41229// CHECK-32-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 31230// CHECK-32-NEXT: store i64 [[TMP46]], i64* [[TMP70]], align 41231// CHECK-32-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 31232// CHECK-32-NEXT: store i8* null, i8** [[TMP71]], align 41233// CHECK-32-NEXT: [[TMP72:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 41234// CHECK-32-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to [5 x [10 x double]]**1235// CHECK-32-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP73]], align 41236// CHECK-32-NEXT: [[TMP74:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 41237// CHECK-32-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to [5 x [10 x double]]**1238// CHECK-32-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP75]], align 41239// CHECK-32-NEXT: [[TMP76:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 41240// CHECK-32-NEXT: store i8* null, i8** [[TMP76]], align 41241// CHECK-32-NEXT: [[TMP77:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 51242// CHECK-32-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i32*1243// CHECK-32-NEXT: store i32 5, i32* [[TMP78]], align 41244// CHECK-32-NEXT: [[TMP79:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 51245// CHECK-32-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i32*1246// CHECK-32-NEXT: store i32 5, i32* [[TMP80]], align 41247// CHECK-32-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 51248// CHECK-32-NEXT: store i8* null, i8** [[TMP81]], align 41249// CHECK-32-NEXT: [[TMP82:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 61250// CHECK-32-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i32*1251// CHECK-32-NEXT: store i32 [[TMP2]], i32* [[TMP83]], align 41252// CHECK-32-NEXT: [[TMP84:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 61253// CHECK-32-NEXT: [[TMP85:%.*]] = bitcast i8** [[TMP84]] to i32*1254// CHECK-32-NEXT: store i32 [[TMP2]], i32* [[TMP85]], align 41255// CHECK-32-NEXT: [[TMP86:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 61256// CHECK-32-NEXT: store i8* null, i8** [[TMP86]], align 41257// CHECK-32-NEXT: [[TMP87:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 71258// CHECK-32-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to double**1259// CHECK-32-NEXT: store double* [[VLA1]], double** [[TMP88]], align 41260// CHECK-32-NEXT: [[TMP89:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 71261// CHECK-32-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to double**1262// CHECK-32-NEXT: store double* [[VLA1]], double** [[TMP90]], align 41263// CHECK-32-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 71264// CHECK-32-NEXT: store i64 [[TMP49]], i64* [[TMP91]], align 41265// CHECK-32-NEXT: [[TMP92:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 71266// CHECK-32-NEXT: store i8* null, i8** [[TMP92]], align 41267// CHECK-32-NEXT: [[TMP93:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 81268// CHECK-32-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to %struct.TT**1269// CHECK-32-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP94]], align 41270// CHECK-32-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 81271// CHECK-32-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to %struct.TT**1272// CHECK-32-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP96]], align 41273// CHECK-32-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 81274// CHECK-32-NEXT: store i8* null, i8** [[TMP97]], align 41275// CHECK-32-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 01276// CHECK-32-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 01277// CHECK-32-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 01278// CHECK-32-NEXT: [[KERNEL_ARGS5:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 81279// CHECK-32-NEXT: [[TMP101:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 01280// CHECK-32-NEXT: store i32 2, i32* [[TMP101]], align 41281// CHECK-32-NEXT: [[TMP102:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 11282// CHECK-32-NEXT: store i32 9, i32* [[TMP102]], align 41283// CHECK-32-NEXT: [[TMP103:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 21284// CHECK-32-NEXT: store i8** [[TMP98]], i8*** [[TMP103]], align 41285// CHECK-32-NEXT: [[TMP104:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 31286// CHECK-32-NEXT: store i8** [[TMP99]], i8*** [[TMP104]], align 41287// CHECK-32-NEXT: [[TMP105:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 41288// CHECK-32-NEXT: store i64* [[TMP100]], i64** [[TMP105]], align 41289// CHECK-32-NEXT: [[TMP106:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 51290// CHECK-32-NEXT: store i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.2, i32 0, i32 0), i64** [[TMP106]], align 41291// CHECK-32-NEXT: [[TMP107:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 61292// CHECK-32-NEXT: store i8** null, i8*** [[TMP107]], align 41293// CHECK-32-NEXT: [[TMP108:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 71294// CHECK-32-NEXT: store i8** null, i8*** [[TMP108]], align 41295// CHECK-32-NEXT: [[TMP109:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 81296// CHECK-32-NEXT: store i64 0, i64* [[TMP109]], align 81297// CHECK-32-NEXT: [[TMP110:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 91298// CHECK-32-NEXT: store i64 0, i64* [[TMP110]], align 81299// CHECK-32-NEXT: [[TMP111:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 101300// CHECK-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP111]], align 41301// CHECK-32-NEXT: [[TMP112:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 111302// CHECK-32-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP112]], align 41303// CHECK-32-NEXT: [[TMP113:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 121304// CHECK-32-NEXT: store i32 0, i32* [[TMP113]], align 41305// CHECK-32-NEXT: [[TMP114:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]])1306// CHECK-32-NEXT: [[TMP115:%.*]] = icmp ne i32 [[TMP114]], 01307// CHECK-32-NEXT: br i1 [[TMP115]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]]1308// CHECK-32: omp_offload.failed6:1309// CHECK-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70(i32 [[TMP44]], [10 x float]* [[B]], i32 [[TMP0]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP2]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]1310// CHECK-32-NEXT: br label [[OMP_OFFLOAD_CONT7]]1311// CHECK-32: omp_offload.cont7:1312// CHECK-32-NEXT: [[TMP116:%.*]] = load double*, double** [[PTR_ADDR]], align 41313// CHECK-32-NEXT: [[TMP117:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 01314// CHECK-32-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to double**1315// CHECK-32-NEXT: store double* [[TMP116]], double** [[TMP118]], align 41316// CHECK-32-NEXT: [[TMP119:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 01317// CHECK-32-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to double**1318// CHECK-32-NEXT: store double* [[TMP116]], double** [[TMP120]], align 41319// CHECK-32-NEXT: [[TMP121:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS10]], i32 0, i32 01320// CHECK-32-NEXT: store i8* null, i8** [[TMP121]], align 41321// CHECK-32-NEXT: [[TMP122:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 11322// CHECK-32-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to %struct.TT.0**1323// CHECK-32-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[TMP123]], align 41324// CHECK-32-NEXT: [[TMP124:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 11325// CHECK-32-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to %struct.TT.0**1326// CHECK-32-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[TMP125]], align 41327// CHECK-32-NEXT: [[TMP126:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS10]], i32 0, i32 11328// CHECK-32-NEXT: store i8* null, i8** [[TMP126]], align 41329// CHECK-32-NEXT: [[TMP127:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 01330// CHECK-32-NEXT: [[TMP128:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 01331// CHECK-32-NEXT: [[KERNEL_ARGS11:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 81332// CHECK-32-NEXT: [[TMP129:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 01333// CHECK-32-NEXT: store i32 2, i32* [[TMP129]], align 41334// CHECK-32-NEXT: [[TMP130:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 11335// CHECK-32-NEXT: store i32 2, i32* [[TMP130]], align 41336// CHECK-32-NEXT: [[TMP131:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 21337// CHECK-32-NEXT: store i8** [[TMP127]], i8*** [[TMP131]], align 41338// CHECK-32-NEXT: [[TMP132:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 31339// CHECK-32-NEXT: store i8** [[TMP128]], i8*** [[TMP132]], align 41340// CHECK-32-NEXT: [[TMP133:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 41341// CHECK-32-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.3, i32 0, i32 0), i64** [[TMP133]], align 41342// CHECK-32-NEXT: [[TMP134:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 51343// CHECK-32-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.4, i32 0, i32 0), i64** [[TMP134]], align 41344// CHECK-32-NEXT: [[TMP135:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 61345// CHECK-32-NEXT: store i8** null, i8*** [[TMP135]], align 41346// CHECK-32-NEXT: [[TMP136:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 71347// CHECK-32-NEXT: store i8** null, i8*** [[TMP136]], align 41348// CHECK-32-NEXT: [[TMP137:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 81349// CHECK-32-NEXT: store i64 0, i64* [[TMP137]], align 81350// CHECK-32-NEXT: [[TMP138:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 91351// CHECK-32-NEXT: store i64 0, i64* [[TMP138]], align 81352// CHECK-32-NEXT: [[TMP139:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 101353// CHECK-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP139]], align 41354// CHECK-32-NEXT: [[TMP140:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 111355// CHECK-32-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP140]], align 41356// CHECK-32-NEXT: [[TMP141:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 121357// CHECK-32-NEXT: store i32 0, i32* [[TMP141]], align 41358// CHECK-32-NEXT: [[TMP142:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]])1359// CHECK-32-NEXT: [[TMP143:%.*]] = icmp ne i32 [[TMP142]], 01360// CHECK-32-NEXT: br i1 [[TMP143]], label [[OMP_OFFLOAD_FAILED12:%.*]], label [[OMP_OFFLOAD_CONT13:%.*]]1361// CHECK-32: omp_offload.failed12:1362// CHECK-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111(double* [[TMP116]], %struct.TT.0* [[E]]) #[[ATTR3]]1363// CHECK-32-NEXT: br label [[OMP_OFFLOAD_CONT13]]1364// CHECK-32: omp_offload.cont13:1365// CHECK-32-NEXT: [[TMP144:%.*]] = load i32, i32* [[A]], align 41366// CHECK-32-NEXT: [[TMP145:%.*]] = load i8*, i8** [[SAVED_STACK]], align 41367// CHECK-32-NEXT: call void @llvm.stackrestore(i8* [[TMP145]])1368// CHECK-32-NEXT: ret i32 [[TMP144]]1369// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l631370// CHECK-32-SAME: (i32 noundef [[A:%.*]], i32* noundef [[P:%.*]], i32 noundef [[GA:%.*]]) #[[ATTR2:[0-9]+]] {1371// CHECK-32-NEXT: entry:1372// CHECK-32-NEXT: [[A_ADDR:%.*]] = alloca i32, align 41373// CHECK-32-NEXT: [[P_ADDR:%.*]] = alloca i32*, align 41374// CHECK-32-NEXT: [[GA_ADDR:%.*]] = alloca i32, align 41375// CHECK-32-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 41376// CHECK-32-NEXT: store i32* [[P]], i32** [[P_ADDR]], align 41377// CHECK-32-NEXT: store i32 [[GA]], i32* [[GA_ADDR]], align 41378// CHECK-32-NEXT: ret void1379// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l701380// CHECK-32-SAME: (i32 noundef [[AA:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {1381// CHECK-32-NEXT: entry:1382// CHECK-32-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 41383// CHECK-32-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 41384// CHECK-32-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 41385// CHECK-32-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 41386// CHECK-32-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 41387// CHECK-32-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 41388// CHECK-32-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 41389// CHECK-32-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 41390// CHECK-32-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 41391// CHECK-32-NEXT: [[B5:%.*]] = alloca [10 x float], align 41392// CHECK-32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 41393// CHECK-32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 41394// CHECK-32-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 81395// CHECK-32-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 41396// CHECK-32-NEXT: [[__VLA_EXPR2:%.*]] = alloca i32, align 41397// CHECK-32-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 41398// CHECK-32-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 41399// CHECK-32-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 41400// CHECK-32-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 41401// CHECK-32-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 41402// CHECK-32-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 41403// CHECK-32-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 41404// CHECK-32-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 41405// CHECK-32-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 41406// CHECK-32-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 41407// CHECK-32-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*1408// CHECK-32-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 41409// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 41410// CHECK-32-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 41411// CHECK-32-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 41412// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 41413// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 41414// CHECK-32-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 41415// CHECK-32-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 41416// CHECK-32-NEXT: [[TMP8:%.*]] = bitcast [10 x float]* [[B5]] to i8*1417// CHECK-32-NEXT: [[TMP9:%.*]] = bitcast [10 x float]* [[TMP0]] to i8*1418// CHECK-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i32 40, i1 false)1419// CHECK-32-NEXT: [[TMP10:%.*]] = call i8* @llvm.stacksave()1420// CHECK-32-NEXT: store i8* [[TMP10]], i8** [[SAVED_STACK]], align 41421// CHECK-32-NEXT: [[VLA6:%.*]] = alloca float, i32 [[TMP1]], align 41422// CHECK-32-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 41423// CHECK-32-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP1]], 41424// CHECK-32-NEXT: [[TMP12:%.*]] = bitcast float* [[VLA6]] to i8*1425// CHECK-32-NEXT: [[TMP13:%.*]] = bitcast float* [[TMP2]] to i8*1426// CHECK-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 [[TMP11]], i1 false)1427// CHECK-32-NEXT: [[TMP14:%.*]] = bitcast [5 x [10 x double]]* [[C7]] to i8*1428// CHECK-32-NEXT: [[TMP15:%.*]] = bitcast [5 x [10 x double]]* [[TMP3]] to i8*1429// CHECK-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 [[TMP14]], i8* align 8 [[TMP15]], i32 400, i1 false)1430// CHECK-32-NEXT: [[TMP16:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]]1431// CHECK-32-NEXT: [[VLA8:%.*]] = alloca double, i32 [[TMP16]], align 81432// CHECK-32-NEXT: store i32 [[TMP4]], i32* [[__VLA_EXPR1]], align 41433// CHECK-32-NEXT: store i32 [[TMP5]], i32* [[__VLA_EXPR2]], align 41434// CHECK-32-NEXT: [[TMP17:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]]1435// CHECK-32-NEXT: [[TMP18:%.*]] = mul nuw i32 [[TMP17]], 81436// CHECK-32-NEXT: [[TMP19:%.*]] = bitcast double* [[VLA8]] to i8*1437// CHECK-32-NEXT: [[TMP20:%.*]] = bitcast double* [[TMP6]] to i8*1438// CHECK-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 [[TMP19]], i8* align 8 [[TMP20]], i32 [[TMP18]], i1 false)1439// CHECK-32-NEXT: [[TMP21:%.*]] = bitcast %struct.TT* [[D9]] to i8*1440// CHECK-32-NEXT: [[TMP22:%.*]] = bitcast %struct.TT* [[TMP7]] to i8*1441// CHECK-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP21]], i8* align 4 [[TMP22]], i32 12, i1 false)1442// CHECK-32-NEXT: [[TMP23:%.*]] = load i16, i16* [[CONV]], align 21443// CHECK-32-NEXT: [[CONV10:%.*]] = sext i16 [[TMP23]] to i321444// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV10]], 11445// CHECK-32-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD]] to i161446// CHECK-32-NEXT: store i16 [[CONV11]], i16* [[CONV]], align 21447// CHECK-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], i32 0, i32 21448// CHECK-32-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 41449// CHECK-32-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA6]], i32 31450// CHECK-32-NEXT: store float 1.000000e+00, float* [[ARRAYIDX12]], align 41451// CHECK-32-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], i32 0, i32 11452// CHECK-32-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i32 0, i32 21453// CHECK-32-NEXT: store double 1.000000e+00, double* [[ARRAYIDX14]], align 81454// CHECK-32-NEXT: [[TMP24:%.*]] = mul nsw i32 1, [[TMP5]]1455// CHECK-32-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[VLA8]], i32 [[TMP24]]1456// CHECK-32-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i32 31457// CHECK-32-NEXT: store double 1.000000e+00, double* [[ARRAYIDX16]], align 81458// CHECK-32-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 01459// CHECK-32-NEXT: store i64 1, i64* [[X]], align 41460// CHECK-32-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 11461// CHECK-32-NEXT: store i8 1, i8* [[Y]], align 41462// CHECK-32-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 41463// CHECK-32-NEXT: call void @llvm.stackrestore(i8* [[TMP25]])1464// CHECK-32-NEXT: ret void1465// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l1111466// CHECK-32-SAME: (double* noundef [[PTR:%.*]], %struct.TT.0* noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR2]] {1467// CHECK-32-NEXT: entry:1468// CHECK-32-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 41469// CHECK-32-NEXT: [[E_ADDR:%.*]] = alloca %struct.TT.0*, align 41470// CHECK-32-NEXT: [[E1:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 41471// CHECK-32-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 41472// CHECK-32-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[E_ADDR]], align 41473// CHECK-32-NEXT: [[TMP0:%.*]] = load %struct.TT.0*, %struct.TT.0** [[E_ADDR]], align 41474// CHECK-32-NEXT: [[TMP1:%.*]] = bitcast %struct.TT.0* [[E1]] to i8*1475// CHECK-32-NEXT: [[TMP2:%.*]] = bitcast %struct.TT.0* [[TMP0]] to i8*1476// CHECK-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 8, i1 false)1477// CHECK-32-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E1]], i32 0, i32 01478// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, i32* [[X]], align 41479// CHECK-32-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP3]] to double1480// CHECK-32-NEXT: [[TMP4:%.*]] = load double*, double** [[PTR_ADDR]], align 41481// CHECK-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP4]], i32 01482// CHECK-32-NEXT: store double [[CONV]], double* [[ARRAYIDX]], align 41483// CHECK-32-NEXT: [[TMP5:%.*]] = load double*, double** [[PTR_ADDR]], align 41484// CHECK-32-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, double* [[TMP5]], i32 01485// CHECK-32-NEXT: [[TMP6:%.*]] = load double, double* [[ARRAYIDX2]], align 41486// CHECK-32-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+001487// CHECK-32-NEXT: store double [[INC]], double* [[ARRAYIDX2]], align 41488// CHECK-32-NEXT: ret void1489// CHECK-32-LABEL: define {{[^@]+}}@_Z3bariPd1490// CHECK-32-SAME: (i32 noundef [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0]] {1491// CHECK-32-NEXT: entry:1492// CHECK-32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 41493// CHECK-32-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 41494// CHECK-32-NEXT: [[A:%.*]] = alloca i32, align 41495// CHECK-32-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 41496// CHECK-32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 41497// CHECK-32-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 41498// CHECK-32-NEXT: store i32 0, i32* [[A]], align 41499// CHECK-32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 41500// CHECK-32-NEXT: [[TMP1:%.*]] = load double*, double** [[PTR_ADDR]], align 41501// CHECK-32-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooiPd(i32 noundef [[TMP0]], double* noundef [[TMP1]])1502// CHECK-32-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 41503// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]]1504// CHECK-32-NEXT: store i32 [[ADD]], i32* [[A]], align 41505// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 41506// CHECK-32-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP3]])1507// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 41508// CHECK-32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]]1509// CHECK-32-NEXT: store i32 [[ADD2]], i32* [[A]], align 41510// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 41511// CHECK-32-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP5]])1512// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 41513// CHECK-32-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]]1514// CHECK-32-NEXT: store i32 [[ADD4]], i32* [[A]], align 41515// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 41516// CHECK-32-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP7]])1517// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 41518// CHECK-32-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]]1519// CHECK-32-NEXT: store i32 [[ADD6]], i32* [[A]], align 41520// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 41521// CHECK-32-NEXT: ret i32 [[TMP9]]1522// CHECK-32-LABEL: define {{[^@]+}}@_ZN2S12r1Ei1523// CHECK-32-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {1524// CHECK-32-NEXT: entry:1525// CHECK-32-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 41526// CHECK-32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 41527// CHECK-32-NEXT: [[B:%.*]] = alloca i32, align 41528// CHECK-32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 41529// CHECK-32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 41530// CHECK-32-NEXT: [[B_CASTED:%.*]] = alloca i32, align 41531// CHECK-32-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 41532// CHECK-32-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 41533// CHECK-32-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 41534// CHECK-32-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 41535// CHECK-32-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 41536// CHECK-32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 41537// CHECK-32-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 41538// CHECK-32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 41539// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 11540// CHECK-32-NEXT: store i32 [[ADD]], i32* [[B]], align 41541// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 41542// CHECK-32-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()1543// CHECK-32-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 41544// CHECK-32-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]1545// CHECK-32-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 21546// CHECK-32-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 41547// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 41548// CHECK-32-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 41549// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 41550// CHECK-32-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 01551// CHECK-32-NEXT: [[TMP6:%.*]] = mul nuw i32 2, [[TMP1]]1552// CHECK-32-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP6]], 21553// CHECK-32-NEXT: [[TMP8:%.*]] = sext i32 [[TMP7]] to i641554// CHECK-32-NEXT: [[TMP9:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8*1555// CHECK-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.5 to i8*), i32 40, i1 false)1556// CHECK-32-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01557// CHECK-32-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**1558// CHECK-32-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 41559// CHECK-32-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 01560// CHECK-32-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**1561// CHECK-32-NEXT: store double* [[A]], double** [[TMP13]], align 41562// CHECK-32-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 01563// CHECK-32-NEXT: store i8* null, i8** [[TMP14]], align 41564// CHECK-32-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 11565// CHECK-32-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32*1566// CHECK-32-NEXT: store i32 [[TMP5]], i32* [[TMP16]], align 41567// CHECK-32-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 11568// CHECK-32-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*1569// CHECK-32-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 41570// CHECK-32-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 11571// CHECK-32-NEXT: store i8* null, i8** [[TMP19]], align 41572// CHECK-32-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 21573// CHECK-32-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32*1574// CHECK-32-NEXT: store i32 2, i32* [[TMP21]], align 41575// CHECK-32-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 21576// CHECK-32-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*1577// CHECK-32-NEXT: store i32 2, i32* [[TMP23]], align 41578// CHECK-32-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 21579// CHECK-32-NEXT: store i8* null, i8** [[TMP24]], align 41580// CHECK-32-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 31581// CHECK-32-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32*1582// CHECK-32-NEXT: store i32 [[TMP1]], i32* [[TMP26]], align 41583// CHECK-32-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 31584// CHECK-32-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32*1585// CHECK-32-NEXT: store i32 [[TMP1]], i32* [[TMP28]], align 41586// CHECK-32-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 31587// CHECK-32-NEXT: store i8* null, i8** [[TMP29]], align 41588// CHECK-32-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 41589// CHECK-32-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i16**1590// CHECK-32-NEXT: store i16* [[VLA]], i16** [[TMP31]], align 41591// CHECK-32-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 41592// CHECK-32-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i16**1593// CHECK-32-NEXT: store i16* [[VLA]], i16** [[TMP33]], align 41594// CHECK-32-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 41595// CHECK-32-NEXT: store i64 [[TMP8]], i64* [[TMP34]], align 41596// CHECK-32-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 41597// CHECK-32-NEXT: store i8* null, i8** [[TMP35]], align 41598// CHECK-32-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01599// CHECK-32-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 01600// CHECK-32-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 01601// CHECK-32-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81602// CHECK-32-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 01603// CHECK-32-NEXT: store i32 2, i32* [[TMP39]], align 41604// CHECK-32-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11605// CHECK-32-NEXT: store i32 5, i32* [[TMP40]], align 41606// CHECK-32-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 21607// CHECK-32-NEXT: store i8** [[TMP36]], i8*** [[TMP41]], align 41608// CHECK-32-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 31609// CHECK-32-NEXT: store i8** [[TMP37]], i8*** [[TMP42]], align 41610// CHECK-32-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 41611// CHECK-32-NEXT: store i64* [[TMP38]], i64** [[TMP43]], align 41612// CHECK-32-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 51613// CHECK-32-NEXT: store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.6, i32 0, i32 0), i64** [[TMP44]], align 41614// CHECK-32-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 61615// CHECK-32-NEXT: store i8** null, i8*** [[TMP45]], align 41616// CHECK-32-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 71617// CHECK-32-NEXT: store i8** null, i8*** [[TMP46]], align 41618// CHECK-32-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 81619// CHECK-32-NEXT: store i64 0, i64* [[TMP47]], align 81620// CHECK-32-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 91621// CHECK-32-NEXT: store i64 0, i64* [[TMP48]], align 81622// CHECK-32-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 101623// CHECK-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP49]], align 41624// CHECK-32-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 111625// CHECK-32-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP50]], align 41626// CHECK-32-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 121627// CHECK-32-NEXT: store i32 0, i32* [[TMP51]], align 41628// CHECK-32-NEXT: [[TMP52:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])1629// CHECK-32-NEXT: [[TMP53:%.*]] = icmp ne i32 [[TMP52]], 01630// CHECK-32-NEXT: br i1 [[TMP53]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]1631// CHECK-32: omp_offload.failed:1632// CHECK-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]]1633// CHECK-32-NEXT: br label [[OMP_OFFLOAD_CONT]]1634// CHECK-32: omp_offload.cont:1635// CHECK-32-NEXT: [[TMP54:%.*]] = mul nsw i32 1, [[TMP1]]1636// CHECK-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP54]]1637// CHECK-32-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 11638// CHECK-32-NEXT: [[TMP55:%.*]] = load i16, i16* [[ARRAYIDX2]], align 21639// CHECK-32-NEXT: [[CONV:%.*]] = sext i16 [[TMP55]] to i321640// CHECK-32-NEXT: [[TMP56:%.*]] = load i32, i32* [[B]], align 41641// CHECK-32-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP56]]1642// CHECK-32-NEXT: [[TMP57:%.*]] = load i8*, i8** [[SAVED_STACK]], align 41643// CHECK-32-NEXT: call void @llvm.stackrestore(i8* [[TMP57]])1644// CHECK-32-NEXT: ret i32 [[ADD3]]1645// CHECK-32-LABEL: define {{[^@]+}}@_ZL7fstatici1646// CHECK-32-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {1647// CHECK-32-NEXT: entry:1648// CHECK-32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 41649// CHECK-32-NEXT: [[A:%.*]] = alloca i32, align 41650// CHECK-32-NEXT: [[AAA:%.*]] = alloca i8, align 11651// CHECK-32-NEXT: [[B:%.*]] = alloca [10 x i32], align 41652// CHECK-32-NEXT: [[A_CASTED:%.*]] = alloca i32, align 41653// CHECK-32-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 41654// CHECK-32-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 41655// CHECK-32-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 41656// CHECK-32-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 41657// CHECK-32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 41658// CHECK-32-NEXT: store i32 0, i32* [[A]], align 41659// CHECK-32-NEXT: store i8 0, i8* [[AAA]], align 11660// CHECK-32-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 41661// CHECK-32-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 41662// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 41663// CHECK-32-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 11664// CHECK-32-NEXT: [[CONV:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*1665// CHECK-32-NEXT: store i8 [[TMP2]], i8* [[CONV]], align 11666// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, i32* [[AAA_CASTED]], align 41667// CHECK-32-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01668// CHECK-32-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32*1669// CHECK-32-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 41670// CHECK-32-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 01671// CHECK-32-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32*1672// CHECK-32-NEXT: store i32 [[TMP1]], i32* [[TMP7]], align 41673// CHECK-32-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 01674// CHECK-32-NEXT: store i8* null, i8** [[TMP8]], align 41675// CHECK-32-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 11676// CHECK-32-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*1677// CHECK-32-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 41678// CHECK-32-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 11679// CHECK-32-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32*1680// CHECK-32-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 41681// CHECK-32-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 11682// CHECK-32-NEXT: store i8* null, i8** [[TMP13]], align 41683// CHECK-32-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 21684// CHECK-32-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [10 x i32]**1685// CHECK-32-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP15]], align 41686// CHECK-32-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 21687// CHECK-32-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [10 x i32]**1688// CHECK-32-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP17]], align 41689// CHECK-32-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 21690// CHECK-32-NEXT: store i8* null, i8** [[TMP18]], align 41691// CHECK-32-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01692// CHECK-32-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 01693// CHECK-32-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81694// CHECK-32-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 01695// CHECK-32-NEXT: store i32 2, i32* [[TMP21]], align 41696// CHECK-32-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11697// CHECK-32-NEXT: store i32 3, i32* [[TMP22]], align 41698// CHECK-32-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 21699// CHECK-32-NEXT: store i8** [[TMP19]], i8*** [[TMP23]], align 41700// CHECK-32-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 31701// CHECK-32-NEXT: store i8** [[TMP20]], i8*** [[TMP24]], align 41702// CHECK-32-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 41703// CHECK-32-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.7, i32 0, i32 0), i64** [[TMP25]], align 41704// CHECK-32-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 51705// CHECK-32-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.8, i32 0, i32 0), i64** [[TMP26]], align 41706// CHECK-32-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 61707// CHECK-32-NEXT: store i8** null, i8*** [[TMP27]], align 41708// CHECK-32-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 71709// CHECK-32-NEXT: store i8** null, i8*** [[TMP28]], align 41710// CHECK-32-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 81711// CHECK-32-NEXT: store i64 0, i64* [[TMP29]], align 81712// CHECK-32-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 91713// CHECK-32-NEXT: store i64 0, i64* [[TMP30]], align 81714// CHECK-32-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 101715// CHECK-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP31]], align 41716// CHECK-32-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 111717// CHECK-32-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP32]], align 41718// CHECK-32-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 121719// CHECK-32-NEXT: store i32 0, i32* [[TMP33]], align 41720// CHECK-32-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])1721// CHECK-32-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 01722// CHECK-32-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]1723// CHECK-32: omp_offload.failed:1724// CHECK-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]1725// CHECK-32-NEXT: br label [[OMP_OFFLOAD_CONT]]1726// CHECK-32: omp_offload.cont:1727// CHECK-32-NEXT: [[TMP36:%.*]] = load i32, i32* [[A]], align 41728// CHECK-32-NEXT: ret i32 [[TMP36]]1729// CHECK-32-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i1730// CHECK-32-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {1731// CHECK-32-NEXT: entry:1732// CHECK-32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 41733// CHECK-32-NEXT: [[A:%.*]] = alloca i32, align 41734// CHECK-32-NEXT: [[B:%.*]] = alloca [10 x i32], align 41735// CHECK-32-NEXT: [[A_CASTED:%.*]] = alloca i32, align 41736// CHECK-32-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 41737// CHECK-32-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 41738// CHECK-32-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 41739// CHECK-32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 41740// CHECK-32-NEXT: store i32 0, i32* [[A]], align 41741// CHECK-32-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 41742// CHECK-32-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 41743// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 41744// CHECK-32-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01745// CHECK-32-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32*1746// CHECK-32-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 41747// CHECK-32-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 01748// CHECK-32-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32*1749// CHECK-32-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 41750// CHECK-32-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 01751// CHECK-32-NEXT: store i8* null, i8** [[TMP6]], align 41752// CHECK-32-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 11753// CHECK-32-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [10 x i32]**1754// CHECK-32-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP8]], align 41755// CHECK-32-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 11756// CHECK-32-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]**1757// CHECK-32-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP10]], align 41758// CHECK-32-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 11759// CHECK-32-NEXT: store i8* null, i8** [[TMP11]], align 41760// CHECK-32-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01761// CHECK-32-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 01762// CHECK-32-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81763// CHECK-32-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 01764// CHECK-32-NEXT: store i32 2, i32* [[TMP14]], align 41765// CHECK-32-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11766// CHECK-32-NEXT: store i32 2, i32* [[TMP15]], align 41767// CHECK-32-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 21768// CHECK-32-NEXT: store i8** [[TMP12]], i8*** [[TMP16]], align 41769// CHECK-32-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 31770// CHECK-32-NEXT: store i8** [[TMP13]], i8*** [[TMP17]], align 41771// CHECK-32-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 41772// CHECK-32-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.9, i32 0, i32 0), i64** [[TMP18]], align 41773// CHECK-32-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 51774// CHECK-32-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.10, i32 0, i32 0), i64** [[TMP19]], align 41775// CHECK-32-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 61776// CHECK-32-NEXT: store i8** null, i8*** [[TMP20]], align 41777// CHECK-32-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 71778// CHECK-32-NEXT: store i8** null, i8*** [[TMP21]], align 41779// CHECK-32-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 81780// CHECK-32-NEXT: store i64 0, i64* [[TMP22]], align 81781// CHECK-32-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 91782// CHECK-32-NEXT: store i64 0, i64* [[TMP23]], align 81783// CHECK-32-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 101784// CHECK-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP24]], align 41785// CHECK-32-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 111786// CHECK-32-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP25]], align 41787// CHECK-32-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 121788// CHECK-32-NEXT: store i32 0, i32* [[TMP26]], align 41789// CHECK-32-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])1790// CHECK-32-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 01791// CHECK-32-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]1792// CHECK-32: omp_offload.failed:1793// CHECK-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128(i32 [[TMP1]], [10 x i32]* [[B]]) #[[ATTR3]]1794// CHECK-32-NEXT: br label [[OMP_OFFLOAD_CONT]]1795// CHECK-32: omp_offload.cont:1796// CHECK-32-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 41797// CHECK-32-NEXT: ret i32 [[TMP29]]1798// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l1671799// CHECK-32-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {1800// CHECK-32-NEXT: entry:1801// CHECK-32-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 41802// CHECK-32-NEXT: [[B_ADDR:%.*]] = alloca i32, align 41803// CHECK-32-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 41804// CHECK-32-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 41805// CHECK-32-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 41806// CHECK-32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 41807// CHECK-32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 41808// CHECK-32-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 41809// CHECK-32-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 41810// CHECK-32-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 41811// CHECK-32-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 41812// CHECK-32-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 41813// CHECK-32-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 41814// CHECK-32-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 41815// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 41816// CHECK-32-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 41817// CHECK-32-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 41818// CHECK-32-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave()1819// CHECK-32-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 41820// CHECK-32-NEXT: [[TMP5:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]1821// CHECK-32-NEXT: [[VLA3:%.*]] = alloca i16, i32 [[TMP5]], align 21822// CHECK-32-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 41823// CHECK-32-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 41824// CHECK-32-NEXT: [[TMP6:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]1825// CHECK-32-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP6]], 21826// CHECK-32-NEXT: [[TMP8:%.*]] = bitcast i16* [[VLA3]] to i8*1827// CHECK-32-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP3]] to i8*1828// CHECK-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 2 [[TMP8]], i8* align 2 [[TMP9]], i32 [[TMP7]], i1 false)1829// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, i32* [[B_ADDR]], align 41830// CHECK-32-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP10]] to double1831// CHECK-32-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+001832// CHECK-32-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 01833// CHECK-32-NEXT: store double [[ADD]], double* [[A]], align 41834// CHECK-32-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 01835// CHECK-32-NEXT: [[TMP11:%.*]] = load double, double* [[A4]], align 41836// CHECK-32-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+001837// CHECK-32-NEXT: store double [[INC]], double* [[A4]], align 41838// CHECK-32-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i161839// CHECK-32-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP2]]1840// CHECK-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA3]], i32 [[TMP12]]1841// CHECK-32-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 11842// CHECK-32-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 21843// CHECK-32-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 41844// CHECK-32-NEXT: call void @llvm.stackrestore(i8* [[TMP13]])1845// CHECK-32-NEXT: ret void1846// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l1421847// CHECK-32-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {1848// CHECK-32-NEXT: entry:1849// CHECK-32-NEXT: [[A_ADDR:%.*]] = alloca i32, align 41850// CHECK-32-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 41851// CHECK-32-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 41852// CHECK-32-NEXT: [[B1:%.*]] = alloca [10 x i32], align 41853// CHECK-32-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 41854// CHECK-32-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 41855// CHECK-32-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 41856// CHECK-32-NEXT: [[CONV:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*1857// CHECK-32-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 41858// CHECK-32-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8*1859// CHECK-32-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*1860// CHECK-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 40, i1 false)1861// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 41862// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 11863// CHECK-32-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 41864// CHECK-32-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 11865// CHECK-32-NEXT: [[CONV2:%.*]] = sext i8 [[TMP4]] to i321866// CHECK-32-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 11867// CHECK-32-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i81868// CHECK-32-NEXT: store i8 [[CONV4]], i8* [[CONV]], align 11869// CHECK-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i32 0, i32 21870// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 41871// CHECK-32-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP5]], 11872// CHECK-32-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 41873// CHECK-32-NEXT: ret void1874// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l1281875// CHECK-32-SAME: (i32 noundef [[A:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {1876// CHECK-32-NEXT: entry:1877// CHECK-32-NEXT: [[A_ADDR:%.*]] = alloca i32, align 41878// CHECK-32-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 41879// CHECK-32-NEXT: [[B1:%.*]] = alloca [10 x i32], align 41880// CHECK-32-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 41881// CHECK-32-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 41882// CHECK-32-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 41883// CHECK-32-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8*1884// CHECK-32-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*1885// CHECK-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 40, i1 false)1886// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 41887// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 11888// CHECK-32-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 41889// CHECK-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i32 0, i32 21890// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 41891// CHECK-32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], 11892// CHECK-32-NEXT: store i32 [[ADD2]], i32* [[ARRAYIDX]], align 41893// CHECK-32-NEXT: ret void1894// CHECK-32-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg1895// CHECK-32-SAME: () #[[ATTR5:[0-9]+]] {1896// CHECK-32-NEXT: entry:1897// CHECK-32-NEXT: call void @__tgt_register_requires(i64 1)1898// CHECK-32-NEXT: ret void1899// CHECK0-64-LABEL: define {{[^@]+}}@_Z3fooiPd1900// CHECK0-64-SAME: (i32 noundef signext [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {1901// CHECK0-64-NEXT: entry:1902// CHECK0-64-NEXT: [[N_ADDR:%.*]] = alloca i32, align 41903// CHECK0-64-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 81904// CHECK0-64-NEXT: [[A:%.*]] = alloca i32, align 41905// CHECK0-64-NEXT: [[AA:%.*]] = alloca i16, align 21906// CHECK0-64-NEXT: [[B:%.*]] = alloca [10 x float], align 41907// CHECK0-64-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 81908// CHECK0-64-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 81909// CHECK0-64-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 81910// CHECK0-64-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 81911// CHECK0-64-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 81912// CHECK0-64-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 41913// CHECK0-64-NEXT: [[P:%.*]] = alloca i32*, align 641914// CHECK0-64-NEXT: [[A_CASTED:%.*]] = alloca i64, align 81915// CHECK0-64-NEXT: [[GA_CASTED:%.*]] = alloca i64, align 81916// CHECK0-64-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 81917// CHECK0-64-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 81918// CHECK0-64-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 81919// CHECK0-64-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 81920// CHECK0-64-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [9 x i8*], align 81921// CHECK0-64-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [9 x i8*], align 81922// CHECK0-64-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [9 x i8*], align 81923// CHECK0-64-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 81924// CHECK0-64-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x i8*], align 81925// CHECK0-64-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x i8*], align 81926// CHECK0-64-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x i8*], align 81927// CHECK0-64-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 41928// CHECK0-64-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 81929// CHECK0-64-NEXT: store i32 0, i32* [[A]], align 41930// CHECK0-64-NEXT: store i16 0, i16* [[AA]], align 21931// CHECK0-64-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 41932// CHECK0-64-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i641933// CHECK0-64-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()1934// CHECK0-64-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 81935// CHECK0-64-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 41936// CHECK0-64-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 81937// CHECK0-64-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 41938// CHECK0-64-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i641939// CHECK0-64-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]1940// CHECK0-64-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 81941// CHECK0-64-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 81942// CHECK0-64-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 01943// CHECK0-64-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 41944// CHECK0-64-NEXT: store i32 [[TMP6]], i32* [[X]], align 41945// CHECK0-64-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 11946// CHECK0-64-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 41947// CHECK0-64-NEXT: store i32 [[TMP7]], i32* [[Y]], align 41948// CHECK0-64-NEXT: store i32* [[A]], i32** [[P]], align 641949// CHECK0-64-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 41950// CHECK0-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*1951// CHECK0-64-NEXT: store i32 [[TMP8]], i32* [[CONV]], align 41952// CHECK0-64-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 81953// CHECK0-64-NEXT: [[TMP10:%.*]] = load i32*, i32** [[P]], align 641954// CHECK0-64-NEXT: [[TMP11:%.*]] = load i32, i32* @ga, align 41955// CHECK0-64-NEXT: [[CONV2:%.*]] = bitcast i64* [[GA_CASTED]] to i32*1956// CHECK0-64-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 41957// CHECK0-64-NEXT: [[TMP12:%.*]] = load i64, i64* [[GA_CASTED]], align 81958// CHECK0-64-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01959// CHECK0-64-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64*1960// CHECK0-64-NEXT: store i64 [[TMP9]], i64* [[TMP14]], align 81961// CHECK0-64-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 01962// CHECK0-64-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64*1963// CHECK0-64-NEXT: store i64 [[TMP9]], i64* [[TMP16]], align 81964// CHECK0-64-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 01965// CHECK0-64-NEXT: store i8* null, i8** [[TMP17]], align 81966// CHECK0-64-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 11967// CHECK0-64-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32**1968// CHECK0-64-NEXT: store i32* [[TMP10]], i32** [[TMP19]], align 81969// CHECK0-64-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 11970// CHECK0-64-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32**1971// CHECK0-64-NEXT: store i32* [[TMP10]], i32** [[TMP21]], align 81972// CHECK0-64-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 11973// CHECK0-64-NEXT: store i8* null, i8** [[TMP22]], align 81974// CHECK0-64-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 21975// CHECK0-64-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64*1976// CHECK0-64-NEXT: store i64 [[TMP12]], i64* [[TMP24]], align 81977// CHECK0-64-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 21978// CHECK0-64-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64*1979// CHECK0-64-NEXT: store i64 [[TMP12]], i64* [[TMP26]], align 81980// CHECK0-64-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 21981// CHECK0-64-NEXT: store i8* null, i8** [[TMP27]], align 81982// CHECK0-64-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01983// CHECK0-64-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 01984// CHECK0-64-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81985// CHECK0-64-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 01986// CHECK0-64-NEXT: store i32 2, i32* [[TMP30]], align 41987// CHECK0-64-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11988// CHECK0-64-NEXT: store i32 3, i32* [[TMP31]], align 41989// CHECK0-64-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 21990// CHECK0-64-NEXT: store i8** [[TMP28]], i8*** [[TMP32]], align 81991// CHECK0-64-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 31992// CHECK0-64-NEXT: store i8** [[TMP29]], i8*** [[TMP33]], align 81993// CHECK0-64-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 41994// CHECK0-64-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP34]], align 81995// CHECK0-64-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 51996// CHECK0-64-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP35]], align 81997// CHECK0-64-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 61998// CHECK0-64-NEXT: store i8** null, i8*** [[TMP36]], align 81999// CHECK0-64-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 72000// CHECK0-64-NEXT: store i8** null, i8*** [[TMP37]], align 82001// CHECK0-64-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 82002// CHECK0-64-NEXT: store i64 0, i64* [[TMP38]], align 82003// CHECK0-64-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 92004// CHECK0-64-NEXT: store i64 0, i64* [[TMP39]], align 82005// CHECK0-64-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 102006// CHECK0-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP40]], align 42007// CHECK0-64-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 112008// CHECK0-64-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP41]], align 42009// CHECK0-64-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 122010// CHECK0-64-NEXT: store i32 0, i32* [[TMP42]], align 42011// CHECK0-64-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])2012// CHECK0-64-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 02013// CHECK0-64-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]2014// CHECK0-64: omp_offload.failed:2015// CHECK0-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63(i64 [[TMP9]], i32* [[TMP10]], i64 [[TMP12]]) #[[ATTR3:[0-9]+]]2016// CHECK0-64-NEXT: br label [[OMP_OFFLOAD_CONT]]2017// CHECK0-64: omp_offload.cont:2018// CHECK0-64-NEXT: [[TMP45:%.*]] = load i16, i16* [[AA]], align 22019// CHECK0-64-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*2020// CHECK0-64-NEXT: store i16 [[TMP45]], i16* [[CONV3]], align 22021// CHECK0-64-NEXT: [[TMP46:%.*]] = load i64, i64* [[AA_CASTED]], align 82022// CHECK0-64-NEXT: [[TMP47:%.*]] = mul nuw i64 [[TMP1]], 42023// CHECK0-64-NEXT: [[TMP48:%.*]] = mul nuw i64 5, [[TMP4]]2024// CHECK0-64-NEXT: [[TMP49:%.*]] = mul nuw i64 [[TMP48]], 82025// CHECK0-64-NEXT: [[TMP50:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8*2026// CHECK0-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 bitcast ([9 x i64]* @.offload_sizes.1 to i8*), i64 72, i1 false)2027// CHECK0-64-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 02028// CHECK0-64-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i64*2029// CHECK0-64-NEXT: store i64 [[TMP46]], i64* [[TMP52]], align 82030// CHECK0-64-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 02031// CHECK0-64-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to i64*2032// CHECK0-64-NEXT: store i64 [[TMP46]], i64* [[TMP54]], align 82033// CHECK0-64-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 02034// CHECK0-64-NEXT: store i8* null, i8** [[TMP55]], align 82035// CHECK0-64-NEXT: [[TMP56:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 12036// CHECK0-64-NEXT: [[TMP57:%.*]] = bitcast i8** [[TMP56]] to [10 x float]**2037// CHECK0-64-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP57]], align 82038// CHECK0-64-NEXT: [[TMP58:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 12039// CHECK0-64-NEXT: [[TMP59:%.*]] = bitcast i8** [[TMP58]] to [10 x float]**2040// CHECK0-64-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP59]], align 82041// CHECK0-64-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 12042// CHECK0-64-NEXT: store i8* null, i8** [[TMP60]], align 82043// CHECK0-64-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 22044// CHECK0-64-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64*2045// CHECK0-64-NEXT: store i64 [[TMP1]], i64* [[TMP62]], align 82046// CHECK0-64-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 22047// CHECK0-64-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64*2048// CHECK0-64-NEXT: store i64 [[TMP1]], i64* [[TMP64]], align 82049// CHECK0-64-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 22050// CHECK0-64-NEXT: store i8* null, i8** [[TMP65]], align 82051// CHECK0-64-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 32052// CHECK0-64-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to float**2053// CHECK0-64-NEXT: store float* [[VLA]], float** [[TMP67]], align 82054// CHECK0-64-NEXT: [[TMP68:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 32055// CHECK0-64-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to float**2056// CHECK0-64-NEXT: store float* [[VLA]], float** [[TMP69]], align 82057// CHECK0-64-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 32058// CHECK0-64-NEXT: store i64 [[TMP47]], i64* [[TMP70]], align 82059// CHECK0-64-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 32060// CHECK0-64-NEXT: store i8* null, i8** [[TMP71]], align 82061// CHECK0-64-NEXT: [[TMP72:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 42062// CHECK0-64-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to [5 x [10 x double]]**2063// CHECK0-64-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP73]], align 82064// CHECK0-64-NEXT: [[TMP74:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 42065// CHECK0-64-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to [5 x [10 x double]]**2066// CHECK0-64-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP75]], align 82067// CHECK0-64-NEXT: [[TMP76:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 42068// CHECK0-64-NEXT: store i8* null, i8** [[TMP76]], align 82069// CHECK0-64-NEXT: [[TMP77:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 52070// CHECK0-64-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64*2071// CHECK0-64-NEXT: store i64 5, i64* [[TMP78]], align 82072// CHECK0-64-NEXT: [[TMP79:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 52073// CHECK0-64-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i64*2074// CHECK0-64-NEXT: store i64 5, i64* [[TMP80]], align 82075// CHECK0-64-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 52076// CHECK0-64-NEXT: store i8* null, i8** [[TMP81]], align 82077// CHECK0-64-NEXT: [[TMP82:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 62078// CHECK0-64-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64*2079// CHECK0-64-NEXT: store i64 [[TMP4]], i64* [[TMP83]], align 82080// CHECK0-64-NEXT: [[TMP84:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 62081// CHECK0-64-NEXT: [[TMP85:%.*]] = bitcast i8** [[TMP84]] to i64*2082// CHECK0-64-NEXT: store i64 [[TMP4]], i64* [[TMP85]], align 82083// CHECK0-64-NEXT: [[TMP86:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 62084// CHECK0-64-NEXT: store i8* null, i8** [[TMP86]], align 82085// CHECK0-64-NEXT: [[TMP87:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 72086// CHECK0-64-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to double**2087// CHECK0-64-NEXT: store double* [[VLA1]], double** [[TMP88]], align 82088// CHECK0-64-NEXT: [[TMP89:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 72089// CHECK0-64-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to double**2090// CHECK0-64-NEXT: store double* [[VLA1]], double** [[TMP90]], align 82091// CHECK0-64-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 72092// CHECK0-64-NEXT: store i64 [[TMP49]], i64* [[TMP91]], align 82093// CHECK0-64-NEXT: [[TMP92:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 72094// CHECK0-64-NEXT: store i8* null, i8** [[TMP92]], align 82095// CHECK0-64-NEXT: [[TMP93:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 82096// CHECK0-64-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to %struct.TT**2097// CHECK0-64-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP94]], align 82098// CHECK0-64-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 82099// CHECK0-64-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to %struct.TT**2100// CHECK0-64-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP96]], align 82101// CHECK0-64-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 82102// CHECK0-64-NEXT: store i8* null, i8** [[TMP97]], align 82103// CHECK0-64-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 02104// CHECK0-64-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 02105// CHECK0-64-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 02106// CHECK0-64-NEXT: [[KERNEL_ARGS7:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 82107// CHECK0-64-NEXT: [[TMP101:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 02108// CHECK0-64-NEXT: store i32 2, i32* [[TMP101]], align 42109// CHECK0-64-NEXT: [[TMP102:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 12110// CHECK0-64-NEXT: store i32 9, i32* [[TMP102]], align 42111// CHECK0-64-NEXT: [[TMP103:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 22112// CHECK0-64-NEXT: store i8** [[TMP98]], i8*** [[TMP103]], align 82113// CHECK0-64-NEXT: [[TMP104:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 32114// CHECK0-64-NEXT: store i8** [[TMP99]], i8*** [[TMP104]], align 82115// CHECK0-64-NEXT: [[TMP105:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 42116// CHECK0-64-NEXT: store i64* [[TMP100]], i64** [[TMP105]], align 82117// CHECK0-64-NEXT: [[TMP106:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 52118// CHECK0-64-NEXT: store i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.2, i32 0, i32 0), i64** [[TMP106]], align 82119// CHECK0-64-NEXT: [[TMP107:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 62120// CHECK0-64-NEXT: store i8** null, i8*** [[TMP107]], align 82121// CHECK0-64-NEXT: [[TMP108:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 72122// CHECK0-64-NEXT: store i8** null, i8*** [[TMP108]], align 82123// CHECK0-64-NEXT: [[TMP109:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 82124// CHECK0-64-NEXT: store i64 0, i64* [[TMP109]], align 82125// CHECK0-64-NEXT: [[TMP110:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 92126// CHECK0-64-NEXT: store i64 0, i64* [[TMP110]], align 82127// CHECK0-64-NEXT: [[TMP111:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 102128// CHECK0-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP111]], align 42129// CHECK0-64-NEXT: [[TMP112:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 112130// CHECK0-64-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP112]], align 42131// CHECK0-64-NEXT: [[TMP113:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 122132// CHECK0-64-NEXT: store i32 0, i32* [[TMP113]], align 42133// CHECK0-64-NEXT: [[TMP114:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]])2134// CHECK0-64-NEXT: [[TMP115:%.*]] = icmp ne i32 [[TMP114]], 02135// CHECK0-64-NEXT: br i1 [[TMP115]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]]2136// CHECK0-64: omp_offload.failed8:2137// CHECK0-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70(i64 [[TMP46]], [10 x float]* [[B]], i64 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP4]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]2138// CHECK0-64-NEXT: br label [[OMP_OFFLOAD_CONT9]]2139// CHECK0-64: omp_offload.cont9:2140// CHECK0-64-NEXT: [[TMP116:%.*]] = load double*, double** [[PTR_ADDR]], align 82141// CHECK0-64-NEXT: [[TMP117:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 02142// CHECK0-64-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to double**2143// CHECK0-64-NEXT: store double* [[TMP116]], double** [[TMP118]], align 82144// CHECK0-64-NEXT: [[TMP119:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 02145// CHECK0-64-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to double**2146// CHECK0-64-NEXT: store double* [[TMP116]], double** [[TMP120]], align 82147// CHECK0-64-NEXT: [[TMP121:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 02148// CHECK0-64-NEXT: store i8* null, i8** [[TMP121]], align 82149// CHECK0-64-NEXT: [[TMP122:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 12150// CHECK0-64-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to %struct.TT.0**2151// CHECK0-64-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[TMP123]], align 82152// CHECK0-64-NEXT: [[TMP124:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 12153// CHECK0-64-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to %struct.TT.0**2154// CHECK0-64-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[TMP125]], align 82155// CHECK0-64-NEXT: [[TMP126:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 12156// CHECK0-64-NEXT: store i8* null, i8** [[TMP126]], align 82157// CHECK0-64-NEXT: [[TMP127:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 02158// CHECK0-64-NEXT: [[TMP128:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 02159// CHECK0-64-NEXT: [[KERNEL_ARGS13:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 82160// CHECK0-64-NEXT: [[TMP129:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 02161// CHECK0-64-NEXT: store i32 2, i32* [[TMP129]], align 42162// CHECK0-64-NEXT: [[TMP130:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 12163// CHECK0-64-NEXT: store i32 2, i32* [[TMP130]], align 42164// CHECK0-64-NEXT: [[TMP131:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 22165// CHECK0-64-NEXT: store i8** [[TMP127]], i8*** [[TMP131]], align 82166// CHECK0-64-NEXT: [[TMP132:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 32167// CHECK0-64-NEXT: store i8** [[TMP128]], i8*** [[TMP132]], align 82168// CHECK0-64-NEXT: [[TMP133:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 42169// CHECK0-64-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.3, i32 0, i32 0), i64** [[TMP133]], align 82170// CHECK0-64-NEXT: [[TMP134:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 52171// CHECK0-64-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.4, i32 0, i32 0), i64** [[TMP134]], align 82172// CHECK0-64-NEXT: [[TMP135:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 62173// CHECK0-64-NEXT: store i8** null, i8*** [[TMP135]], align 82174// CHECK0-64-NEXT: [[TMP136:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 72175// CHECK0-64-NEXT: store i8** null, i8*** [[TMP136]], align 82176// CHECK0-64-NEXT: [[TMP137:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 82177// CHECK0-64-NEXT: store i64 0, i64* [[TMP137]], align 82178// CHECK0-64-NEXT: [[TMP138:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 92179// CHECK0-64-NEXT: store i64 0, i64* [[TMP138]], align 82180// CHECK0-64-NEXT: [[TMP139:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 102181// CHECK0-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP139]], align 42182// CHECK0-64-NEXT: [[TMP140:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 112183// CHECK0-64-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP140]], align 42184// CHECK0-64-NEXT: [[TMP141:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 122185// CHECK0-64-NEXT: store i32 0, i32* [[TMP141]], align 42186// CHECK0-64-NEXT: [[TMP142:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]])2187// CHECK0-64-NEXT: [[TMP143:%.*]] = icmp ne i32 [[TMP142]], 02188// CHECK0-64-NEXT: br i1 [[TMP143]], label [[OMP_OFFLOAD_FAILED14:%.*]], label [[OMP_OFFLOAD_CONT15:%.*]]2189// CHECK0-64: omp_offload.failed14:2190// CHECK0-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111(double* [[TMP116]], %struct.TT.0* [[E]]) #[[ATTR3]]2191// CHECK0-64-NEXT: br label [[OMP_OFFLOAD_CONT15]]2192// CHECK0-64: omp_offload.cont15:2193// CHECK0-64-NEXT: [[TMP144:%.*]] = load i32, i32* [[A]], align 42194// CHECK0-64-NEXT: [[TMP145:%.*]] = load i8*, i8** [[SAVED_STACK]], align 82195// CHECK0-64-NEXT: call void @llvm.stackrestore(i8* [[TMP145]])2196// CHECK0-64-NEXT: ret i32 [[TMP144]]2197// CHECK0-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l632198// CHECK0-64-SAME: (i64 noundef [[A:%.*]], i32* noundef [[P:%.*]], i64 noundef [[GA:%.*]]) #[[ATTR2:[0-9]+]] {2199// CHECK0-64-NEXT: entry:2200// CHECK0-64-NEXT: [[A_ADDR:%.*]] = alloca i64, align 82201// CHECK0-64-NEXT: [[P_ADDR:%.*]] = alloca i32*, align 82202// CHECK0-64-NEXT: [[GA_ADDR:%.*]] = alloca i64, align 82203// CHECK0-64-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 82204// CHECK0-64-NEXT: store i32* [[P]], i32** [[P_ADDR]], align 82205// CHECK0-64-NEXT: store i64 [[GA]], i64* [[GA_ADDR]], align 82206// CHECK0-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*2207// CHECK0-64-NEXT: [[CONV1:%.*]] = bitcast i64* [[GA_ADDR]] to i32*2208// CHECK0-64-NEXT: ret void2209// CHECK0-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l702210// CHECK0-64-SAME: (i64 noundef [[AA:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {2211// CHECK0-64-NEXT: entry:2212// CHECK0-64-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 82213// CHECK0-64-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 82214// CHECK0-64-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 82215// CHECK0-64-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 82216// CHECK0-64-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 82217// CHECK0-64-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 82218// CHECK0-64-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 82219// CHECK0-64-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 82220// CHECK0-64-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 82221// CHECK0-64-NEXT: [[B5:%.*]] = alloca [10 x float], align 42222// CHECK0-64-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 82223// CHECK0-64-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 82224// CHECK0-64-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 82225// CHECK0-64-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 82226// CHECK0-64-NEXT: [[__VLA_EXPR2:%.*]] = alloca i64, align 82227// CHECK0-64-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 82228// CHECK0-64-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 82229// CHECK0-64-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 82230// CHECK0-64-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 82231// CHECK0-64-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 82232// CHECK0-64-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 82233// CHECK0-64-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 82234// CHECK0-64-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 82235// CHECK0-64-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 82236// CHECK0-64-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 82237// CHECK0-64-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*2238// CHECK0-64-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 82239// CHECK0-64-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 82240// CHECK0-64-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 82241// CHECK0-64-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 82242// CHECK0-64-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 82243// CHECK0-64-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 82244// CHECK0-64-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 82245// CHECK0-64-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 82246// CHECK0-64-NEXT: [[TMP8:%.*]] = bitcast [10 x float]* [[B5]] to i8*2247// CHECK0-64-NEXT: [[TMP9:%.*]] = bitcast [10 x float]* [[TMP0]] to i8*2248// CHECK0-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 40, i1 false)2249// CHECK0-64-NEXT: [[TMP10:%.*]] = call i8* @llvm.stacksave()2250// CHECK0-64-NEXT: store i8* [[TMP10]], i8** [[SAVED_STACK]], align 82251// CHECK0-64-NEXT: [[VLA6:%.*]] = alloca float, i64 [[TMP1]], align 42252// CHECK0-64-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 82253// CHECK0-64-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP1]], 42254// CHECK0-64-NEXT: [[TMP12:%.*]] = bitcast float* [[VLA6]] to i8*2255// CHECK0-64-NEXT: [[TMP13:%.*]] = bitcast float* [[TMP2]] to i8*2256// CHECK0-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 [[TMP11]], i1 false)2257// CHECK0-64-NEXT: [[TMP14:%.*]] = bitcast [5 x [10 x double]]* [[C7]] to i8*2258// CHECK0-64-NEXT: [[TMP15:%.*]] = bitcast [5 x [10 x double]]* [[TMP3]] to i8*2259// CHECK0-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP14]], i8* align 8 [[TMP15]], i64 400, i1 false)2260// CHECK0-64-NEXT: [[TMP16:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]]2261// CHECK0-64-NEXT: [[VLA8:%.*]] = alloca double, i64 [[TMP16]], align 82262// CHECK0-64-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 82263// CHECK0-64-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR2]], align 82264// CHECK0-64-NEXT: [[TMP17:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]]2265// CHECK0-64-NEXT: [[TMP18:%.*]] = mul nuw i64 [[TMP17]], 82266// CHECK0-64-NEXT: [[TMP19:%.*]] = bitcast double* [[VLA8]] to i8*2267// CHECK0-64-NEXT: [[TMP20:%.*]] = bitcast double* [[TMP6]] to i8*2268// CHECK0-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP19]], i8* align 8 [[TMP20]], i64 [[TMP18]], i1 false)2269// CHECK0-64-NEXT: [[TMP21:%.*]] = bitcast %struct.TT* [[D9]] to i8*2270// CHECK0-64-NEXT: [[TMP22:%.*]] = bitcast %struct.TT* [[TMP7]] to i8*2271// CHECK0-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP21]], i8* align 8 [[TMP22]], i64 16, i1 false)2272// CHECK0-64-NEXT: [[TMP23:%.*]] = load i16, i16* [[CONV]], align 22273// CHECK0-64-NEXT: [[CONV10:%.*]] = sext i16 [[TMP23]] to i322274// CHECK0-64-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV10]], 12275// CHECK0-64-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD]] to i162276// CHECK0-64-NEXT: store i16 [[CONV11]], i16* [[CONV]], align 22277// CHECK0-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], i64 0, i64 22278// CHECK0-64-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 42279// CHECK0-64-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA6]], i64 32280// CHECK0-64-NEXT: store float 1.000000e+00, float* [[ARRAYIDX12]], align 42281// CHECK0-64-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], i64 0, i64 12282// CHECK0-64-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i64 0, i64 22283// CHECK0-64-NEXT: store double 1.000000e+00, double* [[ARRAYIDX14]], align 82284// CHECK0-64-NEXT: [[TMP24:%.*]] = mul nsw i64 1, [[TMP5]]2285// CHECK0-64-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[VLA8]], i64 [[TMP24]]2286// CHECK0-64-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 32287// CHECK0-64-NEXT: store double 1.000000e+00, double* [[ARRAYIDX16]], align 82288// CHECK0-64-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 02289// CHECK0-64-NEXT: store i64 1, i64* [[X]], align 82290// CHECK0-64-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 12291// CHECK0-64-NEXT: store i8 1, i8* [[Y]], align 82292// CHECK0-64-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 82293// CHECK0-64-NEXT: call void @llvm.stackrestore(i8* [[TMP25]])2294// CHECK0-64-NEXT: ret void2295// CHECK0-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l1112296// CHECK0-64-SAME: (double* noundef [[PTR:%.*]], %struct.TT.0* noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR2]] {2297// CHECK0-64-NEXT: entry:2298// CHECK0-64-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 82299// CHECK0-64-NEXT: [[E_ADDR:%.*]] = alloca %struct.TT.0*, align 82300// CHECK0-64-NEXT: [[E1:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 42301// CHECK0-64-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 82302// CHECK0-64-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[E_ADDR]], align 82303// CHECK0-64-NEXT: [[TMP0:%.*]] = load %struct.TT.0*, %struct.TT.0** [[E_ADDR]], align 82304// CHECK0-64-NEXT: [[TMP1:%.*]] = bitcast %struct.TT.0* [[E1]] to i8*2305// CHECK0-64-NEXT: [[TMP2:%.*]] = bitcast %struct.TT.0* [[TMP0]] to i8*2306// CHECK0-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 8, i1 false)2307// CHECK0-64-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E1]], i32 0, i32 02308// CHECK0-64-NEXT: [[TMP3:%.*]] = load i32, i32* [[X]], align 42309// CHECK0-64-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP3]] to double2310// CHECK0-64-NEXT: [[TMP4:%.*]] = load double*, double** [[PTR_ADDR]], align 82311// CHECK0-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP4]], i64 02312// CHECK0-64-NEXT: store double [[CONV]], double* [[ARRAYIDX]], align 82313// CHECK0-64-NEXT: [[TMP5:%.*]] = load double*, double** [[PTR_ADDR]], align 82314// CHECK0-64-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, double* [[TMP5]], i64 02315// CHECK0-64-NEXT: [[TMP6:%.*]] = load double, double* [[ARRAYIDX2]], align 82316// CHECK0-64-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+002317// CHECK0-64-NEXT: store double [[INC]], double* [[ARRAYIDX2]], align 82318// CHECK0-64-NEXT: ret void2319// CHECK0-64-LABEL: define {{[^@]+}}@_Z3bariPd2320// CHECK0-64-SAME: (i32 noundef signext [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0]] {2321// CHECK0-64-NEXT: entry:2322// CHECK0-64-NEXT: [[N_ADDR:%.*]] = alloca i32, align 42323// CHECK0-64-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 82324// CHECK0-64-NEXT: [[A:%.*]] = alloca i32, align 42325// CHECK0-64-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 82326// CHECK0-64-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 42327// CHECK0-64-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 82328// CHECK0-64-NEXT: store i32 0, i32* [[A]], align 42329// CHECK0-64-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 42330// CHECK0-64-NEXT: [[TMP1:%.*]] = load double*, double** [[PTR_ADDR]], align 82331// CHECK0-64-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooiPd(i32 noundef signext [[TMP0]], double* noundef [[TMP1]])2332// CHECK0-64-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 42333// CHECK0-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]]2334// CHECK0-64-NEXT: store i32 [[ADD]], i32* [[A]], align 42335// CHECK0-64-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 42336// CHECK0-64-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP3]])2337// CHECK0-64-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 42338// CHECK0-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]]2339// CHECK0-64-NEXT: store i32 [[ADD2]], i32* [[A]], align 42340// CHECK0-64-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 42341// CHECK0-64-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP5]])2342// CHECK0-64-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 42343// CHECK0-64-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]]2344// CHECK0-64-NEXT: store i32 [[ADD4]], i32* [[A]], align 42345// CHECK0-64-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 42346// CHECK0-64-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP7]])2347// CHECK0-64-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 42348// CHECK0-64-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]]2349// CHECK0-64-NEXT: store i32 [[ADD6]], i32* [[A]], align 42350// CHECK0-64-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 42351// CHECK0-64-NEXT: ret i32 [[TMP9]]2352// CHECK0-64-LABEL: define {{[^@]+}}@_ZN2S12r1Ei2353// CHECK0-64-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {2354// CHECK0-64-NEXT: entry:2355// CHECK0-64-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 82356// CHECK0-64-NEXT: [[N_ADDR:%.*]] = alloca i32, align 42357// CHECK0-64-NEXT: [[B:%.*]] = alloca i32, align 42358// CHECK0-64-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 82359// CHECK0-64-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 82360// CHECK0-64-NEXT: [[B_CASTED:%.*]] = alloca i64, align 82361// CHECK0-64-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 82362// CHECK0-64-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 82363// CHECK0-64-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 82364// CHECK0-64-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 82365// CHECK0-64-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 82366// CHECK0-64-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 42367// CHECK0-64-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 82368// CHECK0-64-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 42369// CHECK0-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 12370// CHECK0-64-NEXT: store i32 [[ADD]], i32* [[B]], align 42371// CHECK0-64-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 42372// CHECK0-64-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i642373// CHECK0-64-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()2374// CHECK0-64-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 82375// CHECK0-64-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]2376// CHECK0-64-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 22377// CHECK0-64-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 82378// CHECK0-64-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 42379// CHECK0-64-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*2380// CHECK0-64-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 42381// CHECK0-64-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 82382// CHECK0-64-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 02383// CHECK0-64-NEXT: [[TMP7:%.*]] = mul nuw i64 2, [[TMP2]]2384// CHECK0-64-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP7]], 22385// CHECK0-64-NEXT: [[TMP9:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8*2386// CHECK0-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP9]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes.5 to i8*), i64 40, i1 false)2387// CHECK0-64-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 02388// CHECK0-64-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**2389// CHECK0-64-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 82390// CHECK0-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 02391// CHECK0-64-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**2392// CHECK0-64-NEXT: store double* [[A]], double** [[TMP13]], align 82393// CHECK0-64-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 02394// CHECK0-64-NEXT: store i8* null, i8** [[TMP14]], align 82395// CHECK0-64-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 12396// CHECK0-64-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64*2397// CHECK0-64-NEXT: store i64 [[TMP6]], i64* [[TMP16]], align 82398// CHECK0-64-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 12399// CHECK0-64-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*2400// CHECK0-64-NEXT: store i64 [[TMP6]], i64* [[TMP18]], align 82401// CHECK0-64-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 12402// CHECK0-64-NEXT: store i8* null, i8** [[TMP19]], align 82403// CHECK0-64-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 22404// CHECK0-64-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64*2405// CHECK0-64-NEXT: store i64 2, i64* [[TMP21]], align 82406// CHECK0-64-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 22407// CHECK0-64-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64*2408// CHECK0-64-NEXT: store i64 2, i64* [[TMP23]], align 82409// CHECK0-64-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 22410// CHECK0-64-NEXT: store i8* null, i8** [[TMP24]], align 82411// CHECK0-64-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 32412// CHECK0-64-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64*2413// CHECK0-64-NEXT: store i64 [[TMP2]], i64* [[TMP26]], align 82414// CHECK0-64-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 32415// CHECK0-64-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64*2416// CHECK0-64-NEXT: store i64 [[TMP2]], i64* [[TMP28]], align 82417// CHECK0-64-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 32418// CHECK0-64-NEXT: store i8* null, i8** [[TMP29]], align 82419// CHECK0-64-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 42420// CHECK0-64-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i16**2421// CHECK0-64-NEXT: store i16* [[VLA]], i16** [[TMP31]], align 82422// CHECK0-64-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 42423// CHECK0-64-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i16**2424// CHECK0-64-NEXT: store i16* [[VLA]], i16** [[TMP33]], align 82425// CHECK0-64-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 42426// CHECK0-64-NEXT: store i64 [[TMP8]], i64* [[TMP34]], align 82427// CHECK0-64-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 42428// CHECK0-64-NEXT: store i8* null, i8** [[TMP35]], align 82429// CHECK0-64-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 02430// CHECK0-64-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 02431// CHECK0-64-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 02432// CHECK0-64-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 82433// CHECK0-64-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 02434// CHECK0-64-NEXT: store i32 2, i32* [[TMP39]], align 42435// CHECK0-64-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12436// CHECK0-64-NEXT: store i32 5, i32* [[TMP40]], align 42437// CHECK0-64-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 22438// CHECK0-64-NEXT: store i8** [[TMP36]], i8*** [[TMP41]], align 82439// CHECK0-64-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 32440// CHECK0-64-NEXT: store i8** [[TMP37]], i8*** [[TMP42]], align 82441// CHECK0-64-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 42442// CHECK0-64-NEXT: store i64* [[TMP38]], i64** [[TMP43]], align 82443// CHECK0-64-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 52444// CHECK0-64-NEXT: store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.6, i32 0, i32 0), i64** [[TMP44]], align 82445// CHECK0-64-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 62446// CHECK0-64-NEXT: store i8** null, i8*** [[TMP45]], align 82447// CHECK0-64-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 72448// CHECK0-64-NEXT: store i8** null, i8*** [[TMP46]], align 82449// CHECK0-64-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 82450// CHECK0-64-NEXT: store i64 0, i64* [[TMP47]], align 82451// CHECK0-64-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 92452// CHECK0-64-NEXT: store i64 0, i64* [[TMP48]], align 82453// CHECK0-64-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 102454// CHECK0-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP49]], align 42455// CHECK0-64-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 112456// CHECK0-64-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP50]], align 42457// CHECK0-64-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 122458// CHECK0-64-NEXT: store i32 0, i32* [[TMP51]], align 42459// CHECK0-64-NEXT: [[TMP52:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])2460// CHECK0-64-NEXT: [[TMP53:%.*]] = icmp ne i32 [[TMP52]], 02461// CHECK0-64-NEXT: br i1 [[TMP53]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]2462// CHECK0-64: omp_offload.failed:2463// CHECK0-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]]2464// CHECK0-64-NEXT: br label [[OMP_OFFLOAD_CONT]]2465// CHECK0-64: omp_offload.cont:2466// CHECK0-64-NEXT: [[TMP54:%.*]] = mul nsw i64 1, [[TMP2]]2467// CHECK0-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP54]]2468// CHECK0-64-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 12469// CHECK0-64-NEXT: [[TMP55:%.*]] = load i16, i16* [[ARRAYIDX2]], align 22470// CHECK0-64-NEXT: [[CONV3:%.*]] = sext i16 [[TMP55]] to i322471// CHECK0-64-NEXT: [[TMP56:%.*]] = load i32, i32* [[B]], align 42472// CHECK0-64-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP56]]2473// CHECK0-64-NEXT: [[TMP57:%.*]] = load i8*, i8** [[SAVED_STACK]], align 82474// CHECK0-64-NEXT: call void @llvm.stackrestore(i8* [[TMP57]])2475// CHECK0-64-NEXT: ret i32 [[ADD4]]2476// CHECK0-64-LABEL: define {{[^@]+}}@_ZL7fstatici2477// CHECK0-64-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {2478// CHECK0-64-NEXT: entry:2479// CHECK0-64-NEXT: [[N_ADDR:%.*]] = alloca i32, align 42480// CHECK0-64-NEXT: [[A:%.*]] = alloca i32, align 42481// CHECK0-64-NEXT: [[AAA:%.*]] = alloca i8, align 12482// CHECK0-64-NEXT: [[B:%.*]] = alloca [10 x i32], align 42483// CHECK0-64-NEXT: [[A_CASTED:%.*]] = alloca i64, align 82484// CHECK0-64-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 82485// CHECK0-64-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 82486// CHECK0-64-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 82487// CHECK0-64-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 82488// CHECK0-64-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 42489// CHECK0-64-NEXT: store i32 0, i32* [[A]], align 42490// CHECK0-64-NEXT: store i8 0, i8* [[AAA]], align 12491// CHECK0-64-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 42492// CHECK0-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*2493// CHECK0-64-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 42494// CHECK0-64-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 82495// CHECK0-64-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 12496// CHECK0-64-NEXT: [[CONV1:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*2497// CHECK0-64-NEXT: store i8 [[TMP2]], i8* [[CONV1]], align 12498// CHECK0-64-NEXT: [[TMP3:%.*]] = load i64, i64* [[AAA_CASTED]], align 82499// CHECK0-64-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 02500// CHECK0-64-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*2501// CHECK0-64-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 82502// CHECK0-64-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 02503// CHECK0-64-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64*2504// CHECK0-64-NEXT: store i64 [[TMP1]], i64* [[TMP7]], align 82505// CHECK0-64-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 02506// CHECK0-64-NEXT: store i8* null, i8** [[TMP8]], align 82507// CHECK0-64-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 12508// CHECK0-64-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*2509// CHECK0-64-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 82510// CHECK0-64-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 12511// CHECK0-64-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64*2512// CHECK0-64-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 82513// CHECK0-64-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 12514// CHECK0-64-NEXT: store i8* null, i8** [[TMP13]], align 82515// CHECK0-64-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 22516// CHECK0-64-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [10 x i32]**2517// CHECK0-64-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP15]], align 82518// CHECK0-64-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 22519// CHECK0-64-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [10 x i32]**2520// CHECK0-64-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP17]], align 82521// CHECK0-64-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 22522// CHECK0-64-NEXT: store i8* null, i8** [[TMP18]], align 82523// CHECK0-64-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 02524// CHECK0-64-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 02525// CHECK0-64-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 82526// CHECK0-64-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 02527// CHECK0-64-NEXT: store i32 2, i32* [[TMP21]], align 42528// CHECK0-64-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12529// CHECK0-64-NEXT: store i32 3, i32* [[TMP22]], align 42530// CHECK0-64-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 22531// CHECK0-64-NEXT: store i8** [[TMP19]], i8*** [[TMP23]], align 82532// CHECK0-64-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 32533// CHECK0-64-NEXT: store i8** [[TMP20]], i8*** [[TMP24]], align 82534// CHECK0-64-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 42535// CHECK0-64-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.7, i32 0, i32 0), i64** [[TMP25]], align 82536// CHECK0-64-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 52537// CHECK0-64-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.8, i32 0, i32 0), i64** [[TMP26]], align 82538// CHECK0-64-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 62539// CHECK0-64-NEXT: store i8** null, i8*** [[TMP27]], align 82540// CHECK0-64-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 72541// CHECK0-64-NEXT: store i8** null, i8*** [[TMP28]], align 82542// CHECK0-64-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 82543// CHECK0-64-NEXT: store i64 0, i64* [[TMP29]], align 82544// CHECK0-64-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 92545// CHECK0-64-NEXT: store i64 0, i64* [[TMP30]], align 82546// CHECK0-64-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 102547// CHECK0-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP31]], align 42548// CHECK0-64-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 112549// CHECK0-64-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP32]], align 42550// CHECK0-64-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 122551// CHECK0-64-NEXT: store i32 0, i32* [[TMP33]], align 42552// CHECK0-64-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])2553// CHECK0-64-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 02554// CHECK0-64-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]2555// CHECK0-64: omp_offload.failed:2556// CHECK0-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]2557// CHECK0-64-NEXT: br label [[OMP_OFFLOAD_CONT]]2558// CHECK0-64: omp_offload.cont:2559// CHECK0-64-NEXT: [[TMP36:%.*]] = load i32, i32* [[A]], align 42560// CHECK0-64-NEXT: ret i32 [[TMP36]]2561// CHECK0-64-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i2562// CHECK0-64-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {2563// CHECK0-64-NEXT: entry:2564// CHECK0-64-NEXT: [[N_ADDR:%.*]] = alloca i32, align 42565// CHECK0-64-NEXT: [[A:%.*]] = alloca i32, align 42566// CHECK0-64-NEXT: [[B:%.*]] = alloca [10 x i32], align 42567// CHECK0-64-NEXT: [[A_CASTED:%.*]] = alloca i64, align 82568// CHECK0-64-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 82569// CHECK0-64-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 82570// CHECK0-64-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 82571// CHECK0-64-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 42572// CHECK0-64-NEXT: store i32 0, i32* [[A]], align 42573// CHECK0-64-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 42574// CHECK0-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*2575// CHECK0-64-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 42576// CHECK0-64-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 82577// CHECK0-64-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 02578// CHECK0-64-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64*2579// CHECK0-64-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 82580// CHECK0-64-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 02581// CHECK0-64-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*2582// CHECK0-64-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 82583// CHECK0-64-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 02584// CHECK0-64-NEXT: store i8* null, i8** [[TMP6]], align 82585// CHECK0-64-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 12586// CHECK0-64-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [10 x i32]**2587// CHECK0-64-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP8]], align 82588// CHECK0-64-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 12589// CHECK0-64-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]**2590// CHECK0-64-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP10]], align 82591// CHECK0-64-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 12592// CHECK0-64-NEXT: store i8* null, i8** [[TMP11]], align 82593// CHECK0-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 02594// CHECK0-64-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 02595// CHECK0-64-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 82596// CHECK0-64-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 02597// CHECK0-64-NEXT: store i32 2, i32* [[TMP14]], align 42598// CHECK0-64-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12599// CHECK0-64-NEXT: store i32 2, i32* [[TMP15]], align 42600// CHECK0-64-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 22601// CHECK0-64-NEXT: store i8** [[TMP12]], i8*** [[TMP16]], align 82602// CHECK0-64-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 32603// CHECK0-64-NEXT: store i8** [[TMP13]], i8*** [[TMP17]], align 82604// CHECK0-64-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 42605// CHECK0-64-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.9, i32 0, i32 0), i64** [[TMP18]], align 82606// CHECK0-64-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 52607// CHECK0-64-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.10, i32 0, i32 0), i64** [[TMP19]], align 82608// CHECK0-64-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 62609// CHECK0-64-NEXT: store i8** null, i8*** [[TMP20]], align 82610// CHECK0-64-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 72611// CHECK0-64-NEXT: store i8** null, i8*** [[TMP21]], align 82612// CHECK0-64-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 82613// CHECK0-64-NEXT: store i64 0, i64* [[TMP22]], align 82614// CHECK0-64-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 92615// CHECK0-64-NEXT: store i64 0, i64* [[TMP23]], align 82616// CHECK0-64-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 102617// CHECK0-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP24]], align 42618// CHECK0-64-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 112619// CHECK0-64-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP25]], align 42620// CHECK0-64-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 122621// CHECK0-64-NEXT: store i32 0, i32* [[TMP26]], align 42622// CHECK0-64-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])2623// CHECK0-64-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 02624// CHECK0-64-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]2625// CHECK0-64: omp_offload.failed:2626// CHECK0-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128(i64 [[TMP1]], [10 x i32]* [[B]]) #[[ATTR3]]2627// CHECK0-64-NEXT: br label [[OMP_OFFLOAD_CONT]]2628// CHECK0-64: omp_offload.cont:2629// CHECK0-64-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 42630// CHECK0-64-NEXT: ret i32 [[TMP29]]2631// CHECK0-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l1672632// CHECK0-64-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {2633// CHECK0-64-NEXT: entry:2634// CHECK0-64-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 82635// CHECK0-64-NEXT: [[B_ADDR:%.*]] = alloca i64, align 82636// CHECK0-64-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 82637// CHECK0-64-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 82638// CHECK0-64-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 82639// CHECK0-64-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 82640// CHECK0-64-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 82641// CHECK0-64-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 82642// CHECK0-64-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 82643// CHECK0-64-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 82644// CHECK0-64-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 82645// CHECK0-64-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 82646// CHECK0-64-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 82647// CHECK0-64-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 82648// CHECK0-64-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*2649// CHECK0-64-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 82650// CHECK0-64-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 82651// CHECK0-64-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 82652// CHECK0-64-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave()2653// CHECK0-64-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 82654// CHECK0-64-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]]2655// CHECK0-64-NEXT: [[VLA3:%.*]] = alloca i16, i64 [[TMP5]], align 22656// CHECK0-64-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 82657// CHECK0-64-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR1]], align 82658// CHECK0-64-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]]2659// CHECK0-64-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], 22660// CHECK0-64-NEXT: [[TMP8:%.*]] = bitcast i16* [[VLA3]] to i8*2661// CHECK0-64-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP3]] to i8*2662// CHECK0-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 2 [[TMP8]], i8* align 2 [[TMP9]], i64 [[TMP7]], i1 false)2663// CHECK0-64-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 42664// CHECK0-64-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP10]] to double2665// CHECK0-64-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+002666// CHECK0-64-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 02667// CHECK0-64-NEXT: store double [[ADD]], double* [[A]], align 82668// CHECK0-64-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 02669// CHECK0-64-NEXT: [[TMP11:%.*]] = load double, double* [[A5]], align 82670// CHECK0-64-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+002671// CHECK0-64-NEXT: store double [[INC]], double* [[A5]], align 82672// CHECK0-64-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i162673// CHECK0-64-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP2]]2674// CHECK0-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA3]], i64 [[TMP12]]2675// CHECK0-64-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 12676// CHECK0-64-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 22677// CHECK0-64-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 82678// CHECK0-64-NEXT: call void @llvm.stackrestore(i8* [[TMP13]])2679// CHECK0-64-NEXT: ret void2680// CHECK0-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l1422681// CHECK0-64-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {2682// CHECK0-64-NEXT: entry:2683// CHECK0-64-NEXT: [[A_ADDR:%.*]] = alloca i64, align 82684// CHECK0-64-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 82685// CHECK0-64-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 82686// CHECK0-64-NEXT: [[B2:%.*]] = alloca [10 x i32], align 42687// CHECK0-64-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 82688// CHECK0-64-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 82689// CHECK0-64-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 82690// CHECK0-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*2691// CHECK0-64-NEXT: [[CONV1:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*2692// CHECK0-64-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 82693// CHECK0-64-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B2]] to i8*2694// CHECK0-64-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*2695// CHECK0-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 40, i1 false)2696// CHECK0-64-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 42697// CHECK0-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 12698// CHECK0-64-NEXT: store i32 [[ADD]], i32* [[CONV]], align 42699// CHECK0-64-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 12700// CHECK0-64-NEXT: [[CONV3:%.*]] = sext i8 [[TMP4]] to i322701// CHECK0-64-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 12702// CHECK0-64-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i82703// CHECK0-64-NEXT: store i8 [[CONV5]], i8* [[CONV1]], align 12704// CHECK0-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B2]], i64 0, i64 22705// CHECK0-64-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 42706// CHECK0-64-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP5]], 12707// CHECK0-64-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 42708// CHECK0-64-NEXT: ret void2709// CHECK0-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l1282710// CHECK0-64-SAME: (i64 noundef [[A:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {2711// CHECK0-64-NEXT: entry:2712// CHECK0-64-NEXT: [[A_ADDR:%.*]] = alloca i64, align 82713// CHECK0-64-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 82714// CHECK0-64-NEXT: [[B1:%.*]] = alloca [10 x i32], align 42715// CHECK0-64-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 82716// CHECK0-64-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 82717// CHECK0-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*2718// CHECK0-64-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 82719// CHECK0-64-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8*2720// CHECK0-64-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*2721// CHECK0-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 40, i1 false)2722// CHECK0-64-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 42723// CHECK0-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 12724// CHECK0-64-NEXT: store i32 [[ADD]], i32* [[CONV]], align 42725// CHECK0-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i64 0, i64 22726// CHECK0-64-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 42727// CHECK0-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], 12728// CHECK0-64-NEXT: store i32 [[ADD2]], i32* [[ARRAYIDX]], align 42729// CHECK0-64-NEXT: ret void2730// CHECK0-64-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg2731// CHECK0-64-SAME: () #[[ATTR5:[0-9]+]] {2732// CHECK0-64-NEXT: entry:2733// CHECK0-64-NEXT: call void @__tgt_register_requires(i64 1)2734// CHECK0-64-NEXT: ret void2735// CHECK1-64-LABEL: define {{[^@]+}}@_Z3fooiPd2736// CHECK1-64-SAME: (i32 noundef signext [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {2737// CHECK1-64-NEXT: entry:2738// CHECK1-64-NEXT: [[N_ADDR:%.*]] = alloca i32, align 42739// CHECK1-64-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 82740// CHECK1-64-NEXT: [[A:%.*]] = alloca i32, align 42741// CHECK1-64-NEXT: [[AA:%.*]] = alloca i16, align 22742// CHECK1-64-NEXT: [[B:%.*]] = alloca [10 x float], align 42743// CHECK1-64-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 82744// CHECK1-64-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 82745// CHECK1-64-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 82746// CHECK1-64-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 82747// CHECK1-64-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 82748// CHECK1-64-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 42749// CHECK1-64-NEXT: [[P:%.*]] = alloca i32*, align 642750// CHECK1-64-NEXT: [[A_CASTED:%.*]] = alloca i64, align 82751// CHECK1-64-NEXT: [[GA_CASTED:%.*]] = alloca i64, align 82752// CHECK1-64-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 82753// CHECK1-64-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 82754// CHECK1-64-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 82755// CHECK1-64-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 82756// CHECK1-64-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [9 x i8*], align 82757// CHECK1-64-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [9 x i8*], align 82758// CHECK1-64-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [9 x i8*], align 82759// CHECK1-64-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 82760// CHECK1-64-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x i8*], align 82761// CHECK1-64-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x i8*], align 82762// CHECK1-64-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x i8*], align 82763// CHECK1-64-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 42764// CHECK1-64-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 82765// CHECK1-64-NEXT: store i32 0, i32* [[A]], align 42766// CHECK1-64-NEXT: store i16 0, i16* [[AA]], align 22767// CHECK1-64-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 42768// CHECK1-64-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i642769// CHECK1-64-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()2770// CHECK1-64-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 82771// CHECK1-64-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 42772// CHECK1-64-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 82773// CHECK1-64-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 42774// CHECK1-64-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i642775// CHECK1-64-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]2776// CHECK1-64-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 82777// CHECK1-64-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 82778// CHECK1-64-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 02779// CHECK1-64-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 42780// CHECK1-64-NEXT: store i32 [[TMP6]], i32* [[X]], align 42781// CHECK1-64-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 12782// CHECK1-64-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 42783// CHECK1-64-NEXT: store i32 [[TMP7]], i32* [[Y]], align 42784// CHECK1-64-NEXT: store i32* [[A]], i32** [[P]], align 642785// CHECK1-64-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 42786// CHECK1-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*2787// CHECK1-64-NEXT: store i32 [[TMP8]], i32* [[CONV]], align 42788// CHECK1-64-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 82789// CHECK1-64-NEXT: [[TMP10:%.*]] = load i32*, i32** [[P]], align 642790// CHECK1-64-NEXT: [[TMP11:%.*]] = load i32, i32* @ga, align 42791// CHECK1-64-NEXT: [[CONV2:%.*]] = bitcast i64* [[GA_CASTED]] to i32*2792// CHECK1-64-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 42793// CHECK1-64-NEXT: [[TMP12:%.*]] = load i64, i64* [[GA_CASTED]], align 82794// CHECK1-64-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 02795// CHECK1-64-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64*2796// CHECK1-64-NEXT: store i64 [[TMP9]], i64* [[TMP14]], align 82797// CHECK1-64-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 02798// CHECK1-64-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64*2799// CHECK1-64-NEXT: store i64 [[TMP9]], i64* [[TMP16]], align 82800// CHECK1-64-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 02801// CHECK1-64-NEXT: store i8* null, i8** [[TMP17]], align 82802// CHECK1-64-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 12803// CHECK1-64-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32**2804// CHECK1-64-NEXT: store i32* [[TMP10]], i32** [[TMP19]], align 82805// CHECK1-64-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 12806// CHECK1-64-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32**2807// CHECK1-64-NEXT: store i32* [[TMP10]], i32** [[TMP21]], align 82808// CHECK1-64-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 12809// CHECK1-64-NEXT: store i8* null, i8** [[TMP22]], align 82810// CHECK1-64-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 22811// CHECK1-64-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64*2812// CHECK1-64-NEXT: store i64 [[TMP12]], i64* [[TMP24]], align 82813// CHECK1-64-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 22814// CHECK1-64-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64*2815// CHECK1-64-NEXT: store i64 [[TMP12]], i64* [[TMP26]], align 82816// CHECK1-64-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 22817// CHECK1-64-NEXT: store i8* null, i8** [[TMP27]], align 82818// CHECK1-64-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 02819// CHECK1-64-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 02820// CHECK1-64-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 82821// CHECK1-64-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 02822// CHECK1-64-NEXT: store i32 2, i32* [[TMP30]], align 42823// CHECK1-64-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12824// CHECK1-64-NEXT: store i32 3, i32* [[TMP31]], align 42825// CHECK1-64-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 22826// CHECK1-64-NEXT: store i8** [[TMP28]], i8*** [[TMP32]], align 82827// CHECK1-64-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 32828// CHECK1-64-NEXT: store i8** [[TMP29]], i8*** [[TMP33]], align 82829// CHECK1-64-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 42830// CHECK1-64-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP34]], align 82831// CHECK1-64-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 52832// CHECK1-64-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP35]], align 82833// CHECK1-64-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 62834// CHECK1-64-NEXT: store i8** null, i8*** [[TMP36]], align 82835// CHECK1-64-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 72836// CHECK1-64-NEXT: store i8** null, i8*** [[TMP37]], align 82837// CHECK1-64-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 82838// CHECK1-64-NEXT: store i64 0, i64* [[TMP38]], align 82839// CHECK1-64-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 92840// CHECK1-64-NEXT: store i64 0, i64* [[TMP39]], align 82841// CHECK1-64-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 102842// CHECK1-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP40]], align 42843// CHECK1-64-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 112844// CHECK1-64-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP41]], align 42845// CHECK1-64-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 122846// CHECK1-64-NEXT: store i32 0, i32* [[TMP42]], align 42847// CHECK1-64-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])2848// CHECK1-64-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 02849// CHECK1-64-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]2850// CHECK1-64: omp_offload.failed:2851// CHECK1-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63(i64 [[TMP9]], i32* [[TMP10]], i64 [[TMP12]]) #[[ATTR3:[0-9]+]]2852// CHECK1-64-NEXT: br label [[OMP_OFFLOAD_CONT]]2853// CHECK1-64: omp_offload.cont:2854// CHECK1-64-NEXT: [[TMP45:%.*]] = load i16, i16* [[AA]], align 22855// CHECK1-64-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*2856// CHECK1-64-NEXT: store i16 [[TMP45]], i16* [[CONV3]], align 22857// CHECK1-64-NEXT: [[TMP46:%.*]] = load i64, i64* [[AA_CASTED]], align 82858// CHECK1-64-NEXT: [[TMP47:%.*]] = mul nuw i64 [[TMP1]], 42859// CHECK1-64-NEXT: [[TMP48:%.*]] = mul nuw i64 5, [[TMP4]]2860// CHECK1-64-NEXT: [[TMP49:%.*]] = mul nuw i64 [[TMP48]], 82861// CHECK1-64-NEXT: [[TMP50:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8*2862// CHECK1-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 bitcast ([9 x i64]* @.offload_sizes.1 to i8*), i64 72, i1 false)2863// CHECK1-64-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 02864// CHECK1-64-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i64*2865// CHECK1-64-NEXT: store i64 [[TMP46]], i64* [[TMP52]], align 82866// CHECK1-64-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 02867// CHECK1-64-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to i64*2868// CHECK1-64-NEXT: store i64 [[TMP46]], i64* [[TMP54]], align 82869// CHECK1-64-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 02870// CHECK1-64-NEXT: store i8* null, i8** [[TMP55]], align 82871// CHECK1-64-NEXT: [[TMP56:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 12872// CHECK1-64-NEXT: [[TMP57:%.*]] = bitcast i8** [[TMP56]] to [10 x float]**2873// CHECK1-64-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP57]], align 82874// CHECK1-64-NEXT: [[TMP58:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 12875// CHECK1-64-NEXT: [[TMP59:%.*]] = bitcast i8** [[TMP58]] to [10 x float]**2876// CHECK1-64-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP59]], align 82877// CHECK1-64-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 12878// CHECK1-64-NEXT: store i8* null, i8** [[TMP60]], align 82879// CHECK1-64-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 22880// CHECK1-64-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64*2881// CHECK1-64-NEXT: store i64 [[TMP1]], i64* [[TMP62]], align 82882// CHECK1-64-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 22883// CHECK1-64-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64*2884// CHECK1-64-NEXT: store i64 [[TMP1]], i64* [[TMP64]], align 82885// CHECK1-64-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 22886// CHECK1-64-NEXT: store i8* null, i8** [[TMP65]], align 82887// CHECK1-64-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 32888// CHECK1-64-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to float**2889// CHECK1-64-NEXT: store float* [[VLA]], float** [[TMP67]], align 82890// CHECK1-64-NEXT: [[TMP68:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 32891// CHECK1-64-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to float**2892// CHECK1-64-NEXT: store float* [[VLA]], float** [[TMP69]], align 82893// CHECK1-64-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 32894// CHECK1-64-NEXT: store i64 [[TMP47]], i64* [[TMP70]], align 82895// CHECK1-64-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 32896// CHECK1-64-NEXT: store i8* null, i8** [[TMP71]], align 82897// CHECK1-64-NEXT: [[TMP72:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 42898// CHECK1-64-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to [5 x [10 x double]]**2899// CHECK1-64-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP73]], align 82900// CHECK1-64-NEXT: [[TMP74:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 42901// CHECK1-64-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to [5 x [10 x double]]**2902// CHECK1-64-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP75]], align 82903// CHECK1-64-NEXT: [[TMP76:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 42904// CHECK1-64-NEXT: store i8* null, i8** [[TMP76]], align 82905// CHECK1-64-NEXT: [[TMP77:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 52906// CHECK1-64-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64*2907// CHECK1-64-NEXT: store i64 5, i64* [[TMP78]], align 82908// CHECK1-64-NEXT: [[TMP79:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 52909// CHECK1-64-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i64*2910// CHECK1-64-NEXT: store i64 5, i64* [[TMP80]], align 82911// CHECK1-64-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 52912// CHECK1-64-NEXT: store i8* null, i8** [[TMP81]], align 82913// CHECK1-64-NEXT: [[TMP82:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 62914// CHECK1-64-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64*2915// CHECK1-64-NEXT: store i64 [[TMP4]], i64* [[TMP83]], align 82916// CHECK1-64-NEXT: [[TMP84:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 62917// CHECK1-64-NEXT: [[TMP85:%.*]] = bitcast i8** [[TMP84]] to i64*2918// CHECK1-64-NEXT: store i64 [[TMP4]], i64* [[TMP85]], align 82919// CHECK1-64-NEXT: [[TMP86:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 62920// CHECK1-64-NEXT: store i8* null, i8** [[TMP86]], align 82921// CHECK1-64-NEXT: [[TMP87:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 72922// CHECK1-64-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to double**2923// CHECK1-64-NEXT: store double* [[VLA1]], double** [[TMP88]], align 82924// CHECK1-64-NEXT: [[TMP89:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 72925// CHECK1-64-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to double**2926// CHECK1-64-NEXT: store double* [[VLA1]], double** [[TMP90]], align 82927// CHECK1-64-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 72928// CHECK1-64-NEXT: store i64 [[TMP49]], i64* [[TMP91]], align 82929// CHECK1-64-NEXT: [[TMP92:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 72930// CHECK1-64-NEXT: store i8* null, i8** [[TMP92]], align 82931// CHECK1-64-NEXT: [[TMP93:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 82932// CHECK1-64-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to %struct.TT**2933// CHECK1-64-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP94]], align 82934// CHECK1-64-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 82935// CHECK1-64-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to %struct.TT**2936// CHECK1-64-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP96]], align 82937// CHECK1-64-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 82938// CHECK1-64-NEXT: store i8* null, i8** [[TMP97]], align 82939// CHECK1-64-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 02940// CHECK1-64-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 02941// CHECK1-64-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 02942// CHECK1-64-NEXT: [[KERNEL_ARGS7:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 82943// CHECK1-64-NEXT: [[TMP101:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 02944// CHECK1-64-NEXT: store i32 2, i32* [[TMP101]], align 42945// CHECK1-64-NEXT: [[TMP102:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 12946// CHECK1-64-NEXT: store i32 9, i32* [[TMP102]], align 42947// CHECK1-64-NEXT: [[TMP103:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 22948// CHECK1-64-NEXT: store i8** [[TMP98]], i8*** [[TMP103]], align 82949// CHECK1-64-NEXT: [[TMP104:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 32950// CHECK1-64-NEXT: store i8** [[TMP99]], i8*** [[TMP104]], align 82951// CHECK1-64-NEXT: [[TMP105:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 42952// CHECK1-64-NEXT: store i64* [[TMP100]], i64** [[TMP105]], align 82953// CHECK1-64-NEXT: [[TMP106:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 52954// CHECK1-64-NEXT: store i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.2, i32 0, i32 0), i64** [[TMP106]], align 82955// CHECK1-64-NEXT: [[TMP107:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 62956// CHECK1-64-NEXT: store i8** null, i8*** [[TMP107]], align 82957// CHECK1-64-NEXT: [[TMP108:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 72958// CHECK1-64-NEXT: store i8** null, i8*** [[TMP108]], align 82959// CHECK1-64-NEXT: [[TMP109:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 82960// CHECK1-64-NEXT: store i64 0, i64* [[TMP109]], align 82961// CHECK1-64-NEXT: [[TMP110:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 92962// CHECK1-64-NEXT: store i64 0, i64* [[TMP110]], align 82963// CHECK1-64-NEXT: [[TMP111:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 102964// CHECK1-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP111]], align 42965// CHECK1-64-NEXT: [[TMP112:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 112966// CHECK1-64-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP112]], align 42967// CHECK1-64-NEXT: [[TMP113:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 122968// CHECK1-64-NEXT: store i32 0, i32* [[TMP113]], align 42969// CHECK1-64-NEXT: [[TMP114:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]])2970// CHECK1-64-NEXT: [[TMP115:%.*]] = icmp ne i32 [[TMP114]], 02971// CHECK1-64-NEXT: br i1 [[TMP115]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]]2972// CHECK1-64: omp_offload.failed8:2973// CHECK1-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70(i64 [[TMP46]], [10 x float]* [[B]], i64 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP4]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]2974// CHECK1-64-NEXT: br label [[OMP_OFFLOAD_CONT9]]2975// CHECK1-64: omp_offload.cont9:2976// CHECK1-64-NEXT: [[TMP116:%.*]] = load double*, double** [[PTR_ADDR]], align 82977// CHECK1-64-NEXT: [[TMP117:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 02978// CHECK1-64-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to double**2979// CHECK1-64-NEXT: store double* [[TMP116]], double** [[TMP118]], align 82980// CHECK1-64-NEXT: [[TMP119:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 02981// CHECK1-64-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to double**2982// CHECK1-64-NEXT: store double* [[TMP116]], double** [[TMP120]], align 82983// CHECK1-64-NEXT: [[TMP121:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 02984// CHECK1-64-NEXT: store i8* null, i8** [[TMP121]], align 82985// CHECK1-64-NEXT: [[TMP122:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 12986// CHECK1-64-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to %struct.TT.0**2987// CHECK1-64-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[TMP123]], align 82988// CHECK1-64-NEXT: [[TMP124:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 12989// CHECK1-64-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to %struct.TT.0**2990// CHECK1-64-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[TMP125]], align 82991// CHECK1-64-NEXT: [[TMP126:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 12992// CHECK1-64-NEXT: store i8* null, i8** [[TMP126]], align 82993// CHECK1-64-NEXT: [[TMP127:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 02994// CHECK1-64-NEXT: [[TMP128:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 02995// CHECK1-64-NEXT: [[KERNEL_ARGS13:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 82996// CHECK1-64-NEXT: [[TMP129:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 02997// CHECK1-64-NEXT: store i32 2, i32* [[TMP129]], align 42998// CHECK1-64-NEXT: [[TMP130:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 12999// CHECK1-64-NEXT: store i32 2, i32* [[TMP130]], align 43000// CHECK1-64-NEXT: [[TMP131:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 23001// CHECK1-64-NEXT: store i8** [[TMP127]], i8*** [[TMP131]], align 83002// CHECK1-64-NEXT: [[TMP132:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 33003// CHECK1-64-NEXT: store i8** [[TMP128]], i8*** [[TMP132]], align 83004// CHECK1-64-NEXT: [[TMP133:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 43005// CHECK1-64-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.3, i32 0, i32 0), i64** [[TMP133]], align 83006// CHECK1-64-NEXT: [[TMP134:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 53007// CHECK1-64-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.4, i32 0, i32 0), i64** [[TMP134]], align 83008// CHECK1-64-NEXT: [[TMP135:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 63009// CHECK1-64-NEXT: store i8** null, i8*** [[TMP135]], align 83010// CHECK1-64-NEXT: [[TMP136:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 73011// CHECK1-64-NEXT: store i8** null, i8*** [[TMP136]], align 83012// CHECK1-64-NEXT: [[TMP137:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 83013// CHECK1-64-NEXT: store i64 0, i64* [[TMP137]], align 83014// CHECK1-64-NEXT: [[TMP138:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 93015// CHECK1-64-NEXT: store i64 0, i64* [[TMP138]], align 83016// CHECK1-64-NEXT: [[TMP139:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 103017// CHECK1-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP139]], align 43018// CHECK1-64-NEXT: [[TMP140:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 113019// CHECK1-64-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP140]], align 43020// CHECK1-64-NEXT: [[TMP141:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 123021// CHECK1-64-NEXT: store i32 0, i32* [[TMP141]], align 43022// CHECK1-64-NEXT: [[TMP142:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]])3023// CHECK1-64-NEXT: [[TMP143:%.*]] = icmp ne i32 [[TMP142]], 03024// CHECK1-64-NEXT: br i1 [[TMP143]], label [[OMP_OFFLOAD_FAILED14:%.*]], label [[OMP_OFFLOAD_CONT15:%.*]]3025// CHECK1-64: omp_offload.failed14:3026// CHECK1-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111(double* [[TMP116]], %struct.TT.0* [[E]]) #[[ATTR3]]3027// CHECK1-64-NEXT: br label [[OMP_OFFLOAD_CONT15]]3028// CHECK1-64: omp_offload.cont15:3029// CHECK1-64-NEXT: [[TMP144:%.*]] = load i32, i32* [[A]], align 43030// CHECK1-64-NEXT: [[TMP145:%.*]] = load i8*, i8** [[SAVED_STACK]], align 83031// CHECK1-64-NEXT: call void @llvm.stackrestore(i8* [[TMP145]])3032// CHECK1-64-NEXT: ret i32 [[TMP144]]3033// CHECK1-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l633034// CHECK1-64-SAME: (i64 noundef [[A:%.*]], i32* noundef [[P:%.*]], i64 noundef [[GA:%.*]]) #[[ATTR2:[0-9]+]] {3035// CHECK1-64-NEXT: entry:3036// CHECK1-64-NEXT: [[A_ADDR:%.*]] = alloca i64, align 83037// CHECK1-64-NEXT: [[P_ADDR:%.*]] = alloca i32*, align 83038// CHECK1-64-NEXT: [[GA_ADDR:%.*]] = alloca i64, align 83039// CHECK1-64-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 83040// CHECK1-64-NEXT: store i32* [[P]], i32** [[P_ADDR]], align 83041// CHECK1-64-NEXT: store i64 [[GA]], i64* [[GA_ADDR]], align 83042// CHECK1-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*3043// CHECK1-64-NEXT: [[CONV1:%.*]] = bitcast i64* [[GA_ADDR]] to i32*3044// CHECK1-64-NEXT: ret void3045// CHECK1-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l703046// CHECK1-64-SAME: (i64 noundef [[AA:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {3047// CHECK1-64-NEXT: entry:3048// CHECK1-64-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 83049// CHECK1-64-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 83050// CHECK1-64-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 83051// CHECK1-64-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 83052// CHECK1-64-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 83053// CHECK1-64-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 83054// CHECK1-64-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 83055// CHECK1-64-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 83056// CHECK1-64-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 83057// CHECK1-64-NEXT: [[B5:%.*]] = alloca [10 x float], align 43058// CHECK1-64-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 83059// CHECK1-64-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 83060// CHECK1-64-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 83061// CHECK1-64-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 83062// CHECK1-64-NEXT: [[__VLA_EXPR2:%.*]] = alloca i64, align 83063// CHECK1-64-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 83064// CHECK1-64-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 83065// CHECK1-64-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 83066// CHECK1-64-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 83067// CHECK1-64-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 83068// CHECK1-64-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 83069// CHECK1-64-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 83070// CHECK1-64-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 83071// CHECK1-64-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 83072// CHECK1-64-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 83073// CHECK1-64-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*3074// CHECK1-64-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 83075// CHECK1-64-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 83076// CHECK1-64-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 83077// CHECK1-64-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 83078// CHECK1-64-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 83079// CHECK1-64-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 83080// CHECK1-64-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 83081// CHECK1-64-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 83082// CHECK1-64-NEXT: [[TMP8:%.*]] = bitcast [10 x float]* [[B5]] to i8*3083// CHECK1-64-NEXT: [[TMP9:%.*]] = bitcast [10 x float]* [[TMP0]] to i8*3084// CHECK1-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 40, i1 false)3085// CHECK1-64-NEXT: [[TMP10:%.*]] = call i8* @llvm.stacksave()3086// CHECK1-64-NEXT: store i8* [[TMP10]], i8** [[SAVED_STACK]], align 83087// CHECK1-64-NEXT: [[VLA6:%.*]] = alloca float, i64 [[TMP1]], align 43088// CHECK1-64-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 83089// CHECK1-64-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP1]], 43090// CHECK1-64-NEXT: [[TMP12:%.*]] = bitcast float* [[VLA6]] to i8*3091// CHECK1-64-NEXT: [[TMP13:%.*]] = bitcast float* [[TMP2]] to i8*3092// CHECK1-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 [[TMP11]], i1 false)3093// CHECK1-64-NEXT: [[TMP14:%.*]] = bitcast [5 x [10 x double]]* [[C7]] to i8*3094// CHECK1-64-NEXT: [[TMP15:%.*]] = bitcast [5 x [10 x double]]* [[TMP3]] to i8*3095// CHECK1-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP14]], i8* align 8 [[TMP15]], i64 400, i1 false)3096// CHECK1-64-NEXT: [[TMP16:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]]3097// CHECK1-64-NEXT: [[VLA8:%.*]] = alloca double, i64 [[TMP16]], align 83098// CHECK1-64-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 83099// CHECK1-64-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR2]], align 83100// CHECK1-64-NEXT: [[TMP17:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]]3101// CHECK1-64-NEXT: [[TMP18:%.*]] = mul nuw i64 [[TMP17]], 83102// CHECK1-64-NEXT: [[TMP19:%.*]] = bitcast double* [[VLA8]] to i8*3103// CHECK1-64-NEXT: [[TMP20:%.*]] = bitcast double* [[TMP6]] to i8*3104// CHECK1-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP19]], i8* align 8 [[TMP20]], i64 [[TMP18]], i1 false)3105// CHECK1-64-NEXT: [[TMP21:%.*]] = bitcast %struct.TT* [[D9]] to i8*3106// CHECK1-64-NEXT: [[TMP22:%.*]] = bitcast %struct.TT* [[TMP7]] to i8*3107// CHECK1-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP21]], i8* align 8 [[TMP22]], i64 16, i1 false)3108// CHECK1-64-NEXT: [[TMP23:%.*]] = load i16, i16* [[CONV]], align 23109// CHECK1-64-NEXT: [[CONV10:%.*]] = sext i16 [[TMP23]] to i323110// CHECK1-64-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV10]], 13111// CHECK1-64-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD]] to i163112// CHECK1-64-NEXT: store i16 [[CONV11]], i16* [[CONV]], align 23113// CHECK1-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], i64 0, i64 23114// CHECK1-64-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 43115// CHECK1-64-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA6]], i64 33116// CHECK1-64-NEXT: store float 1.000000e+00, float* [[ARRAYIDX12]], align 43117// CHECK1-64-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], i64 0, i64 13118// CHECK1-64-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i64 0, i64 23119// CHECK1-64-NEXT: store double 1.000000e+00, double* [[ARRAYIDX14]], align 83120// CHECK1-64-NEXT: [[TMP24:%.*]] = mul nsw i64 1, [[TMP5]]3121// CHECK1-64-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[VLA8]], i64 [[TMP24]]3122// CHECK1-64-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 33123// CHECK1-64-NEXT: store double 1.000000e+00, double* [[ARRAYIDX16]], align 83124// CHECK1-64-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 03125// CHECK1-64-NEXT: store i64 1, i64* [[X]], align 83126// CHECK1-64-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 13127// CHECK1-64-NEXT: store i8 1, i8* [[Y]], align 83128// CHECK1-64-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 83129// CHECK1-64-NEXT: call void @llvm.stackrestore(i8* [[TMP25]])3130// CHECK1-64-NEXT: ret void3131// CHECK1-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l1113132// CHECK1-64-SAME: (double* noundef [[PTR:%.*]], %struct.TT.0* noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR2]] {3133// CHECK1-64-NEXT: entry:3134// CHECK1-64-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 83135// CHECK1-64-NEXT: [[E_ADDR:%.*]] = alloca %struct.TT.0*, align 83136// CHECK1-64-NEXT: [[E1:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 43137// CHECK1-64-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 83138// CHECK1-64-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[E_ADDR]], align 83139// CHECK1-64-NEXT: [[TMP0:%.*]] = load %struct.TT.0*, %struct.TT.0** [[E_ADDR]], align 83140// CHECK1-64-NEXT: [[TMP1:%.*]] = bitcast %struct.TT.0* [[E1]] to i8*3141// CHECK1-64-NEXT: [[TMP2:%.*]] = bitcast %struct.TT.0* [[TMP0]] to i8*3142// CHECK1-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 8, i1 false)3143// CHECK1-64-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E1]], i32 0, i32 03144// CHECK1-64-NEXT: [[TMP3:%.*]] = load i32, i32* [[X]], align 43145// CHECK1-64-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP3]] to double3146// CHECK1-64-NEXT: [[TMP4:%.*]] = load double*, double** [[PTR_ADDR]], align 83147// CHECK1-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP4]], i64 03148// CHECK1-64-NEXT: store double [[CONV]], double* [[ARRAYIDX]], align 83149// CHECK1-64-NEXT: [[TMP5:%.*]] = load double*, double** [[PTR_ADDR]], align 83150// CHECK1-64-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, double* [[TMP5]], i64 03151// CHECK1-64-NEXT: [[TMP6:%.*]] = load double, double* [[ARRAYIDX2]], align 83152// CHECK1-64-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+003153// CHECK1-64-NEXT: store double [[INC]], double* [[ARRAYIDX2]], align 83154// CHECK1-64-NEXT: ret void3155// CHECK1-64-LABEL: define {{[^@]+}}@_Z3bariPd3156// CHECK1-64-SAME: (i32 noundef signext [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0]] {3157// CHECK1-64-NEXT: entry:3158// CHECK1-64-NEXT: [[N_ADDR:%.*]] = alloca i32, align 43159// CHECK1-64-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 83160// CHECK1-64-NEXT: [[A:%.*]] = alloca i32, align 43161// CHECK1-64-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 83162// CHECK1-64-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 43163// CHECK1-64-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 83164// CHECK1-64-NEXT: store i32 0, i32* [[A]], align 43165// CHECK1-64-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 43166// CHECK1-64-NEXT: [[TMP1:%.*]] = load double*, double** [[PTR_ADDR]], align 83167// CHECK1-64-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooiPd(i32 noundef signext [[TMP0]], double* noundef [[TMP1]])3168// CHECK1-64-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 43169// CHECK1-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]]3170// CHECK1-64-NEXT: store i32 [[ADD]], i32* [[A]], align 43171// CHECK1-64-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 43172// CHECK1-64-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP3]])3173// CHECK1-64-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 43174// CHECK1-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]]3175// CHECK1-64-NEXT: store i32 [[ADD2]], i32* [[A]], align 43176// CHECK1-64-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 43177// CHECK1-64-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP5]])3178// CHECK1-64-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 43179// CHECK1-64-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]]3180// CHECK1-64-NEXT: store i32 [[ADD4]], i32* [[A]], align 43181// CHECK1-64-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 43182// CHECK1-64-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP7]])3183// CHECK1-64-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 43184// CHECK1-64-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]]3185// CHECK1-64-NEXT: store i32 [[ADD6]], i32* [[A]], align 43186// CHECK1-64-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 43187// CHECK1-64-NEXT: ret i32 [[TMP9]]3188// CHECK1-64-LABEL: define {{[^@]+}}@_ZN2S12r1Ei3189// CHECK1-64-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {3190// CHECK1-64-NEXT: entry:3191// CHECK1-64-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 83192// CHECK1-64-NEXT: [[N_ADDR:%.*]] = alloca i32, align 43193// CHECK1-64-NEXT: [[B:%.*]] = alloca i32, align 43194// CHECK1-64-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 83195// CHECK1-64-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 83196// CHECK1-64-NEXT: [[B_CASTED:%.*]] = alloca i64, align 83197// CHECK1-64-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 83198// CHECK1-64-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 83199// CHECK1-64-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 83200// CHECK1-64-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 83201// CHECK1-64-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 83202// CHECK1-64-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 43203// CHECK1-64-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 83204// CHECK1-64-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 43205// CHECK1-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 13206// CHECK1-64-NEXT: store i32 [[ADD]], i32* [[B]], align 43207// CHECK1-64-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 43208// CHECK1-64-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i643209// CHECK1-64-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()3210// CHECK1-64-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 83211// CHECK1-64-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]3212// CHECK1-64-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 23213// CHECK1-64-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 83214// CHECK1-64-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 43215// CHECK1-64-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*3216// CHECK1-64-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 43217// CHECK1-64-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 83218// CHECK1-64-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 03219// CHECK1-64-NEXT: [[TMP7:%.*]] = mul nuw i64 2, [[TMP2]]3220// CHECK1-64-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP7]], 23221// CHECK1-64-NEXT: [[TMP9:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8*3222// CHECK1-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP9]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes.5 to i8*), i64 40, i1 false)3223// CHECK1-64-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 03224// CHECK1-64-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**3225// CHECK1-64-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 83226// CHECK1-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 03227// CHECK1-64-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**3228// CHECK1-64-NEXT: store double* [[A]], double** [[TMP13]], align 83229// CHECK1-64-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 03230// CHECK1-64-NEXT: store i8* null, i8** [[TMP14]], align 83231// CHECK1-64-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 13232// CHECK1-64-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64*3233// CHECK1-64-NEXT: store i64 [[TMP6]], i64* [[TMP16]], align 83234// CHECK1-64-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 13235// CHECK1-64-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*3236// CHECK1-64-NEXT: store i64 [[TMP6]], i64* [[TMP18]], align 83237// CHECK1-64-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 13238// CHECK1-64-NEXT: store i8* null, i8** [[TMP19]], align 83239// CHECK1-64-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 23240// CHECK1-64-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64*3241// CHECK1-64-NEXT: store i64 2, i64* [[TMP21]], align 83242// CHECK1-64-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 23243// CHECK1-64-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64*3244// CHECK1-64-NEXT: store i64 2, i64* [[TMP23]], align 83245// CHECK1-64-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 23246// CHECK1-64-NEXT: store i8* null, i8** [[TMP24]], align 83247// CHECK1-64-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 33248// CHECK1-64-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64*3249// CHECK1-64-NEXT: store i64 [[TMP2]], i64* [[TMP26]], align 83250// CHECK1-64-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 33251// CHECK1-64-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64*3252// CHECK1-64-NEXT: store i64 [[TMP2]], i64* [[TMP28]], align 83253// CHECK1-64-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 33254// CHECK1-64-NEXT: store i8* null, i8** [[TMP29]], align 83255// CHECK1-64-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 43256// CHECK1-64-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i16**3257// CHECK1-64-NEXT: store i16* [[VLA]], i16** [[TMP31]], align 83258// CHECK1-64-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 43259// CHECK1-64-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i16**3260// CHECK1-64-NEXT: store i16* [[VLA]], i16** [[TMP33]], align 83261// CHECK1-64-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 43262// CHECK1-64-NEXT: store i64 [[TMP8]], i64* [[TMP34]], align 83263// CHECK1-64-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 43264// CHECK1-64-NEXT: store i8* null, i8** [[TMP35]], align 83265// CHECK1-64-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 03266// CHECK1-64-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 03267// CHECK1-64-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 03268// CHECK1-64-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 83269// CHECK1-64-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 03270// CHECK1-64-NEXT: store i32 2, i32* [[TMP39]], align 43271// CHECK1-64-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 13272// CHECK1-64-NEXT: store i32 5, i32* [[TMP40]], align 43273// CHECK1-64-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 23274// CHECK1-64-NEXT: store i8** [[TMP36]], i8*** [[TMP41]], align 83275// CHECK1-64-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 33276// CHECK1-64-NEXT: store i8** [[TMP37]], i8*** [[TMP42]], align 83277// CHECK1-64-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 43278// CHECK1-64-NEXT: store i64* [[TMP38]], i64** [[TMP43]], align 83279// CHECK1-64-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 53280// CHECK1-64-NEXT: store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.6, i32 0, i32 0), i64** [[TMP44]], align 83281// CHECK1-64-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 63282// CHECK1-64-NEXT: store i8** null, i8*** [[TMP45]], align 83283// CHECK1-64-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 73284// CHECK1-64-NEXT: store i8** null, i8*** [[TMP46]], align 83285// CHECK1-64-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 83286// CHECK1-64-NEXT: store i64 0, i64* [[TMP47]], align 83287// CHECK1-64-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 93288// CHECK1-64-NEXT: store i64 0, i64* [[TMP48]], align 83289// CHECK1-64-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 103290// CHECK1-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP49]], align 43291// CHECK1-64-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 113292// CHECK1-64-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP50]], align 43293// CHECK1-64-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 123294// CHECK1-64-NEXT: store i32 0, i32* [[TMP51]], align 43295// CHECK1-64-NEXT: [[TMP52:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])3296// CHECK1-64-NEXT: [[TMP53:%.*]] = icmp ne i32 [[TMP52]], 03297// CHECK1-64-NEXT: br i1 [[TMP53]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]3298// CHECK1-64: omp_offload.failed:3299// CHECK1-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]]3300// CHECK1-64-NEXT: br label [[OMP_OFFLOAD_CONT]]3301// CHECK1-64: omp_offload.cont:3302// CHECK1-64-NEXT: [[TMP54:%.*]] = mul nsw i64 1, [[TMP2]]3303// CHECK1-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP54]]3304// CHECK1-64-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 13305// CHECK1-64-NEXT: [[TMP55:%.*]] = load i16, i16* [[ARRAYIDX2]], align 23306// CHECK1-64-NEXT: [[CONV3:%.*]] = sext i16 [[TMP55]] to i323307// CHECK1-64-NEXT: [[TMP56:%.*]] = load i32, i32* [[B]], align 43308// CHECK1-64-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP56]]3309// CHECK1-64-NEXT: [[TMP57:%.*]] = load i8*, i8** [[SAVED_STACK]], align 83310// CHECK1-64-NEXT: call void @llvm.stackrestore(i8* [[TMP57]])3311// CHECK1-64-NEXT: ret i32 [[ADD4]]3312// CHECK1-64-LABEL: define {{[^@]+}}@_ZL7fstatici3313// CHECK1-64-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {3314// CHECK1-64-NEXT: entry:3315// CHECK1-64-NEXT: [[N_ADDR:%.*]] = alloca i32, align 43316// CHECK1-64-NEXT: [[A:%.*]] = alloca i32, align 43317// CHECK1-64-NEXT: [[AAA:%.*]] = alloca i8, align 13318// CHECK1-64-NEXT: [[B:%.*]] = alloca [10 x i32], align 43319// CHECK1-64-NEXT: [[A_CASTED:%.*]] = alloca i64, align 83320// CHECK1-64-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 83321// CHECK1-64-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 83322// CHECK1-64-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 83323// CHECK1-64-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 83324// CHECK1-64-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 43325// CHECK1-64-NEXT: store i32 0, i32* [[A]], align 43326// CHECK1-64-NEXT: store i8 0, i8* [[AAA]], align 13327// CHECK1-64-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 43328// CHECK1-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*3329// CHECK1-64-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 43330// CHECK1-64-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 83331// CHECK1-64-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 13332// CHECK1-64-NEXT: [[CONV1:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*3333// CHECK1-64-NEXT: store i8 [[TMP2]], i8* [[CONV1]], align 13334// CHECK1-64-NEXT: [[TMP3:%.*]] = load i64, i64* [[AAA_CASTED]], align 83335// CHECK1-64-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 03336// CHECK1-64-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*3337// CHECK1-64-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 83338// CHECK1-64-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 03339// CHECK1-64-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64*3340// CHECK1-64-NEXT: store i64 [[TMP1]], i64* [[TMP7]], align 83341// CHECK1-64-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 03342// CHECK1-64-NEXT: store i8* null, i8** [[TMP8]], align 83343// CHECK1-64-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 13344// CHECK1-64-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*3345// CHECK1-64-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 83346// CHECK1-64-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 13347// CHECK1-64-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64*3348// CHECK1-64-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 83349// CHECK1-64-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 13350// CHECK1-64-NEXT: store i8* null, i8** [[TMP13]], align 83351// CHECK1-64-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 23352// CHECK1-64-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [10 x i32]**3353// CHECK1-64-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP15]], align 83354// CHECK1-64-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 23355// CHECK1-64-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [10 x i32]**3356// CHECK1-64-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP17]], align 83357// CHECK1-64-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 23358// CHECK1-64-NEXT: store i8* null, i8** [[TMP18]], align 83359// CHECK1-64-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 03360// CHECK1-64-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 03361// CHECK1-64-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 83362// CHECK1-64-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 03363// CHECK1-64-NEXT: store i32 2, i32* [[TMP21]], align 43364// CHECK1-64-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 13365// CHECK1-64-NEXT: store i32 3, i32* [[TMP22]], align 43366// CHECK1-64-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 23367// CHECK1-64-NEXT: store i8** [[TMP19]], i8*** [[TMP23]], align 83368// CHECK1-64-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 33369// CHECK1-64-NEXT: store i8** [[TMP20]], i8*** [[TMP24]], align 83370// CHECK1-64-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 43371// CHECK1-64-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.7, i32 0, i32 0), i64** [[TMP25]], align 83372// CHECK1-64-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 53373// CHECK1-64-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.8, i32 0, i32 0), i64** [[TMP26]], align 83374// CHECK1-64-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 63375// CHECK1-64-NEXT: store i8** null, i8*** [[TMP27]], align 83376// CHECK1-64-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 73377// CHECK1-64-NEXT: store i8** null, i8*** [[TMP28]], align 83378// CHECK1-64-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 83379// CHECK1-64-NEXT: store i64 0, i64* [[TMP29]], align 83380// CHECK1-64-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 93381// CHECK1-64-NEXT: store i64 0, i64* [[TMP30]], align 83382// CHECK1-64-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 103383// CHECK1-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP31]], align 43384// CHECK1-64-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 113385// CHECK1-64-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP32]], align 43386// CHECK1-64-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 123387// CHECK1-64-NEXT: store i32 0, i32* [[TMP33]], align 43388// CHECK1-64-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])3389// CHECK1-64-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 03390// CHECK1-64-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]3391// CHECK1-64: omp_offload.failed:3392// CHECK1-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]3393// CHECK1-64-NEXT: br label [[OMP_OFFLOAD_CONT]]3394// CHECK1-64: omp_offload.cont:3395// CHECK1-64-NEXT: [[TMP36:%.*]] = load i32, i32* [[A]], align 43396// CHECK1-64-NEXT: ret i32 [[TMP36]]3397// CHECK1-64-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i3398// CHECK1-64-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {3399// CHECK1-64-NEXT: entry:3400// CHECK1-64-NEXT: [[N_ADDR:%.*]] = alloca i32, align 43401// CHECK1-64-NEXT: [[A:%.*]] = alloca i32, align 43402// CHECK1-64-NEXT: [[B:%.*]] = alloca [10 x i32], align 43403// CHECK1-64-NEXT: [[A_CASTED:%.*]] = alloca i64, align 83404// CHECK1-64-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 83405// CHECK1-64-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 83406// CHECK1-64-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 83407// CHECK1-64-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 43408// CHECK1-64-NEXT: store i32 0, i32* [[A]], align 43409// CHECK1-64-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 43410// CHECK1-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*3411// CHECK1-64-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 43412// CHECK1-64-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 83413// CHECK1-64-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 03414// CHECK1-64-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64*3415// CHECK1-64-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 83416// CHECK1-64-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 03417// CHECK1-64-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*3418// CHECK1-64-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 83419// CHECK1-64-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 03420// CHECK1-64-NEXT: store i8* null, i8** [[TMP6]], align 83421// CHECK1-64-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 13422// CHECK1-64-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [10 x i32]**3423// CHECK1-64-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP8]], align 83424// CHECK1-64-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 13425// CHECK1-64-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]**3426// CHECK1-64-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP10]], align 83427// CHECK1-64-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 13428// CHECK1-64-NEXT: store i8* null, i8** [[TMP11]], align 83429// CHECK1-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 03430// CHECK1-64-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 03431// CHECK1-64-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 83432// CHECK1-64-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 03433// CHECK1-64-NEXT: store i32 2, i32* [[TMP14]], align 43434// CHECK1-64-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 13435// CHECK1-64-NEXT: store i32 2, i32* [[TMP15]], align 43436// CHECK1-64-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 23437// CHECK1-64-NEXT: store i8** [[TMP12]], i8*** [[TMP16]], align 83438// CHECK1-64-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 33439// CHECK1-64-NEXT: store i8** [[TMP13]], i8*** [[TMP17]], align 83440// CHECK1-64-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 43441// CHECK1-64-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.9, i32 0, i32 0), i64** [[TMP18]], align 83442// CHECK1-64-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 53443// CHECK1-64-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.10, i32 0, i32 0), i64** [[TMP19]], align 83444// CHECK1-64-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 63445// CHECK1-64-NEXT: store i8** null, i8*** [[TMP20]], align 83446// CHECK1-64-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 73447// CHECK1-64-NEXT: store i8** null, i8*** [[TMP21]], align 83448// CHECK1-64-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 83449// CHECK1-64-NEXT: store i64 0, i64* [[TMP22]], align 83450// CHECK1-64-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 93451// CHECK1-64-NEXT: store i64 0, i64* [[TMP23]], align 83452// CHECK1-64-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 103453// CHECK1-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP24]], align 43454// CHECK1-64-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 113455// CHECK1-64-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP25]], align 43456// CHECK1-64-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 123457// CHECK1-64-NEXT: store i32 0, i32* [[TMP26]], align 43458// CHECK1-64-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])3459// CHECK1-64-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 03460// CHECK1-64-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]3461// CHECK1-64: omp_offload.failed:3462// CHECK1-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128(i64 [[TMP1]], [10 x i32]* [[B]]) #[[ATTR3]]3463// CHECK1-64-NEXT: br label [[OMP_OFFLOAD_CONT]]3464// CHECK1-64: omp_offload.cont:3465// CHECK1-64-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 43466// CHECK1-64-NEXT: ret i32 [[TMP29]]3467// CHECK1-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l1673468// CHECK1-64-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {3469// CHECK1-64-NEXT: entry:3470// CHECK1-64-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 83471// CHECK1-64-NEXT: [[B_ADDR:%.*]] = alloca i64, align 83472// CHECK1-64-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 83473// CHECK1-64-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 83474// CHECK1-64-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 83475// CHECK1-64-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 83476// CHECK1-64-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 83477// CHECK1-64-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 83478// CHECK1-64-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 83479// CHECK1-64-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 83480// CHECK1-64-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 83481// CHECK1-64-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 83482// CHECK1-64-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 83483// CHECK1-64-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 83484// CHECK1-64-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*3485// CHECK1-64-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 83486// CHECK1-64-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 83487// CHECK1-64-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 83488// CHECK1-64-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave()3489// CHECK1-64-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 83490// CHECK1-64-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]]3491// CHECK1-64-NEXT: [[VLA3:%.*]] = alloca i16, i64 [[TMP5]], align 23492// CHECK1-64-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 83493// CHECK1-64-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR1]], align 83494// CHECK1-64-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]]3495// CHECK1-64-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], 23496// CHECK1-64-NEXT: [[TMP8:%.*]] = bitcast i16* [[VLA3]] to i8*3497// CHECK1-64-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP3]] to i8*3498// CHECK1-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 2 [[TMP8]], i8* align 2 [[TMP9]], i64 [[TMP7]], i1 false)3499// CHECK1-64-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 43500// CHECK1-64-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP10]] to double3501// CHECK1-64-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+003502// CHECK1-64-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 03503// CHECK1-64-NEXT: store double [[ADD]], double* [[A]], align 83504// CHECK1-64-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 03505// CHECK1-64-NEXT: [[TMP11:%.*]] = load double, double* [[A5]], align 83506// CHECK1-64-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+003507// CHECK1-64-NEXT: store double [[INC]], double* [[A5]], align 83508// CHECK1-64-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i163509// CHECK1-64-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP2]]3510// CHECK1-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA3]], i64 [[TMP12]]3511// CHECK1-64-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 13512// CHECK1-64-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 23513// CHECK1-64-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 83514// CHECK1-64-NEXT: call void @llvm.stackrestore(i8* [[TMP13]])3515// CHECK1-64-NEXT: ret void3516// CHECK1-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l1423517// CHECK1-64-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {3518// CHECK1-64-NEXT: entry:3519// CHECK1-64-NEXT: [[A_ADDR:%.*]] = alloca i64, align 83520// CHECK1-64-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 83521// CHECK1-64-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 83522// CHECK1-64-NEXT: [[B2:%.*]] = alloca [10 x i32], align 43523// CHECK1-64-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 83524// CHECK1-64-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 83525// CHECK1-64-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 83526// CHECK1-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*3527// CHECK1-64-NEXT: [[CONV1:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*3528// CHECK1-64-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 83529// CHECK1-64-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B2]] to i8*3530// CHECK1-64-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*3531// CHECK1-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 40, i1 false)3532// CHECK1-64-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 43533// CHECK1-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 13534// CHECK1-64-NEXT: store i32 [[ADD]], i32* [[CONV]], align 43535// CHECK1-64-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 13536// CHECK1-64-NEXT: [[CONV3:%.*]] = sext i8 [[TMP4]] to i323537// CHECK1-64-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 13538// CHECK1-64-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i83539// CHECK1-64-NEXT: store i8 [[CONV5]], i8* [[CONV1]], align 13540// CHECK1-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B2]], i64 0, i64 23541// CHECK1-64-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 43542// CHECK1-64-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP5]], 13543// CHECK1-64-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 43544// CHECK1-64-NEXT: ret void3545// CHECK1-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l1283546// CHECK1-64-SAME: (i64 noundef [[A:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {3547// CHECK1-64-NEXT: entry:3548// CHECK1-64-NEXT: [[A_ADDR:%.*]] = alloca i64, align 83549// CHECK1-64-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 83550// CHECK1-64-NEXT: [[B1:%.*]] = alloca [10 x i32], align 43551// CHECK1-64-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 83552// CHECK1-64-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 83553// CHECK1-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*3554// CHECK1-64-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 83555// CHECK1-64-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8*3556// CHECK1-64-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*3557// CHECK1-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 40, i1 false)3558// CHECK1-64-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 43559// CHECK1-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 13560// CHECK1-64-NEXT: store i32 [[ADD]], i32* [[CONV]], align 43561// CHECK1-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i64 0, i64 23562// CHECK1-64-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 43563// CHECK1-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], 13564// CHECK1-64-NEXT: store i32 [[ADD2]], i32* [[ARRAYIDX]], align 43565// CHECK1-64-NEXT: ret void3566// CHECK1-64-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg3567// CHECK1-64-SAME: () #[[ATTR5:[0-9]+]] {3568// CHECK1-64-NEXT: entry:3569// CHECK1-64-NEXT: call void @__tgt_register_requires(i64 1)3570// CHECK1-64-NEXT: ret void3571// CHECK2-32-LABEL: define {{[^@]+}}@_Z3fooiPd3572// CHECK2-32-SAME: (i32 noundef [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {3573// CHECK2-32-NEXT: entry:3574// CHECK2-32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 43575// CHECK2-32-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 43576// CHECK2-32-NEXT: [[A:%.*]] = alloca i32, align 43577// CHECK2-32-NEXT: [[AA:%.*]] = alloca i16, align 23578// CHECK2-32-NEXT: [[B:%.*]] = alloca [10 x float], align 43579// CHECK2-32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 43580// CHECK2-32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 43581// CHECK2-32-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 83582// CHECK2-32-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 43583// CHECK2-32-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 43584// CHECK2-32-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 43585// CHECK2-32-NEXT: [[P:%.*]] = alloca i32*, align 643586// CHECK2-32-NEXT: [[A_CASTED:%.*]] = alloca i32, align 43587// CHECK2-32-NEXT: [[GA_CASTED:%.*]] = alloca i32, align 43588// CHECK2-32-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 43589// CHECK2-32-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 43590// CHECK2-32-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 43591// CHECK2-32-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 43592// CHECK2-32-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [9 x i8*], align 43593// CHECK2-32-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [9 x i8*], align 43594// CHECK2-32-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [9 x i8*], align 43595// CHECK2-32-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 43596// CHECK2-32-NEXT: [[DOTOFFLOAD_BASEPTRS8:%.*]] = alloca [2 x i8*], align 43597// CHECK2-32-NEXT: [[DOTOFFLOAD_PTRS9:%.*]] = alloca [2 x i8*], align 43598// CHECK2-32-NEXT: [[DOTOFFLOAD_MAPPERS10:%.*]] = alloca [2 x i8*], align 43599// CHECK2-32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 43600// CHECK2-32-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 43601// CHECK2-32-NEXT: store i32 0, i32* [[A]], align 43602// CHECK2-32-NEXT: store i16 0, i16* [[AA]], align 23603// CHECK2-32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 43604// CHECK2-32-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave()3605// CHECK2-32-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 43606// CHECK2-32-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 43607// CHECK2-32-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 43608// CHECK2-32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 43609// CHECK2-32-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]3610// CHECK2-32-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 83611// CHECK2-32-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 43612// CHECK2-32-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 03613// CHECK2-32-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 43614// CHECK2-32-NEXT: store i32 [[TMP4]], i32* [[X]], align 43615// CHECK2-32-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 13616// CHECK2-32-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 43617// CHECK2-32-NEXT: store i32 [[TMP5]], i32* [[Y]], align 43618// CHECK2-32-NEXT: store i32* [[A]], i32** [[P]], align 643619// CHECK2-32-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 43620// CHECK2-32-NEXT: store i32 [[TMP6]], i32* [[A_CASTED]], align 43621// CHECK2-32-NEXT: [[TMP7:%.*]] = load i32, i32* [[A_CASTED]], align 43622// CHECK2-32-NEXT: [[TMP8:%.*]] = load i32*, i32** [[P]], align 643623// CHECK2-32-NEXT: [[TMP9:%.*]] = load i32, i32* @ga, align 43624// CHECK2-32-NEXT: store i32 [[TMP9]], i32* [[GA_CASTED]], align 43625// CHECK2-32-NEXT: [[TMP10:%.*]] = load i32, i32* [[GA_CASTED]], align 43626// CHECK2-32-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 03627// CHECK2-32-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32*3628// CHECK2-32-NEXT: store i32 [[TMP7]], i32* [[TMP12]], align 43629// CHECK2-32-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 03630// CHECK2-32-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32*3631// CHECK2-32-NEXT: store i32 [[TMP7]], i32* [[TMP14]], align 43632// CHECK2-32-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 03633// CHECK2-32-NEXT: store i8* null, i8** [[TMP15]], align 43634// CHECK2-32-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 13635// CHECK2-32-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32**3636// CHECK2-32-NEXT: store i32* [[TMP8]], i32** [[TMP17]], align 43637// CHECK2-32-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 13638// CHECK2-32-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32**3639// CHECK2-32-NEXT: store i32* [[TMP8]], i32** [[TMP19]], align 43640// CHECK2-32-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 13641// CHECK2-32-NEXT: store i8* null, i8** [[TMP20]], align 43642// CHECK2-32-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 23643// CHECK2-32-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32*3644// CHECK2-32-NEXT: store i32 [[TMP10]], i32* [[TMP22]], align 43645// CHECK2-32-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 23646// CHECK2-32-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32*3647// CHECK2-32-NEXT: store i32 [[TMP10]], i32* [[TMP24]], align 43648// CHECK2-32-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 23649// CHECK2-32-NEXT: store i8* null, i8** [[TMP25]], align 43650// CHECK2-32-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 03651// CHECK2-32-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 03652// CHECK2-32-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 83653// CHECK2-32-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 03654// CHECK2-32-NEXT: store i32 2, i32* [[TMP28]], align 43655// CHECK2-32-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 13656// CHECK2-32-NEXT: store i32 3, i32* [[TMP29]], align 43657// CHECK2-32-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 23658// CHECK2-32-NEXT: store i8** [[TMP26]], i8*** [[TMP30]], align 43659// CHECK2-32-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 33660// CHECK2-32-NEXT: store i8** [[TMP27]], i8*** [[TMP31]], align 43661// CHECK2-32-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 43662// CHECK2-32-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP32]], align 43663// CHECK2-32-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 53664// CHECK2-32-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP33]], align 43665// CHECK2-32-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 63666// CHECK2-32-NEXT: store i8** null, i8*** [[TMP34]], align 43667// CHECK2-32-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 73668// CHECK2-32-NEXT: store i8** null, i8*** [[TMP35]], align 43669// CHECK2-32-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 83670// CHECK2-32-NEXT: store i64 0, i64* [[TMP36]], align 83671// CHECK2-32-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 93672// CHECK2-32-NEXT: store i64 0, i64* [[TMP37]], align 83673// CHECK2-32-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 103674// CHECK2-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP38]], align 43675// CHECK2-32-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 113676// CHECK2-32-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP39]], align 43677// CHECK2-32-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 123678// CHECK2-32-NEXT: store i32 0, i32* [[TMP40]], align 43679// CHECK2-32-NEXT: [[TMP41:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])3680// CHECK2-32-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 03681// CHECK2-32-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]3682// CHECK2-32: omp_offload.failed:3683// CHECK2-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63(i32 [[TMP7]], i32* [[TMP8]], i32 [[TMP10]]) #[[ATTR3:[0-9]+]]3684// CHECK2-32-NEXT: br label [[OMP_OFFLOAD_CONT]]3685// CHECK2-32: omp_offload.cont:3686// CHECK2-32-NEXT: [[TMP43:%.*]] = load i16, i16* [[AA]], align 23687// CHECK2-32-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*3688// CHECK2-32-NEXT: store i16 [[TMP43]], i16* [[CONV]], align 23689// CHECK2-32-NEXT: [[TMP44:%.*]] = load i32, i32* [[AA_CASTED]], align 43690// CHECK2-32-NEXT: [[TMP45:%.*]] = mul nuw i32 [[TMP0]], 43691// CHECK2-32-NEXT: [[TMP46:%.*]] = sext i32 [[TMP45]] to i643692// CHECK2-32-NEXT: [[TMP47:%.*]] = mul nuw i32 5, [[TMP2]]3693// CHECK2-32-NEXT: [[TMP48:%.*]] = mul nuw i32 [[TMP47]], 83694// CHECK2-32-NEXT: [[TMP49:%.*]] = sext i32 [[TMP48]] to i643695// CHECK2-32-NEXT: [[TMP50:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8*3696// CHECK2-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 bitcast ([9 x i64]* @.offload_sizes.1 to i8*), i32 72, i1 false)3697// CHECK2-32-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 03698// CHECK2-32-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32*3699// CHECK2-32-NEXT: store i32 [[TMP44]], i32* [[TMP52]], align 43700// CHECK2-32-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 03701// CHECK2-32-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to i32*3702// CHECK2-32-NEXT: store i32 [[TMP44]], i32* [[TMP54]], align 43703// CHECK2-32-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 03704// CHECK2-32-NEXT: store i8* null, i8** [[TMP55]], align 43705// CHECK2-32-NEXT: [[TMP56:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 13706// CHECK2-32-NEXT: [[TMP57:%.*]] = bitcast i8** [[TMP56]] to [10 x float]**3707// CHECK2-32-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP57]], align 43708// CHECK2-32-NEXT: [[TMP58:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 13709// CHECK2-32-NEXT: [[TMP59:%.*]] = bitcast i8** [[TMP58]] to [10 x float]**3710// CHECK2-32-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP59]], align 43711// CHECK2-32-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 13712// CHECK2-32-NEXT: store i8* null, i8** [[TMP60]], align 43713// CHECK2-32-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 23714// CHECK2-32-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32*3715// CHECK2-32-NEXT: store i32 [[TMP0]], i32* [[TMP62]], align 43716// CHECK2-32-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 23717// CHECK2-32-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i32*3718// CHECK2-32-NEXT: store i32 [[TMP0]], i32* [[TMP64]], align 43719// CHECK2-32-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 23720// CHECK2-32-NEXT: store i8* null, i8** [[TMP65]], align 43721// CHECK2-32-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 33722// CHECK2-32-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to float**3723// CHECK2-32-NEXT: store float* [[VLA]], float** [[TMP67]], align 43724// CHECK2-32-NEXT: [[TMP68:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 33725// CHECK2-32-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to float**3726// CHECK2-32-NEXT: store float* [[VLA]], float** [[TMP69]], align 43727// CHECK2-32-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 33728// CHECK2-32-NEXT: store i64 [[TMP46]], i64* [[TMP70]], align 43729// CHECK2-32-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 33730// CHECK2-32-NEXT: store i8* null, i8** [[TMP71]], align 43731// CHECK2-32-NEXT: [[TMP72:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 43732// CHECK2-32-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to [5 x [10 x double]]**3733// CHECK2-32-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP73]], align 43734// CHECK2-32-NEXT: [[TMP74:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 43735// CHECK2-32-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to [5 x [10 x double]]**3736// CHECK2-32-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP75]], align 43737// CHECK2-32-NEXT: [[TMP76:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 43738// CHECK2-32-NEXT: store i8* null, i8** [[TMP76]], align 43739// CHECK2-32-NEXT: [[TMP77:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 53740// CHECK2-32-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i32*3741// CHECK2-32-NEXT: store i32 5, i32* [[TMP78]], align 43742// CHECK2-32-NEXT: [[TMP79:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 53743// CHECK2-32-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i32*3744// CHECK2-32-NEXT: store i32 5, i32* [[TMP80]], align 43745// CHECK2-32-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 53746// CHECK2-32-NEXT: store i8* null, i8** [[TMP81]], align 43747// CHECK2-32-NEXT: [[TMP82:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 63748// CHECK2-32-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i32*3749// CHECK2-32-NEXT: store i32 [[TMP2]], i32* [[TMP83]], align 43750// CHECK2-32-NEXT: [[TMP84:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 63751// CHECK2-32-NEXT: [[TMP85:%.*]] = bitcast i8** [[TMP84]] to i32*3752// CHECK2-32-NEXT: store i32 [[TMP2]], i32* [[TMP85]], align 43753// CHECK2-32-NEXT: [[TMP86:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 63754// CHECK2-32-NEXT: store i8* null, i8** [[TMP86]], align 43755// CHECK2-32-NEXT: [[TMP87:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 73756// CHECK2-32-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to double**3757// CHECK2-32-NEXT: store double* [[VLA1]], double** [[TMP88]], align 43758// CHECK2-32-NEXT: [[TMP89:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 73759// CHECK2-32-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to double**3760// CHECK2-32-NEXT: store double* [[VLA1]], double** [[TMP90]], align 43761// CHECK2-32-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 73762// CHECK2-32-NEXT: store i64 [[TMP49]], i64* [[TMP91]], align 43763// CHECK2-32-NEXT: [[TMP92:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 73764// CHECK2-32-NEXT: store i8* null, i8** [[TMP92]], align 43765// CHECK2-32-NEXT: [[TMP93:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 83766// CHECK2-32-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to %struct.TT**3767// CHECK2-32-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP94]], align 43768// CHECK2-32-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 83769// CHECK2-32-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to %struct.TT**3770// CHECK2-32-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP96]], align 43771// CHECK2-32-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 83772// CHECK2-32-NEXT: store i8* null, i8** [[TMP97]], align 43773// CHECK2-32-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 03774// CHECK2-32-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 03775// CHECK2-32-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 03776// CHECK2-32-NEXT: [[KERNEL_ARGS5:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 83777// CHECK2-32-NEXT: [[TMP101:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 03778// CHECK2-32-NEXT: store i32 2, i32* [[TMP101]], align 43779// CHECK2-32-NEXT: [[TMP102:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 13780// CHECK2-32-NEXT: store i32 9, i32* [[TMP102]], align 43781// CHECK2-32-NEXT: [[TMP103:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 23782// CHECK2-32-NEXT: store i8** [[TMP98]], i8*** [[TMP103]], align 43783// CHECK2-32-NEXT: [[TMP104:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 33784// CHECK2-32-NEXT: store i8** [[TMP99]], i8*** [[TMP104]], align 43785// CHECK2-32-NEXT: [[TMP105:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 43786// CHECK2-32-NEXT: store i64* [[TMP100]], i64** [[TMP105]], align 43787// CHECK2-32-NEXT: [[TMP106:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 53788// CHECK2-32-NEXT: store i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.2, i32 0, i32 0), i64** [[TMP106]], align 43789// CHECK2-32-NEXT: [[TMP107:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 63790// CHECK2-32-NEXT: store i8** null, i8*** [[TMP107]], align 43791// CHECK2-32-NEXT: [[TMP108:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 73792// CHECK2-32-NEXT: store i8** null, i8*** [[TMP108]], align 43793// CHECK2-32-NEXT: [[TMP109:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 83794// CHECK2-32-NEXT: store i64 0, i64* [[TMP109]], align 83795// CHECK2-32-NEXT: [[TMP110:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 93796// CHECK2-32-NEXT: store i64 0, i64* [[TMP110]], align 83797// CHECK2-32-NEXT: [[TMP111:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 103798// CHECK2-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP111]], align 43799// CHECK2-32-NEXT: [[TMP112:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 113800// CHECK2-32-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP112]], align 43801// CHECK2-32-NEXT: [[TMP113:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 123802// CHECK2-32-NEXT: store i32 0, i32* [[TMP113]], align 43803// CHECK2-32-NEXT: [[TMP114:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]])3804// CHECK2-32-NEXT: [[TMP115:%.*]] = icmp ne i32 [[TMP114]], 03805// CHECK2-32-NEXT: br i1 [[TMP115]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]]3806// CHECK2-32: omp_offload.failed6:3807// CHECK2-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70(i32 [[TMP44]], [10 x float]* [[B]], i32 [[TMP0]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP2]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]3808// CHECK2-32-NEXT: br label [[OMP_OFFLOAD_CONT7]]3809// CHECK2-32: omp_offload.cont7:3810// CHECK2-32-NEXT: [[TMP116:%.*]] = load double*, double** [[PTR_ADDR]], align 43811// CHECK2-32-NEXT: [[TMP117:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 03812// CHECK2-32-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to double**3813// CHECK2-32-NEXT: store double* [[TMP116]], double** [[TMP118]], align 43814// CHECK2-32-NEXT: [[TMP119:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 03815// CHECK2-32-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to double**3816// CHECK2-32-NEXT: store double* [[TMP116]], double** [[TMP120]], align 43817// CHECK2-32-NEXT: [[TMP121:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS10]], i32 0, i32 03818// CHECK2-32-NEXT: store i8* null, i8** [[TMP121]], align 43819// CHECK2-32-NEXT: [[TMP122:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 13820// CHECK2-32-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to %struct.TT.0**3821// CHECK2-32-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[TMP123]], align 43822// CHECK2-32-NEXT: [[TMP124:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 13823// CHECK2-32-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to %struct.TT.0**3824// CHECK2-32-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[TMP125]], align 43825// CHECK2-32-NEXT: [[TMP126:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS10]], i32 0, i32 13826// CHECK2-32-NEXT: store i8* null, i8** [[TMP126]], align 43827// CHECK2-32-NEXT: [[TMP127:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 03828// CHECK2-32-NEXT: [[TMP128:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 03829// CHECK2-32-NEXT: [[KERNEL_ARGS11:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 83830// CHECK2-32-NEXT: [[TMP129:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 03831// CHECK2-32-NEXT: store i32 2, i32* [[TMP129]], align 43832// CHECK2-32-NEXT: [[TMP130:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 13833// CHECK2-32-NEXT: store i32 2, i32* [[TMP130]], align 43834// CHECK2-32-NEXT: [[TMP131:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 23835// CHECK2-32-NEXT: store i8** [[TMP127]], i8*** [[TMP131]], align 43836// CHECK2-32-NEXT: [[TMP132:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 33837// CHECK2-32-NEXT: store i8** [[TMP128]], i8*** [[TMP132]], align 43838// CHECK2-32-NEXT: [[TMP133:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 43839// CHECK2-32-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.3, i32 0, i32 0), i64** [[TMP133]], align 43840// CHECK2-32-NEXT: [[TMP134:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 53841// CHECK2-32-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.4, i32 0, i32 0), i64** [[TMP134]], align 43842// CHECK2-32-NEXT: [[TMP135:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 63843// CHECK2-32-NEXT: store i8** null, i8*** [[TMP135]], align 43844// CHECK2-32-NEXT: [[TMP136:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 73845// CHECK2-32-NEXT: store i8** null, i8*** [[TMP136]], align 43846// CHECK2-32-NEXT: [[TMP137:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 83847// CHECK2-32-NEXT: store i64 0, i64* [[TMP137]], align 83848// CHECK2-32-NEXT: [[TMP138:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 93849// CHECK2-32-NEXT: store i64 0, i64* [[TMP138]], align 83850// CHECK2-32-NEXT: [[TMP139:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 103851// CHECK2-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP139]], align 43852// CHECK2-32-NEXT: [[TMP140:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 113853// CHECK2-32-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP140]], align 43854// CHECK2-32-NEXT: [[TMP141:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 123855// CHECK2-32-NEXT: store i32 0, i32* [[TMP141]], align 43856// CHECK2-32-NEXT: [[TMP142:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]])3857// CHECK2-32-NEXT: [[TMP143:%.*]] = icmp ne i32 [[TMP142]], 03858// CHECK2-32-NEXT: br i1 [[TMP143]], label [[OMP_OFFLOAD_FAILED12:%.*]], label [[OMP_OFFLOAD_CONT13:%.*]]3859// CHECK2-32: omp_offload.failed12:3860// CHECK2-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111(double* [[TMP116]], %struct.TT.0* [[E]]) #[[ATTR3]]3861// CHECK2-32-NEXT: br label [[OMP_OFFLOAD_CONT13]]3862// CHECK2-32: omp_offload.cont13:3863// CHECK2-32-NEXT: [[TMP144:%.*]] = load i32, i32* [[A]], align 43864// CHECK2-32-NEXT: [[TMP145:%.*]] = load i8*, i8** [[SAVED_STACK]], align 43865// CHECK2-32-NEXT: call void @llvm.stackrestore(i8* [[TMP145]])3866// CHECK2-32-NEXT: ret i32 [[TMP144]]3867// CHECK2-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l633868// CHECK2-32-SAME: (i32 noundef [[A:%.*]], i32* noundef [[P:%.*]], i32 noundef [[GA:%.*]]) #[[ATTR2:[0-9]+]] {3869// CHECK2-32-NEXT: entry:3870// CHECK2-32-NEXT: [[A_ADDR:%.*]] = alloca i32, align 43871// CHECK2-32-NEXT: [[P_ADDR:%.*]] = alloca i32*, align 43872// CHECK2-32-NEXT: [[GA_ADDR:%.*]] = alloca i32, align 43873// CHECK2-32-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 43874// CHECK2-32-NEXT: store i32* [[P]], i32** [[P_ADDR]], align 43875// CHECK2-32-NEXT: store i32 [[GA]], i32* [[GA_ADDR]], align 43876// CHECK2-32-NEXT: ret void3877// CHECK2-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l703878// CHECK2-32-SAME: (i32 noundef [[AA:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {3879// CHECK2-32-NEXT: entry:3880// CHECK2-32-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 43881// CHECK2-32-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 43882// CHECK2-32-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 43883// CHECK2-32-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 43884// CHECK2-32-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 43885// CHECK2-32-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 43886// CHECK2-32-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 43887// CHECK2-32-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 43888// CHECK2-32-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 43889// CHECK2-32-NEXT: [[B5:%.*]] = alloca [10 x float], align 43890// CHECK2-32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 43891// CHECK2-32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 43892// CHECK2-32-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 83893// CHECK2-32-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 43894// CHECK2-32-NEXT: [[__VLA_EXPR2:%.*]] = alloca i32, align 43895// CHECK2-32-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 43896// CHECK2-32-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 43897// CHECK2-32-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 43898// CHECK2-32-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 43899// CHECK2-32-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 43900// CHECK2-32-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 43901// CHECK2-32-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 43902// CHECK2-32-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 43903// CHECK2-32-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 43904// CHECK2-32-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 43905// CHECK2-32-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*3906// CHECK2-32-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 43907// CHECK2-32-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 43908// CHECK2-32-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 43909// CHECK2-32-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 43910// CHECK2-32-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 43911// CHECK2-32-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 43912// CHECK2-32-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 43913// CHECK2-32-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 43914// CHECK2-32-NEXT: [[TMP8:%.*]] = bitcast [10 x float]* [[B5]] to i8*3915// CHECK2-32-NEXT: [[TMP9:%.*]] = bitcast [10 x float]* [[TMP0]] to i8*3916// CHECK2-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i32 40, i1 false)3917// CHECK2-32-NEXT: [[TMP10:%.*]] = call i8* @llvm.stacksave()3918// CHECK2-32-NEXT: store i8* [[TMP10]], i8** [[SAVED_STACK]], align 43919// CHECK2-32-NEXT: [[VLA6:%.*]] = alloca float, i32 [[TMP1]], align 43920// CHECK2-32-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 43921// CHECK2-32-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP1]], 43922// CHECK2-32-NEXT: [[TMP12:%.*]] = bitcast float* [[VLA6]] to i8*3923// CHECK2-32-NEXT: [[TMP13:%.*]] = bitcast float* [[TMP2]] to i8*3924// CHECK2-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 [[TMP11]], i1 false)3925// CHECK2-32-NEXT: [[TMP14:%.*]] = bitcast [5 x [10 x double]]* [[C7]] to i8*3926// CHECK2-32-NEXT: [[TMP15:%.*]] = bitcast [5 x [10 x double]]* [[TMP3]] to i8*3927// CHECK2-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 [[TMP14]], i8* align 8 [[TMP15]], i32 400, i1 false)3928// CHECK2-32-NEXT: [[TMP16:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]]3929// CHECK2-32-NEXT: [[VLA8:%.*]] = alloca double, i32 [[TMP16]], align 83930// CHECK2-32-NEXT: store i32 [[TMP4]], i32* [[__VLA_EXPR1]], align 43931// CHECK2-32-NEXT: store i32 [[TMP5]], i32* [[__VLA_EXPR2]], align 43932// CHECK2-32-NEXT: [[TMP17:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]]3933// CHECK2-32-NEXT: [[TMP18:%.*]] = mul nuw i32 [[TMP17]], 83934// CHECK2-32-NEXT: [[TMP19:%.*]] = bitcast double* [[VLA8]] to i8*3935// CHECK2-32-NEXT: [[TMP20:%.*]] = bitcast double* [[TMP6]] to i8*3936// CHECK2-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 [[TMP19]], i8* align 8 [[TMP20]], i32 [[TMP18]], i1 false)3937// CHECK2-32-NEXT: [[TMP21:%.*]] = bitcast %struct.TT* [[D9]] to i8*3938// CHECK2-32-NEXT: [[TMP22:%.*]] = bitcast %struct.TT* [[TMP7]] to i8*3939// CHECK2-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP21]], i8* align 4 [[TMP22]], i32 12, i1 false)3940// CHECK2-32-NEXT: [[TMP23:%.*]] = load i16, i16* [[CONV]], align 23941// CHECK2-32-NEXT: [[CONV10:%.*]] = sext i16 [[TMP23]] to i323942// CHECK2-32-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV10]], 13943// CHECK2-32-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD]] to i163944// CHECK2-32-NEXT: store i16 [[CONV11]], i16* [[CONV]], align 23945// CHECK2-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], i32 0, i32 23946// CHECK2-32-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 43947// CHECK2-32-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA6]], i32 33948// CHECK2-32-NEXT: store float 1.000000e+00, float* [[ARRAYIDX12]], align 43949// CHECK2-32-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], i32 0, i32 13950// CHECK2-32-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i32 0, i32 23951// CHECK2-32-NEXT: store double 1.000000e+00, double* [[ARRAYIDX14]], align 83952// CHECK2-32-NEXT: [[TMP24:%.*]] = mul nsw i32 1, [[TMP5]]3953// CHECK2-32-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[VLA8]], i32 [[TMP24]]3954// CHECK2-32-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i32 33955// CHECK2-32-NEXT: store double 1.000000e+00, double* [[ARRAYIDX16]], align 83956// CHECK2-32-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 03957// CHECK2-32-NEXT: store i64 1, i64* [[X]], align 43958// CHECK2-32-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 13959// CHECK2-32-NEXT: store i8 1, i8* [[Y]], align 43960// CHECK2-32-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 43961// CHECK2-32-NEXT: call void @llvm.stackrestore(i8* [[TMP25]])3962// CHECK2-32-NEXT: ret void3963// CHECK2-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l1113964// CHECK2-32-SAME: (double* noundef [[PTR:%.*]], %struct.TT.0* noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR2]] {3965// CHECK2-32-NEXT: entry:3966// CHECK2-32-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 43967// CHECK2-32-NEXT: [[E_ADDR:%.*]] = alloca %struct.TT.0*, align 43968// CHECK2-32-NEXT: [[E1:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 43969// CHECK2-32-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 43970// CHECK2-32-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[E_ADDR]], align 43971// CHECK2-32-NEXT: [[TMP0:%.*]] = load %struct.TT.0*, %struct.TT.0** [[E_ADDR]], align 43972// CHECK2-32-NEXT: [[TMP1:%.*]] = bitcast %struct.TT.0* [[E1]] to i8*3973// CHECK2-32-NEXT: [[TMP2:%.*]] = bitcast %struct.TT.0* [[TMP0]] to i8*3974// CHECK2-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 8, i1 false)3975// CHECK2-32-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E1]], i32 0, i32 03976// CHECK2-32-NEXT: [[TMP3:%.*]] = load i32, i32* [[X]], align 43977// CHECK2-32-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP3]] to double3978// CHECK2-32-NEXT: [[TMP4:%.*]] = load double*, double** [[PTR_ADDR]], align 43979// CHECK2-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP4]], i32 03980// CHECK2-32-NEXT: store double [[CONV]], double* [[ARRAYIDX]], align 43981// CHECK2-32-NEXT: [[TMP5:%.*]] = load double*, double** [[PTR_ADDR]], align 43982// CHECK2-32-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, double* [[TMP5]], i32 03983// CHECK2-32-NEXT: [[TMP6:%.*]] = load double, double* [[ARRAYIDX2]], align 43984// CHECK2-32-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+003985// CHECK2-32-NEXT: store double [[INC]], double* [[ARRAYIDX2]], align 43986// CHECK2-32-NEXT: ret void3987// CHECK2-32-LABEL: define {{[^@]+}}@_Z3bariPd3988// CHECK2-32-SAME: (i32 noundef [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0]] {3989// CHECK2-32-NEXT: entry:3990// CHECK2-32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 43991// CHECK2-32-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 43992// CHECK2-32-NEXT: [[A:%.*]] = alloca i32, align 43993// CHECK2-32-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 43994// CHECK2-32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 43995// CHECK2-32-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 43996// CHECK2-32-NEXT: store i32 0, i32* [[A]], align 43997// CHECK2-32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 43998// CHECK2-32-NEXT: [[TMP1:%.*]] = load double*, double** [[PTR_ADDR]], align 43999// CHECK2-32-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooiPd(i32 noundef [[TMP0]], double* noundef [[TMP1]])4000// CHECK2-32-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 44001// CHECK2-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]]4002// CHECK2-32-NEXT: store i32 [[ADD]], i32* [[A]], align 44003// CHECK2-32-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 44004// CHECK2-32-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP3]])4005// CHECK2-32-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 44006// CHECK2-32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]]4007// CHECK2-32-NEXT: store i32 [[ADD2]], i32* [[A]], align 44008// CHECK2-32-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 44009// CHECK2-32-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP5]])4010// CHECK2-32-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 44011// CHECK2-32-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]]4012// CHECK2-32-NEXT: store i32 [[ADD4]], i32* [[A]], align 44013// CHECK2-32-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 44014// CHECK2-32-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP7]])4015// CHECK2-32-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 44016// CHECK2-32-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]]4017// CHECK2-32-NEXT: store i32 [[ADD6]], i32* [[A]], align 44018// CHECK2-32-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 44019// CHECK2-32-NEXT: ret i32 [[TMP9]]4020// CHECK2-32-LABEL: define {{[^@]+}}@_ZN2S12r1Ei4021// CHECK2-32-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {4022// CHECK2-32-NEXT: entry:4023// CHECK2-32-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 44024// CHECK2-32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 44025// CHECK2-32-NEXT: [[B:%.*]] = alloca i32, align 44026// CHECK2-32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 44027// CHECK2-32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 44028// CHECK2-32-NEXT: [[B_CASTED:%.*]] = alloca i32, align 44029// CHECK2-32-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 44030// CHECK2-32-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 44031// CHECK2-32-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 44032// CHECK2-32-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 44033// CHECK2-32-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 44034// CHECK2-32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 44035// CHECK2-32-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 44036// CHECK2-32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 44037// CHECK2-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 14038// CHECK2-32-NEXT: store i32 [[ADD]], i32* [[B]], align 44039// CHECK2-32-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 44040// CHECK2-32-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()4041// CHECK2-32-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 44042// CHECK2-32-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]4043// CHECK2-32-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 24044// CHECK2-32-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 44045// CHECK2-32-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 44046// CHECK2-32-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 44047// CHECK2-32-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 44048// CHECK2-32-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 04049// CHECK2-32-NEXT: [[TMP6:%.*]] = mul nuw i32 2, [[TMP1]]4050// CHECK2-32-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP6]], 24051// CHECK2-32-NEXT: [[TMP8:%.*]] = sext i32 [[TMP7]] to i644052// CHECK2-32-NEXT: [[TMP9:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8*4053// CHECK2-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.5 to i8*), i32 40, i1 false)4054// CHECK2-32-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 04055// CHECK2-32-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**4056// CHECK2-32-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 44057// CHECK2-32-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 04058// CHECK2-32-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**4059// CHECK2-32-NEXT: store double* [[A]], double** [[TMP13]], align 44060// CHECK2-32-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 04061// CHECK2-32-NEXT: store i8* null, i8** [[TMP14]], align 44062// CHECK2-32-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 14063// CHECK2-32-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32*4064// CHECK2-32-NEXT: store i32 [[TMP5]], i32* [[TMP16]], align 44065// CHECK2-32-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 14066// CHECK2-32-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*4067// CHECK2-32-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 44068// CHECK2-32-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 14069// CHECK2-32-NEXT: store i8* null, i8** [[TMP19]], align 44070// CHECK2-32-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 24071// CHECK2-32-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32*4072// CHECK2-32-NEXT: store i32 2, i32* [[TMP21]], align 44073// CHECK2-32-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 24074// CHECK2-32-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*4075// CHECK2-32-NEXT: store i32 2, i32* [[TMP23]], align 44076// CHECK2-32-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 24077// CHECK2-32-NEXT: store i8* null, i8** [[TMP24]], align 44078// CHECK2-32-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 34079// CHECK2-32-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32*4080// CHECK2-32-NEXT: store i32 [[TMP1]], i32* [[TMP26]], align 44081// CHECK2-32-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 34082// CHECK2-32-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32*4083// CHECK2-32-NEXT: store i32 [[TMP1]], i32* [[TMP28]], align 44084// CHECK2-32-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 34085// CHECK2-32-NEXT: store i8* null, i8** [[TMP29]], align 44086// CHECK2-32-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 44087// CHECK2-32-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i16**4088// CHECK2-32-NEXT: store i16* [[VLA]], i16** [[TMP31]], align 44089// CHECK2-32-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 44090// CHECK2-32-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i16**4091// CHECK2-32-NEXT: store i16* [[VLA]], i16** [[TMP33]], align 44092// CHECK2-32-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 44093// CHECK2-32-NEXT: store i64 [[TMP8]], i64* [[TMP34]], align 44094// CHECK2-32-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 44095// CHECK2-32-NEXT: store i8* null, i8** [[TMP35]], align 44096// CHECK2-32-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 04097// CHECK2-32-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 04098// CHECK2-32-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 04099// CHECK2-32-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 84100// CHECK2-32-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 04101// CHECK2-32-NEXT: store i32 2, i32* [[TMP39]], align 44102// CHECK2-32-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 14103// CHECK2-32-NEXT: store i32 5, i32* [[TMP40]], align 44104// CHECK2-32-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 24105// CHECK2-32-NEXT: store i8** [[TMP36]], i8*** [[TMP41]], align 44106// CHECK2-32-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 34107// CHECK2-32-NEXT: store i8** [[TMP37]], i8*** [[TMP42]], align 44108// CHECK2-32-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 44109// CHECK2-32-NEXT: store i64* [[TMP38]], i64** [[TMP43]], align 44110// CHECK2-32-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 54111// CHECK2-32-NEXT: store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.6, i32 0, i32 0), i64** [[TMP44]], align 44112// CHECK2-32-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 64113// CHECK2-32-NEXT: store i8** null, i8*** [[TMP45]], align 44114// CHECK2-32-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 74115// CHECK2-32-NEXT: store i8** null, i8*** [[TMP46]], align 44116// CHECK2-32-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 84117// CHECK2-32-NEXT: store i64 0, i64* [[TMP47]], align 84118// CHECK2-32-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 94119// CHECK2-32-NEXT: store i64 0, i64* [[TMP48]], align 84120// CHECK2-32-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 104121// CHECK2-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP49]], align 44122// CHECK2-32-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 114123// CHECK2-32-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP50]], align 44124// CHECK2-32-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 124125// CHECK2-32-NEXT: store i32 0, i32* [[TMP51]], align 44126// CHECK2-32-NEXT: [[TMP52:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])4127// CHECK2-32-NEXT: [[TMP53:%.*]] = icmp ne i32 [[TMP52]], 04128// CHECK2-32-NEXT: br i1 [[TMP53]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]4129// CHECK2-32: omp_offload.failed:4130// CHECK2-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]]4131// CHECK2-32-NEXT: br label [[OMP_OFFLOAD_CONT]]4132// CHECK2-32: omp_offload.cont:4133// CHECK2-32-NEXT: [[TMP54:%.*]] = mul nsw i32 1, [[TMP1]]4134// CHECK2-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP54]]4135// CHECK2-32-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 14136// CHECK2-32-NEXT: [[TMP55:%.*]] = load i16, i16* [[ARRAYIDX2]], align 24137// CHECK2-32-NEXT: [[CONV:%.*]] = sext i16 [[TMP55]] to i324138// CHECK2-32-NEXT: [[TMP56:%.*]] = load i32, i32* [[B]], align 44139// CHECK2-32-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP56]]4140// CHECK2-32-NEXT: [[TMP57:%.*]] = load i8*, i8** [[SAVED_STACK]], align 44141// CHECK2-32-NEXT: call void @llvm.stackrestore(i8* [[TMP57]])4142// CHECK2-32-NEXT: ret i32 [[ADD3]]4143// CHECK2-32-LABEL: define {{[^@]+}}@_ZL7fstatici4144// CHECK2-32-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {4145// CHECK2-32-NEXT: entry:4146// CHECK2-32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 44147// CHECK2-32-NEXT: [[A:%.*]] = alloca i32, align 44148// CHECK2-32-NEXT: [[AAA:%.*]] = alloca i8, align 14149// CHECK2-32-NEXT: [[B:%.*]] = alloca [10 x i32], align 44150// CHECK2-32-NEXT: [[A_CASTED:%.*]] = alloca i32, align 44151// CHECK2-32-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 44152// CHECK2-32-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 44153// CHECK2-32-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 44154// CHECK2-32-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 44155// CHECK2-32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 44156// CHECK2-32-NEXT: store i32 0, i32* [[A]], align 44157// CHECK2-32-NEXT: store i8 0, i8* [[AAA]], align 14158// CHECK2-32-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 44159// CHECK2-32-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 44160// CHECK2-32-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 44161// CHECK2-32-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 14162// CHECK2-32-NEXT: [[CONV:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*4163// CHECK2-32-NEXT: store i8 [[TMP2]], i8* [[CONV]], align 14164// CHECK2-32-NEXT: [[TMP3:%.*]] = load i32, i32* [[AAA_CASTED]], align 44165// CHECK2-32-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 04166// CHECK2-32-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32*4167// CHECK2-32-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 44168// CHECK2-32-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 04169// CHECK2-32-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32*4170// CHECK2-32-NEXT: store i32 [[TMP1]], i32* [[TMP7]], align 44171// CHECK2-32-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 04172// CHECK2-32-NEXT: store i8* null, i8** [[TMP8]], align 44173// CHECK2-32-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 14174// CHECK2-32-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*4175// CHECK2-32-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 44176// CHECK2-32-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 14177// CHECK2-32-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32*4178// CHECK2-32-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 44179// CHECK2-32-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 14180// CHECK2-32-NEXT: store i8* null, i8** [[TMP13]], align 44181// CHECK2-32-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 24182// CHECK2-32-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [10 x i32]**4183// CHECK2-32-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP15]], align 44184// CHECK2-32-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 24185// CHECK2-32-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [10 x i32]**4186// CHECK2-32-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP17]], align 44187// CHECK2-32-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 24188// CHECK2-32-NEXT: store i8* null, i8** [[TMP18]], align 44189// CHECK2-32-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 04190// CHECK2-32-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 04191// CHECK2-32-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 84192// CHECK2-32-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 04193// CHECK2-32-NEXT: store i32 2, i32* [[TMP21]], align 44194// CHECK2-32-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 14195// CHECK2-32-NEXT: store i32 3, i32* [[TMP22]], align 44196// CHECK2-32-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 24197// CHECK2-32-NEXT: store i8** [[TMP19]], i8*** [[TMP23]], align 44198// CHECK2-32-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 34199// CHECK2-32-NEXT: store i8** [[TMP20]], i8*** [[TMP24]], align 44200// CHECK2-32-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 44201// CHECK2-32-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.7, i32 0, i32 0), i64** [[TMP25]], align 44202// CHECK2-32-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 54203// CHECK2-32-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.8, i32 0, i32 0), i64** [[TMP26]], align 44204// CHECK2-32-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 64205// CHECK2-32-NEXT: store i8** null, i8*** [[TMP27]], align 44206// CHECK2-32-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 74207// CHECK2-32-NEXT: store i8** null, i8*** [[TMP28]], align 44208// CHECK2-32-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 84209// CHECK2-32-NEXT: store i64 0, i64* [[TMP29]], align 84210// CHECK2-32-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 94211// CHECK2-32-NEXT: store i64 0, i64* [[TMP30]], align 84212// CHECK2-32-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 104213// CHECK2-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP31]], align 44214// CHECK2-32-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 114215// CHECK2-32-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP32]], align 44216// CHECK2-32-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 124217// CHECK2-32-NEXT: store i32 0, i32* [[TMP33]], align 44218// CHECK2-32-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])4219// CHECK2-32-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 04220// CHECK2-32-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]4221// CHECK2-32: omp_offload.failed:4222// CHECK2-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]4223// CHECK2-32-NEXT: br label [[OMP_OFFLOAD_CONT]]4224// CHECK2-32: omp_offload.cont:4225// CHECK2-32-NEXT: [[TMP36:%.*]] = load i32, i32* [[A]], align 44226// CHECK2-32-NEXT: ret i32 [[TMP36]]4227// CHECK2-32-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i4228// CHECK2-32-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {4229// CHECK2-32-NEXT: entry:4230// CHECK2-32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 44231// CHECK2-32-NEXT: [[A:%.*]] = alloca i32, align 44232// CHECK2-32-NEXT: [[B:%.*]] = alloca [10 x i32], align 44233// CHECK2-32-NEXT: [[A_CASTED:%.*]] = alloca i32, align 44234// CHECK2-32-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 44235// CHECK2-32-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 44236// CHECK2-32-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 44237// CHECK2-32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 44238// CHECK2-32-NEXT: store i32 0, i32* [[A]], align 44239// CHECK2-32-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 44240// CHECK2-32-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 44241// CHECK2-32-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 44242// CHECK2-32-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 04243// CHECK2-32-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32*4244// CHECK2-32-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 44245// CHECK2-32-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 04246// CHECK2-32-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32*4247// CHECK2-32-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 44248// CHECK2-32-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 04249// CHECK2-32-NEXT: store i8* null, i8** [[TMP6]], align 44250// CHECK2-32-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 14251// CHECK2-32-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [10 x i32]**4252// CHECK2-32-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP8]], align 44253// CHECK2-32-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 14254// CHECK2-32-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]**4255// CHECK2-32-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP10]], align 44256// CHECK2-32-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 14257// CHECK2-32-NEXT: store i8* null, i8** [[TMP11]], align 44258// CHECK2-32-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 04259// CHECK2-32-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 04260// CHECK2-32-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 84261// CHECK2-32-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 04262// CHECK2-32-NEXT: store i32 2, i32* [[TMP14]], align 44263// CHECK2-32-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 14264// CHECK2-32-NEXT: store i32 2, i32* [[TMP15]], align 44265// CHECK2-32-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 24266// CHECK2-32-NEXT: store i8** [[TMP12]], i8*** [[TMP16]], align 44267// CHECK2-32-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 34268// CHECK2-32-NEXT: store i8** [[TMP13]], i8*** [[TMP17]], align 44269// CHECK2-32-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 44270// CHECK2-32-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.9, i32 0, i32 0), i64** [[TMP18]], align 44271// CHECK2-32-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 54272// CHECK2-32-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.10, i32 0, i32 0), i64** [[TMP19]], align 44273// CHECK2-32-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 64274// CHECK2-32-NEXT: store i8** null, i8*** [[TMP20]], align 44275// CHECK2-32-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 74276// CHECK2-32-NEXT: store i8** null, i8*** [[TMP21]], align 44277// CHECK2-32-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 84278// CHECK2-32-NEXT: store i64 0, i64* [[TMP22]], align 84279// CHECK2-32-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 94280// CHECK2-32-NEXT: store i64 0, i64* [[TMP23]], align 84281// CHECK2-32-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 104282// CHECK2-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP24]], align 44283// CHECK2-32-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 114284// CHECK2-32-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP25]], align 44285// CHECK2-32-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 124286// CHECK2-32-NEXT: store i32 0, i32* [[TMP26]], align 44287// CHECK2-32-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])4288// CHECK2-32-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 04289// CHECK2-32-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]4290// CHECK2-32: omp_offload.failed:4291// CHECK2-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128(i32 [[TMP1]], [10 x i32]* [[B]]) #[[ATTR3]]4292// CHECK2-32-NEXT: br label [[OMP_OFFLOAD_CONT]]4293// CHECK2-32: omp_offload.cont:4294// CHECK2-32-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 44295// CHECK2-32-NEXT: ret i32 [[TMP29]]4296// CHECK2-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l1674297// CHECK2-32-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {4298// CHECK2-32-NEXT: entry:4299// CHECK2-32-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 44300// CHECK2-32-NEXT: [[B_ADDR:%.*]] = alloca i32, align 44301// CHECK2-32-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 44302// CHECK2-32-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 44303// CHECK2-32-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 44304// CHECK2-32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 44305// CHECK2-32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 44306// CHECK2-32-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 44307// CHECK2-32-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 44308// CHECK2-32-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 44309// CHECK2-32-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 44310// CHECK2-32-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 44311// CHECK2-32-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 44312// CHECK2-32-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 44313// CHECK2-32-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 44314// CHECK2-32-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 44315// CHECK2-32-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 44316// CHECK2-32-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave()4317// CHECK2-32-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 44318// CHECK2-32-NEXT: [[TMP5:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]4319// CHECK2-32-NEXT: [[VLA3:%.*]] = alloca i16, i32 [[TMP5]], align 24320// CHECK2-32-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 44321// CHECK2-32-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 44322// CHECK2-32-NEXT: [[TMP6:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]4323// CHECK2-32-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP6]], 24324// CHECK2-32-NEXT: [[TMP8:%.*]] = bitcast i16* [[VLA3]] to i8*4325// CHECK2-32-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP3]] to i8*4326// CHECK2-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 2 [[TMP8]], i8* align 2 [[TMP9]], i32 [[TMP7]], i1 false)4327// CHECK2-32-NEXT: [[TMP10:%.*]] = load i32, i32* [[B_ADDR]], align 44328// CHECK2-32-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP10]] to double4329// CHECK2-32-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+004330// CHECK2-32-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 04331// CHECK2-32-NEXT: store double [[ADD]], double* [[A]], align 44332// CHECK2-32-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 04333// CHECK2-32-NEXT: [[TMP11:%.*]] = load double, double* [[A4]], align 44334// CHECK2-32-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+004335// CHECK2-32-NEXT: store double [[INC]], double* [[A4]], align 44336// CHECK2-32-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i164337// CHECK2-32-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP2]]4338// CHECK2-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA3]], i32 [[TMP12]]4339// CHECK2-32-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 14340// CHECK2-32-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 24341// CHECK2-32-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 44342// CHECK2-32-NEXT: call void @llvm.stackrestore(i8* [[TMP13]])4343// CHECK2-32-NEXT: ret void4344// CHECK2-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l1424345// CHECK2-32-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {4346// CHECK2-32-NEXT: entry:4347// CHECK2-32-NEXT: [[A_ADDR:%.*]] = alloca i32, align 44348// CHECK2-32-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 44349// CHECK2-32-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 44350// CHECK2-32-NEXT: [[B1:%.*]] = alloca [10 x i32], align 44351// CHECK2-32-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 44352// CHECK2-32-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 44353// CHECK2-32-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 44354// CHECK2-32-NEXT: [[CONV:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*4355// CHECK2-32-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 44356// CHECK2-32-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8*4357// CHECK2-32-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*4358// CHECK2-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 40, i1 false)4359// CHECK2-32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 44360// CHECK2-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 14361// CHECK2-32-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 44362// CHECK2-32-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 14363// CHECK2-32-NEXT: [[CONV2:%.*]] = sext i8 [[TMP4]] to i324364// CHECK2-32-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 14365// CHECK2-32-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i84366// CHECK2-32-NEXT: store i8 [[CONV4]], i8* [[CONV]], align 14367// CHECK2-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i32 0, i32 24368// CHECK2-32-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 44369// CHECK2-32-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP5]], 14370// CHECK2-32-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 44371// CHECK2-32-NEXT: ret void4372// CHECK2-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l1284373// CHECK2-32-SAME: (i32 noundef [[A:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {4374// CHECK2-32-NEXT: entry:4375// CHECK2-32-NEXT: [[A_ADDR:%.*]] = alloca i32, align 44376// CHECK2-32-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 44377// CHECK2-32-NEXT: [[B1:%.*]] = alloca [10 x i32], align 44378// CHECK2-32-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 44379// CHECK2-32-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 44380// CHECK2-32-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 44381// CHECK2-32-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8*4382// CHECK2-32-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*4383// CHECK2-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 40, i1 false)4384// CHECK2-32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 44385// CHECK2-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 14386// CHECK2-32-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 44387// CHECK2-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i32 0, i32 24388// CHECK2-32-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 44389// CHECK2-32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], 14390// CHECK2-32-NEXT: store i32 [[ADD2]], i32* [[ARRAYIDX]], align 44391// CHECK2-32-NEXT: ret void4392// CHECK2-32-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg4393// CHECK2-32-SAME: () #[[ATTR5:[0-9]+]] {4394// CHECK2-32-NEXT: entry:4395// CHECK2-32-NEXT: call void @__tgt_register_requires(i64 1)4396// CHECK2-32-NEXT: ret void4397// CHECK3-32-LABEL: define {{[^@]+}}@_Z3fooiPd4398// CHECK3-32-SAME: (i32 noundef [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {4399// CHECK3-32-NEXT: entry:4400// CHECK3-32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 44401// CHECK3-32-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 44402// CHECK3-32-NEXT: [[A:%.*]] = alloca i32, align 44403// CHECK3-32-NEXT: [[AA:%.*]] = alloca i16, align 24404// CHECK3-32-NEXT: [[B:%.*]] = alloca [10 x float], align 44405// CHECK3-32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 44406// CHECK3-32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 44407// CHECK3-32-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 84408// CHECK3-32-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 44409// CHECK3-32-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 44410// CHECK3-32-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 44411// CHECK3-32-NEXT: [[P:%.*]] = alloca i32*, align 644412// CHECK3-32-NEXT: [[A_CASTED:%.*]] = alloca i32, align 44413// CHECK3-32-NEXT: [[GA_CASTED:%.*]] = alloca i32, align 44414// CHECK3-32-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 44415// CHECK3-32-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 44416// CHECK3-32-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 44417// CHECK3-32-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 44418// CHECK3-32-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [9 x i8*], align 44419// CHECK3-32-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [9 x i8*], align 44420// CHECK3-32-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [9 x i8*], align 44421// CHECK3-32-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 44422// CHECK3-32-NEXT: [[DOTOFFLOAD_BASEPTRS8:%.*]] = alloca [2 x i8*], align 44423// CHECK3-32-NEXT: [[DOTOFFLOAD_PTRS9:%.*]] = alloca [2 x i8*], align 44424// CHECK3-32-NEXT: [[DOTOFFLOAD_MAPPERS10:%.*]] = alloca [2 x i8*], align 44425// CHECK3-32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 44426// CHECK3-32-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 44427// CHECK3-32-NEXT: store i32 0, i32* [[A]], align 44428// CHECK3-32-NEXT: store i16 0, i16* [[AA]], align 24429// CHECK3-32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 44430// CHECK3-32-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave()4431// CHECK3-32-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 44432// CHECK3-32-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 44433// CHECK3-32-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 44434// CHECK3-32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 44435// CHECK3-32-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]4436// CHECK3-32-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 84437// CHECK3-32-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 44438// CHECK3-32-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 04439// CHECK3-32-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 44440// CHECK3-32-NEXT: store i32 [[TMP4]], i32* [[X]], align 44441// CHECK3-32-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 14442// CHECK3-32-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 44443// CHECK3-32-NEXT: store i32 [[TMP5]], i32* [[Y]], align 44444// CHECK3-32-NEXT: store i32* [[A]], i32** [[P]], align 644445// CHECK3-32-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 44446// CHECK3-32-NEXT: store i32 [[TMP6]], i32* [[A_CASTED]], align 44447// CHECK3-32-NEXT: [[TMP7:%.*]] = load i32, i32* [[A_CASTED]], align 44448// CHECK3-32-NEXT: [[TMP8:%.*]] = load i32*, i32** [[P]], align 644449// CHECK3-32-NEXT: [[TMP9:%.*]] = load i32, i32* @ga, align 44450// CHECK3-32-NEXT: store i32 [[TMP9]], i32* [[GA_CASTED]], align 44451// CHECK3-32-NEXT: [[TMP10:%.*]] = load i32, i32* [[GA_CASTED]], align 44452// CHECK3-32-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 04453// CHECK3-32-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32*4454// CHECK3-32-NEXT: store i32 [[TMP7]], i32* [[TMP12]], align 44455// CHECK3-32-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 04456// CHECK3-32-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32*4457// CHECK3-32-NEXT: store i32 [[TMP7]], i32* [[TMP14]], align 44458// CHECK3-32-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 04459// CHECK3-32-NEXT: store i8* null, i8** [[TMP15]], align 44460// CHECK3-32-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 14461// CHECK3-32-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32**4462// CHECK3-32-NEXT: store i32* [[TMP8]], i32** [[TMP17]], align 44463// CHECK3-32-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 14464// CHECK3-32-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32**4465// CHECK3-32-NEXT: store i32* [[TMP8]], i32** [[TMP19]], align 44466// CHECK3-32-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 14467// CHECK3-32-NEXT: store i8* null, i8** [[TMP20]], align 44468// CHECK3-32-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 24469// CHECK3-32-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32*4470// CHECK3-32-NEXT: store i32 [[TMP10]], i32* [[TMP22]], align 44471// CHECK3-32-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 24472// CHECK3-32-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32*4473// CHECK3-32-NEXT: store i32 [[TMP10]], i32* [[TMP24]], align 44474// CHECK3-32-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 24475// CHECK3-32-NEXT: store i8* null, i8** [[TMP25]], align 44476// CHECK3-32-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 04477// CHECK3-32-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 04478// CHECK3-32-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 84479// CHECK3-32-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 04480// CHECK3-32-NEXT: store i32 2, i32* [[TMP28]], align 44481// CHECK3-32-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 14482// CHECK3-32-NEXT: store i32 3, i32* [[TMP29]], align 44483// CHECK3-32-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 24484// CHECK3-32-NEXT: store i8** [[TMP26]], i8*** [[TMP30]], align 44485// CHECK3-32-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 34486// CHECK3-32-NEXT: store i8** [[TMP27]], i8*** [[TMP31]], align 44487// CHECK3-32-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 44488// CHECK3-32-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP32]], align 44489// CHECK3-32-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 54490// CHECK3-32-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP33]], align 44491// CHECK3-32-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 64492// CHECK3-32-NEXT: store i8** null, i8*** [[TMP34]], align 44493// CHECK3-32-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 74494// CHECK3-32-NEXT: store i8** null, i8*** [[TMP35]], align 44495// CHECK3-32-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 84496// CHECK3-32-NEXT: store i64 0, i64* [[TMP36]], align 84497// CHECK3-32-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 94498// CHECK3-32-NEXT: store i64 0, i64* [[TMP37]], align 84499// CHECK3-32-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 104500// CHECK3-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP38]], align 44501// CHECK3-32-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 114502// CHECK3-32-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP39]], align 44503// CHECK3-32-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 124504// CHECK3-32-NEXT: store i32 0, i32* [[TMP40]], align 44505// CHECK3-32-NEXT: [[TMP41:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])4506// CHECK3-32-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 04507// CHECK3-32-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]4508// CHECK3-32: omp_offload.failed:4509// CHECK3-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63(i32 [[TMP7]], i32* [[TMP8]], i32 [[TMP10]]) #[[ATTR3:[0-9]+]]4510// CHECK3-32-NEXT: br label [[OMP_OFFLOAD_CONT]]4511// CHECK3-32: omp_offload.cont:4512// CHECK3-32-NEXT: [[TMP43:%.*]] = load i16, i16* [[AA]], align 24513// CHECK3-32-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*4514// CHECK3-32-NEXT: store i16 [[TMP43]], i16* [[CONV]], align 24515// CHECK3-32-NEXT: [[TMP44:%.*]] = load i32, i32* [[AA_CASTED]], align 44516// CHECK3-32-NEXT: [[TMP45:%.*]] = mul nuw i32 [[TMP0]], 44517// CHECK3-32-NEXT: [[TMP46:%.*]] = sext i32 [[TMP45]] to i644518// CHECK3-32-NEXT: [[TMP47:%.*]] = mul nuw i32 5, [[TMP2]]4519// CHECK3-32-NEXT: [[TMP48:%.*]] = mul nuw i32 [[TMP47]], 84520// CHECK3-32-NEXT: [[TMP49:%.*]] = sext i32 [[TMP48]] to i644521// CHECK3-32-NEXT: [[TMP50:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8*4522// CHECK3-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 bitcast ([9 x i64]* @.offload_sizes.1 to i8*), i32 72, i1 false)4523// CHECK3-32-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 04524// CHECK3-32-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32*4525// CHECK3-32-NEXT: store i32 [[TMP44]], i32* [[TMP52]], align 44526// CHECK3-32-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 04527// CHECK3-32-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to i32*4528// CHECK3-32-NEXT: store i32 [[TMP44]], i32* [[TMP54]], align 44529// CHECK3-32-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 04530// CHECK3-32-NEXT: store i8* null, i8** [[TMP55]], align 44531// CHECK3-32-NEXT: [[TMP56:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 14532// CHECK3-32-NEXT: [[TMP57:%.*]] = bitcast i8** [[TMP56]] to [10 x float]**4533// CHECK3-32-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP57]], align 44534// CHECK3-32-NEXT: [[TMP58:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 14535// CHECK3-32-NEXT: [[TMP59:%.*]] = bitcast i8** [[TMP58]] to [10 x float]**4536// CHECK3-32-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP59]], align 44537// CHECK3-32-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 14538// CHECK3-32-NEXT: store i8* null, i8** [[TMP60]], align 44539// CHECK3-32-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 24540// CHECK3-32-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32*4541// CHECK3-32-NEXT: store i32 [[TMP0]], i32* [[TMP62]], align 44542// CHECK3-32-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 24543// CHECK3-32-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i32*4544// CHECK3-32-NEXT: store i32 [[TMP0]], i32* [[TMP64]], align 44545// CHECK3-32-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 24546// CHECK3-32-NEXT: store i8* null, i8** [[TMP65]], align 44547// CHECK3-32-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 34548// CHECK3-32-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to float**4549// CHECK3-32-NEXT: store float* [[VLA]], float** [[TMP67]], align 44550// CHECK3-32-NEXT: [[TMP68:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 34551// CHECK3-32-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to float**4552// CHECK3-32-NEXT: store float* [[VLA]], float** [[TMP69]], align 44553// CHECK3-32-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 34554// CHECK3-32-NEXT: store i64 [[TMP46]], i64* [[TMP70]], align 44555// CHECK3-32-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 34556// CHECK3-32-NEXT: store i8* null, i8** [[TMP71]], align 44557// CHECK3-32-NEXT: [[TMP72:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 44558// CHECK3-32-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to [5 x [10 x double]]**4559// CHECK3-32-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP73]], align 44560// CHECK3-32-NEXT: [[TMP74:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 44561// CHECK3-32-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to [5 x [10 x double]]**4562// CHECK3-32-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP75]], align 44563// CHECK3-32-NEXT: [[TMP76:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 44564// CHECK3-32-NEXT: store i8* null, i8** [[TMP76]], align 44565// CHECK3-32-NEXT: [[TMP77:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 54566// CHECK3-32-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i32*4567// CHECK3-32-NEXT: store i32 5, i32* [[TMP78]], align 44568// CHECK3-32-NEXT: [[TMP79:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 54569// CHECK3-32-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i32*4570// CHECK3-32-NEXT: store i32 5, i32* [[TMP80]], align 44571// CHECK3-32-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 54572// CHECK3-32-NEXT: store i8* null, i8** [[TMP81]], align 44573// CHECK3-32-NEXT: [[TMP82:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 64574// CHECK3-32-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i32*4575// CHECK3-32-NEXT: store i32 [[TMP2]], i32* [[TMP83]], align 44576// CHECK3-32-NEXT: [[TMP84:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 64577// CHECK3-32-NEXT: [[TMP85:%.*]] = bitcast i8** [[TMP84]] to i32*4578// CHECK3-32-NEXT: store i32 [[TMP2]], i32* [[TMP85]], align 44579// CHECK3-32-NEXT: [[TMP86:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 64580// CHECK3-32-NEXT: store i8* null, i8** [[TMP86]], align 44581// CHECK3-32-NEXT: [[TMP87:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 74582// CHECK3-32-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to double**4583// CHECK3-32-NEXT: store double* [[VLA1]], double** [[TMP88]], align 44584// CHECK3-32-NEXT: [[TMP89:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 74585// CHECK3-32-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to double**4586// CHECK3-32-NEXT: store double* [[VLA1]], double** [[TMP90]], align 44587// CHECK3-32-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 74588// CHECK3-32-NEXT: store i64 [[TMP49]], i64* [[TMP91]], align 44589// CHECK3-32-NEXT: [[TMP92:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 74590// CHECK3-32-NEXT: store i8* null, i8** [[TMP92]], align 44591// CHECK3-32-NEXT: [[TMP93:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 84592// CHECK3-32-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to %struct.TT**4593// CHECK3-32-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP94]], align 44594// CHECK3-32-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 84595// CHECK3-32-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to %struct.TT**4596// CHECK3-32-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP96]], align 44597// CHECK3-32-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 84598// CHECK3-32-NEXT: store i8* null, i8** [[TMP97]], align 44599// CHECK3-32-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 04600// CHECK3-32-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 04601// CHECK3-32-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 04602// CHECK3-32-NEXT: [[KERNEL_ARGS5:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 84603// CHECK3-32-NEXT: [[TMP101:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 04604// CHECK3-32-NEXT: store i32 2, i32* [[TMP101]], align 44605// CHECK3-32-NEXT: [[TMP102:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 14606// CHECK3-32-NEXT: store i32 9, i32* [[TMP102]], align 44607// CHECK3-32-NEXT: [[TMP103:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 24608// CHECK3-32-NEXT: store i8** [[TMP98]], i8*** [[TMP103]], align 44609// CHECK3-32-NEXT: [[TMP104:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 34610// CHECK3-32-NEXT: store i8** [[TMP99]], i8*** [[TMP104]], align 44611// CHECK3-32-NEXT: [[TMP105:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 44612// CHECK3-32-NEXT: store i64* [[TMP100]], i64** [[TMP105]], align 44613// CHECK3-32-NEXT: [[TMP106:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 54614// CHECK3-32-NEXT: store i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.2, i32 0, i32 0), i64** [[TMP106]], align 44615// CHECK3-32-NEXT: [[TMP107:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 64616// CHECK3-32-NEXT: store i8** null, i8*** [[TMP107]], align 44617// CHECK3-32-NEXT: [[TMP108:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 74618// CHECK3-32-NEXT: store i8** null, i8*** [[TMP108]], align 44619// CHECK3-32-NEXT: [[TMP109:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 84620// CHECK3-32-NEXT: store i64 0, i64* [[TMP109]], align 84621// CHECK3-32-NEXT: [[TMP110:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 94622// CHECK3-32-NEXT: store i64 0, i64* [[TMP110]], align 84623// CHECK3-32-NEXT: [[TMP111:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 104624// CHECK3-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP111]], align 44625// CHECK3-32-NEXT: [[TMP112:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 114626// CHECK3-32-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP112]], align 44627// CHECK3-32-NEXT: [[TMP113:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 124628// CHECK3-32-NEXT: store i32 0, i32* [[TMP113]], align 44629// CHECK3-32-NEXT: [[TMP114:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]])4630// CHECK3-32-NEXT: [[TMP115:%.*]] = icmp ne i32 [[TMP114]], 04631// CHECK3-32-NEXT: br i1 [[TMP115]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]]4632// CHECK3-32: omp_offload.failed6:4633// CHECK3-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70(i32 [[TMP44]], [10 x float]* [[B]], i32 [[TMP0]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP2]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]4634// CHECK3-32-NEXT: br label [[OMP_OFFLOAD_CONT7]]4635// CHECK3-32: omp_offload.cont7:4636// CHECK3-32-NEXT: [[TMP116:%.*]] = load double*, double** [[PTR_ADDR]], align 44637// CHECK3-32-NEXT: [[TMP117:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 04638// CHECK3-32-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to double**4639// CHECK3-32-NEXT: store double* [[TMP116]], double** [[TMP118]], align 44640// CHECK3-32-NEXT: [[TMP119:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 04641// CHECK3-32-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to double**4642// CHECK3-32-NEXT: store double* [[TMP116]], double** [[TMP120]], align 44643// CHECK3-32-NEXT: [[TMP121:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS10]], i32 0, i32 04644// CHECK3-32-NEXT: store i8* null, i8** [[TMP121]], align 44645// CHECK3-32-NEXT: [[TMP122:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 14646// CHECK3-32-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to %struct.TT.0**4647// CHECK3-32-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[TMP123]], align 44648// CHECK3-32-NEXT: [[TMP124:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 14649// CHECK3-32-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to %struct.TT.0**4650// CHECK3-32-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[TMP125]], align 44651// CHECK3-32-NEXT: [[TMP126:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS10]], i32 0, i32 14652// CHECK3-32-NEXT: store i8* null, i8** [[TMP126]], align 44653// CHECK3-32-NEXT: [[TMP127:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 04654// CHECK3-32-NEXT: [[TMP128:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 04655// CHECK3-32-NEXT: [[KERNEL_ARGS11:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 84656// CHECK3-32-NEXT: [[TMP129:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 04657// CHECK3-32-NEXT: store i32 2, i32* [[TMP129]], align 44658// CHECK3-32-NEXT: [[TMP130:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 14659// CHECK3-32-NEXT: store i32 2, i32* [[TMP130]], align 44660// CHECK3-32-NEXT: [[TMP131:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 24661// CHECK3-32-NEXT: store i8** [[TMP127]], i8*** [[TMP131]], align 44662// CHECK3-32-NEXT: [[TMP132:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 34663// CHECK3-32-NEXT: store i8** [[TMP128]], i8*** [[TMP132]], align 44664// CHECK3-32-NEXT: [[TMP133:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 44665// CHECK3-32-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.3, i32 0, i32 0), i64** [[TMP133]], align 44666// CHECK3-32-NEXT: [[TMP134:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 54667// CHECK3-32-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.4, i32 0, i32 0), i64** [[TMP134]], align 44668// CHECK3-32-NEXT: [[TMP135:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 64669// CHECK3-32-NEXT: store i8** null, i8*** [[TMP135]], align 44670// CHECK3-32-NEXT: [[TMP136:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 74671// CHECK3-32-NEXT: store i8** null, i8*** [[TMP136]], align 44672// CHECK3-32-NEXT: [[TMP137:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 84673// CHECK3-32-NEXT: store i64 0, i64* [[TMP137]], align 84674// CHECK3-32-NEXT: [[TMP138:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 94675// CHECK3-32-NEXT: store i64 0, i64* [[TMP138]], align 84676// CHECK3-32-NEXT: [[TMP139:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 104677// CHECK3-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP139]], align 44678// CHECK3-32-NEXT: [[TMP140:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 114679// CHECK3-32-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP140]], align 44680// CHECK3-32-NEXT: [[TMP141:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 124681// CHECK3-32-NEXT: store i32 0, i32* [[TMP141]], align 44682// CHECK3-32-NEXT: [[TMP142:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]])4683// CHECK3-32-NEXT: [[TMP143:%.*]] = icmp ne i32 [[TMP142]], 04684// CHECK3-32-NEXT: br i1 [[TMP143]], label [[OMP_OFFLOAD_FAILED12:%.*]], label [[OMP_OFFLOAD_CONT13:%.*]]4685// CHECK3-32: omp_offload.failed12:4686// CHECK3-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111(double* [[TMP116]], %struct.TT.0* [[E]]) #[[ATTR3]]4687// CHECK3-32-NEXT: br label [[OMP_OFFLOAD_CONT13]]4688// CHECK3-32: omp_offload.cont13:4689// CHECK3-32-NEXT: [[TMP144:%.*]] = load i32, i32* [[A]], align 44690// CHECK3-32-NEXT: [[TMP145:%.*]] = load i8*, i8** [[SAVED_STACK]], align 44691// CHECK3-32-NEXT: call void @llvm.stackrestore(i8* [[TMP145]])4692// CHECK3-32-NEXT: ret i32 [[TMP144]]4693// CHECK3-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l634694// CHECK3-32-SAME: (i32 noundef [[A:%.*]], i32* noundef [[P:%.*]], i32 noundef [[GA:%.*]]) #[[ATTR2:[0-9]+]] {4695// CHECK3-32-NEXT: entry:4696// CHECK3-32-NEXT: [[A_ADDR:%.*]] = alloca i32, align 44697// CHECK3-32-NEXT: [[P_ADDR:%.*]] = alloca i32*, align 44698// CHECK3-32-NEXT: [[GA_ADDR:%.*]] = alloca i32, align 44699// CHECK3-32-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 44700// CHECK3-32-NEXT: store i32* [[P]], i32** [[P_ADDR]], align 44701// CHECK3-32-NEXT: store i32 [[GA]], i32* [[GA_ADDR]], align 44702// CHECK3-32-NEXT: ret void4703// CHECK3-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l704704// CHECK3-32-SAME: (i32 noundef [[AA:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {4705// CHECK3-32-NEXT: entry:4706// CHECK3-32-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 44707// CHECK3-32-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 44708// CHECK3-32-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 44709// CHECK3-32-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 44710// CHECK3-32-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 44711// CHECK3-32-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 44712// CHECK3-32-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 44713// CHECK3-32-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 44714// CHECK3-32-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 44715// CHECK3-32-NEXT: [[B5:%.*]] = alloca [10 x float], align 44716// CHECK3-32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 44717// CHECK3-32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 44718// CHECK3-32-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 84719// CHECK3-32-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 44720// CHECK3-32-NEXT: [[__VLA_EXPR2:%.*]] = alloca i32, align 44721// CHECK3-32-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 44722// CHECK3-32-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 44723// CHECK3-32-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 44724// CHECK3-32-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 44725// CHECK3-32-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 44726// CHECK3-32-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 44727// CHECK3-32-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 44728// CHECK3-32-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 44729// CHECK3-32-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 44730// CHECK3-32-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 44731// CHECK3-32-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*4732// CHECK3-32-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 44733// CHECK3-32-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 44734// CHECK3-32-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 44735// CHECK3-32-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 44736// CHECK3-32-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 44737// CHECK3-32-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 44738// CHECK3-32-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 44739// CHECK3-32-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 44740// CHECK3-32-NEXT: [[TMP8:%.*]] = bitcast [10 x float]* [[B5]] to i8*4741// CHECK3-32-NEXT: [[TMP9:%.*]] = bitcast [10 x float]* [[TMP0]] to i8*4742// CHECK3-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i32 40, i1 false)4743// CHECK3-32-NEXT: [[TMP10:%.*]] = call i8* @llvm.stacksave()4744// CHECK3-32-NEXT: store i8* [[TMP10]], i8** [[SAVED_STACK]], align 44745// CHECK3-32-NEXT: [[VLA6:%.*]] = alloca float, i32 [[TMP1]], align 44746// CHECK3-32-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 44747// CHECK3-32-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP1]], 44748// CHECK3-32-NEXT: [[TMP12:%.*]] = bitcast float* [[VLA6]] to i8*4749// CHECK3-32-NEXT: [[TMP13:%.*]] = bitcast float* [[TMP2]] to i8*4750// CHECK3-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 [[TMP11]], i1 false)4751// CHECK3-32-NEXT: [[TMP14:%.*]] = bitcast [5 x [10 x double]]* [[C7]] to i8*4752// CHECK3-32-NEXT: [[TMP15:%.*]] = bitcast [5 x [10 x double]]* [[TMP3]] to i8*4753// CHECK3-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 [[TMP14]], i8* align 8 [[TMP15]], i32 400, i1 false)4754// CHECK3-32-NEXT: [[TMP16:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]]4755// CHECK3-32-NEXT: [[VLA8:%.*]] = alloca double, i32 [[TMP16]], align 84756// CHECK3-32-NEXT: store i32 [[TMP4]], i32* [[__VLA_EXPR1]], align 44757// CHECK3-32-NEXT: store i32 [[TMP5]], i32* [[__VLA_EXPR2]], align 44758// CHECK3-32-NEXT: [[TMP17:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]]4759// CHECK3-32-NEXT: [[TMP18:%.*]] = mul nuw i32 [[TMP17]], 84760// CHECK3-32-NEXT: [[TMP19:%.*]] = bitcast double* [[VLA8]] to i8*4761// CHECK3-32-NEXT: [[TMP20:%.*]] = bitcast double* [[TMP6]] to i8*4762// CHECK3-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 [[TMP19]], i8* align 8 [[TMP20]], i32 [[TMP18]], i1 false)4763// CHECK3-32-NEXT: [[TMP21:%.*]] = bitcast %struct.TT* [[D9]] to i8*4764// CHECK3-32-NEXT: [[TMP22:%.*]] = bitcast %struct.TT* [[TMP7]] to i8*4765// CHECK3-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP21]], i8* align 4 [[TMP22]], i32 12, i1 false)4766// CHECK3-32-NEXT: [[TMP23:%.*]] = load i16, i16* [[CONV]], align 24767// CHECK3-32-NEXT: [[CONV10:%.*]] = sext i16 [[TMP23]] to i324768// CHECK3-32-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV10]], 14769// CHECK3-32-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD]] to i164770// CHECK3-32-NEXT: store i16 [[CONV11]], i16* [[CONV]], align 24771// CHECK3-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], i32 0, i32 24772// CHECK3-32-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 44773// CHECK3-32-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA6]], i32 34774// CHECK3-32-NEXT: store float 1.000000e+00, float* [[ARRAYIDX12]], align 44775// CHECK3-32-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], i32 0, i32 14776// CHECK3-32-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i32 0, i32 24777// CHECK3-32-NEXT: store double 1.000000e+00, double* [[ARRAYIDX14]], align 84778// CHECK3-32-NEXT: [[TMP24:%.*]] = mul nsw i32 1, [[TMP5]]4779// CHECK3-32-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[VLA8]], i32 [[TMP24]]4780// CHECK3-32-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i32 34781// CHECK3-32-NEXT: store double 1.000000e+00, double* [[ARRAYIDX16]], align 84782// CHECK3-32-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 04783// CHECK3-32-NEXT: store i64 1, i64* [[X]], align 44784// CHECK3-32-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 14785// CHECK3-32-NEXT: store i8 1, i8* [[Y]], align 44786// CHECK3-32-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 44787// CHECK3-32-NEXT: call void @llvm.stackrestore(i8* [[TMP25]])4788// CHECK3-32-NEXT: ret void4789// CHECK3-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l1114790// CHECK3-32-SAME: (double* noundef [[PTR:%.*]], %struct.TT.0* noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR2]] {4791// CHECK3-32-NEXT: entry:4792// CHECK3-32-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 44793// CHECK3-32-NEXT: [[E_ADDR:%.*]] = alloca %struct.TT.0*, align 44794// CHECK3-32-NEXT: [[E1:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 44795// CHECK3-32-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 44796// CHECK3-32-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[E_ADDR]], align 44797// CHECK3-32-NEXT: [[TMP0:%.*]] = load %struct.TT.0*, %struct.TT.0** [[E_ADDR]], align 44798// CHECK3-32-NEXT: [[TMP1:%.*]] = bitcast %struct.TT.0* [[E1]] to i8*4799// CHECK3-32-NEXT: [[TMP2:%.*]] = bitcast %struct.TT.0* [[TMP0]] to i8*4800// CHECK3-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 8, i1 false)4801// CHECK3-32-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E1]], i32 0, i32 04802// CHECK3-32-NEXT: [[TMP3:%.*]] = load i32, i32* [[X]], align 44803// CHECK3-32-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP3]] to double4804// CHECK3-32-NEXT: [[TMP4:%.*]] = load double*, double** [[PTR_ADDR]], align 44805// CHECK3-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP4]], i32 04806// CHECK3-32-NEXT: store double [[CONV]], double* [[ARRAYIDX]], align 44807// CHECK3-32-NEXT: [[TMP5:%.*]] = load double*, double** [[PTR_ADDR]], align 44808// CHECK3-32-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, double* [[TMP5]], i32 04809// CHECK3-32-NEXT: [[TMP6:%.*]] = load double, double* [[ARRAYIDX2]], align 44810// CHECK3-32-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+004811// CHECK3-32-NEXT: store double [[INC]], double* [[ARRAYIDX2]], align 44812// CHECK3-32-NEXT: ret void4813// CHECK3-32-LABEL: define {{[^@]+}}@_Z3bariPd4814// CHECK3-32-SAME: (i32 noundef [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0]] {4815// CHECK3-32-NEXT: entry:4816// CHECK3-32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 44817// CHECK3-32-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 44818// CHECK3-32-NEXT: [[A:%.*]] = alloca i32, align 44819// CHECK3-32-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 44820// CHECK3-32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 44821// CHECK3-32-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 44822// CHECK3-32-NEXT: store i32 0, i32* [[A]], align 44823// CHECK3-32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 44824// CHECK3-32-NEXT: [[TMP1:%.*]] = load double*, double** [[PTR_ADDR]], align 44825// CHECK3-32-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooiPd(i32 noundef [[TMP0]], double* noundef [[TMP1]])4826// CHECK3-32-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 44827// CHECK3-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]]4828// CHECK3-32-NEXT: store i32 [[ADD]], i32* [[A]], align 44829// CHECK3-32-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 44830// CHECK3-32-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP3]])4831// CHECK3-32-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 44832// CHECK3-32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]]4833// CHECK3-32-NEXT: store i32 [[ADD2]], i32* [[A]], align 44834// CHECK3-32-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 44835// CHECK3-32-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP5]])4836// CHECK3-32-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 44837// CHECK3-32-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]]4838// CHECK3-32-NEXT: store i32 [[ADD4]], i32* [[A]], align 44839// CHECK3-32-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 44840// CHECK3-32-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP7]])4841// CHECK3-32-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 44842// CHECK3-32-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]]4843// CHECK3-32-NEXT: store i32 [[ADD6]], i32* [[A]], align 44844// CHECK3-32-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 44845// CHECK3-32-NEXT: ret i32 [[TMP9]]4846// CHECK3-32-LABEL: define {{[^@]+}}@_ZN2S12r1Ei4847// CHECK3-32-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {4848// CHECK3-32-NEXT: entry:4849// CHECK3-32-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 44850// CHECK3-32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 44851// CHECK3-32-NEXT: [[B:%.*]] = alloca i32, align 44852// CHECK3-32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 44853// CHECK3-32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 44854// CHECK3-32-NEXT: [[B_CASTED:%.*]] = alloca i32, align 44855// CHECK3-32-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 44856// CHECK3-32-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 44857// CHECK3-32-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 44858// CHECK3-32-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 44859// CHECK3-32-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 44860// CHECK3-32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 44861// CHECK3-32-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 44862// CHECK3-32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 44863// CHECK3-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 14864// CHECK3-32-NEXT: store i32 [[ADD]], i32* [[B]], align 44865// CHECK3-32-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 44866// CHECK3-32-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()4867// CHECK3-32-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 44868// CHECK3-32-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]4869// CHECK3-32-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 24870// CHECK3-32-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 44871// CHECK3-32-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 44872// CHECK3-32-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 44873// CHECK3-32-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 44874// CHECK3-32-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 04875// CHECK3-32-NEXT: [[TMP6:%.*]] = mul nuw i32 2, [[TMP1]]4876// CHECK3-32-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP6]], 24877// CHECK3-32-NEXT: [[TMP8:%.*]] = sext i32 [[TMP7]] to i644878// CHECK3-32-NEXT: [[TMP9:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8*4879// CHECK3-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.5 to i8*), i32 40, i1 false)4880// CHECK3-32-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 04881// CHECK3-32-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**4882// CHECK3-32-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 44883// CHECK3-32-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 04884// CHECK3-32-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**4885// CHECK3-32-NEXT: store double* [[A]], double** [[TMP13]], align 44886// CHECK3-32-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 04887// CHECK3-32-NEXT: store i8* null, i8** [[TMP14]], align 44888// CHECK3-32-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 14889// CHECK3-32-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32*4890// CHECK3-32-NEXT: store i32 [[TMP5]], i32* [[TMP16]], align 44891// CHECK3-32-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 14892// CHECK3-32-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*4893// CHECK3-32-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 44894// CHECK3-32-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 14895// CHECK3-32-NEXT: store i8* null, i8** [[TMP19]], align 44896// CHECK3-32-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 24897// CHECK3-32-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32*4898// CHECK3-32-NEXT: store i32 2, i32* [[TMP21]], align 44899// CHECK3-32-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 24900// CHECK3-32-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*4901// CHECK3-32-NEXT: store i32 2, i32* [[TMP23]], align 44902// CHECK3-32-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 24903// CHECK3-32-NEXT: store i8* null, i8** [[TMP24]], align 44904// CHECK3-32-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 34905// CHECK3-32-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32*4906// CHECK3-32-NEXT: store i32 [[TMP1]], i32* [[TMP26]], align 44907// CHECK3-32-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 34908// CHECK3-32-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32*4909// CHECK3-32-NEXT: store i32 [[TMP1]], i32* [[TMP28]], align 44910// CHECK3-32-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 34911// CHECK3-32-NEXT: store i8* null, i8** [[TMP29]], align 44912// CHECK3-32-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 44913// CHECK3-32-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i16**4914// CHECK3-32-NEXT: store i16* [[VLA]], i16** [[TMP31]], align 44915// CHECK3-32-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 44916// CHECK3-32-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i16**4917// CHECK3-32-NEXT: store i16* [[VLA]], i16** [[TMP33]], align 44918// CHECK3-32-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 44919// CHECK3-32-NEXT: store i64 [[TMP8]], i64* [[TMP34]], align 44920// CHECK3-32-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 44921// CHECK3-32-NEXT: store i8* null, i8** [[TMP35]], align 44922// CHECK3-32-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 04923// CHECK3-32-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 04924// CHECK3-32-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 04925// CHECK3-32-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 84926// CHECK3-32-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 04927// CHECK3-32-NEXT: store i32 2, i32* [[TMP39]], align 44928// CHECK3-32-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 14929// CHECK3-32-NEXT: store i32 5, i32* [[TMP40]], align 44930// CHECK3-32-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 24931// CHECK3-32-NEXT: store i8** [[TMP36]], i8*** [[TMP41]], align 44932// CHECK3-32-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 34933// CHECK3-32-NEXT: store i8** [[TMP37]], i8*** [[TMP42]], align 44934// CHECK3-32-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 44935// CHECK3-32-NEXT: store i64* [[TMP38]], i64** [[TMP43]], align 44936// CHECK3-32-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 54937// CHECK3-32-NEXT: store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.6, i32 0, i32 0), i64** [[TMP44]], align 44938// CHECK3-32-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 64939// CHECK3-32-NEXT: store i8** null, i8*** [[TMP45]], align 44940// CHECK3-32-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 74941// CHECK3-32-NEXT: store i8** null, i8*** [[TMP46]], align 44942// CHECK3-32-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 84943// CHECK3-32-NEXT: store i64 0, i64* [[TMP47]], align 84944// CHECK3-32-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 94945// CHECK3-32-NEXT: store i64 0, i64* [[TMP48]], align 84946// CHECK3-32-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 104947// CHECK3-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP49]], align 44948// CHECK3-32-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 114949// CHECK3-32-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP50]], align 44950// CHECK3-32-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 124951// CHECK3-32-NEXT: store i32 0, i32* [[TMP51]], align 44952// CHECK3-32-NEXT: [[TMP52:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])4953// CHECK3-32-NEXT: [[TMP53:%.*]] = icmp ne i32 [[TMP52]], 04954// CHECK3-32-NEXT: br i1 [[TMP53]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]4955// CHECK3-32: omp_offload.failed:4956// CHECK3-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]]4957// CHECK3-32-NEXT: br label [[OMP_OFFLOAD_CONT]]4958// CHECK3-32: omp_offload.cont:4959// CHECK3-32-NEXT: [[TMP54:%.*]] = mul nsw i32 1, [[TMP1]]4960// CHECK3-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP54]]4961// CHECK3-32-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 14962// CHECK3-32-NEXT: [[TMP55:%.*]] = load i16, i16* [[ARRAYIDX2]], align 24963// CHECK3-32-NEXT: [[CONV:%.*]] = sext i16 [[TMP55]] to i324964// CHECK3-32-NEXT: [[TMP56:%.*]] = load i32, i32* [[B]], align 44965// CHECK3-32-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP56]]4966// CHECK3-32-NEXT: [[TMP57:%.*]] = load i8*, i8** [[SAVED_STACK]], align 44967// CHECK3-32-NEXT: call void @llvm.stackrestore(i8* [[TMP57]])4968// CHECK3-32-NEXT: ret i32 [[ADD3]]4969// CHECK3-32-LABEL: define {{[^@]+}}@_ZL7fstatici4970// CHECK3-32-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {4971// CHECK3-32-NEXT: entry:4972// CHECK3-32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 44973// CHECK3-32-NEXT: [[A:%.*]] = alloca i32, align 44974// CHECK3-32-NEXT: [[AAA:%.*]] = alloca i8, align 14975// CHECK3-32-NEXT: [[B:%.*]] = alloca [10 x i32], align 44976// CHECK3-32-NEXT: [[A_CASTED:%.*]] = alloca i32, align 44977// CHECK3-32-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 44978// CHECK3-32-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 44979// CHECK3-32-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 44980// CHECK3-32-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 44981// CHECK3-32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 44982// CHECK3-32-NEXT: store i32 0, i32* [[A]], align 44983// CHECK3-32-NEXT: store i8 0, i8* [[AAA]], align 14984// CHECK3-32-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 44985// CHECK3-32-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 44986// CHECK3-32-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 44987// CHECK3-32-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 14988// CHECK3-32-NEXT: [[CONV:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*4989// CHECK3-32-NEXT: store i8 [[TMP2]], i8* [[CONV]], align 14990// CHECK3-32-NEXT: [[TMP3:%.*]] = load i32, i32* [[AAA_CASTED]], align 44991// CHECK3-32-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 04992// CHECK3-32-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32*4993// CHECK3-32-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 44994// CHECK3-32-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 04995// CHECK3-32-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32*4996// CHECK3-32-NEXT: store i32 [[TMP1]], i32* [[TMP7]], align 44997// CHECK3-32-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 04998// CHECK3-32-NEXT: store i8* null, i8** [[TMP8]], align 44999// CHECK3-32-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 15000// CHECK3-32-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*5001// CHECK3-32-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 45002// CHECK3-32-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 15003// CHECK3-32-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32*5004// CHECK3-32-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 45005// CHECK3-32-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 15006// CHECK3-32-NEXT: store i8* null, i8** [[TMP13]], align 45007// CHECK3-32-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 25008// CHECK3-32-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [10 x i32]**5009// CHECK3-32-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP15]], align 45010// CHECK3-32-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 25011// CHECK3-32-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [10 x i32]**5012// CHECK3-32-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP17]], align 45013// CHECK3-32-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 25014// CHECK3-32-NEXT: store i8* null, i8** [[TMP18]], align 45015// CHECK3-32-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 05016// CHECK3-32-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 05017// CHECK3-32-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 85018// CHECK3-32-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 05019// CHECK3-32-NEXT: store i32 2, i32* [[TMP21]], align 45020// CHECK3-32-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 15021// CHECK3-32-NEXT: store i32 3, i32* [[TMP22]], align 45022// CHECK3-32-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 25023// CHECK3-32-NEXT: store i8** [[TMP19]], i8*** [[TMP23]], align 45024// CHECK3-32-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 35025// CHECK3-32-NEXT: store i8** [[TMP20]], i8*** [[TMP24]], align 45026// CHECK3-32-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 45027// CHECK3-32-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.7, i32 0, i32 0), i64** [[TMP25]], align 45028// CHECK3-32-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 55029// CHECK3-32-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.8, i32 0, i32 0), i64** [[TMP26]], align 45030// CHECK3-32-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 65031// CHECK3-32-NEXT: store i8** null, i8*** [[TMP27]], align 45032// CHECK3-32-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 75033// CHECK3-32-NEXT: store i8** null, i8*** [[TMP28]], align 45034// CHECK3-32-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 85035// CHECK3-32-NEXT: store i64 0, i64* [[TMP29]], align 85036// CHECK3-32-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 95037// CHECK3-32-NEXT: store i64 0, i64* [[TMP30]], align 85038// CHECK3-32-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 105039// CHECK3-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP31]], align 45040// CHECK3-32-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 115041// CHECK3-32-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP32]], align 45042// CHECK3-32-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 125043// CHECK3-32-NEXT: store i32 0, i32* [[TMP33]], align 45044// CHECK3-32-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])5045// CHECK3-32-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 05046// CHECK3-32-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]5047// CHECK3-32: omp_offload.failed:5048// CHECK3-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]5049// CHECK3-32-NEXT: br label [[OMP_OFFLOAD_CONT]]5050// CHECK3-32: omp_offload.cont:5051// CHECK3-32-NEXT: [[TMP36:%.*]] = load i32, i32* [[A]], align 45052// CHECK3-32-NEXT: ret i32 [[TMP36]]5053// CHECK3-32-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i5054// CHECK3-32-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {5055// CHECK3-32-NEXT: entry:5056// CHECK3-32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 45057// CHECK3-32-NEXT: [[A:%.*]] = alloca i32, align 45058// CHECK3-32-NEXT: [[B:%.*]] = alloca [10 x i32], align 45059// CHECK3-32-NEXT: [[A_CASTED:%.*]] = alloca i32, align 45060// CHECK3-32-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 45061// CHECK3-32-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 45062// CHECK3-32-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 45063// CHECK3-32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 45064// CHECK3-32-NEXT: store i32 0, i32* [[A]], align 45065// CHECK3-32-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 45066// CHECK3-32-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 45067// CHECK3-32-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 45068// CHECK3-32-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 05069// CHECK3-32-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32*5070// CHECK3-32-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 45071// CHECK3-32-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 05072// CHECK3-32-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32*5073// CHECK3-32-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 45074// CHECK3-32-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 05075// CHECK3-32-NEXT: store i8* null, i8** [[TMP6]], align 45076// CHECK3-32-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 15077// CHECK3-32-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [10 x i32]**5078// CHECK3-32-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP8]], align 45079// CHECK3-32-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 15080// CHECK3-32-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]**5081// CHECK3-32-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP10]], align 45082// CHECK3-32-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 15083// CHECK3-32-NEXT: store i8* null, i8** [[TMP11]], align 45084// CHECK3-32-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 05085// CHECK3-32-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 05086// CHECK3-32-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 85087// CHECK3-32-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 05088// CHECK3-32-NEXT: store i32 2, i32* [[TMP14]], align 45089// CHECK3-32-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 15090// CHECK3-32-NEXT: store i32 2, i32* [[TMP15]], align 45091// CHECK3-32-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 25092// CHECK3-32-NEXT: store i8** [[TMP12]], i8*** [[TMP16]], align 45093// CHECK3-32-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 35094// CHECK3-32-NEXT: store i8** [[TMP13]], i8*** [[TMP17]], align 45095// CHECK3-32-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 45096// CHECK3-32-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.9, i32 0, i32 0), i64** [[TMP18]], align 45097// CHECK3-32-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 55098// CHECK3-32-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.10, i32 0, i32 0), i64** [[TMP19]], align 45099// CHECK3-32-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 65100// CHECK3-32-NEXT: store i8** null, i8*** [[TMP20]], align 45101// CHECK3-32-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 75102// CHECK3-32-NEXT: store i8** null, i8*** [[TMP21]], align 45103// CHECK3-32-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 85104// CHECK3-32-NEXT: store i64 0, i64* [[TMP22]], align 85105// CHECK3-32-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 95106// CHECK3-32-NEXT: store i64 0, i64* [[TMP23]], align 85107// CHECK3-32-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 105108// CHECK3-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP24]], align 45109// CHECK3-32-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 115110// CHECK3-32-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP25]], align 45111// CHECK3-32-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 125112// CHECK3-32-NEXT: store i32 0, i32* [[TMP26]], align 45113// CHECK3-32-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])5114// CHECK3-32-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 05115// CHECK3-32-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]5116// CHECK3-32: omp_offload.failed:5117// CHECK3-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128(i32 [[TMP1]], [10 x i32]* [[B]]) #[[ATTR3]]5118// CHECK3-32-NEXT: br label [[OMP_OFFLOAD_CONT]]5119// CHECK3-32: omp_offload.cont:5120// CHECK3-32-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 45121// CHECK3-32-NEXT: ret i32 [[TMP29]]5122// CHECK3-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l1675123// CHECK3-32-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {5124// CHECK3-32-NEXT: entry:5125// CHECK3-32-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 45126// CHECK3-32-NEXT: [[B_ADDR:%.*]] = alloca i32, align 45127// CHECK3-32-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 45128// CHECK3-32-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 45129// CHECK3-32-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 45130// CHECK3-32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 45131// CHECK3-32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 45132// CHECK3-32-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 45133// CHECK3-32-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 45134// CHECK3-32-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 45135// CHECK3-32-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 45136// CHECK3-32-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 45137// CHECK3-32-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 45138// CHECK3-32-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 45139// CHECK3-32-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 45140// CHECK3-32-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 45141// CHECK3-32-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 45142// CHECK3-32-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave()5143// CHECK3-32-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 45144// CHECK3-32-NEXT: [[TMP5:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]5145// CHECK3-32-NEXT: [[VLA3:%.*]] = alloca i16, i32 [[TMP5]], align 25146// CHECK3-32-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 45147// CHECK3-32-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 45148// CHECK3-32-NEXT: [[TMP6:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]5149// CHECK3-32-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP6]], 25150// CHECK3-32-NEXT: [[TMP8:%.*]] = bitcast i16* [[VLA3]] to i8*5151// CHECK3-32-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP3]] to i8*5152// CHECK3-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 2 [[TMP8]], i8* align 2 [[TMP9]], i32 [[TMP7]], i1 false)5153// CHECK3-32-NEXT: [[TMP10:%.*]] = load i32, i32* [[B_ADDR]], align 45154// CHECK3-32-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP10]] to double5155// CHECK3-32-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+005156// CHECK3-32-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 05157// CHECK3-32-NEXT: store double [[ADD]], double* [[A]], align 45158// CHECK3-32-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 05159// CHECK3-32-NEXT: [[TMP11:%.*]] = load double, double* [[A4]], align 45160// CHECK3-32-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+005161// CHECK3-32-NEXT: store double [[INC]], double* [[A4]], align 45162// CHECK3-32-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i165163// CHECK3-32-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP2]]5164// CHECK3-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA3]], i32 [[TMP12]]5165// CHECK3-32-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 15166// CHECK3-32-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 25167// CHECK3-32-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 45168// CHECK3-32-NEXT: call void @llvm.stackrestore(i8* [[TMP13]])5169// CHECK3-32-NEXT: ret void5170// CHECK3-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l1425171// CHECK3-32-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {5172// CHECK3-32-NEXT: entry:5173// CHECK3-32-NEXT: [[A_ADDR:%.*]] = alloca i32, align 45174// CHECK3-32-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 45175// CHECK3-32-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 45176// CHECK3-32-NEXT: [[B1:%.*]] = alloca [10 x i32], align 45177// CHECK3-32-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 45178// CHECK3-32-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 45179// CHECK3-32-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 45180// CHECK3-32-NEXT: [[CONV:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*5181// CHECK3-32-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 45182// CHECK3-32-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8*5183// CHECK3-32-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*5184// CHECK3-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 40, i1 false)5185// CHECK3-32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 45186// CHECK3-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 15187// CHECK3-32-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 45188// CHECK3-32-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 15189// CHECK3-32-NEXT: [[CONV2:%.*]] = sext i8 [[TMP4]] to i325190// CHECK3-32-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 15191// CHECK3-32-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i85192// CHECK3-32-NEXT: store i8 [[CONV4]], i8* [[CONV]], align 15193// CHECK3-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i32 0, i32 25194// CHECK3-32-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 45195// CHECK3-32-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP5]], 15196// CHECK3-32-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 45197// CHECK3-32-NEXT: ret void5198// CHECK3-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l1285199// CHECK3-32-SAME: (i32 noundef [[A:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {5200// CHECK3-32-NEXT: entry:5201// CHECK3-32-NEXT: [[A_ADDR:%.*]] = alloca i32, align 45202// CHECK3-32-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 45203// CHECK3-32-NEXT: [[B1:%.*]] = alloca [10 x i32], align 45204// CHECK3-32-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 45205// CHECK3-32-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 45206// CHECK3-32-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 45207// CHECK3-32-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8*5208// CHECK3-32-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*5209// CHECK3-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 40, i1 false)5210// CHECK3-32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 45211// CHECK3-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 15212// CHECK3-32-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 45213// CHECK3-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i32 0, i32 25214// CHECK3-32-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 45215// CHECK3-32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], 15216// CHECK3-32-NEXT: store i32 [[ADD2]], i32* [[ARRAYIDX]], align 45217// CHECK3-32-NEXT: ret void5218// CHECK3-32-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg5219// CHECK3-32-SAME: () #[[ATTR5:[0-9]+]] {5220// CHECK3-32-NEXT: entry:5221// CHECK3-32-NEXT: call void @__tgt_register_requires(i64 1)5222// CHECK3-32-NEXT: ret void5223// TCHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l635224// TCHECK-64-SAME: (i64 noundef [[A:%.*]], i32* noundef [[P:%.*]], i64 noundef [[GA:%.*]]) #[[ATTR0:[0-9]+]] {5225// TCHECK-64-NEXT: entry:5226// TCHECK-64-NEXT: [[A_ADDR:%.*]] = alloca i64, align 85227// TCHECK-64-NEXT: [[P_ADDR:%.*]] = alloca i32*, align 85228// TCHECK-64-NEXT: [[GA_ADDR:%.*]] = alloca i64, align 85229// TCHECK-64-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 85230// TCHECK-64-NEXT: store i32* [[P]], i32** [[P_ADDR]], align 85231// TCHECK-64-NEXT: store i64 [[GA]], i64* [[GA_ADDR]], align 85232// TCHECK-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*5233// TCHECK-64-NEXT: [[CONV1:%.*]] = bitcast i64* [[GA_ADDR]] to i32*5234// TCHECK-64-NEXT: ret void5235// TCHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l705236// TCHECK-64-SAME: (i64 noundef [[AA:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {5237// TCHECK-64-NEXT: entry:5238// TCHECK-64-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 85239// TCHECK-64-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 85240// TCHECK-64-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 85241// TCHECK-64-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 85242// TCHECK-64-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 85243// TCHECK-64-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 85244// TCHECK-64-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 85245// TCHECK-64-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 85246// TCHECK-64-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 85247// TCHECK-64-NEXT: [[B5:%.*]] = alloca [10 x float], align 45248// TCHECK-64-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 85249// TCHECK-64-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 85250// TCHECK-64-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 85251// TCHECK-64-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 85252// TCHECK-64-NEXT: [[__VLA_EXPR2:%.*]] = alloca i64, align 85253// TCHECK-64-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 85254// TCHECK-64-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 85255// TCHECK-64-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 85256// TCHECK-64-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 85257// TCHECK-64-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 85258// TCHECK-64-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 85259// TCHECK-64-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 85260// TCHECK-64-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 85261// TCHECK-64-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 85262// TCHECK-64-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 85263// TCHECK-64-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*5264// TCHECK-64-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 85265// TCHECK-64-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 85266// TCHECK-64-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 85267// TCHECK-64-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 85268// TCHECK-64-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 85269// TCHECK-64-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 85270// TCHECK-64-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 85271// TCHECK-64-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 85272// TCHECK-64-NEXT: [[TMP8:%.*]] = bitcast [10 x float]* [[B5]] to i8*5273// TCHECK-64-NEXT: [[TMP9:%.*]] = bitcast [10 x float]* [[TMP0]] to i8*5274// TCHECK-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 40, i1 false)5275// TCHECK-64-NEXT: [[TMP10:%.*]] = call i8* @llvm.stacksave()5276// TCHECK-64-NEXT: store i8* [[TMP10]], i8** [[SAVED_STACK]], align 85277// TCHECK-64-NEXT: [[VLA6:%.*]] = alloca float, i64 [[TMP1]], align 45278// TCHECK-64-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 85279// TCHECK-64-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP1]], 45280// TCHECK-64-NEXT: [[TMP12:%.*]] = bitcast float* [[VLA6]] to i8*5281// TCHECK-64-NEXT: [[TMP13:%.*]] = bitcast float* [[TMP2]] to i8*5282// TCHECK-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 [[TMP11]], i1 false)5283// TCHECK-64-NEXT: [[TMP14:%.*]] = bitcast [5 x [10 x double]]* [[C7]] to i8*5284// TCHECK-64-NEXT: [[TMP15:%.*]] = bitcast [5 x [10 x double]]* [[TMP3]] to i8*5285// TCHECK-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP14]], i8* align 8 [[TMP15]], i64 400, i1 false)5286// TCHECK-64-NEXT: [[TMP16:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]]5287// TCHECK-64-NEXT: [[VLA8:%.*]] = alloca double, i64 [[TMP16]], align 85288// TCHECK-64-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 85289// TCHECK-64-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR2]], align 85290// TCHECK-64-NEXT: [[TMP17:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]]5291// TCHECK-64-NEXT: [[TMP18:%.*]] = mul nuw i64 [[TMP17]], 85292// TCHECK-64-NEXT: [[TMP19:%.*]] = bitcast double* [[VLA8]] to i8*5293// TCHECK-64-NEXT: [[TMP20:%.*]] = bitcast double* [[TMP6]] to i8*5294// TCHECK-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP19]], i8* align 8 [[TMP20]], i64 [[TMP18]], i1 false)5295// TCHECK-64-NEXT: [[TMP21:%.*]] = bitcast %struct.TT* [[D9]] to i8*5296// TCHECK-64-NEXT: [[TMP22:%.*]] = bitcast %struct.TT* [[TMP7]] to i8*5297// TCHECK-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP21]], i8* align 8 [[TMP22]], i64 16, i1 false)5298// TCHECK-64-NEXT: [[TMP23:%.*]] = load i16, i16* [[CONV]], align 25299// TCHECK-64-NEXT: [[CONV10:%.*]] = sext i16 [[TMP23]] to i325300// TCHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV10]], 15301// TCHECK-64-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD]] to i165302// TCHECK-64-NEXT: store i16 [[CONV11]], i16* [[CONV]], align 25303// TCHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], i64 0, i64 25304// TCHECK-64-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 45305// TCHECK-64-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA6]], i64 35306// TCHECK-64-NEXT: store float 1.000000e+00, float* [[ARRAYIDX12]], align 45307// TCHECK-64-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], i64 0, i64 15308// TCHECK-64-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i64 0, i64 25309// TCHECK-64-NEXT: store double 1.000000e+00, double* [[ARRAYIDX14]], align 85310// TCHECK-64-NEXT: [[TMP24:%.*]] = mul nsw i64 1, [[TMP5]]5311// TCHECK-64-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[VLA8]], i64 [[TMP24]]5312// TCHECK-64-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 35313// TCHECK-64-NEXT: store double 1.000000e+00, double* [[ARRAYIDX16]], align 85314// TCHECK-64-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 05315// TCHECK-64-NEXT: store i64 1, i64* [[X]], align 85316// TCHECK-64-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 15317// TCHECK-64-NEXT: store i8 1, i8* [[Y]], align 85318// TCHECK-64-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 85319// TCHECK-64-NEXT: call void @llvm.stackrestore(i8* [[TMP25]])5320// TCHECK-64-NEXT: ret void5321// TCHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l1115322// TCHECK-64-SAME: (double* noundef [[PTR:%.*]], %struct.TT.0* noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR0]] {5323// TCHECK-64-NEXT: entry:5324// TCHECK-64-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 85325// TCHECK-64-NEXT: [[E_ADDR:%.*]] = alloca %struct.TT.0*, align 85326// TCHECK-64-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 85327// TCHECK-64-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[E_ADDR]], align 85328// TCHECK-64-NEXT: [[TMP0:%.*]] = load %struct.TT.0*, %struct.TT.0** [[E_ADDR]], align 85329// TCHECK-64-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0:%.*]], %struct.TT.0* [[TMP0]], i32 0, i32 05330// TCHECK-64-NEXT: [[TMP1:%.*]] = load i32, i32* [[X]], align 45331// TCHECK-64-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double5332// TCHECK-64-NEXT: [[TMP2:%.*]] = load double*, double** [[PTR_ADDR]], align 85333// TCHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP2]], i64 05334// TCHECK-64-NEXT: store double [[CONV]], double* [[ARRAYIDX]], align 85335// TCHECK-64-NEXT: [[TMP3:%.*]] = load double*, double** [[PTR_ADDR]], align 85336// TCHECK-64-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds double, double* [[TMP3]], i64 05337// TCHECK-64-NEXT: [[TMP4:%.*]] = load double, double* [[ARRAYIDX1]], align 85338// TCHECK-64-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+005339// TCHECK-64-NEXT: store double [[INC]], double* [[ARRAYIDX1]], align 85340// TCHECK-64-NEXT: ret void5341// TCHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l1425342// TCHECK-64-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {5343// TCHECK-64-NEXT: entry:5344// TCHECK-64-NEXT: [[A_ADDR:%.*]] = alloca i64, align 85345// TCHECK-64-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 85346// TCHECK-64-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 85347// TCHECK-64-NEXT: [[B2:%.*]] = alloca [10 x i32], align 45348// TCHECK-64-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 85349// TCHECK-64-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 85350// TCHECK-64-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 85351// TCHECK-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*5352// TCHECK-64-NEXT: [[CONV1:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*5353// TCHECK-64-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 85354// TCHECK-64-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B2]] to i8*5355// TCHECK-64-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*5356// TCHECK-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 40, i1 false)5357// TCHECK-64-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 45358// TCHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 15359// TCHECK-64-NEXT: store i32 [[ADD]], i32* [[CONV]], align 45360// TCHECK-64-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 15361// TCHECK-64-NEXT: [[CONV3:%.*]] = sext i8 [[TMP4]] to i325362// TCHECK-64-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 15363// TCHECK-64-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i85364// TCHECK-64-NEXT: store i8 [[CONV5]], i8* [[CONV1]], align 15365// TCHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B2]], i64 0, i64 25366// TCHECK-64-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 45367// TCHECK-64-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP5]], 15368// TCHECK-64-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 45369// TCHECK-64-NEXT: ret void5370// TCHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l1675371// TCHECK-64-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {5372// TCHECK-64-NEXT: entry:5373// TCHECK-64-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 85374// TCHECK-64-NEXT: [[B_ADDR:%.*]] = alloca i64, align 85375// TCHECK-64-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 85376// TCHECK-64-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 85377// TCHECK-64-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 85378// TCHECK-64-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 85379// TCHECK-64-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 85380// TCHECK-64-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 85381// TCHECK-64-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 85382// TCHECK-64-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 85383// TCHECK-64-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 85384// TCHECK-64-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 85385// TCHECK-64-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 85386// TCHECK-64-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 85387// TCHECK-64-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*5388// TCHECK-64-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 85389// TCHECK-64-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 85390// TCHECK-64-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 85391// TCHECK-64-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave()5392// TCHECK-64-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 85393// TCHECK-64-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]]5394// TCHECK-64-NEXT: [[VLA3:%.*]] = alloca i16, i64 [[TMP5]], align 25395// TCHECK-64-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 85396// TCHECK-64-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR1]], align 85397// TCHECK-64-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]]5398// TCHECK-64-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], 25399// TCHECK-64-NEXT: [[TMP8:%.*]] = bitcast i16* [[VLA3]] to i8*5400// TCHECK-64-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP3]] to i8*5401// TCHECK-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 2 [[TMP8]], i8* align 2 [[TMP9]], i64 [[TMP7]], i1 false)5402// TCHECK-64-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 45403// TCHECK-64-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP10]] to double5404// TCHECK-64-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+005405// TCHECK-64-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 05406// TCHECK-64-NEXT: store double [[ADD]], double* [[A]], align 85407// TCHECK-64-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 05408// TCHECK-64-NEXT: [[TMP11:%.*]] = load double, double* [[A5]], align 85409// TCHECK-64-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+005410// TCHECK-64-NEXT: store double [[INC]], double* [[A5]], align 85411// TCHECK-64-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i165412// TCHECK-64-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP2]]5413// TCHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA3]], i64 [[TMP12]]5414// TCHECK-64-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 15415// TCHECK-64-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 25416// TCHECK-64-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 85417// TCHECK-64-NEXT: call void @llvm.stackrestore(i8* [[TMP13]])5418// TCHECK-64-NEXT: ret void5419// TCHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l1285420// TCHECK-64-SAME: (i64 noundef [[A:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {5421// TCHECK-64-NEXT: entry:5422// TCHECK-64-NEXT: [[A_ADDR:%.*]] = alloca i64, align 85423// TCHECK-64-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 85424// TCHECK-64-NEXT: [[B1:%.*]] = alloca [10 x i32], align 45425// TCHECK-64-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 85426// TCHECK-64-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 85427// TCHECK-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*5428// TCHECK-64-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 85429// TCHECK-64-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8*5430// TCHECK-64-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*5431// TCHECK-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 40, i1 false)5432// TCHECK-64-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 45433// TCHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 15434// TCHECK-64-NEXT: store i32 [[ADD]], i32* [[CONV]], align 45435// TCHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i64 0, i64 25436// TCHECK-64-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 45437// TCHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], 15438// TCHECK-64-NEXT: store i32 [[ADD2]], i32* [[ARRAYIDX]], align 45439// TCHECK-64-NEXT: ret void5440// TCHECK1-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l635441// TCHECK1-64-SAME: (i64 noundef [[A:%.*]], i32* noundef [[P:%.*]], i64 noundef [[GA:%.*]]) #[[ATTR0:[0-9]+]] {5442// TCHECK1-64-NEXT: entry:5443// TCHECK1-64-NEXT: [[A_ADDR:%.*]] = alloca i64, align 85444// TCHECK1-64-NEXT: [[P_ADDR:%.*]] = alloca i32*, align 85445// TCHECK1-64-NEXT: [[GA_ADDR:%.*]] = alloca i64, align 85446// TCHECK1-64-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 85447// TCHECK1-64-NEXT: store i32* [[P]], i32** [[P_ADDR]], align 85448// TCHECK1-64-NEXT: store i64 [[GA]], i64* [[GA_ADDR]], align 85449// TCHECK1-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*5450// TCHECK1-64-NEXT: [[CONV1:%.*]] = bitcast i64* [[GA_ADDR]] to i32*5451// TCHECK1-64-NEXT: ret void5452// TCHECK1-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l705453// TCHECK1-64-SAME: (i64 noundef [[AA:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {5454// TCHECK1-64-NEXT: entry:5455// TCHECK1-64-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 85456// TCHECK1-64-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 85457// TCHECK1-64-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 85458// TCHECK1-64-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 85459// TCHECK1-64-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 85460// TCHECK1-64-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 85461// TCHECK1-64-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 85462// TCHECK1-64-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 85463// TCHECK1-64-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 85464// TCHECK1-64-NEXT: [[B5:%.*]] = alloca [10 x float], align 45465// TCHECK1-64-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 85466// TCHECK1-64-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 85467// TCHECK1-64-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 85468// TCHECK1-64-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 85469// TCHECK1-64-NEXT: [[__VLA_EXPR2:%.*]] = alloca i64, align 85470// TCHECK1-64-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 85471// TCHECK1-64-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 85472// TCHECK1-64-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 85473// TCHECK1-64-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 85474// TCHECK1-64-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 85475// TCHECK1-64-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 85476// TCHECK1-64-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 85477// TCHECK1-64-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 85478// TCHECK1-64-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 85479// TCHECK1-64-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 85480// TCHECK1-64-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*5481// TCHECK1-64-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 85482// TCHECK1-64-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 85483// TCHECK1-64-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 85484// TCHECK1-64-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 85485// TCHECK1-64-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 85486// TCHECK1-64-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 85487// TCHECK1-64-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 85488// TCHECK1-64-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 85489// TCHECK1-64-NEXT: [[TMP8:%.*]] = bitcast [10 x float]* [[B5]] to i8*5490// TCHECK1-64-NEXT: [[TMP9:%.*]] = bitcast [10 x float]* [[TMP0]] to i8*5491// TCHECK1-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 40, i1 false)5492// TCHECK1-64-NEXT: [[TMP10:%.*]] = call i8* @llvm.stacksave()5493// TCHECK1-64-NEXT: store i8* [[TMP10]], i8** [[SAVED_STACK]], align 85494// TCHECK1-64-NEXT: [[VLA6:%.*]] = alloca float, i64 [[TMP1]], align 45495// TCHECK1-64-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 85496// TCHECK1-64-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP1]], 45497// TCHECK1-64-NEXT: [[TMP12:%.*]] = bitcast float* [[VLA6]] to i8*5498// TCHECK1-64-NEXT: [[TMP13:%.*]] = bitcast float* [[TMP2]] to i8*5499// TCHECK1-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 [[TMP11]], i1 false)5500// TCHECK1-64-NEXT: [[TMP14:%.*]] = bitcast [5 x [10 x double]]* [[C7]] to i8*5501// TCHECK1-64-NEXT: [[TMP15:%.*]] = bitcast [5 x [10 x double]]* [[TMP3]] to i8*5502// TCHECK1-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP14]], i8* align 8 [[TMP15]], i64 400, i1 false)5503// TCHECK1-64-NEXT: [[TMP16:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]]5504// TCHECK1-64-NEXT: [[VLA8:%.*]] = alloca double, i64 [[TMP16]], align 85505// TCHECK1-64-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 85506// TCHECK1-64-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR2]], align 85507// TCHECK1-64-NEXT: [[TMP17:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]]5508// TCHECK1-64-NEXT: [[TMP18:%.*]] = mul nuw i64 [[TMP17]], 85509// TCHECK1-64-NEXT: [[TMP19:%.*]] = bitcast double* [[VLA8]] to i8*5510// TCHECK1-64-NEXT: [[TMP20:%.*]] = bitcast double* [[TMP6]] to i8*5511// TCHECK1-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP19]], i8* align 8 [[TMP20]], i64 [[TMP18]], i1 false)5512// TCHECK1-64-NEXT: [[TMP21:%.*]] = bitcast %struct.TT* [[D9]] to i8*5513// TCHECK1-64-NEXT: [[TMP22:%.*]] = bitcast %struct.TT* [[TMP7]] to i8*5514// TCHECK1-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP21]], i8* align 8 [[TMP22]], i64 16, i1 false)5515// TCHECK1-64-NEXT: [[TMP23:%.*]] = load i16, i16* [[CONV]], align 25516// TCHECK1-64-NEXT: [[CONV10:%.*]] = sext i16 [[TMP23]] to i325517// TCHECK1-64-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV10]], 15518// TCHECK1-64-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD]] to i165519// TCHECK1-64-NEXT: store i16 [[CONV11]], i16* [[CONV]], align 25520// TCHECK1-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], i64 0, i64 25521// TCHECK1-64-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 45522// TCHECK1-64-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA6]], i64 35523// TCHECK1-64-NEXT: store float 1.000000e+00, float* [[ARRAYIDX12]], align 45524// TCHECK1-64-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], i64 0, i64 15525// TCHECK1-64-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i64 0, i64 25526// TCHECK1-64-NEXT: store double 1.000000e+00, double* [[ARRAYIDX14]], align 85527// TCHECK1-64-NEXT: [[TMP24:%.*]] = mul nsw i64 1, [[TMP5]]5528// TCHECK1-64-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[VLA8]], i64 [[TMP24]]5529// TCHECK1-64-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 35530// TCHECK1-64-NEXT: store double 1.000000e+00, double* [[ARRAYIDX16]], align 85531// TCHECK1-64-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 05532// TCHECK1-64-NEXT: store i64 1, i64* [[X]], align 85533// TCHECK1-64-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 15534// TCHECK1-64-NEXT: store i8 1, i8* [[Y]], align 85535// TCHECK1-64-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 85536// TCHECK1-64-NEXT: call void @llvm.stackrestore(i8* [[TMP25]])5537// TCHECK1-64-NEXT: ret void5538// TCHECK1-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l1115539// TCHECK1-64-SAME: (double* noundef [[PTR:%.*]], %struct.TT.0* noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR0]] {5540// TCHECK1-64-NEXT: entry:5541// TCHECK1-64-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 85542// TCHECK1-64-NEXT: [[E_ADDR:%.*]] = alloca %struct.TT.0*, align 85543// TCHECK1-64-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 85544// TCHECK1-64-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[E_ADDR]], align 85545// TCHECK1-64-NEXT: [[TMP0:%.*]] = load %struct.TT.0*, %struct.TT.0** [[E_ADDR]], align 85546// TCHECK1-64-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0:%.*]], %struct.TT.0* [[TMP0]], i32 0, i32 05547// TCHECK1-64-NEXT: [[TMP1:%.*]] = load i32, i32* [[X]], align 45548// TCHECK1-64-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double5549// TCHECK1-64-NEXT: [[TMP2:%.*]] = load double*, double** [[PTR_ADDR]], align 85550// TCHECK1-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP2]], i64 05551// TCHECK1-64-NEXT: store double [[CONV]], double* [[ARRAYIDX]], align 85552// TCHECK1-64-NEXT: [[TMP3:%.*]] = load double*, double** [[PTR_ADDR]], align 85553// TCHECK1-64-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds double, double* [[TMP3]], i64 05554// TCHECK1-64-NEXT: [[TMP4:%.*]] = load double, double* [[ARRAYIDX1]], align 85555// TCHECK1-64-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+005556// TCHECK1-64-NEXT: store double [[INC]], double* [[ARRAYIDX1]], align 85557// TCHECK1-64-NEXT: ret void5558// TCHECK1-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l1425559// TCHECK1-64-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {5560// TCHECK1-64-NEXT: entry:5561// TCHECK1-64-NEXT: [[A_ADDR:%.*]] = alloca i64, align 85562// TCHECK1-64-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 85563// TCHECK1-64-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 85564// TCHECK1-64-NEXT: [[B2:%.*]] = alloca [10 x i32], align 45565// TCHECK1-64-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 85566// TCHECK1-64-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 85567// TCHECK1-64-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 85568// TCHECK1-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*5569// TCHECK1-64-NEXT: [[CONV1:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*5570// TCHECK1-64-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 85571// TCHECK1-64-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B2]] to i8*5572// TCHECK1-64-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*5573// TCHECK1-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 40, i1 false)5574// TCHECK1-64-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 45575// TCHECK1-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 15576// TCHECK1-64-NEXT: store i32 [[ADD]], i32* [[CONV]], align 45577// TCHECK1-64-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 15578// TCHECK1-64-NEXT: [[CONV3:%.*]] = sext i8 [[TMP4]] to i325579// TCHECK1-64-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 15580// TCHECK1-64-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i85581// TCHECK1-64-NEXT: store i8 [[CONV5]], i8* [[CONV1]], align 15582// TCHECK1-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B2]], i64 0, i64 25583// TCHECK1-64-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 45584// TCHECK1-64-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP5]], 15585// TCHECK1-64-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 45586// TCHECK1-64-NEXT: ret void5587// TCHECK1-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l1675588// TCHECK1-64-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {5589// TCHECK1-64-NEXT: entry:5590// TCHECK1-64-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 85591// TCHECK1-64-NEXT: [[B_ADDR:%.*]] = alloca i64, align 85592// TCHECK1-64-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 85593// TCHECK1-64-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 85594// TCHECK1-64-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 85595// TCHECK1-64-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 85596// TCHECK1-64-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 85597// TCHECK1-64-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 85598// TCHECK1-64-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 85599// TCHECK1-64-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 85600// TCHECK1-64-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 85601// TCHECK1-64-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 85602// TCHECK1-64-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 85603// TCHECK1-64-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 85604// TCHECK1-64-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*5605// TCHECK1-64-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 85606// TCHECK1-64-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 85607// TCHECK1-64-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 85608// TCHECK1-64-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave()5609// TCHECK1-64-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 85610// TCHECK1-64-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]]5611// TCHECK1-64-NEXT: [[VLA3:%.*]] = alloca i16, i64 [[TMP5]], align 25612// TCHECK1-64-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 85613// TCHECK1-64-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR1]], align 85614// TCHECK1-64-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]]5615// TCHECK1-64-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], 25616// TCHECK1-64-NEXT: [[TMP8:%.*]] = bitcast i16* [[VLA3]] to i8*5617// TCHECK1-64-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP3]] to i8*5618// TCHECK1-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 2 [[TMP8]], i8* align 2 [[TMP9]], i64 [[TMP7]], i1 false)5619// TCHECK1-64-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 45620// TCHECK1-64-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP10]] to double5621// TCHECK1-64-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+005622// TCHECK1-64-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 05623// TCHECK1-64-NEXT: store double [[ADD]], double* [[A]], align 85624// TCHECK1-64-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 05625// TCHECK1-64-NEXT: [[TMP11:%.*]] = load double, double* [[A5]], align 85626// TCHECK1-64-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+005627// TCHECK1-64-NEXT: store double [[INC]], double* [[A5]], align 85628// TCHECK1-64-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i165629// TCHECK1-64-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP2]]5630// TCHECK1-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA3]], i64 [[TMP12]]5631// TCHECK1-64-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 15632// TCHECK1-64-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 25633// TCHECK1-64-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 85634// TCHECK1-64-NEXT: call void @llvm.stackrestore(i8* [[TMP13]])5635// TCHECK1-64-NEXT: ret void5636// TCHECK1-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l1285637// TCHECK1-64-SAME: (i64 noundef [[A:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {5638// TCHECK1-64-NEXT: entry:5639// TCHECK1-64-NEXT: [[A_ADDR:%.*]] = alloca i64, align 85640// TCHECK1-64-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 85641// TCHECK1-64-NEXT: [[B1:%.*]] = alloca [10 x i32], align 45642// TCHECK1-64-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 85643// TCHECK1-64-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 85644// TCHECK1-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*5645// TCHECK1-64-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 85646// TCHECK1-64-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8*5647// TCHECK1-64-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*5648// TCHECK1-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 40, i1 false)5649// TCHECK1-64-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 45650// TCHECK1-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 15651// TCHECK1-64-NEXT: store i32 [[ADD]], i32* [[CONV]], align 45652// TCHECK1-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i64 0, i64 25653// TCHECK1-64-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 45654// TCHECK1-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], 15655// TCHECK1-64-NEXT: store i32 [[ADD2]], i32* [[ARRAYIDX]], align 45656// TCHECK1-64-NEXT: ret void5657// TCHECK2-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l635658// TCHECK2-32-SAME: (i32 noundef [[A:%.*]], i32* noundef [[P:%.*]], i32 noundef [[GA:%.*]]) #[[ATTR0:[0-9]+]] {5659// TCHECK2-32-NEXT: entry:5660// TCHECK2-32-NEXT: [[A_ADDR:%.*]] = alloca i32, align 45661// TCHECK2-32-NEXT: [[P_ADDR:%.*]] = alloca i32*, align 45662// TCHECK2-32-NEXT: [[GA_ADDR:%.*]] = alloca i32, align 45663// TCHECK2-32-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 45664// TCHECK2-32-NEXT: store i32* [[P]], i32** [[P_ADDR]], align 45665// TCHECK2-32-NEXT: store i32 [[GA]], i32* [[GA_ADDR]], align 45666// TCHECK2-32-NEXT: ret void5667// TCHECK2-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l705668// TCHECK2-32-SAME: (i32 noundef [[AA:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {5669// TCHECK2-32-NEXT: entry:5670// TCHECK2-32-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 45671// TCHECK2-32-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 45672// TCHECK2-32-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 45673// TCHECK2-32-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 45674// TCHECK2-32-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 45675// TCHECK2-32-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 45676// TCHECK2-32-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 45677// TCHECK2-32-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 45678// TCHECK2-32-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 45679// TCHECK2-32-NEXT: [[B5:%.*]] = alloca [10 x float], align 45680// TCHECK2-32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 45681// TCHECK2-32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 45682// TCHECK2-32-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 85683// TCHECK2-32-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 45684// TCHECK2-32-NEXT: [[__VLA_EXPR2:%.*]] = alloca i32, align 45685// TCHECK2-32-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 45686// TCHECK2-32-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 45687// TCHECK2-32-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 45688// TCHECK2-32-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 45689// TCHECK2-32-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 45690// TCHECK2-32-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 45691// TCHECK2-32-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 45692// TCHECK2-32-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 45693// TCHECK2-32-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 45694// TCHECK2-32-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 45695// TCHECK2-32-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*5696// TCHECK2-32-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 45697// TCHECK2-32-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 45698// TCHECK2-32-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 45699// TCHECK2-32-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 45700// TCHECK2-32-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 45701// TCHECK2-32-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 45702// TCHECK2-32-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 45703// TCHECK2-32-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 45704// TCHECK2-32-NEXT: [[TMP8:%.*]] = bitcast [10 x float]* [[B5]] to i8*5705// TCHECK2-32-NEXT: [[TMP9:%.*]] = bitcast [10 x float]* [[TMP0]] to i8*5706// TCHECK2-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i32 40, i1 false)5707// TCHECK2-32-NEXT: [[TMP10:%.*]] = call i8* @llvm.stacksave()5708// TCHECK2-32-NEXT: store i8* [[TMP10]], i8** [[SAVED_STACK]], align 45709// TCHECK2-32-NEXT: [[VLA6:%.*]] = alloca float, i32 [[TMP1]], align 45710// TCHECK2-32-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 45711// TCHECK2-32-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP1]], 45712// TCHECK2-32-NEXT: [[TMP12:%.*]] = bitcast float* [[VLA6]] to i8*5713// TCHECK2-32-NEXT: [[TMP13:%.*]] = bitcast float* [[TMP2]] to i8*5714// TCHECK2-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 [[TMP11]], i1 false)5715// TCHECK2-32-NEXT: [[TMP14:%.*]] = bitcast [5 x [10 x double]]* [[C7]] to i8*5716// TCHECK2-32-NEXT: [[TMP15:%.*]] = bitcast [5 x [10 x double]]* [[TMP3]] to i8*5717// TCHECK2-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 [[TMP14]], i8* align 8 [[TMP15]], i32 400, i1 false)5718// TCHECK2-32-NEXT: [[TMP16:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]]5719// TCHECK2-32-NEXT: [[VLA8:%.*]] = alloca double, i32 [[TMP16]], align 85720// TCHECK2-32-NEXT: store i32 [[TMP4]], i32* [[__VLA_EXPR1]], align 45721// TCHECK2-32-NEXT: store i32 [[TMP5]], i32* [[__VLA_EXPR2]], align 45722// TCHECK2-32-NEXT: [[TMP17:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]]5723// TCHECK2-32-NEXT: [[TMP18:%.*]] = mul nuw i32 [[TMP17]], 85724// TCHECK2-32-NEXT: [[TMP19:%.*]] = bitcast double* [[VLA8]] to i8*5725// TCHECK2-32-NEXT: [[TMP20:%.*]] = bitcast double* [[TMP6]] to i8*5726// TCHECK2-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 [[TMP19]], i8* align 8 [[TMP20]], i32 [[TMP18]], i1 false)5727// TCHECK2-32-NEXT: [[TMP21:%.*]] = bitcast %struct.TT* [[D9]] to i8*5728// TCHECK2-32-NEXT: [[TMP22:%.*]] = bitcast %struct.TT* [[TMP7]] to i8*5729// TCHECK2-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP21]], i8* align 4 [[TMP22]], i32 12, i1 false)5730// TCHECK2-32-NEXT: [[TMP23:%.*]] = load i16, i16* [[CONV]], align 25731// TCHECK2-32-NEXT: [[CONV10:%.*]] = sext i16 [[TMP23]] to i325732// TCHECK2-32-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV10]], 15733// TCHECK2-32-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD]] to i165734// TCHECK2-32-NEXT: store i16 [[CONV11]], i16* [[CONV]], align 25735// TCHECK2-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], i32 0, i32 25736// TCHECK2-32-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 45737// TCHECK2-32-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA6]], i32 35738// TCHECK2-32-NEXT: store float 1.000000e+00, float* [[ARRAYIDX12]], align 45739// TCHECK2-32-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], i32 0, i32 15740// TCHECK2-32-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i32 0, i32 25741// TCHECK2-32-NEXT: store double 1.000000e+00, double* [[ARRAYIDX14]], align 85742// TCHECK2-32-NEXT: [[TMP24:%.*]] = mul nsw i32 1, [[TMP5]]5743// TCHECK2-32-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[VLA8]], i32 [[TMP24]]5744// TCHECK2-32-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i32 35745// TCHECK2-32-NEXT: store double 1.000000e+00, double* [[ARRAYIDX16]], align 85746// TCHECK2-32-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 05747// TCHECK2-32-NEXT: store i64 1, i64* [[X]], align 45748// TCHECK2-32-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 15749// TCHECK2-32-NEXT: store i8 1, i8* [[Y]], align 45750// TCHECK2-32-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 45751// TCHECK2-32-NEXT: call void @llvm.stackrestore(i8* [[TMP25]])5752// TCHECK2-32-NEXT: ret void5753// TCHECK2-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l1115754// TCHECK2-32-SAME: (double* noundef [[PTR:%.*]], %struct.TT.0* noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR0]] {5755// TCHECK2-32-NEXT: entry:5756// TCHECK2-32-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 45757// TCHECK2-32-NEXT: [[E_ADDR:%.*]] = alloca %struct.TT.0*, align 45758// TCHECK2-32-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 45759// TCHECK2-32-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[E_ADDR]], align 45760// TCHECK2-32-NEXT: [[TMP0:%.*]] = load %struct.TT.0*, %struct.TT.0** [[E_ADDR]], align 45761// TCHECK2-32-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0:%.*]], %struct.TT.0* [[TMP0]], i32 0, i32 05762// TCHECK2-32-NEXT: [[TMP1:%.*]] = load i32, i32* [[X]], align 45763// TCHECK2-32-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double5764// TCHECK2-32-NEXT: [[TMP2:%.*]] = load double*, double** [[PTR_ADDR]], align 45765// TCHECK2-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP2]], i32 05766// TCHECK2-32-NEXT: store double [[CONV]], double* [[ARRAYIDX]], align 45767// TCHECK2-32-NEXT: [[TMP3:%.*]] = load double*, double** [[PTR_ADDR]], align 45768// TCHECK2-32-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds double, double* [[TMP3]], i32 05769// TCHECK2-32-NEXT: [[TMP4:%.*]] = load double, double* [[ARRAYIDX1]], align 45770// TCHECK2-32-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+005771// TCHECK2-32-NEXT: store double [[INC]], double* [[ARRAYIDX1]], align 45772// TCHECK2-32-NEXT: ret void5773// TCHECK2-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l1425774// TCHECK2-32-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {5775// TCHECK2-32-NEXT: entry:5776// TCHECK2-32-NEXT: [[A_ADDR:%.*]] = alloca i32, align 45777// TCHECK2-32-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 45778// TCHECK2-32-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 45779// TCHECK2-32-NEXT: [[B1:%.*]] = alloca [10 x i32], align 45780// TCHECK2-32-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 45781// TCHECK2-32-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 45782// TCHECK2-32-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 45783// TCHECK2-32-NEXT: [[CONV:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*5784// TCHECK2-32-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 45785// TCHECK2-32-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8*5786// TCHECK2-32-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*5787// TCHECK2-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 40, i1 false)5788// TCHECK2-32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 45789// TCHECK2-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 15790// TCHECK2-32-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 45791// TCHECK2-32-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 15792// TCHECK2-32-NEXT: [[CONV2:%.*]] = sext i8 [[TMP4]] to i325793// TCHECK2-32-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 15794// TCHECK2-32-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i85795// TCHECK2-32-NEXT: store i8 [[CONV4]], i8* [[CONV]], align 15796// TCHECK2-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i32 0, i32 25797// TCHECK2-32-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 45798// TCHECK2-32-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP5]], 15799// TCHECK2-32-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 45800// TCHECK2-32-NEXT: ret void5801// TCHECK2-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l1675802// TCHECK2-32-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {5803// TCHECK2-32-NEXT: entry:5804// TCHECK2-32-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 45805// TCHECK2-32-NEXT: [[B_ADDR:%.*]] = alloca i32, align 45806// TCHECK2-32-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 45807// TCHECK2-32-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 45808// TCHECK2-32-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 45809// TCHECK2-32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 45810// TCHECK2-32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 45811// TCHECK2-32-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 45812// TCHECK2-32-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 45813// TCHECK2-32-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 45814// TCHECK2-32-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 45815// TCHECK2-32-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 45816// TCHECK2-32-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 45817// TCHECK2-32-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 45818// TCHECK2-32-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 45819// TCHECK2-32-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 45820// TCHECK2-32-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 45821// TCHECK2-32-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave()5822// TCHECK2-32-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 45823// TCHECK2-32-NEXT: [[TMP5:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]5824// TCHECK2-32-NEXT: [[VLA3:%.*]] = alloca i16, i32 [[TMP5]], align 25825// TCHECK2-32-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 45826// TCHECK2-32-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 45827// TCHECK2-32-NEXT: [[TMP6:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]5828// TCHECK2-32-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP6]], 25829// TCHECK2-32-NEXT: [[TMP8:%.*]] = bitcast i16* [[VLA3]] to i8*5830// TCHECK2-32-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP3]] to i8*5831// TCHECK2-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 2 [[TMP8]], i8* align 2 [[TMP9]], i32 [[TMP7]], i1 false)5832// TCHECK2-32-NEXT: [[TMP10:%.*]] = load i32, i32* [[B_ADDR]], align 45833// TCHECK2-32-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP10]] to double5834// TCHECK2-32-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+005835// TCHECK2-32-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 05836// TCHECK2-32-NEXT: store double [[ADD]], double* [[A]], align 45837// TCHECK2-32-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 05838// TCHECK2-32-NEXT: [[TMP11:%.*]] = load double, double* [[A4]], align 45839// TCHECK2-32-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+005840// TCHECK2-32-NEXT: store double [[INC]], double* [[A4]], align 45841// TCHECK2-32-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i165842// TCHECK2-32-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP2]]5843// TCHECK2-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA3]], i32 [[TMP12]]5844// TCHECK2-32-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 15845// TCHECK2-32-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 25846// TCHECK2-32-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 45847// TCHECK2-32-NEXT: call void @llvm.stackrestore(i8* [[TMP13]])5848// TCHECK2-32-NEXT: ret void5849// TCHECK2-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l1285850// TCHECK2-32-SAME: (i32 noundef [[A:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {5851// TCHECK2-32-NEXT: entry:5852// TCHECK2-32-NEXT: [[A_ADDR:%.*]] = alloca i32, align 45853// TCHECK2-32-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 45854// TCHECK2-32-NEXT: [[B1:%.*]] = alloca [10 x i32], align 45855// TCHECK2-32-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 45856// TCHECK2-32-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 45857// TCHECK2-32-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 45858// TCHECK2-32-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8*5859// TCHECK2-32-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*5860// TCHECK2-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 40, i1 false)5861// TCHECK2-32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 45862// TCHECK2-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 15863// TCHECK2-32-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 45864// TCHECK2-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i32 0, i32 25865// TCHECK2-32-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 45866// TCHECK2-32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], 15867// TCHECK2-32-NEXT: store i32 [[ADD2]], i32* [[ARRAYIDX]], align 45868// TCHECK2-32-NEXT: ret void5869// TCHECK3-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l635870// TCHECK3-32-SAME: (i32 noundef [[A:%.*]], i32* noundef [[P:%.*]], i32 noundef [[GA:%.*]]) #[[ATTR0:[0-9]+]] {5871// TCHECK3-32-NEXT: entry:5872// TCHECK3-32-NEXT: [[A_ADDR:%.*]] = alloca i32, align 45873// TCHECK3-32-NEXT: [[P_ADDR:%.*]] = alloca i32*, align 45874// TCHECK3-32-NEXT: [[GA_ADDR:%.*]] = alloca i32, align 45875// TCHECK3-32-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 45876// TCHECK3-32-NEXT: store i32* [[P]], i32** [[P_ADDR]], align 45877// TCHECK3-32-NEXT: store i32 [[GA]], i32* [[GA_ADDR]], align 45878// TCHECK3-32-NEXT: ret void5879// TCHECK3-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l705880// TCHECK3-32-SAME: (i32 noundef [[AA:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {5881// TCHECK3-32-NEXT: entry:5882// TCHECK3-32-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 45883// TCHECK3-32-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 45884// TCHECK3-32-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 45885// TCHECK3-32-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 45886// TCHECK3-32-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 45887// TCHECK3-32-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 45888// TCHECK3-32-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 45889// TCHECK3-32-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 45890// TCHECK3-32-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 45891// TCHECK3-32-NEXT: [[B5:%.*]] = alloca [10 x float], align 45892// TCHECK3-32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 45893// TCHECK3-32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 45894// TCHECK3-32-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 85895// TCHECK3-32-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 45896// TCHECK3-32-NEXT: [[__VLA_EXPR2:%.*]] = alloca i32, align 45897// TCHECK3-32-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 45898// TCHECK3-32-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 45899// TCHECK3-32-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 45900// TCHECK3-32-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 45901// TCHECK3-32-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 45902// TCHECK3-32-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 45903// TCHECK3-32-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 45904// TCHECK3-32-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 45905// TCHECK3-32-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 45906// TCHECK3-32-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 45907// TCHECK3-32-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*5908// TCHECK3-32-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 45909// TCHECK3-32-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 45910// TCHECK3-32-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 45911// TCHECK3-32-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 45912// TCHECK3-32-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 45913// TCHECK3-32-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 45914// TCHECK3-32-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 45915// TCHECK3-32-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 45916// TCHECK3-32-NEXT: [[TMP8:%.*]] = bitcast [10 x float]* [[B5]] to i8*5917// TCHECK3-32-NEXT: [[TMP9:%.*]] = bitcast [10 x float]* [[TMP0]] to i8*5918// TCHECK3-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i32 40, i1 false)5919// TCHECK3-32-NEXT: [[TMP10:%.*]] = call i8* @llvm.stacksave()5920// TCHECK3-32-NEXT: store i8* [[TMP10]], i8** [[SAVED_STACK]], align 45921// TCHECK3-32-NEXT: [[VLA6:%.*]] = alloca float, i32 [[TMP1]], align 45922// TCHECK3-32-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 45923// TCHECK3-32-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP1]], 45924// TCHECK3-32-NEXT: [[TMP12:%.*]] = bitcast float* [[VLA6]] to i8*5925// TCHECK3-32-NEXT: [[TMP13:%.*]] = bitcast float* [[TMP2]] to i8*5926// TCHECK3-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 [[TMP11]], i1 false)5927// TCHECK3-32-NEXT: [[TMP14:%.*]] = bitcast [5 x [10 x double]]* [[C7]] to i8*5928// TCHECK3-32-NEXT: [[TMP15:%.*]] = bitcast [5 x [10 x double]]* [[TMP3]] to i8*5929// TCHECK3-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 [[TMP14]], i8* align 8 [[TMP15]], i32 400, i1 false)5930// TCHECK3-32-NEXT: [[TMP16:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]]5931// TCHECK3-32-NEXT: [[VLA8:%.*]] = alloca double, i32 [[TMP16]], align 85932// TCHECK3-32-NEXT: store i32 [[TMP4]], i32* [[__VLA_EXPR1]], align 45933// TCHECK3-32-NEXT: store i32 [[TMP5]], i32* [[__VLA_EXPR2]], align 45934// TCHECK3-32-NEXT: [[TMP17:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]]5935// TCHECK3-32-NEXT: [[TMP18:%.*]] = mul nuw i32 [[TMP17]], 85936// TCHECK3-32-NEXT: [[TMP19:%.*]] = bitcast double* [[VLA8]] to i8*5937// TCHECK3-32-NEXT: [[TMP20:%.*]] = bitcast double* [[TMP6]] to i8*5938// TCHECK3-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 [[TMP19]], i8* align 8 [[TMP20]], i32 [[TMP18]], i1 false)5939// TCHECK3-32-NEXT: [[TMP21:%.*]] = bitcast %struct.TT* [[D9]] to i8*5940// TCHECK3-32-NEXT: [[TMP22:%.*]] = bitcast %struct.TT* [[TMP7]] to i8*5941// TCHECK3-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP21]], i8* align 4 [[TMP22]], i32 12, i1 false)5942// TCHECK3-32-NEXT: [[TMP23:%.*]] = load i16, i16* [[CONV]], align 25943// TCHECK3-32-NEXT: [[CONV10:%.*]] = sext i16 [[TMP23]] to i325944// TCHECK3-32-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV10]], 15945// TCHECK3-32-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD]] to i165946// TCHECK3-32-NEXT: store i16 [[CONV11]], i16* [[CONV]], align 25947// TCHECK3-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], i32 0, i32 25948// TCHECK3-32-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 45949// TCHECK3-32-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA6]], i32 35950// TCHECK3-32-NEXT: store float 1.000000e+00, float* [[ARRAYIDX12]], align 45951// TCHECK3-32-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], i32 0, i32 15952// TCHECK3-32-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i32 0, i32 25953// TCHECK3-32-NEXT: store double 1.000000e+00, double* [[ARRAYIDX14]], align 85954// TCHECK3-32-NEXT: [[TMP24:%.*]] = mul nsw i32 1, [[TMP5]]5955// TCHECK3-32-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[VLA8]], i32 [[TMP24]]5956// TCHECK3-32-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i32 35957// TCHECK3-32-NEXT: store double 1.000000e+00, double* [[ARRAYIDX16]], align 85958// TCHECK3-32-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 05959// TCHECK3-32-NEXT: store i64 1, i64* [[X]], align 45960// TCHECK3-32-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 15961// TCHECK3-32-NEXT: store i8 1, i8* [[Y]], align 45962// TCHECK3-32-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 45963// TCHECK3-32-NEXT: call void @llvm.stackrestore(i8* [[TMP25]])5964// TCHECK3-32-NEXT: ret void5965// TCHECK3-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l1115966// TCHECK3-32-SAME: (double* noundef [[PTR:%.*]], %struct.TT.0* noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR0]] {5967// TCHECK3-32-NEXT: entry:5968// TCHECK3-32-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 45969// TCHECK3-32-NEXT: [[E_ADDR:%.*]] = alloca %struct.TT.0*, align 45970// TCHECK3-32-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 45971// TCHECK3-32-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[E_ADDR]], align 45972// TCHECK3-32-NEXT: [[TMP0:%.*]] = load %struct.TT.0*, %struct.TT.0** [[E_ADDR]], align 45973// TCHECK3-32-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0:%.*]], %struct.TT.0* [[TMP0]], i32 0, i32 05974// TCHECK3-32-NEXT: [[TMP1:%.*]] = load i32, i32* [[X]], align 45975// TCHECK3-32-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double5976// TCHECK3-32-NEXT: [[TMP2:%.*]] = load double*, double** [[PTR_ADDR]], align 45977// TCHECK3-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP2]], i32 05978// TCHECK3-32-NEXT: store double [[CONV]], double* [[ARRAYIDX]], align 45979// TCHECK3-32-NEXT: [[TMP3:%.*]] = load double*, double** [[PTR_ADDR]], align 45980// TCHECK3-32-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds double, double* [[TMP3]], i32 05981// TCHECK3-32-NEXT: [[TMP4:%.*]] = load double, double* [[ARRAYIDX1]], align 45982// TCHECK3-32-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+005983// TCHECK3-32-NEXT: store double [[INC]], double* [[ARRAYIDX1]], align 45984// TCHECK3-32-NEXT: ret void5985// TCHECK3-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l1425986// TCHECK3-32-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {5987// TCHECK3-32-NEXT: entry:5988// TCHECK3-32-NEXT: [[A_ADDR:%.*]] = alloca i32, align 45989// TCHECK3-32-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 45990// TCHECK3-32-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 45991// TCHECK3-32-NEXT: [[B1:%.*]] = alloca [10 x i32], align 45992// TCHECK3-32-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 45993// TCHECK3-32-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 45994// TCHECK3-32-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 45995// TCHECK3-32-NEXT: [[CONV:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*5996// TCHECK3-32-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 45997// TCHECK3-32-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8*5998// TCHECK3-32-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*5999// TCHECK3-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 40, i1 false)6000// TCHECK3-32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 46001// TCHECK3-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 16002// TCHECK3-32-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 46003// TCHECK3-32-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 16004// TCHECK3-32-NEXT: [[CONV2:%.*]] = sext i8 [[TMP4]] to i326005// TCHECK3-32-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 16006// TCHECK3-32-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i86007// TCHECK3-32-NEXT: store i8 [[CONV4]], i8* [[CONV]], align 16008// TCHECK3-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i32 0, i32 26009// TCHECK3-32-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 46010// TCHECK3-32-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP5]], 16011// TCHECK3-32-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 46012// TCHECK3-32-NEXT: ret void6013// TCHECK3-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l1676014// TCHECK3-32-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {6015// TCHECK3-32-NEXT: entry:6016// TCHECK3-32-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 46017// TCHECK3-32-NEXT: [[B_ADDR:%.*]] = alloca i32, align 46018// TCHECK3-32-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 46019// TCHECK3-32-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 46020// TCHECK3-32-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 46021// TCHECK3-32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 46022// TCHECK3-32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 46023// TCHECK3-32-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 46024// TCHECK3-32-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 46025// TCHECK3-32-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 46026// TCHECK3-32-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 46027// TCHECK3-32-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 46028// TCHECK3-32-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 46029// TCHECK3-32-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 46030// TCHECK3-32-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 46031// TCHECK3-32-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 46032// TCHECK3-32-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 46033// TCHECK3-32-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave()6034// TCHECK3-32-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 46035// TCHECK3-32-NEXT: [[TMP5:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]6036// TCHECK3-32-NEXT: [[VLA3:%.*]] = alloca i16, i32 [[TMP5]], align 26037// TCHECK3-32-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 46038// TCHECK3-32-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 46039// TCHECK3-32-NEXT: [[TMP6:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]6040// TCHECK3-32-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP6]], 26041// TCHECK3-32-NEXT: [[TMP8:%.*]] = bitcast i16* [[VLA3]] to i8*6042// TCHECK3-32-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP3]] to i8*6043// TCHECK3-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 2 [[TMP8]], i8* align 2 [[TMP9]], i32 [[TMP7]], i1 false)6044// TCHECK3-32-NEXT: [[TMP10:%.*]] = load i32, i32* [[B_ADDR]], align 46045// TCHECK3-32-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP10]] to double6046// TCHECK3-32-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+006047// TCHECK3-32-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 06048// TCHECK3-32-NEXT: store double [[ADD]], double* [[A]], align 46049// TCHECK3-32-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 06050// TCHECK3-32-NEXT: [[TMP11:%.*]] = load double, double* [[A4]], align 46051// TCHECK3-32-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+006052// TCHECK3-32-NEXT: store double [[INC]], double* [[A4]], align 46053// TCHECK3-32-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i166054// TCHECK3-32-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP2]]6055// TCHECK3-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA3]], i32 [[TMP12]]6056// TCHECK3-32-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 16057// TCHECK3-32-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 26058// TCHECK3-32-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 46059// TCHECK3-32-NEXT: call void @llvm.stackrestore(i8* [[TMP13]])6060// TCHECK3-32-NEXT: ret void6061// TCHECK3-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l1286062// TCHECK3-32-SAME: (i32 noundef [[A:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {6063// TCHECK3-32-NEXT: entry:6064// TCHECK3-32-NEXT: [[A_ADDR:%.*]] = alloca i32, align 46065// TCHECK3-32-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 46066// TCHECK3-32-NEXT: [[B1:%.*]] = alloca [10 x i32], align 46067// TCHECK3-32-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 46068// TCHECK3-32-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 46069// TCHECK3-32-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 46070// TCHECK3-32-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8*6071// TCHECK3-32-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*6072// TCHECK3-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 40, i1 false)6073// TCHECK3-32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 46074// TCHECK3-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 16075// TCHECK3-32-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 46076// TCHECK3-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i32 0, i32 26077// TCHECK3-32-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 46078// TCHECK3-32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], 16079// TCHECK3-32-NEXT: store i32 [[ADD2]], i32* [[ARRAYIDX]], align 46080// TCHECK3-32-NEXT: ret void6081// CHECK0-LABEL: define {{[^@]+}}@_Z3fooiPd6082// CHECK0-SAME: (i32 noundef signext [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {6083// CHECK0-NEXT: entry:6084// CHECK0-NEXT: [[N_ADDR:%.*]] = alloca i32, align 46085// CHECK0-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 86086// CHECK0-NEXT: [[A:%.*]] = alloca i32, align 46087// CHECK0-NEXT: [[AA:%.*]] = alloca i16, align 26088// CHECK0-NEXT: [[B:%.*]] = alloca [10 x float], align 46089// CHECK0-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 86090// CHECK0-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 86091// CHECK0-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 86092// CHECK0-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 86093// CHECK0-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 86094// CHECK0-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 46095// CHECK0-NEXT: [[P:%.*]] = alloca ptr, align 646096// CHECK0-NEXT: [[A_CASTED:%.*]] = alloca i64, align 86097// CHECK0-NEXT: [[GA_CASTED:%.*]] = alloca i64, align 86098// CHECK0-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 86099// CHECK0-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 86100// CHECK0-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 86101// CHECK0-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 86102// CHECK0-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 86103// CHECK0-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [9 x ptr], align 86104// CHECK0-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [9 x ptr], align 86105// CHECK0-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [9 x ptr], align 86106// CHECK0-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 86107// CHECK0-NEXT: [[KERNEL_ARGS5:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 86108// CHECK0-NEXT: [[DOTOFFLOAD_BASEPTRS8:%.*]] = alloca [2 x ptr], align 86109// CHECK0-NEXT: [[DOTOFFLOAD_PTRS9:%.*]] = alloca [2 x ptr], align 86110// CHECK0-NEXT: [[DOTOFFLOAD_MAPPERS10:%.*]] = alloca [2 x ptr], align 86111// CHECK0-NEXT: [[KERNEL_ARGS11:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 86112// CHECK0-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 46113// CHECK0-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 86114// CHECK0-NEXT: store i32 0, ptr [[A]], align 46115// CHECK0-NEXT: store i16 0, ptr [[AA]], align 26116// CHECK0-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 46117// CHECK0-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i646118// CHECK0-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()6119// CHECK0-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 86120// CHECK0-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 46121// CHECK0-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 86122// CHECK0-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 46123// CHECK0-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i646124// CHECK0-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]6125// CHECK0-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 86126// CHECK0-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 86127// CHECK0-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 06128// CHECK0-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 46129// CHECK0-NEXT: store i32 [[TMP6]], ptr [[X]], align 46130// CHECK0-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 16131// CHECK0-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 46132// CHECK0-NEXT: store i32 [[TMP7]], ptr [[Y]], align 46133// CHECK0-NEXT: store ptr [[A]], ptr [[P]], align 646134// CHECK0-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 46135// CHECK0-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 46136// CHECK0-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 86137// CHECK0-NEXT: [[TMP10:%.*]] = load ptr, ptr [[P]], align 646138// CHECK0-NEXT: [[TMP11:%.*]] = load i32, ptr @ga, align 46139// CHECK0-NEXT: store i32 [[TMP11]], ptr [[GA_CASTED]], align 46140// CHECK0-NEXT: [[TMP12:%.*]] = load i64, ptr [[GA_CASTED]], align 86141// CHECK0-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 06142// CHECK0-NEXT: store i64 [[TMP9]], ptr [[TMP13]], align 86143// CHECK0-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 06144// CHECK0-NEXT: store i64 [[TMP9]], ptr [[TMP14]], align 86145// CHECK0-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 06146// CHECK0-NEXT: store ptr null, ptr [[TMP15]], align 86147// CHECK0-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 16148// CHECK0-NEXT: store ptr [[TMP10]], ptr [[TMP16]], align 86149// CHECK0-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 16150// CHECK0-NEXT: store ptr [[TMP10]], ptr [[TMP17]], align 86151// CHECK0-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 16152// CHECK0-NEXT: store ptr null, ptr [[TMP18]], align 86153// CHECK0-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 26154// CHECK0-NEXT: store i64 [[TMP12]], ptr [[TMP19]], align 86155// CHECK0-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 26156// CHECK0-NEXT: store i64 [[TMP12]], ptr [[TMP20]], align 86157// CHECK0-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 26158// CHECK0-NEXT: store ptr null, ptr [[TMP21]], align 86159// CHECK0-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 06160// CHECK0-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 06161// CHECK0-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 06162// CHECK0-NEXT: store i32 3, ptr [[TMP24]], align 46163// CHECK0-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 16164// CHECK0-NEXT: store i32 3, ptr [[TMP25]], align 46165// CHECK0-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 26166// CHECK0-NEXT: store ptr [[TMP22]], ptr [[TMP26]], align 86167// CHECK0-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 36168// CHECK0-NEXT: store ptr [[TMP23]], ptr [[TMP27]], align 86169// CHECK0-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 46170// CHECK0-NEXT: store ptr @.offload_sizes, ptr [[TMP28]], align 86171// CHECK0-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 56172// CHECK0-NEXT: store ptr @.offload_maptypes, ptr [[TMP29]], align 86173// CHECK0-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 66174// CHECK0-NEXT: store ptr null, ptr [[TMP30]], align 86175// CHECK0-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 76176// CHECK0-NEXT: store ptr null, ptr [[TMP31]], align 86177// CHECK0-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 86178// CHECK0-NEXT: store i64 0, ptr [[TMP32]], align 86179// CHECK0-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 96180// CHECK0-NEXT: store i64 0, ptr [[TMP33]], align 86181// CHECK0-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 106182// CHECK0-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP34]], align 46183// CHECK0-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 116184// CHECK0-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP35]], align 46185// CHECK0-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 126186// CHECK0-NEXT: store i32 0, ptr [[TMP36]], align 46187// CHECK0-NEXT: [[TMP37:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63.region_id, ptr [[KERNEL_ARGS]])6188// CHECK0-NEXT: [[TMP38:%.*]] = icmp ne i32 [[TMP37]], 06189// CHECK0-NEXT: br i1 [[TMP38]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]6190// CHECK0: omp_offload.failed:6191// CHECK0-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63(i64 [[TMP9]], ptr [[TMP10]], i64 [[TMP12]]) #[[ATTR3:[0-9]+]]6192// CHECK0-NEXT: br label [[OMP_OFFLOAD_CONT]]6193// CHECK0: omp_offload.cont:6194// CHECK0-NEXT: [[TMP39:%.*]] = load i16, ptr [[AA]], align 26195// CHECK0-NEXT: store i16 [[TMP39]], ptr [[AA_CASTED]], align 26196// CHECK0-NEXT: [[TMP40:%.*]] = load i64, ptr [[AA_CASTED]], align 86197// CHECK0-NEXT: [[TMP41:%.*]] = mul nuw i64 [[TMP1]], 46198// CHECK0-NEXT: [[TMP42:%.*]] = mul nuw i64 5, [[TMP4]]6199// CHECK0-NEXT: [[TMP43:%.*]] = mul nuw i64 [[TMP42]], 86200// CHECK0-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.1, i64 72, i1 false)6201// CHECK0-NEXT: [[TMP44:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 06202// CHECK0-NEXT: store i64 [[TMP40]], ptr [[TMP44]], align 86203// CHECK0-NEXT: [[TMP45:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 06204// CHECK0-NEXT: store i64 [[TMP40]], ptr [[TMP45]], align 86205// CHECK0-NEXT: [[TMP46:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i64 0, i64 06206// CHECK0-NEXT: store ptr null, ptr [[TMP46]], align 86207// CHECK0-NEXT: [[TMP47:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 16208// CHECK0-NEXT: store ptr [[B]], ptr [[TMP47]], align 86209// CHECK0-NEXT: [[TMP48:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 16210// CHECK0-NEXT: store ptr [[B]], ptr [[TMP48]], align 86211// CHECK0-NEXT: [[TMP49:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i64 0, i64 16212// CHECK0-NEXT: store ptr null, ptr [[TMP49]], align 86213// CHECK0-NEXT: [[TMP50:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 26214// CHECK0-NEXT: store i64 [[TMP1]], ptr [[TMP50]], align 86215// CHECK0-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 26216// CHECK0-NEXT: store i64 [[TMP1]], ptr [[TMP51]], align 86217// CHECK0-NEXT: [[TMP52:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i64 0, i64 26218// CHECK0-NEXT: store ptr null, ptr [[TMP52]], align 86219// CHECK0-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 36220// CHECK0-NEXT: store ptr [[VLA]], ptr [[TMP53]], align 86221// CHECK0-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 36222// CHECK0-NEXT: store ptr [[VLA]], ptr [[TMP54]], align 86223// CHECK0-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 36224// CHECK0-NEXT: store i64 [[TMP41]], ptr [[TMP55]], align 86225// CHECK0-NEXT: [[TMP56:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i64 0, i64 36226// CHECK0-NEXT: store ptr null, ptr [[TMP56]], align 86227// CHECK0-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 46228// CHECK0-NEXT: store ptr [[C]], ptr [[TMP57]], align 86229// CHECK0-NEXT: [[TMP58:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 46230// CHECK0-NEXT: store ptr [[C]], ptr [[TMP58]], align 86231// CHECK0-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i64 0, i64 46232// CHECK0-NEXT: store ptr null, ptr [[TMP59]], align 86233// CHECK0-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 56234// CHECK0-NEXT: store i64 5, ptr [[TMP60]], align 86235// CHECK0-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 56236// CHECK0-NEXT: store i64 5, ptr [[TMP61]], align 86237// CHECK0-NEXT: [[TMP62:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i64 0, i64 56238// CHECK0-NEXT: store ptr null, ptr [[TMP62]], align 86239// CHECK0-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 66240// CHECK0-NEXT: store i64 [[TMP4]], ptr [[TMP63]], align 86241// CHECK0-NEXT: [[TMP64:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 66242// CHECK0-NEXT: store i64 [[TMP4]], ptr [[TMP64]], align 86243// CHECK0-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i64 0, i64 66244// CHECK0-NEXT: store ptr null, ptr [[TMP65]], align 86245// CHECK0-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 76246// CHECK0-NEXT: store ptr [[VLA1]], ptr [[TMP66]], align 86247// CHECK0-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 76248// CHECK0-NEXT: store ptr [[VLA1]], ptr [[TMP67]], align 86249// CHECK0-NEXT: [[TMP68:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 76250// CHECK0-NEXT: store i64 [[TMP43]], ptr [[TMP68]], align 86251// CHECK0-NEXT: [[TMP69:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i64 0, i64 76252// CHECK0-NEXT: store ptr null, ptr [[TMP69]], align 86253// CHECK0-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 86254// CHECK0-NEXT: store ptr [[D]], ptr [[TMP70]], align 86255// CHECK0-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 86256// CHECK0-NEXT: store ptr [[D]], ptr [[TMP71]], align 86257// CHECK0-NEXT: [[TMP72:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i64 0, i64 86258// CHECK0-NEXT: store ptr null, ptr [[TMP72]], align 86259// CHECK0-NEXT: [[TMP73:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 06260// CHECK0-NEXT: [[TMP74:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 06261// CHECK0-NEXT: [[TMP75:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 06262// CHECK0-NEXT: [[TMP76:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 06263// CHECK0-NEXT: store i32 3, ptr [[TMP76]], align 46264// CHECK0-NEXT: [[TMP77:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 16265// CHECK0-NEXT: store i32 9, ptr [[TMP77]], align 46266// CHECK0-NEXT: [[TMP78:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 26267// CHECK0-NEXT: store ptr [[TMP73]], ptr [[TMP78]], align 86268// CHECK0-NEXT: [[TMP79:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 36269// CHECK0-NEXT: store ptr [[TMP74]], ptr [[TMP79]], align 86270// CHECK0-NEXT: [[TMP80:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 46271// CHECK0-NEXT: store ptr [[TMP75]], ptr [[TMP80]], align 86272// CHECK0-NEXT: [[TMP81:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 56273// CHECK0-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP81]], align 86274// CHECK0-NEXT: [[TMP82:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 66275// CHECK0-NEXT: store ptr null, ptr [[TMP82]], align 86276// CHECK0-NEXT: [[TMP83:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 76277// CHECK0-NEXT: store ptr null, ptr [[TMP83]], align 86278// CHECK0-NEXT: [[TMP84:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 86279// CHECK0-NEXT: store i64 0, ptr [[TMP84]], align 86280// CHECK0-NEXT: [[TMP85:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 96281// CHECK0-NEXT: store i64 0, ptr [[TMP85]], align 86282// CHECK0-NEXT: [[TMP86:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 106283// CHECK0-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP86]], align 46284// CHECK0-NEXT: [[TMP87:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 116285// CHECK0-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP87]], align 46286// CHECK0-NEXT: [[TMP88:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 126287// CHECK0-NEXT: store i32 0, ptr [[TMP88]], align 46288// CHECK0-NEXT: [[TMP89:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70.region_id, ptr [[KERNEL_ARGS5]])6289// CHECK0-NEXT: [[TMP90:%.*]] = icmp ne i32 [[TMP89]], 06290// CHECK0-NEXT: br i1 [[TMP90]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]]6291// CHECK0: omp_offload.failed6:6292// CHECK0-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70(i64 [[TMP40]], ptr [[B]], i64 [[TMP1]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP4]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]]6293// CHECK0-NEXT: br label [[OMP_OFFLOAD_CONT7]]6294// CHECK0: omp_offload.cont7:6295// CHECK0-NEXT: [[TMP91:%.*]] = load ptr, ptr [[PTR_ADDR]], align 86296// CHECK0-NEXT: [[TMP92:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 06297// CHECK0-NEXT: store ptr [[TMP91]], ptr [[TMP92]], align 86298// CHECK0-NEXT: [[TMP93:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS9]], i32 0, i32 06299// CHECK0-NEXT: store ptr [[TMP91]], ptr [[TMP93]], align 86300// CHECK0-NEXT: [[TMP94:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS10]], i64 0, i64 06301// CHECK0-NEXT: store ptr null, ptr [[TMP94]], align 86302// CHECK0-NEXT: [[TMP95:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 16303// CHECK0-NEXT: store ptr [[E]], ptr [[TMP95]], align 86304// CHECK0-NEXT: [[TMP96:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS9]], i32 0, i32 16305// CHECK0-NEXT: store ptr [[E]], ptr [[TMP96]], align 86306// CHECK0-NEXT: [[TMP97:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS10]], i64 0, i64 16307// CHECK0-NEXT: store ptr null, ptr [[TMP97]], align 86308// CHECK0-NEXT: [[TMP98:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 06309// CHECK0-NEXT: [[TMP99:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS9]], i32 0, i32 06310// CHECK0-NEXT: [[TMP100:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 06311// CHECK0-NEXT: store i32 3, ptr [[TMP100]], align 46312// CHECK0-NEXT: [[TMP101:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 16313// CHECK0-NEXT: store i32 2, ptr [[TMP101]], align 46314// CHECK0-NEXT: [[TMP102:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 26315// CHECK0-NEXT: store ptr [[TMP98]], ptr [[TMP102]], align 86316// CHECK0-NEXT: [[TMP103:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 36317// CHECK0-NEXT: store ptr [[TMP99]], ptr [[TMP103]], align 86318// CHECK0-NEXT: [[TMP104:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 46319// CHECK0-NEXT: store ptr @.offload_sizes.3, ptr [[TMP104]], align 86320// CHECK0-NEXT: [[TMP105:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 56321// CHECK0-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP105]], align 86322// CHECK0-NEXT: [[TMP106:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 66323// CHECK0-NEXT: store ptr null, ptr [[TMP106]], align 86324// CHECK0-NEXT: [[TMP107:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 76325// CHECK0-NEXT: store ptr null, ptr [[TMP107]], align 86326// CHECK0-NEXT: [[TMP108:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 86327// CHECK0-NEXT: store i64 0, ptr [[TMP108]], align 86328// CHECK0-NEXT: [[TMP109:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 96329// CHECK0-NEXT: store i64 0, ptr [[TMP109]], align 86330// CHECK0-NEXT: [[TMP110:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 106331// CHECK0-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP110]], align 46332// CHECK0-NEXT: [[TMP111:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 116333// CHECK0-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP111]], align 46334// CHECK0-NEXT: [[TMP112:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 126335// CHECK0-NEXT: store i32 0, ptr [[TMP112]], align 46336// CHECK0-NEXT: [[TMP113:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111.region_id, ptr [[KERNEL_ARGS11]])6337// CHECK0-NEXT: [[TMP114:%.*]] = icmp ne i32 [[TMP113]], 06338// CHECK0-NEXT: br i1 [[TMP114]], label [[OMP_OFFLOAD_FAILED12:%.*]], label [[OMP_OFFLOAD_CONT13:%.*]]6339// CHECK0: omp_offload.failed12:6340// CHECK0-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111(ptr [[TMP91]], ptr [[E]]) #[[ATTR3]]6341// CHECK0-NEXT: br label [[OMP_OFFLOAD_CONT13]]6342// CHECK0: omp_offload.cont13:6343// CHECK0-NEXT: [[TMP115:%.*]] = load i32, ptr [[A]], align 46344// CHECK0-NEXT: [[TMP116:%.*]] = load ptr, ptr [[SAVED_STACK]], align 86345// CHECK0-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP116]])6346// CHECK0-NEXT: ret i32 [[TMP115]]6347//6348//6349// CHECK0-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l636350// CHECK0-SAME: (i64 noundef [[A:%.*]], ptr noundef [[P:%.*]], i64 noundef [[GA:%.*]]) #[[ATTR2:[0-9]+]] {6351// CHECK0-NEXT: entry:6352// CHECK0-NEXT: [[A_ADDR:%.*]] = alloca i64, align 86353// CHECK0-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 86354// CHECK0-NEXT: [[GA_ADDR:%.*]] = alloca i64, align 86355// CHECK0-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 86356// CHECK0-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 86357// CHECK0-NEXT: store i64 [[GA]], ptr [[GA_ADDR]], align 86358// CHECK0-NEXT: ret void6359//6360//6361// CHECK0-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l706362// CHECK0-SAME: (i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {6363// CHECK0-NEXT: entry:6364// CHECK0-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 86365// CHECK0-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 86366// CHECK0-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 86367// CHECK0-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 86368// CHECK0-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 86369// CHECK0-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 86370// CHECK0-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 86371// CHECK0-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 86372// CHECK0-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 86373// CHECK0-NEXT: [[B5:%.*]] = alloca [10 x float], align 46374// CHECK0-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 86375// CHECK0-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 86376// CHECK0-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 86377// CHECK0-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 86378// CHECK0-NEXT: [[__VLA_EXPR2:%.*]] = alloca i64, align 86379// CHECK0-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 86380// CHECK0-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 86381// CHECK0-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 86382// CHECK0-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 86383// CHECK0-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 86384// CHECK0-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 86385// CHECK0-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 86386// CHECK0-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 86387// CHECK0-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 86388// CHECK0-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 86389// CHECK0-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 86390// CHECK0-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 86391// CHECK0-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 86392// CHECK0-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 86393// CHECK0-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 86394// CHECK0-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 86395// CHECK0-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 86396// CHECK0-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 86397// CHECK0-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B5]], ptr align 4 [[TMP0]], i64 40, i1 false)6398// CHECK0-NEXT: [[TMP8:%.*]] = call ptr @llvm.stacksave.p0()6399// CHECK0-NEXT: store ptr [[TMP8]], ptr [[SAVED_STACK]], align 86400// CHECK0-NEXT: [[VLA6:%.*]] = alloca float, i64 [[TMP1]], align 46401// CHECK0-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 86402// CHECK0-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP1]], 46403// CHECK0-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VLA6]], ptr align 4 [[TMP2]], i64 [[TMP9]], i1 false)6404// CHECK0-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[C7]], ptr align 8 [[TMP3]], i64 400, i1 false)6405// CHECK0-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]]6406// CHECK0-NEXT: [[VLA8:%.*]] = alloca double, i64 [[TMP10]], align 86407// CHECK0-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 86408// CHECK0-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR2]], align 86409// CHECK0-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]]6410// CHECK0-NEXT: [[TMP12:%.*]] = mul nuw i64 [[TMP11]], 86411// CHECK0-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[VLA8]], ptr align 8 [[TMP6]], i64 [[TMP12]], i1 false)6412// CHECK0-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[D9]], ptr align 8 [[TMP7]], i64 16, i1 false)6413// CHECK0-NEXT: [[TMP13:%.*]] = load i16, ptr [[AA_ADDR]], align 26414// CHECK0-NEXT: [[CONV:%.*]] = sext i16 [[TMP13]] to i326415// CHECK0-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 16416// CHECK0-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i166417// CHECK0-NEXT: store i16 [[CONV10]], ptr [[AA_ADDR]], align 26418// CHECK0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B5]], i64 0, i64 26419// CHECK0-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX]], align 46420// CHECK0-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, ptr [[VLA6]], i64 36421// CHECK0-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX11]], align 46422// CHECK0-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C7]], i64 0, i64 16423// CHECK0-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX12]], i64 0, i64 26424// CHECK0-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX13]], align 86425// CHECK0-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP5]]6426// CHECK0-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[VLA8]], i64 [[TMP14]]6427// CHECK0-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i64 36428// CHECK0-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX15]], align 86429// CHECK0-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D9]], i32 0, i32 06430// CHECK0-NEXT: store i64 1, ptr [[X]], align 86431// CHECK0-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D9]], i32 0, i32 16432// CHECK0-NEXT: store i8 1, ptr [[Y]], align 86433// CHECK0-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 86434// CHECK0-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP15]])6435// CHECK0-NEXT: ret void6436//6437//6438// CHECK0-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l1116439// CHECK0-SAME: (ptr noundef [[PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR2]] {6440// CHECK0-NEXT: entry:6441// CHECK0-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 86442// CHECK0-NEXT: [[E_ADDR:%.*]] = alloca ptr, align 86443// CHECK0-NEXT: [[E1:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 46444// CHECK0-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 86445// CHECK0-NEXT: store ptr [[E]], ptr [[E_ADDR]], align 86446// CHECK0-NEXT: [[TMP0:%.*]] = load ptr, ptr [[E_ADDR]], align 86447// CHECK0-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[E1]], ptr align 4 [[TMP0]], i64 8, i1 false)6448// CHECK0-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT_0]], ptr [[E1]], i32 0, i32 06449// CHECK0-NEXT: [[TMP1:%.*]] = load i32, ptr [[X]], align 46450// CHECK0-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double6451// CHECK0-NEXT: [[TMP2:%.*]] = load ptr, ptr [[PTR_ADDR]], align 86452// CHECK0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP2]], i64 06453// CHECK0-NEXT: store double [[CONV]], ptr [[ARRAYIDX]], align 86454// CHECK0-NEXT: [[TMP3:%.*]] = load ptr, ptr [[PTR_ADDR]], align 86455// CHECK0-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, ptr [[TMP3]], i64 06456// CHECK0-NEXT: [[TMP4:%.*]] = load double, ptr [[ARRAYIDX2]], align 86457// CHECK0-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+006458// CHECK0-NEXT: store double [[INC]], ptr [[ARRAYIDX2]], align 86459// CHECK0-NEXT: ret void6460//6461//6462// CHECK0-LABEL: define {{[^@]+}}@_Z3bariPd6463// CHECK0-SAME: (i32 noundef signext [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0]] {6464// CHECK0-NEXT: entry:6465// CHECK0-NEXT: [[N_ADDR:%.*]] = alloca i32, align 46466// CHECK0-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 86467// CHECK0-NEXT: [[A:%.*]] = alloca i32, align 46468// CHECK0-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 86469// CHECK0-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 46470// CHECK0-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 86471// CHECK0-NEXT: store i32 0, ptr [[A]], align 46472// CHECK0-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 46473// CHECK0-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 86474// CHECK0-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooiPd(i32 noundef signext [[TMP0]], ptr noundef [[TMP1]])6475// CHECK0-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 46476// CHECK0-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]]6477// CHECK0-NEXT: store i32 [[ADD]], ptr [[A]], align 46478// CHECK0-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 46479// CHECK0-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP3]])6480// CHECK0-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 46481// CHECK0-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]]6482// CHECK0-NEXT: store i32 [[ADD2]], ptr [[A]], align 46483// CHECK0-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 46484// CHECK0-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP5]])6485// CHECK0-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 46486// CHECK0-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]]6487// CHECK0-NEXT: store i32 [[ADD4]], ptr [[A]], align 46488// CHECK0-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 46489// CHECK0-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP7]])6490// CHECK0-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 46491// CHECK0-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]]6492// CHECK0-NEXT: store i32 [[ADD6]], ptr [[A]], align 46493// CHECK0-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 46494// CHECK0-NEXT: ret i32 [[TMP9]]6495//6496//6497// CHECK0-LABEL: define {{[^@]+}}@_ZN2S12r1Ei6498// CHECK0-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {6499// CHECK0-NEXT: entry:6500// CHECK0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 86501// CHECK0-NEXT: [[N_ADDR:%.*]] = alloca i32, align 46502// CHECK0-NEXT: [[B:%.*]] = alloca i32, align 46503// CHECK0-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 86504// CHECK0-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 86505// CHECK0-NEXT: [[B_CASTED:%.*]] = alloca i64, align 86506// CHECK0-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 86507// CHECK0-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 86508// CHECK0-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 86509// CHECK0-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 86510// CHECK0-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 86511// CHECK0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 86512// CHECK0-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 46513// CHECK0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 86514// CHECK0-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 46515// CHECK0-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 16516// CHECK0-NEXT: store i32 [[ADD]], ptr [[B]], align 46517// CHECK0-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 46518// CHECK0-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i646519// CHECK0-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()6520// CHECK0-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 86521// CHECK0-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]6522// CHECK0-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 26523// CHECK0-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 86524// CHECK0-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 46525// CHECK0-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 46526// CHECK0-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 86527// CHECK0-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 06528// CHECK0-NEXT: [[TMP7:%.*]] = mul nuw i64 2, [[TMP2]]6529// CHECK0-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP7]], 26530// CHECK0-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.5, i64 40, i1 false)6531// CHECK0-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 06532// CHECK0-NEXT: store ptr [[THIS1]], ptr [[TMP9]], align 86533// CHECK0-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 06534// CHECK0-NEXT: store ptr [[A]], ptr [[TMP10]], align 86535// CHECK0-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 06536// CHECK0-NEXT: store ptr null, ptr [[TMP11]], align 86537// CHECK0-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 16538// CHECK0-NEXT: store i64 [[TMP6]], ptr [[TMP12]], align 86539// CHECK0-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 16540// CHECK0-NEXT: store i64 [[TMP6]], ptr [[TMP13]], align 86541// CHECK0-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 16542// CHECK0-NEXT: store ptr null, ptr [[TMP14]], align 86543// CHECK0-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 26544// CHECK0-NEXT: store i64 2, ptr [[TMP15]], align 86545// CHECK0-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 26546// CHECK0-NEXT: store i64 2, ptr [[TMP16]], align 86547// CHECK0-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 26548// CHECK0-NEXT: store ptr null, ptr [[TMP17]], align 86549// CHECK0-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 36550// CHECK0-NEXT: store i64 [[TMP2]], ptr [[TMP18]], align 86551// CHECK0-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 36552// CHECK0-NEXT: store i64 [[TMP2]], ptr [[TMP19]], align 86553// CHECK0-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 36554// CHECK0-NEXT: store ptr null, ptr [[TMP20]], align 86555// CHECK0-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 46556// CHECK0-NEXT: store ptr [[VLA]], ptr [[TMP21]], align 86557// CHECK0-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 46558// CHECK0-NEXT: store ptr [[VLA]], ptr [[TMP22]], align 86559// CHECK0-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 46560// CHECK0-NEXT: store i64 [[TMP8]], ptr [[TMP23]], align 86561// CHECK0-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 46562// CHECK0-NEXT: store ptr null, ptr [[TMP24]], align 86563// CHECK0-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 06564// CHECK0-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 06565// CHECK0-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 06566// CHECK0-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 06567// CHECK0-NEXT: store i32 3, ptr [[TMP28]], align 46568// CHECK0-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 16569// CHECK0-NEXT: store i32 5, ptr [[TMP29]], align 46570// CHECK0-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 26571// CHECK0-NEXT: store ptr [[TMP25]], ptr [[TMP30]], align 86572// CHECK0-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 36573// CHECK0-NEXT: store ptr [[TMP26]], ptr [[TMP31]], align 86574// CHECK0-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 46575// CHECK0-NEXT: store ptr [[TMP27]], ptr [[TMP32]], align 86576// CHECK0-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 56577// CHECK0-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP33]], align 86578// CHECK0-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 66579// CHECK0-NEXT: store ptr null, ptr [[TMP34]], align 86580// CHECK0-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 76581// CHECK0-NEXT: store ptr null, ptr [[TMP35]], align 86582// CHECK0-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 86583// CHECK0-NEXT: store i64 0, ptr [[TMP36]], align 86584// CHECK0-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 96585// CHECK0-NEXT: store i64 0, ptr [[TMP37]], align 86586// CHECK0-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 106587// CHECK0-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP38]], align 46588// CHECK0-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 116589// CHECK0-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP39]], align 46590// CHECK0-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 126591// CHECK0-NEXT: store i32 0, ptr [[TMP40]], align 46592// CHECK0-NEXT: [[TMP41:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167.region_id, ptr [[KERNEL_ARGS]])6593// CHECK0-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 06594// CHECK0-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]6595// CHECK0: omp_offload.failed:6596// CHECK0-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR3]]6597// CHECK0-NEXT: br label [[OMP_OFFLOAD_CONT]]6598// CHECK0: omp_offload.cont:6599// CHECK0-NEXT: [[TMP43:%.*]] = mul nsw i64 1, [[TMP2]]6600// CHECK0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP43]]6601// CHECK0-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 16602// CHECK0-NEXT: [[TMP44:%.*]] = load i16, ptr [[ARRAYIDX2]], align 26603// CHECK0-NEXT: [[CONV:%.*]] = sext i16 [[TMP44]] to i326604// CHECK0-NEXT: [[TMP45:%.*]] = load i32, ptr [[B]], align 46605// CHECK0-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP45]]6606// CHECK0-NEXT: [[TMP46:%.*]] = load ptr, ptr [[SAVED_STACK]], align 86607// CHECK0-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP46]])6608// CHECK0-NEXT: ret i32 [[ADD3]]6609//6610//6611// CHECK0-LABEL: define {{[^@]+}}@_ZL7fstatici6612// CHECK0-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {6613// CHECK0-NEXT: entry:6614// CHECK0-NEXT: [[N_ADDR:%.*]] = alloca i32, align 46615// CHECK0-NEXT: [[A:%.*]] = alloca i32, align 46616// CHECK0-NEXT: [[AAA:%.*]] = alloca i8, align 16617// CHECK0-NEXT: [[B:%.*]] = alloca [10 x i32], align 46618// CHECK0-NEXT: [[A_CASTED:%.*]] = alloca i64, align 86619// CHECK0-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 86620// CHECK0-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 86621// CHECK0-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 86622// CHECK0-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 86623// CHECK0-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 86624// CHECK0-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 46625// CHECK0-NEXT: store i32 0, ptr [[A]], align 46626// CHECK0-NEXT: store i8 0, ptr [[AAA]], align 16627// CHECK0-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 46628// CHECK0-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 46629// CHECK0-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 86630// CHECK0-NEXT: [[TMP2:%.*]] = load i8, ptr [[AAA]], align 16631// CHECK0-NEXT: store i8 [[TMP2]], ptr [[AAA_CASTED]], align 16632// CHECK0-NEXT: [[TMP3:%.*]] = load i64, ptr [[AAA_CASTED]], align 86633// CHECK0-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 06634// CHECK0-NEXT: store i64 [[TMP1]], ptr [[TMP4]], align 86635// CHECK0-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 06636// CHECK0-NEXT: store i64 [[TMP1]], ptr [[TMP5]], align 86637// CHECK0-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 06638// CHECK0-NEXT: store ptr null, ptr [[TMP6]], align 86639// CHECK0-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 16640// CHECK0-NEXT: store i64 [[TMP3]], ptr [[TMP7]], align 86641// CHECK0-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 16642// CHECK0-NEXT: store i64 [[TMP3]], ptr [[TMP8]], align 86643// CHECK0-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 16644// CHECK0-NEXT: store ptr null, ptr [[TMP9]], align 86645// CHECK0-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 26646// CHECK0-NEXT: store ptr [[B]], ptr [[TMP10]], align 86647// CHECK0-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 26648// CHECK0-NEXT: store ptr [[B]], ptr [[TMP11]], align 86649// CHECK0-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 26650// CHECK0-NEXT: store ptr null, ptr [[TMP12]], align 86651// CHECK0-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 06652// CHECK0-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 06653// CHECK0-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 06654// CHECK0-NEXT: store i32 3, ptr [[TMP15]], align 46655// CHECK0-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 16656// CHECK0-NEXT: store i32 3, ptr [[TMP16]], align 46657// CHECK0-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 26658// CHECK0-NEXT: store ptr [[TMP13]], ptr [[TMP17]], align 86659// CHECK0-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 36660// CHECK0-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 86661// CHECK0-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 46662// CHECK0-NEXT: store ptr @.offload_sizes.7, ptr [[TMP19]], align 86663// CHECK0-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 56664// CHECK0-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP20]], align 86665// CHECK0-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 66666// CHECK0-NEXT: store ptr null, ptr [[TMP21]], align 86667// CHECK0-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 76668// CHECK0-NEXT: store ptr null, ptr [[TMP22]], align 86669// CHECK0-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 86670// CHECK0-NEXT: store i64 0, ptr [[TMP23]], align 86671// CHECK0-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 96672// CHECK0-NEXT: store i64 0, ptr [[TMP24]], align 86673// CHECK0-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 106674// CHECK0-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP25]], align 46675// CHECK0-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 116676// CHECK0-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP26]], align 46677// CHECK0-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 126678// CHECK0-NEXT: store i32 0, ptr [[TMP27]], align 46679// CHECK0-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142.region_id, ptr [[KERNEL_ARGS]])6680// CHECK0-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 06681// CHECK0-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]6682// CHECK0: omp_offload.failed:6683// CHECK0-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]]6684// CHECK0-NEXT: br label [[OMP_OFFLOAD_CONT]]6685// CHECK0: omp_offload.cont:6686// CHECK0-NEXT: [[TMP30:%.*]] = load i32, ptr [[A]], align 46687// CHECK0-NEXT: ret i32 [[TMP30]]6688//6689//6690// CHECK0-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i6691// CHECK0-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {6692// CHECK0-NEXT: entry:6693// CHECK0-NEXT: [[N_ADDR:%.*]] = alloca i32, align 46694// CHECK0-NEXT: [[A:%.*]] = alloca i32, align 46695// CHECK0-NEXT: [[B:%.*]] = alloca [10 x i32], align 46696// CHECK0-NEXT: [[A_CASTED:%.*]] = alloca i64, align 86697// CHECK0-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x ptr], align 86698// CHECK0-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x ptr], align 86699// CHECK0-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x ptr], align 86700// CHECK0-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 86701// CHECK0-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 46702// CHECK0-NEXT: store i32 0, ptr [[A]], align 46703// CHECK0-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 46704// CHECK0-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 46705// CHECK0-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 86706// CHECK0-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 06707// CHECK0-NEXT: store i64 [[TMP1]], ptr [[TMP2]], align 86708// CHECK0-NEXT: [[TMP3:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 06709// CHECK0-NEXT: store i64 [[TMP1]], ptr [[TMP3]], align 86710// CHECK0-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 06711// CHECK0-NEXT: store ptr null, ptr [[TMP4]], align 86712// CHECK0-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 16713// CHECK0-NEXT: store ptr [[B]], ptr [[TMP5]], align 86714// CHECK0-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 16715// CHECK0-NEXT: store ptr [[B]], ptr [[TMP6]], align 86716// CHECK0-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 16717// CHECK0-NEXT: store ptr null, ptr [[TMP7]], align 86718// CHECK0-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 06719// CHECK0-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 06720// CHECK0-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 06721// CHECK0-NEXT: store i32 3, ptr [[TMP10]], align 46722// CHECK0-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 16723// CHECK0-NEXT: store i32 2, ptr [[TMP11]], align 46724// CHECK0-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 26725// CHECK0-NEXT: store ptr [[TMP8]], ptr [[TMP12]], align 86726// CHECK0-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 36727// CHECK0-NEXT: store ptr [[TMP9]], ptr [[TMP13]], align 86728// CHECK0-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 46729// CHECK0-NEXT: store ptr @.offload_sizes.9, ptr [[TMP14]], align 86730// CHECK0-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 56731// CHECK0-NEXT: store ptr @.offload_maptypes.10, ptr [[TMP15]], align 86732// CHECK0-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 66733// CHECK0-NEXT: store ptr null, ptr [[TMP16]], align 86734// CHECK0-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 76735// CHECK0-NEXT: store ptr null, ptr [[TMP17]], align 86736// CHECK0-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 86737// CHECK0-NEXT: store i64 0, ptr [[TMP18]], align 86738// CHECK0-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 96739// CHECK0-NEXT: store i64 0, ptr [[TMP19]], align 86740// CHECK0-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 106741// CHECK0-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP20]], align 46742// CHECK0-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 116743// CHECK0-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP21]], align 46744// CHECK0-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 126745// CHECK0-NEXT: store i32 0, ptr [[TMP22]], align 46746// CHECK0-NEXT: [[TMP23:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128.region_id, ptr [[KERNEL_ARGS]])6747// CHECK0-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 06748// CHECK0-NEXT: br i1 [[TMP24]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]6749// CHECK0: omp_offload.failed:6750// CHECK0-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128(i64 [[TMP1]], ptr [[B]]) #[[ATTR3]]6751// CHECK0-NEXT: br label [[OMP_OFFLOAD_CONT]]6752// CHECK0: omp_offload.cont:6753// CHECK0-NEXT: [[TMP25:%.*]] = load i32, ptr [[A]], align 46754// CHECK0-NEXT: ret i32 [[TMP25]]6755//6756//6757// CHECK0-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l1676758// CHECK0-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {6759// CHECK0-NEXT: entry:6760// CHECK0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 86761// CHECK0-NEXT: [[B_ADDR:%.*]] = alloca i64, align 86762// CHECK0-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 86763// CHECK0-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 86764// CHECK0-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 86765// CHECK0-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 86766// CHECK0-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 86767// CHECK0-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 86768// CHECK0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 86769// CHECK0-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 86770// CHECK0-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 86771// CHECK0-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 86772// CHECK0-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 86773// CHECK0-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 86774// CHECK0-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 86775// CHECK0-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 86776// CHECK0-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 86777// CHECK0-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave.p0()6778// CHECK0-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 86779// CHECK0-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]]6780// CHECK0-NEXT: [[VLA3:%.*]] = alloca i16, i64 [[TMP5]], align 26781// CHECK0-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 86782// CHECK0-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR1]], align 86783// CHECK0-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]]6784// CHECK0-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], 26785// CHECK0-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 2 [[VLA3]], ptr align 2 [[TMP3]], i64 [[TMP7]], i1 false)6786// CHECK0-NEXT: [[TMP8:%.*]] = load i32, ptr [[B_ADDR]], align 46787// CHECK0-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double6788// CHECK0-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+006789// CHECK0-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 06790// CHECK0-NEXT: store double [[ADD]], ptr [[A]], align 86791// CHECK0-NEXT: [[A4:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 06792// CHECK0-NEXT: [[TMP9:%.*]] = load double, ptr [[A4]], align 86793// CHECK0-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+006794// CHECK0-NEXT: store double [[INC]], ptr [[A4]], align 86795// CHECK0-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i166796// CHECK0-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]]6797// CHECK0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA3]], i64 [[TMP10]]6798// CHECK0-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 16799// CHECK0-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 26800// CHECK0-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 86801// CHECK0-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP11]])6802// CHECK0-NEXT: ret void6803//6804//6805// CHECK0-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l1426806// CHECK0-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {6807// CHECK0-NEXT: entry:6808// CHECK0-NEXT: [[A_ADDR:%.*]] = alloca i64, align 86809// CHECK0-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 86810// CHECK0-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 86811// CHECK0-NEXT: [[B1:%.*]] = alloca [10 x i32], align 46812// CHECK0-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 86813// CHECK0-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 86814// CHECK0-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 86815// CHECK0-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 86816// CHECK0-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B1]], ptr align 4 [[TMP0]], i64 40, i1 false)6817// CHECK0-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 46818// CHECK0-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 16819// CHECK0-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 46820// CHECK0-NEXT: [[TMP2:%.*]] = load i8, ptr [[AAA_ADDR]], align 16821// CHECK0-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i326822// CHECK0-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 16823// CHECK0-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i86824// CHECK0-NEXT: store i8 [[CONV3]], ptr [[AAA_ADDR]], align 16825// CHECK0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B1]], i64 0, i64 26826// CHECK0-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 46827// CHECK0-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 16828// CHECK0-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 46829// CHECK0-NEXT: ret void6830//6831//6832// CHECK0-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l1286833// CHECK0-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {6834// CHECK0-NEXT: entry:6835// CHECK0-NEXT: [[A_ADDR:%.*]] = alloca i64, align 86836// CHECK0-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 86837// CHECK0-NEXT: [[B1:%.*]] = alloca [10 x i32], align 46838// CHECK0-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 86839// CHECK0-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 86840// CHECK0-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 86841// CHECK0-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B1]], ptr align 4 [[TMP0]], i64 40, i1 false)6842// CHECK0-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 46843// CHECK0-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 16844// CHECK0-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 46845// CHECK0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B1]], i64 0, i64 26846// CHECK0-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 46847// CHECK0-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 16848// CHECK0-NEXT: store i32 [[ADD2]], ptr [[ARRAYIDX]], align 46849// CHECK0-NEXT: ret void6850//6851//6852// CHECK1-LABEL: define {{[^@]+}}@_Z3fooiPd6853// CHECK1-SAME: (i32 noundef signext [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {6854// CHECK1-NEXT: entry:6855// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 46856// CHECK1-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 86857// CHECK1-NEXT: [[A:%.*]] = alloca i32, align 46858// CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 26859// CHECK1-NEXT: [[B:%.*]] = alloca [10 x float], align 46860// CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 86861// CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 86862// CHECK1-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 86863// CHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 86864// CHECK1-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 86865// CHECK1-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 46866// CHECK1-NEXT: [[P:%.*]] = alloca ptr, align 646867// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 86868// CHECK1-NEXT: [[GA_CASTED:%.*]] = alloca i64, align 86869// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 86870// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 86871// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 86872// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 86873// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 86874// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [9 x ptr], align 86875// CHECK1-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [9 x ptr], align 86876// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [9 x ptr], align 86877// CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 86878// CHECK1-NEXT: [[KERNEL_ARGS5:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 86879// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS8:%.*]] = alloca [2 x ptr], align 86880// CHECK1-NEXT: [[DOTOFFLOAD_PTRS9:%.*]] = alloca [2 x ptr], align 86881// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS10:%.*]] = alloca [2 x ptr], align 86882// CHECK1-NEXT: [[KERNEL_ARGS11:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 86883// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 46884// CHECK1-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 86885// CHECK1-NEXT: store i32 0, ptr [[A]], align 46886// CHECK1-NEXT: store i16 0, ptr [[AA]], align 26887// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 46888// CHECK1-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i646889// CHECK1-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()6890// CHECK1-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 86891// CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 46892// CHECK1-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 86893// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 46894// CHECK1-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i646895// CHECK1-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]6896// CHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 86897// CHECK1-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 86898// CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 06899// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 46900// CHECK1-NEXT: store i32 [[TMP6]], ptr [[X]], align 46901// CHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 16902// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 46903// CHECK1-NEXT: store i32 [[TMP7]], ptr [[Y]], align 46904// CHECK1-NEXT: store ptr [[A]], ptr [[P]], align 646905// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 46906// CHECK1-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 46907// CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 86908// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[P]], align 646909// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr @ga, align 46910// CHECK1-NEXT: store i32 [[TMP11]], ptr [[GA_CASTED]], align 46911// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[GA_CASTED]], align 86912// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 06913// CHECK1-NEXT: store i64 [[TMP9]], ptr [[TMP13]], align 86914// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 06915// CHECK1-NEXT: store i64 [[TMP9]], ptr [[TMP14]], align 86916// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 06917// CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 86918// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 16919// CHECK1-NEXT: store ptr [[TMP10]], ptr [[TMP16]], align 86920// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 16921// CHECK1-NEXT: store ptr [[TMP10]], ptr [[TMP17]], align 86922// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 16923// CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 86924// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 26925// CHECK1-NEXT: store i64 [[TMP12]], ptr [[TMP19]], align 86926// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 26927// CHECK1-NEXT: store i64 [[TMP12]], ptr [[TMP20]], align 86928// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 26929// CHECK1-NEXT: store ptr null, ptr [[TMP21]], align 86930// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 06931// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 06932// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 06933// CHECK1-NEXT: store i32 3, ptr [[TMP24]], align 46934// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 16935// CHECK1-NEXT: store i32 3, ptr [[TMP25]], align 46936// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 26937// CHECK1-NEXT: store ptr [[TMP22]], ptr [[TMP26]], align 86938// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 36939// CHECK1-NEXT: store ptr [[TMP23]], ptr [[TMP27]], align 86940// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 46941// CHECK1-NEXT: store ptr @.offload_sizes, ptr [[TMP28]], align 86942// CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 56943// CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP29]], align 86944// CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 66945// CHECK1-NEXT: store ptr null, ptr [[TMP30]], align 86946// CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 76947// CHECK1-NEXT: store ptr null, ptr [[TMP31]], align 86948// CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 86949// CHECK1-NEXT: store i64 0, ptr [[TMP32]], align 86950// CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 96951// CHECK1-NEXT: store i64 0, ptr [[TMP33]], align 86952// CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 106953// CHECK1-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP34]], align 46954// CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 116955// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP35]], align 46956// CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 126957// CHECK1-NEXT: store i32 0, ptr [[TMP36]], align 46958// CHECK1-NEXT: [[TMP37:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63.region_id, ptr [[KERNEL_ARGS]])6959// CHECK1-NEXT: [[TMP38:%.*]] = icmp ne i32 [[TMP37]], 06960// CHECK1-NEXT: br i1 [[TMP38]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]6961// CHECK1: omp_offload.failed:6962// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63(i64 [[TMP9]], ptr [[TMP10]], i64 [[TMP12]]) #[[ATTR3:[0-9]+]]6963// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]6964// CHECK1: omp_offload.cont:6965// CHECK1-NEXT: [[TMP39:%.*]] = load i16, ptr [[AA]], align 26966// CHECK1-NEXT: store i16 [[TMP39]], ptr [[AA_CASTED]], align 26967// CHECK1-NEXT: [[TMP40:%.*]] = load i64, ptr [[AA_CASTED]], align 86968// CHECK1-NEXT: [[TMP41:%.*]] = mul nuw i64 [[TMP1]], 46969// CHECK1-NEXT: [[TMP42:%.*]] = mul nuw i64 5, [[TMP4]]6970// CHECK1-NEXT: [[TMP43:%.*]] = mul nuw i64 [[TMP42]], 86971// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.1, i64 72, i1 false)6972// CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 06973// CHECK1-NEXT: store i64 [[TMP40]], ptr [[TMP44]], align 86974// CHECK1-NEXT: [[TMP45:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 06975// CHECK1-NEXT: store i64 [[TMP40]], ptr [[TMP45]], align 86976// CHECK1-NEXT: [[TMP46:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i64 0, i64 06977// CHECK1-NEXT: store ptr null, ptr [[TMP46]], align 86978// CHECK1-NEXT: [[TMP47:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 16979// CHECK1-NEXT: store ptr [[B]], ptr [[TMP47]], align 86980// CHECK1-NEXT: [[TMP48:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 16981// CHECK1-NEXT: store ptr [[B]], ptr [[TMP48]], align 86982// CHECK1-NEXT: [[TMP49:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i64 0, i64 16983// CHECK1-NEXT: store ptr null, ptr [[TMP49]], align 86984// CHECK1-NEXT: [[TMP50:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 26985// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP50]], align 86986// CHECK1-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 26987// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP51]], align 86988// CHECK1-NEXT: [[TMP52:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i64 0, i64 26989// CHECK1-NEXT: store ptr null, ptr [[TMP52]], align 86990// CHECK1-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 36991// CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP53]], align 86992// CHECK1-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 36993// CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP54]], align 86994// CHECK1-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 36995// CHECK1-NEXT: store i64 [[TMP41]], ptr [[TMP55]], align 86996// CHECK1-NEXT: [[TMP56:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i64 0, i64 36997// CHECK1-NEXT: store ptr null, ptr [[TMP56]], align 86998// CHECK1-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 46999// CHECK1-NEXT: store ptr [[C]], ptr [[TMP57]], align 87000// CHECK1-NEXT: [[TMP58:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 47001// CHECK1-NEXT: store ptr [[C]], ptr [[TMP58]], align 87002// CHECK1-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i64 0, i64 47003// CHECK1-NEXT: store ptr null, ptr [[TMP59]], align 87004// CHECK1-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 57005// CHECK1-NEXT: store i64 5, ptr [[TMP60]], align 87006// CHECK1-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 57007// CHECK1-NEXT: store i64 5, ptr [[TMP61]], align 87008// CHECK1-NEXT: [[TMP62:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i64 0, i64 57009// CHECK1-NEXT: store ptr null, ptr [[TMP62]], align 87010// CHECK1-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 67011// CHECK1-NEXT: store i64 [[TMP4]], ptr [[TMP63]], align 87012// CHECK1-NEXT: [[TMP64:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 67013// CHECK1-NEXT: store i64 [[TMP4]], ptr [[TMP64]], align 87014// CHECK1-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i64 0, i64 67015// CHECK1-NEXT: store ptr null, ptr [[TMP65]], align 87016// CHECK1-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 77017// CHECK1-NEXT: store ptr [[VLA1]], ptr [[TMP66]], align 87018// CHECK1-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 77019// CHECK1-NEXT: store ptr [[VLA1]], ptr [[TMP67]], align 87020// CHECK1-NEXT: [[TMP68:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 77021// CHECK1-NEXT: store i64 [[TMP43]], ptr [[TMP68]], align 87022// CHECK1-NEXT: [[TMP69:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i64 0, i64 77023// CHECK1-NEXT: store ptr null, ptr [[TMP69]], align 87024// CHECK1-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 87025// CHECK1-NEXT: store ptr [[D]], ptr [[TMP70]], align 87026// CHECK1-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 87027// CHECK1-NEXT: store ptr [[D]], ptr [[TMP71]], align 87028// CHECK1-NEXT: [[TMP72:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i64 0, i64 87029// CHECK1-NEXT: store ptr null, ptr [[TMP72]], align 87030// CHECK1-NEXT: [[TMP73:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 07031// CHECK1-NEXT: [[TMP74:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 07032// CHECK1-NEXT: [[TMP75:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 07033// CHECK1-NEXT: [[TMP76:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 07034// CHECK1-NEXT: store i32 3, ptr [[TMP76]], align 47035// CHECK1-NEXT: [[TMP77:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 17036// CHECK1-NEXT: store i32 9, ptr [[TMP77]], align 47037// CHECK1-NEXT: [[TMP78:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 27038// CHECK1-NEXT: store ptr [[TMP73]], ptr [[TMP78]], align 87039// CHECK1-NEXT: [[TMP79:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 37040// CHECK1-NEXT: store ptr [[TMP74]], ptr [[TMP79]], align 87041// CHECK1-NEXT: [[TMP80:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 47042// CHECK1-NEXT: store ptr [[TMP75]], ptr [[TMP80]], align 87043// CHECK1-NEXT: [[TMP81:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 57044// CHECK1-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP81]], align 87045// CHECK1-NEXT: [[TMP82:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 67046// CHECK1-NEXT: store ptr null, ptr [[TMP82]], align 87047// CHECK1-NEXT: [[TMP83:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 77048// CHECK1-NEXT: store ptr null, ptr [[TMP83]], align 87049// CHECK1-NEXT: [[TMP84:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 87050// CHECK1-NEXT: store i64 0, ptr [[TMP84]], align 87051// CHECK1-NEXT: [[TMP85:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 97052// CHECK1-NEXT: store i64 0, ptr [[TMP85]], align 87053// CHECK1-NEXT: [[TMP86:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 107054// CHECK1-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP86]], align 47055// CHECK1-NEXT: [[TMP87:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 117056// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP87]], align 47057// CHECK1-NEXT: [[TMP88:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 127058// CHECK1-NEXT: store i32 0, ptr [[TMP88]], align 47059// CHECK1-NEXT: [[TMP89:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70.region_id, ptr [[KERNEL_ARGS5]])7060// CHECK1-NEXT: [[TMP90:%.*]] = icmp ne i32 [[TMP89]], 07061// CHECK1-NEXT: br i1 [[TMP90]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]]7062// CHECK1: omp_offload.failed6:7063// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70(i64 [[TMP40]], ptr [[B]], i64 [[TMP1]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP4]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]]7064// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT7]]7065// CHECK1: omp_offload.cont7:7066// CHECK1-NEXT: [[TMP91:%.*]] = load ptr, ptr [[PTR_ADDR]], align 87067// CHECK1-NEXT: [[TMP92:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 07068// CHECK1-NEXT: store ptr [[TMP91]], ptr [[TMP92]], align 87069// CHECK1-NEXT: [[TMP93:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS9]], i32 0, i32 07070// CHECK1-NEXT: store ptr [[TMP91]], ptr [[TMP93]], align 87071// CHECK1-NEXT: [[TMP94:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS10]], i64 0, i64 07072// CHECK1-NEXT: store ptr null, ptr [[TMP94]], align 87073// CHECK1-NEXT: [[TMP95:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 17074// CHECK1-NEXT: store ptr [[E]], ptr [[TMP95]], align 87075// CHECK1-NEXT: [[TMP96:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS9]], i32 0, i32 17076// CHECK1-NEXT: store ptr [[E]], ptr [[TMP96]], align 87077// CHECK1-NEXT: [[TMP97:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS10]], i64 0, i64 17078// CHECK1-NEXT: store ptr null, ptr [[TMP97]], align 87079// CHECK1-NEXT: [[TMP98:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 07080// CHECK1-NEXT: [[TMP99:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS9]], i32 0, i32 07081// CHECK1-NEXT: [[TMP100:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 07082// CHECK1-NEXT: store i32 3, ptr [[TMP100]], align 47083// CHECK1-NEXT: [[TMP101:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 17084// CHECK1-NEXT: store i32 2, ptr [[TMP101]], align 47085// CHECK1-NEXT: [[TMP102:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 27086// CHECK1-NEXT: store ptr [[TMP98]], ptr [[TMP102]], align 87087// CHECK1-NEXT: [[TMP103:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 37088// CHECK1-NEXT: store ptr [[TMP99]], ptr [[TMP103]], align 87089// CHECK1-NEXT: [[TMP104:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 47090// CHECK1-NEXT: store ptr @.offload_sizes.3, ptr [[TMP104]], align 87091// CHECK1-NEXT: [[TMP105:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 57092// CHECK1-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP105]], align 87093// CHECK1-NEXT: [[TMP106:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 67094// CHECK1-NEXT: store ptr null, ptr [[TMP106]], align 87095// CHECK1-NEXT: [[TMP107:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 77096// CHECK1-NEXT: store ptr null, ptr [[TMP107]], align 87097// CHECK1-NEXT: [[TMP108:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 87098// CHECK1-NEXT: store i64 0, ptr [[TMP108]], align 87099// CHECK1-NEXT: [[TMP109:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 97100// CHECK1-NEXT: store i64 0, ptr [[TMP109]], align 87101// CHECK1-NEXT: [[TMP110:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 107102// CHECK1-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP110]], align 47103// CHECK1-NEXT: [[TMP111:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 117104// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP111]], align 47105// CHECK1-NEXT: [[TMP112:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 127106// CHECK1-NEXT: store i32 0, ptr [[TMP112]], align 47107// CHECK1-NEXT: [[TMP113:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111.region_id, ptr [[KERNEL_ARGS11]])7108// CHECK1-NEXT: [[TMP114:%.*]] = icmp ne i32 [[TMP113]], 07109// CHECK1-NEXT: br i1 [[TMP114]], label [[OMP_OFFLOAD_FAILED12:%.*]], label [[OMP_OFFLOAD_CONT13:%.*]]7110// CHECK1: omp_offload.failed12:7111// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111(ptr [[TMP91]], ptr [[E]]) #[[ATTR3]]7112// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT13]]7113// CHECK1: omp_offload.cont13:7114// CHECK1-NEXT: [[TMP115:%.*]] = load i32, ptr [[A]], align 47115// CHECK1-NEXT: [[TMP116:%.*]] = load ptr, ptr [[SAVED_STACK]], align 87116// CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP116]])7117// CHECK1-NEXT: ret i32 [[TMP115]]7118//7119//7120// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l637121// CHECK1-SAME: (i64 noundef [[A:%.*]], ptr noundef [[P:%.*]], i64 noundef [[GA:%.*]]) #[[ATTR2:[0-9]+]] {7122// CHECK1-NEXT: entry:7123// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 87124// CHECK1-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 87125// CHECK1-NEXT: [[GA_ADDR:%.*]] = alloca i64, align 87126// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 87127// CHECK1-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 87128// CHECK1-NEXT: store i64 [[GA]], ptr [[GA_ADDR]], align 87129// CHECK1-NEXT: ret void7130//7131//7132// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l707133// CHECK1-SAME: (i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {7134// CHECK1-NEXT: entry:7135// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 87136// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 87137// CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 87138// CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 87139// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 87140// CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 87141// CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 87142// CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 87143// CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 87144// CHECK1-NEXT: [[B5:%.*]] = alloca [10 x float], align 47145// CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 87146// CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 87147// CHECK1-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 87148// CHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 87149// CHECK1-NEXT: [[__VLA_EXPR2:%.*]] = alloca i64, align 87150// CHECK1-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 87151// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 87152// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 87153// CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 87154// CHECK1-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 87155// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 87156// CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 87157// CHECK1-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 87158// CHECK1-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 87159// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 87160// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 87161// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 87162// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 87163// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 87164// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 87165// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 87166// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 87167// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 87168// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B5]], ptr align 4 [[TMP0]], i64 40, i1 false)7169// CHECK1-NEXT: [[TMP8:%.*]] = call ptr @llvm.stacksave.p0()7170// CHECK1-NEXT: store ptr [[TMP8]], ptr [[SAVED_STACK]], align 87171// CHECK1-NEXT: [[VLA6:%.*]] = alloca float, i64 [[TMP1]], align 47172// CHECK1-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 87173// CHECK1-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP1]], 47174// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VLA6]], ptr align 4 [[TMP2]], i64 [[TMP9]], i1 false)7175// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[C7]], ptr align 8 [[TMP3]], i64 400, i1 false)7176// CHECK1-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]]7177// CHECK1-NEXT: [[VLA8:%.*]] = alloca double, i64 [[TMP10]], align 87178// CHECK1-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 87179// CHECK1-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR2]], align 87180// CHECK1-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]]7181// CHECK1-NEXT: [[TMP12:%.*]] = mul nuw i64 [[TMP11]], 87182// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[VLA8]], ptr align 8 [[TMP6]], i64 [[TMP12]], i1 false)7183// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[D9]], ptr align 8 [[TMP7]], i64 16, i1 false)7184// CHECK1-NEXT: [[TMP13:%.*]] = load i16, ptr [[AA_ADDR]], align 27185// CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP13]] to i327186// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 17187// CHECK1-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i167188// CHECK1-NEXT: store i16 [[CONV10]], ptr [[AA_ADDR]], align 27189// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B5]], i64 0, i64 27190// CHECK1-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX]], align 47191// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, ptr [[VLA6]], i64 37192// CHECK1-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX11]], align 47193// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C7]], i64 0, i64 17194// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX12]], i64 0, i64 27195// CHECK1-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX13]], align 87196// CHECK1-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP5]]7197// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[VLA8]], i64 [[TMP14]]7198// CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i64 37199// CHECK1-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX15]], align 87200// CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D9]], i32 0, i32 07201// CHECK1-NEXT: store i64 1, ptr [[X]], align 87202// CHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D9]], i32 0, i32 17203// CHECK1-NEXT: store i8 1, ptr [[Y]], align 87204// CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 87205// CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP15]])7206// CHECK1-NEXT: ret void7207//7208//7209// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l1117210// CHECK1-SAME: (ptr noundef [[PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR2]] {7211// CHECK1-NEXT: entry:7212// CHECK1-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 87213// CHECK1-NEXT: [[E_ADDR:%.*]] = alloca ptr, align 87214// CHECK1-NEXT: [[E1:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 47215// CHECK1-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 87216// CHECK1-NEXT: store ptr [[E]], ptr [[E_ADDR]], align 87217// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[E_ADDR]], align 87218// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[E1]], ptr align 4 [[TMP0]], i64 8, i1 false)7219// CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT_0]], ptr [[E1]], i32 0, i32 07220// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[X]], align 47221// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double7222// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[PTR_ADDR]], align 87223// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP2]], i64 07224// CHECK1-NEXT: store double [[CONV]], ptr [[ARRAYIDX]], align 87225// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[PTR_ADDR]], align 87226// CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, ptr [[TMP3]], i64 07227// CHECK1-NEXT: [[TMP4:%.*]] = load double, ptr [[ARRAYIDX2]], align 87228// CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+007229// CHECK1-NEXT: store double [[INC]], ptr [[ARRAYIDX2]], align 87230// CHECK1-NEXT: ret void7231//7232//7233// CHECK1-LABEL: define {{[^@]+}}@_Z3bariPd7234// CHECK1-SAME: (i32 noundef signext [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0]] {7235// CHECK1-NEXT: entry:7236// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 47237// CHECK1-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 87238// CHECK1-NEXT: [[A:%.*]] = alloca i32, align 47239// CHECK1-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 87240// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 47241// CHECK1-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 87242// CHECK1-NEXT: store i32 0, ptr [[A]], align 47243// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 47244// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 87245// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooiPd(i32 noundef signext [[TMP0]], ptr noundef [[TMP1]])7246// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 47247// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]]7248// CHECK1-NEXT: store i32 [[ADD]], ptr [[A]], align 47249// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 47250// CHECK1-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP3]])7251// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 47252// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]]7253// CHECK1-NEXT: store i32 [[ADD2]], ptr [[A]], align 47254// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 47255// CHECK1-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP5]])7256// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 47257// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]]7258// CHECK1-NEXT: store i32 [[ADD4]], ptr [[A]], align 47259// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 47260// CHECK1-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP7]])7261// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 47262// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]]7263// CHECK1-NEXT: store i32 [[ADD6]], ptr [[A]], align 47264// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 47265// CHECK1-NEXT: ret i32 [[TMP9]]7266//7267//7268// CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei7269// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {7270// CHECK1-NEXT: entry:7271// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 87272// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 47273// CHECK1-NEXT: [[B:%.*]] = alloca i32, align 47274// CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 87275// CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 87276// CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 87277// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 87278// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 87279// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 87280// CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 87281// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 87282// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 87283// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 47284// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 87285// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 47286// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 17287// CHECK1-NEXT: store i32 [[ADD]], ptr [[B]], align 47288// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 47289// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i647290// CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()7291// CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 87292// CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]7293// CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 27294// CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 87295// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 47296// CHECK1-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 47297// CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 87298// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 07299// CHECK1-NEXT: [[TMP7:%.*]] = mul nuw i64 2, [[TMP2]]7300// CHECK1-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP7]], 27301// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.5, i64 40, i1 false)7302// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 07303// CHECK1-NEXT: store ptr [[THIS1]], ptr [[TMP9]], align 87304// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 07305// CHECK1-NEXT: store ptr [[A]], ptr [[TMP10]], align 87306// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 07307// CHECK1-NEXT: store ptr null, ptr [[TMP11]], align 87308// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 17309// CHECK1-NEXT: store i64 [[TMP6]], ptr [[TMP12]], align 87310// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 17311// CHECK1-NEXT: store i64 [[TMP6]], ptr [[TMP13]], align 87312// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 17313// CHECK1-NEXT: store ptr null, ptr [[TMP14]], align 87314// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 27315// CHECK1-NEXT: store i64 2, ptr [[TMP15]], align 87316// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 27317// CHECK1-NEXT: store i64 2, ptr [[TMP16]], align 87318// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 27319// CHECK1-NEXT: store ptr null, ptr [[TMP17]], align 87320// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 37321// CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP18]], align 87322// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 37323// CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP19]], align 87324// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 37325// CHECK1-NEXT: store ptr null, ptr [[TMP20]], align 87326// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 47327// CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP21]], align 87328// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 47329// CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP22]], align 87330// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 47331// CHECK1-NEXT: store i64 [[TMP8]], ptr [[TMP23]], align 87332// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 47333// CHECK1-NEXT: store ptr null, ptr [[TMP24]], align 87334// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 07335// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 07336// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 07337// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 07338// CHECK1-NEXT: store i32 3, ptr [[TMP28]], align 47339// CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 17340// CHECK1-NEXT: store i32 5, ptr [[TMP29]], align 47341// CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 27342// CHECK1-NEXT: store ptr [[TMP25]], ptr [[TMP30]], align 87343// CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 37344// CHECK1-NEXT: store ptr [[TMP26]], ptr [[TMP31]], align 87345// CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 47346// CHECK1-NEXT: store ptr [[TMP27]], ptr [[TMP32]], align 87347// CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 57348// CHECK1-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP33]], align 87349// CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 67350// CHECK1-NEXT: store ptr null, ptr [[TMP34]], align 87351// CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 77352// CHECK1-NEXT: store ptr null, ptr [[TMP35]], align 87353// CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 87354// CHECK1-NEXT: store i64 0, ptr [[TMP36]], align 87355// CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 97356// CHECK1-NEXT: store i64 0, ptr [[TMP37]], align 87357// CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 107358// CHECK1-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP38]], align 47359// CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 117360// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP39]], align 47361// CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 127362// CHECK1-NEXT: store i32 0, ptr [[TMP40]], align 47363// CHECK1-NEXT: [[TMP41:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167.region_id, ptr [[KERNEL_ARGS]])7364// CHECK1-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 07365// CHECK1-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]7366// CHECK1: omp_offload.failed:7367// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR3]]7368// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]7369// CHECK1: omp_offload.cont:7370// CHECK1-NEXT: [[TMP43:%.*]] = mul nsw i64 1, [[TMP2]]7371// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP43]]7372// CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 17373// CHECK1-NEXT: [[TMP44:%.*]] = load i16, ptr [[ARRAYIDX2]], align 27374// CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP44]] to i327375// CHECK1-NEXT: [[TMP45:%.*]] = load i32, ptr [[B]], align 47376// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP45]]7377// CHECK1-NEXT: [[TMP46:%.*]] = load ptr, ptr [[SAVED_STACK]], align 87378// CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP46]])7379// CHECK1-NEXT: ret i32 [[ADD3]]7380//7381//7382// CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici7383// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {7384// CHECK1-NEXT: entry:7385// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 47386// CHECK1-NEXT: [[A:%.*]] = alloca i32, align 47387// CHECK1-NEXT: [[AAA:%.*]] = alloca i8, align 17388// CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 47389// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 87390// CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 87391// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 87392// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 87393// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 87394// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 87395// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 47396// CHECK1-NEXT: store i32 0, ptr [[A]], align 47397// CHECK1-NEXT: store i8 0, ptr [[AAA]], align 17398// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 47399// CHECK1-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 47400// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 87401// CHECK1-NEXT: [[TMP2:%.*]] = load i8, ptr [[AAA]], align 17402// CHECK1-NEXT: store i8 [[TMP2]], ptr [[AAA_CASTED]], align 17403// CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[AAA_CASTED]], align 87404// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 07405// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP4]], align 87406// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 07407// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP5]], align 87408// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 07409// CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 87410// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 17411// CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP7]], align 87412// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 17413// CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP8]], align 87414// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 17415// CHECK1-NEXT: store ptr null, ptr [[TMP9]], align 87416// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 27417// CHECK1-NEXT: store ptr [[B]], ptr [[TMP10]], align 87418// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 27419// CHECK1-NEXT: store ptr [[B]], ptr [[TMP11]], align 87420// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 27421// CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 87422// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 07423// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 07424// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 07425// CHECK1-NEXT: store i32 3, ptr [[TMP15]], align 47426// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 17427// CHECK1-NEXT: store i32 3, ptr [[TMP16]], align 47428// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 27429// CHECK1-NEXT: store ptr [[TMP13]], ptr [[TMP17]], align 87430// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 37431// CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 87432// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 47433// CHECK1-NEXT: store ptr @.offload_sizes.7, ptr [[TMP19]], align 87434// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 57435// CHECK1-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP20]], align 87436// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 67437// CHECK1-NEXT: store ptr null, ptr [[TMP21]], align 87438// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 77439// CHECK1-NEXT: store ptr null, ptr [[TMP22]], align 87440// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 87441// CHECK1-NEXT: store i64 0, ptr [[TMP23]], align 87442// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 97443// CHECK1-NEXT: store i64 0, ptr [[TMP24]], align 87444// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 107445// CHECK1-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP25]], align 47446// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 117447// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP26]], align 47448// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 127449// CHECK1-NEXT: store i32 0, ptr [[TMP27]], align 47450// CHECK1-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142.region_id, ptr [[KERNEL_ARGS]])7451// CHECK1-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 07452// CHECK1-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]7453// CHECK1: omp_offload.failed:7454// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]]7455// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]7456// CHECK1: omp_offload.cont:7457// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[A]], align 47458// CHECK1-NEXT: ret i32 [[TMP30]]7459//7460//7461// CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i7462// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {7463// CHECK1-NEXT: entry:7464// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 47465// CHECK1-NEXT: [[A:%.*]] = alloca i32, align 47466// CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 47467// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 87468// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x ptr], align 87469// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x ptr], align 87470// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x ptr], align 87471// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 87472// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 47473// CHECK1-NEXT: store i32 0, ptr [[A]], align 47474// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 47475// CHECK1-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 47476// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 87477// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 07478// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP2]], align 87479// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 07480// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP3]], align 87481// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 07482// CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 87483// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 17484// CHECK1-NEXT: store ptr [[B]], ptr [[TMP5]], align 87485// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 17486// CHECK1-NEXT: store ptr [[B]], ptr [[TMP6]], align 87487// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 17488// CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 87489// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 07490// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 07491// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 07492// CHECK1-NEXT: store i32 3, ptr [[TMP10]], align 47493// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 17494// CHECK1-NEXT: store i32 2, ptr [[TMP11]], align 47495// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 27496// CHECK1-NEXT: store ptr [[TMP8]], ptr [[TMP12]], align 87497// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 37498// CHECK1-NEXT: store ptr [[TMP9]], ptr [[TMP13]], align 87499// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 47500// CHECK1-NEXT: store ptr @.offload_sizes.9, ptr [[TMP14]], align 87501// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 57502// CHECK1-NEXT: store ptr @.offload_maptypes.10, ptr [[TMP15]], align 87503// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 67504// CHECK1-NEXT: store ptr null, ptr [[TMP16]], align 87505// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 77506// CHECK1-NEXT: store ptr null, ptr [[TMP17]], align 87507// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 87508// CHECK1-NEXT: store i64 0, ptr [[TMP18]], align 87509// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 97510// CHECK1-NEXT: store i64 0, ptr [[TMP19]], align 87511// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 107512// CHECK1-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP20]], align 47513// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 117514// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP21]], align 47515// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 127516// CHECK1-NEXT: store i32 0, ptr [[TMP22]], align 47517// CHECK1-NEXT: [[TMP23:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128.region_id, ptr [[KERNEL_ARGS]])7518// CHECK1-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 07519// CHECK1-NEXT: br i1 [[TMP24]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]7520// CHECK1: omp_offload.failed:7521// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128(i64 [[TMP1]], ptr [[B]]) #[[ATTR3]]7522// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]7523// CHECK1: omp_offload.cont:7524// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[A]], align 47525// CHECK1-NEXT: ret i32 [[TMP25]]7526//7527//7528// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l1677529// CHECK1-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {7530// CHECK1-NEXT: entry:7531// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 87532// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 87533// CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 87534// CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 87535// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 87536// CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 87537// CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 87538// CHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 87539// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 87540// CHECK1-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 87541// CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 87542// CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 87543// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 87544// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 87545// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 87546// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 87547// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 87548// CHECK1-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave.p0()7549// CHECK1-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 87550// CHECK1-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]]7551// CHECK1-NEXT: [[VLA3:%.*]] = alloca i16, i64 [[TMP5]], align 27552// CHECK1-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 87553// CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR1]], align 87554// CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]]7555// CHECK1-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], 27556// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 2 [[VLA3]], ptr align 2 [[TMP3]], i64 [[TMP7]], i1 false)7557// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[B_ADDR]], align 47558// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double7559// CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+007560// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 07561// CHECK1-NEXT: store double [[ADD]], ptr [[A]], align 87562// CHECK1-NEXT: [[A4:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 07563// CHECK1-NEXT: [[TMP9:%.*]] = load double, ptr [[A4]], align 87564// CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+007565// CHECK1-NEXT: store double [[INC]], ptr [[A4]], align 87566// CHECK1-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i167567// CHECK1-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]]7568// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA3]], i64 [[TMP10]]7569// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 17570// CHECK1-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 27571// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 87572// CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP11]])7573// CHECK1-NEXT: ret void7574//7575//7576// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l1427577// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {7578// CHECK1-NEXT: entry:7579// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 87580// CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 87581// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 87582// CHECK1-NEXT: [[B1:%.*]] = alloca [10 x i32], align 47583// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 87584// CHECK1-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 87585// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 87586// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 87587// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B1]], ptr align 4 [[TMP0]], i64 40, i1 false)7588// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 47589// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 17590// CHECK1-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 47591// CHECK1-NEXT: [[TMP2:%.*]] = load i8, ptr [[AAA_ADDR]], align 17592// CHECK1-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i327593// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 17594// CHECK1-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i87595// CHECK1-NEXT: store i8 [[CONV3]], ptr [[AAA_ADDR]], align 17596// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B1]], i64 0, i64 27597// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 47598// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 17599// CHECK1-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 47600// CHECK1-NEXT: ret void7601//7602//7603// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l1287604// CHECK1-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {7605// CHECK1-NEXT: entry:7606// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 87607// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 87608// CHECK1-NEXT: [[B1:%.*]] = alloca [10 x i32], align 47609// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 87610// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 87611// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 87612// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B1]], ptr align 4 [[TMP0]], i64 40, i1 false)7613// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 47614// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 17615// CHECK1-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 47616// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B1]], i64 0, i64 27617// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 47618// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 17619// CHECK1-NEXT: store i32 [[ADD2]], ptr [[ARRAYIDX]], align 47620// CHECK1-NEXT: ret void7621//7622//7623// CHECK2-LABEL: define {{[^@]+}}@_Z3fooiPd7624// CHECK2-SAME: (i32 noundef [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {7625// CHECK2-NEXT: entry:7626// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 47627// CHECK2-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 47628// CHECK2-NEXT: [[A:%.*]] = alloca i32, align 47629// CHECK2-NEXT: [[AA:%.*]] = alloca i16, align 27630// CHECK2-NEXT: [[B:%.*]] = alloca [10 x float], align 47631// CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 47632// CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 47633// CHECK2-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 87634// CHECK2-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 47635// CHECK2-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 47636// CHECK2-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 47637// CHECK2-NEXT: [[P:%.*]] = alloca ptr, align 647638// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i32, align 47639// CHECK2-NEXT: [[GA_CASTED:%.*]] = alloca i32, align 47640// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 47641// CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 47642// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 47643// CHECK2-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 87644// CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 47645// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [9 x ptr], align 47646// CHECK2-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [9 x ptr], align 47647// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [9 x ptr], align 47648// CHECK2-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 47649// CHECK2-NEXT: [[KERNEL_ARGS5:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 87650// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS8:%.*]] = alloca [2 x ptr], align 47651// CHECK2-NEXT: [[DOTOFFLOAD_PTRS9:%.*]] = alloca [2 x ptr], align 47652// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS10:%.*]] = alloca [2 x ptr], align 47653// CHECK2-NEXT: [[KERNEL_ARGS11:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 87654// CHECK2-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 47655// CHECK2-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 47656// CHECK2-NEXT: store i32 0, ptr [[A]], align 47657// CHECK2-NEXT: store i16 0, ptr [[AA]], align 27658// CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 47659// CHECK2-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()7660// CHECK2-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 47661// CHECK2-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 47662// CHECK2-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 47663// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 47664// CHECK2-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]7665// CHECK2-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 87666// CHECK2-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 47667// CHECK2-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 07668// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 47669// CHECK2-NEXT: store i32 [[TMP4]], ptr [[X]], align 47670// CHECK2-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 17671// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 47672// CHECK2-NEXT: store i32 [[TMP5]], ptr [[Y]], align 47673// CHECK2-NEXT: store ptr [[A]], ptr [[P]], align 647674// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 47675// CHECK2-NEXT: store i32 [[TMP6]], ptr [[A_CASTED]], align 47676// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[A_CASTED]], align 47677// CHECK2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[P]], align 647678// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr @ga, align 47679// CHECK2-NEXT: store i32 [[TMP9]], ptr [[GA_CASTED]], align 47680// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[GA_CASTED]], align 47681// CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 07682// CHECK2-NEXT: store i32 [[TMP7]], ptr [[TMP11]], align 47683// CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 07684// CHECK2-NEXT: store i32 [[TMP7]], ptr [[TMP12]], align 47685// CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 07686// CHECK2-NEXT: store ptr null, ptr [[TMP13]], align 47687// CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 17688// CHECK2-NEXT: store ptr [[TMP8]], ptr [[TMP14]], align 47689// CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 17690// CHECK2-NEXT: store ptr [[TMP8]], ptr [[TMP15]], align 47691// CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 17692// CHECK2-NEXT: store ptr null, ptr [[TMP16]], align 47693// CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 27694// CHECK2-NEXT: store i32 [[TMP10]], ptr [[TMP17]], align 47695// CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 27696// CHECK2-NEXT: store i32 [[TMP10]], ptr [[TMP18]], align 47697// CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 27698// CHECK2-NEXT: store ptr null, ptr [[TMP19]], align 47699// CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 07700// CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 07701// CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 07702// CHECK2-NEXT: store i32 3, ptr [[TMP22]], align 47703// CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 17704// CHECK2-NEXT: store i32 3, ptr [[TMP23]], align 47705// CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 27706// CHECK2-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 47707// CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 37708// CHECK2-NEXT: store ptr [[TMP21]], ptr [[TMP25]], align 47709// CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 47710// CHECK2-NEXT: store ptr @.offload_sizes, ptr [[TMP26]], align 47711// CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 57712// CHECK2-NEXT: store ptr @.offload_maptypes, ptr [[TMP27]], align 47713// CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 67714// CHECK2-NEXT: store ptr null, ptr [[TMP28]], align 47715// CHECK2-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 77716// CHECK2-NEXT: store ptr null, ptr [[TMP29]], align 47717// CHECK2-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 87718// CHECK2-NEXT: store i64 0, ptr [[TMP30]], align 87719// CHECK2-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 97720// CHECK2-NEXT: store i64 0, ptr [[TMP31]], align 87721// CHECK2-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 107722// CHECK2-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP32]], align 47723// CHECK2-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 117724// CHECK2-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP33]], align 47725// CHECK2-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 127726// CHECK2-NEXT: store i32 0, ptr [[TMP34]], align 47727// CHECK2-NEXT: [[TMP35:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63.region_id, ptr [[KERNEL_ARGS]])7728// CHECK2-NEXT: [[TMP36:%.*]] = icmp ne i32 [[TMP35]], 07729// CHECK2-NEXT: br i1 [[TMP36]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]7730// CHECK2: omp_offload.failed:7731// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63(i32 [[TMP7]], ptr [[TMP8]], i32 [[TMP10]]) #[[ATTR3:[0-9]+]]7732// CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]7733// CHECK2: omp_offload.cont:7734// CHECK2-NEXT: [[TMP37:%.*]] = load i16, ptr [[AA]], align 27735// CHECK2-NEXT: store i16 [[TMP37]], ptr [[AA_CASTED]], align 27736// CHECK2-NEXT: [[TMP38:%.*]] = load i32, ptr [[AA_CASTED]], align 47737// CHECK2-NEXT: [[TMP39:%.*]] = mul nuw i32 [[TMP0]], 47738// CHECK2-NEXT: [[TMP40:%.*]] = sext i32 [[TMP39]] to i647739// CHECK2-NEXT: [[TMP41:%.*]] = mul nuw i32 5, [[TMP2]]7740// CHECK2-NEXT: [[TMP42:%.*]] = mul nuw i32 [[TMP41]], 87741// CHECK2-NEXT: [[TMP43:%.*]] = sext i32 [[TMP42]] to i647742// CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.1, i32 72, i1 false)7743// CHECK2-NEXT: [[TMP44:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 07744// CHECK2-NEXT: store i32 [[TMP38]], ptr [[TMP44]], align 47745// CHECK2-NEXT: [[TMP45:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 07746// CHECK2-NEXT: store i32 [[TMP38]], ptr [[TMP45]], align 47747// CHECK2-NEXT: [[TMP46:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 07748// CHECK2-NEXT: store ptr null, ptr [[TMP46]], align 47749// CHECK2-NEXT: [[TMP47:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 17750// CHECK2-NEXT: store ptr [[B]], ptr [[TMP47]], align 47751// CHECK2-NEXT: [[TMP48:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 17752// CHECK2-NEXT: store ptr [[B]], ptr [[TMP48]], align 47753// CHECK2-NEXT: [[TMP49:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 17754// CHECK2-NEXT: store ptr null, ptr [[TMP49]], align 47755// CHECK2-NEXT: [[TMP50:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 27756// CHECK2-NEXT: store i32 [[TMP0]], ptr [[TMP50]], align 47757// CHECK2-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 27758// CHECK2-NEXT: store i32 [[TMP0]], ptr [[TMP51]], align 47759// CHECK2-NEXT: [[TMP52:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 27760// CHECK2-NEXT: store ptr null, ptr [[TMP52]], align 47761// CHECK2-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 37762// CHECK2-NEXT: store ptr [[VLA]], ptr [[TMP53]], align 47763// CHECK2-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 37764// CHECK2-NEXT: store ptr [[VLA]], ptr [[TMP54]], align 47765// CHECK2-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 37766// CHECK2-NEXT: store i64 [[TMP40]], ptr [[TMP55]], align 47767// CHECK2-NEXT: [[TMP56:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 37768// CHECK2-NEXT: store ptr null, ptr [[TMP56]], align 47769// CHECK2-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 47770// CHECK2-NEXT: store ptr [[C]], ptr [[TMP57]], align 47771// CHECK2-NEXT: [[TMP58:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 47772// CHECK2-NEXT: store ptr [[C]], ptr [[TMP58]], align 47773// CHECK2-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 47774// CHECK2-NEXT: store ptr null, ptr [[TMP59]], align 47775// CHECK2-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 57776// CHECK2-NEXT: store i32 5, ptr [[TMP60]], align 47777// CHECK2-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 57778// CHECK2-NEXT: store i32 5, ptr [[TMP61]], align 47779// CHECK2-NEXT: [[TMP62:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 57780// CHECK2-NEXT: store ptr null, ptr [[TMP62]], align 47781// CHECK2-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 67782// CHECK2-NEXT: store i32 [[TMP2]], ptr [[TMP63]], align 47783// CHECK2-NEXT: [[TMP64:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 67784// CHECK2-NEXT: store i32 [[TMP2]], ptr [[TMP64]], align 47785// CHECK2-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 67786// CHECK2-NEXT: store ptr null, ptr [[TMP65]], align 47787// CHECK2-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 77788// CHECK2-NEXT: store ptr [[VLA1]], ptr [[TMP66]], align 47789// CHECK2-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 77790// CHECK2-NEXT: store ptr [[VLA1]], ptr [[TMP67]], align 47791// CHECK2-NEXT: [[TMP68:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 77792// CHECK2-NEXT: store i64 [[TMP43]], ptr [[TMP68]], align 47793// CHECK2-NEXT: [[TMP69:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 77794// CHECK2-NEXT: store ptr null, ptr [[TMP69]], align 47795// CHECK2-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 87796// CHECK2-NEXT: store ptr [[D]], ptr [[TMP70]], align 47797// CHECK2-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 87798// CHECK2-NEXT: store ptr [[D]], ptr [[TMP71]], align 47799// CHECK2-NEXT: [[TMP72:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 87800// CHECK2-NEXT: store ptr null, ptr [[TMP72]], align 47801// CHECK2-NEXT: [[TMP73:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 07802// CHECK2-NEXT: [[TMP74:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 07803// CHECK2-NEXT: [[TMP75:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 07804// CHECK2-NEXT: [[TMP76:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 07805// CHECK2-NEXT: store i32 3, ptr [[TMP76]], align 47806// CHECK2-NEXT: [[TMP77:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 17807// CHECK2-NEXT: store i32 9, ptr [[TMP77]], align 47808// CHECK2-NEXT: [[TMP78:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 27809// CHECK2-NEXT: store ptr [[TMP73]], ptr [[TMP78]], align 47810// CHECK2-NEXT: [[TMP79:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 37811// CHECK2-NEXT: store ptr [[TMP74]], ptr [[TMP79]], align 47812// CHECK2-NEXT: [[TMP80:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 47813// CHECK2-NEXT: store ptr [[TMP75]], ptr [[TMP80]], align 47814// CHECK2-NEXT: [[TMP81:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 57815// CHECK2-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP81]], align 47816// CHECK2-NEXT: [[TMP82:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 67817// CHECK2-NEXT: store ptr null, ptr [[TMP82]], align 47818// CHECK2-NEXT: [[TMP83:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 77819// CHECK2-NEXT: store ptr null, ptr [[TMP83]], align 47820// CHECK2-NEXT: [[TMP84:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 87821// CHECK2-NEXT: store i64 0, ptr [[TMP84]], align 87822// CHECK2-NEXT: [[TMP85:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 97823// CHECK2-NEXT: store i64 0, ptr [[TMP85]], align 87824// CHECK2-NEXT: [[TMP86:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 107825// CHECK2-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP86]], align 47826// CHECK2-NEXT: [[TMP87:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 117827// CHECK2-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP87]], align 47828// CHECK2-NEXT: [[TMP88:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 127829// CHECK2-NEXT: store i32 0, ptr [[TMP88]], align 47830// CHECK2-NEXT: [[TMP89:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70.region_id, ptr [[KERNEL_ARGS5]])7831// CHECK2-NEXT: [[TMP90:%.*]] = icmp ne i32 [[TMP89]], 07832// CHECK2-NEXT: br i1 [[TMP90]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]]7833// CHECK2: omp_offload.failed6:7834// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70(i32 [[TMP38]], ptr [[B]], i32 [[TMP0]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP2]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]]7835// CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT7]]7836// CHECK2: omp_offload.cont7:7837// CHECK2-NEXT: [[TMP91:%.*]] = load ptr, ptr [[PTR_ADDR]], align 47838// CHECK2-NEXT: [[TMP92:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 07839// CHECK2-NEXT: store ptr [[TMP91]], ptr [[TMP92]], align 47840// CHECK2-NEXT: [[TMP93:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS9]], i32 0, i32 07841// CHECK2-NEXT: store ptr [[TMP91]], ptr [[TMP93]], align 47842// CHECK2-NEXT: [[TMP94:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS10]], i32 0, i32 07843// CHECK2-NEXT: store ptr null, ptr [[TMP94]], align 47844// CHECK2-NEXT: [[TMP95:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 17845// CHECK2-NEXT: store ptr [[E]], ptr [[TMP95]], align 47846// CHECK2-NEXT: [[TMP96:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS9]], i32 0, i32 17847// CHECK2-NEXT: store ptr [[E]], ptr [[TMP96]], align 47848// CHECK2-NEXT: [[TMP97:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS10]], i32 0, i32 17849// CHECK2-NEXT: store ptr null, ptr [[TMP97]], align 47850// CHECK2-NEXT: [[TMP98:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 07851// CHECK2-NEXT: [[TMP99:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS9]], i32 0, i32 07852// CHECK2-NEXT: [[TMP100:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 07853// CHECK2-NEXT: store i32 3, ptr [[TMP100]], align 47854// CHECK2-NEXT: [[TMP101:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 17855// CHECK2-NEXT: store i32 2, ptr [[TMP101]], align 47856// CHECK2-NEXT: [[TMP102:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 27857// CHECK2-NEXT: store ptr [[TMP98]], ptr [[TMP102]], align 47858// CHECK2-NEXT: [[TMP103:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 37859// CHECK2-NEXT: store ptr [[TMP99]], ptr [[TMP103]], align 47860// CHECK2-NEXT: [[TMP104:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 47861// CHECK2-NEXT: store ptr @.offload_sizes.3, ptr [[TMP104]], align 47862// CHECK2-NEXT: [[TMP105:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 57863// CHECK2-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP105]], align 47864// CHECK2-NEXT: [[TMP106:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 67865// CHECK2-NEXT: store ptr null, ptr [[TMP106]], align 47866// CHECK2-NEXT: [[TMP107:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 77867// CHECK2-NEXT: store ptr null, ptr [[TMP107]], align 47868// CHECK2-NEXT: [[TMP108:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 87869// CHECK2-NEXT: store i64 0, ptr [[TMP108]], align 87870// CHECK2-NEXT: [[TMP109:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 97871// CHECK2-NEXT: store i64 0, ptr [[TMP109]], align 87872// CHECK2-NEXT: [[TMP110:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 107873// CHECK2-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP110]], align 47874// CHECK2-NEXT: [[TMP111:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 117875// CHECK2-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP111]], align 47876// CHECK2-NEXT: [[TMP112:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 127877// CHECK2-NEXT: store i32 0, ptr [[TMP112]], align 47878// CHECK2-NEXT: [[TMP113:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111.region_id, ptr [[KERNEL_ARGS11]])7879// CHECK2-NEXT: [[TMP114:%.*]] = icmp ne i32 [[TMP113]], 07880// CHECK2-NEXT: br i1 [[TMP114]], label [[OMP_OFFLOAD_FAILED12:%.*]], label [[OMP_OFFLOAD_CONT13:%.*]]7881// CHECK2: omp_offload.failed12:7882// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111(ptr [[TMP91]], ptr [[E]]) #[[ATTR3]]7883// CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT13]]7884// CHECK2: omp_offload.cont13:7885// CHECK2-NEXT: [[TMP115:%.*]] = load i32, ptr [[A]], align 47886// CHECK2-NEXT: [[TMP116:%.*]] = load ptr, ptr [[SAVED_STACK]], align 47887// CHECK2-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP116]])7888// CHECK2-NEXT: ret i32 [[TMP115]]7889//7890//7891// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l637892// CHECK2-SAME: (i32 noundef [[A:%.*]], ptr noundef [[P:%.*]], i32 noundef [[GA:%.*]]) #[[ATTR2:[0-9]+]] {7893// CHECK2-NEXT: entry:7894// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 47895// CHECK2-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 47896// CHECK2-NEXT: [[GA_ADDR:%.*]] = alloca i32, align 47897// CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 47898// CHECK2-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 47899// CHECK2-NEXT: store i32 [[GA]], ptr [[GA_ADDR]], align 47900// CHECK2-NEXT: ret void7901//7902//7903// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l707904// CHECK2-SAME: (i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {7905// CHECK2-NEXT: entry:7906// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 47907// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 47908// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 47909// CHECK2-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 47910// CHECK2-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 47911// CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 47912// CHECK2-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 47913// CHECK2-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 47914// CHECK2-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 47915// CHECK2-NEXT: [[B5:%.*]] = alloca [10 x float], align 47916// CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 47917// CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 47918// CHECK2-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 87919// CHECK2-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 47920// CHECK2-NEXT: [[__VLA_EXPR2:%.*]] = alloca i32, align 47921// CHECK2-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 47922// CHECK2-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 47923// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 47924// CHECK2-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 47925// CHECK2-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 47926// CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 47927// CHECK2-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 47928// CHECK2-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 47929// CHECK2-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 47930// CHECK2-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 47931// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 47932// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 47933// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 47934// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 47935// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 47936// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 47937// CHECK2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 47938// CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 47939// CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B5]], ptr align 4 [[TMP0]], i32 40, i1 false)7940// CHECK2-NEXT: [[TMP8:%.*]] = call ptr @llvm.stacksave.p0()7941// CHECK2-NEXT: store ptr [[TMP8]], ptr [[SAVED_STACK]], align 47942// CHECK2-NEXT: [[VLA6:%.*]] = alloca float, i32 [[TMP1]], align 47943// CHECK2-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 47944// CHECK2-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP1]], 47945// CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VLA6]], ptr align 4 [[TMP2]], i32 [[TMP9]], i1 false)7946// CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[C7]], ptr align 8 [[TMP3]], i32 400, i1 false)7947// CHECK2-NEXT: [[TMP10:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]]7948// CHECK2-NEXT: [[VLA8:%.*]] = alloca double, i32 [[TMP10]], align 87949// CHECK2-NEXT: store i32 [[TMP4]], ptr [[__VLA_EXPR1]], align 47950// CHECK2-NEXT: store i32 [[TMP5]], ptr [[__VLA_EXPR2]], align 47951// CHECK2-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]]7952// CHECK2-NEXT: [[TMP12:%.*]] = mul nuw i32 [[TMP11]], 87953// CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[VLA8]], ptr align 8 [[TMP6]], i32 [[TMP12]], i1 false)7954// CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[D9]], ptr align 4 [[TMP7]], i32 12, i1 false)7955// CHECK2-NEXT: [[TMP13:%.*]] = load i16, ptr [[AA_ADDR]], align 27956// CHECK2-NEXT: [[CONV:%.*]] = sext i16 [[TMP13]] to i327957// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 17958// CHECK2-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i167959// CHECK2-NEXT: store i16 [[CONV10]], ptr [[AA_ADDR]], align 27960// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B5]], i32 0, i32 27961// CHECK2-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX]], align 47962// CHECK2-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, ptr [[VLA6]], i32 37963// CHECK2-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX11]], align 47964// CHECK2-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C7]], i32 0, i32 17965// CHECK2-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX12]], i32 0, i32 27966// CHECK2-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX13]], align 87967// CHECK2-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP5]]7968// CHECK2-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[VLA8]], i32 [[TMP14]]7969// CHECK2-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i32 37970// CHECK2-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX15]], align 87971// CHECK2-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D9]], i32 0, i32 07972// CHECK2-NEXT: store i64 1, ptr [[X]], align 47973// CHECK2-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D9]], i32 0, i32 17974// CHECK2-NEXT: store i8 1, ptr [[Y]], align 47975// CHECK2-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 47976// CHECK2-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP15]])7977// CHECK2-NEXT: ret void7978//7979//7980// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l1117981// CHECK2-SAME: (ptr noundef [[PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR2]] {7982// CHECK2-NEXT: entry:7983// CHECK2-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 47984// CHECK2-NEXT: [[E_ADDR:%.*]] = alloca ptr, align 47985// CHECK2-NEXT: [[E1:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 47986// CHECK2-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 47987// CHECK2-NEXT: store ptr [[E]], ptr [[E_ADDR]], align 47988// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[E_ADDR]], align 47989// CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[E1]], ptr align 4 [[TMP0]], i32 8, i1 false)7990// CHECK2-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT_0]], ptr [[E1]], i32 0, i32 07991// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[X]], align 47992// CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double7993// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[PTR_ADDR]], align 47994// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP2]], i32 07995// CHECK2-NEXT: store double [[CONV]], ptr [[ARRAYIDX]], align 47996// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[PTR_ADDR]], align 47997// CHECK2-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, ptr [[TMP3]], i32 07998// CHECK2-NEXT: [[TMP4:%.*]] = load double, ptr [[ARRAYIDX2]], align 47999// CHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+008000// CHECK2-NEXT: store double [[INC]], ptr [[ARRAYIDX2]], align 48001// CHECK2-NEXT: ret void8002//8003//8004// CHECK2-LABEL: define {{[^@]+}}@_Z3bariPd8005// CHECK2-SAME: (i32 noundef [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0]] {8006// CHECK2-NEXT: entry:8007// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 48008// CHECK2-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 48009// CHECK2-NEXT: [[A:%.*]] = alloca i32, align 48010// CHECK2-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 48011// CHECK2-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 48012// CHECK2-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 48013// CHECK2-NEXT: store i32 0, ptr [[A]], align 48014// CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 48015// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 48016// CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooiPd(i32 noundef [[TMP0]], ptr noundef [[TMP1]])8017// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 48018// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]]8019// CHECK2-NEXT: store i32 [[ADD]], ptr [[A]], align 48020// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 48021// CHECK2-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP3]])8022// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 48023// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]]8024// CHECK2-NEXT: store i32 [[ADD2]], ptr [[A]], align 48025// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 48026// CHECK2-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP5]])8027// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 48028// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]]8029// CHECK2-NEXT: store i32 [[ADD4]], ptr [[A]], align 48030// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 48031// CHECK2-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP7]])8032// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 48033// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]]8034// CHECK2-NEXT: store i32 [[ADD6]], ptr [[A]], align 48035// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 48036// CHECK2-NEXT: ret i32 [[TMP9]]8037//8038//8039// CHECK2-LABEL: define {{[^@]+}}@_ZN2S12r1Ei8040// CHECK2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {8041// CHECK2-NEXT: entry:8042// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 48043// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 48044// CHECK2-NEXT: [[B:%.*]] = alloca i32, align 48045// CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 48046// CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 48047// CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i32, align 48048// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 48049// CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 48050// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 48051// CHECK2-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 48052// CHECK2-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 88053// CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 48054// CHECK2-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 48055// CHECK2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 48056// CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 48057// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 18058// CHECK2-NEXT: store i32 [[ADD]], ptr [[B]], align 48059// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 48060// CHECK2-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()8061// CHECK2-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 48062// CHECK2-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]8063// CHECK2-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 28064// CHECK2-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 48065// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 48066// CHECK2-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 48067// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 48068// CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 08069// CHECK2-NEXT: [[TMP6:%.*]] = mul nuw i32 2, [[TMP1]]8070// CHECK2-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP6]], 28071// CHECK2-NEXT: [[TMP8:%.*]] = sext i32 [[TMP7]] to i648072// CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.5, i32 40, i1 false)8073// CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 08074// CHECK2-NEXT: store ptr [[THIS1]], ptr [[TMP9]], align 48075// CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 08076// CHECK2-NEXT: store ptr [[A]], ptr [[TMP10]], align 48077// CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 08078// CHECK2-NEXT: store ptr null, ptr [[TMP11]], align 48079// CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 18080// CHECK2-NEXT: store i32 [[TMP5]], ptr [[TMP12]], align 48081// CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 18082// CHECK2-NEXT: store i32 [[TMP5]], ptr [[TMP13]], align 48083// CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 18084// CHECK2-NEXT: store ptr null, ptr [[TMP14]], align 48085// CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 28086// CHECK2-NEXT: store i32 2, ptr [[TMP15]], align 48087// CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 28088// CHECK2-NEXT: store i32 2, ptr [[TMP16]], align 48089// CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 28090// CHECK2-NEXT: store ptr null, ptr [[TMP17]], align 48091// CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 38092// CHECK2-NEXT: store i32 [[TMP1]], ptr [[TMP18]], align 48093// CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 38094// CHECK2-NEXT: store i32 [[TMP1]], ptr [[TMP19]], align 48095// CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 38096// CHECK2-NEXT: store ptr null, ptr [[TMP20]], align 48097// CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 48098// CHECK2-NEXT: store ptr [[VLA]], ptr [[TMP21]], align 48099// CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 48100// CHECK2-NEXT: store ptr [[VLA]], ptr [[TMP22]], align 48101// CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 48102// CHECK2-NEXT: store i64 [[TMP8]], ptr [[TMP23]], align 48103// CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 48104// CHECK2-NEXT: store ptr null, ptr [[TMP24]], align 48105// CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 08106// CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 08107// CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 08108// CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 08109// CHECK2-NEXT: store i32 3, ptr [[TMP28]], align 48110// CHECK2-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 18111// CHECK2-NEXT: store i32 5, ptr [[TMP29]], align 48112// CHECK2-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 28113// CHECK2-NEXT: store ptr [[TMP25]], ptr [[TMP30]], align 48114// CHECK2-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 38115// CHECK2-NEXT: store ptr [[TMP26]], ptr [[TMP31]], align 48116// CHECK2-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 48117// CHECK2-NEXT: store ptr [[TMP27]], ptr [[TMP32]], align 48118// CHECK2-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 58119// CHECK2-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP33]], align 48120// CHECK2-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 68121// CHECK2-NEXT: store ptr null, ptr [[TMP34]], align 48122// CHECK2-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 78123// CHECK2-NEXT: store ptr null, ptr [[TMP35]], align 48124// CHECK2-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 88125// CHECK2-NEXT: store i64 0, ptr [[TMP36]], align 88126// CHECK2-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 98127// CHECK2-NEXT: store i64 0, ptr [[TMP37]], align 88128// CHECK2-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 108129// CHECK2-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP38]], align 48130// CHECK2-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 118131// CHECK2-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP39]], align 48132// CHECK2-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 128133// CHECK2-NEXT: store i32 0, ptr [[TMP40]], align 48134// CHECK2-NEXT: [[TMP41:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167.region_id, ptr [[KERNEL_ARGS]])8135// CHECK2-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 08136// CHECK2-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]8137// CHECK2: omp_offload.failed:8138// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3]]8139// CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]8140// CHECK2: omp_offload.cont:8141// CHECK2-NEXT: [[TMP43:%.*]] = mul nsw i32 1, [[TMP1]]8142// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP43]]8143// CHECK2-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 18144// CHECK2-NEXT: [[TMP44:%.*]] = load i16, ptr [[ARRAYIDX2]], align 28145// CHECK2-NEXT: [[CONV:%.*]] = sext i16 [[TMP44]] to i328146// CHECK2-NEXT: [[TMP45:%.*]] = load i32, ptr [[B]], align 48147// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP45]]8148// CHECK2-NEXT: [[TMP46:%.*]] = load ptr, ptr [[SAVED_STACK]], align 48149// CHECK2-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP46]])8150// CHECK2-NEXT: ret i32 [[ADD3]]8151//8152//8153// CHECK2-LABEL: define {{[^@]+}}@_ZL7fstatici8154// CHECK2-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {8155// CHECK2-NEXT: entry:8156// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 48157// CHECK2-NEXT: [[A:%.*]] = alloca i32, align 48158// CHECK2-NEXT: [[AAA:%.*]] = alloca i8, align 18159// CHECK2-NEXT: [[B:%.*]] = alloca [10 x i32], align 48160// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i32, align 48161// CHECK2-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 48162// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 48163// CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 48164// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 48165// CHECK2-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 88166// CHECK2-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 48167// CHECK2-NEXT: store i32 0, ptr [[A]], align 48168// CHECK2-NEXT: store i8 0, ptr [[AAA]], align 18169// CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 48170// CHECK2-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 48171// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 48172// CHECK2-NEXT: [[TMP2:%.*]] = load i8, ptr [[AAA]], align 18173// CHECK2-NEXT: store i8 [[TMP2]], ptr [[AAA_CASTED]], align 18174// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[AAA_CASTED]], align 48175// CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 08176// CHECK2-NEXT: store i32 [[TMP1]], ptr [[TMP4]], align 48177// CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 08178// CHECK2-NEXT: store i32 [[TMP1]], ptr [[TMP5]], align 48179// CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 08180// CHECK2-NEXT: store ptr null, ptr [[TMP6]], align 48181// CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 18182// CHECK2-NEXT: store i32 [[TMP3]], ptr [[TMP7]], align 48183// CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 18184// CHECK2-NEXT: store i32 [[TMP3]], ptr [[TMP8]], align 48185// CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 18186// CHECK2-NEXT: store ptr null, ptr [[TMP9]], align 48187// CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 28188// CHECK2-NEXT: store ptr [[B]], ptr [[TMP10]], align 48189// CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 28190// CHECK2-NEXT: store ptr [[B]], ptr [[TMP11]], align 48191// CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 28192// CHECK2-NEXT: store ptr null, ptr [[TMP12]], align 48193// CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 08194// CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 08195// CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 08196// CHECK2-NEXT: store i32 3, ptr [[TMP15]], align 48197// CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 18198// CHECK2-NEXT: store i32 3, ptr [[TMP16]], align 48199// CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 28200// CHECK2-NEXT: store ptr [[TMP13]], ptr [[TMP17]], align 48201// CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 38202// CHECK2-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 48203// CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 48204// CHECK2-NEXT: store ptr @.offload_sizes.7, ptr [[TMP19]], align 48205// CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 58206// CHECK2-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP20]], align 48207// CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 68208// CHECK2-NEXT: store ptr null, ptr [[TMP21]], align 48209// CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 78210// CHECK2-NEXT: store ptr null, ptr [[TMP22]], align 48211// CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 88212// CHECK2-NEXT: store i64 0, ptr [[TMP23]], align 88213// CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 98214// CHECK2-NEXT: store i64 0, ptr [[TMP24]], align 88215// CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 108216// CHECK2-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP25]], align 48217// CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 118218// CHECK2-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP26]], align 48219// CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 128220// CHECK2-NEXT: store i32 0, ptr [[TMP27]], align 48221// CHECK2-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142.region_id, ptr [[KERNEL_ARGS]])8222// CHECK2-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 08223// CHECK2-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]8224// CHECK2: omp_offload.failed:8225// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]]8226// CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]8227// CHECK2: omp_offload.cont:8228// CHECK2-NEXT: [[TMP30:%.*]] = load i32, ptr [[A]], align 48229// CHECK2-NEXT: ret i32 [[TMP30]]8230//8231//8232// CHECK2-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i8233// CHECK2-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {8234// CHECK2-NEXT: entry:8235// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 48236// CHECK2-NEXT: [[A:%.*]] = alloca i32, align 48237// CHECK2-NEXT: [[B:%.*]] = alloca [10 x i32], align 48238// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i32, align 48239// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x ptr], align 48240// CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x ptr], align 48241// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x ptr], align 48242// CHECK2-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 88243// CHECK2-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 48244// CHECK2-NEXT: store i32 0, ptr [[A]], align 48245// CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 48246// CHECK2-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 48247// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 48248// CHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 08249// CHECK2-NEXT: store i32 [[TMP1]], ptr [[TMP2]], align 48250// CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 08251// CHECK2-NEXT: store i32 [[TMP1]], ptr [[TMP3]], align 48252// CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 08253// CHECK2-NEXT: store ptr null, ptr [[TMP4]], align 48254// CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 18255// CHECK2-NEXT: store ptr [[B]], ptr [[TMP5]], align 48256// CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 18257// CHECK2-NEXT: store ptr [[B]], ptr [[TMP6]], align 48258// CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 18259// CHECK2-NEXT: store ptr null, ptr [[TMP7]], align 48260// CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 08261// CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 08262// CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 08263// CHECK2-NEXT: store i32 3, ptr [[TMP10]], align 48264// CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 18265// CHECK2-NEXT: store i32 2, ptr [[TMP11]], align 48266// CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 28267// CHECK2-NEXT: store ptr [[TMP8]], ptr [[TMP12]], align 48268// CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 38269// CHECK2-NEXT: store ptr [[TMP9]], ptr [[TMP13]], align 48270// CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 48271// CHECK2-NEXT: store ptr @.offload_sizes.9, ptr [[TMP14]], align 48272// CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 58273// CHECK2-NEXT: store ptr @.offload_maptypes.10, ptr [[TMP15]], align 48274// CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 68275// CHECK2-NEXT: store ptr null, ptr [[TMP16]], align 48276// CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 78277// CHECK2-NEXT: store ptr null, ptr [[TMP17]], align 48278// CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 88279// CHECK2-NEXT: store i64 0, ptr [[TMP18]], align 88280// CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 98281// CHECK2-NEXT: store i64 0, ptr [[TMP19]], align 88282// CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 108283// CHECK2-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP20]], align 48284// CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 118285// CHECK2-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP21]], align 48286// CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 128287// CHECK2-NEXT: store i32 0, ptr [[TMP22]], align 48288// CHECK2-NEXT: [[TMP23:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128.region_id, ptr [[KERNEL_ARGS]])8289// CHECK2-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 08290// CHECK2-NEXT: br i1 [[TMP24]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]8291// CHECK2: omp_offload.failed:8292// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128(i32 [[TMP1]], ptr [[B]]) #[[ATTR3]]8293// CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]8294// CHECK2: omp_offload.cont:8295// CHECK2-NEXT: [[TMP25:%.*]] = load i32, ptr [[A]], align 48296// CHECK2-NEXT: ret i32 [[TMP25]]8297//8298//8299// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l1678300// CHECK2-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {8301// CHECK2-NEXT: entry:8302// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 48303// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i32, align 48304// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 48305// CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 48306// CHECK2-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 48307// CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 48308// CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 48309// CHECK2-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 48310// CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 48311// CHECK2-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 48312// CHECK2-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 48313// CHECK2-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 48314// CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 48315// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 48316// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 48317// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 48318// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 48319// CHECK2-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave.p0()8320// CHECK2-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 48321// CHECK2-NEXT: [[TMP5:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]8322// CHECK2-NEXT: [[VLA3:%.*]] = alloca i16, i32 [[TMP5]], align 28323// CHECK2-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 48324// CHECK2-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 48325// CHECK2-NEXT: [[TMP6:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]8326// CHECK2-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP6]], 28327// CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 2 [[VLA3]], ptr align 2 [[TMP3]], i32 [[TMP7]], i1 false)8328// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[B_ADDR]], align 48329// CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double8330// CHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+008331// CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 08332// CHECK2-NEXT: store double [[ADD]], ptr [[A]], align 48333// CHECK2-NEXT: [[A4:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 08334// CHECK2-NEXT: [[TMP9:%.*]] = load double, ptr [[A4]], align 48335// CHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+008336// CHECK2-NEXT: store double [[INC]], ptr [[A4]], align 48337// CHECK2-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i168338// CHECK2-NEXT: [[TMP10:%.*]] = mul nsw i32 1, [[TMP2]]8339// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA3]], i32 [[TMP10]]8340// CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 18341// CHECK2-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 28342// CHECK2-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 48343// CHECK2-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP11]])8344// CHECK2-NEXT: ret void8345//8346//8347// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l1428348// CHECK2-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {8349// CHECK2-NEXT: entry:8350// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 48351// CHECK2-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 48352// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 48353// CHECK2-NEXT: [[B1:%.*]] = alloca [10 x i32], align 48354// CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 48355// CHECK2-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 48356// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 48357// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 48358// CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B1]], ptr align 4 [[TMP0]], i32 40, i1 false)8359// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 48360// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 18361// CHECK2-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 48362// CHECK2-NEXT: [[TMP2:%.*]] = load i8, ptr [[AAA_ADDR]], align 18363// CHECK2-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i328364// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 18365// CHECK2-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i88366// CHECK2-NEXT: store i8 [[CONV3]], ptr [[AAA_ADDR]], align 18367// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B1]], i32 0, i32 28368// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 48369// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 18370// CHECK2-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 48371// CHECK2-NEXT: ret void8372//8373//8374// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l1288375// CHECK2-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {8376// CHECK2-NEXT: entry:8377// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 48378// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 48379// CHECK2-NEXT: [[B1:%.*]] = alloca [10 x i32], align 48380// CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 48381// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 48382// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 48383// CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B1]], ptr align 4 [[TMP0]], i32 40, i1 false)8384// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 48385// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 18386// CHECK2-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 48387// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B1]], i32 0, i32 28388// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 48389// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 18390// CHECK2-NEXT: store i32 [[ADD2]], ptr [[ARRAYIDX]], align 48391// CHECK2-NEXT: ret void8392//8393//8394// CHECK3-LABEL: define {{[^@]+}}@_Z3fooiPd8395// CHECK3-SAME: (i32 noundef [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {8396// CHECK3-NEXT: entry:8397// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 48398// CHECK3-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 48399// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 48400// CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 28401// CHECK3-NEXT: [[B:%.*]] = alloca [10 x float], align 48402// CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 48403// CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 48404// CHECK3-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 88405// CHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 48406// CHECK3-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 48407// CHECK3-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 48408// CHECK3-NEXT: [[P:%.*]] = alloca ptr, align 648409// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 48410// CHECK3-NEXT: [[GA_CASTED:%.*]] = alloca i32, align 48411// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 48412// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 48413// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 48414// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 88415// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 48416// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [9 x ptr], align 48417// CHECK3-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [9 x ptr], align 48418// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [9 x ptr], align 48419// CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 48420// CHECK3-NEXT: [[KERNEL_ARGS5:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 88421// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS8:%.*]] = alloca [2 x ptr], align 48422// CHECK3-NEXT: [[DOTOFFLOAD_PTRS9:%.*]] = alloca [2 x ptr], align 48423// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS10:%.*]] = alloca [2 x ptr], align 48424// CHECK3-NEXT: [[KERNEL_ARGS11:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 88425// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 48426// CHECK3-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 48427// CHECK3-NEXT: store i32 0, ptr [[A]], align 48428// CHECK3-NEXT: store i16 0, ptr [[AA]], align 28429// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 48430// CHECK3-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()8431// CHECK3-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 48432// CHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 48433// CHECK3-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 48434// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 48435// CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]8436// CHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 88437// CHECK3-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 48438// CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 08439// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 48440// CHECK3-NEXT: store i32 [[TMP4]], ptr [[X]], align 48441// CHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 18442// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 48443// CHECK3-NEXT: store i32 [[TMP5]], ptr [[Y]], align 48444// CHECK3-NEXT: store ptr [[A]], ptr [[P]], align 648445// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 48446// CHECK3-NEXT: store i32 [[TMP6]], ptr [[A_CASTED]], align 48447// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[A_CASTED]], align 48448// CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[P]], align 648449// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr @ga, align 48450// CHECK3-NEXT: store i32 [[TMP9]], ptr [[GA_CASTED]], align 48451// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[GA_CASTED]], align 48452// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 08453// CHECK3-NEXT: store i32 [[TMP7]], ptr [[TMP11]], align 48454// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 08455// CHECK3-NEXT: store i32 [[TMP7]], ptr [[TMP12]], align 48456// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 08457// CHECK3-NEXT: store ptr null, ptr [[TMP13]], align 48458// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 18459// CHECK3-NEXT: store ptr [[TMP8]], ptr [[TMP14]], align 48460// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 18461// CHECK3-NEXT: store ptr [[TMP8]], ptr [[TMP15]], align 48462// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 18463// CHECK3-NEXT: store ptr null, ptr [[TMP16]], align 48464// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 28465// CHECK3-NEXT: store i32 [[TMP10]], ptr [[TMP17]], align 48466// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 28467// CHECK3-NEXT: store i32 [[TMP10]], ptr [[TMP18]], align 48468// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 28469// CHECK3-NEXT: store ptr null, ptr [[TMP19]], align 48470// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 08471// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 08472// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 08473// CHECK3-NEXT: store i32 3, ptr [[TMP22]], align 48474// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 18475// CHECK3-NEXT: store i32 3, ptr [[TMP23]], align 48476// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 28477// CHECK3-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 48478// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 38479// CHECK3-NEXT: store ptr [[TMP21]], ptr [[TMP25]], align 48480// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 48481// CHECK3-NEXT: store ptr @.offload_sizes, ptr [[TMP26]], align 48482// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 58483// CHECK3-NEXT: store ptr @.offload_maptypes, ptr [[TMP27]], align 48484// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 68485// CHECK3-NEXT: store ptr null, ptr [[TMP28]], align 48486// CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 78487// CHECK3-NEXT: store ptr null, ptr [[TMP29]], align 48488// CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 88489// CHECK3-NEXT: store i64 0, ptr [[TMP30]], align 88490// CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 98491// CHECK3-NEXT: store i64 0, ptr [[TMP31]], align 88492// CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 108493// CHECK3-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP32]], align 48494// CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 118495// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP33]], align 48496// CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 128497// CHECK3-NEXT: store i32 0, ptr [[TMP34]], align 48498// CHECK3-NEXT: [[TMP35:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63.region_id, ptr [[KERNEL_ARGS]])8499// CHECK3-NEXT: [[TMP36:%.*]] = icmp ne i32 [[TMP35]], 08500// CHECK3-NEXT: br i1 [[TMP36]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]8501// CHECK3: omp_offload.failed:8502// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63(i32 [[TMP7]], ptr [[TMP8]], i32 [[TMP10]]) #[[ATTR3:[0-9]+]]8503// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]8504// CHECK3: omp_offload.cont:8505// CHECK3-NEXT: [[TMP37:%.*]] = load i16, ptr [[AA]], align 28506// CHECK3-NEXT: store i16 [[TMP37]], ptr [[AA_CASTED]], align 28507// CHECK3-NEXT: [[TMP38:%.*]] = load i32, ptr [[AA_CASTED]], align 48508// CHECK3-NEXT: [[TMP39:%.*]] = mul nuw i32 [[TMP0]], 48509// CHECK3-NEXT: [[TMP40:%.*]] = sext i32 [[TMP39]] to i648510// CHECK3-NEXT: [[TMP41:%.*]] = mul nuw i32 5, [[TMP2]]8511// CHECK3-NEXT: [[TMP42:%.*]] = mul nuw i32 [[TMP41]], 88512// CHECK3-NEXT: [[TMP43:%.*]] = sext i32 [[TMP42]] to i648513// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.1, i32 72, i1 false)8514// CHECK3-NEXT: [[TMP44:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 08515// CHECK3-NEXT: store i32 [[TMP38]], ptr [[TMP44]], align 48516// CHECK3-NEXT: [[TMP45:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 08517// CHECK3-NEXT: store i32 [[TMP38]], ptr [[TMP45]], align 48518// CHECK3-NEXT: [[TMP46:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 08519// CHECK3-NEXT: store ptr null, ptr [[TMP46]], align 48520// CHECK3-NEXT: [[TMP47:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 18521// CHECK3-NEXT: store ptr [[B]], ptr [[TMP47]], align 48522// CHECK3-NEXT: [[TMP48:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 18523// CHECK3-NEXT: store ptr [[B]], ptr [[TMP48]], align 48524// CHECK3-NEXT: [[TMP49:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 18525// CHECK3-NEXT: store ptr null, ptr [[TMP49]], align 48526// CHECK3-NEXT: [[TMP50:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 28527// CHECK3-NEXT: store i32 [[TMP0]], ptr [[TMP50]], align 48528// CHECK3-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 28529// CHECK3-NEXT: store i32 [[TMP0]], ptr [[TMP51]], align 48530// CHECK3-NEXT: [[TMP52:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 28531// CHECK3-NEXT: store ptr null, ptr [[TMP52]], align 48532// CHECK3-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 38533// CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP53]], align 48534// CHECK3-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 38535// CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP54]], align 48536// CHECK3-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 38537// CHECK3-NEXT: store i64 [[TMP40]], ptr [[TMP55]], align 48538// CHECK3-NEXT: [[TMP56:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 38539// CHECK3-NEXT: store ptr null, ptr [[TMP56]], align 48540// CHECK3-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 48541// CHECK3-NEXT: store ptr [[C]], ptr [[TMP57]], align 48542// CHECK3-NEXT: [[TMP58:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 48543// CHECK3-NEXT: store ptr [[C]], ptr [[TMP58]], align 48544// CHECK3-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 48545// CHECK3-NEXT: store ptr null, ptr [[TMP59]], align 48546// CHECK3-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 58547// CHECK3-NEXT: store i32 5, ptr [[TMP60]], align 48548// CHECK3-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 58549// CHECK3-NEXT: store i32 5, ptr [[TMP61]], align 48550// CHECK3-NEXT: [[TMP62:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 58551// CHECK3-NEXT: store ptr null, ptr [[TMP62]], align 48552// CHECK3-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 68553// CHECK3-NEXT: store i32 [[TMP2]], ptr [[TMP63]], align 48554// CHECK3-NEXT: [[TMP64:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 68555// CHECK3-NEXT: store i32 [[TMP2]], ptr [[TMP64]], align 48556// CHECK3-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 68557// CHECK3-NEXT: store ptr null, ptr [[TMP65]], align 48558// CHECK3-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 78559// CHECK3-NEXT: store ptr [[VLA1]], ptr [[TMP66]], align 48560// CHECK3-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 78561// CHECK3-NEXT: store ptr [[VLA1]], ptr [[TMP67]], align 48562// CHECK3-NEXT: [[TMP68:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 78563// CHECK3-NEXT: store i64 [[TMP43]], ptr [[TMP68]], align 48564// CHECK3-NEXT: [[TMP69:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 78565// CHECK3-NEXT: store ptr null, ptr [[TMP69]], align 48566// CHECK3-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 88567// CHECK3-NEXT: store ptr [[D]], ptr [[TMP70]], align 48568// CHECK3-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 88569// CHECK3-NEXT: store ptr [[D]], ptr [[TMP71]], align 48570// CHECK3-NEXT: [[TMP72:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 88571// CHECK3-NEXT: store ptr null, ptr [[TMP72]], align 48572// CHECK3-NEXT: [[TMP73:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 08573// CHECK3-NEXT: [[TMP74:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 08574// CHECK3-NEXT: [[TMP75:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 08575// CHECK3-NEXT: [[TMP76:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 08576// CHECK3-NEXT: store i32 3, ptr [[TMP76]], align 48577// CHECK3-NEXT: [[TMP77:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 18578// CHECK3-NEXT: store i32 9, ptr [[TMP77]], align 48579// CHECK3-NEXT: [[TMP78:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 28580// CHECK3-NEXT: store ptr [[TMP73]], ptr [[TMP78]], align 48581// CHECK3-NEXT: [[TMP79:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 38582// CHECK3-NEXT: store ptr [[TMP74]], ptr [[TMP79]], align 48583// CHECK3-NEXT: [[TMP80:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 48584// CHECK3-NEXT: store ptr [[TMP75]], ptr [[TMP80]], align 48585// CHECK3-NEXT: [[TMP81:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 58586// CHECK3-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP81]], align 48587// CHECK3-NEXT: [[TMP82:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 68588// CHECK3-NEXT: store ptr null, ptr [[TMP82]], align 48589// CHECK3-NEXT: [[TMP83:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 78590// CHECK3-NEXT: store ptr null, ptr [[TMP83]], align 48591// CHECK3-NEXT: [[TMP84:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 88592// CHECK3-NEXT: store i64 0, ptr [[TMP84]], align 88593// CHECK3-NEXT: [[TMP85:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 98594// CHECK3-NEXT: store i64 0, ptr [[TMP85]], align 88595// CHECK3-NEXT: [[TMP86:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 108596// CHECK3-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP86]], align 48597// CHECK3-NEXT: [[TMP87:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 118598// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP87]], align 48599// CHECK3-NEXT: [[TMP88:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 128600// CHECK3-NEXT: store i32 0, ptr [[TMP88]], align 48601// CHECK3-NEXT: [[TMP89:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70.region_id, ptr [[KERNEL_ARGS5]])8602// CHECK3-NEXT: [[TMP90:%.*]] = icmp ne i32 [[TMP89]], 08603// CHECK3-NEXT: br i1 [[TMP90]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]]8604// CHECK3: omp_offload.failed6:8605// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70(i32 [[TMP38]], ptr [[B]], i32 [[TMP0]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP2]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]]8606// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT7]]8607// CHECK3: omp_offload.cont7:8608// CHECK3-NEXT: [[TMP91:%.*]] = load ptr, ptr [[PTR_ADDR]], align 48609// CHECK3-NEXT: [[TMP92:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 08610// CHECK3-NEXT: store ptr [[TMP91]], ptr [[TMP92]], align 48611// CHECK3-NEXT: [[TMP93:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS9]], i32 0, i32 08612// CHECK3-NEXT: store ptr [[TMP91]], ptr [[TMP93]], align 48613// CHECK3-NEXT: [[TMP94:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS10]], i32 0, i32 08614// CHECK3-NEXT: store ptr null, ptr [[TMP94]], align 48615// CHECK3-NEXT: [[TMP95:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 18616// CHECK3-NEXT: store ptr [[E]], ptr [[TMP95]], align 48617// CHECK3-NEXT: [[TMP96:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS9]], i32 0, i32 18618// CHECK3-NEXT: store ptr [[E]], ptr [[TMP96]], align 48619// CHECK3-NEXT: [[TMP97:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS10]], i32 0, i32 18620// CHECK3-NEXT: store ptr null, ptr [[TMP97]], align 48621// CHECK3-NEXT: [[TMP98:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 08622// CHECK3-NEXT: [[TMP99:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS9]], i32 0, i32 08623// CHECK3-NEXT: [[TMP100:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 08624// CHECK3-NEXT: store i32 3, ptr [[TMP100]], align 48625// CHECK3-NEXT: [[TMP101:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 18626// CHECK3-NEXT: store i32 2, ptr [[TMP101]], align 48627// CHECK3-NEXT: [[TMP102:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 28628// CHECK3-NEXT: store ptr [[TMP98]], ptr [[TMP102]], align 48629// CHECK3-NEXT: [[TMP103:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 38630// CHECK3-NEXT: store ptr [[TMP99]], ptr [[TMP103]], align 48631// CHECK3-NEXT: [[TMP104:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 48632// CHECK3-NEXT: store ptr @.offload_sizes.3, ptr [[TMP104]], align 48633// CHECK3-NEXT: [[TMP105:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 58634// CHECK3-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP105]], align 48635// CHECK3-NEXT: [[TMP106:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 68636// CHECK3-NEXT: store ptr null, ptr [[TMP106]], align 48637// CHECK3-NEXT: [[TMP107:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 78638// CHECK3-NEXT: store ptr null, ptr [[TMP107]], align 48639// CHECK3-NEXT: [[TMP108:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 88640// CHECK3-NEXT: store i64 0, ptr [[TMP108]], align 88641// CHECK3-NEXT: [[TMP109:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 98642// CHECK3-NEXT: store i64 0, ptr [[TMP109]], align 88643// CHECK3-NEXT: [[TMP110:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 108644// CHECK3-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP110]], align 48645// CHECK3-NEXT: [[TMP111:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 118646// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP111]], align 48647// CHECK3-NEXT: [[TMP112:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 128648// CHECK3-NEXT: store i32 0, ptr [[TMP112]], align 48649// CHECK3-NEXT: [[TMP113:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111.region_id, ptr [[KERNEL_ARGS11]])8650// CHECK3-NEXT: [[TMP114:%.*]] = icmp ne i32 [[TMP113]], 08651// CHECK3-NEXT: br i1 [[TMP114]], label [[OMP_OFFLOAD_FAILED12:%.*]], label [[OMP_OFFLOAD_CONT13:%.*]]8652// CHECK3: omp_offload.failed12:8653// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111(ptr [[TMP91]], ptr [[E]]) #[[ATTR3]]8654// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT13]]8655// CHECK3: omp_offload.cont13:8656// CHECK3-NEXT: [[TMP115:%.*]] = load i32, ptr [[A]], align 48657// CHECK3-NEXT: [[TMP116:%.*]] = load ptr, ptr [[SAVED_STACK]], align 48658// CHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP116]])8659// CHECK3-NEXT: ret i32 [[TMP115]]8660//8661//8662// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l638663// CHECK3-SAME: (i32 noundef [[A:%.*]], ptr noundef [[P:%.*]], i32 noundef [[GA:%.*]]) #[[ATTR2:[0-9]+]] {8664// CHECK3-NEXT: entry:8665// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 48666// CHECK3-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 48667// CHECK3-NEXT: [[GA_ADDR:%.*]] = alloca i32, align 48668// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 48669// CHECK3-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 48670// CHECK3-NEXT: store i32 [[GA]], ptr [[GA_ADDR]], align 48671// CHECK3-NEXT: ret void8672//8673//8674// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l708675// CHECK3-SAME: (i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {8676// CHECK3-NEXT: entry:8677// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 48678// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 48679// CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 48680// CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 48681// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 48682// CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 48683// CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 48684// CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 48685// CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 48686// CHECK3-NEXT: [[B5:%.*]] = alloca [10 x float], align 48687// CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 48688// CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 48689// CHECK3-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 88690// CHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 48691// CHECK3-NEXT: [[__VLA_EXPR2:%.*]] = alloca i32, align 48692// CHECK3-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 48693// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 48694// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 48695// CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 48696// CHECK3-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 48697// CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 48698// CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 48699// CHECK3-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 48700// CHECK3-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 48701// CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 48702// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 48703// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 48704// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 48705// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 48706// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 48707// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 48708// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 48709// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 48710// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B5]], ptr align 4 [[TMP0]], i32 40, i1 false)8711// CHECK3-NEXT: [[TMP8:%.*]] = call ptr @llvm.stacksave.p0()8712// CHECK3-NEXT: store ptr [[TMP8]], ptr [[SAVED_STACK]], align 48713// CHECK3-NEXT: [[VLA6:%.*]] = alloca float, i32 [[TMP1]], align 48714// CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 48715// CHECK3-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP1]], 48716// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VLA6]], ptr align 4 [[TMP2]], i32 [[TMP9]], i1 false)8717// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[C7]], ptr align 8 [[TMP3]], i32 400, i1 false)8718// CHECK3-NEXT: [[TMP10:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]]8719// CHECK3-NEXT: [[VLA8:%.*]] = alloca double, i32 [[TMP10]], align 88720// CHECK3-NEXT: store i32 [[TMP4]], ptr [[__VLA_EXPR1]], align 48721// CHECK3-NEXT: store i32 [[TMP5]], ptr [[__VLA_EXPR2]], align 48722// CHECK3-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]]8723// CHECK3-NEXT: [[TMP12:%.*]] = mul nuw i32 [[TMP11]], 88724// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[VLA8]], ptr align 8 [[TMP6]], i32 [[TMP12]], i1 false)8725// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[D9]], ptr align 4 [[TMP7]], i32 12, i1 false)8726// CHECK3-NEXT: [[TMP13:%.*]] = load i16, ptr [[AA_ADDR]], align 28727// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP13]] to i328728// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 18729// CHECK3-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i168730// CHECK3-NEXT: store i16 [[CONV10]], ptr [[AA_ADDR]], align 28731// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B5]], i32 0, i32 28732// CHECK3-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX]], align 48733// CHECK3-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, ptr [[VLA6]], i32 38734// CHECK3-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX11]], align 48735// CHECK3-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C7]], i32 0, i32 18736// CHECK3-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX12]], i32 0, i32 28737// CHECK3-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX13]], align 88738// CHECK3-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP5]]8739// CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[VLA8]], i32 [[TMP14]]8740// CHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i32 38741// CHECK3-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX15]], align 88742// CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D9]], i32 0, i32 08743// CHECK3-NEXT: store i64 1, ptr [[X]], align 48744// CHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D9]], i32 0, i32 18745// CHECK3-NEXT: store i8 1, ptr [[Y]], align 48746// CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 48747// CHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP15]])8748// CHECK3-NEXT: ret void8749//8750//8751// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l1118752// CHECK3-SAME: (ptr noundef [[PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR2]] {8753// CHECK3-NEXT: entry:8754// CHECK3-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 48755// CHECK3-NEXT: [[E_ADDR:%.*]] = alloca ptr, align 48756// CHECK3-NEXT: [[E1:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 48757// CHECK3-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 48758// CHECK3-NEXT: store ptr [[E]], ptr [[E_ADDR]], align 48759// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[E_ADDR]], align 48760// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[E1]], ptr align 4 [[TMP0]], i32 8, i1 false)8761// CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT_0]], ptr [[E1]], i32 0, i32 08762// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[X]], align 48763// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double8764// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[PTR_ADDR]], align 48765// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP2]], i32 08766// CHECK3-NEXT: store double [[CONV]], ptr [[ARRAYIDX]], align 48767// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[PTR_ADDR]], align 48768// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, ptr [[TMP3]], i32 08769// CHECK3-NEXT: [[TMP4:%.*]] = load double, ptr [[ARRAYIDX2]], align 48770// CHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+008771// CHECK3-NEXT: store double [[INC]], ptr [[ARRAYIDX2]], align 48772// CHECK3-NEXT: ret void8773//8774//8775// CHECK3-LABEL: define {{[^@]+}}@_Z3bariPd8776// CHECK3-SAME: (i32 noundef [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0]] {8777// CHECK3-NEXT: entry:8778// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 48779// CHECK3-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 48780// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 48781// CHECK3-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 48782// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 48783// CHECK3-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 48784// CHECK3-NEXT: store i32 0, ptr [[A]], align 48785// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 48786// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 48787// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooiPd(i32 noundef [[TMP0]], ptr noundef [[TMP1]])8788// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 48789// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]]8790// CHECK3-NEXT: store i32 [[ADD]], ptr [[A]], align 48791// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 48792// CHECK3-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP3]])8793// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 48794// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]]8795// CHECK3-NEXT: store i32 [[ADD2]], ptr [[A]], align 48796// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 48797// CHECK3-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP5]])8798// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 48799// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]]8800// CHECK3-NEXT: store i32 [[ADD4]], ptr [[A]], align 48801// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 48802// CHECK3-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP7]])8803// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 48804// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]]8805// CHECK3-NEXT: store i32 [[ADD6]], ptr [[A]], align 48806// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 48807// CHECK3-NEXT: ret i32 [[TMP9]]8808//8809//8810// CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei8811// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {8812// CHECK3-NEXT: entry:8813// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 48814// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 48815// CHECK3-NEXT: [[B:%.*]] = alloca i32, align 48816// CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 48817// CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 48818// CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 48819// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 48820// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 48821// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 48822// CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 48823// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 88824// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 48825// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 48826// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 48827// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 48828// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 18829// CHECK3-NEXT: store i32 [[ADD]], ptr [[B]], align 48830// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 48831// CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()8832// CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 48833// CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]8834// CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 28835// CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 48836// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 48837// CHECK3-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 48838// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 48839// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 08840// CHECK3-NEXT: [[TMP6:%.*]] = mul nuw i32 2, [[TMP1]]8841// CHECK3-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP6]], 28842// CHECK3-NEXT: [[TMP8:%.*]] = sext i32 [[TMP7]] to i648843// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.5, i32 40, i1 false)8844// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 08845// CHECK3-NEXT: store ptr [[THIS1]], ptr [[TMP9]], align 48846// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 08847// CHECK3-NEXT: store ptr [[A]], ptr [[TMP10]], align 48848// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 08849// CHECK3-NEXT: store ptr null, ptr [[TMP11]], align 48850// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 18851// CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP12]], align 48852// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 18853// CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP13]], align 48854// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 18855// CHECK3-NEXT: store ptr null, ptr [[TMP14]], align 48856// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 28857// CHECK3-NEXT: store i32 2, ptr [[TMP15]], align 48858// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 28859// CHECK3-NEXT: store i32 2, ptr [[TMP16]], align 48860// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 28861// CHECK3-NEXT: store ptr null, ptr [[TMP17]], align 48862// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 38863// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP18]], align 48864// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 38865// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP19]], align 48866// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 38867// CHECK3-NEXT: store ptr null, ptr [[TMP20]], align 48868// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 48869// CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP21]], align 48870// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 48871// CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP22]], align 48872// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 48873// CHECK3-NEXT: store i64 [[TMP8]], ptr [[TMP23]], align 48874// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 48875// CHECK3-NEXT: store ptr null, ptr [[TMP24]], align 48876// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 08877// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 08878// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 08879// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 08880// CHECK3-NEXT: store i32 3, ptr [[TMP28]], align 48881// CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 18882// CHECK3-NEXT: store i32 5, ptr [[TMP29]], align 48883// CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 28884// CHECK3-NEXT: store ptr [[TMP25]], ptr [[TMP30]], align 48885// CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 38886// CHECK3-NEXT: store ptr [[TMP26]], ptr [[TMP31]], align 48887// CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 48888// CHECK3-NEXT: store ptr [[TMP27]], ptr [[TMP32]], align 48889// CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 58890// CHECK3-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP33]], align 48891// CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 68892// CHECK3-NEXT: store ptr null, ptr [[TMP34]], align 48893// CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 78894// CHECK3-NEXT: store ptr null, ptr [[TMP35]], align 48895// CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 88896// CHECK3-NEXT: store i64 0, ptr [[TMP36]], align 88897// CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 98898// CHECK3-NEXT: store i64 0, ptr [[TMP37]], align 88899// CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 108900// CHECK3-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP38]], align 48901// CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 118902// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP39]], align 48903// CHECK3-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 128904// CHECK3-NEXT: store i32 0, ptr [[TMP40]], align 48905// CHECK3-NEXT: [[TMP41:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167.region_id, ptr [[KERNEL_ARGS]])8906// CHECK3-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 08907// CHECK3-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]8908// CHECK3: omp_offload.failed:8909// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3]]8910// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]8911// CHECK3: omp_offload.cont:8912// CHECK3-NEXT: [[TMP43:%.*]] = mul nsw i32 1, [[TMP1]]8913// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP43]]8914// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 18915// CHECK3-NEXT: [[TMP44:%.*]] = load i16, ptr [[ARRAYIDX2]], align 28916// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP44]] to i328917// CHECK3-NEXT: [[TMP45:%.*]] = load i32, ptr [[B]], align 48918// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP45]]8919// CHECK3-NEXT: [[TMP46:%.*]] = load ptr, ptr [[SAVED_STACK]], align 48920// CHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP46]])8921// CHECK3-NEXT: ret i32 [[ADD3]]8922//8923//8924// CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici8925// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {8926// CHECK3-NEXT: entry:8927// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 48928// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 48929// CHECK3-NEXT: [[AAA:%.*]] = alloca i8, align 18930// CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 48931// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 48932// CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 48933// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 48934// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 48935// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 48936// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 88937// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 48938// CHECK3-NEXT: store i32 0, ptr [[A]], align 48939// CHECK3-NEXT: store i8 0, ptr [[AAA]], align 18940// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 48941// CHECK3-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 48942// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 48943// CHECK3-NEXT: [[TMP2:%.*]] = load i8, ptr [[AAA]], align 18944// CHECK3-NEXT: store i8 [[TMP2]], ptr [[AAA_CASTED]], align 18945// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[AAA_CASTED]], align 48946// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 08947// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP4]], align 48948// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 08949// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP5]], align 48950// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 08951// CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 48952// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 18953// CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP7]], align 48954// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 18955// CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP8]], align 48956// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 18957// CHECK3-NEXT: store ptr null, ptr [[TMP9]], align 48958// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 28959// CHECK3-NEXT: store ptr [[B]], ptr [[TMP10]], align 48960// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 28961// CHECK3-NEXT: store ptr [[B]], ptr [[TMP11]], align 48962// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 28963// CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 48964// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 08965// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 08966// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 08967// CHECK3-NEXT: store i32 3, ptr [[TMP15]], align 48968// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 18969// CHECK3-NEXT: store i32 3, ptr [[TMP16]], align 48970// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 28971// CHECK3-NEXT: store ptr [[TMP13]], ptr [[TMP17]], align 48972// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 38973// CHECK3-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 48974// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 48975// CHECK3-NEXT: store ptr @.offload_sizes.7, ptr [[TMP19]], align 48976// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 58977// CHECK3-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP20]], align 48978// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 68979// CHECK3-NEXT: store ptr null, ptr [[TMP21]], align 48980// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 78981// CHECK3-NEXT: store ptr null, ptr [[TMP22]], align 48982// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 88983// CHECK3-NEXT: store i64 0, ptr [[TMP23]], align 88984// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 98985// CHECK3-NEXT: store i64 0, ptr [[TMP24]], align 88986// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 108987// CHECK3-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP25]], align 48988// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 118989// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP26]], align 48990// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 128991// CHECK3-NEXT: store i32 0, ptr [[TMP27]], align 48992// CHECK3-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142.region_id, ptr [[KERNEL_ARGS]])8993// CHECK3-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 08994// CHECK3-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]8995// CHECK3: omp_offload.failed:8996// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]]8997// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]8998// CHECK3: omp_offload.cont:8999// CHECK3-NEXT: [[TMP30:%.*]] = load i32, ptr [[A]], align 49000// CHECK3-NEXT: ret i32 [[TMP30]]9001//9002//9003// CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i9004// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {9005// CHECK3-NEXT: entry:9006// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 49007// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 49008// CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 49009// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 49010// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x ptr], align 49011// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x ptr], align 49012// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x ptr], align 49013// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 89014// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 49015// CHECK3-NEXT: store i32 0, ptr [[A]], align 49016// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 49017// CHECK3-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 49018// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 49019// CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 09020// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP2]], align 49021// CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 09022// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP3]], align 49023// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 09024// CHECK3-NEXT: store ptr null, ptr [[TMP4]], align 49025// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 19026// CHECK3-NEXT: store ptr [[B]], ptr [[TMP5]], align 49027// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 19028// CHECK3-NEXT: store ptr [[B]], ptr [[TMP6]], align 49029// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 19030// CHECK3-NEXT: store ptr null, ptr [[TMP7]], align 49031// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 09032// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 09033// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 09034// CHECK3-NEXT: store i32 3, ptr [[TMP10]], align 49035// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 19036// CHECK3-NEXT: store i32 2, ptr [[TMP11]], align 49037// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 29038// CHECK3-NEXT: store ptr [[TMP8]], ptr [[TMP12]], align 49039// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 39040// CHECK3-NEXT: store ptr [[TMP9]], ptr [[TMP13]], align 49041// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 49042// CHECK3-NEXT: store ptr @.offload_sizes.9, ptr [[TMP14]], align 49043// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 59044// CHECK3-NEXT: store ptr @.offload_maptypes.10, ptr [[TMP15]], align 49045// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 69046// CHECK3-NEXT: store ptr null, ptr [[TMP16]], align 49047// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 79048// CHECK3-NEXT: store ptr null, ptr [[TMP17]], align 49049// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 89050// CHECK3-NEXT: store i64 0, ptr [[TMP18]], align 89051// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 99052// CHECK3-NEXT: store i64 0, ptr [[TMP19]], align 89053// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 109054// CHECK3-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP20]], align 49055// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 119056// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP21]], align 49057// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 129058// CHECK3-NEXT: store i32 0, ptr [[TMP22]], align 49059// CHECK3-NEXT: [[TMP23:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128.region_id, ptr [[KERNEL_ARGS]])9060// CHECK3-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 09061// CHECK3-NEXT: br i1 [[TMP24]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]9062// CHECK3: omp_offload.failed:9063// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128(i32 [[TMP1]], ptr [[B]]) #[[ATTR3]]9064// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]9065// CHECK3: omp_offload.cont:9066// CHECK3-NEXT: [[TMP25:%.*]] = load i32, ptr [[A]], align 49067// CHECK3-NEXT: ret i32 [[TMP25]]9068//9069//9070// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l1679071// CHECK3-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {9072// CHECK3-NEXT: entry:9073// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 49074// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 49075// CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 49076// CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 49077// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 49078// CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 49079// CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 49080// CHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 49081// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 49082// CHECK3-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 49083// CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 49084// CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 49085// CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 49086// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 49087// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 49088// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 49089// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 49090// CHECK3-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave.p0()9091// CHECK3-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 49092// CHECK3-NEXT: [[TMP5:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]9093// CHECK3-NEXT: [[VLA3:%.*]] = alloca i16, i32 [[TMP5]], align 29094// CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 49095// CHECK3-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 49096// CHECK3-NEXT: [[TMP6:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]9097// CHECK3-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP6]], 29098// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 2 [[VLA3]], ptr align 2 [[TMP3]], i32 [[TMP7]], i1 false)9099// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[B_ADDR]], align 49100// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double9101// CHECK3-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+009102// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 09103// CHECK3-NEXT: store double [[ADD]], ptr [[A]], align 49104// CHECK3-NEXT: [[A4:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 09105// CHECK3-NEXT: [[TMP9:%.*]] = load double, ptr [[A4]], align 49106// CHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+009107// CHECK3-NEXT: store double [[INC]], ptr [[A4]], align 49108// CHECK3-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i169109// CHECK3-NEXT: [[TMP10:%.*]] = mul nsw i32 1, [[TMP2]]9110// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA3]], i32 [[TMP10]]9111// CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 19112// CHECK3-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 29113// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 49114// CHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP11]])9115// CHECK3-NEXT: ret void9116//9117//9118// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l1429119// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {9120// CHECK3-NEXT: entry:9121// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 49122// CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 49123// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 49124// CHECK3-NEXT: [[B1:%.*]] = alloca [10 x i32], align 49125// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 49126// CHECK3-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 49127// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 49128// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 49129// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B1]], ptr align 4 [[TMP0]], i32 40, i1 false)9130// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 49131// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 19132// CHECK3-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 49133// CHECK3-NEXT: [[TMP2:%.*]] = load i8, ptr [[AAA_ADDR]], align 19134// CHECK3-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i329135// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 19136// CHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i89137// CHECK3-NEXT: store i8 [[CONV3]], ptr [[AAA_ADDR]], align 19138// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B1]], i32 0, i32 29139// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 49140// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 19141// CHECK3-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 49142// CHECK3-NEXT: ret void9143//9144//9145// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l1289146// CHECK3-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {9147// CHECK3-NEXT: entry:9148// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 49149// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 49150// CHECK3-NEXT: [[B1:%.*]] = alloca [10 x i32], align 49151// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 49152// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 49153// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 49154// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B1]], ptr align 4 [[TMP0]], i32 40, i1 false)9155// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 49156// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 19157// CHECK3-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 49158// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B1]], i32 0, i32 29159// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 49160// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 19161// CHECK3-NEXT: store i32 [[ADD2]], ptr [[ARRAYIDX]], align 49162// CHECK3-NEXT: ret void9163//9164//9165// SIMD-ONLY0-LABEL: define {{[^@]+}}@_Z3fooiPd9166// SIMD-ONLY0-SAME: (i32 noundef signext [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {9167// SIMD-ONLY0-NEXT: entry:9168// SIMD-ONLY0-NEXT: [[N_ADDR:%.*]] = alloca i32, align 49169// SIMD-ONLY0-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 89170// SIMD-ONLY0-NEXT: [[A:%.*]] = alloca i32, align 49171// SIMD-ONLY0-NEXT: [[AA:%.*]] = alloca i16, align 29172// SIMD-ONLY0-NEXT: [[B:%.*]] = alloca [10 x float], align 49173// SIMD-ONLY0-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 89174// SIMD-ONLY0-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 89175// SIMD-ONLY0-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 89176// SIMD-ONLY0-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 89177// SIMD-ONLY0-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 89178// SIMD-ONLY0-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 49179// SIMD-ONLY0-NEXT: [[P:%.*]] = alloca ptr, align 649180// SIMD-ONLY0-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 49181// SIMD-ONLY0-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 89182// SIMD-ONLY0-NEXT: store i32 0, ptr [[A]], align 49183// SIMD-ONLY0-NEXT: store i16 0, ptr [[AA]], align 29184// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 49185// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i649186// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()9187// SIMD-ONLY0-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 89188// SIMD-ONLY0-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 49189// SIMD-ONLY0-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 89190// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 49191// SIMD-ONLY0-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i649192// SIMD-ONLY0-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]9193// SIMD-ONLY0-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 89194// SIMD-ONLY0-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 89195// SIMD-ONLY0-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 09196// SIMD-ONLY0-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 49197// SIMD-ONLY0-NEXT: store i32 [[TMP6]], ptr [[X]], align 49198// SIMD-ONLY0-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 19199// SIMD-ONLY0-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 49200// SIMD-ONLY0-NEXT: store i32 [[TMP7]], ptr [[Y]], align 49201// SIMD-ONLY0-NEXT: store ptr [[A]], ptr [[P]], align 649202// SIMD-ONLY0-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA]], align 29203// SIMD-ONLY0-NEXT: [[CONV:%.*]] = sext i16 [[TMP8]] to i329204// SIMD-ONLY0-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 19205// SIMD-ONLY0-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i169206// SIMD-ONLY0-NEXT: store i16 [[CONV2]], ptr [[AA]], align 29207// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i64 0, i64 29208// SIMD-ONLY0-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX]], align 49209// SIMD-ONLY0-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[VLA]], i64 39210// SIMD-ONLY0-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX3]], align 49211// SIMD-ONLY0-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i64 0, i64 19212// SIMD-ONLY0-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX4]], i64 0, i64 29213// SIMD-ONLY0-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX5]], align 89214// SIMD-ONLY0-NEXT: [[TMP9:%.*]] = mul nsw i64 1, [[TMP4]]9215// SIMD-ONLY0-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, ptr [[VLA1]], i64 [[TMP9]]9216// SIMD-ONLY0-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX6]], i64 39217// SIMD-ONLY0-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX7]], align 89218// SIMD-ONLY0-NEXT: [[X8:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D]], i32 0, i32 09219// SIMD-ONLY0-NEXT: store i64 1, ptr [[X8]], align 89220// SIMD-ONLY0-NEXT: [[Y9:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D]], i32 0, i32 19221// SIMD-ONLY0-NEXT: store i8 1, ptr [[Y9]], align 89222// SIMD-ONLY0-NEXT: [[X10:%.*]] = getelementptr inbounds nuw [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 09223// SIMD-ONLY0-NEXT: [[TMP10:%.*]] = load i32, ptr [[X10]], align 49224// SIMD-ONLY0-NEXT: [[CONV11:%.*]] = sitofp i32 [[TMP10]] to double9225// SIMD-ONLY0-NEXT: [[TMP11:%.*]] = load ptr, ptr [[PTR_ADDR]], align 89226// SIMD-ONLY0-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds double, ptr [[TMP11]], i64 09227// SIMD-ONLY0-NEXT: store double [[CONV11]], ptr [[ARRAYIDX12]], align 89228// SIMD-ONLY0-NEXT: [[TMP12:%.*]] = load ptr, ptr [[PTR_ADDR]], align 89229// SIMD-ONLY0-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, ptr [[TMP12]], i64 09230// SIMD-ONLY0-NEXT: [[TMP13:%.*]] = load double, ptr [[ARRAYIDX13]], align 89231// SIMD-ONLY0-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+009232// SIMD-ONLY0-NEXT: store double [[INC]], ptr [[ARRAYIDX13]], align 89233// SIMD-ONLY0-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 49234// SIMD-ONLY0-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 89235// SIMD-ONLY0-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP15]])9236// SIMD-ONLY0-NEXT: ret i32 [[TMP14]]9237//9238//9239// SIMD-ONLY0-LABEL: define {{[^@]+}}@_Z3bariPd9240// SIMD-ONLY0-SAME: (i32 noundef signext [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0]] {9241// SIMD-ONLY0-NEXT: entry:9242// SIMD-ONLY0-NEXT: [[N_ADDR:%.*]] = alloca i32, align 49243// SIMD-ONLY0-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 89244// SIMD-ONLY0-NEXT: [[A:%.*]] = alloca i32, align 49245// SIMD-ONLY0-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 89246// SIMD-ONLY0-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 49247// SIMD-ONLY0-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 89248// SIMD-ONLY0-NEXT: store i32 0, ptr [[A]], align 49249// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 49250// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 89251// SIMD-ONLY0-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooiPd(i32 noundef signext [[TMP0]], ptr noundef [[TMP1]])9252// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 49253// SIMD-ONLY0-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]]9254// SIMD-ONLY0-NEXT: store i32 [[ADD]], ptr [[A]], align 49255// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 49256// SIMD-ONLY0-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP3]])9257// SIMD-ONLY0-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 49258// SIMD-ONLY0-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]]9259// SIMD-ONLY0-NEXT: store i32 [[ADD2]], ptr [[A]], align 49260// SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 49261// SIMD-ONLY0-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP5]])9262// SIMD-ONLY0-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 49263// SIMD-ONLY0-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]]9264// SIMD-ONLY0-NEXT: store i32 [[ADD4]], ptr [[A]], align 49265// SIMD-ONLY0-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 49266// SIMD-ONLY0-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP7]])9267// SIMD-ONLY0-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 49268// SIMD-ONLY0-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]]9269// SIMD-ONLY0-NEXT: store i32 [[ADD6]], ptr [[A]], align 49270// SIMD-ONLY0-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 49271// SIMD-ONLY0-NEXT: ret i32 [[TMP9]]9272//9273//9274// SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN2S12r1Ei9275// SIMD-ONLY0-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {9276// SIMD-ONLY0-NEXT: entry:9277// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 89278// SIMD-ONLY0-NEXT: [[N_ADDR:%.*]] = alloca i32, align 49279// SIMD-ONLY0-NEXT: [[B:%.*]] = alloca i32, align 49280// SIMD-ONLY0-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 89281// SIMD-ONLY0-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 89282// SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 89283// SIMD-ONLY0-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 49284// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 89285// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 49286// SIMD-ONLY0-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 19287// SIMD-ONLY0-NEXT: store i32 [[ADD]], ptr [[B]], align 49288// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 49289// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i649290// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()9291// SIMD-ONLY0-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 89292// SIMD-ONLY0-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]9293// SIMD-ONLY0-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 29294// SIMD-ONLY0-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 89295// SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 49296// SIMD-ONLY0-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double9297// SIMD-ONLY0-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+009298// SIMD-ONLY0-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 09299// SIMD-ONLY0-NEXT: store double [[ADD2]], ptr [[A]], align 89300// SIMD-ONLY0-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 09301// SIMD-ONLY0-NEXT: [[TMP6:%.*]] = load double, ptr [[A3]], align 89302// SIMD-ONLY0-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+009303// SIMD-ONLY0-NEXT: store double [[INC]], ptr [[A3]], align 89304// SIMD-ONLY0-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i169305// SIMD-ONLY0-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]]9306// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP7]]9307// SIMD-ONLY0-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 19308// SIMD-ONLY0-NEXT: store i16 [[CONV4]], ptr [[ARRAYIDX5]], align 29309// SIMD-ONLY0-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]]9310// SIMD-ONLY0-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP8]]9311// SIMD-ONLY0-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX6]], i64 19312// SIMD-ONLY0-NEXT: [[TMP9:%.*]] = load i16, ptr [[ARRAYIDX7]], align 29313// SIMD-ONLY0-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i329314// SIMD-ONLY0-NEXT: [[TMP10:%.*]] = load i32, ptr [[B]], align 49315// SIMD-ONLY0-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]]9316// SIMD-ONLY0-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 89317// SIMD-ONLY0-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP11]])9318// SIMD-ONLY0-NEXT: ret i32 [[ADD9]]9319//9320//9321// SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZL7fstatici9322// SIMD-ONLY0-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {9323// SIMD-ONLY0-NEXT: entry:9324// SIMD-ONLY0-NEXT: [[N_ADDR:%.*]] = alloca i32, align 49325// SIMD-ONLY0-NEXT: [[A:%.*]] = alloca i32, align 49326// SIMD-ONLY0-NEXT: [[AAA:%.*]] = alloca i8, align 19327// SIMD-ONLY0-NEXT: [[B:%.*]] = alloca [10 x i32], align 49328// SIMD-ONLY0-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 49329// SIMD-ONLY0-NEXT: store i32 0, ptr [[A]], align 49330// SIMD-ONLY0-NEXT: store i8 0, ptr [[AAA]], align 19331// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 49332// SIMD-ONLY0-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 19333// SIMD-ONLY0-NEXT: store i32 [[ADD]], ptr [[A]], align 49334// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i8, ptr [[AAA]], align 19335// SIMD-ONLY0-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i329336// SIMD-ONLY0-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 19337// SIMD-ONLY0-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i89338// SIMD-ONLY0-NEXT: store i8 [[CONV2]], ptr [[AAA]], align 19339// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i64 0, i64 29340// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 49341// SIMD-ONLY0-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 19342// SIMD-ONLY0-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 49343// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 49344// SIMD-ONLY0-NEXT: ret i32 [[TMP3]]9345//9346//9347// SIMD-ONLY0-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i9348// SIMD-ONLY0-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {9349// SIMD-ONLY0-NEXT: entry:9350// SIMD-ONLY0-NEXT: [[N_ADDR:%.*]] = alloca i32, align 49351// SIMD-ONLY0-NEXT: [[A:%.*]] = alloca i32, align 49352// SIMD-ONLY0-NEXT: [[B:%.*]] = alloca [10 x i32], align 49353// SIMD-ONLY0-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 49354// SIMD-ONLY0-NEXT: store i32 0, ptr [[A]], align 49355// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 49356// SIMD-ONLY0-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 19357// SIMD-ONLY0-NEXT: store i32 [[ADD]], ptr [[A]], align 49358// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i64 0, i64 29359// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 49360// SIMD-ONLY0-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP1]], 19361// SIMD-ONLY0-NEXT: store i32 [[ADD1]], ptr [[ARRAYIDX]], align 49362// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 49363// SIMD-ONLY0-NEXT: ret i32 [[TMP2]]9364//9365//9366// SIMD-ONLY01-LABEL: define {{[^@]+}}@_Z3fooiPd9367// SIMD-ONLY01-SAME: (i32 noundef signext [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {9368// SIMD-ONLY01-NEXT: entry:9369// SIMD-ONLY01-NEXT: [[N_ADDR:%.*]] = alloca i32, align 49370// SIMD-ONLY01-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 89371// SIMD-ONLY01-NEXT: [[A:%.*]] = alloca i32, align 49372// SIMD-ONLY01-NEXT: [[AA:%.*]] = alloca i16, align 29373// SIMD-ONLY01-NEXT: [[B:%.*]] = alloca [10 x float], align 49374// SIMD-ONLY01-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 89375// SIMD-ONLY01-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 89376// SIMD-ONLY01-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 89377// SIMD-ONLY01-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 89378// SIMD-ONLY01-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 89379// SIMD-ONLY01-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 49380// SIMD-ONLY01-NEXT: [[P:%.*]] = alloca ptr, align 649381// SIMD-ONLY01-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 49382// SIMD-ONLY01-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 89383// SIMD-ONLY01-NEXT: store i32 0, ptr [[A]], align 49384// SIMD-ONLY01-NEXT: store i16 0, ptr [[AA]], align 29385// SIMD-ONLY01-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 49386// SIMD-ONLY01-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i649387// SIMD-ONLY01-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()9388// SIMD-ONLY01-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 89389// SIMD-ONLY01-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 49390// SIMD-ONLY01-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 89391// SIMD-ONLY01-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 49392// SIMD-ONLY01-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i649393// SIMD-ONLY01-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]9394// SIMD-ONLY01-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 89395// SIMD-ONLY01-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 89396// SIMD-ONLY01-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 09397// SIMD-ONLY01-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 49398// SIMD-ONLY01-NEXT: store i32 [[TMP6]], ptr [[X]], align 49399// SIMD-ONLY01-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 19400// SIMD-ONLY01-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 49401// SIMD-ONLY01-NEXT: store i32 [[TMP7]], ptr [[Y]], align 49402// SIMD-ONLY01-NEXT: store ptr [[A]], ptr [[P]], align 649403// SIMD-ONLY01-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA]], align 29404// SIMD-ONLY01-NEXT: [[CONV:%.*]] = sext i16 [[TMP8]] to i329405// SIMD-ONLY01-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 19406// SIMD-ONLY01-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i169407// SIMD-ONLY01-NEXT: store i16 [[CONV2]], ptr [[AA]], align 29408// SIMD-ONLY01-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i64 0, i64 29409// SIMD-ONLY01-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX]], align 49410// SIMD-ONLY01-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[VLA]], i64 39411// SIMD-ONLY01-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX3]], align 49412// SIMD-ONLY01-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i64 0, i64 19413// SIMD-ONLY01-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX4]], i64 0, i64 29414// SIMD-ONLY01-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX5]], align 89415// SIMD-ONLY01-NEXT: [[TMP9:%.*]] = mul nsw i64 1, [[TMP4]]9416// SIMD-ONLY01-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, ptr [[VLA1]], i64 [[TMP9]]9417// SIMD-ONLY01-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX6]], i64 39418// SIMD-ONLY01-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX7]], align 89419// SIMD-ONLY01-NEXT: [[X8:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D]], i32 0, i32 09420// SIMD-ONLY01-NEXT: store i64 1, ptr [[X8]], align 89421// SIMD-ONLY01-NEXT: [[Y9:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D]], i32 0, i32 19422// SIMD-ONLY01-NEXT: store i8 1, ptr [[Y9]], align 89423// SIMD-ONLY01-NEXT: [[X10:%.*]] = getelementptr inbounds nuw [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 09424// SIMD-ONLY01-NEXT: [[TMP10:%.*]] = load i32, ptr [[X10]], align 49425// SIMD-ONLY01-NEXT: [[CONV11:%.*]] = sitofp i32 [[TMP10]] to double9426// SIMD-ONLY01-NEXT: [[TMP11:%.*]] = load ptr, ptr [[PTR_ADDR]], align 89427// SIMD-ONLY01-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds double, ptr [[TMP11]], i64 09428// SIMD-ONLY01-NEXT: store double [[CONV11]], ptr [[ARRAYIDX12]], align 89429// SIMD-ONLY01-NEXT: [[TMP12:%.*]] = load ptr, ptr [[PTR_ADDR]], align 89430// SIMD-ONLY01-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, ptr [[TMP12]], i64 09431// SIMD-ONLY01-NEXT: [[TMP13:%.*]] = load double, ptr [[ARRAYIDX13]], align 89432// SIMD-ONLY01-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+009433// SIMD-ONLY01-NEXT: store double [[INC]], ptr [[ARRAYIDX13]], align 89434// SIMD-ONLY01-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 49435// SIMD-ONLY01-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 89436// SIMD-ONLY01-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP15]])9437// SIMD-ONLY01-NEXT: ret i32 [[TMP14]]9438//9439//9440// SIMD-ONLY01-LABEL: define {{[^@]+}}@_Z3bariPd9441// SIMD-ONLY01-SAME: (i32 noundef signext [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0]] {9442// SIMD-ONLY01-NEXT: entry:9443// SIMD-ONLY01-NEXT: [[N_ADDR:%.*]] = alloca i32, align 49444// SIMD-ONLY01-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 89445// SIMD-ONLY01-NEXT: [[A:%.*]] = alloca i32, align 49446// SIMD-ONLY01-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 89447// SIMD-ONLY01-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 49448// SIMD-ONLY01-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 89449// SIMD-ONLY01-NEXT: store i32 0, ptr [[A]], align 49450// SIMD-ONLY01-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 49451// SIMD-ONLY01-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 89452// SIMD-ONLY01-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooiPd(i32 noundef signext [[TMP0]], ptr noundef [[TMP1]])9453// SIMD-ONLY01-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 49454// SIMD-ONLY01-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]]9455// SIMD-ONLY01-NEXT: store i32 [[ADD]], ptr [[A]], align 49456// SIMD-ONLY01-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 49457// SIMD-ONLY01-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP3]])9458// SIMD-ONLY01-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 49459// SIMD-ONLY01-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]]9460// SIMD-ONLY01-NEXT: store i32 [[ADD2]], ptr [[A]], align 49461// SIMD-ONLY01-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 49462// SIMD-ONLY01-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP5]])9463// SIMD-ONLY01-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 49464// SIMD-ONLY01-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]]9465// SIMD-ONLY01-NEXT: store i32 [[ADD4]], ptr [[A]], align 49466// SIMD-ONLY01-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 49467// SIMD-ONLY01-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP7]])9468// SIMD-ONLY01-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 49469// SIMD-ONLY01-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]]9470// SIMD-ONLY01-NEXT: store i32 [[ADD6]], ptr [[A]], align 49471// SIMD-ONLY01-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 49472// SIMD-ONLY01-NEXT: ret i32 [[TMP9]]9473//9474//9475// SIMD-ONLY01-LABEL: define {{[^@]+}}@_ZN2S12r1Ei9476// SIMD-ONLY01-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {9477// SIMD-ONLY01-NEXT: entry:9478// SIMD-ONLY01-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 89479// SIMD-ONLY01-NEXT: [[N_ADDR:%.*]] = alloca i32, align 49480// SIMD-ONLY01-NEXT: [[B:%.*]] = alloca i32, align 49481// SIMD-ONLY01-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 89482// SIMD-ONLY01-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 89483// SIMD-ONLY01-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 89484// SIMD-ONLY01-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 49485// SIMD-ONLY01-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 89486// SIMD-ONLY01-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 49487// SIMD-ONLY01-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 19488// SIMD-ONLY01-NEXT: store i32 [[ADD]], ptr [[B]], align 49489// SIMD-ONLY01-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 49490// SIMD-ONLY01-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i649491// SIMD-ONLY01-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()9492// SIMD-ONLY01-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 89493// SIMD-ONLY01-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]9494// SIMD-ONLY01-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 29495// SIMD-ONLY01-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 89496// SIMD-ONLY01-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 49497// SIMD-ONLY01-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double9498// SIMD-ONLY01-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+009499// SIMD-ONLY01-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 09500// SIMD-ONLY01-NEXT: store double [[ADD2]], ptr [[A]], align 89501// SIMD-ONLY01-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 09502// SIMD-ONLY01-NEXT: [[TMP6:%.*]] = load double, ptr [[A3]], align 89503// SIMD-ONLY01-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+009504// SIMD-ONLY01-NEXT: store double [[INC]], ptr [[A3]], align 89505// SIMD-ONLY01-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i169506// SIMD-ONLY01-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]]9507// SIMD-ONLY01-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP7]]9508// SIMD-ONLY01-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 19509// SIMD-ONLY01-NEXT: store i16 [[CONV4]], ptr [[ARRAYIDX5]], align 29510// SIMD-ONLY01-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]]9511// SIMD-ONLY01-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP8]]9512// SIMD-ONLY01-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX6]], i64 19513// SIMD-ONLY01-NEXT: [[TMP9:%.*]] = load i16, ptr [[ARRAYIDX7]], align 29514// SIMD-ONLY01-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i329515// SIMD-ONLY01-NEXT: [[TMP10:%.*]] = load i32, ptr [[B]], align 49516// SIMD-ONLY01-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]]9517// SIMD-ONLY01-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 89518// SIMD-ONLY01-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP11]])9519// SIMD-ONLY01-NEXT: ret i32 [[ADD9]]9520//9521//9522// SIMD-ONLY01-LABEL: define {{[^@]+}}@_ZL7fstatici9523// SIMD-ONLY01-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {9524// SIMD-ONLY01-NEXT: entry:9525// SIMD-ONLY01-NEXT: [[N_ADDR:%.*]] = alloca i32, align 49526// SIMD-ONLY01-NEXT: [[A:%.*]] = alloca i32, align 49527// SIMD-ONLY01-NEXT: [[AAA:%.*]] = alloca i8, align 19528// SIMD-ONLY01-NEXT: [[B:%.*]] = alloca [10 x i32], align 49529// SIMD-ONLY01-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 49530// SIMD-ONLY01-NEXT: store i32 0, ptr [[A]], align 49531// SIMD-ONLY01-NEXT: store i8 0, ptr [[AAA]], align 19532// SIMD-ONLY01-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 49533// SIMD-ONLY01-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 19534// SIMD-ONLY01-NEXT: store i32 [[ADD]], ptr [[A]], align 49535// SIMD-ONLY01-NEXT: [[TMP1:%.*]] = load i8, ptr [[AAA]], align 19536// SIMD-ONLY01-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i329537// SIMD-ONLY01-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 19538// SIMD-ONLY01-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i89539// SIMD-ONLY01-NEXT: store i8 [[CONV2]], ptr [[AAA]], align 19540// SIMD-ONLY01-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i64 0, i64 29541// SIMD-ONLY01-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 49542// SIMD-ONLY01-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 19543// SIMD-ONLY01-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 49544// SIMD-ONLY01-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 49545// SIMD-ONLY01-NEXT: ret i32 [[TMP3]]9546//9547//9548// SIMD-ONLY01-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i9549// SIMD-ONLY01-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {9550// SIMD-ONLY01-NEXT: entry:9551// SIMD-ONLY01-NEXT: [[N_ADDR:%.*]] = alloca i32, align 49552// SIMD-ONLY01-NEXT: [[A:%.*]] = alloca i32, align 49553// SIMD-ONLY01-NEXT: [[B:%.*]] = alloca [10 x i32], align 49554// SIMD-ONLY01-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 49555// SIMD-ONLY01-NEXT: store i32 0, ptr [[A]], align 49556// SIMD-ONLY01-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 49557// SIMD-ONLY01-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 19558// SIMD-ONLY01-NEXT: store i32 [[ADD]], ptr [[A]], align 49559// SIMD-ONLY01-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i64 0, i64 29560// SIMD-ONLY01-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 49561// SIMD-ONLY01-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP1]], 19562// SIMD-ONLY01-NEXT: store i32 [[ADD1]], ptr [[ARRAYIDX]], align 49563// SIMD-ONLY01-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 49564// SIMD-ONLY01-NEXT: ret i32 [[TMP2]]9565//9566//9567// SIMD-ONLY02-LABEL: define {{[^@]+}}@_Z3fooiPd9568// SIMD-ONLY02-SAME: (i32 noundef [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {9569// SIMD-ONLY02-NEXT: entry:9570// SIMD-ONLY02-NEXT: [[N_ADDR:%.*]] = alloca i32, align 49571// SIMD-ONLY02-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 49572// SIMD-ONLY02-NEXT: [[A:%.*]] = alloca i32, align 49573// SIMD-ONLY02-NEXT: [[AA:%.*]] = alloca i16, align 29574// SIMD-ONLY02-NEXT: [[B:%.*]] = alloca [10 x float], align 49575// SIMD-ONLY02-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 49576// SIMD-ONLY02-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 49577// SIMD-ONLY02-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 89578// SIMD-ONLY02-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 49579// SIMD-ONLY02-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 49580// SIMD-ONLY02-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 49581// SIMD-ONLY02-NEXT: [[P:%.*]] = alloca ptr, align 649582// SIMD-ONLY02-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 49583// SIMD-ONLY02-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 49584// SIMD-ONLY02-NEXT: store i32 0, ptr [[A]], align 49585// SIMD-ONLY02-NEXT: store i16 0, ptr [[AA]], align 29586// SIMD-ONLY02-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 49587// SIMD-ONLY02-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()9588// SIMD-ONLY02-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 49589// SIMD-ONLY02-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 49590// SIMD-ONLY02-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 49591// SIMD-ONLY02-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 49592// SIMD-ONLY02-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]9593// SIMD-ONLY02-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 89594// SIMD-ONLY02-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 49595// SIMD-ONLY02-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 09596// SIMD-ONLY02-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 49597// SIMD-ONLY02-NEXT: store i32 [[TMP4]], ptr [[X]], align 49598// SIMD-ONLY02-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 19599// SIMD-ONLY02-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 49600// SIMD-ONLY02-NEXT: store i32 [[TMP5]], ptr [[Y]], align 49601// SIMD-ONLY02-NEXT: store ptr [[A]], ptr [[P]], align 649602// SIMD-ONLY02-NEXT: [[TMP6:%.*]] = load i16, ptr [[AA]], align 29603// SIMD-ONLY02-NEXT: [[CONV:%.*]] = sext i16 [[TMP6]] to i329604// SIMD-ONLY02-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 19605// SIMD-ONLY02-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i169606// SIMD-ONLY02-NEXT: store i16 [[CONV2]], ptr [[AA]], align 29607// SIMD-ONLY02-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i32 0, i32 29608// SIMD-ONLY02-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX]], align 49609// SIMD-ONLY02-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[VLA]], i32 39610// SIMD-ONLY02-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX3]], align 49611// SIMD-ONLY02-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i32 0, i32 19612// SIMD-ONLY02-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX4]], i32 0, i32 29613// SIMD-ONLY02-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX5]], align 89614// SIMD-ONLY02-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP2]]9615// SIMD-ONLY02-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, ptr [[VLA1]], i32 [[TMP7]]9616// SIMD-ONLY02-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX6]], i32 39617// SIMD-ONLY02-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX7]], align 89618// SIMD-ONLY02-NEXT: [[X8:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D]], i32 0, i32 09619// SIMD-ONLY02-NEXT: store i64 1, ptr [[X8]], align 49620// SIMD-ONLY02-NEXT: [[Y9:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D]], i32 0, i32 19621// SIMD-ONLY02-NEXT: store i8 1, ptr [[Y9]], align 49622// SIMD-ONLY02-NEXT: [[X10:%.*]] = getelementptr inbounds nuw [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 09623// SIMD-ONLY02-NEXT: [[TMP8:%.*]] = load i32, ptr [[X10]], align 49624// SIMD-ONLY02-NEXT: [[CONV11:%.*]] = sitofp i32 [[TMP8]] to double9625// SIMD-ONLY02-NEXT: [[TMP9:%.*]] = load ptr, ptr [[PTR_ADDR]], align 49626// SIMD-ONLY02-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds double, ptr [[TMP9]], i32 09627// SIMD-ONLY02-NEXT: store double [[CONV11]], ptr [[ARRAYIDX12]], align 49628// SIMD-ONLY02-NEXT: [[TMP10:%.*]] = load ptr, ptr [[PTR_ADDR]], align 49629// SIMD-ONLY02-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, ptr [[TMP10]], i32 09630// SIMD-ONLY02-NEXT: [[TMP11:%.*]] = load double, ptr [[ARRAYIDX13]], align 49631// SIMD-ONLY02-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+009632// SIMD-ONLY02-NEXT: store double [[INC]], ptr [[ARRAYIDX13]], align 49633// SIMD-ONLY02-NEXT: [[TMP12:%.*]] = load i32, ptr [[A]], align 49634// SIMD-ONLY02-NEXT: [[TMP13:%.*]] = load ptr, ptr [[SAVED_STACK]], align 49635// SIMD-ONLY02-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP13]])9636// SIMD-ONLY02-NEXT: ret i32 [[TMP12]]9637//9638//9639// SIMD-ONLY02-LABEL: define {{[^@]+}}@_Z3bariPd9640// SIMD-ONLY02-SAME: (i32 noundef [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0]] {9641// SIMD-ONLY02-NEXT: entry:9642// SIMD-ONLY02-NEXT: [[N_ADDR:%.*]] = alloca i32, align 49643// SIMD-ONLY02-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 49644// SIMD-ONLY02-NEXT: [[A:%.*]] = alloca i32, align 49645// SIMD-ONLY02-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 49646// SIMD-ONLY02-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 49647// SIMD-ONLY02-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 49648// SIMD-ONLY02-NEXT: store i32 0, ptr [[A]], align 49649// SIMD-ONLY02-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 49650// SIMD-ONLY02-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 49651// SIMD-ONLY02-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooiPd(i32 noundef [[TMP0]], ptr noundef [[TMP1]])9652// SIMD-ONLY02-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 49653// SIMD-ONLY02-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]]9654// SIMD-ONLY02-NEXT: store i32 [[ADD]], ptr [[A]], align 49655// SIMD-ONLY02-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 49656// SIMD-ONLY02-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP3]])9657// SIMD-ONLY02-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 49658// SIMD-ONLY02-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]]9659// SIMD-ONLY02-NEXT: store i32 [[ADD2]], ptr [[A]], align 49660// SIMD-ONLY02-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 49661// SIMD-ONLY02-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP5]])9662// SIMD-ONLY02-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 49663// SIMD-ONLY02-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]]9664// SIMD-ONLY02-NEXT: store i32 [[ADD4]], ptr [[A]], align 49665// SIMD-ONLY02-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 49666// SIMD-ONLY02-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP7]])9667// SIMD-ONLY02-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 49668// SIMD-ONLY02-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]]9669// SIMD-ONLY02-NEXT: store i32 [[ADD6]], ptr [[A]], align 49670// SIMD-ONLY02-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 49671// SIMD-ONLY02-NEXT: ret i32 [[TMP9]]9672//9673//9674// SIMD-ONLY02-LABEL: define {{[^@]+}}@_ZN2S12r1Ei9675// SIMD-ONLY02-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {9676// SIMD-ONLY02-NEXT: entry:9677// SIMD-ONLY02-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 49678// SIMD-ONLY02-NEXT: [[N_ADDR:%.*]] = alloca i32, align 49679// SIMD-ONLY02-NEXT: [[B:%.*]] = alloca i32, align 49680// SIMD-ONLY02-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 49681// SIMD-ONLY02-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 49682// SIMD-ONLY02-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 49683// SIMD-ONLY02-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 49684// SIMD-ONLY02-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 49685// SIMD-ONLY02-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 49686// SIMD-ONLY02-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 19687// SIMD-ONLY02-NEXT: store i32 [[ADD]], ptr [[B]], align 49688// SIMD-ONLY02-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 49689// SIMD-ONLY02-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()9690// SIMD-ONLY02-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 49691// SIMD-ONLY02-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]9692// SIMD-ONLY02-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 29693// SIMD-ONLY02-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 49694// SIMD-ONLY02-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 49695// SIMD-ONLY02-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double9696// SIMD-ONLY02-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+009697// SIMD-ONLY02-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 09698// SIMD-ONLY02-NEXT: store double [[ADD2]], ptr [[A]], align 49699// SIMD-ONLY02-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 09700// SIMD-ONLY02-NEXT: [[TMP5:%.*]] = load double, ptr [[A3]], align 49701// SIMD-ONLY02-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+009702// SIMD-ONLY02-NEXT: store double [[INC]], ptr [[A3]], align 49703// SIMD-ONLY02-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i169704// SIMD-ONLY02-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]]9705// SIMD-ONLY02-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP6]]9706// SIMD-ONLY02-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 19707// SIMD-ONLY02-NEXT: store i16 [[CONV4]], ptr [[ARRAYIDX5]], align 29708// SIMD-ONLY02-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]]9709// SIMD-ONLY02-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP7]]9710// SIMD-ONLY02-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX6]], i32 19711// SIMD-ONLY02-NEXT: [[TMP8:%.*]] = load i16, ptr [[ARRAYIDX7]], align 29712// SIMD-ONLY02-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i329713// SIMD-ONLY02-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 49714// SIMD-ONLY02-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]]9715// SIMD-ONLY02-NEXT: [[TMP10:%.*]] = load ptr, ptr [[SAVED_STACK]], align 49716// SIMD-ONLY02-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP10]])9717// SIMD-ONLY02-NEXT: ret i32 [[ADD9]]9718//9719//9720// SIMD-ONLY02-LABEL: define {{[^@]+}}@_ZL7fstatici9721// SIMD-ONLY02-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {9722// SIMD-ONLY02-NEXT: entry:9723// SIMD-ONLY02-NEXT: [[N_ADDR:%.*]] = alloca i32, align 49724// SIMD-ONLY02-NEXT: [[A:%.*]] = alloca i32, align 49725// SIMD-ONLY02-NEXT: [[AAA:%.*]] = alloca i8, align 19726// SIMD-ONLY02-NEXT: [[B:%.*]] = alloca [10 x i32], align 49727// SIMD-ONLY02-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 49728// SIMD-ONLY02-NEXT: store i32 0, ptr [[A]], align 49729// SIMD-ONLY02-NEXT: store i8 0, ptr [[AAA]], align 19730// SIMD-ONLY02-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 49731// SIMD-ONLY02-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 19732// SIMD-ONLY02-NEXT: store i32 [[ADD]], ptr [[A]], align 49733// SIMD-ONLY02-NEXT: [[TMP1:%.*]] = load i8, ptr [[AAA]], align 19734// SIMD-ONLY02-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i329735// SIMD-ONLY02-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 19736// SIMD-ONLY02-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i89737// SIMD-ONLY02-NEXT: store i8 [[CONV2]], ptr [[AAA]], align 19738// SIMD-ONLY02-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i32 0, i32 29739// SIMD-ONLY02-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 49740// SIMD-ONLY02-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 19741// SIMD-ONLY02-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 49742// SIMD-ONLY02-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 49743// SIMD-ONLY02-NEXT: ret i32 [[TMP3]]9744//9745//9746// SIMD-ONLY02-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i9747// SIMD-ONLY02-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {9748// SIMD-ONLY02-NEXT: entry:9749// SIMD-ONLY02-NEXT: [[N_ADDR:%.*]] = alloca i32, align 49750// SIMD-ONLY02-NEXT: [[A:%.*]] = alloca i32, align 49751// SIMD-ONLY02-NEXT: [[B:%.*]] = alloca [10 x i32], align 49752// SIMD-ONLY02-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 49753// SIMD-ONLY02-NEXT: store i32 0, ptr [[A]], align 49754// SIMD-ONLY02-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 49755// SIMD-ONLY02-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 19756// SIMD-ONLY02-NEXT: store i32 [[ADD]], ptr [[A]], align 49757// SIMD-ONLY02-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i32 0, i32 29758// SIMD-ONLY02-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 49759// SIMD-ONLY02-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP1]], 19760// SIMD-ONLY02-NEXT: store i32 [[ADD1]], ptr [[ARRAYIDX]], align 49761// SIMD-ONLY02-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 49762// SIMD-ONLY02-NEXT: ret i32 [[TMP2]]9763//9764//9765// SIMD-ONLY03-LABEL: define {{[^@]+}}@_Z3fooiPd9766// SIMD-ONLY03-SAME: (i32 noundef [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {9767// SIMD-ONLY03-NEXT: entry:9768// SIMD-ONLY03-NEXT: [[N_ADDR:%.*]] = alloca i32, align 49769// SIMD-ONLY03-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 49770// SIMD-ONLY03-NEXT: [[A:%.*]] = alloca i32, align 49771// SIMD-ONLY03-NEXT: [[AA:%.*]] = alloca i16, align 29772// SIMD-ONLY03-NEXT: [[B:%.*]] = alloca [10 x float], align 49773// SIMD-ONLY03-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 49774// SIMD-ONLY03-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 49775// SIMD-ONLY03-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 89776// SIMD-ONLY03-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 49777// SIMD-ONLY03-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 49778// SIMD-ONLY03-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 49779// SIMD-ONLY03-NEXT: [[P:%.*]] = alloca ptr, align 649780// SIMD-ONLY03-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 49781// SIMD-ONLY03-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 49782// SIMD-ONLY03-NEXT: store i32 0, ptr [[A]], align 49783// SIMD-ONLY03-NEXT: store i16 0, ptr [[AA]], align 29784// SIMD-ONLY03-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 49785// SIMD-ONLY03-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()9786// SIMD-ONLY03-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 49787// SIMD-ONLY03-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 49788// SIMD-ONLY03-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 49789// SIMD-ONLY03-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 49790// SIMD-ONLY03-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]9791// SIMD-ONLY03-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 89792// SIMD-ONLY03-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 49793// SIMD-ONLY03-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 09794// SIMD-ONLY03-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 49795// SIMD-ONLY03-NEXT: store i32 [[TMP4]], ptr [[X]], align 49796// SIMD-ONLY03-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 19797// SIMD-ONLY03-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 49798// SIMD-ONLY03-NEXT: store i32 [[TMP5]], ptr [[Y]], align 49799// SIMD-ONLY03-NEXT: store ptr [[A]], ptr [[P]], align 649800// SIMD-ONLY03-NEXT: [[TMP6:%.*]] = load i16, ptr [[AA]], align 29801// SIMD-ONLY03-NEXT: [[CONV:%.*]] = sext i16 [[TMP6]] to i329802// SIMD-ONLY03-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 19803// SIMD-ONLY03-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i169804// SIMD-ONLY03-NEXT: store i16 [[CONV2]], ptr [[AA]], align 29805// SIMD-ONLY03-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i32 0, i32 29806// SIMD-ONLY03-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX]], align 49807// SIMD-ONLY03-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[VLA]], i32 39808// SIMD-ONLY03-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX3]], align 49809// SIMD-ONLY03-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i32 0, i32 19810// SIMD-ONLY03-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX4]], i32 0, i32 29811// SIMD-ONLY03-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX5]], align 89812// SIMD-ONLY03-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP2]]9813// SIMD-ONLY03-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, ptr [[VLA1]], i32 [[TMP7]]9814// SIMD-ONLY03-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX6]], i32 39815// SIMD-ONLY03-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX7]], align 89816// SIMD-ONLY03-NEXT: [[X8:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D]], i32 0, i32 09817// SIMD-ONLY03-NEXT: store i64 1, ptr [[X8]], align 49818// SIMD-ONLY03-NEXT: [[Y9:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D]], i32 0, i32 19819// SIMD-ONLY03-NEXT: store i8 1, ptr [[Y9]], align 49820// SIMD-ONLY03-NEXT: [[X10:%.*]] = getelementptr inbounds nuw [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 09821// SIMD-ONLY03-NEXT: [[TMP8:%.*]] = load i32, ptr [[X10]], align 49822// SIMD-ONLY03-NEXT: [[CONV11:%.*]] = sitofp i32 [[TMP8]] to double9823// SIMD-ONLY03-NEXT: [[TMP9:%.*]] = load ptr, ptr [[PTR_ADDR]], align 49824// SIMD-ONLY03-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds double, ptr [[TMP9]], i32 09825// SIMD-ONLY03-NEXT: store double [[CONV11]], ptr [[ARRAYIDX12]], align 49826// SIMD-ONLY03-NEXT: [[TMP10:%.*]] = load ptr, ptr [[PTR_ADDR]], align 49827// SIMD-ONLY03-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, ptr [[TMP10]], i32 09828// SIMD-ONLY03-NEXT: [[TMP11:%.*]] = load double, ptr [[ARRAYIDX13]], align 49829// SIMD-ONLY03-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+009830// SIMD-ONLY03-NEXT: store double [[INC]], ptr [[ARRAYIDX13]], align 49831// SIMD-ONLY03-NEXT: [[TMP12:%.*]] = load i32, ptr [[A]], align 49832// SIMD-ONLY03-NEXT: [[TMP13:%.*]] = load ptr, ptr [[SAVED_STACK]], align 49833// SIMD-ONLY03-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP13]])9834// SIMD-ONLY03-NEXT: ret i32 [[TMP12]]9835//9836//9837// SIMD-ONLY03-LABEL: define {{[^@]+}}@_Z3bariPd9838// SIMD-ONLY03-SAME: (i32 noundef [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0]] {9839// SIMD-ONLY03-NEXT: entry:9840// SIMD-ONLY03-NEXT: [[N_ADDR:%.*]] = alloca i32, align 49841// SIMD-ONLY03-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 49842// SIMD-ONLY03-NEXT: [[A:%.*]] = alloca i32, align 49843// SIMD-ONLY03-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 49844// SIMD-ONLY03-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 49845// SIMD-ONLY03-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 49846// SIMD-ONLY03-NEXT: store i32 0, ptr [[A]], align 49847// SIMD-ONLY03-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 49848// SIMD-ONLY03-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 49849// SIMD-ONLY03-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooiPd(i32 noundef [[TMP0]], ptr noundef [[TMP1]])9850// SIMD-ONLY03-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 49851// SIMD-ONLY03-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]]9852// SIMD-ONLY03-NEXT: store i32 [[ADD]], ptr [[A]], align 49853// SIMD-ONLY03-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 49854// SIMD-ONLY03-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP3]])9855// SIMD-ONLY03-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 49856// SIMD-ONLY03-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]]9857// SIMD-ONLY03-NEXT: store i32 [[ADD2]], ptr [[A]], align 49858// SIMD-ONLY03-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 49859// SIMD-ONLY03-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP5]])9860// SIMD-ONLY03-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 49861// SIMD-ONLY03-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]]9862// SIMD-ONLY03-NEXT: store i32 [[ADD4]], ptr [[A]], align 49863// SIMD-ONLY03-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 49864// SIMD-ONLY03-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP7]])9865// SIMD-ONLY03-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 49866// SIMD-ONLY03-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]]9867// SIMD-ONLY03-NEXT: store i32 [[ADD6]], ptr [[A]], align 49868// SIMD-ONLY03-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 49869// SIMD-ONLY03-NEXT: ret i32 [[TMP9]]9870//9871//9872// SIMD-ONLY03-LABEL: define {{[^@]+}}@_ZN2S12r1Ei9873// SIMD-ONLY03-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {9874// SIMD-ONLY03-NEXT: entry:9875// SIMD-ONLY03-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 49876// SIMD-ONLY03-NEXT: [[N_ADDR:%.*]] = alloca i32, align 49877// SIMD-ONLY03-NEXT: [[B:%.*]] = alloca i32, align 49878// SIMD-ONLY03-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 49879// SIMD-ONLY03-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 49880// SIMD-ONLY03-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 49881// SIMD-ONLY03-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 49882// SIMD-ONLY03-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 49883// SIMD-ONLY03-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 49884// SIMD-ONLY03-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 19885// SIMD-ONLY03-NEXT: store i32 [[ADD]], ptr [[B]], align 49886// SIMD-ONLY03-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 49887// SIMD-ONLY03-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()9888// SIMD-ONLY03-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 49889// SIMD-ONLY03-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]9890// SIMD-ONLY03-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 29891// SIMD-ONLY03-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 49892// SIMD-ONLY03-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 49893// SIMD-ONLY03-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double9894// SIMD-ONLY03-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+009895// SIMD-ONLY03-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 09896// SIMD-ONLY03-NEXT: store double [[ADD2]], ptr [[A]], align 49897// SIMD-ONLY03-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 09898// SIMD-ONLY03-NEXT: [[TMP5:%.*]] = load double, ptr [[A3]], align 49899// SIMD-ONLY03-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+009900// SIMD-ONLY03-NEXT: store double [[INC]], ptr [[A3]], align 49901// SIMD-ONLY03-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i169902// SIMD-ONLY03-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]]9903// SIMD-ONLY03-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP6]]9904// SIMD-ONLY03-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 19905// SIMD-ONLY03-NEXT: store i16 [[CONV4]], ptr [[ARRAYIDX5]], align 29906// SIMD-ONLY03-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]]9907// SIMD-ONLY03-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP7]]9908// SIMD-ONLY03-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX6]], i32 19909// SIMD-ONLY03-NEXT: [[TMP8:%.*]] = load i16, ptr [[ARRAYIDX7]], align 29910// SIMD-ONLY03-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i329911// SIMD-ONLY03-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 49912// SIMD-ONLY03-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]]9913// SIMD-ONLY03-NEXT: [[TMP10:%.*]] = load ptr, ptr [[SAVED_STACK]], align 49914// SIMD-ONLY03-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP10]])9915// SIMD-ONLY03-NEXT: ret i32 [[ADD9]]9916//9917//9918// SIMD-ONLY03-LABEL: define {{[^@]+}}@_ZL7fstatici9919// SIMD-ONLY03-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {9920// SIMD-ONLY03-NEXT: entry:9921// SIMD-ONLY03-NEXT: [[N_ADDR:%.*]] = alloca i32, align 49922// SIMD-ONLY03-NEXT: [[A:%.*]] = alloca i32, align 49923// SIMD-ONLY03-NEXT: [[AAA:%.*]] = alloca i8, align 19924// SIMD-ONLY03-NEXT: [[B:%.*]] = alloca [10 x i32], align 49925// SIMD-ONLY03-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 49926// SIMD-ONLY03-NEXT: store i32 0, ptr [[A]], align 49927// SIMD-ONLY03-NEXT: store i8 0, ptr [[AAA]], align 19928// SIMD-ONLY03-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 49929// SIMD-ONLY03-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 19930// SIMD-ONLY03-NEXT: store i32 [[ADD]], ptr [[A]], align 49931// SIMD-ONLY03-NEXT: [[TMP1:%.*]] = load i8, ptr [[AAA]], align 19932// SIMD-ONLY03-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i329933// SIMD-ONLY03-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 19934// SIMD-ONLY03-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i89935// SIMD-ONLY03-NEXT: store i8 [[CONV2]], ptr [[AAA]], align 19936// SIMD-ONLY03-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i32 0, i32 29937// SIMD-ONLY03-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 49938// SIMD-ONLY03-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 19939// SIMD-ONLY03-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 49940// SIMD-ONLY03-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 49941// SIMD-ONLY03-NEXT: ret i32 [[TMP3]]9942//9943//9944// SIMD-ONLY03-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i9945// SIMD-ONLY03-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {9946// SIMD-ONLY03-NEXT: entry:9947// SIMD-ONLY03-NEXT: [[N_ADDR:%.*]] = alloca i32, align 49948// SIMD-ONLY03-NEXT: [[A:%.*]] = alloca i32, align 49949// SIMD-ONLY03-NEXT: [[B:%.*]] = alloca [10 x i32], align 49950// SIMD-ONLY03-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 49951// SIMD-ONLY03-NEXT: store i32 0, ptr [[A]], align 49952// SIMD-ONLY03-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 49953// SIMD-ONLY03-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 19954// SIMD-ONLY03-NEXT: store i32 [[ADD]], ptr [[A]], align 49955// SIMD-ONLY03-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i32 0, i32 29956// SIMD-ONLY03-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 49957// SIMD-ONLY03-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP1]], 19958// SIMD-ONLY03-NEXT: store i32 [[ADD1]], ptr [[ARRAYIDX]], align 49959// SIMD-ONLY03-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 49960// SIMD-ONLY03-NEXT: ret i32 [[TMP2]]9961//9962//9963// TCHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l639964// TCHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], ptr noundef [[P:%.*]], i64 noundef [[GA:%.*]]) #[[ATTR0:[0-9]+]] {9965// TCHECK-NEXT: entry:9966// TCHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 89967// TCHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 89968// TCHECK-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 89969// TCHECK-NEXT: [[GA_ADDR:%.*]] = alloca i64, align 89970// TCHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 89971// TCHECK-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 89972// TCHECK-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 89973// TCHECK-NEXT: store i64 [[GA]], ptr [[GA_ADDR]], align 89974// TCHECK-NEXT: ret void9975//9976//9977// TCHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l709978// TCHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {9979// TCHECK-NEXT: entry:9980// TCHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 89981// TCHECK-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 89982// TCHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 89983// TCHECK-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 89984// TCHECK-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 89985// TCHECK-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 89986// TCHECK-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 89987// TCHECK-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 89988// TCHECK-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 89989// TCHECK-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 89990// TCHECK-NEXT: [[B5:%.*]] = alloca [10 x float], align 49991// TCHECK-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 89992// TCHECK-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 89993// TCHECK-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 89994// TCHECK-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 89995// TCHECK-NEXT: [[__VLA_EXPR2:%.*]] = alloca i64, align 89996// TCHECK-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 89997// TCHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 89998// TCHECK-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 89999// TCHECK-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 810000// TCHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 810001// TCHECK-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 810002// TCHECK-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 810003// TCHECK-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 810004// TCHECK-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 810005// TCHECK-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 810006// TCHECK-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 810007// TCHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 810008// TCHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 810009// TCHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 810010// TCHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 810011// TCHECK-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 810012// TCHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 810013// TCHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 810014// TCHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 810015// TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B5]], ptr align 4 [[TMP0]], i64 40, i1 false)10016// TCHECK-NEXT: [[TMP8:%.*]] = call ptr @llvm.stacksave.p0()10017// TCHECK-NEXT: store ptr [[TMP8]], ptr [[SAVED_STACK]], align 810018// TCHECK-NEXT: [[VLA6:%.*]] = alloca float, i64 [[TMP1]], align 410019// TCHECK-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 810020// TCHECK-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP1]], 410021// TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VLA6]], ptr align 4 [[TMP2]], i64 [[TMP9]], i1 false)10022// TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[C7]], ptr align 8 [[TMP3]], i64 400, i1 false)10023// TCHECK-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]]10024// TCHECK-NEXT: [[VLA8:%.*]] = alloca double, i64 [[TMP10]], align 810025// TCHECK-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 810026// TCHECK-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR2]], align 810027// TCHECK-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]]10028// TCHECK-NEXT: [[TMP12:%.*]] = mul nuw i64 [[TMP11]], 810029// TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[VLA8]], ptr align 8 [[TMP6]], i64 [[TMP12]], i1 false)10030// TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[D9]], ptr align 8 [[TMP7]], i64 16, i1 false)10031// TCHECK-NEXT: [[TMP13:%.*]] = load i16, ptr [[AA_ADDR]], align 210032// TCHECK-NEXT: [[CONV:%.*]] = sext i16 [[TMP13]] to i3210033// TCHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 110034// TCHECK-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i1610035// TCHECK-NEXT: store i16 [[CONV10]], ptr [[AA_ADDR]], align 210036// TCHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B5]], i64 0, i64 210037// TCHECK-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX]], align 410038// TCHECK-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, ptr [[VLA6]], i64 310039// TCHECK-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX11]], align 410040// TCHECK-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C7]], i64 0, i64 110041// TCHECK-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX12]], i64 0, i64 210042// TCHECK-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX13]], align 810043// TCHECK-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP5]]10044// TCHECK-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[VLA8]], i64 [[TMP14]]10045// TCHECK-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i64 310046// TCHECK-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX15]], align 810047// TCHECK-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D9]], i32 0, i32 010048// TCHECK-NEXT: store i64 1, ptr [[X]], align 810049// TCHECK-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D9]], i32 0, i32 110050// TCHECK-NEXT: store i8 1, ptr [[Y]], align 810051// TCHECK-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 810052// TCHECK-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP15]])10053// TCHECK-NEXT: ret void10054//10055//10056// TCHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l11110057// TCHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR0]] {10058// TCHECK-NEXT: entry:10059// TCHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 810060// TCHECK-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 810061// TCHECK-NEXT: [[E_ADDR:%.*]] = alloca ptr, align 810062// TCHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 810063// TCHECK-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 810064// TCHECK-NEXT: store ptr [[E]], ptr [[E_ADDR]], align 810065// TCHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[E_ADDR]], align 810066// TCHECK-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT_0:%.*]], ptr [[TMP0]], i32 0, i32 010067// TCHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[X]], align 410068// TCHECK-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double10069// TCHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[PTR_ADDR]], align 810070// TCHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP2]], i64 010071// TCHECK-NEXT: store double [[CONV]], ptr [[ARRAYIDX]], align 810072// TCHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[PTR_ADDR]], align 810073// TCHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds double, ptr [[TMP3]], i64 010074// TCHECK-NEXT: [[TMP4:%.*]] = load double, ptr [[ARRAYIDX1]], align 810075// TCHECK-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+0010076// TCHECK-NEXT: store double [[INC]], ptr [[ARRAYIDX1]], align 810077// TCHECK-NEXT: ret void10078//10079//10080// TCHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l14210081// TCHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {10082// TCHECK-NEXT: entry:10083// TCHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 810084// TCHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 810085// TCHECK-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 810086// TCHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 810087// TCHECK-NEXT: [[B1:%.*]] = alloca [10 x i32], align 410088// TCHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 810089// TCHECK-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 810090// TCHECK-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 810091// TCHECK-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 810092// TCHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 810093// TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B1]], ptr align 4 [[TMP0]], i64 40, i1 false)10094// TCHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 410095// TCHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 110096// TCHECK-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 410097// TCHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[AAA_ADDR]], align 110098// TCHECK-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i3210099// TCHECK-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 110100// TCHECK-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i810101// TCHECK-NEXT: store i8 [[CONV3]], ptr [[AAA_ADDR]], align 110102// TCHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B1]], i64 0, i64 210103// TCHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 410104// TCHECK-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 110105// TCHECK-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 410106// TCHECK-NEXT: ret void10107//10108//10109// TCHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l16710110// TCHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {10111// TCHECK-NEXT: entry:10112// TCHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 810113// TCHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 810114// TCHECK-NEXT: [[B_ADDR:%.*]] = alloca i64, align 810115// TCHECK-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 810116// TCHECK-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 810117// TCHECK-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 810118// TCHECK-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 810119// TCHECK-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 810120// TCHECK-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 810121// TCHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 810122// TCHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 810123// TCHECK-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 810124// TCHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 810125// TCHECK-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 810126// TCHECK-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 810127// TCHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 810128// TCHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 810129// TCHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 810130// TCHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 810131// TCHECK-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave.p0()10132// TCHECK-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 810133// TCHECK-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]]10134// TCHECK-NEXT: [[VLA3:%.*]] = alloca i16, i64 [[TMP5]], align 210135// TCHECK-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 810136// TCHECK-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR1]], align 810137// TCHECK-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]]10138// TCHECK-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], 210139// TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 2 [[VLA3]], ptr align 2 [[TMP3]], i64 [[TMP7]], i1 false)10140// TCHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[B_ADDR]], align 410141// TCHECK-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double10142// TCHECK-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+0010143// TCHECK-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 010144// TCHECK-NEXT: store double [[ADD]], ptr [[A]], align 810145// TCHECK-NEXT: [[A4:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 010146// TCHECK-NEXT: [[TMP9:%.*]] = load double, ptr [[A4]], align 810147// TCHECK-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+0010148// TCHECK-NEXT: store double [[INC]], ptr [[A4]], align 810149// TCHECK-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i1610150// TCHECK-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]]10151// TCHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA3]], i64 [[TMP10]]10152// TCHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 110153// TCHECK-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 210154// TCHECK-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 810155// TCHECK-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP11]])10156// TCHECK-NEXT: ret void10157//10158//10159// TCHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l12810160// TCHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {10161// TCHECK-NEXT: entry:10162// TCHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 810163// TCHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 810164// TCHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 810165// TCHECK-NEXT: [[B1:%.*]] = alloca [10 x i32], align 410166// TCHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 810167// TCHECK-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 810168// TCHECK-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 810169// TCHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 810170// TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B1]], ptr align 4 [[TMP0]], i64 40, i1 false)10171// TCHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 410172// TCHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 110173// TCHECK-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 410174// TCHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B1]], i64 0, i64 210175// TCHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 410176// TCHECK-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 110177// TCHECK-NEXT: store i32 [[ADD2]], ptr [[ARRAYIDX]], align 410178// TCHECK-NEXT: ret void10179//10180//10181// TCHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l6310182// TCHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], ptr noundef [[P:%.*]], i64 noundef [[GA:%.*]]) #[[ATTR0:[0-9]+]] {10183// TCHECK1-NEXT: entry:10184// TCHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 810185// TCHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 810186// TCHECK1-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 810187// TCHECK1-NEXT: [[GA_ADDR:%.*]] = alloca i64, align 810188// TCHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 810189// TCHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 810190// TCHECK1-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 810191// TCHECK1-NEXT: store i64 [[GA]], ptr [[GA_ADDR]], align 810192// TCHECK1-NEXT: ret void10193//10194//10195// TCHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l7010196// TCHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {10197// TCHECK1-NEXT: entry:10198// TCHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 810199// TCHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 810200// TCHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 810201// TCHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 810202// TCHECK1-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 810203// TCHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 810204// TCHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 810205// TCHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 810206// TCHECK1-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 810207// TCHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 810208// TCHECK1-NEXT: [[B5:%.*]] = alloca [10 x float], align 410209// TCHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 810210// TCHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 810211// TCHECK1-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 810212// TCHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 810213// TCHECK1-NEXT: [[__VLA_EXPR2:%.*]] = alloca i64, align 810214// TCHECK1-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 810215// TCHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 810216// TCHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 810217// TCHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 810218// TCHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 810219// TCHECK1-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 810220// TCHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 810221// TCHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 810222// TCHECK1-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 810223// TCHECK1-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 810224// TCHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 810225// TCHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 810226// TCHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 810227// TCHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 810228// TCHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 810229// TCHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 810230// TCHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 810231// TCHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 810232// TCHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 810233// TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B5]], ptr align 4 [[TMP0]], i64 40, i1 false)10234// TCHECK1-NEXT: [[TMP8:%.*]] = call ptr @llvm.stacksave.p0()10235// TCHECK1-NEXT: store ptr [[TMP8]], ptr [[SAVED_STACK]], align 810236// TCHECK1-NEXT: [[VLA6:%.*]] = alloca float, i64 [[TMP1]], align 410237// TCHECK1-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 810238// TCHECK1-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP1]], 410239// TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VLA6]], ptr align 4 [[TMP2]], i64 [[TMP9]], i1 false)10240// TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[C7]], ptr align 8 [[TMP3]], i64 400, i1 false)10241// TCHECK1-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]]10242// TCHECK1-NEXT: [[VLA8:%.*]] = alloca double, i64 [[TMP10]], align 810243// TCHECK1-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 810244// TCHECK1-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR2]], align 810245// TCHECK1-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]]10246// TCHECK1-NEXT: [[TMP12:%.*]] = mul nuw i64 [[TMP11]], 810247// TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[VLA8]], ptr align 8 [[TMP6]], i64 [[TMP12]], i1 false)10248// TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[D9]], ptr align 8 [[TMP7]], i64 16, i1 false)10249// TCHECK1-NEXT: [[TMP13:%.*]] = load i16, ptr [[AA_ADDR]], align 210250// TCHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP13]] to i3210251// TCHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 110252// TCHECK1-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i1610253// TCHECK1-NEXT: store i16 [[CONV10]], ptr [[AA_ADDR]], align 210254// TCHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B5]], i64 0, i64 210255// TCHECK1-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX]], align 410256// TCHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, ptr [[VLA6]], i64 310257// TCHECK1-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX11]], align 410258// TCHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C7]], i64 0, i64 110259// TCHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX12]], i64 0, i64 210260// TCHECK1-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX13]], align 810261// TCHECK1-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP5]]10262// TCHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[VLA8]], i64 [[TMP14]]10263// TCHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i64 310264// TCHECK1-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX15]], align 810265// TCHECK1-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D9]], i32 0, i32 010266// TCHECK1-NEXT: store i64 1, ptr [[X]], align 810267// TCHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D9]], i32 0, i32 110268// TCHECK1-NEXT: store i8 1, ptr [[Y]], align 810269// TCHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 810270// TCHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP15]])10271// TCHECK1-NEXT: ret void10272//10273//10274// TCHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l11110275// TCHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR0]] {10276// TCHECK1-NEXT: entry:10277// TCHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 810278// TCHECK1-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 810279// TCHECK1-NEXT: [[E_ADDR:%.*]] = alloca ptr, align 810280// TCHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 810281// TCHECK1-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 810282// TCHECK1-NEXT: store ptr [[E]], ptr [[E_ADDR]], align 810283// TCHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[E_ADDR]], align 810284// TCHECK1-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT_0:%.*]], ptr [[TMP0]], i32 0, i32 010285// TCHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[X]], align 410286// TCHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double10287// TCHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[PTR_ADDR]], align 810288// TCHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP2]], i64 010289// TCHECK1-NEXT: store double [[CONV]], ptr [[ARRAYIDX]], align 810290// TCHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[PTR_ADDR]], align 810291// TCHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds double, ptr [[TMP3]], i64 010292// TCHECK1-NEXT: [[TMP4:%.*]] = load double, ptr [[ARRAYIDX1]], align 810293// TCHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+0010294// TCHECK1-NEXT: store double [[INC]], ptr [[ARRAYIDX1]], align 810295// TCHECK1-NEXT: ret void10296//10297//10298// TCHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l14210299// TCHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {10300// TCHECK1-NEXT: entry:10301// TCHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 810302// TCHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 810303// TCHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 810304// TCHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 810305// TCHECK1-NEXT: [[B1:%.*]] = alloca [10 x i32], align 410306// TCHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 810307// TCHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 810308// TCHECK1-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 810309// TCHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 810310// TCHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 810311// TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B1]], ptr align 4 [[TMP0]], i64 40, i1 false)10312// TCHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 410313// TCHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 110314// TCHECK1-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 410315// TCHECK1-NEXT: [[TMP2:%.*]] = load i8, ptr [[AAA_ADDR]], align 110316// TCHECK1-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i3210317// TCHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 110318// TCHECK1-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i810319// TCHECK1-NEXT: store i8 [[CONV3]], ptr [[AAA_ADDR]], align 110320// TCHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B1]], i64 0, i64 210321// TCHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 410322// TCHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 110323// TCHECK1-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 410324// TCHECK1-NEXT: ret void10325//10326//10327// TCHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l16710328// TCHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {10329// TCHECK1-NEXT: entry:10330// TCHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 810331// TCHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 810332// TCHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 810333// TCHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 810334// TCHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 810335// TCHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 810336// TCHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 810337// TCHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 810338// TCHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 810339// TCHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 810340// TCHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 810341// TCHECK1-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 810342// TCHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 810343// TCHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 810344// TCHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 810345// TCHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 810346// TCHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 810347// TCHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 810348// TCHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 810349// TCHECK1-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave.p0()10350// TCHECK1-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 810351// TCHECK1-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]]10352// TCHECK1-NEXT: [[VLA3:%.*]] = alloca i16, i64 [[TMP5]], align 210353// TCHECK1-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 810354// TCHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR1]], align 810355// TCHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]]10356// TCHECK1-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], 210357// TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 2 [[VLA3]], ptr align 2 [[TMP3]], i64 [[TMP7]], i1 false)10358// TCHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[B_ADDR]], align 410359// TCHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double10360// TCHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+0010361// TCHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 010362// TCHECK1-NEXT: store double [[ADD]], ptr [[A]], align 810363// TCHECK1-NEXT: [[A4:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 010364// TCHECK1-NEXT: [[TMP9:%.*]] = load double, ptr [[A4]], align 810365// TCHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+0010366// TCHECK1-NEXT: store double [[INC]], ptr [[A4]], align 810367// TCHECK1-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i1610368// TCHECK1-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]]10369// TCHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA3]], i64 [[TMP10]]10370// TCHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 110371// TCHECK1-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 210372// TCHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 810373// TCHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP11]])10374// TCHECK1-NEXT: ret void10375//10376//10377// TCHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l12810378// TCHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {10379// TCHECK1-NEXT: entry:10380// TCHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 810381// TCHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 810382// TCHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 810383// TCHECK1-NEXT: [[B1:%.*]] = alloca [10 x i32], align 410384// TCHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 810385// TCHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 810386// TCHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 810387// TCHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 810388// TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B1]], ptr align 4 [[TMP0]], i64 40, i1 false)10389// TCHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 410390// TCHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 110391// TCHECK1-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 410392// TCHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B1]], i64 0, i64 210393// TCHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 410394// TCHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 110395// TCHECK1-NEXT: store i32 [[ADD2]], ptr [[ARRAYIDX]], align 410396// TCHECK1-NEXT: ret void10397//10398//10399// TCHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l6310400// TCHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], ptr noundef [[P:%.*]], i32 noundef [[GA:%.*]]) #[[ATTR0:[0-9]+]] {10401// TCHECK2-NEXT: entry:10402// TCHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 410403// TCHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 410404// TCHECK2-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 410405// TCHECK2-NEXT: [[GA_ADDR:%.*]] = alloca i32, align 410406// TCHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 410407// TCHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 410408// TCHECK2-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 410409// TCHECK2-NEXT: store i32 [[GA]], ptr [[GA_ADDR]], align 410410// TCHECK2-NEXT: ret void10411//10412//10413// TCHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l7010414// TCHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {10415// TCHECK2-NEXT: entry:10416// TCHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 410417// TCHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 410418// TCHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 410419// TCHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 410420// TCHECK2-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 410421// TCHECK2-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 410422// TCHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 410423// TCHECK2-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 410424// TCHECK2-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 410425// TCHECK2-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 410426// TCHECK2-NEXT: [[B5:%.*]] = alloca [10 x float], align 410427// TCHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 410428// TCHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 410429// TCHECK2-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 810430// TCHECK2-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 410431// TCHECK2-NEXT: [[__VLA_EXPR2:%.*]] = alloca i32, align 410432// TCHECK2-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 410433// TCHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 410434// TCHECK2-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 410435// TCHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 410436// TCHECK2-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 410437// TCHECK2-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 410438// TCHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 410439// TCHECK2-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 410440// TCHECK2-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 410441// TCHECK2-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 410442// TCHECK2-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 410443// TCHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 410444// TCHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 410445// TCHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 410446// TCHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 410447// TCHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 410448// TCHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 410449// TCHECK2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 410450// TCHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 410451// TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B5]], ptr align 4 [[TMP0]], i32 40, i1 false)10452// TCHECK2-NEXT: [[TMP8:%.*]] = call ptr @llvm.stacksave.p0()10453// TCHECK2-NEXT: store ptr [[TMP8]], ptr [[SAVED_STACK]], align 410454// TCHECK2-NEXT: [[VLA6:%.*]] = alloca float, i32 [[TMP1]], align 410455// TCHECK2-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 410456// TCHECK2-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP1]], 410457// TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VLA6]], ptr align 4 [[TMP2]], i32 [[TMP9]], i1 false)10458// TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[C7]], ptr align 8 [[TMP3]], i32 400, i1 false)10459// TCHECK2-NEXT: [[TMP10:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]]10460// TCHECK2-NEXT: [[VLA8:%.*]] = alloca double, i32 [[TMP10]], align 810461// TCHECK2-NEXT: store i32 [[TMP4]], ptr [[__VLA_EXPR1]], align 410462// TCHECK2-NEXT: store i32 [[TMP5]], ptr [[__VLA_EXPR2]], align 410463// TCHECK2-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]]10464// TCHECK2-NEXT: [[TMP12:%.*]] = mul nuw i32 [[TMP11]], 810465// TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[VLA8]], ptr align 8 [[TMP6]], i32 [[TMP12]], i1 false)10466// TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[D9]], ptr align 4 [[TMP7]], i32 12, i1 false)10467// TCHECK2-NEXT: [[TMP13:%.*]] = load i16, ptr [[AA_ADDR]], align 210468// TCHECK2-NEXT: [[CONV:%.*]] = sext i16 [[TMP13]] to i3210469// TCHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 110470// TCHECK2-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i1610471// TCHECK2-NEXT: store i16 [[CONV10]], ptr [[AA_ADDR]], align 210472// TCHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B5]], i32 0, i32 210473// TCHECK2-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX]], align 410474// TCHECK2-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, ptr [[VLA6]], i32 310475// TCHECK2-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX11]], align 410476// TCHECK2-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C7]], i32 0, i32 110477// TCHECK2-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX12]], i32 0, i32 210478// TCHECK2-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX13]], align 810479// TCHECK2-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP5]]10480// TCHECK2-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[VLA8]], i32 [[TMP14]]10481// TCHECK2-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i32 310482// TCHECK2-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX15]], align 810483// TCHECK2-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D9]], i32 0, i32 010484// TCHECK2-NEXT: store i64 1, ptr [[X]], align 410485// TCHECK2-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D9]], i32 0, i32 110486// TCHECK2-NEXT: store i8 1, ptr [[Y]], align 410487// TCHECK2-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 410488// TCHECK2-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP15]])10489// TCHECK2-NEXT: ret void10490//10491//10492// TCHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l11110493// TCHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR0]] {10494// TCHECK2-NEXT: entry:10495// TCHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 410496// TCHECK2-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 410497// TCHECK2-NEXT: [[E_ADDR:%.*]] = alloca ptr, align 410498// TCHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 410499// TCHECK2-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 410500// TCHECK2-NEXT: store ptr [[E]], ptr [[E_ADDR]], align 410501// TCHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[E_ADDR]], align 410502// TCHECK2-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT_0:%.*]], ptr [[TMP0]], i32 0, i32 010503// TCHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[X]], align 410504// TCHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double10505// TCHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[PTR_ADDR]], align 410506// TCHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP2]], i32 010507// TCHECK2-NEXT: store double [[CONV]], ptr [[ARRAYIDX]], align 410508// TCHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[PTR_ADDR]], align 410509// TCHECK2-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds double, ptr [[TMP3]], i32 010510// TCHECK2-NEXT: [[TMP4:%.*]] = load double, ptr [[ARRAYIDX1]], align 410511// TCHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+0010512// TCHECK2-NEXT: store double [[INC]], ptr [[ARRAYIDX1]], align 410513// TCHECK2-NEXT: ret void10514//10515//10516// TCHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l14210517// TCHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {10518// TCHECK2-NEXT: entry:10519// TCHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 410520// TCHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 410521// TCHECK2-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 410522// TCHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 410523// TCHECK2-NEXT: [[B1:%.*]] = alloca [10 x i32], align 410524// TCHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 410525// TCHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 410526// TCHECK2-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 410527// TCHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 410528// TCHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 410529// TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B1]], ptr align 4 [[TMP0]], i32 40, i1 false)10530// TCHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 410531// TCHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 110532// TCHECK2-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 410533// TCHECK2-NEXT: [[TMP2:%.*]] = load i8, ptr [[AAA_ADDR]], align 110534// TCHECK2-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i3210535// TCHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 110536// TCHECK2-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i810537// TCHECK2-NEXT: store i8 [[CONV3]], ptr [[AAA_ADDR]], align 110538// TCHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B1]], i32 0, i32 210539// TCHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 410540// TCHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 110541// TCHECK2-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 410542// TCHECK2-NEXT: ret void10543//10544//10545// TCHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l16710546// TCHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {10547// TCHECK2-NEXT: entry:10548// TCHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 410549// TCHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 410550// TCHECK2-NEXT: [[B_ADDR:%.*]] = alloca i32, align 410551// TCHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 410552// TCHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 410553// TCHECK2-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 410554// TCHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 410555// TCHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 410556// TCHECK2-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 410557// TCHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 410558// TCHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 410559// TCHECK2-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 410560// TCHECK2-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 410561// TCHECK2-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 410562// TCHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 410563// TCHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 410564// TCHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 410565// TCHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 410566// TCHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 410567// TCHECK2-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave.p0()10568// TCHECK2-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 410569// TCHECK2-NEXT: [[TMP5:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]10570// TCHECK2-NEXT: [[VLA3:%.*]] = alloca i16, i32 [[TMP5]], align 210571// TCHECK2-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 410572// TCHECK2-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 410573// TCHECK2-NEXT: [[TMP6:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]10574// TCHECK2-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP6]], 210575// TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 2 [[VLA3]], ptr align 2 [[TMP3]], i32 [[TMP7]], i1 false)10576// TCHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[B_ADDR]], align 410577// TCHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double10578// TCHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+0010579// TCHECK2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 010580// TCHECK2-NEXT: store double [[ADD]], ptr [[A]], align 410581// TCHECK2-NEXT: [[A4:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 010582// TCHECK2-NEXT: [[TMP9:%.*]] = load double, ptr [[A4]], align 410583// TCHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+0010584// TCHECK2-NEXT: store double [[INC]], ptr [[A4]], align 410585// TCHECK2-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i1610586// TCHECK2-NEXT: [[TMP10:%.*]] = mul nsw i32 1, [[TMP2]]10587// TCHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA3]], i32 [[TMP10]]10588// TCHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 110589// TCHECK2-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 210590// TCHECK2-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 410591// TCHECK2-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP11]])10592// TCHECK2-NEXT: ret void10593//10594//10595// TCHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l12810596// TCHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {10597// TCHECK2-NEXT: entry:10598// TCHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 410599// TCHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 410600// TCHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 410601// TCHECK2-NEXT: [[B1:%.*]] = alloca [10 x i32], align 410602// TCHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 410603// TCHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 410604// TCHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 410605// TCHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 410606// TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B1]], ptr align 4 [[TMP0]], i32 40, i1 false)10607// TCHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 410608// TCHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 110609// TCHECK2-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 410610// TCHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B1]], i32 0, i32 210611// TCHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 410612// TCHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 110613// TCHECK2-NEXT: store i32 [[ADD2]], ptr [[ARRAYIDX]], align 410614// TCHECK2-NEXT: ret void10615//10616//10617// TCHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l6310618// TCHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], ptr noundef [[P:%.*]], i32 noundef [[GA:%.*]]) #[[ATTR0:[0-9]+]] {10619// TCHECK3-NEXT: entry:10620// TCHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 410621// TCHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 410622// TCHECK3-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 410623// TCHECK3-NEXT: [[GA_ADDR:%.*]] = alloca i32, align 410624// TCHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 410625// TCHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 410626// TCHECK3-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 410627// TCHECK3-NEXT: store i32 [[GA]], ptr [[GA_ADDR]], align 410628// TCHECK3-NEXT: ret void10629//10630//10631// TCHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l7010632// TCHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {10633// TCHECK3-NEXT: entry:10634// TCHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 410635// TCHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 410636// TCHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 410637// TCHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 410638// TCHECK3-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 410639// TCHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 410640// TCHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 410641// TCHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 410642// TCHECK3-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 410643// TCHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 410644// TCHECK3-NEXT: [[B5:%.*]] = alloca [10 x float], align 410645// TCHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 410646// TCHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 410647// TCHECK3-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 810648// TCHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 410649// TCHECK3-NEXT: [[__VLA_EXPR2:%.*]] = alloca i32, align 410650// TCHECK3-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 410651// TCHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 410652// TCHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 410653// TCHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 410654// TCHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 410655// TCHECK3-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 410656// TCHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 410657// TCHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 410658// TCHECK3-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 410659// TCHECK3-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 410660// TCHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 410661// TCHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 410662// TCHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 410663// TCHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 410664// TCHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 410665// TCHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 410666// TCHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 410667// TCHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 410668// TCHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 410669// TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B5]], ptr align 4 [[TMP0]], i32 40, i1 false)10670// TCHECK3-NEXT: [[TMP8:%.*]] = call ptr @llvm.stacksave.p0()10671// TCHECK3-NEXT: store ptr [[TMP8]], ptr [[SAVED_STACK]], align 410672// TCHECK3-NEXT: [[VLA6:%.*]] = alloca float, i32 [[TMP1]], align 410673// TCHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 410674// TCHECK3-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP1]], 410675// TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VLA6]], ptr align 4 [[TMP2]], i32 [[TMP9]], i1 false)10676// TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[C7]], ptr align 8 [[TMP3]], i32 400, i1 false)10677// TCHECK3-NEXT: [[TMP10:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]]10678// TCHECK3-NEXT: [[VLA8:%.*]] = alloca double, i32 [[TMP10]], align 810679// TCHECK3-NEXT: store i32 [[TMP4]], ptr [[__VLA_EXPR1]], align 410680// TCHECK3-NEXT: store i32 [[TMP5]], ptr [[__VLA_EXPR2]], align 410681// TCHECK3-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]]10682// TCHECK3-NEXT: [[TMP12:%.*]] = mul nuw i32 [[TMP11]], 810683// TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[VLA8]], ptr align 8 [[TMP6]], i32 [[TMP12]], i1 false)10684// TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[D9]], ptr align 4 [[TMP7]], i32 12, i1 false)10685// TCHECK3-NEXT: [[TMP13:%.*]] = load i16, ptr [[AA_ADDR]], align 210686// TCHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP13]] to i3210687// TCHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 110688// TCHECK3-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i1610689// TCHECK3-NEXT: store i16 [[CONV10]], ptr [[AA_ADDR]], align 210690// TCHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B5]], i32 0, i32 210691// TCHECK3-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX]], align 410692// TCHECK3-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, ptr [[VLA6]], i32 310693// TCHECK3-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX11]], align 410694// TCHECK3-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C7]], i32 0, i32 110695// TCHECK3-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX12]], i32 0, i32 210696// TCHECK3-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX13]], align 810697// TCHECK3-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP5]]10698// TCHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[VLA8]], i32 [[TMP14]]10699// TCHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i32 310700// TCHECK3-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX15]], align 810701// TCHECK3-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D9]], i32 0, i32 010702// TCHECK3-NEXT: store i64 1, ptr [[X]], align 410703// TCHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D9]], i32 0, i32 110704// TCHECK3-NEXT: store i8 1, ptr [[Y]], align 410705// TCHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 410706// TCHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP15]])10707// TCHECK3-NEXT: ret void10708//10709//10710// TCHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l11110711// TCHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR0]] {10712// TCHECK3-NEXT: entry:10713// TCHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 410714// TCHECK3-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 410715// TCHECK3-NEXT: [[E_ADDR:%.*]] = alloca ptr, align 410716// TCHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 410717// TCHECK3-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 410718// TCHECK3-NEXT: store ptr [[E]], ptr [[E_ADDR]], align 410719// TCHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[E_ADDR]], align 410720// TCHECK3-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT_0:%.*]], ptr [[TMP0]], i32 0, i32 010721// TCHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[X]], align 410722// TCHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double10723// TCHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[PTR_ADDR]], align 410724// TCHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP2]], i32 010725// TCHECK3-NEXT: store double [[CONV]], ptr [[ARRAYIDX]], align 410726// TCHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[PTR_ADDR]], align 410727// TCHECK3-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds double, ptr [[TMP3]], i32 010728// TCHECK3-NEXT: [[TMP4:%.*]] = load double, ptr [[ARRAYIDX1]], align 410729// TCHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+0010730// TCHECK3-NEXT: store double [[INC]], ptr [[ARRAYIDX1]], align 410731// TCHECK3-NEXT: ret void10732//10733//10734// TCHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l14210735// TCHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {10736// TCHECK3-NEXT: entry:10737// TCHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 410738// TCHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 410739// TCHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 410740// TCHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 410741// TCHECK3-NEXT: [[B1:%.*]] = alloca [10 x i32], align 410742// TCHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 410743// TCHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 410744// TCHECK3-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 410745// TCHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 410746// TCHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 410747// TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B1]], ptr align 4 [[TMP0]], i32 40, i1 false)10748// TCHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 410749// TCHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 110750// TCHECK3-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 410751// TCHECK3-NEXT: [[TMP2:%.*]] = load i8, ptr [[AAA_ADDR]], align 110752// TCHECK3-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i3210753// TCHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 110754// TCHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i810755// TCHECK3-NEXT: store i8 [[CONV3]], ptr [[AAA_ADDR]], align 110756// TCHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B1]], i32 0, i32 210757// TCHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 410758// TCHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 110759// TCHECK3-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 410760// TCHECK3-NEXT: ret void10761//10762//10763// TCHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l16710764// TCHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {10765// TCHECK3-NEXT: entry:10766// TCHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 410767// TCHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 410768// TCHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 410769// TCHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 410770// TCHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 410771// TCHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 410772// TCHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 410773// TCHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 410774// TCHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 410775// TCHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 410776// TCHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 410777// TCHECK3-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 410778// TCHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 410779// TCHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 410780// TCHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 410781// TCHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 410782// TCHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 410783// TCHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 410784// TCHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 410785// TCHECK3-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave.p0()10786// TCHECK3-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 410787// TCHECK3-NEXT: [[TMP5:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]10788// TCHECK3-NEXT: [[VLA3:%.*]] = alloca i16, i32 [[TMP5]], align 210789// TCHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 410790// TCHECK3-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 410791// TCHECK3-NEXT: [[TMP6:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]10792// TCHECK3-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP6]], 210793// TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 2 [[VLA3]], ptr align 2 [[TMP3]], i32 [[TMP7]], i1 false)10794// TCHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[B_ADDR]], align 410795// TCHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double10796// TCHECK3-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+0010797// TCHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 010798// TCHECK3-NEXT: store double [[ADD]], ptr [[A]], align 410799// TCHECK3-NEXT: [[A4:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 010800// TCHECK3-NEXT: [[TMP9:%.*]] = load double, ptr [[A4]], align 410801// TCHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+0010802// TCHECK3-NEXT: store double [[INC]], ptr [[A4]], align 410803// TCHECK3-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i1610804// TCHECK3-NEXT: [[TMP10:%.*]] = mul nsw i32 1, [[TMP2]]10805// TCHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA3]], i32 [[TMP10]]10806// TCHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 110807// TCHECK3-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 210808// TCHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 410809// TCHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP11]])10810// TCHECK3-NEXT: ret void10811//10812//10813// TCHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l12810814// TCHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {10815// TCHECK3-NEXT: entry:10816// TCHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 410817// TCHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 410818// TCHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 410819// TCHECK3-NEXT: [[B1:%.*]] = alloca [10 x i32], align 410820// TCHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 410821// TCHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 410822// TCHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 410823// TCHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 410824// TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B1]], ptr align 4 [[TMP0]], i32 40, i1 false)10825// TCHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 410826// TCHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 110827// TCHECK3-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 410828// TCHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B1]], i32 0, i32 210829// TCHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 410830// TCHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 110831// TCHECK3-NEXT: store i32 [[ADD2]], ptr [[ARRAYIDX]], align 410832// TCHECK3-NEXT: ret void10833//10834//10835// SIMD-ONLY1-LABEL: define {{[^@]+}}@_Z3fooiPd10836// SIMD-ONLY1-SAME: (i32 noundef signext [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {10837// SIMD-ONLY1-NEXT: entry:10838// SIMD-ONLY1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 410839// SIMD-ONLY1-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 810840// SIMD-ONLY1-NEXT: [[A:%.*]] = alloca i32, align 410841// SIMD-ONLY1-NEXT: [[AA:%.*]] = alloca i16, align 210842// SIMD-ONLY1-NEXT: [[B:%.*]] = alloca [10 x float], align 410843// SIMD-ONLY1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 810844// SIMD-ONLY1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 810845// SIMD-ONLY1-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 810846// SIMD-ONLY1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 810847// SIMD-ONLY1-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 810848// SIMD-ONLY1-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 410849// SIMD-ONLY1-NEXT: [[P:%.*]] = alloca ptr, align 6410850// SIMD-ONLY1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 410851// SIMD-ONLY1-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 810852// SIMD-ONLY1-NEXT: store i32 0, ptr [[A]], align 410853// SIMD-ONLY1-NEXT: store i16 0, ptr [[AA]], align 210854// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 410855// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i6410856// SIMD-ONLY1-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()10857// SIMD-ONLY1-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 810858// SIMD-ONLY1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 410859// SIMD-ONLY1-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 810860// SIMD-ONLY1-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 410861// SIMD-ONLY1-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i6410862// SIMD-ONLY1-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]10863// SIMD-ONLY1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 810864// SIMD-ONLY1-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 810865// SIMD-ONLY1-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 010866// SIMD-ONLY1-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 410867// SIMD-ONLY1-NEXT: store i32 [[TMP6]], ptr [[X]], align 410868// SIMD-ONLY1-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 110869// SIMD-ONLY1-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 410870// SIMD-ONLY1-NEXT: store i32 [[TMP7]], ptr [[Y]], align 410871// SIMD-ONLY1-NEXT: store ptr [[A]], ptr [[P]], align 6410872// SIMD-ONLY1-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA]], align 210873// SIMD-ONLY1-NEXT: [[CONV:%.*]] = sext i16 [[TMP8]] to i3210874// SIMD-ONLY1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 110875// SIMD-ONLY1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i1610876// SIMD-ONLY1-NEXT: store i16 [[CONV2]], ptr [[AA]], align 210877// SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i64 0, i64 210878// SIMD-ONLY1-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX]], align 410879// SIMD-ONLY1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[VLA]], i64 310880// SIMD-ONLY1-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX3]], align 410881// SIMD-ONLY1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i64 0, i64 110882// SIMD-ONLY1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX4]], i64 0, i64 210883// SIMD-ONLY1-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX5]], align 810884// SIMD-ONLY1-NEXT: [[TMP9:%.*]] = mul nsw i64 1, [[TMP4]]10885// SIMD-ONLY1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, ptr [[VLA1]], i64 [[TMP9]]10886// SIMD-ONLY1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX6]], i64 310887// SIMD-ONLY1-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX7]], align 810888// SIMD-ONLY1-NEXT: [[X8:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D]], i32 0, i32 010889// SIMD-ONLY1-NEXT: store i64 1, ptr [[X8]], align 810890// SIMD-ONLY1-NEXT: [[Y9:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D]], i32 0, i32 110891// SIMD-ONLY1-NEXT: store i8 1, ptr [[Y9]], align 810892// SIMD-ONLY1-NEXT: [[X10:%.*]] = getelementptr inbounds nuw [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 010893// SIMD-ONLY1-NEXT: [[TMP10:%.*]] = load i32, ptr [[X10]], align 410894// SIMD-ONLY1-NEXT: [[CONV11:%.*]] = sitofp i32 [[TMP10]] to double10895// SIMD-ONLY1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[PTR_ADDR]], align 810896// SIMD-ONLY1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds double, ptr [[TMP11]], i64 010897// SIMD-ONLY1-NEXT: store double [[CONV11]], ptr [[ARRAYIDX12]], align 810898// SIMD-ONLY1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[PTR_ADDR]], align 810899// SIMD-ONLY1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, ptr [[TMP12]], i64 010900// SIMD-ONLY1-NEXT: [[TMP13:%.*]] = load double, ptr [[ARRAYIDX13]], align 810901// SIMD-ONLY1-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+0010902// SIMD-ONLY1-NEXT: store double [[INC]], ptr [[ARRAYIDX13]], align 810903// SIMD-ONLY1-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 410904// SIMD-ONLY1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 810905// SIMD-ONLY1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP15]])10906// SIMD-ONLY1-NEXT: ret i32 [[TMP14]]10907//10908//10909// SIMD-ONLY1-LABEL: define {{[^@]+}}@_Z3bariPd10910// SIMD-ONLY1-SAME: (i32 noundef signext [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0]] {10911// SIMD-ONLY1-NEXT: entry:10912// SIMD-ONLY1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 410913// SIMD-ONLY1-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 810914// SIMD-ONLY1-NEXT: [[A:%.*]] = alloca i32, align 410915// SIMD-ONLY1-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 810916// SIMD-ONLY1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 410917// SIMD-ONLY1-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 810918// SIMD-ONLY1-NEXT: store i32 0, ptr [[A]], align 410919// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 410920// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 810921// SIMD-ONLY1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooiPd(i32 noundef signext [[TMP0]], ptr noundef [[TMP1]])10922// SIMD-ONLY1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 410923// SIMD-ONLY1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]]10924// SIMD-ONLY1-NEXT: store i32 [[ADD]], ptr [[A]], align 410925// SIMD-ONLY1-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 410926// SIMD-ONLY1-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP3]])10927// SIMD-ONLY1-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 410928// SIMD-ONLY1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]]10929// SIMD-ONLY1-NEXT: store i32 [[ADD2]], ptr [[A]], align 410930// SIMD-ONLY1-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 410931// SIMD-ONLY1-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP5]])10932// SIMD-ONLY1-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 410933// SIMD-ONLY1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]]10934// SIMD-ONLY1-NEXT: store i32 [[ADD4]], ptr [[A]], align 410935// SIMD-ONLY1-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 410936// SIMD-ONLY1-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP7]])10937// SIMD-ONLY1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 410938// SIMD-ONLY1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]]10939// SIMD-ONLY1-NEXT: store i32 [[ADD6]], ptr [[A]], align 410940// SIMD-ONLY1-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 410941// SIMD-ONLY1-NEXT: ret i32 [[TMP9]]10942//10943//10944// SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei10945// SIMD-ONLY1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {10946// SIMD-ONLY1-NEXT: entry:10947// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 810948// SIMD-ONLY1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 410949// SIMD-ONLY1-NEXT: [[B:%.*]] = alloca i32, align 410950// SIMD-ONLY1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 810951// SIMD-ONLY1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 810952// SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 810953// SIMD-ONLY1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 410954// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 810955// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 410956// SIMD-ONLY1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 110957// SIMD-ONLY1-NEXT: store i32 [[ADD]], ptr [[B]], align 410958// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 410959// SIMD-ONLY1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i6410960// SIMD-ONLY1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()10961// SIMD-ONLY1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 810962// SIMD-ONLY1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]10963// SIMD-ONLY1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 210964// SIMD-ONLY1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 810965// SIMD-ONLY1-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 410966// SIMD-ONLY1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double10967// SIMD-ONLY1-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+0010968// SIMD-ONLY1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 010969// SIMD-ONLY1-NEXT: store double [[ADD2]], ptr [[A]], align 810970// SIMD-ONLY1-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 010971// SIMD-ONLY1-NEXT: [[TMP6:%.*]] = load double, ptr [[A3]], align 810972// SIMD-ONLY1-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+0010973// SIMD-ONLY1-NEXT: store double [[INC]], ptr [[A3]], align 810974// SIMD-ONLY1-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i1610975// SIMD-ONLY1-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]]10976// SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP7]]10977// SIMD-ONLY1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 110978// SIMD-ONLY1-NEXT: store i16 [[CONV4]], ptr [[ARRAYIDX5]], align 210979// SIMD-ONLY1-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]]10980// SIMD-ONLY1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP8]]10981// SIMD-ONLY1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX6]], i64 110982// SIMD-ONLY1-NEXT: [[TMP9:%.*]] = load i16, ptr [[ARRAYIDX7]], align 210983// SIMD-ONLY1-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i3210984// SIMD-ONLY1-NEXT: [[TMP10:%.*]] = load i32, ptr [[B]], align 410985// SIMD-ONLY1-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]]10986// SIMD-ONLY1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 810987// SIMD-ONLY1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP11]])10988// SIMD-ONLY1-NEXT: ret i32 [[ADD9]]10989//10990//10991// SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZL7fstatici10992// SIMD-ONLY1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {10993// SIMD-ONLY1-NEXT: entry:10994// SIMD-ONLY1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 410995// SIMD-ONLY1-NEXT: [[A:%.*]] = alloca i32, align 410996// SIMD-ONLY1-NEXT: [[AAA:%.*]] = alloca i8, align 110997// SIMD-ONLY1-NEXT: [[B:%.*]] = alloca [10 x i32], align 410998// SIMD-ONLY1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 410999// SIMD-ONLY1-NEXT: store i32 0, ptr [[A]], align 411000// SIMD-ONLY1-NEXT: store i8 0, ptr [[AAA]], align 111001// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 411002// SIMD-ONLY1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 111003// SIMD-ONLY1-NEXT: store i32 [[ADD]], ptr [[A]], align 411004// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load i8, ptr [[AAA]], align 111005// SIMD-ONLY1-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i3211006// SIMD-ONLY1-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 111007// SIMD-ONLY1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i811008// SIMD-ONLY1-NEXT: store i8 [[CONV2]], ptr [[AAA]], align 111009// SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i64 0, i64 211010// SIMD-ONLY1-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 411011// SIMD-ONLY1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 111012// SIMD-ONLY1-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 411013// SIMD-ONLY1-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 411014// SIMD-ONLY1-NEXT: ret i32 [[TMP3]]11015//11016//11017// SIMD-ONLY1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i11018// SIMD-ONLY1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {11019// SIMD-ONLY1-NEXT: entry:11020// SIMD-ONLY1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 411021// SIMD-ONLY1-NEXT: [[A:%.*]] = alloca i32, align 411022// SIMD-ONLY1-NEXT: [[B:%.*]] = alloca [10 x i32], align 411023// SIMD-ONLY1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 411024// SIMD-ONLY1-NEXT: store i32 0, ptr [[A]], align 411025// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 411026// SIMD-ONLY1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 111027// SIMD-ONLY1-NEXT: store i32 [[ADD]], ptr [[A]], align 411028// SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i64 0, i64 211029// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 411030// SIMD-ONLY1-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP1]], 111031// SIMD-ONLY1-NEXT: store i32 [[ADD1]], ptr [[ARRAYIDX]], align 411032// SIMD-ONLY1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 411033// SIMD-ONLY1-NEXT: ret i32 [[TMP2]]11034//11035//11036// SIMD-ONLY11-LABEL: define {{[^@]+}}@_Z3fooiPd11037// SIMD-ONLY11-SAME: (i32 noundef signext [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {11038// SIMD-ONLY11-NEXT: entry:11039// SIMD-ONLY11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 411040// SIMD-ONLY11-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 811041// SIMD-ONLY11-NEXT: [[A:%.*]] = alloca i32, align 411042// SIMD-ONLY11-NEXT: [[AA:%.*]] = alloca i16, align 211043// SIMD-ONLY11-NEXT: [[B:%.*]] = alloca [10 x float], align 411044// SIMD-ONLY11-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 811045// SIMD-ONLY11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 811046// SIMD-ONLY11-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 811047// SIMD-ONLY11-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 811048// SIMD-ONLY11-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 811049// SIMD-ONLY11-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 411050// SIMD-ONLY11-NEXT: [[P:%.*]] = alloca ptr, align 6411051// SIMD-ONLY11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 411052// SIMD-ONLY11-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 811053// SIMD-ONLY11-NEXT: store i32 0, ptr [[A]], align 411054// SIMD-ONLY11-NEXT: store i16 0, ptr [[AA]], align 211055// SIMD-ONLY11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 411056// SIMD-ONLY11-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i6411057// SIMD-ONLY11-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()11058// SIMD-ONLY11-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 811059// SIMD-ONLY11-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 411060// SIMD-ONLY11-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 811061// SIMD-ONLY11-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 411062// SIMD-ONLY11-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i6411063// SIMD-ONLY11-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]11064// SIMD-ONLY11-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 811065// SIMD-ONLY11-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 811066// SIMD-ONLY11-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 011067// SIMD-ONLY11-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 411068// SIMD-ONLY11-NEXT: store i32 [[TMP6]], ptr [[X]], align 411069// SIMD-ONLY11-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 111070// SIMD-ONLY11-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 411071// SIMD-ONLY11-NEXT: store i32 [[TMP7]], ptr [[Y]], align 411072// SIMD-ONLY11-NEXT: store ptr [[A]], ptr [[P]], align 6411073// SIMD-ONLY11-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA]], align 211074// SIMD-ONLY11-NEXT: [[CONV:%.*]] = sext i16 [[TMP8]] to i3211075// SIMD-ONLY11-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 111076// SIMD-ONLY11-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i1611077// SIMD-ONLY11-NEXT: store i16 [[CONV2]], ptr [[AA]], align 211078// SIMD-ONLY11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i64 0, i64 211079// SIMD-ONLY11-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX]], align 411080// SIMD-ONLY11-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[VLA]], i64 311081// SIMD-ONLY11-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX3]], align 411082// SIMD-ONLY11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i64 0, i64 111083// SIMD-ONLY11-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX4]], i64 0, i64 211084// SIMD-ONLY11-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX5]], align 811085// SIMD-ONLY11-NEXT: [[TMP9:%.*]] = mul nsw i64 1, [[TMP4]]11086// SIMD-ONLY11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, ptr [[VLA1]], i64 [[TMP9]]11087// SIMD-ONLY11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX6]], i64 311088// SIMD-ONLY11-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX7]], align 811089// SIMD-ONLY11-NEXT: [[X8:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D]], i32 0, i32 011090// SIMD-ONLY11-NEXT: store i64 1, ptr [[X8]], align 811091// SIMD-ONLY11-NEXT: [[Y9:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D]], i32 0, i32 111092// SIMD-ONLY11-NEXT: store i8 1, ptr [[Y9]], align 811093// SIMD-ONLY11-NEXT: [[X10:%.*]] = getelementptr inbounds nuw [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 011094// SIMD-ONLY11-NEXT: [[TMP10:%.*]] = load i32, ptr [[X10]], align 411095// SIMD-ONLY11-NEXT: [[CONV11:%.*]] = sitofp i32 [[TMP10]] to double11096// SIMD-ONLY11-NEXT: [[TMP11:%.*]] = load ptr, ptr [[PTR_ADDR]], align 811097// SIMD-ONLY11-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds double, ptr [[TMP11]], i64 011098// SIMD-ONLY11-NEXT: store double [[CONV11]], ptr [[ARRAYIDX12]], align 811099// SIMD-ONLY11-NEXT: [[TMP12:%.*]] = load ptr, ptr [[PTR_ADDR]], align 811100// SIMD-ONLY11-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, ptr [[TMP12]], i64 011101// SIMD-ONLY11-NEXT: [[TMP13:%.*]] = load double, ptr [[ARRAYIDX13]], align 811102// SIMD-ONLY11-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+0011103// SIMD-ONLY11-NEXT: store double [[INC]], ptr [[ARRAYIDX13]], align 811104// SIMD-ONLY11-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 411105// SIMD-ONLY11-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 811106// SIMD-ONLY11-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP15]])11107// SIMD-ONLY11-NEXT: ret i32 [[TMP14]]11108//11109//11110// SIMD-ONLY11-LABEL: define {{[^@]+}}@_Z3bariPd11111// SIMD-ONLY11-SAME: (i32 noundef signext [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0]] {11112// SIMD-ONLY11-NEXT: entry:11113// SIMD-ONLY11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 411114// SIMD-ONLY11-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 811115// SIMD-ONLY11-NEXT: [[A:%.*]] = alloca i32, align 411116// SIMD-ONLY11-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 811117// SIMD-ONLY11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 411118// SIMD-ONLY11-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 811119// SIMD-ONLY11-NEXT: store i32 0, ptr [[A]], align 411120// SIMD-ONLY11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 411121// SIMD-ONLY11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 811122// SIMD-ONLY11-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooiPd(i32 noundef signext [[TMP0]], ptr noundef [[TMP1]])11123// SIMD-ONLY11-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 411124// SIMD-ONLY11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]]11125// SIMD-ONLY11-NEXT: store i32 [[ADD]], ptr [[A]], align 411126// SIMD-ONLY11-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 411127// SIMD-ONLY11-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP3]])11128// SIMD-ONLY11-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 411129// SIMD-ONLY11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]]11130// SIMD-ONLY11-NEXT: store i32 [[ADD2]], ptr [[A]], align 411131// SIMD-ONLY11-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 411132// SIMD-ONLY11-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP5]])11133// SIMD-ONLY11-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 411134// SIMD-ONLY11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]]11135// SIMD-ONLY11-NEXT: store i32 [[ADD4]], ptr [[A]], align 411136// SIMD-ONLY11-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 411137// SIMD-ONLY11-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP7]])11138// SIMD-ONLY11-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 411139// SIMD-ONLY11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]]11140// SIMD-ONLY11-NEXT: store i32 [[ADD6]], ptr [[A]], align 411141// SIMD-ONLY11-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 411142// SIMD-ONLY11-NEXT: ret i32 [[TMP9]]11143//11144//11145// SIMD-ONLY11-LABEL: define {{[^@]+}}@_ZN2S12r1Ei11146// SIMD-ONLY11-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {11147// SIMD-ONLY11-NEXT: entry:11148// SIMD-ONLY11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 811149// SIMD-ONLY11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 411150// SIMD-ONLY11-NEXT: [[B:%.*]] = alloca i32, align 411151// SIMD-ONLY11-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 811152// SIMD-ONLY11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 811153// SIMD-ONLY11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 811154// SIMD-ONLY11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 411155// SIMD-ONLY11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 811156// SIMD-ONLY11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 411157// SIMD-ONLY11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 111158// SIMD-ONLY11-NEXT: store i32 [[ADD]], ptr [[B]], align 411159// SIMD-ONLY11-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 411160// SIMD-ONLY11-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i6411161// SIMD-ONLY11-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()11162// SIMD-ONLY11-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 811163// SIMD-ONLY11-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]11164// SIMD-ONLY11-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 211165// SIMD-ONLY11-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 811166// SIMD-ONLY11-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 411167// SIMD-ONLY11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double11168// SIMD-ONLY11-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+0011169// SIMD-ONLY11-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 011170// SIMD-ONLY11-NEXT: store double [[ADD2]], ptr [[A]], align 811171// SIMD-ONLY11-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 011172// SIMD-ONLY11-NEXT: [[TMP6:%.*]] = load double, ptr [[A3]], align 811173// SIMD-ONLY11-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+0011174// SIMD-ONLY11-NEXT: store double [[INC]], ptr [[A3]], align 811175// SIMD-ONLY11-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i1611176// SIMD-ONLY11-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]]11177// SIMD-ONLY11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP7]]11178// SIMD-ONLY11-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 111179// SIMD-ONLY11-NEXT: store i16 [[CONV4]], ptr [[ARRAYIDX5]], align 211180// SIMD-ONLY11-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]]11181// SIMD-ONLY11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP8]]11182// SIMD-ONLY11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX6]], i64 111183// SIMD-ONLY11-NEXT: [[TMP9:%.*]] = load i16, ptr [[ARRAYIDX7]], align 211184// SIMD-ONLY11-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i3211185// SIMD-ONLY11-NEXT: [[TMP10:%.*]] = load i32, ptr [[B]], align 411186// SIMD-ONLY11-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]]11187// SIMD-ONLY11-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 811188// SIMD-ONLY11-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP11]])11189// SIMD-ONLY11-NEXT: ret i32 [[ADD9]]11190//11191//11192// SIMD-ONLY11-LABEL: define {{[^@]+}}@_ZL7fstatici11193// SIMD-ONLY11-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {11194// SIMD-ONLY11-NEXT: entry:11195// SIMD-ONLY11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 411196// SIMD-ONLY11-NEXT: [[A:%.*]] = alloca i32, align 411197// SIMD-ONLY11-NEXT: [[AAA:%.*]] = alloca i8, align 111198// SIMD-ONLY11-NEXT: [[B:%.*]] = alloca [10 x i32], align 411199// SIMD-ONLY11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 411200// SIMD-ONLY11-NEXT: store i32 0, ptr [[A]], align 411201// SIMD-ONLY11-NEXT: store i8 0, ptr [[AAA]], align 111202// SIMD-ONLY11-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 411203// SIMD-ONLY11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 111204// SIMD-ONLY11-NEXT: store i32 [[ADD]], ptr [[A]], align 411205// SIMD-ONLY11-NEXT: [[TMP1:%.*]] = load i8, ptr [[AAA]], align 111206// SIMD-ONLY11-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i3211207// SIMD-ONLY11-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 111208// SIMD-ONLY11-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i811209// SIMD-ONLY11-NEXT: store i8 [[CONV2]], ptr [[AAA]], align 111210// SIMD-ONLY11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i64 0, i64 211211// SIMD-ONLY11-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 411212// SIMD-ONLY11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 111213// SIMD-ONLY11-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 411214// SIMD-ONLY11-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 411215// SIMD-ONLY11-NEXT: ret i32 [[TMP3]]11216//11217//11218// SIMD-ONLY11-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i11219// SIMD-ONLY11-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {11220// SIMD-ONLY11-NEXT: entry:11221// SIMD-ONLY11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 411222// SIMD-ONLY11-NEXT: [[A:%.*]] = alloca i32, align 411223// SIMD-ONLY11-NEXT: [[B:%.*]] = alloca [10 x i32], align 411224// SIMD-ONLY11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 411225// SIMD-ONLY11-NEXT: store i32 0, ptr [[A]], align 411226// SIMD-ONLY11-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 411227// SIMD-ONLY11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 111228// SIMD-ONLY11-NEXT: store i32 [[ADD]], ptr [[A]], align 411229// SIMD-ONLY11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i64 0, i64 211230// SIMD-ONLY11-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 411231// SIMD-ONLY11-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP1]], 111232// SIMD-ONLY11-NEXT: store i32 [[ADD1]], ptr [[ARRAYIDX]], align 411233// SIMD-ONLY11-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 411234// SIMD-ONLY11-NEXT: ret i32 [[TMP2]]11235//11236//11237// SIMD-ONLY12-LABEL: define {{[^@]+}}@_Z3fooiPd11238// SIMD-ONLY12-SAME: (i32 noundef [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {11239// SIMD-ONLY12-NEXT: entry:11240// SIMD-ONLY12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 411241// SIMD-ONLY12-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 411242// SIMD-ONLY12-NEXT: [[A:%.*]] = alloca i32, align 411243// SIMD-ONLY12-NEXT: [[AA:%.*]] = alloca i16, align 211244// SIMD-ONLY12-NEXT: [[B:%.*]] = alloca [10 x float], align 411245// SIMD-ONLY12-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 411246// SIMD-ONLY12-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 411247// SIMD-ONLY12-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 811248// SIMD-ONLY12-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 411249// SIMD-ONLY12-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 411250// SIMD-ONLY12-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 411251// SIMD-ONLY12-NEXT: [[P:%.*]] = alloca ptr, align 6411252// SIMD-ONLY12-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 411253// SIMD-ONLY12-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 411254// SIMD-ONLY12-NEXT: store i32 0, ptr [[A]], align 411255// SIMD-ONLY12-NEXT: store i16 0, ptr [[AA]], align 211256// SIMD-ONLY12-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 411257// SIMD-ONLY12-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()11258// SIMD-ONLY12-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 411259// SIMD-ONLY12-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 411260// SIMD-ONLY12-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 411261// SIMD-ONLY12-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 411262// SIMD-ONLY12-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]11263// SIMD-ONLY12-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 811264// SIMD-ONLY12-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 411265// SIMD-ONLY12-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 011266// SIMD-ONLY12-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 411267// SIMD-ONLY12-NEXT: store i32 [[TMP4]], ptr [[X]], align 411268// SIMD-ONLY12-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 111269// SIMD-ONLY12-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 411270// SIMD-ONLY12-NEXT: store i32 [[TMP5]], ptr [[Y]], align 411271// SIMD-ONLY12-NEXT: store ptr [[A]], ptr [[P]], align 6411272// SIMD-ONLY12-NEXT: [[TMP6:%.*]] = load i16, ptr [[AA]], align 211273// SIMD-ONLY12-NEXT: [[CONV:%.*]] = sext i16 [[TMP6]] to i3211274// SIMD-ONLY12-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 111275// SIMD-ONLY12-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i1611276// SIMD-ONLY12-NEXT: store i16 [[CONV2]], ptr [[AA]], align 211277// SIMD-ONLY12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i32 0, i32 211278// SIMD-ONLY12-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX]], align 411279// SIMD-ONLY12-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[VLA]], i32 311280// SIMD-ONLY12-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX3]], align 411281// SIMD-ONLY12-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i32 0, i32 111282// SIMD-ONLY12-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX4]], i32 0, i32 211283// SIMD-ONLY12-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX5]], align 811284// SIMD-ONLY12-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP2]]11285// SIMD-ONLY12-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, ptr [[VLA1]], i32 [[TMP7]]11286// SIMD-ONLY12-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX6]], i32 311287// SIMD-ONLY12-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX7]], align 811288// SIMD-ONLY12-NEXT: [[X8:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D]], i32 0, i32 011289// SIMD-ONLY12-NEXT: store i64 1, ptr [[X8]], align 411290// SIMD-ONLY12-NEXT: [[Y9:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D]], i32 0, i32 111291// SIMD-ONLY12-NEXT: store i8 1, ptr [[Y9]], align 411292// SIMD-ONLY12-NEXT: [[X10:%.*]] = getelementptr inbounds nuw [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 011293// SIMD-ONLY12-NEXT: [[TMP8:%.*]] = load i32, ptr [[X10]], align 411294// SIMD-ONLY12-NEXT: [[CONV11:%.*]] = sitofp i32 [[TMP8]] to double11295// SIMD-ONLY12-NEXT: [[TMP9:%.*]] = load ptr, ptr [[PTR_ADDR]], align 411296// SIMD-ONLY12-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds double, ptr [[TMP9]], i32 011297// SIMD-ONLY12-NEXT: store double [[CONV11]], ptr [[ARRAYIDX12]], align 411298// SIMD-ONLY12-NEXT: [[TMP10:%.*]] = load ptr, ptr [[PTR_ADDR]], align 411299// SIMD-ONLY12-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, ptr [[TMP10]], i32 011300// SIMD-ONLY12-NEXT: [[TMP11:%.*]] = load double, ptr [[ARRAYIDX13]], align 411301// SIMD-ONLY12-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+0011302// SIMD-ONLY12-NEXT: store double [[INC]], ptr [[ARRAYIDX13]], align 411303// SIMD-ONLY12-NEXT: [[TMP12:%.*]] = load i32, ptr [[A]], align 411304// SIMD-ONLY12-NEXT: [[TMP13:%.*]] = load ptr, ptr [[SAVED_STACK]], align 411305// SIMD-ONLY12-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP13]])11306// SIMD-ONLY12-NEXT: ret i32 [[TMP12]]11307//11308//11309// SIMD-ONLY12-LABEL: define {{[^@]+}}@_Z3bariPd11310// SIMD-ONLY12-SAME: (i32 noundef [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0]] {11311// SIMD-ONLY12-NEXT: entry:11312// SIMD-ONLY12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 411313// SIMD-ONLY12-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 411314// SIMD-ONLY12-NEXT: [[A:%.*]] = alloca i32, align 411315// SIMD-ONLY12-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 411316// SIMD-ONLY12-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 411317// SIMD-ONLY12-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 411318// SIMD-ONLY12-NEXT: store i32 0, ptr [[A]], align 411319// SIMD-ONLY12-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 411320// SIMD-ONLY12-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 411321// SIMD-ONLY12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooiPd(i32 noundef [[TMP0]], ptr noundef [[TMP1]])11322// SIMD-ONLY12-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 411323// SIMD-ONLY12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]]11324// SIMD-ONLY12-NEXT: store i32 [[ADD]], ptr [[A]], align 411325// SIMD-ONLY12-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 411326// SIMD-ONLY12-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP3]])11327// SIMD-ONLY12-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 411328// SIMD-ONLY12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]]11329// SIMD-ONLY12-NEXT: store i32 [[ADD2]], ptr [[A]], align 411330// SIMD-ONLY12-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 411331// SIMD-ONLY12-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP5]])11332// SIMD-ONLY12-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 411333// SIMD-ONLY12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]]11334// SIMD-ONLY12-NEXT: store i32 [[ADD4]], ptr [[A]], align 411335// SIMD-ONLY12-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 411336// SIMD-ONLY12-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP7]])11337// SIMD-ONLY12-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 411338// SIMD-ONLY12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]]11339// SIMD-ONLY12-NEXT: store i32 [[ADD6]], ptr [[A]], align 411340// SIMD-ONLY12-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 411341// SIMD-ONLY12-NEXT: ret i32 [[TMP9]]11342//11343//11344// SIMD-ONLY12-LABEL: define {{[^@]+}}@_ZN2S12r1Ei11345// SIMD-ONLY12-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {11346// SIMD-ONLY12-NEXT: entry:11347// SIMD-ONLY12-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 411348// SIMD-ONLY12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 411349// SIMD-ONLY12-NEXT: [[B:%.*]] = alloca i32, align 411350// SIMD-ONLY12-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 411351// SIMD-ONLY12-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 411352// SIMD-ONLY12-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 411353// SIMD-ONLY12-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 411354// SIMD-ONLY12-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 411355// SIMD-ONLY12-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 411356// SIMD-ONLY12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 111357// SIMD-ONLY12-NEXT: store i32 [[ADD]], ptr [[B]], align 411358// SIMD-ONLY12-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 411359// SIMD-ONLY12-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()11360// SIMD-ONLY12-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 411361// SIMD-ONLY12-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]11362// SIMD-ONLY12-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 211363// SIMD-ONLY12-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 411364// SIMD-ONLY12-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 411365// SIMD-ONLY12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double11366// SIMD-ONLY12-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+0011367// SIMD-ONLY12-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 011368// SIMD-ONLY12-NEXT: store double [[ADD2]], ptr [[A]], align 411369// SIMD-ONLY12-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 011370// SIMD-ONLY12-NEXT: [[TMP5:%.*]] = load double, ptr [[A3]], align 411371// SIMD-ONLY12-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+0011372// SIMD-ONLY12-NEXT: store double [[INC]], ptr [[A3]], align 411373// SIMD-ONLY12-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i1611374// SIMD-ONLY12-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]]11375// SIMD-ONLY12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP6]]11376// SIMD-ONLY12-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 111377// SIMD-ONLY12-NEXT: store i16 [[CONV4]], ptr [[ARRAYIDX5]], align 211378// SIMD-ONLY12-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]]11379// SIMD-ONLY12-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP7]]11380// SIMD-ONLY12-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX6]], i32 111381// SIMD-ONLY12-NEXT: [[TMP8:%.*]] = load i16, ptr [[ARRAYIDX7]], align 211382// SIMD-ONLY12-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i3211383// SIMD-ONLY12-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 411384// SIMD-ONLY12-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]]11385// SIMD-ONLY12-NEXT: [[TMP10:%.*]] = load ptr, ptr [[SAVED_STACK]], align 411386// SIMD-ONLY12-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP10]])11387// SIMD-ONLY12-NEXT: ret i32 [[ADD9]]11388//11389//11390// SIMD-ONLY12-LABEL: define {{[^@]+}}@_ZL7fstatici11391// SIMD-ONLY12-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {11392// SIMD-ONLY12-NEXT: entry:11393// SIMD-ONLY12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 411394// SIMD-ONLY12-NEXT: [[A:%.*]] = alloca i32, align 411395// SIMD-ONLY12-NEXT: [[AAA:%.*]] = alloca i8, align 111396// SIMD-ONLY12-NEXT: [[B:%.*]] = alloca [10 x i32], align 411397// SIMD-ONLY12-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 411398// SIMD-ONLY12-NEXT: store i32 0, ptr [[A]], align 411399// SIMD-ONLY12-NEXT: store i8 0, ptr [[AAA]], align 111400// SIMD-ONLY12-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 411401// SIMD-ONLY12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 111402// SIMD-ONLY12-NEXT: store i32 [[ADD]], ptr [[A]], align 411403// SIMD-ONLY12-NEXT: [[TMP1:%.*]] = load i8, ptr [[AAA]], align 111404// SIMD-ONLY12-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i3211405// SIMD-ONLY12-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 111406// SIMD-ONLY12-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i811407// SIMD-ONLY12-NEXT: store i8 [[CONV2]], ptr [[AAA]], align 111408// SIMD-ONLY12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i32 0, i32 211409// SIMD-ONLY12-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 411410// SIMD-ONLY12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 111411// SIMD-ONLY12-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 411412// SIMD-ONLY12-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 411413// SIMD-ONLY12-NEXT: ret i32 [[TMP3]]11414//11415//11416// SIMD-ONLY12-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i11417// SIMD-ONLY12-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {11418// SIMD-ONLY12-NEXT: entry:11419// SIMD-ONLY12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 411420// SIMD-ONLY12-NEXT: [[A:%.*]] = alloca i32, align 411421// SIMD-ONLY12-NEXT: [[B:%.*]] = alloca [10 x i32], align 411422// SIMD-ONLY12-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 411423// SIMD-ONLY12-NEXT: store i32 0, ptr [[A]], align 411424// SIMD-ONLY12-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 411425// SIMD-ONLY12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 111426// SIMD-ONLY12-NEXT: store i32 [[ADD]], ptr [[A]], align 411427// SIMD-ONLY12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i32 0, i32 211428// SIMD-ONLY12-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 411429// SIMD-ONLY12-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP1]], 111430// SIMD-ONLY12-NEXT: store i32 [[ADD1]], ptr [[ARRAYIDX]], align 411431// SIMD-ONLY12-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 411432// SIMD-ONLY12-NEXT: ret i32 [[TMP2]]11433//11434//11435// SIMD-ONLY13-LABEL: define {{[^@]+}}@_Z3fooiPd11436// SIMD-ONLY13-SAME: (i32 noundef [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {11437// SIMD-ONLY13-NEXT: entry:11438// SIMD-ONLY13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 411439// SIMD-ONLY13-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 411440// SIMD-ONLY13-NEXT: [[A:%.*]] = alloca i32, align 411441// SIMD-ONLY13-NEXT: [[AA:%.*]] = alloca i16, align 211442// SIMD-ONLY13-NEXT: [[B:%.*]] = alloca [10 x float], align 411443// SIMD-ONLY13-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 411444// SIMD-ONLY13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 411445// SIMD-ONLY13-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 811446// SIMD-ONLY13-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 411447// SIMD-ONLY13-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 411448// SIMD-ONLY13-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 411449// SIMD-ONLY13-NEXT: [[P:%.*]] = alloca ptr, align 6411450// SIMD-ONLY13-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 411451// SIMD-ONLY13-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 411452// SIMD-ONLY13-NEXT: store i32 0, ptr [[A]], align 411453// SIMD-ONLY13-NEXT: store i16 0, ptr [[AA]], align 211454// SIMD-ONLY13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 411455// SIMD-ONLY13-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()11456// SIMD-ONLY13-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 411457// SIMD-ONLY13-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 411458// SIMD-ONLY13-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 411459// SIMD-ONLY13-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 411460// SIMD-ONLY13-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]11461// SIMD-ONLY13-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 811462// SIMD-ONLY13-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 411463// SIMD-ONLY13-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 011464// SIMD-ONLY13-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 411465// SIMD-ONLY13-NEXT: store i32 [[TMP4]], ptr [[X]], align 411466// SIMD-ONLY13-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 111467// SIMD-ONLY13-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 411468// SIMD-ONLY13-NEXT: store i32 [[TMP5]], ptr [[Y]], align 411469// SIMD-ONLY13-NEXT: store ptr [[A]], ptr [[P]], align 6411470// SIMD-ONLY13-NEXT: [[TMP6:%.*]] = load i16, ptr [[AA]], align 211471// SIMD-ONLY13-NEXT: [[CONV:%.*]] = sext i16 [[TMP6]] to i3211472// SIMD-ONLY13-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 111473// SIMD-ONLY13-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i1611474// SIMD-ONLY13-NEXT: store i16 [[CONV2]], ptr [[AA]], align 211475// SIMD-ONLY13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i32 0, i32 211476// SIMD-ONLY13-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX]], align 411477// SIMD-ONLY13-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[VLA]], i32 311478// SIMD-ONLY13-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX3]], align 411479// SIMD-ONLY13-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i32 0, i32 111480// SIMD-ONLY13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX4]], i32 0, i32 211481// SIMD-ONLY13-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX5]], align 811482// SIMD-ONLY13-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP2]]11483// SIMD-ONLY13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, ptr [[VLA1]], i32 [[TMP7]]11484// SIMD-ONLY13-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX6]], i32 311485// SIMD-ONLY13-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX7]], align 811486// SIMD-ONLY13-NEXT: [[X8:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D]], i32 0, i32 011487// SIMD-ONLY13-NEXT: store i64 1, ptr [[X8]], align 411488// SIMD-ONLY13-NEXT: [[Y9:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D]], i32 0, i32 111489// SIMD-ONLY13-NEXT: store i8 1, ptr [[Y9]], align 411490// SIMD-ONLY13-NEXT: [[X10:%.*]] = getelementptr inbounds nuw [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 011491// SIMD-ONLY13-NEXT: [[TMP8:%.*]] = load i32, ptr [[X10]], align 411492// SIMD-ONLY13-NEXT: [[CONV11:%.*]] = sitofp i32 [[TMP8]] to double11493// SIMD-ONLY13-NEXT: [[TMP9:%.*]] = load ptr, ptr [[PTR_ADDR]], align 411494// SIMD-ONLY13-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds double, ptr [[TMP9]], i32 011495// SIMD-ONLY13-NEXT: store double [[CONV11]], ptr [[ARRAYIDX12]], align 411496// SIMD-ONLY13-NEXT: [[TMP10:%.*]] = load ptr, ptr [[PTR_ADDR]], align 411497// SIMD-ONLY13-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, ptr [[TMP10]], i32 011498// SIMD-ONLY13-NEXT: [[TMP11:%.*]] = load double, ptr [[ARRAYIDX13]], align 411499// SIMD-ONLY13-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+0011500// SIMD-ONLY13-NEXT: store double [[INC]], ptr [[ARRAYIDX13]], align 411501// SIMD-ONLY13-NEXT: [[TMP12:%.*]] = load i32, ptr [[A]], align 411502// SIMD-ONLY13-NEXT: [[TMP13:%.*]] = load ptr, ptr [[SAVED_STACK]], align 411503// SIMD-ONLY13-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP13]])11504// SIMD-ONLY13-NEXT: ret i32 [[TMP12]]11505//11506//11507// SIMD-ONLY13-LABEL: define {{[^@]+}}@_Z3bariPd11508// SIMD-ONLY13-SAME: (i32 noundef [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0]] {11509// SIMD-ONLY13-NEXT: entry:11510// SIMD-ONLY13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 411511// SIMD-ONLY13-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 411512// SIMD-ONLY13-NEXT: [[A:%.*]] = alloca i32, align 411513// SIMD-ONLY13-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 411514// SIMD-ONLY13-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 411515// SIMD-ONLY13-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 411516// SIMD-ONLY13-NEXT: store i32 0, ptr [[A]], align 411517// SIMD-ONLY13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 411518// SIMD-ONLY13-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 411519// SIMD-ONLY13-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooiPd(i32 noundef [[TMP0]], ptr noundef [[TMP1]])11520// SIMD-ONLY13-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 411521// SIMD-ONLY13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]]11522// SIMD-ONLY13-NEXT: store i32 [[ADD]], ptr [[A]], align 411523// SIMD-ONLY13-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 411524// SIMD-ONLY13-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP3]])11525// SIMD-ONLY13-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 411526// SIMD-ONLY13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]]11527// SIMD-ONLY13-NEXT: store i32 [[ADD2]], ptr [[A]], align 411528// SIMD-ONLY13-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 411529// SIMD-ONLY13-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP5]])11530// SIMD-ONLY13-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 411531// SIMD-ONLY13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]]11532// SIMD-ONLY13-NEXT: store i32 [[ADD4]], ptr [[A]], align 411533// SIMD-ONLY13-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 411534// SIMD-ONLY13-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP7]])11535// SIMD-ONLY13-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 411536// SIMD-ONLY13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]]11537// SIMD-ONLY13-NEXT: store i32 [[ADD6]], ptr [[A]], align 411538// SIMD-ONLY13-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 411539// SIMD-ONLY13-NEXT: ret i32 [[TMP9]]11540//11541//11542// SIMD-ONLY13-LABEL: define {{[^@]+}}@_ZN2S12r1Ei11543// SIMD-ONLY13-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {11544// SIMD-ONLY13-NEXT: entry:11545// SIMD-ONLY13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 411546// SIMD-ONLY13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 411547// SIMD-ONLY13-NEXT: [[B:%.*]] = alloca i32, align 411548// SIMD-ONLY13-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 411549// SIMD-ONLY13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 411550// SIMD-ONLY13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 411551// SIMD-ONLY13-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 411552// SIMD-ONLY13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 411553// SIMD-ONLY13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 411554// SIMD-ONLY13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 111555// SIMD-ONLY13-NEXT: store i32 [[ADD]], ptr [[B]], align 411556// SIMD-ONLY13-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 411557// SIMD-ONLY13-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()11558// SIMD-ONLY13-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 411559// SIMD-ONLY13-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]11560// SIMD-ONLY13-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 211561// SIMD-ONLY13-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 411562// SIMD-ONLY13-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 411563// SIMD-ONLY13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double11564// SIMD-ONLY13-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+0011565// SIMD-ONLY13-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 011566// SIMD-ONLY13-NEXT: store double [[ADD2]], ptr [[A]], align 411567// SIMD-ONLY13-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 011568// SIMD-ONLY13-NEXT: [[TMP5:%.*]] = load double, ptr [[A3]], align 411569// SIMD-ONLY13-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+0011570// SIMD-ONLY13-NEXT: store double [[INC]], ptr [[A3]], align 411571// SIMD-ONLY13-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i1611572// SIMD-ONLY13-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]]11573// SIMD-ONLY13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP6]]11574// SIMD-ONLY13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 111575// SIMD-ONLY13-NEXT: store i16 [[CONV4]], ptr [[ARRAYIDX5]], align 211576// SIMD-ONLY13-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]]11577// SIMD-ONLY13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP7]]11578// SIMD-ONLY13-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX6]], i32 111579// SIMD-ONLY13-NEXT: [[TMP8:%.*]] = load i16, ptr [[ARRAYIDX7]], align 211580// SIMD-ONLY13-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i3211581// SIMD-ONLY13-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 411582// SIMD-ONLY13-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]]11583// SIMD-ONLY13-NEXT: [[TMP10:%.*]] = load ptr, ptr [[SAVED_STACK]], align 411584// SIMD-ONLY13-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP10]])11585// SIMD-ONLY13-NEXT: ret i32 [[ADD9]]11586//11587//11588// SIMD-ONLY13-LABEL: define {{[^@]+}}@_ZL7fstatici11589// SIMD-ONLY13-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {11590// SIMD-ONLY13-NEXT: entry:11591// SIMD-ONLY13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 411592// SIMD-ONLY13-NEXT: [[A:%.*]] = alloca i32, align 411593// SIMD-ONLY13-NEXT: [[AAA:%.*]] = alloca i8, align 111594// SIMD-ONLY13-NEXT: [[B:%.*]] = alloca [10 x i32], align 411595// SIMD-ONLY13-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 411596// SIMD-ONLY13-NEXT: store i32 0, ptr [[A]], align 411597// SIMD-ONLY13-NEXT: store i8 0, ptr [[AAA]], align 111598// SIMD-ONLY13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 411599// SIMD-ONLY13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 111600// SIMD-ONLY13-NEXT: store i32 [[ADD]], ptr [[A]], align 411601// SIMD-ONLY13-NEXT: [[TMP1:%.*]] = load i8, ptr [[AAA]], align 111602// SIMD-ONLY13-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i3211603// SIMD-ONLY13-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 111604// SIMD-ONLY13-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i811605// SIMD-ONLY13-NEXT: store i8 [[CONV2]], ptr [[AAA]], align 111606// SIMD-ONLY13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i32 0, i32 211607// SIMD-ONLY13-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 411608// SIMD-ONLY13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 111609// SIMD-ONLY13-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 411610// SIMD-ONLY13-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 411611// SIMD-ONLY13-NEXT: ret i32 [[TMP3]]11612//11613//11614// SIMD-ONLY13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i11615// SIMD-ONLY13-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {11616// SIMD-ONLY13-NEXT: entry:11617// SIMD-ONLY13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 411618// SIMD-ONLY13-NEXT: [[A:%.*]] = alloca i32, align 411619// SIMD-ONLY13-NEXT: [[B:%.*]] = alloca [10 x i32], align 411620// SIMD-ONLY13-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 411621// SIMD-ONLY13-NEXT: store i32 0, ptr [[A]], align 411622// SIMD-ONLY13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 411623// SIMD-ONLY13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 111624// SIMD-ONLY13-NEXT: store i32 [[ADD]], ptr [[A]], align 411625// SIMD-ONLY13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i32 0, i32 211626// SIMD-ONLY13-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 411627// SIMD-ONLY13-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP1]], 111628// SIMD-ONLY13-NEXT: store i32 [[ADD1]], ptr [[ARRAYIDX]], align 411629// SIMD-ONLY13-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 411630// SIMD-ONLY13-NEXT: ret i32 [[TMP2]]11631//11632