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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _2// Test host codegen.3// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK14// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s5// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK37// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s8// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK39 10// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"11// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s12// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"13// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"14// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s15// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"16 17// Test target codegen - host bc file has to be created first.18// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc19// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK920// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s21// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK922// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc23// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK1124// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s25// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1126 27// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc28// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"29// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s30// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"31// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc32// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"33// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s34// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"35 36// Test host codegen.37// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK138// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s39// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK140// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK341// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s42// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK343 44// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"45// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s46// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"47// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"48// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s49// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"50 51// Test target codegen - host bc file has to be created first.52// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc53// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK954// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s55// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK956// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc57// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK1158// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s59// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1160 61// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc62// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"63// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s64// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"65// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc66// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"67// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s68// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"69 70// expected-no-diagnostics71#ifndef HEADER72#define HEADER73 74 75 76 77// We have 8 target regions, but only 6 that actually will generate offloading78// code and have mapped arguments, and only 4 have all-constant map sizes.79 80 81 82// Check target registration is registered as a Ctor.83 84 85template<typename tx, typename ty>86struct TT{87  tx X;88  ty Y;89};90 91int foo(int n) {92  int a = 0;93  short aa = 0;94  float b[10];95  float bn[n];96  double c[5][10];97  double cn[5][n];98  TT<long long, char> d;99 100  #pragma omp target parallel nowait101  {102  }103 104  #pragma omp target parallel if(target: 0)105  {106    a += 1;107  }108 109 110  #pragma omp target parallel if(target: 1)111  {112    aa += 1;113#pragma omp cancel parallel114  }115 116 117 118 119  #pragma omp target parallel if(target: n>10)120  {121    a += 1;122    aa += 1;123  }124 125  // We capture 3 VLA sizes in this target region126 127 128 129 130 131  // The names below are not necessarily consistent with the names used for the132  // addresses above as some are repeated.133 134 135 136 137 138 139 140 141 142 143 144  #pragma omp target parallel if(target: n>20)145  {146    a += 1;147    b[2] += 1.0;148    bn[3] += 1.0;149    c[1][2] += 1.0;150    cn[1][3] += 1.0;151    d.X += 1;152    d.Y += 1;153  }154 155  return a;156}157 158// Check that the offloading functions are emitted and that the arguments are159// correct and loaded correctly for the target regions in foo().160 161 162 163// Create stack storage and store argument in there.164 165// Create stack storage and store argument in there.166 167// Create stack storage and store argument in there.168 169// Create local storage for each capture.170 171 172 173// To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.174 175template<typename tx>176tx ftemplate(int n) {177  tx a = 0;178  short aa = 0;179  tx b[10];180 181  #pragma omp target parallel if(target: n>40)182  {183    a += 1;184    aa += 1;185    b[2] += 1;186  }187 188  return a;189}190 191static192int fstatic(int n) {193  int a = 0;194  short aa = 0;195  char aaa = 0;196  int b[10];197 198  #pragma omp target parallel if(target: n>50)199  {200    a += 1;201    aa += 1;202    aaa += 1;203    b[2] += 1;204  }205 206  return a;207}208 209struct S1 {210  double a;211 212  int r1(int n){213    int b = n+1;214    short int c[2][n];215 216    #pragma omp target parallel if(target: n>60)217    {218      this->a = (double)b + 1.5;219      c[1][1] = ++a;220    }221 222    return c[1][1] + (int)b;223  }224};225 226int bar(int n){227  int a = 0;228 229  a += foo(n);230 231  S1 S;232  a += S.r1(n);233 234  a += fstatic(n);235 236  a += ftemplate<int>(n);237 238  return a;239}240 241 242 243// We capture 2 VLA sizes in this target region244 245 246// The names below are not necessarily consistent with the names used for the247// addresses above as some are repeated.248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267// Check that the offloading functions are emitted and that the arguments are268// correct and loaded correctly for the target regions of the callees of bar().269 270// Create local storage for each capture.271// Store captures in the context.272 273 274// To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.275 276 277// Create local storage for each capture.278// Store captures in the context.279 280 281 282 283// To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.284 285// Create local storage for each capture.286// Store captures in the context.287 288 289 290// To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.291 292 293#endif294// CHECK1-LABEL: define {{[^@]+}}@_Z3fooi295// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {296// CHECK1-NEXT:  entry:297// CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4298// CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 4299// CHECK1-NEXT:    [[AA:%.*]] = alloca i16, align 2300// CHECK1-NEXT:    [[B:%.*]] = alloca [10 x float], align 4301// CHECK1-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 8302// CHECK1-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8303// CHECK1-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8304// CHECK1-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8305// CHECK1-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8306// CHECK1-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1307// CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8308// CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8309// CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8310// CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8311// CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8312// CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8313// CHECK1-NEXT:    [[A_CASTED2:%.*]] = alloca i64, align 8314// CHECK1-NEXT:    [[AA_CASTED3:%.*]] = alloca i64, align 8315// CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [2 x ptr], align 8316// CHECK1-NEXT:    [[DOTOFFLOAD_PTRS5:%.*]] = alloca [2 x ptr], align 8317// CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [2 x ptr], align 8318// CHECK1-NEXT:    [[KERNEL_ARGS7:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8319// CHECK1-NEXT:    [[A_CASTED10:%.*]] = alloca i64, align 8320// CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [9 x ptr], align 8321// CHECK1-NEXT:    [[DOTOFFLOAD_PTRS14:%.*]] = alloca [9 x ptr], align 8322// CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [9 x ptr], align 8323// CHECK1-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8324// CHECK1-NEXT:    [[KERNEL_ARGS16:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8325// CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])326// CHECK1-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4327// CHECK1-NEXT:    store i32 0, ptr [[A]], align 4328// CHECK1-NEXT:    store i16 0, ptr [[AA]], align 2329// CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4330// CHECK1-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64331// CHECK1-NEXT:    [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()332// CHECK1-NEXT:    store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8333// CHECK1-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4334// CHECK1-NEXT:    store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8335// CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4336// CHECK1-NEXT:    [[TMP5:%.*]] = zext i32 [[TMP4]] to i64337// CHECK1-NEXT:    [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]338// CHECK1-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8339// CHECK1-NEXT:    store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8340// CHECK1-NEXT:    [[TMP7:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, ptr @.omp_task_entry., i64 -1)341// CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP7]], i32 0, i32 0342// CHECK1-NEXT:    [[TMP9:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP7]])343// CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[A]], align 4344// CHECK1-NEXT:    store i32 [[TMP10]], ptr [[A_CASTED]], align 4345// CHECK1-NEXT:    [[TMP11:%.*]] = load i64, ptr [[A_CASTED]], align 8346// CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i64 [[TMP11]]) #[[ATTR3:[0-9]+]]347// CHECK1-NEXT:    [[TMP12:%.*]] = load i16, ptr [[AA]], align 2348// CHECK1-NEXT:    store i16 [[TMP12]], ptr [[AA_CASTED]], align 2349// CHECK1-NEXT:    [[TMP13:%.*]] = load i64, ptr [[AA_CASTED]], align 8350// CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0351// CHECK1-NEXT:    store i64 [[TMP13]], ptr [[TMP14]], align 8352// CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0353// CHECK1-NEXT:    store i64 [[TMP13]], ptr [[TMP15]], align 8354// CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0355// CHECK1-NEXT:    store ptr null, ptr [[TMP16]], align 8356// CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0357// CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0358// CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0359// CHECK1-NEXT:    store i32 3, ptr [[TMP19]], align 4360// CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1361// CHECK1-NEXT:    store i32 1, ptr [[TMP20]], align 4362// CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2363// CHECK1-NEXT:    store ptr [[TMP17]], ptr [[TMP21]], align 8364// CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3365// CHECK1-NEXT:    store ptr [[TMP18]], ptr [[TMP22]], align 8366// CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4367// CHECK1-NEXT:    store ptr @.offload_sizes, ptr [[TMP23]], align 8368// CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5369// CHECK1-NEXT:    store ptr @.offload_maptypes, ptr [[TMP24]], align 8370// CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6371// CHECK1-NEXT:    store ptr null, ptr [[TMP25]], align 8372// CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7373// CHECK1-NEXT:    store ptr null, ptr [[TMP26]], align 8374// CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8375// CHECK1-NEXT:    store i64 0, ptr [[TMP27]], align 8376// CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9377// CHECK1-NEXT:    store i64 0, ptr [[TMP28]], align 8378// CHECK1-NEXT:    [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10379// CHECK1-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP29]], align 4380// CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11381// CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP30]], align 4382// CHECK1-NEXT:    [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12383// CHECK1-NEXT:    store i32 0, ptr [[TMP31]], align 4384// CHECK1-NEXT:    [[TMP32:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.region_id, ptr [[KERNEL_ARGS]])385// CHECK1-NEXT:    [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0386// CHECK1-NEXT:    br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]387// CHECK1:       omp_offload.failed:388// CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP13]]) #[[ATTR3]]389// CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]390// CHECK1:       omp_offload.cont:391// CHECK1-NEXT:    [[TMP34:%.*]] = load i32, ptr [[A]], align 4392// CHECK1-NEXT:    store i32 [[TMP34]], ptr [[A_CASTED2]], align 4393// CHECK1-NEXT:    [[TMP35:%.*]] = load i64, ptr [[A_CASTED2]], align 8394// CHECK1-NEXT:    [[TMP36:%.*]] = load i16, ptr [[AA]], align 2395// CHECK1-NEXT:    store i16 [[TMP36]], ptr [[AA_CASTED3]], align 2396// CHECK1-NEXT:    [[TMP37:%.*]] = load i64, ptr [[AA_CASTED3]], align 8397// CHECK1-NEXT:    [[TMP38:%.*]] = load i32, ptr [[N_ADDR]], align 4398// CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP38]], 10399// CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]400// CHECK1:       omp_if.then:401// CHECK1-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0402// CHECK1-NEXT:    store i64 [[TMP35]], ptr [[TMP39]], align 8403// CHECK1-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS5]], i32 0, i32 0404// CHECK1-NEXT:    store i64 [[TMP35]], ptr [[TMP40]], align 8405// CHECK1-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0406// CHECK1-NEXT:    store ptr null, ptr [[TMP41]], align 8407// CHECK1-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1408// CHECK1-NEXT:    store i64 [[TMP37]], ptr [[TMP42]], align 8409// CHECK1-NEXT:    [[TMP43:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS5]], i32 0, i32 1410// CHECK1-NEXT:    store i64 [[TMP37]], ptr [[TMP43]], align 8411// CHECK1-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 1412// CHECK1-NEXT:    store ptr null, ptr [[TMP44]], align 8413// CHECK1-NEXT:    [[TMP45:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0414// CHECK1-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS5]], i32 0, i32 0415// CHECK1-NEXT:    [[TMP47:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 0416// CHECK1-NEXT:    store i32 3, ptr [[TMP47]], align 4417// CHECK1-NEXT:    [[TMP48:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 1418// CHECK1-NEXT:    store i32 2, ptr [[TMP48]], align 4419// CHECK1-NEXT:    [[TMP49:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 2420// CHECK1-NEXT:    store ptr [[TMP45]], ptr [[TMP49]], align 8421// CHECK1-NEXT:    [[TMP50:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 3422// CHECK1-NEXT:    store ptr [[TMP46]], ptr [[TMP50]], align 8423// CHECK1-NEXT:    [[TMP51:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 4424// CHECK1-NEXT:    store ptr @.offload_sizes.1, ptr [[TMP51]], align 8425// CHECK1-NEXT:    [[TMP52:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 5426// CHECK1-NEXT:    store ptr @.offload_maptypes.2, ptr [[TMP52]], align 8427// CHECK1-NEXT:    [[TMP53:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 6428// CHECK1-NEXT:    store ptr null, ptr [[TMP53]], align 8429// CHECK1-NEXT:    [[TMP54:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 7430// CHECK1-NEXT:    store ptr null, ptr [[TMP54]], align 8431// CHECK1-NEXT:    [[TMP55:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 8432// CHECK1-NEXT:    store i64 0, ptr [[TMP55]], align 8433// CHECK1-NEXT:    [[TMP56:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 9434// CHECK1-NEXT:    store i64 0, ptr [[TMP56]], align 8435// CHECK1-NEXT:    [[TMP57:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 10436// CHECK1-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP57]], align 4437// CHECK1-NEXT:    [[TMP58:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 11438// CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP58]], align 4439// CHECK1-NEXT:    [[TMP59:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 12440// CHECK1-NEXT:    store i32 0, ptr [[TMP59]], align 4441// CHECK1-NEXT:    [[TMP60:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.region_id, ptr [[KERNEL_ARGS7]])442// CHECK1-NEXT:    [[TMP61:%.*]] = icmp ne i32 [[TMP60]], 0443// CHECK1-NEXT:    br i1 [[TMP61]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]]444// CHECK1:       omp_offload.failed8:445// CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP35]], i64 [[TMP37]]) #[[ATTR3]]446// CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT9]]447// CHECK1:       omp_offload.cont9:448// CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]449// CHECK1:       omp_if.else:450// CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP35]], i64 [[TMP37]]) #[[ATTR3]]451// CHECK1-NEXT:    br label [[OMP_IF_END]]452// CHECK1:       omp_if.end:453// CHECK1-NEXT:    [[TMP62:%.*]] = load i32, ptr [[A]], align 4454// CHECK1-NEXT:    store i32 [[TMP62]], ptr [[A_CASTED10]], align 4455// CHECK1-NEXT:    [[TMP63:%.*]] = load i64, ptr [[A_CASTED10]], align 8456// CHECK1-NEXT:    [[TMP64:%.*]] = load i32, ptr [[N_ADDR]], align 4457// CHECK1-NEXT:    [[CMP11:%.*]] = icmp sgt i32 [[TMP64]], 20458// CHECK1-NEXT:    br i1 [[CMP11]], label [[OMP_IF_THEN12:%.*]], label [[OMP_IF_ELSE19:%.*]]459// CHECK1:       omp_if.then12:460// CHECK1-NEXT:    [[TMP65:%.*]] = mul nuw i64 [[TMP2]], 4461// CHECK1-NEXT:    [[TMP66:%.*]] = mul nuw i64 5, [[TMP5]]462// CHECK1-NEXT:    [[TMP67:%.*]] = mul nuw i64 [[TMP66]], 8463// CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.3, i64 72, i1 false)464// CHECK1-NEXT:    [[TMP68:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0465// CHECK1-NEXT:    store i64 [[TMP63]], ptr [[TMP68]], align 8466// CHECK1-NEXT:    [[TMP69:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 0467// CHECK1-NEXT:    store i64 [[TMP63]], ptr [[TMP69]], align 8468// CHECK1-NEXT:    [[TMP70:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS15]], i64 0, i64 0469// CHECK1-NEXT:    store ptr null, ptr [[TMP70]], align 8470// CHECK1-NEXT:    [[TMP71:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 1471// CHECK1-NEXT:    store ptr [[B]], ptr [[TMP71]], align 8472// CHECK1-NEXT:    [[TMP72:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 1473// CHECK1-NEXT:    store ptr [[B]], ptr [[TMP72]], align 8474// CHECK1-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS15]], i64 0, i64 1475// CHECK1-NEXT:    store ptr null, ptr [[TMP73]], align 8476// CHECK1-NEXT:    [[TMP74:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 2477// CHECK1-NEXT:    store i64 [[TMP2]], ptr [[TMP74]], align 8478// CHECK1-NEXT:    [[TMP75:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 2479// CHECK1-NEXT:    store i64 [[TMP2]], ptr [[TMP75]], align 8480// CHECK1-NEXT:    [[TMP76:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS15]], i64 0, i64 2481// CHECK1-NEXT:    store ptr null, ptr [[TMP76]], align 8482// CHECK1-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 3483// CHECK1-NEXT:    store ptr [[VLA]], ptr [[TMP77]], align 8484// CHECK1-NEXT:    [[TMP78:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 3485// CHECK1-NEXT:    store ptr [[VLA]], ptr [[TMP78]], align 8486// CHECK1-NEXT:    [[TMP79:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3487// CHECK1-NEXT:    store i64 [[TMP65]], ptr [[TMP79]], align 8488// CHECK1-NEXT:    [[TMP80:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS15]], i64 0, i64 3489// CHECK1-NEXT:    store ptr null, ptr [[TMP80]], align 8490// CHECK1-NEXT:    [[TMP81:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 4491// CHECK1-NEXT:    store ptr [[C]], ptr [[TMP81]], align 8492// CHECK1-NEXT:    [[TMP82:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 4493// CHECK1-NEXT:    store ptr [[C]], ptr [[TMP82]], align 8494// CHECK1-NEXT:    [[TMP83:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS15]], i64 0, i64 4495// CHECK1-NEXT:    store ptr null, ptr [[TMP83]], align 8496// CHECK1-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 5497// CHECK1-NEXT:    store i64 5, ptr [[TMP84]], align 8498// CHECK1-NEXT:    [[TMP85:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 5499// CHECK1-NEXT:    store i64 5, ptr [[TMP85]], align 8500// CHECK1-NEXT:    [[TMP86:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS15]], i64 0, i64 5501// CHECK1-NEXT:    store ptr null, ptr [[TMP86]], align 8502// CHECK1-NEXT:    [[TMP87:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 6503// CHECK1-NEXT:    store i64 [[TMP5]], ptr [[TMP87]], align 8504// CHECK1-NEXT:    [[TMP88:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 6505// CHECK1-NEXT:    store i64 [[TMP5]], ptr [[TMP88]], align 8506// CHECK1-NEXT:    [[TMP89:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS15]], i64 0, i64 6507// CHECK1-NEXT:    store ptr null, ptr [[TMP89]], align 8508// CHECK1-NEXT:    [[TMP90:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 7509// CHECK1-NEXT:    store ptr [[VLA1]], ptr [[TMP90]], align 8510// CHECK1-NEXT:    [[TMP91:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 7511// CHECK1-NEXT:    store ptr [[VLA1]], ptr [[TMP91]], align 8512// CHECK1-NEXT:    [[TMP92:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 7513// CHECK1-NEXT:    store i64 [[TMP67]], ptr [[TMP92]], align 8514// CHECK1-NEXT:    [[TMP93:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS15]], i64 0, i64 7515// CHECK1-NEXT:    store ptr null, ptr [[TMP93]], align 8516// CHECK1-NEXT:    [[TMP94:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 8517// CHECK1-NEXT:    store ptr [[D]], ptr [[TMP94]], align 8518// CHECK1-NEXT:    [[TMP95:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 8519// CHECK1-NEXT:    store ptr [[D]], ptr [[TMP95]], align 8520// CHECK1-NEXT:    [[TMP96:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS15]], i64 0, i64 8521// CHECK1-NEXT:    store ptr null, ptr [[TMP96]], align 8522// CHECK1-NEXT:    [[TMP97:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0523// CHECK1-NEXT:    [[TMP98:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 0524// CHECK1-NEXT:    [[TMP99:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0525// CHECK1-NEXT:    [[TMP100:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 0526// CHECK1-NEXT:    store i32 3, ptr [[TMP100]], align 4527// CHECK1-NEXT:    [[TMP101:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 1528// CHECK1-NEXT:    store i32 9, ptr [[TMP101]], align 4529// CHECK1-NEXT:    [[TMP102:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 2530// CHECK1-NEXT:    store ptr [[TMP97]], ptr [[TMP102]], align 8531// CHECK1-NEXT:    [[TMP103:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 3532// CHECK1-NEXT:    store ptr [[TMP98]], ptr [[TMP103]], align 8533// CHECK1-NEXT:    [[TMP104:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 4534// CHECK1-NEXT:    store ptr [[TMP99]], ptr [[TMP104]], align 8535// CHECK1-NEXT:    [[TMP105:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 5536// CHECK1-NEXT:    store ptr @.offload_maptypes.4, ptr [[TMP105]], align 8537// CHECK1-NEXT:    [[TMP106:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 6538// CHECK1-NEXT:    store ptr null, ptr [[TMP106]], align 8539// CHECK1-NEXT:    [[TMP107:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 7540// CHECK1-NEXT:    store ptr null, ptr [[TMP107]], align 8541// CHECK1-NEXT:    [[TMP108:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 8542// CHECK1-NEXT:    store i64 0, ptr [[TMP108]], align 8543// CHECK1-NEXT:    [[TMP109:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 9544// CHECK1-NEXT:    store i64 0, ptr [[TMP109]], align 8545// CHECK1-NEXT:    [[TMP110:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 10546// CHECK1-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP110]], align 4547// CHECK1-NEXT:    [[TMP111:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 11548// CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP111]], align 4549// CHECK1-NEXT:    [[TMP112:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 12550// CHECK1-NEXT:    store i32 0, ptr [[TMP112]], align 4551// CHECK1-NEXT:    [[TMP113:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.region_id, ptr [[KERNEL_ARGS16]])552// CHECK1-NEXT:    [[TMP114:%.*]] = icmp ne i32 [[TMP113]], 0553// CHECK1-NEXT:    br i1 [[TMP114]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]]554// CHECK1:       omp_offload.failed17:555// CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP63]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]]556// CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT18]]557// CHECK1:       omp_offload.cont18:558// CHECK1-NEXT:    br label [[OMP_IF_END20:%.*]]559// CHECK1:       omp_if.else19:560// CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP63]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]]561// CHECK1-NEXT:    br label [[OMP_IF_END20]]562// CHECK1:       omp_if.end20:563// CHECK1-NEXT:    [[TMP115:%.*]] = load i32, ptr [[A]], align 4564// CHECK1-NEXT:    [[TMP116:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8565// CHECK1-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP116]])566// CHECK1-NEXT:    ret i32 [[TMP115]]567//568//569// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100570// CHECK1-SAME: () #[[ATTR2:[0-9]+]] {571// CHECK1-NEXT:  entry:572// CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.omp_outlined)573// CHECK1-NEXT:    ret void574//575//576// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.omp_outlined577// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] {578// CHECK1-NEXT:  entry:579// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8580// CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8581// CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8582// CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8583// CHECK1-NEXT:    ret void584//585//586// CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry.587// CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] {588// CHECK1-NEXT:  entry:589// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4590// CHECK1-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8591// CHECK1-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8592// CHECK1-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8593// CHECK1-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8594// CHECK1-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8595// CHECK1-NEXT:    [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8596// CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4597// CHECK1-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 8598// CHECK1-NEXT:    store i32 [[TMP0]], ptr [[DOTADDR]], align 4599// CHECK1-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 8600// CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4601// CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8602// CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0603// CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2604// CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0605// CHECK1-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8606// CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])607// CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])608// CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])609// CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])610// CHECK1-NEXT:    store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META21:![0-9]+]]611// CHECK1-NEXT:    store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META21]]612// CHECK1-NEXT:    store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META21]]613// CHECK1-NEXT:    store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META21]]614// CHECK1-NEXT:    store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META21]]615// CHECK1-NEXT:    store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META21]]616// CHECK1-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META21]]617// CHECK1-NEXT:    store i32 3, ptr [[KERNEL_ARGS_I]], align 4, !noalias [[META21]]618// CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 1619// CHECK1-NEXT:    store i32 0, ptr [[TMP9]], align 4, !noalias [[META21]]620// CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 2621// CHECK1-NEXT:    store ptr null, ptr [[TMP10]], align 8, !noalias [[META21]]622// CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 3623// CHECK1-NEXT:    store ptr null, ptr [[TMP11]], align 8, !noalias [[META21]]624// CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 4625// CHECK1-NEXT:    store ptr null, ptr [[TMP12]], align 8, !noalias [[META21]]626// CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 5627// CHECK1-NEXT:    store ptr null, ptr [[TMP13]], align 8, !noalias [[META21]]628// CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 6629// CHECK1-NEXT:    store ptr null, ptr [[TMP14]], align 8, !noalias [[META21]]630// CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 7631// CHECK1-NEXT:    store ptr null, ptr [[TMP15]], align 8, !noalias [[META21]]632// CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 8633// CHECK1-NEXT:    store i64 0, ptr [[TMP16]], align 8, !noalias [[META21]]634// CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 9635// CHECK1-NEXT:    store i64 1, ptr [[TMP17]], align 8, !noalias [[META21]]636// CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 10637// CHECK1-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP18]], align 4, !noalias [[META21]]638// CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 11639// CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP19]], align 4, !noalias [[META21]]640// CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 12641// CHECK1-NEXT:    store i32 0, ptr [[TMP20]], align 4, !noalias [[META21]]642// CHECK1-NEXT:    [[TMP21:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, ptr [[KERNEL_ARGS_I]])643// CHECK1-NEXT:    [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0644// CHECK1-NEXT:    br i1 [[TMP22]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]]645// CHECK1:       omp_offload.failed.i:646// CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR3]]647// CHECK1-NEXT:    br label [[DOTOMP_OUTLINED__EXIT]]648// CHECK1:       .omp_outlined..exit:649// CHECK1-NEXT:    ret i32 0650//651//652// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104653// CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR2]] {654// CHECK1-NEXT:  entry:655// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8656// CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8657// CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8658// CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4659// CHECK1-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4660// CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8661// CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104.omp_outlined, i64 [[TMP1]])662// CHECK1-NEXT:    ret void663//664//665// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104.omp_outlined666// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] {667// CHECK1-NEXT:  entry:668// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8669// CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8670// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8671// CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8672// CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8673// CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8674// CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4675// CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1676// CHECK1-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4677// CHECK1-NEXT:    ret void678//679//680// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110681// CHECK1-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] {682// CHECK1-NEXT:  entry:683// CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8684// CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8685// CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8686// CHECK1-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2687// CHECK1-NEXT:    store i16 [[TMP0]], ptr [[AA_CASTED]], align 2688// CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8689// CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined, i64 [[TMP1]])690// CHECK1-NEXT:    ret void691//692//693// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined694// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {695// CHECK1-NEXT:  entry:696// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8697// CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8698// CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8699// CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8700// CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8701// CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8702// CHECK1-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2703// CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP0]] to i32704// CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 1705// CHECK1-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i16706// CHECK1-NEXT:    store i16 [[CONV1]], ptr [[AA_ADDR]], align 2707// CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8708// CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4709// CHECK1-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_cancel(ptr @[[GLOB1]], i32 [[TMP2]], i32 1)710// CHECK1-NEXT:    [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0711// CHECK1-NEXT:    br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]712// CHECK1:       .cancel.exit:713// CHECK1-NEXT:    [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(ptr @[[GLOB2:[0-9]+]], i32 [[TMP2]])714// CHECK1-NEXT:    br label [[DOTCANCEL_CONTINUE]]715// CHECK1:       .cancel.continue:716// CHECK1-NEXT:    ret void717//718//719// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119720// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {721// CHECK1-NEXT:  entry:722// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8723// CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8724// CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8725// CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8726// CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8727// CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8728// CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4729// CHECK1-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4730// CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8731// CHECK1-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2732// CHECK1-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 2733// CHECK1-NEXT:    [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8734// CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.omp_outlined, i64 [[TMP1]], i64 [[TMP3]])735// CHECK1-NEXT:    ret void736//737//738// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.omp_outlined739// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {740// CHECK1-NEXT:  entry:741// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8742// CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8743// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8744// CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8745// CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8746// CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8747// CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8748// CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8749// CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4750// CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1751// CHECK1-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4752// CHECK1-NEXT:    [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 2753// CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32754// CHECK1-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1755// CHECK1-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16756// CHECK1-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 2757// CHECK1-NEXT:    ret void758//759//760// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144761// CHECK1-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {762// CHECK1-NEXT:  entry:763// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8764// CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8765// CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8766// CHECK1-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 8767// CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8768// CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8769// CHECK1-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8770// CHECK1-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 8771// CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8772// CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8773// CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8774// CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8775// CHECK1-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8776// CHECK1-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 8777// CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8778// CHECK1-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8779// CHECK1-NEXT:    store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8780// CHECK1-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 8781// CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8782// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8783// CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8784// CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8785// CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8786// CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8787// CHECK1-NEXT:    [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8788// CHECK1-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8789// CHECK1-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8790// CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4791// CHECK1-NEXT:    store i32 [[TMP8]], ptr [[A_CASTED]], align 4792// CHECK1-NEXT:    [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8793// CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]])794// CHECK1-NEXT:    ret void795//796//797// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.omp_outlined798// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {799// CHECK1-NEXT:  entry:800// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8801// CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8802// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8803// CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8804// CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8805// CHECK1-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 8806// CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8807// CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8808// CHECK1-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8809// CHECK1-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 8810// CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8811// CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8812// CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8813// CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8814// CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8815// CHECK1-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8816// CHECK1-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 8817// CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8818// CHECK1-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8819// CHECK1-NEXT:    store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8820// CHECK1-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 8821// CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8822// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8823// CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8824// CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8825// CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8826// CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8827// CHECK1-NEXT:    [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8828// CHECK1-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8829// CHECK1-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8830// CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4831// CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP8]], 1832// CHECK1-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4833// CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2834// CHECK1-NEXT:    [[TMP9:%.*]] = load float, ptr [[ARRAYIDX]], align 4835// CHECK1-NEXT:    [[CONV:%.*]] = fpext float [[TMP9]] to double836// CHECK1-NEXT:    [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00837// CHECK1-NEXT:    [[CONV6:%.*]] = fptrunc double [[ADD5]] to float838// CHECK1-NEXT:    store float [[CONV6]], ptr [[ARRAYIDX]], align 4839// CHECK1-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 3840// CHECK1-NEXT:    [[TMP10:%.*]] = load float, ptr [[ARRAYIDX7]], align 4841// CHECK1-NEXT:    [[CONV8:%.*]] = fpext float [[TMP10]] to double842// CHECK1-NEXT:    [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00843// CHECK1-NEXT:    [[CONV10:%.*]] = fptrunc double [[ADD9]] to float844// CHECK1-NEXT:    store float [[CONV10]], ptr [[ARRAYIDX7]], align 4845// CHECK1-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1846// CHECK1-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX11]], i64 0, i64 2847// CHECK1-NEXT:    [[TMP11:%.*]] = load double, ptr [[ARRAYIDX12]], align 8848// CHECK1-NEXT:    [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00849// CHECK1-NEXT:    store double [[ADD13]], ptr [[ARRAYIDX12]], align 8850// CHECK1-NEXT:    [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]]851// CHECK1-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP12]]852// CHECK1-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i64 3853// CHECK1-NEXT:    [[TMP13:%.*]] = load double, ptr [[ARRAYIDX15]], align 8854// CHECK1-NEXT:    [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00855// CHECK1-NEXT:    store double [[ADD16]], ptr [[ARRAYIDX15]], align 8856// CHECK1-NEXT:    [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0857// CHECK1-NEXT:    [[TMP14:%.*]] = load i64, ptr [[X]], align 8858// CHECK1-NEXT:    [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1859// CHECK1-NEXT:    store i64 [[ADD17]], ptr [[X]], align 8860// CHECK1-NEXT:    [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1861// CHECK1-NEXT:    [[TMP15:%.*]] = load i8, ptr [[Y]], align 8862// CHECK1-NEXT:    [[CONV18:%.*]] = sext i8 [[TMP15]] to i32863// CHECK1-NEXT:    [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1864// CHECK1-NEXT:    [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8865// CHECK1-NEXT:    store i8 [[CONV20]], ptr [[Y]], align 8866// CHECK1-NEXT:    ret void867//868//869// CHECK1-LABEL: define {{[^@]+}}@_Z3bari870// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {871// CHECK1-NEXT:  entry:872// CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4873// CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 4874// CHECK1-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8875// CHECK1-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4876// CHECK1-NEXT:    store i32 0, ptr [[A]], align 4877// CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4878// CHECK1-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]])879// CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A]], align 4880// CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]881// CHECK1-NEXT:    store i32 [[ADD]], ptr [[A]], align 4882// CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4883// CHECK1-NEXT:    [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]])884// CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 4885// CHECK1-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]886// CHECK1-NEXT:    store i32 [[ADD2]], ptr [[A]], align 4887// CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4888// CHECK1-NEXT:    [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]])889// CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A]], align 4890// CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]891// CHECK1-NEXT:    store i32 [[ADD4]], ptr [[A]], align 4892// CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4893// CHECK1-NEXT:    [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]])894// CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[A]], align 4895// CHECK1-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]896// CHECK1-NEXT:    store i32 [[ADD6]], ptr [[A]], align 4897// CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A]], align 4898// CHECK1-NEXT:    ret i32 [[TMP8]]899//900//901// CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei902// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {903// CHECK1-NEXT:  entry:904// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8905// CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4906// CHECK1-NEXT:    [[B:%.*]] = alloca i32, align 4907// CHECK1-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 8908// CHECK1-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8909// CHECK1-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8910// CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8911// CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8912// CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8913// CHECK1-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8914// CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8915// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8916// CHECK1-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4917// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8918// CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4919// CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1920// CHECK1-NEXT:    store i32 [[ADD]], ptr [[B]], align 4921// CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4922// CHECK1-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64923// CHECK1-NEXT:    [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()924// CHECK1-NEXT:    store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8925// CHECK1-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]926// CHECK1-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2927// CHECK1-NEXT:    store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8928// CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B]], align 4929// CHECK1-NEXT:    store i32 [[TMP5]], ptr [[B_CASTED]], align 4930// CHECK1-NEXT:    [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8931// CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4932// CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60933// CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]934// CHECK1:       omp_if.then:935// CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0936// CHECK1-NEXT:    [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]]937// CHECK1-NEXT:    [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2938// CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.5, i64 40, i1 false)939// CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0940// CHECK1-NEXT:    store ptr [[THIS1]], ptr [[TMP10]], align 8941// CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0942// CHECK1-NEXT:    store ptr [[A]], ptr [[TMP11]], align 8943// CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0944// CHECK1-NEXT:    store ptr null, ptr [[TMP12]], align 8945// CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1946// CHECK1-NEXT:    store i64 [[TMP6]], ptr [[TMP13]], align 8947// CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1948// CHECK1-NEXT:    store i64 [[TMP6]], ptr [[TMP14]], align 8949// CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1950// CHECK1-NEXT:    store ptr null, ptr [[TMP15]], align 8951// CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2952// CHECK1-NEXT:    store i64 2, ptr [[TMP16]], align 8953// CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2954// CHECK1-NEXT:    store i64 2, ptr [[TMP17]], align 8955// CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2956// CHECK1-NEXT:    store ptr null, ptr [[TMP18]], align 8957// CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3958// CHECK1-NEXT:    store i64 [[TMP2]], ptr [[TMP19]], align 8959// CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3960// CHECK1-NEXT:    store i64 [[TMP2]], ptr [[TMP20]], align 8961// CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3962// CHECK1-NEXT:    store ptr null, ptr [[TMP21]], align 8963// CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4964// CHECK1-NEXT:    store ptr [[VLA]], ptr [[TMP22]], align 8965// CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4966// CHECK1-NEXT:    store ptr [[VLA]], ptr [[TMP23]], align 8967// CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 4968// CHECK1-NEXT:    store i64 [[TMP9]], ptr [[TMP24]], align 8969// CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4970// CHECK1-NEXT:    store ptr null, ptr [[TMP25]], align 8971// CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0972// CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0973// CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0974// CHECK1-NEXT:    [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0975// CHECK1-NEXT:    store i32 3, ptr [[TMP29]], align 4976// CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1977// CHECK1-NEXT:    store i32 5, ptr [[TMP30]], align 4978// CHECK1-NEXT:    [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2979// CHECK1-NEXT:    store ptr [[TMP26]], ptr [[TMP31]], align 8980// CHECK1-NEXT:    [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3981// CHECK1-NEXT:    store ptr [[TMP27]], ptr [[TMP32]], align 8982// CHECK1-NEXT:    [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4983// CHECK1-NEXT:    store ptr [[TMP28]], ptr [[TMP33]], align 8984// CHECK1-NEXT:    [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5985// CHECK1-NEXT:    store ptr @.offload_maptypes.6, ptr [[TMP34]], align 8986// CHECK1-NEXT:    [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6987// CHECK1-NEXT:    store ptr null, ptr [[TMP35]], align 8988// CHECK1-NEXT:    [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7989// CHECK1-NEXT:    store ptr null, ptr [[TMP36]], align 8990// CHECK1-NEXT:    [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8991// CHECK1-NEXT:    store i64 0, ptr [[TMP37]], align 8992// CHECK1-NEXT:    [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9993// CHECK1-NEXT:    store i64 0, ptr [[TMP38]], align 8994// CHECK1-NEXT:    [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10995// CHECK1-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP39]], align 4996// CHECK1-NEXT:    [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11997// CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP40]], align 4998// CHECK1-NEXT:    [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12999// CHECK1-NEXT:    store i32 0, ptr [[TMP41]], align 41000// CHECK1-NEXT:    [[TMP42:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, ptr [[KERNEL_ARGS]])1001// CHECK1-NEXT:    [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 01002// CHECK1-NEXT:    br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]1003// CHECK1:       omp_offload.failed:1004// CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR3]]1005// CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]1006// CHECK1:       omp_offload.cont:1007// CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]1008// CHECK1:       omp_if.else:1009// CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR3]]1010// CHECK1-NEXT:    br label [[OMP_IF_END]]1011// CHECK1:       omp_if.end:1012// CHECK1-NEXT:    [[TMP44:%.*]] = mul nsw i64 1, [[TMP2]]1013// CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP44]]1014// CHECK1-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 11015// CHECK1-NEXT:    [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 21016// CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP45]] to i321017// CHECK1-NEXT:    [[TMP46:%.*]] = load i32, ptr [[B]], align 41018// CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]]1019// CHECK1-NEXT:    [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 81020// CHECK1-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP47]])1021// CHECK1-NEXT:    ret i32 [[ADD3]]1022//1023//1024// CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici1025// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {1026// CHECK1-NEXT:  entry:1027// CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 41028// CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 41029// CHECK1-NEXT:    [[AA:%.*]] = alloca i16, align 21030// CHECK1-NEXT:    [[AAA:%.*]] = alloca i8, align 11031// CHECK1-NEXT:    [[B:%.*]] = alloca [10 x i32], align 41032// CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 81033// CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 81034// CHECK1-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 81035// CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 81036// CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 81037// CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 81038// CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81039// CHECK1-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 41040// CHECK1-NEXT:    store i32 0, ptr [[A]], align 41041// CHECK1-NEXT:    store i16 0, ptr [[AA]], align 21042// CHECK1-NEXT:    store i8 0, ptr [[AAA]], align 11043// CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A]], align 41044// CHECK1-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 41045// CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 81046// CHECK1-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA]], align 21047// CHECK1-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 21048// CHECK1-NEXT:    [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 81049// CHECK1-NEXT:    [[TMP4:%.*]] = load i8, ptr [[AAA]], align 11050// CHECK1-NEXT:    store i8 [[TMP4]], ptr [[AAA_CASTED]], align 11051// CHECK1-NEXT:    [[TMP5:%.*]] = load i64, ptr [[AAA_CASTED]], align 81052// CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 41053// CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 501054// CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]1055// CHECK1:       omp_if.then:1056// CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01057// CHECK1-NEXT:    store i64 [[TMP1]], ptr [[TMP7]], align 81058// CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01059// CHECK1-NEXT:    store i64 [[TMP1]], ptr [[TMP8]], align 81060// CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 01061// CHECK1-NEXT:    store ptr null, ptr [[TMP9]], align 81062// CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 11063// CHECK1-NEXT:    store i64 [[TMP3]], ptr [[TMP10]], align 81064// CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 11065// CHECK1-NEXT:    store i64 [[TMP3]], ptr [[TMP11]], align 81066// CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 11067// CHECK1-NEXT:    store ptr null, ptr [[TMP12]], align 81068// CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 21069// CHECK1-NEXT:    store i64 [[TMP5]], ptr [[TMP13]], align 81070// CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 21071// CHECK1-NEXT:    store i64 [[TMP5]], ptr [[TMP14]], align 81072// CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 21073// CHECK1-NEXT:    store ptr null, ptr [[TMP15]], align 81074// CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 31075// CHECK1-NEXT:    store ptr [[B]], ptr [[TMP16]], align 81076// CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 31077// CHECK1-NEXT:    store ptr [[B]], ptr [[TMP17]], align 81078// CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 31079// CHECK1-NEXT:    store ptr null, ptr [[TMP18]], align 81080// CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01081// CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01082// CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 01083// CHECK1-NEXT:    store i32 3, ptr [[TMP21]], align 41084// CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11085// CHECK1-NEXT:    store i32 4, ptr [[TMP22]], align 41086// CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 21087// CHECK1-NEXT:    store ptr [[TMP19]], ptr [[TMP23]], align 81088// CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 31089// CHECK1-NEXT:    store ptr [[TMP20]], ptr [[TMP24]], align 81090// CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 41091// CHECK1-NEXT:    store ptr @.offload_sizes.7, ptr [[TMP25]], align 81092// CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 51093// CHECK1-NEXT:    store ptr @.offload_maptypes.8, ptr [[TMP26]], align 81094// CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 61095// CHECK1-NEXT:    store ptr null, ptr [[TMP27]], align 81096// CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 71097// CHECK1-NEXT:    store ptr null, ptr [[TMP28]], align 81098// CHECK1-NEXT:    [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 81099// CHECK1-NEXT:    store i64 0, ptr [[TMP29]], align 81100// CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 91101// CHECK1-NEXT:    store i64 0, ptr [[TMP30]], align 81102// CHECK1-NEXT:    [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 101103// CHECK1-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP31]], align 41104// CHECK1-NEXT:    [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 111105// CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP32]], align 41106// CHECK1-NEXT:    [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 121107// CHECK1-NEXT:    store i32 0, ptr [[TMP33]], align 41108// CHECK1-NEXT:    [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.region_id, ptr [[KERNEL_ARGS]])1109// CHECK1-NEXT:    [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 01110// CHECK1-NEXT:    br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]1111// CHECK1:       omp_offload.failed:1112// CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR3]]1113// CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]1114// CHECK1:       omp_offload.cont:1115// CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]1116// CHECK1:       omp_if.else:1117// CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR3]]1118// CHECK1-NEXT:    br label [[OMP_IF_END]]1119// CHECK1:       omp_if.end:1120// CHECK1-NEXT:    [[TMP36:%.*]] = load i32, ptr [[A]], align 41121// CHECK1-NEXT:    ret i32 [[TMP36]]1122//1123//1124// CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i1125// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {1126// CHECK1-NEXT:  entry:1127// CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 41128// CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 41129// CHECK1-NEXT:    [[AA:%.*]] = alloca i16, align 21130// CHECK1-NEXT:    [[B:%.*]] = alloca [10 x i32], align 41131// CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 81132// CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 81133// CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 81134// CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 81135// CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 81136// CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81137// CHECK1-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 41138// CHECK1-NEXT:    store i32 0, ptr [[A]], align 41139// CHECK1-NEXT:    store i16 0, ptr [[AA]], align 21140// CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A]], align 41141// CHECK1-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 41142// CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 81143// CHECK1-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA]], align 21144// CHECK1-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 21145// CHECK1-NEXT:    [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 81146// CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 41147// CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 401148// CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]1149// CHECK1:       omp_if.then:1150// CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01151// CHECK1-NEXT:    store i64 [[TMP1]], ptr [[TMP5]], align 81152// CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01153// CHECK1-NEXT:    store i64 [[TMP1]], ptr [[TMP6]], align 81154// CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 01155// CHECK1-NEXT:    store ptr null, ptr [[TMP7]], align 81156// CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 11157// CHECK1-NEXT:    store i64 [[TMP3]], ptr [[TMP8]], align 81158// CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 11159// CHECK1-NEXT:    store i64 [[TMP3]], ptr [[TMP9]], align 81160// CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 11161// CHECK1-NEXT:    store ptr null, ptr [[TMP10]], align 81162// CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 21163// CHECK1-NEXT:    store ptr [[B]], ptr [[TMP11]], align 81164// CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 21165// CHECK1-NEXT:    store ptr [[B]], ptr [[TMP12]], align 81166// CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 21167// CHECK1-NEXT:    store ptr null, ptr [[TMP13]], align 81168// CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01169// CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01170// CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 01171// CHECK1-NEXT:    store i32 3, ptr [[TMP16]], align 41172// CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11173// CHECK1-NEXT:    store i32 3, ptr [[TMP17]], align 41174// CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 21175// CHECK1-NEXT:    store ptr [[TMP14]], ptr [[TMP18]], align 81176// CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 31177// CHECK1-NEXT:    store ptr [[TMP15]], ptr [[TMP19]], align 81178// CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 41179// CHECK1-NEXT:    store ptr @.offload_sizes.9, ptr [[TMP20]], align 81180// CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 51181// CHECK1-NEXT:    store ptr @.offload_maptypes.10, ptr [[TMP21]], align 81182// CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 61183// CHECK1-NEXT:    store ptr null, ptr [[TMP22]], align 81184// CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 71185// CHECK1-NEXT:    store ptr null, ptr [[TMP23]], align 81186// CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 81187// CHECK1-NEXT:    store i64 0, ptr [[TMP24]], align 81188// CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 91189// CHECK1-NEXT:    store i64 0, ptr [[TMP25]], align 81190// CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 101191// CHECK1-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP26]], align 41192// CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 111193// CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP27]], align 41194// CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 121195// CHECK1-NEXT:    store i32 0, ptr [[TMP28]], align 41196// CHECK1-NEXT:    [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.region_id, ptr [[KERNEL_ARGS]])1197// CHECK1-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 01198// CHECK1-NEXT:    br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]1199// CHECK1:       omp_offload.failed:1200// CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]]1201// CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]1202// CHECK1:       omp_offload.cont:1203// CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]1204// CHECK1:       omp_if.else:1205// CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]]1206// CHECK1-NEXT:    br label [[OMP_IF_END]]1207// CHECK1:       omp_if.end:1208// CHECK1-NEXT:    [[TMP31:%.*]] = load i32, ptr [[A]], align 41209// CHECK1-NEXT:    ret i32 [[TMP31]]1210//1211//1212// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l2161213// CHECK1-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {1214// CHECK1-NEXT:  entry:1215// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81216// CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 81217// CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 81218// CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 81219// CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 81220// CHECK1-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 81221// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81222// CHECK1-NEXT:    store i64 [[B]], ptr [[B_ADDR]], align 81223// CHECK1-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 81224// CHECK1-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 81225// CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 81226// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81227// CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 81228// CHECK1-NEXT:    [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 81229// CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 81230// CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 41231// CHECK1-NEXT:    store i32 [[TMP4]], ptr [[B_CASTED]], align 41232// CHECK1-NEXT:    [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 81233// CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]])1234// CHECK1-NEXT:    ret void1235//1236//1237// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined1238// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {1239// CHECK1-NEXT:  entry:1240// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81241// CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81242// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81243// CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 81244// CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 81245// CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 81246// CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 81247// CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81248// CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81249// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81250// CHECK1-NEXT:    store i64 [[B]], ptr [[B_ADDR]], align 81251// CHECK1-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 81252// CHECK1-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 81253// CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 81254// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81255// CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 81256// CHECK1-NEXT:    [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 81257// CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 81258// CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 41259// CHECK1-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP4]] to double1260// CHECK1-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+001261// CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 01262// CHECK1-NEXT:    store double [[ADD]], ptr [[A]], align 81263// CHECK1-NEXT:    [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 01264// CHECK1-NEXT:    [[TMP5:%.*]] = load double, ptr [[A3]], align 81265// CHECK1-NEXT:    [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+001266// CHECK1-NEXT:    store double [[INC]], ptr [[A3]], align 81267// CHECK1-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i161268// CHECK1-NEXT:    [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]]1269// CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP6]]1270// CHECK1-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 11271// CHECK1-NEXT:    store i16 [[CONV4]], ptr [[ARRAYIDX5]], align 21272// CHECK1-NEXT:    ret void1273//1274//1275// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l1981276// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {1277// CHECK1-NEXT:  entry:1278// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 81279// CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 81280// CHECK1-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 81281// CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 81282// CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 81283// CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 81284// CHECK1-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 81285// CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 81286// CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 81287// CHECK1-NEXT:    store i64 [[AAA]], ptr [[AAA_ADDR]], align 81288// CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 81289// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 81290// CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 41291// CHECK1-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 41292// CHECK1-NEXT:    [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 81293// CHECK1-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 21294// CHECK1-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 21295// CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 81296// CHECK1-NEXT:    [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 11297// CHECK1-NEXT:    store i8 [[TMP5]], ptr [[AAA_CASTED]], align 11298// CHECK1-NEXT:    [[TMP6:%.*]] = load i64, ptr [[AAA_CASTED]], align 81299// CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], ptr [[TMP0]])1300// CHECK1-NEXT:    ret void1301//1302//1303// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.omp_outlined1304// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {1305// CHECK1-NEXT:  entry:1306// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81307// CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81308// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 81309// CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 81310// CHECK1-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 81311// CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 81312// CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81313// CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81314// CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 81315// CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 81316// CHECK1-NEXT:    store i64 [[AAA]], ptr [[AAA_ADDR]], align 81317// CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 81318// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 81319// CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 41320// CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 11321// CHECK1-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 41322// CHECK1-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 21323// CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i321324// CHECK1-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 11325// CHECK1-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i161326// CHECK1-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 21327// CHECK1-NEXT:    [[TMP3:%.*]] = load i8, ptr [[AAA_ADDR]], align 11328// CHECK1-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP3]] to i321329// CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 11330// CHECK1-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i81331// CHECK1-NEXT:    store i8 [[CONV5]], ptr [[AAA_ADDR]], align 11332// CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 21333// CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX]], align 41334// CHECK1-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP4]], 11335// CHECK1-NEXT:    store i32 [[ADD6]], ptr [[ARRAYIDX]], align 41336// CHECK1-NEXT:    ret void1337//1338//1339// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l1811340// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {1341// CHECK1-NEXT:  entry:1342// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 81343// CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 81344// CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 81345// CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 81346// CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 81347// CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 81348// CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 81349// CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 81350// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 81351// CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 41352// CHECK1-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 41353// CHECK1-NEXT:    [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 81354// CHECK1-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 21355// CHECK1-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 21356// CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 81357// CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]])1358// CHECK1-NEXT:    ret void1359//1360//1361// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.omp_outlined1362// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {1363// CHECK1-NEXT:  entry:1364// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81365// CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81366// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 81367// CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 81368// CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 81369// CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81370// CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81371// CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 81372// CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 81373// CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 81374// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 81375// CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 41376// CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 11377// CHECK1-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 41378// CHECK1-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 21379// CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i321380// CHECK1-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 11381// CHECK1-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i161382// CHECK1-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 21383// CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 21384// CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 41385// CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 11386// CHECK1-NEXT:    store i32 [[ADD3]], ptr [[ARRAYIDX]], align 41387// CHECK1-NEXT:    ret void1388//1389//1390// CHECK3-LABEL: define {{[^@]+}}@_Z3fooi1391// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] {1392// CHECK3-NEXT:  entry:1393// CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 41394// CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 41395// CHECK3-NEXT:    [[AA:%.*]] = alloca i16, align 21396// CHECK3-NEXT:    [[B:%.*]] = alloca [10 x float], align 41397// CHECK3-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 41398// CHECK3-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 41399// CHECK3-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 81400// CHECK3-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 41401// CHECK3-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 41402// CHECK3-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 11403// CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 41404// CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 41405// CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 41406// CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 41407// CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 41408// CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81409// CHECK3-NEXT:    [[A_CASTED2:%.*]] = alloca i32, align 41410// CHECK3-NEXT:    [[AA_CASTED3:%.*]] = alloca i32, align 41411// CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [2 x ptr], align 41412// CHECK3-NEXT:    [[DOTOFFLOAD_PTRS5:%.*]] = alloca [2 x ptr], align 41413// CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [2 x ptr], align 41414// CHECK3-NEXT:    [[KERNEL_ARGS7:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 81415// CHECK3-NEXT:    [[A_CASTED10:%.*]] = alloca i32, align 41416// CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [9 x ptr], align 41417// CHECK3-NEXT:    [[DOTOFFLOAD_PTRS14:%.*]] = alloca [9 x ptr], align 41418// CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [9 x ptr], align 41419// CHECK3-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 41420// CHECK3-NEXT:    [[KERNEL_ARGS16:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 81421// CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])1422// CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 41423// CHECK3-NEXT:    store i32 0, ptr [[A]], align 41424// CHECK3-NEXT:    store i16 0, ptr [[AA]], align 21425// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 41426// CHECK3-NEXT:    [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()1427// CHECK3-NEXT:    store ptr [[TMP2]], ptr [[SAVED_STACK]], align 41428// CHECK3-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 41429// CHECK3-NEXT:    store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 41430// CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 41431// CHECK3-NEXT:    [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]1432// CHECK3-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 81433// CHECK3-NEXT:    store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 41434// CHECK3-NEXT:    [[TMP5:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 20, i32 1, ptr @.omp_task_entry., i64 -1)1435// CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP5]], i32 0, i32 01436// CHECK3-NEXT:    [[TMP7:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP5]])1437// CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A]], align 41438// CHECK3-NEXT:    store i32 [[TMP8]], ptr [[A_CASTED]], align 41439// CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 41440// CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i32 [[TMP9]]) #[[ATTR3:[0-9]+]]1441// CHECK3-NEXT:    [[TMP10:%.*]] = load i16, ptr [[AA]], align 21442// CHECK3-NEXT:    store i16 [[TMP10]], ptr [[AA_CASTED]], align 21443// CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[AA_CASTED]], align 41444// CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01445// CHECK3-NEXT:    store i32 [[TMP11]], ptr [[TMP12]], align 41446// CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01447// CHECK3-NEXT:    store i32 [[TMP11]], ptr [[TMP13]], align 41448// CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 01449// CHECK3-NEXT:    store ptr null, ptr [[TMP14]], align 41450// CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01451// CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01452// CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 01453// CHECK3-NEXT:    store i32 3, ptr [[TMP17]], align 41454// CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11455// CHECK3-NEXT:    store i32 1, ptr [[TMP18]], align 41456// CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 21457// CHECK3-NEXT:    store ptr [[TMP15]], ptr [[TMP19]], align 41458// CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 31459// CHECK3-NEXT:    store ptr [[TMP16]], ptr [[TMP20]], align 41460// CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 41461// CHECK3-NEXT:    store ptr @.offload_sizes, ptr [[TMP21]], align 41462// CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 51463// CHECK3-NEXT:    store ptr @.offload_maptypes, ptr [[TMP22]], align 41464// CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 61465// CHECK3-NEXT:    store ptr null, ptr [[TMP23]], align 41466// CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 71467// CHECK3-NEXT:    store ptr null, ptr [[TMP24]], align 41468// CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 81469// CHECK3-NEXT:    store i64 0, ptr [[TMP25]], align 81470// CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 91471// CHECK3-NEXT:    store i64 0, ptr [[TMP26]], align 81472// CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 101473// CHECK3-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP27]], align 41474// CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 111475// CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP28]], align 41476// CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 121477// CHECK3-NEXT:    store i32 0, ptr [[TMP29]], align 41478// CHECK3-NEXT:    [[TMP30:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.region_id, ptr [[KERNEL_ARGS]])1479// CHECK3-NEXT:    [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 01480// CHECK3-NEXT:    br i1 [[TMP31]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]1481// CHECK3:       omp_offload.failed:1482// CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP11]]) #[[ATTR3]]1483// CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]1484// CHECK3:       omp_offload.cont:1485// CHECK3-NEXT:    [[TMP32:%.*]] = load i32, ptr [[A]], align 41486// CHECK3-NEXT:    store i32 [[TMP32]], ptr [[A_CASTED2]], align 41487// CHECK3-NEXT:    [[TMP33:%.*]] = load i32, ptr [[A_CASTED2]], align 41488// CHECK3-NEXT:    [[TMP34:%.*]] = load i16, ptr [[AA]], align 21489// CHECK3-NEXT:    store i16 [[TMP34]], ptr [[AA_CASTED3]], align 21490// CHECK3-NEXT:    [[TMP35:%.*]] = load i32, ptr [[AA_CASTED3]], align 41491// CHECK3-NEXT:    [[TMP36:%.*]] = load i32, ptr [[N_ADDR]], align 41492// CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP36]], 101493// CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]1494// CHECK3:       omp_if.then:1495// CHECK3-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 01496// CHECK3-NEXT:    store i32 [[TMP33]], ptr [[TMP37]], align 41497// CHECK3-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS5]], i32 0, i32 01498// CHECK3-NEXT:    store i32 [[TMP33]], ptr [[TMP38]], align 41499// CHECK3-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 01500// CHECK3-NEXT:    store ptr null, ptr [[TMP39]], align 41501// CHECK3-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 11502// CHECK3-NEXT:    store i32 [[TMP35]], ptr [[TMP40]], align 41503// CHECK3-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS5]], i32 0, i32 11504// CHECK3-NEXT:    store i32 [[TMP35]], ptr [[TMP41]], align 41505// CHECK3-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 11506// CHECK3-NEXT:    store ptr null, ptr [[TMP42]], align 41507// CHECK3-NEXT:    [[TMP43:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 01508// CHECK3-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS5]], i32 0, i32 01509// CHECK3-NEXT:    [[TMP45:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 01510// CHECK3-NEXT:    store i32 3, ptr [[TMP45]], align 41511// CHECK3-NEXT:    [[TMP46:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 11512// CHECK3-NEXT:    store i32 2, ptr [[TMP46]], align 41513// CHECK3-NEXT:    [[TMP47:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 21514// CHECK3-NEXT:    store ptr [[TMP43]], ptr [[TMP47]], align 41515// CHECK3-NEXT:    [[TMP48:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 31516// CHECK3-NEXT:    store ptr [[TMP44]], ptr [[TMP48]], align 41517// CHECK3-NEXT:    [[TMP49:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 41518// CHECK3-NEXT:    store ptr @.offload_sizes.1, ptr [[TMP49]], align 41519// CHECK3-NEXT:    [[TMP50:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 51520// CHECK3-NEXT:    store ptr @.offload_maptypes.2, ptr [[TMP50]], align 41521// CHECK3-NEXT:    [[TMP51:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 61522// CHECK3-NEXT:    store ptr null, ptr [[TMP51]], align 41523// CHECK3-NEXT:    [[TMP52:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 71524// CHECK3-NEXT:    store ptr null, ptr [[TMP52]], align 41525// CHECK3-NEXT:    [[TMP53:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 81526// CHECK3-NEXT:    store i64 0, ptr [[TMP53]], align 81527// CHECK3-NEXT:    [[TMP54:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 91528// CHECK3-NEXT:    store i64 0, ptr [[TMP54]], align 81529// CHECK3-NEXT:    [[TMP55:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 101530// CHECK3-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP55]], align 41531// CHECK3-NEXT:    [[TMP56:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 111532// CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP56]], align 41533// CHECK3-NEXT:    [[TMP57:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 121534// CHECK3-NEXT:    store i32 0, ptr [[TMP57]], align 41535// CHECK3-NEXT:    [[TMP58:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.region_id, ptr [[KERNEL_ARGS7]])1536// CHECK3-NEXT:    [[TMP59:%.*]] = icmp ne i32 [[TMP58]], 01537// CHECK3-NEXT:    br i1 [[TMP59]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]]1538// CHECK3:       omp_offload.failed8:1539// CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP33]], i32 [[TMP35]]) #[[ATTR3]]1540// CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT9]]1541// CHECK3:       omp_offload.cont9:1542// CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]1543// CHECK3:       omp_if.else:1544// CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP33]], i32 [[TMP35]]) #[[ATTR3]]1545// CHECK3-NEXT:    br label [[OMP_IF_END]]1546// CHECK3:       omp_if.end:1547// CHECK3-NEXT:    [[TMP60:%.*]] = load i32, ptr [[A]], align 41548// CHECK3-NEXT:    store i32 [[TMP60]], ptr [[A_CASTED10]], align 41549// CHECK3-NEXT:    [[TMP61:%.*]] = load i32, ptr [[A_CASTED10]], align 41550// CHECK3-NEXT:    [[TMP62:%.*]] = load i32, ptr [[N_ADDR]], align 41551// CHECK3-NEXT:    [[CMP11:%.*]] = icmp sgt i32 [[TMP62]], 201552// CHECK3-NEXT:    br i1 [[CMP11]], label [[OMP_IF_THEN12:%.*]], label [[OMP_IF_ELSE19:%.*]]1553// CHECK3:       omp_if.then12:1554// CHECK3-NEXT:    [[TMP63:%.*]] = mul nuw i32 [[TMP1]], 41555// CHECK3-NEXT:    [[TMP64:%.*]] = sext i32 [[TMP63]] to i641556// CHECK3-NEXT:    [[TMP65:%.*]] = mul nuw i32 5, [[TMP3]]1557// CHECK3-NEXT:    [[TMP66:%.*]] = mul nuw i32 [[TMP65]], 81558// CHECK3-NEXT:    [[TMP67:%.*]] = sext i32 [[TMP66]] to i641559// CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.3, i32 72, i1 false)1560// CHECK3-NEXT:    [[TMP68:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 01561// CHECK3-NEXT:    store i32 [[TMP61]], ptr [[TMP68]], align 41562// CHECK3-NEXT:    [[TMP69:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 01563// CHECK3-NEXT:    store i32 [[TMP61]], ptr [[TMP69]], align 41564// CHECK3-NEXT:    [[TMP70:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 01565// CHECK3-NEXT:    store ptr null, ptr [[TMP70]], align 41566// CHECK3-NEXT:    [[TMP71:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 11567// CHECK3-NEXT:    store ptr [[B]], ptr [[TMP71]], align 41568// CHECK3-NEXT:    [[TMP72:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 11569// CHECK3-NEXT:    store ptr [[B]], ptr [[TMP72]], align 41570// CHECK3-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 11571// CHECK3-NEXT:    store ptr null, ptr [[TMP73]], align 41572// CHECK3-NEXT:    [[TMP74:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 21573// CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP74]], align 41574// CHECK3-NEXT:    [[TMP75:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 21575// CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP75]], align 41576// CHECK3-NEXT:    [[TMP76:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 21577// CHECK3-NEXT:    store ptr null, ptr [[TMP76]], align 41578// CHECK3-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 31579// CHECK3-NEXT:    store ptr [[VLA]], ptr [[TMP77]], align 41580// CHECK3-NEXT:    [[TMP78:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 31581// CHECK3-NEXT:    store ptr [[VLA]], ptr [[TMP78]], align 41582// CHECK3-NEXT:    [[TMP79:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 31583// CHECK3-NEXT:    store i64 [[TMP64]], ptr [[TMP79]], align 41584// CHECK3-NEXT:    [[TMP80:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 31585// CHECK3-NEXT:    store ptr null, ptr [[TMP80]], align 41586// CHECK3-NEXT:    [[TMP81:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 41587// CHECK3-NEXT:    store ptr [[C]], ptr [[TMP81]], align 41588// CHECK3-NEXT:    [[TMP82:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 41589// CHECK3-NEXT:    store ptr [[C]], ptr [[TMP82]], align 41590// CHECK3-NEXT:    [[TMP83:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 41591// CHECK3-NEXT:    store ptr null, ptr [[TMP83]], align 41592// CHECK3-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 51593// CHECK3-NEXT:    store i32 5, ptr [[TMP84]], align 41594// CHECK3-NEXT:    [[TMP85:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 51595// CHECK3-NEXT:    store i32 5, ptr [[TMP85]], align 41596// CHECK3-NEXT:    [[TMP86:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 51597// CHECK3-NEXT:    store ptr null, ptr [[TMP86]], align 41598// CHECK3-NEXT:    [[TMP87:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 61599// CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP87]], align 41600// CHECK3-NEXT:    [[TMP88:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 61601// CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP88]], align 41602// CHECK3-NEXT:    [[TMP89:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 61603// CHECK3-NEXT:    store ptr null, ptr [[TMP89]], align 41604// CHECK3-NEXT:    [[TMP90:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 71605// CHECK3-NEXT:    store ptr [[VLA1]], ptr [[TMP90]], align 41606// CHECK3-NEXT:    [[TMP91:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 71607// CHECK3-NEXT:    store ptr [[VLA1]], ptr [[TMP91]], align 41608// CHECK3-NEXT:    [[TMP92:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 71609// CHECK3-NEXT:    store i64 [[TMP67]], ptr [[TMP92]], align 41610// CHECK3-NEXT:    [[TMP93:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 71611// CHECK3-NEXT:    store ptr null, ptr [[TMP93]], align 41612// CHECK3-NEXT:    [[TMP94:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 81613// CHECK3-NEXT:    store ptr [[D]], ptr [[TMP94]], align 41614// CHECK3-NEXT:    [[TMP95:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 81615// CHECK3-NEXT:    store ptr [[D]], ptr [[TMP95]], align 41616// CHECK3-NEXT:    [[TMP96:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 81617// CHECK3-NEXT:    store ptr null, ptr [[TMP96]], align 41618// CHECK3-NEXT:    [[TMP97:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 01619// CHECK3-NEXT:    [[TMP98:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 01620// CHECK3-NEXT:    [[TMP99:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 01621// CHECK3-NEXT:    [[TMP100:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 01622// CHECK3-NEXT:    store i32 3, ptr [[TMP100]], align 41623// CHECK3-NEXT:    [[TMP101:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 11624// CHECK3-NEXT:    store i32 9, ptr [[TMP101]], align 41625// CHECK3-NEXT:    [[TMP102:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 21626// CHECK3-NEXT:    store ptr [[TMP97]], ptr [[TMP102]], align 41627// CHECK3-NEXT:    [[TMP103:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 31628// CHECK3-NEXT:    store ptr [[TMP98]], ptr [[TMP103]], align 41629// CHECK3-NEXT:    [[TMP104:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 41630// CHECK3-NEXT:    store ptr [[TMP99]], ptr [[TMP104]], align 41631// CHECK3-NEXT:    [[TMP105:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 51632// CHECK3-NEXT:    store ptr @.offload_maptypes.4, ptr [[TMP105]], align 41633// CHECK3-NEXT:    [[TMP106:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 61634// CHECK3-NEXT:    store ptr null, ptr [[TMP106]], align 41635// CHECK3-NEXT:    [[TMP107:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 71636// CHECK3-NEXT:    store ptr null, ptr [[TMP107]], align 41637// CHECK3-NEXT:    [[TMP108:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 81638// CHECK3-NEXT:    store i64 0, ptr [[TMP108]], align 81639// CHECK3-NEXT:    [[TMP109:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 91640// CHECK3-NEXT:    store i64 0, ptr [[TMP109]], align 81641// CHECK3-NEXT:    [[TMP110:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 101642// CHECK3-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP110]], align 41643// CHECK3-NEXT:    [[TMP111:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 111644// CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP111]], align 41645// CHECK3-NEXT:    [[TMP112:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 121646// CHECK3-NEXT:    store i32 0, ptr [[TMP112]], align 41647// CHECK3-NEXT:    [[TMP113:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.region_id, ptr [[KERNEL_ARGS16]])1648// CHECK3-NEXT:    [[TMP114:%.*]] = icmp ne i32 [[TMP113]], 01649// CHECK3-NEXT:    br i1 [[TMP114]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]]1650// CHECK3:       omp_offload.failed17:1651// CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP61]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]]1652// CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT18]]1653// CHECK3:       omp_offload.cont18:1654// CHECK3-NEXT:    br label [[OMP_IF_END20:%.*]]1655// CHECK3:       omp_if.else19:1656// CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP61]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]]1657// CHECK3-NEXT:    br label [[OMP_IF_END20]]1658// CHECK3:       omp_if.end20:1659// CHECK3-NEXT:    [[TMP115:%.*]] = load i32, ptr [[A]], align 41660// CHECK3-NEXT:    [[TMP116:%.*]] = load ptr, ptr [[SAVED_STACK]], align 41661// CHECK3-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP116]])1662// CHECK3-NEXT:    ret i32 [[TMP115]]1663//1664//1665// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1001666// CHECK3-SAME: () #[[ATTR2:[0-9]+]] {1667// CHECK3-NEXT:  entry:1668// CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.omp_outlined)1669// CHECK3-NEXT:    ret void1670//1671//1672// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.omp_outlined1673// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] {1674// CHECK3-NEXT:  entry:1675// CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 41676// CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 41677// CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 41678// CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 41679// CHECK3-NEXT:    ret void1680//1681//1682// CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry.1683// CHECK3-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] {1684// CHECK3-NEXT:  entry:1685// CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 41686// CHECK3-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 41687// CHECK3-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 41688// CHECK3-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 41689// CHECK3-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 41690// CHECK3-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 41691// CHECK3-NEXT:    [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81692// CHECK3-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 41693// CHECK3-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 41694// CHECK3-NEXT:    store i32 [[TMP0]], ptr [[DOTADDR]], align 41695// CHECK3-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 41696// CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 41697// CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 41698// CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 01699// CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 21700// CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 01701// CHECK3-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 41702// CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]])1703// CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])1704// CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])1705// CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])1706// CHECK3-NEXT:    store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META22:![0-9]+]]1707// CHECK3-NEXT:    store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 4, !noalias [[META22]]1708// CHECK3-NEXT:    store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias [[META22]]1709// CHECK3-NEXT:    store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias [[META22]]1710// CHECK3-NEXT:    store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 4, !noalias [[META22]]1711// CHECK3-NEXT:    store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 4, !noalias [[META22]]1712// CHECK3-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias [[META22]]1713// CHECK3-NEXT:    store i32 3, ptr [[KERNEL_ARGS_I]], align 4, !noalias [[META22]]1714// CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 11715// CHECK3-NEXT:    store i32 0, ptr [[TMP9]], align 4, !noalias [[META22]]1716// CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 21717// CHECK3-NEXT:    store ptr null, ptr [[TMP10]], align 4, !noalias [[META22]]1718// CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 31719// CHECK3-NEXT:    store ptr null, ptr [[TMP11]], align 4, !noalias [[META22]]1720// CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 41721// CHECK3-NEXT:    store ptr null, ptr [[TMP12]], align 4, !noalias [[META22]]1722// CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 51723// CHECK3-NEXT:    store ptr null, ptr [[TMP13]], align 4, !noalias [[META22]]1724// CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 61725// CHECK3-NEXT:    store ptr null, ptr [[TMP14]], align 4, !noalias [[META22]]1726// CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 71727// CHECK3-NEXT:    store ptr null, ptr [[TMP15]], align 4, !noalias [[META22]]1728// CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 81729// CHECK3-NEXT:    store i64 0, ptr [[TMP16]], align 8, !noalias [[META22]]1730// CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 91731// CHECK3-NEXT:    store i64 1, ptr [[TMP17]], align 8, !noalias [[META22]]1732// CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 101733// CHECK3-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP18]], align 4, !noalias [[META22]]1734// CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 111735// CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP19]], align 4, !noalias [[META22]]1736// CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 121737// CHECK3-NEXT:    store i32 0, ptr [[TMP20]], align 4, !noalias [[META22]]1738// CHECK3-NEXT:    [[TMP21:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, ptr [[KERNEL_ARGS_I]])1739// CHECK3-NEXT:    [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 01740// CHECK3-NEXT:    br i1 [[TMP22]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]]1741// CHECK3:       omp_offload.failed.i:1742// CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR3]]1743// CHECK3-NEXT:    br label [[DOTOMP_OUTLINED__EXIT]]1744// CHECK3:       .omp_outlined..exit:1745// CHECK3-NEXT:    ret i32 01746//1747//1748// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1041749// CHECK3-SAME: (i32 noundef [[A:%.*]]) #[[ATTR2]] {1750// CHECK3-NEXT:  entry:1751// CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 41752// CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 41753// CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 41754// CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41755// CHECK3-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 41756// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 41757// CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104.omp_outlined, i32 [[TMP1]])1758// CHECK3-NEXT:    ret void1759//1760//1761// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104.omp_outlined1762// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] {1763// CHECK3-NEXT:  entry:1764// CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 41765// CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 41766// CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 41767// CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 41768// CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 41769// CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 41770// CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41771// CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 11772// CHECK3-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 41773// CHECK3-NEXT:    ret void1774//1775//1776// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1101777// CHECK3-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] {1778// CHECK3-NEXT:  entry:1779// CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 41780// CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 41781// CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 41782// CHECK3-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 21783// CHECK3-NEXT:    store i16 [[TMP0]], ptr [[AA_CASTED]], align 21784// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 41785// CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined, i32 [[TMP1]])1786// CHECK3-NEXT:    ret void1787//1788//1789// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined1790// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {1791// CHECK3-NEXT:  entry:1792// CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 41793// CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 41794// CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 41795// CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 41796// CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 41797// CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 41798// CHECK3-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 21799// CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP0]] to i321800// CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 11801// CHECK3-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i161802// CHECK3-NEXT:    store i16 [[CONV1]], ptr [[AA_ADDR]], align 21803// CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41804// CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 41805// CHECK3-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_cancel(ptr @[[GLOB1]], i32 [[TMP2]], i32 1)1806// CHECK3-NEXT:    [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 01807// CHECK3-NEXT:    br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]1808// CHECK3:       .cancel.exit:1809// CHECK3-NEXT:    [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(ptr @[[GLOB2:[0-9]+]], i32 [[TMP2]])1810// CHECK3-NEXT:    br label [[DOTCANCEL_CONTINUE]]1811// CHECK3:       .cancel.continue:1812// CHECK3-NEXT:    ret void1813//1814//1815// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1191816// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {1817// CHECK3-NEXT:  entry:1818// CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 41819// CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 41820// CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 41821// CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 41822// CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 41823// CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 41824// CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41825// CHECK3-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 41826// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 41827// CHECK3-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 21828// CHECK3-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 21829// CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 41830// CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.omp_outlined, i32 [[TMP1]], i32 [[TMP3]])1831// CHECK3-NEXT:    ret void1832//1833//1834// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.omp_outlined1835// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {1836// CHECK3-NEXT:  entry:1837// CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 41838// CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 41839// CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 41840// CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 41841// CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 41842// CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 41843// CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 41844// CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 41845// CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41846// CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 11847// CHECK3-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 41848// CHECK3-NEXT:    [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 21849// CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i321850// CHECK3-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 11851// CHECK3-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i161852// CHECK3-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 21853// CHECK3-NEXT:    ret void1854//1855//1856// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1441857// CHECK3-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {1858// CHECK3-NEXT:  entry:1859// CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 41860// CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 41861// CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 41862// CHECK3-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 41863// CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 41864// CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 41865// CHECK3-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 41866// CHECK3-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 41867// CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 41868// CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 41869// CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 41870// CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 41871// CHECK3-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 41872// CHECK3-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 41873// CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 41874// CHECK3-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 41875// CHECK3-NEXT:    store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 41876// CHECK3-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 41877// CHECK3-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 41878// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 41879// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 41880// CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 41881// CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 41882// CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 41883// CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 41884// CHECK3-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 41885// CHECK3-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 41886// CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 41887// CHECK3-NEXT:    store i32 [[TMP8]], ptr [[A_CASTED]], align 41888// CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 41889// CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]])1890// CHECK3-NEXT:    ret void1891//1892//1893// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.omp_outlined1894// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {1895// CHECK3-NEXT:  entry:1896// CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 41897// CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 41898// CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 41899// CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 41900// CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 41901// CHECK3-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 41902// CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 41903// CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 41904// CHECK3-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 41905// CHECK3-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 41906// CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 41907// CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 41908// CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 41909// CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 41910// CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 41911// CHECK3-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 41912// CHECK3-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 41913// CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 41914// CHECK3-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 41915// CHECK3-NEXT:    store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 41916// CHECK3-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 41917// CHECK3-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 41918// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 41919// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 41920// CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 41921// CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 41922// CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 41923// CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 41924// CHECK3-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 41925// CHECK3-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 41926// CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 41927// CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP8]], 11928// CHECK3-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 41929// CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 21930// CHECK3-NEXT:    [[TMP9:%.*]] = load float, ptr [[ARRAYIDX]], align 41931// CHECK3-NEXT:    [[CONV:%.*]] = fpext float [[TMP9]] to double1932// CHECK3-NEXT:    [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+001933// CHECK3-NEXT:    [[CONV6:%.*]] = fptrunc double [[ADD5]] to float1934// CHECK3-NEXT:    store float [[CONV6]], ptr [[ARRAYIDX]], align 41935// CHECK3-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 31936// CHECK3-NEXT:    [[TMP10:%.*]] = load float, ptr [[ARRAYIDX7]], align 41937// CHECK3-NEXT:    [[CONV8:%.*]] = fpext float [[TMP10]] to double1938// CHECK3-NEXT:    [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+001939// CHECK3-NEXT:    [[CONV10:%.*]] = fptrunc double [[ADD9]] to float1940// CHECK3-NEXT:    store float [[CONV10]], ptr [[ARRAYIDX7]], align 41941// CHECK3-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 11942// CHECK3-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX11]], i32 0, i32 21943// CHECK3-NEXT:    [[TMP11:%.*]] = load double, ptr [[ARRAYIDX12]], align 81944// CHECK3-NEXT:    [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+001945// CHECK3-NEXT:    store double [[ADD13]], ptr [[ARRAYIDX12]], align 81946// CHECK3-NEXT:    [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]]1947// CHECK3-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP12]]1948// CHECK3-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i32 31949// CHECK3-NEXT:    [[TMP13:%.*]] = load double, ptr [[ARRAYIDX15]], align 81950// CHECK3-NEXT:    [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+001951// CHECK3-NEXT:    store double [[ADD16]], ptr [[ARRAYIDX15]], align 81952// CHECK3-NEXT:    [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 01953// CHECK3-NEXT:    [[TMP14:%.*]] = load i64, ptr [[X]], align 41954// CHECK3-NEXT:    [[ADD17:%.*]] = add nsw i64 [[TMP14]], 11955// CHECK3-NEXT:    store i64 [[ADD17]], ptr [[X]], align 41956// CHECK3-NEXT:    [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 11957// CHECK3-NEXT:    [[TMP15:%.*]] = load i8, ptr [[Y]], align 41958// CHECK3-NEXT:    [[CONV18:%.*]] = sext i8 [[TMP15]] to i321959// CHECK3-NEXT:    [[ADD19:%.*]] = add nsw i32 [[CONV18]], 11960// CHECK3-NEXT:    [[CONV20:%.*]] = trunc i32 [[ADD19]] to i81961// CHECK3-NEXT:    store i8 [[CONV20]], ptr [[Y]], align 41962// CHECK3-NEXT:    ret void1963//1964//1965// CHECK3-LABEL: define {{[^@]+}}@_Z3bari1966// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {1967// CHECK3-NEXT:  entry:1968// CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 41969// CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 41970// CHECK3-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 41971// CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 41972// CHECK3-NEXT:    store i32 0, ptr [[A]], align 41973// CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 41974// CHECK3-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]])1975// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A]], align 41976// CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]1977// CHECK3-NEXT:    store i32 [[ADD]], ptr [[A]], align 41978// CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 41979// CHECK3-NEXT:    [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]])1980// CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 41981// CHECK3-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]1982// CHECK3-NEXT:    store i32 [[ADD2]], ptr [[A]], align 41983// CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 41984// CHECK3-NEXT:    [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]])1985// CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A]], align 41986// CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]1987// CHECK3-NEXT:    store i32 [[ADD4]], ptr [[A]], align 41988// CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 41989// CHECK3-NEXT:    [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]])1990// CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[A]], align 41991// CHECK3-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]1992// CHECK3-NEXT:    store i32 [[ADD6]], ptr [[A]], align 41993// CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A]], align 41994// CHECK3-NEXT:    ret i32 [[TMP8]]1995//1996//1997// CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei1998// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {1999// CHECK3-NEXT:  entry:2000// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 42001// CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 42002// CHECK3-NEXT:    [[B:%.*]] = alloca i32, align 42003// CHECK3-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 42004// CHECK3-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 42005// CHECK3-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 42006// CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 42007// CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 42008// CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 42009// CHECK3-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 42010// CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 82011// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 42012// CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 42013// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42014// CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 42015// CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 12016// CHECK3-NEXT:    store i32 [[ADD]], ptr [[B]], align 42017// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 42018// CHECK3-NEXT:    [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()2019// CHECK3-NEXT:    store ptr [[TMP2]], ptr [[SAVED_STACK]], align 42020// CHECK3-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]2021// CHECK3-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 22022// CHECK3-NEXT:    store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 42023// CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B]], align 42024// CHECK3-NEXT:    store i32 [[TMP4]], ptr [[B_CASTED]], align 42025// CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 42026// CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 42027// CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 602028// CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]2029// CHECK3:       omp_if.then:2030// CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 02031// CHECK3-NEXT:    [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]]2032// CHECK3-NEXT:    [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 22033// CHECK3-NEXT:    [[TMP9:%.*]] = sext i32 [[TMP8]] to i642034// CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.5, i32 40, i1 false)2035// CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 02036// CHECK3-NEXT:    store ptr [[THIS1]], ptr [[TMP10]], align 42037// CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 02038// CHECK3-NEXT:    store ptr [[A]], ptr [[TMP11]], align 42039// CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 02040// CHECK3-NEXT:    store ptr null, ptr [[TMP12]], align 42041// CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 12042// CHECK3-NEXT:    store i32 [[TMP5]], ptr [[TMP13]], align 42043// CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 12044// CHECK3-NEXT:    store i32 [[TMP5]], ptr [[TMP14]], align 42045// CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 12046// CHECK3-NEXT:    store ptr null, ptr [[TMP15]], align 42047// CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 22048// CHECK3-NEXT:    store i32 2, ptr [[TMP16]], align 42049// CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 22050// CHECK3-NEXT:    store i32 2, ptr [[TMP17]], align 42051// CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 22052// CHECK3-NEXT:    store ptr null, ptr [[TMP18]], align 42053// CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 32054// CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP19]], align 42055// CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 32056// CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP20]], align 42057// CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 32058// CHECK3-NEXT:    store ptr null, ptr [[TMP21]], align 42059// CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 42060// CHECK3-NEXT:    store ptr [[VLA]], ptr [[TMP22]], align 42061// CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 42062// CHECK3-NEXT:    store ptr [[VLA]], ptr [[TMP23]], align 42063// CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 42064// CHECK3-NEXT:    store i64 [[TMP9]], ptr [[TMP24]], align 42065// CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 42066// CHECK3-NEXT:    store ptr null, ptr [[TMP25]], align 42067// CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 02068// CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 02069// CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 02070// CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 02071// CHECK3-NEXT:    store i32 3, ptr [[TMP29]], align 42072// CHECK3-NEXT:    [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12073// CHECK3-NEXT:    store i32 5, ptr [[TMP30]], align 42074// CHECK3-NEXT:    [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 22075// CHECK3-NEXT:    store ptr [[TMP26]], ptr [[TMP31]], align 42076// CHECK3-NEXT:    [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 32077// CHECK3-NEXT:    store ptr [[TMP27]], ptr [[TMP32]], align 42078// CHECK3-NEXT:    [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 42079// CHECK3-NEXT:    store ptr [[TMP28]], ptr [[TMP33]], align 42080// CHECK3-NEXT:    [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 52081// CHECK3-NEXT:    store ptr @.offload_maptypes.6, ptr [[TMP34]], align 42082// CHECK3-NEXT:    [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 62083// CHECK3-NEXT:    store ptr null, ptr [[TMP35]], align 42084// CHECK3-NEXT:    [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 72085// CHECK3-NEXT:    store ptr null, ptr [[TMP36]], align 42086// CHECK3-NEXT:    [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 82087// CHECK3-NEXT:    store i64 0, ptr [[TMP37]], align 82088// CHECK3-NEXT:    [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 92089// CHECK3-NEXT:    store i64 0, ptr [[TMP38]], align 82090// CHECK3-NEXT:    [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 102091// CHECK3-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP39]], align 42092// CHECK3-NEXT:    [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 112093// CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP40]], align 42094// CHECK3-NEXT:    [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 122095// CHECK3-NEXT:    store i32 0, ptr [[TMP41]], align 42096// CHECK3-NEXT:    [[TMP42:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, ptr [[KERNEL_ARGS]])2097// CHECK3-NEXT:    [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 02098// CHECK3-NEXT:    br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]2099// CHECK3:       omp_offload.failed:2100// CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3]]2101// CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]2102// CHECK3:       omp_offload.cont:2103// CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]2104// CHECK3:       omp_if.else:2105// CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3]]2106// CHECK3-NEXT:    br label [[OMP_IF_END]]2107// CHECK3:       omp_if.end:2108// CHECK3-NEXT:    [[TMP44:%.*]] = mul nsw i32 1, [[TMP1]]2109// CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP44]]2110// CHECK3-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 12111// CHECK3-NEXT:    [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 22112// CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP45]] to i322113// CHECK3-NEXT:    [[TMP46:%.*]] = load i32, ptr [[B]], align 42114// CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]]2115// CHECK3-NEXT:    [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 42116// CHECK3-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP47]])2117// CHECK3-NEXT:    ret i32 [[ADD3]]2118//2119//2120// CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici2121// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {2122// CHECK3-NEXT:  entry:2123// CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 42124// CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 42125// CHECK3-NEXT:    [[AA:%.*]] = alloca i16, align 22126// CHECK3-NEXT:    [[AAA:%.*]] = alloca i8, align 12127// CHECK3-NEXT:    [[B:%.*]] = alloca [10 x i32], align 42128// CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 42129// CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 42130// CHECK3-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 42131// CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 42132// CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 42133// CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 42134// CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 82135// CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 42136// CHECK3-NEXT:    store i32 0, ptr [[A]], align 42137// CHECK3-NEXT:    store i16 0, ptr [[AA]], align 22138// CHECK3-NEXT:    store i8 0, ptr [[AAA]], align 12139// CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A]], align 42140// CHECK3-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 42141// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 42142// CHECK3-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA]], align 22143// CHECK3-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 22144// CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 42145// CHECK3-NEXT:    [[TMP4:%.*]] = load i8, ptr [[AAA]], align 12146// CHECK3-NEXT:    store i8 [[TMP4]], ptr [[AAA_CASTED]], align 12147// CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[AAA_CASTED]], align 42148// CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 42149// CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 502150// CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]2151// CHECK3:       omp_if.then:2152// CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 02153// CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP7]], align 42154// CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 02155// CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP8]], align 42156// CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 02157// CHECK3-NEXT:    store ptr null, ptr [[TMP9]], align 42158// CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 12159// CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP10]], align 42160// CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 12161// CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP11]], align 42162// CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 12163// CHECK3-NEXT:    store ptr null, ptr [[TMP12]], align 42164// CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 22165// CHECK3-NEXT:    store i32 [[TMP5]], ptr [[TMP13]], align 42166// CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 22167// CHECK3-NEXT:    store i32 [[TMP5]], ptr [[TMP14]], align 42168// CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 22169// CHECK3-NEXT:    store ptr null, ptr [[TMP15]], align 42170// CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 32171// CHECK3-NEXT:    store ptr [[B]], ptr [[TMP16]], align 42172// CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 32173// CHECK3-NEXT:    store ptr [[B]], ptr [[TMP17]], align 42174// CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 32175// CHECK3-NEXT:    store ptr null, ptr [[TMP18]], align 42176// CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 02177// CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 02178// CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 02179// CHECK3-NEXT:    store i32 3, ptr [[TMP21]], align 42180// CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12181// CHECK3-NEXT:    store i32 4, ptr [[TMP22]], align 42182// CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 22183// CHECK3-NEXT:    store ptr [[TMP19]], ptr [[TMP23]], align 42184// CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 32185// CHECK3-NEXT:    store ptr [[TMP20]], ptr [[TMP24]], align 42186// CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 42187// CHECK3-NEXT:    store ptr @.offload_sizes.7, ptr [[TMP25]], align 42188// CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 52189// CHECK3-NEXT:    store ptr @.offload_maptypes.8, ptr [[TMP26]], align 42190// CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 62191// CHECK3-NEXT:    store ptr null, ptr [[TMP27]], align 42192// CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 72193// CHECK3-NEXT:    store ptr null, ptr [[TMP28]], align 42194// CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 82195// CHECK3-NEXT:    store i64 0, ptr [[TMP29]], align 82196// CHECK3-NEXT:    [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 92197// CHECK3-NEXT:    store i64 0, ptr [[TMP30]], align 82198// CHECK3-NEXT:    [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 102199// CHECK3-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP31]], align 42200// CHECK3-NEXT:    [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 112201// CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP32]], align 42202// CHECK3-NEXT:    [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 122203// CHECK3-NEXT:    store i32 0, ptr [[TMP33]], align 42204// CHECK3-NEXT:    [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.region_id, ptr [[KERNEL_ARGS]])2205// CHECK3-NEXT:    [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 02206// CHECK3-NEXT:    br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]2207// CHECK3:       omp_offload.failed:2208// CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR3]]2209// CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]2210// CHECK3:       omp_offload.cont:2211// CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]2212// CHECK3:       omp_if.else:2213// CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR3]]2214// CHECK3-NEXT:    br label [[OMP_IF_END]]2215// CHECK3:       omp_if.end:2216// CHECK3-NEXT:    [[TMP36:%.*]] = load i32, ptr [[A]], align 42217// CHECK3-NEXT:    ret i32 [[TMP36]]2218//2219//2220// CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i2221// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {2222// CHECK3-NEXT:  entry:2223// CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 42224// CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 42225// CHECK3-NEXT:    [[AA:%.*]] = alloca i16, align 22226// CHECK3-NEXT:    [[B:%.*]] = alloca [10 x i32], align 42227// CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 42228// CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 42229// CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 42230// CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 42231// CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 42232// CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 82233// CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 42234// CHECK3-NEXT:    store i32 0, ptr [[A]], align 42235// CHECK3-NEXT:    store i16 0, ptr [[AA]], align 22236// CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A]], align 42237// CHECK3-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 42238// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 42239// CHECK3-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA]], align 22240// CHECK3-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 22241// CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 42242// CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 42243// CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 402244// CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]2245// CHECK3:       omp_if.then:2246// CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 02247// CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP5]], align 42248// CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 02249// CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP6]], align 42250// CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 02251// CHECK3-NEXT:    store ptr null, ptr [[TMP7]], align 42252// CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 12253// CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP8]], align 42254// CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 12255// CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP9]], align 42256// CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 12257// CHECK3-NEXT:    store ptr null, ptr [[TMP10]], align 42258// CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 22259// CHECK3-NEXT:    store ptr [[B]], ptr [[TMP11]], align 42260// CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 22261// CHECK3-NEXT:    store ptr [[B]], ptr [[TMP12]], align 42262// CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 22263// CHECK3-NEXT:    store ptr null, ptr [[TMP13]], align 42264// CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 02265// CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 02266// CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 02267// CHECK3-NEXT:    store i32 3, ptr [[TMP16]], align 42268// CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12269// CHECK3-NEXT:    store i32 3, ptr [[TMP17]], align 42270// CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 22271// CHECK3-NEXT:    store ptr [[TMP14]], ptr [[TMP18]], align 42272// CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 32273// CHECK3-NEXT:    store ptr [[TMP15]], ptr [[TMP19]], align 42274// CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 42275// CHECK3-NEXT:    store ptr @.offload_sizes.9, ptr [[TMP20]], align 42276// CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 52277// CHECK3-NEXT:    store ptr @.offload_maptypes.10, ptr [[TMP21]], align 42278// CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 62279// CHECK3-NEXT:    store ptr null, ptr [[TMP22]], align 42280// CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 72281// CHECK3-NEXT:    store ptr null, ptr [[TMP23]], align 42282// CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 82283// CHECK3-NEXT:    store i64 0, ptr [[TMP24]], align 82284// CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 92285// CHECK3-NEXT:    store i64 0, ptr [[TMP25]], align 82286// CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 102287// CHECK3-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP26]], align 42288// CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 112289// CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP27]], align 42290// CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 122291// CHECK3-NEXT:    store i32 0, ptr [[TMP28]], align 42292// CHECK3-NEXT:    [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.region_id, ptr [[KERNEL_ARGS]])2293// CHECK3-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 02294// CHECK3-NEXT:    br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]2295// CHECK3:       omp_offload.failed:2296// CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]]2297// CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]2298// CHECK3:       omp_offload.cont:2299// CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]2300// CHECK3:       omp_if.else:2301// CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]]2302// CHECK3-NEXT:    br label [[OMP_IF_END]]2303// CHECK3:       omp_if.end:2304// CHECK3-NEXT:    [[TMP31:%.*]] = load i32, ptr [[A]], align 42305// CHECK3-NEXT:    ret i32 [[TMP31]]2306//2307//2308// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l2162309// CHECK3-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {2310// CHECK3-NEXT:  entry:2311// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 42312// CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 42313// CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 42314// CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 42315// CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 42316// CHECK3-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 42317// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 42318// CHECK3-NEXT:    store i32 [[B]], ptr [[B_ADDR]], align 42319// CHECK3-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 42320// CHECK3-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 42321// CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 42322// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42323// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 42324// CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 42325// CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 42326// CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 42327// CHECK3-NEXT:    store i32 [[TMP4]], ptr [[B_CASTED]], align 42328// CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 42329// CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]])2330// CHECK3-NEXT:    ret void2331//2332//2333// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined2334// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {2335// CHECK3-NEXT:  entry:2336// CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 42337// CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 42338// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 42339// CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 42340// CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 42341// CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 42342// CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 42343// CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 42344// CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 42345// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 42346// CHECK3-NEXT:    store i32 [[B]], ptr [[B_ADDR]], align 42347// CHECK3-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 42348// CHECK3-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 42349// CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 42350// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42351// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 42352// CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 42353// CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 42354// CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 42355// CHECK3-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP4]] to double2356// CHECK3-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+002357// CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 02358// CHECK3-NEXT:    store double [[ADD]], ptr [[A]], align 42359// CHECK3-NEXT:    [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 02360// CHECK3-NEXT:    [[TMP5:%.*]] = load double, ptr [[A3]], align 42361// CHECK3-NEXT:    [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+002362// CHECK3-NEXT:    store double [[INC]], ptr [[A3]], align 42363// CHECK3-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i162364// CHECK3-NEXT:    [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]]2365// CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP6]]2366// CHECK3-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 12367// CHECK3-NEXT:    store i16 [[CONV4]], ptr [[ARRAYIDX5]], align 22368// CHECK3-NEXT:    ret void2369//2370//2371// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l1982372// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {2373// CHECK3-NEXT:  entry:2374// CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 42375// CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 42376// CHECK3-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 42377// CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 42378// CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 42379// CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 42380// CHECK3-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 42381// CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 42382// CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 42383// CHECK3-NEXT:    store i32 [[AAA]], ptr [[AAA_ADDR]], align 42384// CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 42385// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 42386// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 42387// CHECK3-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 42388// CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 42389// CHECK3-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 22390// CHECK3-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 22391// CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 42392// CHECK3-NEXT:    [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 12393// CHECK3-NEXT:    store i8 [[TMP5]], ptr [[AAA_CASTED]], align 12394// CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[AAA_CASTED]], align 42395// CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], ptr [[TMP0]])2396// CHECK3-NEXT:    ret void2397//2398//2399// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.omp_outlined2400// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {2401// CHECK3-NEXT:  entry:2402// CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 42403// CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 42404// CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 42405// CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 42406// CHECK3-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 42407// CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 42408// CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 42409// CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 42410// CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 42411// CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 42412// CHECK3-NEXT:    store i32 [[AAA]], ptr [[AAA_ADDR]], align 42413// CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 42414// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 42415// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 42416// CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 12417// CHECK3-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 42418// CHECK3-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 22419// CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i322420// CHECK3-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 12421// CHECK3-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i162422// CHECK3-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 22423// CHECK3-NEXT:    [[TMP3:%.*]] = load i8, ptr [[AAA_ADDR]], align 12424// CHECK3-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP3]] to i322425// CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 12426// CHECK3-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i82427// CHECK3-NEXT:    store i8 [[CONV5]], ptr [[AAA_ADDR]], align 12428// CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 22429// CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX]], align 42430// CHECK3-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP4]], 12431// CHECK3-NEXT:    store i32 [[ADD6]], ptr [[ARRAYIDX]], align 42432// CHECK3-NEXT:    ret void2433//2434//2435// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l1812436// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {2437// CHECK3-NEXT:  entry:2438// CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 42439// CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 42440// CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 42441// CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 42442// CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 42443// CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 42444// CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 42445// CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 42446// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 42447// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 42448// CHECK3-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 42449// CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 42450// CHECK3-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 22451// CHECK3-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 22452// CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 42453// CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]])2454// CHECK3-NEXT:    ret void2455//2456//2457// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.omp_outlined2458// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {2459// CHECK3-NEXT:  entry:2460// CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 42461// CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 42462// CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 42463// CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 42464// CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 42465// CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 42466// CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 42467// CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 42468// CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 42469// CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 42470// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 42471// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 42472// CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 12473// CHECK3-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 42474// CHECK3-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 22475// CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i322476// CHECK3-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 12477// CHECK3-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i162478// CHECK3-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 22479// CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 22480// CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 42481// CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 12482// CHECK3-NEXT:    store i32 [[ADD3]], ptr [[ARRAYIDX]], align 42483// CHECK3-NEXT:    ret void2484//2485//2486// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1002487// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {2488// CHECK9-NEXT:  entry:2489// CHECK9-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 82490// CHECK9-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 82491// CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.omp_outlined)2492// CHECK9-NEXT:    ret void2493//2494//2495// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.omp_outlined2496// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {2497// CHECK9-NEXT:  entry:2498// CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 82499// CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 82500// CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 82501// CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 82502// CHECK9-NEXT:    ret void2503//2504//2505// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1102506// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {2507// CHECK9-NEXT:  entry:2508// CHECK9-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 82509// CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 82510// CHECK9-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 82511// CHECK9-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 82512// CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 82513// CHECK9-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 22514// CHECK9-NEXT:    store i16 [[TMP0]], ptr [[AA_CASTED]], align 22515// CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 82516// CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined, i64 [[TMP1]])2517// CHECK9-NEXT:    ret void2518//2519//2520// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined2521// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {2522// CHECK9-NEXT:  entry:2523// CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 82524// CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 82525// CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 82526// CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 82527// CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 82528// CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 82529// CHECK9-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 22530// CHECK9-NEXT:    [[CONV:%.*]] = sext i16 [[TMP0]] to i322531// CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 12532// CHECK9-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i162533// CHECK9-NEXT:    store i16 [[CONV1]], ptr [[AA_ADDR]], align 22534// CHECK9-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 82535// CHECK9-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 42536// CHECK9-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_cancel(ptr @[[GLOB1]], i32 [[TMP2]], i32 1)2537// CHECK9-NEXT:    [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 02538// CHECK9-NEXT:    br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]2539// CHECK9:       .cancel.exit:2540// CHECK9-NEXT:    [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(ptr @[[GLOB2:[0-9]+]], i32 [[TMP2]])2541// CHECK9-NEXT:    br label [[DOTCANCEL_CONTINUE]]2542// CHECK9:       .cancel.continue:2543// CHECK9-NEXT:    ret void2544//2545//2546// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1192547// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {2548// CHECK9-NEXT:  entry:2549// CHECK9-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 82550// CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 82551// CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 82552// CHECK9-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 82553// CHECK9-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 82554// CHECK9-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 82555// CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 82556// CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 82557// CHECK9-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 42558// CHECK9-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 42559// CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 82560// CHECK9-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 22561// CHECK9-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 22562// CHECK9-NEXT:    [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 82563// CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.omp_outlined, i64 [[TMP1]], i64 [[TMP3]])2564// CHECK9-NEXT:    ret void2565//2566//2567// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.omp_outlined2568// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {2569// CHECK9-NEXT:  entry:2570// CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 82571// CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 82572// CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 82573// CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 82574// CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 82575// CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 82576// CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 82577// CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 82578// CHECK9-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 42579// CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 12580// CHECK9-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 42581// CHECK9-NEXT:    [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 22582// CHECK9-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i322583// CHECK9-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 12584// CHECK9-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i162585// CHECK9-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 22586// CHECK9-NEXT:    ret void2587//2588//2589// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1442590// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {2591// CHECK9-NEXT:  entry:2592// CHECK9-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 82593// CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 82594// CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 82595// CHECK9-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 82596// CHECK9-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 82597// CHECK9-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 82598// CHECK9-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 82599// CHECK9-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 82600// CHECK9-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 82601// CHECK9-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 82602// CHECK9-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 82603// CHECK9-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 82604// CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 82605// CHECK9-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 82606// CHECK9-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 82607// CHECK9-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 82608// CHECK9-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 82609// CHECK9-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 82610// CHECK9-NEXT:    store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 82611// CHECK9-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 82612// CHECK9-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 82613// CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 82614// CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 82615// CHECK9-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 82616// CHECK9-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 82617// CHECK9-NEXT:    [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 82618// CHECK9-NEXT:    [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 82619// CHECK9-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 82620// CHECK9-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 82621// CHECK9-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 42622// CHECK9-NEXT:    store i32 [[TMP8]], ptr [[A_CASTED]], align 42623// CHECK9-NEXT:    [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 82624// CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]])2625// CHECK9-NEXT:    ret void2626//2627//2628// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.omp_outlined2629// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {2630// CHECK9-NEXT:  entry:2631// CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 82632// CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 82633// CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 82634// CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 82635// CHECK9-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 82636// CHECK9-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 82637// CHECK9-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 82638// CHECK9-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 82639// CHECK9-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 82640// CHECK9-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 82641// CHECK9-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 82642// CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 82643// CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 82644// CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 82645// CHECK9-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 82646// CHECK9-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 82647// CHECK9-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 82648// CHECK9-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 82649// CHECK9-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 82650// CHECK9-NEXT:    store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 82651// CHECK9-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 82652// CHECK9-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 82653// CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 82654// CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 82655// CHECK9-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 82656// CHECK9-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 82657// CHECK9-NEXT:    [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 82658// CHECK9-NEXT:    [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 82659// CHECK9-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 82660// CHECK9-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 82661// CHECK9-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 42662// CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP8]], 12663// CHECK9-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 42664// CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 22665// CHECK9-NEXT:    [[TMP9:%.*]] = load float, ptr [[ARRAYIDX]], align 42666// CHECK9-NEXT:    [[CONV:%.*]] = fpext float [[TMP9]] to double2667// CHECK9-NEXT:    [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+002668// CHECK9-NEXT:    [[CONV6:%.*]] = fptrunc double [[ADD5]] to float2669// CHECK9-NEXT:    store float [[CONV6]], ptr [[ARRAYIDX]], align 42670// CHECK9-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 32671// CHECK9-NEXT:    [[TMP10:%.*]] = load float, ptr [[ARRAYIDX7]], align 42672// CHECK9-NEXT:    [[CONV8:%.*]] = fpext float [[TMP10]] to double2673// CHECK9-NEXT:    [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+002674// CHECK9-NEXT:    [[CONV10:%.*]] = fptrunc double [[ADD9]] to float2675// CHECK9-NEXT:    store float [[CONV10]], ptr [[ARRAYIDX7]], align 42676// CHECK9-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 12677// CHECK9-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX11]], i64 0, i64 22678// CHECK9-NEXT:    [[TMP11:%.*]] = load double, ptr [[ARRAYIDX12]], align 82679// CHECK9-NEXT:    [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+002680// CHECK9-NEXT:    store double [[ADD13]], ptr [[ARRAYIDX12]], align 82681// CHECK9-NEXT:    [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]]2682// CHECK9-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP12]]2683// CHECK9-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i64 32684// CHECK9-NEXT:    [[TMP13:%.*]] = load double, ptr [[ARRAYIDX15]], align 82685// CHECK9-NEXT:    [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+002686// CHECK9-NEXT:    store double [[ADD16]], ptr [[ARRAYIDX15]], align 82687// CHECK9-NEXT:    [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 02688// CHECK9-NEXT:    [[TMP14:%.*]] = load i64, ptr [[X]], align 82689// CHECK9-NEXT:    [[ADD17:%.*]] = add nsw i64 [[TMP14]], 12690// CHECK9-NEXT:    store i64 [[ADD17]], ptr [[X]], align 82691// CHECK9-NEXT:    [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 12692// CHECK9-NEXT:    [[TMP15:%.*]] = load i8, ptr [[Y]], align 82693// CHECK9-NEXT:    [[CONV18:%.*]] = sext i8 [[TMP15]] to i322694// CHECK9-NEXT:    [[ADD19:%.*]] = add nsw i32 [[CONV18]], 12695// CHECK9-NEXT:    [[CONV20:%.*]] = trunc i32 [[ADD19]] to i82696// CHECK9-NEXT:    store i8 [[CONV20]], ptr [[Y]], align 82697// CHECK9-NEXT:    ret void2698//2699//2700// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l1982701// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {2702// CHECK9-NEXT:  entry:2703// CHECK9-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 82704// CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 82705// CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 82706// CHECK9-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 82707// CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 82708// CHECK9-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 82709// CHECK9-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 82710// CHECK9-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 82711// CHECK9-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 82712// CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 82713// CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 82714// CHECK9-NEXT:    store i64 [[AAA]], ptr [[AAA_ADDR]], align 82715// CHECK9-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 82716// CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 82717// CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 42718// CHECK9-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 42719// CHECK9-NEXT:    [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 82720// CHECK9-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 22721// CHECK9-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 22722// CHECK9-NEXT:    [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 82723// CHECK9-NEXT:    [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 12724// CHECK9-NEXT:    store i8 [[TMP5]], ptr [[AAA_CASTED]], align 12725// CHECK9-NEXT:    [[TMP6:%.*]] = load i64, ptr [[AAA_CASTED]], align 82726// CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], ptr [[TMP0]])2727// CHECK9-NEXT:    ret void2728//2729//2730// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.omp_outlined2731// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {2732// CHECK9-NEXT:  entry:2733// CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 82734// CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 82735// CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 82736// CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 82737// CHECK9-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 82738// CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 82739// CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 82740// CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 82741// CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 82742// CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 82743// CHECK9-NEXT:    store i64 [[AAA]], ptr [[AAA_ADDR]], align 82744// CHECK9-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 82745// CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 82746// CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 42747// CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 12748// CHECK9-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 42749// CHECK9-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 22750// CHECK9-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i322751// CHECK9-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 12752// CHECK9-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i162753// CHECK9-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 22754// CHECK9-NEXT:    [[TMP3:%.*]] = load i8, ptr [[AAA_ADDR]], align 12755// CHECK9-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP3]] to i322756// CHECK9-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 12757// CHECK9-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i82758// CHECK9-NEXT:    store i8 [[CONV5]], ptr [[AAA_ADDR]], align 12759// CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 22760// CHECK9-NEXT:    [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX]], align 42761// CHECK9-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP4]], 12762// CHECK9-NEXT:    store i32 [[ADD6]], ptr [[ARRAYIDX]], align 42763// CHECK9-NEXT:    ret void2764//2765//2766// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l2162767// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {2768// CHECK9-NEXT:  entry:2769// CHECK9-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 82770// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82771// CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 82772// CHECK9-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 82773// CHECK9-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 82774// CHECK9-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 82775// CHECK9-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 82776// CHECK9-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 82777// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82778// CHECK9-NEXT:    store i64 [[B]], ptr [[B_ADDR]], align 82779// CHECK9-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 82780// CHECK9-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 82781// CHECK9-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 82782// CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82783// CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 82784// CHECK9-NEXT:    [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 82785// CHECK9-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 82786// CHECK9-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 42787// CHECK9-NEXT:    store i32 [[TMP4]], ptr [[B_CASTED]], align 42788// CHECK9-NEXT:    [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 82789// CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]])2790// CHECK9-NEXT:    ret void2791//2792//2793// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined2794// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {2795// CHECK9-NEXT:  entry:2796// CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 82797// CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 82798// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82799// CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 82800// CHECK9-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 82801// CHECK9-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 82802// CHECK9-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 82803// CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 82804// CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 82805// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82806// CHECK9-NEXT:    store i64 [[B]], ptr [[B_ADDR]], align 82807// CHECK9-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 82808// CHECK9-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 82809// CHECK9-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 82810// CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82811// CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 82812// CHECK9-NEXT:    [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 82813// CHECK9-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 82814// CHECK9-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 42815// CHECK9-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP4]] to double2816// CHECK9-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+002817// CHECK9-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 02818// CHECK9-NEXT:    store double [[ADD]], ptr [[A]], align 82819// CHECK9-NEXT:    [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 02820// CHECK9-NEXT:    [[TMP5:%.*]] = load double, ptr [[A3]], align 82821// CHECK9-NEXT:    [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+002822// CHECK9-NEXT:    store double [[INC]], ptr [[A3]], align 82823// CHECK9-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i162824// CHECK9-NEXT:    [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]]2825// CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP6]]2826// CHECK9-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 12827// CHECK9-NEXT:    store i16 [[CONV4]], ptr [[ARRAYIDX5]], align 22828// CHECK9-NEXT:    ret void2829//2830//2831// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l1812832// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {2833// CHECK9-NEXT:  entry:2834// CHECK9-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 82835// CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 82836// CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 82837// CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 82838// CHECK9-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 82839// CHECK9-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 82840// CHECK9-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 82841// CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 82842// CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 82843// CHECK9-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 82844// CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 82845// CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 42846// CHECK9-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 42847// CHECK9-NEXT:    [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 82848// CHECK9-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 22849// CHECK9-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 22850// CHECK9-NEXT:    [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 82851// CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]])2852// CHECK9-NEXT:    ret void2853//2854//2855// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.omp_outlined2856// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {2857// CHECK9-NEXT:  entry:2858// CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 82859// CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 82860// CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 82861// CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 82862// CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 82863// CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 82864// CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 82865// CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 82866// CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 82867// CHECK9-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 82868// CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 82869// CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 42870// CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 12871// CHECK9-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 42872// CHECK9-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 22873// CHECK9-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i322874// CHECK9-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 12875// CHECK9-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i162876// CHECK9-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 22877// CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 22878// CHECK9-NEXT:    [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 42879// CHECK9-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 12880// CHECK9-NEXT:    store i32 [[ADD3]], ptr [[ARRAYIDX]], align 42881// CHECK9-NEXT:    ret void2882//2883//2884// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1002885// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {2886// CHECK11-NEXT:  entry:2887// CHECK11-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 42888// CHECK11-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 42889// CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.omp_outlined)2890// CHECK11-NEXT:    ret void2891//2892//2893// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.omp_outlined2894// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {2895// CHECK11-NEXT:  entry:2896// CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 42897// CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 42898// CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 42899// CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 42900// CHECK11-NEXT:    ret void2901//2902//2903// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1102904// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {2905// CHECK11-NEXT:  entry:2906// CHECK11-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 42907// CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 42908// CHECK11-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 42909// CHECK11-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 42910// CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 42911// CHECK11-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 22912// CHECK11-NEXT:    store i16 [[TMP0]], ptr [[AA_CASTED]], align 22913// CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 42914// CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined, i32 [[TMP1]])2915// CHECK11-NEXT:    ret void2916//2917//2918// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined2919// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {2920// CHECK11-NEXT:  entry:2921// CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 42922// CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 42923// CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 42924// CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 42925// CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 42926// CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 42927// CHECK11-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 22928// CHECK11-NEXT:    [[CONV:%.*]] = sext i16 [[TMP0]] to i322929// CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 12930// CHECK11-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i162931// CHECK11-NEXT:    store i16 [[CONV1]], ptr [[AA_ADDR]], align 22932// CHECK11-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 42933// CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 42934// CHECK11-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_cancel(ptr @[[GLOB1]], i32 [[TMP2]], i32 1)2935// CHECK11-NEXT:    [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 02936// CHECK11-NEXT:    br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]2937// CHECK11:       .cancel.exit:2938// CHECK11-NEXT:    [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(ptr @[[GLOB2:[0-9]+]], i32 [[TMP2]])2939// CHECK11-NEXT:    br label [[DOTCANCEL_CONTINUE]]2940// CHECK11:       .cancel.continue:2941// CHECK11-NEXT:    ret void2942//2943//2944// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1192945// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {2946// CHECK11-NEXT:  entry:2947// CHECK11-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 42948// CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 42949// CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 42950// CHECK11-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 42951// CHECK11-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 42952// CHECK11-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 42953// CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 42954// CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 42955// CHECK11-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 42956// CHECK11-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 42957// CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 42958// CHECK11-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 22959// CHECK11-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 22960// CHECK11-NEXT:    [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 42961// CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.omp_outlined, i32 [[TMP1]], i32 [[TMP3]])2962// CHECK11-NEXT:    ret void2963//2964//2965// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.omp_outlined2966// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {2967// CHECK11-NEXT:  entry:2968// CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 42969// CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 42970// CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 42971// CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 42972// CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 42973// CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 42974// CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 42975// CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 42976// CHECK11-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 42977// CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 12978// CHECK11-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 42979// CHECK11-NEXT:    [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 22980// CHECK11-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i322981// CHECK11-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 12982// CHECK11-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i162983// CHECK11-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 22984// CHECK11-NEXT:    ret void2985//2986//2987// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1442988// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {2989// CHECK11-NEXT:  entry:2990// CHECK11-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 42991// CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 42992// CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 42993// CHECK11-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 42994// CHECK11-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 42995// CHECK11-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 42996// CHECK11-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 42997// CHECK11-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 42998// CHECK11-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 42999// CHECK11-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 43000// CHECK11-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 43001// CHECK11-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 43002// CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 43003// CHECK11-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 43004// CHECK11-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 43005// CHECK11-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 43006// CHECK11-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 43007// CHECK11-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 43008// CHECK11-NEXT:    store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 43009// CHECK11-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 43010// CHECK11-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 43011// CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 43012// CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 43013// CHECK11-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 43014// CHECK11-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 43015// CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 43016// CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 43017// CHECK11-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 43018// CHECK11-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 43019// CHECK11-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 43020// CHECK11-NEXT:    store i32 [[TMP8]], ptr [[A_CASTED]], align 43021// CHECK11-NEXT:    [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 43022// CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]])3023// CHECK11-NEXT:    ret void3024//3025//3026// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.omp_outlined3027// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {3028// CHECK11-NEXT:  entry:3029// CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 43030// CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 43031// CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 43032// CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 43033// CHECK11-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 43034// CHECK11-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 43035// CHECK11-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 43036// CHECK11-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 43037// CHECK11-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 43038// CHECK11-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 43039// CHECK11-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 43040// CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 43041// CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 43042// CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 43043// CHECK11-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 43044// CHECK11-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 43045// CHECK11-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 43046// CHECK11-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 43047// CHECK11-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 43048// CHECK11-NEXT:    store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 43049// CHECK11-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 43050// CHECK11-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 43051// CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 43052// CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 43053// CHECK11-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 43054// CHECK11-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 43055// CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 43056// CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 43057// CHECK11-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 43058// CHECK11-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 43059// CHECK11-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 43060// CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP8]], 13061// CHECK11-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 43062// CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 23063// CHECK11-NEXT:    [[TMP9:%.*]] = load float, ptr [[ARRAYIDX]], align 43064// CHECK11-NEXT:    [[CONV:%.*]] = fpext float [[TMP9]] to double3065// CHECK11-NEXT:    [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+003066// CHECK11-NEXT:    [[CONV6:%.*]] = fptrunc double [[ADD5]] to float3067// CHECK11-NEXT:    store float [[CONV6]], ptr [[ARRAYIDX]], align 43068// CHECK11-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 33069// CHECK11-NEXT:    [[TMP10:%.*]] = load float, ptr [[ARRAYIDX7]], align 43070// CHECK11-NEXT:    [[CONV8:%.*]] = fpext float [[TMP10]] to double3071// CHECK11-NEXT:    [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+003072// CHECK11-NEXT:    [[CONV10:%.*]] = fptrunc double [[ADD9]] to float3073// CHECK11-NEXT:    store float [[CONV10]], ptr [[ARRAYIDX7]], align 43074// CHECK11-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 13075// CHECK11-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX11]], i32 0, i32 23076// CHECK11-NEXT:    [[TMP11:%.*]] = load double, ptr [[ARRAYIDX12]], align 83077// CHECK11-NEXT:    [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+003078// CHECK11-NEXT:    store double [[ADD13]], ptr [[ARRAYIDX12]], align 83079// CHECK11-NEXT:    [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]]3080// CHECK11-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP12]]3081// CHECK11-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i32 33082// CHECK11-NEXT:    [[TMP13:%.*]] = load double, ptr [[ARRAYIDX15]], align 83083// CHECK11-NEXT:    [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+003084// CHECK11-NEXT:    store double [[ADD16]], ptr [[ARRAYIDX15]], align 83085// CHECK11-NEXT:    [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 03086// CHECK11-NEXT:    [[TMP14:%.*]] = load i64, ptr [[X]], align 43087// CHECK11-NEXT:    [[ADD17:%.*]] = add nsw i64 [[TMP14]], 13088// CHECK11-NEXT:    store i64 [[ADD17]], ptr [[X]], align 43089// CHECK11-NEXT:    [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 13090// CHECK11-NEXT:    [[TMP15:%.*]] = load i8, ptr [[Y]], align 43091// CHECK11-NEXT:    [[CONV18:%.*]] = sext i8 [[TMP15]] to i323092// CHECK11-NEXT:    [[ADD19:%.*]] = add nsw i32 [[CONV18]], 13093// CHECK11-NEXT:    [[CONV20:%.*]] = trunc i32 [[ADD19]] to i83094// CHECK11-NEXT:    store i8 [[CONV20]], ptr [[Y]], align 43095// CHECK11-NEXT:    ret void3096//3097//3098// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l1983099// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {3100// CHECK11-NEXT:  entry:3101// CHECK11-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 43102// CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 43103// CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 43104// CHECK11-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 43105// CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 43106// CHECK11-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 43107// CHECK11-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 43108// CHECK11-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 43109// CHECK11-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 43110// CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 43111// CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 43112// CHECK11-NEXT:    store i32 [[AAA]], ptr [[AAA_ADDR]], align 43113// CHECK11-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 43114// CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 43115// CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 43116// CHECK11-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 43117// CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 43118// CHECK11-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 23119// CHECK11-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 23120// CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 43121// CHECK11-NEXT:    [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 13122// CHECK11-NEXT:    store i8 [[TMP5]], ptr [[AAA_CASTED]], align 13123// CHECK11-NEXT:    [[TMP6:%.*]] = load i32, ptr [[AAA_CASTED]], align 43124// CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], ptr [[TMP0]])3125// CHECK11-NEXT:    ret void3126//3127//3128// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.omp_outlined3129// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {3130// CHECK11-NEXT:  entry:3131// CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 43132// CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 43133// CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 43134// CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 43135// CHECK11-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 43136// CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 43137// CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 43138// CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 43139// CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 43140// CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 43141// CHECK11-NEXT:    store i32 [[AAA]], ptr [[AAA_ADDR]], align 43142// CHECK11-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 43143// CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 43144// CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 43145// CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 13146// CHECK11-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 43147// CHECK11-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 23148// CHECK11-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i323149// CHECK11-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 13150// CHECK11-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i163151// CHECK11-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 23152// CHECK11-NEXT:    [[TMP3:%.*]] = load i8, ptr [[AAA_ADDR]], align 13153// CHECK11-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP3]] to i323154// CHECK11-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 13155// CHECK11-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i83156// CHECK11-NEXT:    store i8 [[CONV5]], ptr [[AAA_ADDR]], align 13157// CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 23158// CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX]], align 43159// CHECK11-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP4]], 13160// CHECK11-NEXT:    store i32 [[ADD6]], ptr [[ARRAYIDX]], align 43161// CHECK11-NEXT:    ret void3162//3163//3164// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l2163165// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {3166// CHECK11-NEXT:  entry:3167// CHECK11-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 43168// CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 43169// CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 43170// CHECK11-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 43171// CHECK11-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 43172// CHECK11-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 43173// CHECK11-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 43174// CHECK11-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 43175// CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 43176// CHECK11-NEXT:    store i32 [[B]], ptr [[B_ADDR]], align 43177// CHECK11-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 43178// CHECK11-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 43179// CHECK11-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 43180// CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 43181// CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 43182// CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 43183// CHECK11-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 43184// CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 43185// CHECK11-NEXT:    store i32 [[TMP4]], ptr [[B_CASTED]], align 43186// CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 43187// CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]])3188// CHECK11-NEXT:    ret void3189//3190//3191// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined3192// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {3193// CHECK11-NEXT:  entry:3194// CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 43195// CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 43196// CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 43197// CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 43198// CHECK11-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 43199// CHECK11-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 43200// CHECK11-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 43201// CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 43202// CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 43203// CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 43204// CHECK11-NEXT:    store i32 [[B]], ptr [[B_ADDR]], align 43205// CHECK11-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 43206// CHECK11-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 43207// CHECK11-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 43208// CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 43209// CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 43210// CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 43211// CHECK11-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 43212// CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 43213// CHECK11-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP4]] to double3214// CHECK11-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+003215// CHECK11-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 03216// CHECK11-NEXT:    store double [[ADD]], ptr [[A]], align 43217// CHECK11-NEXT:    [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 03218// CHECK11-NEXT:    [[TMP5:%.*]] = load double, ptr [[A3]], align 43219// CHECK11-NEXT:    [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+003220// CHECK11-NEXT:    store double [[INC]], ptr [[A3]], align 43221// CHECK11-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i163222// CHECK11-NEXT:    [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]]3223// CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP6]]3224// CHECK11-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 13225// CHECK11-NEXT:    store i16 [[CONV4]], ptr [[ARRAYIDX5]], align 23226// CHECK11-NEXT:    ret void3227//3228//3229// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l1813230// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {3231// CHECK11-NEXT:  entry:3232// CHECK11-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 43233// CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 43234// CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 43235// CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 43236// CHECK11-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 43237// CHECK11-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 43238// CHECK11-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 43239// CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 43240// CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 43241// CHECK11-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 43242// CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 43243// CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 43244// CHECK11-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 43245// CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 43246// CHECK11-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 23247// CHECK11-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 23248// CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 43249// CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]])3250// CHECK11-NEXT:    ret void3251//3252//3253// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.omp_outlined3254// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {3255// CHECK11-NEXT:  entry:3256// CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 43257// CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 43258// CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 43259// CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 43260// CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 43261// CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 43262// CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 43263// CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 43264// CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 43265// CHECK11-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 43266// CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 43267// CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 43268// CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 13269// CHECK11-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 43270// CHECK11-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 23271// CHECK11-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i323272// CHECK11-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 13273// CHECK11-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i163274// CHECK11-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 23275// CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 23276// CHECK11-NEXT:    [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 43277// CHECK11-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 13278// CHECK11-NEXT:    store i32 [[ADD3]], ptr [[ARRAYIDX]], align 43279// CHECK11-NEXT:    ret void3280//3281