8534 lines · cpp
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _2// Test host codegen.3// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK14// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s5// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK16// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK37// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s8// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK39 10// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"11// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s12// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"13// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"14// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s15// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"16 17// Test target codegen - host bc file has to be created first.18// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc19// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK920// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s21// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK922// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc23// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1124// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s25// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1126 27// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc28// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"29// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s30// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"31// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc32// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"33// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s34// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"35 36// Test host codegen.37// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1738// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s39// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1740// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1941// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s42// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1943 44// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"45// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s46// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"47// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"48// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s49// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"50 51// Test target codegen - host bc file has to be created first.52// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc53// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK954// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s55// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK956// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc57// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1158// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s59// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1160 61// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc62// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"63// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s64// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"65// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc66// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"67// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s68// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"69 70// expected-no-diagnostics71#ifndef HEADER72#define HEADER73 74 75 76 77// We have 8 target regions, but only 7 that actually will generate offloading78// code, only 6 will have mapped arguments, and only 4 have all-constant map79// sizes.80 81 82 83// Check target registration is registered as a Ctor.84 85 86template<typename tx, typename ty>87struct TT{88 tx X;89 ty Y;90};91 92long long get_val() { return 0; }93 94int foo(int n) {95 int a = 0;96 short aa = 0;97 float b[10];98 float bn[n];99 double c[5][10];100 double cn[5][n];101 TT<long long, char> d;102 103 #pragma omp target parallel for104 for (int i = 3; i < 32; i += 5) {105#pragma omp cancel for106#pragma omp cancellation point for107 }108 109 long long k = get_val();110 #pragma omp target parallel for if(target: 0) linear(k : 3) schedule(dynamic)111 for (int i = 10; i > 1; i--) {112 a += 1;113 }114 115 // CHECK-32: [[FPSIZEGEP]] = getelementptr inbounds [[KMP_PRIVATES_T]], ptr [[KMP_PRIVATES]], i32 0, i32 0116 // CHECK-32: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[FPSIZEGEP]], ptr align 8 [[SIZET2]], i64 24, i1 false)117 // CHECK-32: [[FPBPGEP:%.+]] = getelementptr inbounds [[KMP_PRIVATES_T]], ptr [[KMP_PRIVATES]], i32 0, i32 1118 // CHECK-32: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[FPBPGEP]], ptr align 8 [[BPGEP]], i64 24, i1 false)119 // CHECK-32: [[FPPGEP:%.+]] = getelementptr inbounds [[KMP_PRIVATES_T]], ptr [[KMP_PRIVATES]], i32 0, i32 2120 // CHECK-32: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[FPPGEP]], ptr align 8 [[BCAST]], i64 24, i1 false)121 // CHECK-64: [[FPBPGEP:%.+]] = getelementptr inbounds [[KMP_PRIVATES_T]], ptr [[KMP_PRIVATES]], i32 0, i32 0122 // CHECK-64: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[FPBPGEP]], ptr align 8 [[BPGEP]], i64 24, i1 false)123 // CHECK-64: [[FPPGEP:%.+]] = getelementptr inbounds [[KMP_PRIVATES_T]], ptr [[KMP_PRIVATES]], i32 0, i32 1124 // CHECK-64: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[FPPGEP]], ptr align 8 [[BCAST]], i64 24, i1 false)125 // CHECK-64: [[FPSIZEGEP]] = getelementptr inbounds [[KMP_PRIVATES_T]], ptr [[KMP_PRIVATES]], i32 0, i32 2126 // CHECK-64: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[FPSIZEGEP]], ptr align 8 [[SIZET2]], i64 24, i1 false)127 int lin = 12;128 #pragma omp target parallel for if(target: 1) linear(lin, a : get_val()) nowait129 for (unsigned long long it = 2000; it >= 600; it-=400) {130 aa += 1;131 }132 133 134 135 136 #pragma omp target parallel for if(target: n>10)137 for (short it = 6; it <= 20; it-=-4) {138 a += 1;139 aa += 1;140 }141 142 // We capture 3 VLA sizes in this target region143 144 145 146 147 148 // The names below are not necessarily consistent with the names used for the149 // addresses above as some are repeated.150 151 152 153 154 155 156 157 158 159 160 #pragma omp target parallel for if(target: n>20) schedule(static, a)161 for (unsigned char it = 'z'; it >= 'a'; it+=-1) {162 a += 1;163 b[2] += 1.0;164 bn[3] += 1.0;165 c[1][2] += 1.0;166 cn[1][3] += 1.0;167 d.X += 1;168 d.Y += 1;169 }170 171 return a;172}173 174// Check that the offloading functions are emitted and that the arguments are175// correct and loaded correctly for the target regions in foo().176 177 178// Create stack storage and store argument in there.179 180// Create stack storage and store argument in there.181 182 183// Create stack storage and store argument in there.184 185// Create local storage for each capture.186 187 188 189// To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.190 191template<typename tx>192tx ftemplate(int n) {193 tx a = 0;194 short aa = 0;195 tx b[10];196 197 #pragma omp target parallel for if(target: n>40)198 for (long long i = -10; i < 10; i += 3) {199 a += 1;200 aa += 1;201 b[2] += 1;202 }203 204 return a;205}206 207static208int fstatic(int n) {209 int a = 0;210 short aa = 0;211 char aaa = 0;212 int b[10];213 214 #pragma omp target parallel for if(target: n>50)215 for (unsigned i=100; i<10; i+=10) {216 a += 1;217 aa += 1;218 aaa += 1;219 b[2] += 1;220 }221 222 return a;223}224 225struct S1 {226 double a;227 228 int r1(int n){229 int b = n+1;230 short int c[2][n];231 232 #pragma omp target parallel for if(target: n>60)233 for (unsigned long long it = 2000; it >= 600; it -= 400) {234 this->a = (double)b + 1.5;235 c[1][1] = ++a;236 }237 238 return c[1][1] + (int)b;239 }240};241 242int bar(int n){243 int a = 0;244 245 a += foo(n);246 247 S1 S;248 a += S.r1(n);249 250 a += fstatic(n);251 252 a += ftemplate<int>(n);253 254 return a;255}256 257 258 259// We capture 2 VLA sizes in this target region260 261 262// The names below are not necessarily consistent with the names used for the263// addresses above as some are repeated.264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282// Check that the offloading functions are emitted and that the arguments are283// correct and loaded correctly for the target regions of the callees of bar().284 285// Create local storage for each capture.286// Store captures in the context.287 288 289// To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.290 291 292// Create local storage for each capture.293// Store captures in the context.294 295 296 297 298// To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.299 300// Create local storage for each capture.301// Store captures in the context.302 303 304 305// To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.306 307 308#endif309// CHECK1-LABEL: define {{[^@]+}}@_Z7get_valv310// CHECK1-SAME: () #[[ATTR0:[0-9]+]] {311// CHECK1-NEXT: entry:312// CHECK1-NEXT: ret i64 0313//314//315// CHECK1-LABEL: define {{[^@]+}}@_Z3fooi316// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {317// CHECK1-NEXT: entry:318// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4319// CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4320// CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2321// CHECK1-NEXT: [[B:%.*]] = alloca [10 x float], align 4322// CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8323// CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8324// CHECK1-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8325// CHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8326// CHECK1-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8327// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8328// CHECK1-NEXT: [[K:%.*]] = alloca i64, align 8329// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8330// CHECK1-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8331// CHECK1-NEXT: [[LIN:%.*]] = alloca i32, align 4332// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8333// CHECK1-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8334// CHECK1-NEXT: [[A_CASTED2:%.*]] = alloca i64, align 8335// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8336// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8337// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8338// CHECK1-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4339// CHECK1-NEXT: [[A_CASTED3:%.*]] = alloca i64, align 8340// CHECK1-NEXT: [[AA_CASTED4:%.*]] = alloca i64, align 8341// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x ptr], align 8342// CHECK1-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x ptr], align 8343// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x ptr], align 8344// CHECK1-NEXT: [[KERNEL_ARGS8:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8345// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4346// CHECK1-NEXT: [[A_CASTED11:%.*]] = alloca i64, align 8347// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8348// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x ptr], align 8349// CHECK1-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x ptr], align 8350// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x ptr], align 8351// CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8352// CHECK1-NEXT: [[KERNEL_ARGS17:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8353// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])354// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4355// CHECK1-NEXT: store i32 0, ptr [[A]], align 4356// CHECK1-NEXT: store i16 0, ptr [[AA]], align 2357// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4358// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64359// CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()360// CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8361// CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4362// CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8363// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4364// CHECK1-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64365// CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]366// CHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8367// CHECK1-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8368// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0369// CHECK1-NEXT: store i32 3, ptr [[TMP7]], align 4370// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1371// CHECK1-NEXT: store i32 0, ptr [[TMP8]], align 4372// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2373// CHECK1-NEXT: store ptr null, ptr [[TMP9]], align 8374// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3375// CHECK1-NEXT: store ptr null, ptr [[TMP10]], align 8376// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4377// CHECK1-NEXT: store ptr null, ptr [[TMP11]], align 8378// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5379// CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8380// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6381// CHECK1-NEXT: store ptr null, ptr [[TMP13]], align 8382// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7383// CHECK1-NEXT: store ptr null, ptr [[TMP14]], align 8384// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8385// CHECK1-NEXT: store i64 0, ptr [[TMP15]], align 8386// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9387// CHECK1-NEXT: store i64 0, ptr [[TMP16]], align 8388// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10389// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP17]], align 4390// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11391// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP18]], align 4392// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12393// CHECK1-NEXT: store i32 0, ptr [[TMP19]], align 4394// CHECK1-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, ptr [[KERNEL_ARGS]])395// CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0396// CHECK1-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]397// CHECK1: omp_offload.failed:398// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR3:[0-9]+]]399// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]400// CHECK1: omp_offload.cont:401// CHECK1-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()402// CHECK1-NEXT: store i64 [[CALL]], ptr [[K]], align 8403// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[A]], align 4404// CHECK1-NEXT: store i32 [[TMP22]], ptr [[A_CASTED]], align 4405// CHECK1-NEXT: [[TMP23:%.*]] = load i64, ptr [[A_CASTED]], align 8406// CHECK1-NEXT: [[TMP24:%.*]] = load i64, ptr [[K]], align 8407// CHECK1-NEXT: store i64 [[TMP24]], ptr [[K_CASTED]], align 8408// CHECK1-NEXT: [[TMP25:%.*]] = load i64, ptr [[K_CASTED]], align 8409// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP23]], i64 [[TMP25]]) #[[ATTR3]]410// CHECK1-NEXT: store i32 12, ptr [[LIN]], align 4411// CHECK1-NEXT: [[TMP26:%.*]] = load i16, ptr [[AA]], align 2412// CHECK1-NEXT: store i16 [[TMP26]], ptr [[AA_CASTED]], align 2413// CHECK1-NEXT: [[TMP27:%.*]] = load i64, ptr [[AA_CASTED]], align 8414// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[LIN]], align 4415// CHECK1-NEXT: store i32 [[TMP28]], ptr [[LIN_CASTED]], align 4416// CHECK1-NEXT: [[TMP29:%.*]] = load i64, ptr [[LIN_CASTED]], align 8417// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[A]], align 4418// CHECK1-NEXT: store i32 [[TMP30]], ptr [[A_CASTED2]], align 4419// CHECK1-NEXT: [[TMP31:%.*]] = load i64, ptr [[A_CASTED2]], align 8420// CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0421// CHECK1-NEXT: store i64 [[TMP27]], ptr [[TMP32]], align 8422// CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0423// CHECK1-NEXT: store i64 [[TMP27]], ptr [[TMP33]], align 8424// CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0425// CHECK1-NEXT: store ptr null, ptr [[TMP34]], align 8426// CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1427// CHECK1-NEXT: store i64 [[TMP29]], ptr [[TMP35]], align 8428// CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1429// CHECK1-NEXT: store i64 [[TMP29]], ptr [[TMP36]], align 8430// CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1431// CHECK1-NEXT: store ptr null, ptr [[TMP37]], align 8432// CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2433// CHECK1-NEXT: store i64 [[TMP31]], ptr [[TMP38]], align 8434// CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2435// CHECK1-NEXT: store i64 [[TMP31]], ptr [[TMP39]], align 8436// CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2437// CHECK1-NEXT: store ptr null, ptr [[TMP40]], align 8438// CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0439// CHECK1-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0440// CHECK1-NEXT: [[TMP43:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0441// CHECK1-NEXT: [[TMP44:%.*]] = load i16, ptr [[AA]], align 2442// CHECK1-NEXT: store i16 [[TMP44]], ptr [[TMP43]], align 4443// CHECK1-NEXT: [[TMP45:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1444// CHECK1-NEXT: [[TMP46:%.*]] = load i32, ptr [[LIN]], align 4445// CHECK1-NEXT: store i32 [[TMP46]], ptr [[TMP45]], align 4446// CHECK1-NEXT: [[TMP47:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 2447// CHECK1-NEXT: [[TMP48:%.*]] = load i32, ptr [[A]], align 4448// CHECK1-NEXT: store i32 [[TMP48]], ptr [[TMP47]], align 4449// CHECK1-NEXT: [[TMP49:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, ptr @.omp_task_entry., i64 -1)450// CHECK1-NEXT: [[TMP50:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP49]], i32 0, i32 0451// CHECK1-NEXT: [[TMP51:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP50]], i32 0, i32 0452// CHECK1-NEXT: [[TMP52:%.*]] = load ptr, ptr [[TMP51]], align 8453// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP52]], ptr align 4 [[AGG_CAPTURED]], i64 12, i1 false)454// CHECK1-NEXT: [[TMP53:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP49]], i32 0, i32 1455// CHECK1-NEXT: [[TMP54:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP53]], i32 0, i32 0456// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP54]], ptr align 8 [[TMP41]], i64 24, i1 false)457// CHECK1-NEXT: [[TMP55:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP53]], i32 0, i32 1458// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP55]], ptr align 8 [[TMP42]], i64 24, i1 false)459// CHECK1-NEXT: [[TMP56:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP53]], i32 0, i32 2460// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP56]], ptr align 8 @.offload_sizes, i64 24, i1 false)461// CHECK1-NEXT: [[TMP57:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP53]], i32 0, i32 3462// CHECK1-NEXT: [[TMP58:%.*]] = load i16, ptr [[AA]], align 2463// CHECK1-NEXT: store i16 [[TMP58]], ptr [[TMP57]], align 8464// CHECK1-NEXT: [[TMP59:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB2]], i32 [[TMP0]], ptr [[TMP49]])465// CHECK1-NEXT: [[TMP60:%.*]] = load i32, ptr [[A]], align 4466// CHECK1-NEXT: store i32 [[TMP60]], ptr [[A_CASTED3]], align 4467// CHECK1-NEXT: [[TMP61:%.*]] = load i64, ptr [[A_CASTED3]], align 8468// CHECK1-NEXT: [[TMP62:%.*]] = load i16, ptr [[AA]], align 2469// CHECK1-NEXT: store i16 [[TMP62]], ptr [[AA_CASTED4]], align 2470// CHECK1-NEXT: [[TMP63:%.*]] = load i64, ptr [[AA_CASTED4]], align 8471// CHECK1-NEXT: [[TMP64:%.*]] = load i32, ptr [[N_ADDR]], align 4472// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP64]], 10473// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]474// CHECK1: omp_if.then:475// CHECK1-NEXT: [[TMP65:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0476// CHECK1-NEXT: store i64 [[TMP61]], ptr [[TMP65]], align 8477// CHECK1-NEXT: [[TMP66:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0478// CHECK1-NEXT: store i64 [[TMP61]], ptr [[TMP66]], align 8479// CHECK1-NEXT: [[TMP67:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0480// CHECK1-NEXT: store ptr null, ptr [[TMP67]], align 8481// CHECK1-NEXT: [[TMP68:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1482// CHECK1-NEXT: store i64 [[TMP63]], ptr [[TMP68]], align 8483// CHECK1-NEXT: [[TMP69:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 1484// CHECK1-NEXT: store i64 [[TMP63]], ptr [[TMP69]], align 8485// CHECK1-NEXT: [[TMP70:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1486// CHECK1-NEXT: store ptr null, ptr [[TMP70]], align 8487// CHECK1-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0488// CHECK1-NEXT: [[TMP72:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0489// CHECK1-NEXT: [[TMP73:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 0490// CHECK1-NEXT: store i32 3, ptr [[TMP73]], align 4491// CHECK1-NEXT: [[TMP74:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 1492// CHECK1-NEXT: store i32 2, ptr [[TMP74]], align 4493// CHECK1-NEXT: [[TMP75:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 2494// CHECK1-NEXT: store ptr [[TMP71]], ptr [[TMP75]], align 8495// CHECK1-NEXT: [[TMP76:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 3496// CHECK1-NEXT: store ptr [[TMP72]], ptr [[TMP76]], align 8497// CHECK1-NEXT: [[TMP77:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 4498// CHECK1-NEXT: store ptr @.offload_sizes.1, ptr [[TMP77]], align 8499// CHECK1-NEXT: [[TMP78:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 5500// CHECK1-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP78]], align 8501// CHECK1-NEXT: [[TMP79:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 6502// CHECK1-NEXT: store ptr null, ptr [[TMP79]], align 8503// CHECK1-NEXT: [[TMP80:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 7504// CHECK1-NEXT: store ptr null, ptr [[TMP80]], align 8505// CHECK1-NEXT: [[TMP81:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 8506// CHECK1-NEXT: store i64 0, ptr [[TMP81]], align 8507// CHECK1-NEXT: [[TMP82:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 9508// CHECK1-NEXT: store i64 0, ptr [[TMP82]], align 8509// CHECK1-NEXT: [[TMP83:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 10510// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP83]], align 4511// CHECK1-NEXT: [[TMP84:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 11512// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP84]], align 4513// CHECK1-NEXT: [[TMP85:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 12514// CHECK1-NEXT: store i32 0, ptr [[TMP85]], align 4515// CHECK1-NEXT: [[TMP86:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.region_id, ptr [[KERNEL_ARGS8]])516// CHECK1-NEXT: [[TMP87:%.*]] = icmp ne i32 [[TMP86]], 0517// CHECK1-NEXT: br i1 [[TMP87]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]]518// CHECK1: omp_offload.failed9:519// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136(i64 [[TMP61]], i64 [[TMP63]]) #[[ATTR3]]520// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT10]]521// CHECK1: omp_offload.cont10:522// CHECK1-NEXT: br label [[OMP_IF_END:%.*]]523// CHECK1: omp_if.else:524// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136(i64 [[TMP61]], i64 [[TMP63]]) #[[ATTR3]]525// CHECK1-NEXT: br label [[OMP_IF_END]]526// CHECK1: omp_if.end:527// CHECK1-NEXT: [[TMP88:%.*]] = load i32, ptr [[A]], align 4528// CHECK1-NEXT: store i32 [[TMP88]], ptr [[DOTCAPTURE_EXPR_]], align 4529// CHECK1-NEXT: [[TMP89:%.*]] = load i32, ptr [[A]], align 4530// CHECK1-NEXT: store i32 [[TMP89]], ptr [[A_CASTED11]], align 4531// CHECK1-NEXT: [[TMP90:%.*]] = load i64, ptr [[A_CASTED11]], align 8532// CHECK1-NEXT: [[TMP91:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4533// CHECK1-NEXT: store i32 [[TMP91]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4534// CHECK1-NEXT: [[TMP92:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8535// CHECK1-NEXT: [[TMP93:%.*]] = load i32, ptr [[N_ADDR]], align 4536// CHECK1-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP93]], 20537// CHECK1-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE20:%.*]]538// CHECK1: omp_if.then13:539// CHECK1-NEXT: [[TMP94:%.*]] = mul nuw i64 [[TMP2]], 4540// CHECK1-NEXT: [[TMP95:%.*]] = mul nuw i64 5, [[TMP5]]541// CHECK1-NEXT: [[TMP96:%.*]] = mul nuw i64 [[TMP95]], 8542// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.3, i64 80, i1 false)543// CHECK1-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0544// CHECK1-NEXT: store i64 [[TMP90]], ptr [[TMP97]], align 8545// CHECK1-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 0546// CHECK1-NEXT: store i64 [[TMP90]], ptr [[TMP98]], align 8547// CHECK1-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 0548// CHECK1-NEXT: store ptr null, ptr [[TMP99]], align 8549// CHECK1-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1550// CHECK1-NEXT: store ptr [[B]], ptr [[TMP100]], align 8551// CHECK1-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 1552// CHECK1-NEXT: store ptr [[B]], ptr [[TMP101]], align 8553// CHECK1-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 1554// CHECK1-NEXT: store ptr null, ptr [[TMP102]], align 8555// CHECK1-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2556// CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP103]], align 8557// CHECK1-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 2558// CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP104]], align 8559// CHECK1-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 2560// CHECK1-NEXT: store ptr null, ptr [[TMP105]], align 8561// CHECK1-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3562// CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP106]], align 8563// CHECK1-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 3564// CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP107]], align 8565// CHECK1-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3566// CHECK1-NEXT: store i64 [[TMP94]], ptr [[TMP108]], align 8567// CHECK1-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 3568// CHECK1-NEXT: store ptr null, ptr [[TMP109]], align 8569// CHECK1-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4570// CHECK1-NEXT: store ptr [[C]], ptr [[TMP110]], align 8571// CHECK1-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 4572// CHECK1-NEXT: store ptr [[C]], ptr [[TMP111]], align 8573// CHECK1-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 4574// CHECK1-NEXT: store ptr null, ptr [[TMP112]], align 8575// CHECK1-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5576// CHECK1-NEXT: store i64 5, ptr [[TMP113]], align 8577// CHECK1-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 5578// CHECK1-NEXT: store i64 5, ptr [[TMP114]], align 8579// CHECK1-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 5580// CHECK1-NEXT: store ptr null, ptr [[TMP115]], align 8581// CHECK1-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6582// CHECK1-NEXT: store i64 [[TMP5]], ptr [[TMP116]], align 8583// CHECK1-NEXT: [[TMP117:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 6584// CHECK1-NEXT: store i64 [[TMP5]], ptr [[TMP117]], align 8585// CHECK1-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 6586// CHECK1-NEXT: store ptr null, ptr [[TMP118]], align 8587// CHECK1-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7588// CHECK1-NEXT: store ptr [[VLA1]], ptr [[TMP119]], align 8589// CHECK1-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 7590// CHECK1-NEXT: store ptr [[VLA1]], ptr [[TMP120]], align 8591// CHECK1-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 7592// CHECK1-NEXT: store i64 [[TMP96]], ptr [[TMP121]], align 8593// CHECK1-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 7594// CHECK1-NEXT: store ptr null, ptr [[TMP122]], align 8595// CHECK1-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8596// CHECK1-NEXT: store ptr [[D]], ptr [[TMP123]], align 8597// CHECK1-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 8598// CHECK1-NEXT: store ptr [[D]], ptr [[TMP124]], align 8599// CHECK1-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 8600// CHECK1-NEXT: store ptr null, ptr [[TMP125]], align 8601// CHECK1-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9602// CHECK1-NEXT: store i64 [[TMP92]], ptr [[TMP126]], align 8603// CHECK1-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 9604// CHECK1-NEXT: store i64 [[TMP92]], ptr [[TMP127]], align 8605// CHECK1-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 9606// CHECK1-NEXT: store ptr null, ptr [[TMP128]], align 8607// CHECK1-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0608// CHECK1-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 0609// CHECK1-NEXT: [[TMP131:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0610// CHECK1-NEXT: [[TMP132:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 0611// CHECK1-NEXT: store i32 3, ptr [[TMP132]], align 4612// CHECK1-NEXT: [[TMP133:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 1613// CHECK1-NEXT: store i32 10, ptr [[TMP133]], align 4614// CHECK1-NEXT: [[TMP134:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 2615// CHECK1-NEXT: store ptr [[TMP129]], ptr [[TMP134]], align 8616// CHECK1-NEXT: [[TMP135:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 3617// CHECK1-NEXT: store ptr [[TMP130]], ptr [[TMP135]], align 8618// CHECK1-NEXT: [[TMP136:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 4619// CHECK1-NEXT: store ptr [[TMP131]], ptr [[TMP136]], align 8620// CHECK1-NEXT: [[TMP137:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 5621// CHECK1-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP137]], align 8622// CHECK1-NEXT: [[TMP138:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 6623// CHECK1-NEXT: store ptr null, ptr [[TMP138]], align 8624// CHECK1-NEXT: [[TMP139:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 7625// CHECK1-NEXT: store ptr null, ptr [[TMP139]], align 8626// CHECK1-NEXT: [[TMP140:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 8627// CHECK1-NEXT: store i64 0, ptr [[TMP140]], align 8628// CHECK1-NEXT: [[TMP141:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 9629// CHECK1-NEXT: store i64 0, ptr [[TMP141]], align 8630// CHECK1-NEXT: [[TMP142:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 10631// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP142]], align 4632// CHECK1-NEXT: [[TMP143:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 11633// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP143]], align 4634// CHECK1-NEXT: [[TMP144:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 12635// CHECK1-NEXT: store i32 0, ptr [[TMP144]], align 4636// CHECK1-NEXT: [[TMP145:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.region_id, ptr [[KERNEL_ARGS17]])637// CHECK1-NEXT: [[TMP146:%.*]] = icmp ne i32 [[TMP145]], 0638// CHECK1-NEXT: br i1 [[TMP146]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]]639// CHECK1: omp_offload.failed18:640// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i64 [[TMP90]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP92]]) #[[ATTR3]]641// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT19]]642// CHECK1: omp_offload.cont19:643// CHECK1-NEXT: br label [[OMP_IF_END21:%.*]]644// CHECK1: omp_if.else20:645// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i64 [[TMP90]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP92]]) #[[ATTR3]]646// CHECK1-NEXT: br label [[OMP_IF_END21]]647// CHECK1: omp_if.end21:648// CHECK1-NEXT: [[TMP147:%.*]] = load i32, ptr [[A]], align 4649// CHECK1-NEXT: [[TMP148:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8650// CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP148]])651// CHECK1-NEXT: ret i32 [[TMP147]]652//653//654// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103655// CHECK1-SAME: () #[[ATTR2:[0-9]+]] {656// CHECK1-NEXT: entry:657// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined)658// CHECK1-NEXT: ret void659//660//661// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined662// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] {663// CHECK1-NEXT: entry:664// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8665// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8666// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4667// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4668// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4669// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4670// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4671// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4672// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4673// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8674// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8675// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4676// CHECK1-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 4677// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4678// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4679// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8680// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4681// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)682// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4683// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5684// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]685// CHECK1: cond.true:686// CHECK1-NEXT: br label [[COND_END:%.*]]687// CHECK1: cond.false:688// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4689// CHECK1-NEXT: br label [[COND_END]]690// CHECK1: cond.end:691// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]692// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4693// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4694// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4695// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]696// CHECK1: omp.inner.for.cond:697// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4698// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4699// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]700// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]701// CHECK1: omp.inner.for.body:702// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4703// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5704// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]705// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4706// CHECK1-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(ptr @[[GLOB2]], i32 [[TMP1]], i32 2)707// CHECK1-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0708// CHECK1-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]709// CHECK1: .cancel.exit:710// CHECK1-NEXT: br label [[CANCEL_EXIT:%.*]]711// CHECK1: .cancel.continue:712// CHECK1-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(ptr @[[GLOB2]], i32 [[TMP1]], i32 2)713// CHECK1-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0714// CHECK1-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]715// CHECK1: .cancel.exit2:716// CHECK1-NEXT: br label [[CANCEL_EXIT]]717// CHECK1: .cancel.continue3:718// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]719// CHECK1: omp.body.continue:720// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]721// CHECK1: omp.inner.for.inc:722// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4723// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1724// CHECK1-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4725// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]726// CHECK1: omp.inner.for.end:727// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]728// CHECK1: omp.loop.exit:729// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])730// CHECK1-NEXT: br label [[CANCEL_CONT:%.*]]731// CHECK1: cancel.cont:732// CHECK1-NEXT: ret void733// CHECK1: cancel.exit:734// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])735// CHECK1-NEXT: br label [[CANCEL_CONT]]736//737//738// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110739// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR2]] {740// CHECK1-NEXT: entry:741// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8742// CHECK1-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8743// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8744// CHECK1-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8745// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8746// CHECK1-NEXT: store i64 [[K]], ptr [[K_ADDR]], align 8747// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4748// CHECK1-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4749// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8750// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[K_ADDR]], align 8751// CHECK1-NEXT: store i64 [[TMP2]], ptr [[K_CASTED]], align 8752// CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[K_CASTED]], align 8753// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined, i64 [[TMP1]], i64 [[TMP3]])754// CHECK1-NEXT: ret void755//756//757// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined758// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR2]] {759// CHECK1-NEXT: entry:760// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8761// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8762// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8763// CHECK1-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8764// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4765// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4766// CHECK1-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8767// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4768// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4769// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4770// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4771// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4772// CHECK1-NEXT: [[K1:%.*]] = alloca i64, align 8773// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8774// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8775// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8776// CHECK1-NEXT: store i64 [[K]], ptr [[K_ADDR]], align 8777// CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[K_ADDR]], align 8778// CHECK1-NEXT: store i64 [[TMP0]], ptr [[DOTLINEAR_START]], align 8779// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4780// CHECK1-NEXT: store i32 8, ptr [[DOTOMP_UB]], align 4781// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4782// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4783// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8784// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4785// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP2]])786// CHECK1-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 35, i32 0, i32 8, i32 1, i32 1)787// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]]788// CHECK1: omp.dispatch.cond:789// CHECK1-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB2]], i32 [[TMP2]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])790// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0791// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]792// CHECK1: omp.dispatch.body:793// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4794// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4795// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]796// CHECK1: omp.inner.for.cond:797// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]]798// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]]799// CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]800// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]801// CHECK1: omp.inner.for.body:802// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]803// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1804// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]805// CHECK1-NEXT: store i32 [[SUB]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]]806// CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP12]]807// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]808// CHECK1-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3809// CHECK1-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64810// CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV]]811// CHECK1-NEXT: store i64 [[ADD]], ptr [[K1]], align 8, !llvm.access.group [[ACC_GRP12]]812// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP12]]813// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1814// CHECK1-NEXT: store i32 [[ADD3]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP12]]815// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]816// CHECK1: omp.body.continue:817// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]818// CHECK1: omp.inner.for.inc:819// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]820// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1821// CHECK1-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]822// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]823// CHECK1: omp.inner.for.end:824// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]825// CHECK1: omp.dispatch.inc:826// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]827// CHECK1: omp.dispatch.end:828// CHECK1-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB2]], i32 [[TMP2]])829// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4830// CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0831// CHECK1-NEXT: br i1 [[TMP13]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]832// CHECK1: .omp.linear.pu:833// CHECK1-NEXT: [[TMP14:%.*]] = load i64, ptr [[K1]], align 8834// CHECK1-NEXT: store i64 [[TMP14]], ptr [[K_ADDR]], align 8835// CHECK1-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]836// CHECK1: .omp.linear.pu.done:837// CHECK1-NEXT: ret void838//839//840// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128841// CHECK1-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] {842// CHECK1-NEXT: entry:843// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8844// CHECK1-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8845// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8846// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8847// CHECK1-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8848// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8849// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8850// CHECK1-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 8851// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8852// CHECK1-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2853// CHECK1-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2854// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8855// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 4856// CHECK1-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 4857// CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[LIN_CASTED]], align 8858// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4859// CHECK1-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 4860// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[A_CASTED]], align 8861// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.omp_outlined, i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])862// CHECK1-NEXT: ret void863//864//865// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.omp_outlined866// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] {867// CHECK1-NEXT: entry:868// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8869// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8870// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8871// CHECK1-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8872// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8873// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8874// CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8875// CHECK1-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4876// CHECK1-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4877// CHECK1-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8878// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8879// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8880// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8881// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4882// CHECK1-NEXT: [[IT:%.*]] = alloca i64, align 8883// CHECK1-NEXT: [[LIN2:%.*]] = alloca i32, align 4884// CHECK1-NEXT: [[A3:%.*]] = alloca i32, align 4885// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8886// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8887// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8888// CHECK1-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 8889// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8890// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 4891// CHECK1-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 4892// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4893// CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 4894// CHECK1-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()895// CHECK1-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 8896// CHECK1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8897// CHECK1-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8898// CHECK1-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8899// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4900// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8901// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4902// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP3]])903// CHECK1-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)904// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8905// CHECK1-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3906// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]907// CHECK1: cond.true:908// CHECK1-NEXT: br label [[COND_END:%.*]]909// CHECK1: cond.false:910// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8911// CHECK1-NEXT: br label [[COND_END]]912// CHECK1: cond.end:913// CHECK1-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]914// CHECK1-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8915// CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8916// CHECK1-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 8917// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]918// CHECK1: omp.inner.for.cond:919// CHECK1-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8920// CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8921// CHECK1-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]922// CHECK1-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]923// CHECK1: omp.inner.for.body:924// CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8925// CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400926// CHECK1-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]927// CHECK1-NEXT: store i64 [[SUB]], ptr [[IT]], align 8928// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4929// CHECK1-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i64930// CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8931// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8932// CHECK1-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]]933// CHECK1-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]]934// CHECK1-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i32935// CHECK1-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 4936// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4937// CHECK1-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64938// CHECK1-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8939// CHECK1-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8940// CHECK1-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]]941// CHECK1-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]]942// CHECK1-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i32943// CHECK1-NEXT: store i32 [[CONV10]], ptr [[A3]], align 4944// CHECK1-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2945// CHECK1-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i32946// CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 1947// CHECK1-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16948// CHECK1-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 2949// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]950// CHECK1: omp.body.continue:951// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]952// CHECK1: omp.inner.for.inc:953// CHECK1-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8954// CHECK1-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 1955// CHECK1-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8956// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]957// CHECK1: omp.inner.for.end:958// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]959// CHECK1: omp.loop.exit:960// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]])961// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4962// CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0963// CHECK1-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]964// CHECK1: .omp.linear.pu:965// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[LIN2]], align 4966// CHECK1-NEXT: store i32 [[TMP20]], ptr [[LIN_ADDR]], align 4967// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[A3]], align 4968// CHECK1-NEXT: store i32 [[TMP21]], ptr [[A_ADDR]], align 4969// CHECK1-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]970// CHECK1: .omp.linear.pu.done:971// CHECK1-NEXT: ret void972//973//974// CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map.975// CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] {976// CHECK1-NEXT: entry:977// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8978// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8979// CHECK1-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8980// CHECK1-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8981// CHECK1-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8982// CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8983// CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8984// CHECK1-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 8985// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3]], align 8986// CHECK1-NEXT: store ptr [[TMP4]], ptr [[DOTADDR4]], align 8987// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 8988// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP5]], i32 0, i32 0989// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTADDR2]], align 8990// CHECK1-NEXT: store ptr [[TMP6]], ptr [[TMP7]], align 8991// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 1992// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTADDR3]], align 8993// CHECK1-NEXT: store ptr [[TMP8]], ptr [[TMP9]], align 8994// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 2995// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTADDR4]], align 8996// CHECK1-NEXT: store ptr [[TMP10]], ptr [[TMP11]], align 8997// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 3998// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTADDR1]], align 8999// CHECK1-NEXT: store ptr [[TMP12]], ptr [[TMP13]], align 81000// CHECK1-NEXT: ret void1001//1002//1003// CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry.1004// CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] {1005// CHECK1-NEXT: entry:1006// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 41007// CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 81008// CHECK1-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 81009// CHECK1-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 81010// CHECK1-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 81011// CHECK1-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 81012// CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 81013// CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 81014// CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca ptr, align 81015// CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca ptr, align 81016// CHECK1-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81017// CHECK1-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 81018// CHECK1-NEXT: [[LIN_CASTED_I:%.*]] = alloca i64, align 81019// CHECK1-NEXT: [[A_CASTED_I:%.*]] = alloca i64, align 81020// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32, align 41021// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 81022// CHECK1-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 41023// CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 81024// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 41025// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 81026// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 01027// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 21028// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 01029// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 81030// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 11031// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])1032// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])1033// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])1034// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])1035// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META24:![0-9]+]]1036// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META24]]1037// CHECK1-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META24]]1038// CHECK1-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META24]]1039// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META24]]1040// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META24]]1041// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META24]]1042// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META24]]1043// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META24]]1044// CHECK1-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]1045// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META24]]1046// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META24]]1047// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias [[META24]]1048// CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias [[META24]]1049// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP9]], i32 0, i32 11050// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 21051// CHECK1-NEXT: store i32 3, ptr [[KERNEL_ARGS_I]], align 4, !noalias [[META24]]1052// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 11053// CHECK1-NEXT: store i32 3, ptr [[TMP18]], align 4, !noalias [[META24]]1054// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 21055// CHECK1-NEXT: store ptr [[TMP13]], ptr [[TMP19]], align 8, !noalias [[META24]]1056// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 31057// CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP20]], align 8, !noalias [[META24]]1058// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 41059// CHECK1-NEXT: store ptr [[TMP15]], ptr [[TMP21]], align 8, !noalias [[META24]]1060// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 51061// CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP22]], align 8, !noalias [[META24]]1062// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 61063// CHECK1-NEXT: store ptr null, ptr [[TMP23]], align 8, !noalias [[META24]]1064// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 71065// CHECK1-NEXT: store ptr null, ptr [[TMP24]], align 8, !noalias [[META24]]1066// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 81067// CHECK1-NEXT: store i64 0, ptr [[TMP25]], align 8, !noalias [[META24]]1068// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 91069// CHECK1-NEXT: store i64 1, ptr [[TMP26]], align 8, !noalias [[META24]]1070// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 101071// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP27]], align 4, !noalias [[META24]]1072// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 111073// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4, !noalias [[META24]]1074// CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 121075// CHECK1-NEXT: store i32 0, ptr [[TMP29]], align 4, !noalias [[META24]]1076// CHECK1-NEXT: [[TMP30:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.region_id, ptr [[KERNEL_ARGS_I]])1077// CHECK1-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 01078// CHECK1-NEXT: br i1 [[TMP31]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]]1079// CHECK1: omp_offload.failed.i:1080// CHECK1-NEXT: [[TMP32:%.*]] = load i16, ptr [[TMP12]], align 21081// CHECK1-NEXT: store i16 [[TMP32]], ptr [[AA_CASTED_I]], align 2, !noalias [[META24]]1082// CHECK1-NEXT: [[TMP33:%.*]] = load i64, ptr [[AA_CASTED_I]], align 8, !noalias [[META24]]1083// CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[TMP16]], align 41084// CHECK1-NEXT: store i32 [[TMP34]], ptr [[LIN_CASTED_I]], align 4, !noalias [[META24]]1085// CHECK1-NEXT: [[TMP35:%.*]] = load i64, ptr [[LIN_CASTED_I]], align 8, !noalias [[META24]]1086// CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[TMP17]], align 41087// CHECK1-NEXT: store i32 [[TMP36]], ptr [[A_CASTED_I]], align 4, !noalias [[META24]]1088// CHECK1-NEXT: [[TMP37:%.*]] = load i64, ptr [[A_CASTED_I]], align 8, !noalias [[META24]]1089// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128(i64 [[TMP33]], i64 [[TMP35]], i64 [[TMP37]]) #[[ATTR3]]1090// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__EXIT]]1091// CHECK1: .omp_outlined..exit:1092// CHECK1-NEXT: ret i32 01093//1094//1095// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1361096// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {1097// CHECK1-NEXT: entry:1098// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 81099// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 81100// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 81101// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 81102// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 81103// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 81104// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41105// CHECK1-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 41106// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 81107// CHECK1-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 21108// CHECK1-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 21109// CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 81110// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined, i64 [[TMP1]], i64 [[TMP3]])1111// CHECK1-NEXT: ret void1112//1113//1114// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined1115// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {1116// CHECK1-NEXT: entry:1117// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81118// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81119// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 81120// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 81121// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41122// CHECK1-NEXT: [[TMP:%.*]] = alloca i16, align 21123// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 41124// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 41125// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41126// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41127// CHECK1-NEXT: [[IT:%.*]] = alloca i16, align 21128// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81129// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81130// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 81131// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 81132// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 41133// CHECK1-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 41134// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 41135// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41136// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81137// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 41138// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1139// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41140// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 31141// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1142// CHECK1: cond.true:1143// CHECK1-NEXT: br label [[COND_END:%.*]]1144// CHECK1: cond.false:1145// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41146// CHECK1-NEXT: br label [[COND_END]]1147// CHECK1: cond.end:1148// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]1149// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 41150// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41151// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 41152// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1153// CHECK1: omp.inner.for.cond:1154// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41155// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41156// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]1157// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1158// CHECK1: omp.inner.for.body:1159// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41160// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 41161// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]1162// CHECK1-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i161163// CHECK1-NEXT: store i16 [[CONV]], ptr [[IT]], align 21164// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 41165// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 11166// CHECK1-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 41167// CHECK1-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 21168// CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i321169// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 11170// CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i161171// CHECK1-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 21172// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1173// CHECK1: omp.body.continue:1174// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1175// CHECK1: omp.inner.for.inc:1176// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41177// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 11178// CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 41179// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]1180// CHECK1: omp.inner.for.end:1181// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]1182// CHECK1: omp.loop.exit:1183// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])1184// CHECK1-NEXT: ret void1185//1186//1187// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1601188// CHECK1-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {1189// CHECK1-NEXT: entry:1190// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 81191// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 81192// CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 81193// CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 81194// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 81195// CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 81196// CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 81197// CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 81198// CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 81199// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 81200// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 81201// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 81202// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 81203// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 81204// CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 81205// CHECK1-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 81206// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 81207// CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 81208// CHECK1-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 81209// CHECK1-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 81210// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 81211// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 81212// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 81213// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 81214// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 81215// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 81216// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 81217// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 81218// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 81219// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 81220// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 41221// CHECK1-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 41222// CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 81223// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 41224// CHECK1-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 41225// CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 81226// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i64 [[TMP11]])1227// CHECK1-NEXT: ret void1228//1229//1230// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined1231// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {1232// CHECK1-NEXT: entry:1233// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81234// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81235// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 81236// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 81237// CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 81238// CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 81239// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 81240// CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 81241// CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 81242// CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 81243// CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 81244// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 81245// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41246// CHECK1-NEXT: [[TMP:%.*]] = alloca i8, align 11247// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 41248// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 41249// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41250// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41251// CHECK1-NEXT: [[IT:%.*]] = alloca i8, align 11252// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81253// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81254// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 81255// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 81256// CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 81257// CHECK1-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 81258// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 81259// CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 81260// CHECK1-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 81261// CHECK1-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 81262// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 81263// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 81264// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 81265// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 81266// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 81267// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 81268// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 81269// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 81270// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 81271// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 81272// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 41273// CHECK1-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 41274// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 41275// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41276// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 41277// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81278// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 41279// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])1280// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]]1281// CHECK1: omp.dispatch.cond:1282// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41283// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 251284// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1285// CHECK1: cond.true:1286// CHECK1-NEXT: br label [[COND_END:%.*]]1287// CHECK1: cond.false:1288// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41289// CHECK1-NEXT: br label [[COND_END]]1290// CHECK1: cond.end:1291// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]1292// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 41293// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41294// CHECK1-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 41295// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41296// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41297// CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]1298// CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]1299// CHECK1: omp.dispatch.body:1300// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1301// CHECK1: omp.inner.for.cond:1302// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41303// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41304// CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]1305// CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1306// CHECK1: omp.inner.for.body:1307// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41308// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 11309// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]1310// CHECK1-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i81311// CHECK1-NEXT: store i8 [[CONV]], ptr [[IT]], align 11312// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 41313// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 11314// CHECK1-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 41315// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 21316// CHECK1-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 41317// CHECK1-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double1318// CHECK1-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+001319// CHECK1-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float1320// CHECK1-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 41321// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 31322// CHECK1-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 41323// CHECK1-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double1324// CHECK1-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+001325// CHECK1-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float1326// CHECK1-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 41327// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 11328// CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i64 0, i64 21329// CHECK1-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 81330// CHECK1-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+001331// CHECK1-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 81332// CHECK1-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]1333// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP23]]1334// CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i64 31335// CHECK1-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 81336// CHECK1-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+001337// CHECK1-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 81338// CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 01339// CHECK1-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 81340// CHECK1-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 11341// CHECK1-NEXT: store i64 [[ADD20]], ptr [[X]], align 81342// CHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 11343// CHECK1-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 81344// CHECK1-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i321345// CHECK1-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 11346// CHECK1-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i81347// CHECK1-NEXT: store i8 [[CONV23]], ptr [[Y]], align 81348// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1349// CHECK1: omp.body.continue:1350// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1351// CHECK1: omp.inner.for.inc:1352// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41353// CHECK1-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 11354// CHECK1-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 41355// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]1356// CHECK1: omp.inner.for.end:1357// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]1358// CHECK1: omp.dispatch.inc:1359// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41360// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 41361// CHECK1-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]1362// CHECK1-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 41363// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41364// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 41365// CHECK1-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]1366// CHECK1-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 41367// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]1368// CHECK1: omp.dispatch.end:1369// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]])1370// CHECK1-NEXT: ret void1371//1372//1373// CHECK1-LABEL: define {{[^@]+}}@_Z3bari1374// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {1375// CHECK1-NEXT: entry:1376// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 41377// CHECK1-NEXT: [[A:%.*]] = alloca i32, align 41378// CHECK1-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 81379// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 41380// CHECK1-NEXT: store i32 0, ptr [[A]], align 41381// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 41382// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]])1383// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 41384// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]1385// CHECK1-NEXT: store i32 [[ADD]], ptr [[A]], align 41386// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 41387// CHECK1-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]])1388// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 41389// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]1390// CHECK1-NEXT: store i32 [[ADD2]], ptr [[A]], align 41391// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 41392// CHECK1-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]])1393// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 41394// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]1395// CHECK1-NEXT: store i32 [[ADD4]], ptr [[A]], align 41396// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 41397// CHECK1-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]])1398// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 41399// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]1400// CHECK1-NEXT: store i32 [[ADD6]], ptr [[A]], align 41401// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 41402// CHECK1-NEXT: ret i32 [[TMP8]]1403//1404//1405// CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei1406// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {1407// CHECK1-NEXT: entry:1408// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81409// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 41410// CHECK1-NEXT: [[B:%.*]] = alloca i32, align 41411// CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 81412// CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 81413// CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 81414// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 81415// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 81416// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 81417// CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 81418// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81419// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81420// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 41421// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81422// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 41423// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 11424// CHECK1-NEXT: store i32 [[ADD]], ptr [[B]], align 41425// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 41426// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i641427// CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()1428// CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 81429// CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]1430// CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 21431// CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 81432// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 41433// CHECK1-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 41434// CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 81435// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 41436// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 601437// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]1438// CHECK1: omp_if.then:1439// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 01440// CHECK1-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]]1441// CHECK1-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 21442// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.5, i64 40, i1 false)1443// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01444// CHECK1-NEXT: store ptr [[THIS1]], ptr [[TMP10]], align 81445// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01446// CHECK1-NEXT: store ptr [[A]], ptr [[TMP11]], align 81447// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 01448// CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 81449// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 11450// CHECK1-NEXT: store i64 [[TMP6]], ptr [[TMP13]], align 81451// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 11452// CHECK1-NEXT: store i64 [[TMP6]], ptr [[TMP14]], align 81453// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 11454// CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 81455// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 21456// CHECK1-NEXT: store i64 2, ptr [[TMP16]], align 81457// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 21458// CHECK1-NEXT: store i64 2, ptr [[TMP17]], align 81459// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 21460// CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 81461// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 31462// CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP19]], align 81463// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 31464// CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP20]], align 81465// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 31466// CHECK1-NEXT: store ptr null, ptr [[TMP21]], align 81467// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 41468// CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP22]], align 81469// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 41470// CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP23]], align 81471// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 41472// CHECK1-NEXT: store i64 [[TMP9]], ptr [[TMP24]], align 81473// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 41474// CHECK1-NEXT: store ptr null, ptr [[TMP25]], align 81475// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01476// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01477// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 01478// CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 01479// CHECK1-NEXT: store i32 3, ptr [[TMP29]], align 41480// CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11481// CHECK1-NEXT: store i32 5, ptr [[TMP30]], align 41482// CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 21483// CHECK1-NEXT: store ptr [[TMP26]], ptr [[TMP31]], align 81484// CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 31485// CHECK1-NEXT: store ptr [[TMP27]], ptr [[TMP32]], align 81486// CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 41487// CHECK1-NEXT: store ptr [[TMP28]], ptr [[TMP33]], align 81488// CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 51489// CHECK1-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP34]], align 81490// CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 61491// CHECK1-NEXT: store ptr null, ptr [[TMP35]], align 81492// CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 71493// CHECK1-NEXT: store ptr null, ptr [[TMP36]], align 81494// CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 81495// CHECK1-NEXT: store i64 0, ptr [[TMP37]], align 81496// CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 91497// CHECK1-NEXT: store i64 0, ptr [[TMP38]], align 81498// CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 101499// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP39]], align 41500// CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 111501// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP40]], align 41502// CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 121503// CHECK1-NEXT: store i32 0, ptr [[TMP41]], align 41504// CHECK1-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.region_id, ptr [[KERNEL_ARGS]])1505// CHECK1-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 01506// CHECK1-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]1507// CHECK1: omp_offload.failed:1508// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR3]]1509// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]1510// CHECK1: omp_offload.cont:1511// CHECK1-NEXT: br label [[OMP_IF_END:%.*]]1512// CHECK1: omp_if.else:1513// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR3]]1514// CHECK1-NEXT: br label [[OMP_IF_END]]1515// CHECK1: omp_if.end:1516// CHECK1-NEXT: [[TMP44:%.*]] = mul nsw i64 1, [[TMP2]]1517// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP44]]1518// CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 11519// CHECK1-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 21520// CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i321521// CHECK1-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 41522// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]]1523// CHECK1-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 81524// CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP47]])1525// CHECK1-NEXT: ret i32 [[ADD3]]1526//1527//1528// CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici1529// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {1530// CHECK1-NEXT: entry:1531// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 41532// CHECK1-NEXT: [[A:%.*]] = alloca i32, align 41533// CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 21534// CHECK1-NEXT: [[AAA:%.*]] = alloca i8, align 11535// CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 41536// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 81537// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 81538// CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 81539// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 81540// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 81541// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 81542// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81543// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 41544// CHECK1-NEXT: store i32 0, ptr [[A]], align 41545// CHECK1-NEXT: store i16 0, ptr [[AA]], align 21546// CHECK1-NEXT: store i8 0, ptr [[AAA]], align 11547// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 41548// CHECK1-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 41549// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 81550// CHECK1-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 21551// CHECK1-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 21552// CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 81553// CHECK1-NEXT: [[TMP4:%.*]] = load i8, ptr [[AAA]], align 11554// CHECK1-NEXT: store i8 [[TMP4]], ptr [[AAA_CASTED]], align 11555// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[AAA_CASTED]], align 81556// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 41557// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 501558// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]1559// CHECK1: omp_if.then:1560// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01561// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP7]], align 81562// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01563// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP8]], align 81564// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 01565// CHECK1-NEXT: store ptr null, ptr [[TMP9]], align 81566// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 11567// CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP10]], align 81568// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 11569// CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP11]], align 81570// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 11571// CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 81572// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 21573// CHECK1-NEXT: store i64 [[TMP5]], ptr [[TMP13]], align 81574// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 21575// CHECK1-NEXT: store i64 [[TMP5]], ptr [[TMP14]], align 81576// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 21577// CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 81578// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 31579// CHECK1-NEXT: store ptr [[B]], ptr [[TMP16]], align 81580// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 31581// CHECK1-NEXT: store ptr [[B]], ptr [[TMP17]], align 81582// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 31583// CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 81584// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01585// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01586// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 01587// CHECK1-NEXT: store i32 3, ptr [[TMP21]], align 41588// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11589// CHECK1-NEXT: store i32 4, ptr [[TMP22]], align 41590// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 21591// CHECK1-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 81592// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 31593// CHECK1-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 81594// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 41595// CHECK1-NEXT: store ptr @.offload_sizes.7, ptr [[TMP25]], align 81596// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 51597// CHECK1-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP26]], align 81598// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 61599// CHECK1-NEXT: store ptr null, ptr [[TMP27]], align 81600// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 71601// CHECK1-NEXT: store ptr null, ptr [[TMP28]], align 81602// CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 81603// CHECK1-NEXT: store i64 0, ptr [[TMP29]], align 81604// CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 91605// CHECK1-NEXT: store i64 0, ptr [[TMP30]], align 81606// CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 101607// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP31]], align 41608// CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 111609// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP32]], align 41610// CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 121611// CHECK1-NEXT: store i32 0, ptr [[TMP33]], align 41612// CHECK1-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.region_id, ptr [[KERNEL_ARGS]])1613// CHECK1-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 01614// CHECK1-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]1615// CHECK1: omp_offload.failed:1616// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR3]]1617// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]1618// CHECK1: omp_offload.cont:1619// CHECK1-NEXT: br label [[OMP_IF_END:%.*]]1620// CHECK1: omp_if.else:1621// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR3]]1622// CHECK1-NEXT: br label [[OMP_IF_END]]1623// CHECK1: omp_if.end:1624// CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[A]], align 41625// CHECK1-NEXT: ret i32 [[TMP36]]1626//1627//1628// CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i1629// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {1630// CHECK1-NEXT: entry:1631// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 41632// CHECK1-NEXT: [[A:%.*]] = alloca i32, align 41633// CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 21634// CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 41635// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 81636// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 81637// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 81638// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 81639// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 81640// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81641// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 41642// CHECK1-NEXT: store i32 0, ptr [[A]], align 41643// CHECK1-NEXT: store i16 0, ptr [[AA]], align 21644// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 41645// CHECK1-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 41646// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 81647// CHECK1-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 21648// CHECK1-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 21649// CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 81650// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 41651// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 401652// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]1653// CHECK1: omp_if.then:1654// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01655// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP5]], align 81656// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01657// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP6]], align 81658// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 01659// CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 81660// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 11661// CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP8]], align 81662// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 11663// CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP9]], align 81664// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 11665// CHECK1-NEXT: store ptr null, ptr [[TMP10]], align 81666// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 21667// CHECK1-NEXT: store ptr [[B]], ptr [[TMP11]], align 81668// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 21669// CHECK1-NEXT: store ptr [[B]], ptr [[TMP12]], align 81670// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 21671// CHECK1-NEXT: store ptr null, ptr [[TMP13]], align 81672// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01673// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01674// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 01675// CHECK1-NEXT: store i32 3, ptr [[TMP16]], align 41676// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11677// CHECK1-NEXT: store i32 3, ptr [[TMP17]], align 41678// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 21679// CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 81680// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 31681// CHECK1-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 81682// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 41683// CHECK1-NEXT: store ptr @.offload_sizes.9, ptr [[TMP20]], align 81684// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 51685// CHECK1-NEXT: store ptr @.offload_maptypes.10, ptr [[TMP21]], align 81686// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 61687// CHECK1-NEXT: store ptr null, ptr [[TMP22]], align 81688// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 71689// CHECK1-NEXT: store ptr null, ptr [[TMP23]], align 81690// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 81691// CHECK1-NEXT: store i64 0, ptr [[TMP24]], align 81692// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 91693// CHECK1-NEXT: store i64 0, ptr [[TMP25]], align 81694// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 101695// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP26]], align 41696// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 111697// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP27]], align 41698// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 121699// CHECK1-NEXT: store i32 0, ptr [[TMP28]], align 41700// CHECK1-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.region_id, ptr [[KERNEL_ARGS]])1701// CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 01702// CHECK1-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]1703// CHECK1: omp_offload.failed:1704// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]]1705// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]1706// CHECK1: omp_offload.cont:1707// CHECK1-NEXT: br label [[OMP_IF_END:%.*]]1708// CHECK1: omp_if.else:1709// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]]1710// CHECK1-NEXT: br label [[OMP_IF_END]]1711// CHECK1: omp_if.end:1712// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[A]], align 41713// CHECK1-NEXT: ret i32 [[TMP31]]1714//1715//1716// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l2321717// CHECK1-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {1718// CHECK1-NEXT: entry:1719// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81720// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 81721// CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 81722// CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 81723// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 81724// CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 81725// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81726// CHECK1-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 81727// CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 81728// CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 81729// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 81730// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81731// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 81732// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 81733// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 81734// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 41735// CHECK1-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 41736// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 81737// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.omp_outlined, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]])1738// CHECK1-NEXT: ret void1739//1740//1741// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.omp_outlined1742// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {1743// CHECK1-NEXT: entry:1744// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81745// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81746// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81747// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 81748// CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 81749// CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 81750// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 81751// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 81752// CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 81753// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 81754// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 81755// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 81756// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41757// CHECK1-NEXT: [[IT:%.*]] = alloca i64, align 81758// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81759// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81760// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81761// CHECK1-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 81762// CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 81763// CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 81764// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 81765// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81766// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 81767// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 81768// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 81769// CHECK1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 81770// CHECK1-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 81771// CHECK1-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 81772// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41773// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81774// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 41775// CHECK1-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)1776// CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_UB]], align 81777// CHECK1-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 31778// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1779// CHECK1: cond.true:1780// CHECK1-NEXT: br label [[COND_END:%.*]]1781// CHECK1: cond.false:1782// CHECK1-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 81783// CHECK1-NEXT: br label [[COND_END]]1784// CHECK1: cond.end:1785// CHECK1-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]1786// CHECK1-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 81787// CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_LB]], align 81788// CHECK1-NEXT: store i64 [[TMP8]], ptr [[DOTOMP_IV]], align 81789// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1790// CHECK1: omp.inner.for.cond:1791// CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 81792// CHECK1-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 81793// CHECK1-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]1794// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1795// CHECK1: omp.inner.for.body:1796// CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 81797// CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 4001798// CHECK1-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]1799// CHECK1-NEXT: store i64 [[SUB]], ptr [[IT]], align 81800// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 41801// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double1802// CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+001803// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 01804// CHECK1-NEXT: store double [[ADD]], ptr [[A]], align 81805// CHECK1-NEXT: [[A4:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 01806// CHECK1-NEXT: [[TMP13:%.*]] = load double, ptr [[A4]], align 81807// CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+001808// CHECK1-NEXT: store double [[INC]], ptr [[A4]], align 81809// CHECK1-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i161810// CHECK1-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]1811// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP14]]1812// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 11813// CHECK1-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 21814// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1815// CHECK1: omp.body.continue:1816// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1817// CHECK1: omp.inner.for.inc:1818// CHECK1-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 81819// CHECK1-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 11820// CHECK1-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 81821// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]1822// CHECK1: omp.inner.for.end:1823// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]1824// CHECK1: omp.loop.exit:1825// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])1826// CHECK1-NEXT: ret void1827//1828//1829// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l2141830// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {1831// CHECK1-NEXT: entry:1832// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 81833// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 81834// CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 81835// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 81836// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 81837// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 81838// CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 81839// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 81840// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 81841// CHECK1-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 81842// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 81843// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 81844// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 41845// CHECK1-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 41846// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 81847// CHECK1-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 21848// CHECK1-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 21849// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 81850// CHECK1-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 11851// CHECK1-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 11852// CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[AAA_CASTED]], align 81853// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], ptr [[TMP0]])1854// CHECK1-NEXT: ret void1855//1856//1857// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.omp_outlined1858// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {1859// CHECK1-NEXT: entry:1860// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81861// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81862// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 81863// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 81864// CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 81865// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 81866// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41867// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 41868// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81869// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81870// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 81871// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 81872// CHECK1-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 81873// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 81874// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 81875// CHECK1-NEXT: ret void1876//1877//1878// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l1971879// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {1880// CHECK1-NEXT: entry:1881// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 81882// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 81883// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 81884// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 81885// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 81886// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 81887// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 81888// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 81889// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 81890// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 41891// CHECK1-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 41892// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 81893// CHECK1-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 21894// CHECK1-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 21895// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 81896// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]])1897// CHECK1-NEXT: ret void1898//1899//1900// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.omp_outlined1901// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {1902// CHECK1-NEXT: entry:1903// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81904// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81905// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 81906// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 81907// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 81908// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 81909// CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 81910// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 81911// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 81912// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 81913// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41914// CHECK1-NEXT: [[I:%.*]] = alloca i64, align 81915// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81916// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81917// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 81918// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 81919// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 81920// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 81921// CHECK1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 81922// CHECK1-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 81923// CHECK1-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 81924// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41925// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81926// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 41927// CHECK1-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)1928// CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 81929// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 61930// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1931// CHECK1: cond.true:1932// CHECK1-NEXT: br label [[COND_END:%.*]]1933// CHECK1: cond.false:1934// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 81935// CHECK1-NEXT: br label [[COND_END]]1936// CHECK1: cond.end:1937// CHECK1-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]1938// CHECK1-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 81939// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 81940// CHECK1-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 81941// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1942// CHECK1: omp.inner.for.cond:1943// CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 81944// CHECK1-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 81945// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]1946// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1947// CHECK1: omp.inner.for.body:1948// CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 81949// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 31950// CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]1951// CHECK1-NEXT: store i64 [[ADD]], ptr [[I]], align 81952// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 41953// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 11954// CHECK1-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 41955// CHECK1-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 21956// CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i321957// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 11958// CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i161959// CHECK1-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 21960// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 21961// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 41962// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 11963// CHECK1-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 41964// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1965// CHECK1: omp.body.continue:1966// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1967// CHECK1: omp.inner.for.inc:1968// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 81969// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 11970// CHECK1-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 81971// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]1972// CHECK1: omp.inner.for.end:1973// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]1974// CHECK1: omp.loop.exit:1975// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])1976// CHECK1-NEXT: ret void1977//1978//1979// CHECK3-LABEL: define {{[^@]+}}@_Z7get_valv1980// CHECK3-SAME: () #[[ATTR0:[0-9]+]] {1981// CHECK3-NEXT: entry:1982// CHECK3-NEXT: ret i64 01983//1984//1985// CHECK3-LABEL: define {{[^@]+}}@_Z3fooi1986// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {1987// CHECK3-NEXT: entry:1988// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 41989// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 41990// CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 21991// CHECK3-NEXT: [[B:%.*]] = alloca [10 x float], align 41992// CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 41993// CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 41994// CHECK3-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 81995// CHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 41996// CHECK3-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 41997// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81998// CHECK3-NEXT: [[K:%.*]] = alloca i64, align 81999// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 42000// CHECK3-NEXT: [[LIN:%.*]] = alloca i32, align 42001// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 42002// CHECK3-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 42003// CHECK3-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 42004// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 42005// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 42006// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 42007// CHECK3-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 42008// CHECK3-NEXT: [[A_CASTED3:%.*]] = alloca i32, align 42009// CHECK3-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 42010// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x ptr], align 42011// CHECK3-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x ptr], align 42012// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x ptr], align 42013// CHECK3-NEXT: [[KERNEL_ARGS8:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 82014// CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 42015// CHECK3-NEXT: [[A_CASTED11:%.*]] = alloca i32, align 42016// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 42017// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x ptr], align 42018// CHECK3-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x ptr], align 42019// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x ptr], align 42020// CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 42021// CHECK3-NEXT: [[KERNEL_ARGS17:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 82022// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])2023// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 42024// CHECK3-NEXT: store i32 0, ptr [[A]], align 42025// CHECK3-NEXT: store i16 0, ptr [[AA]], align 22026// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 42027// CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()2028// CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 42029// CHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 42030// CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 42031// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 42032// CHECK3-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]2033// CHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 82034// CHECK3-NEXT: store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 42035// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 02036// CHECK3-NEXT: store i32 3, ptr [[TMP5]], align 42037// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12038// CHECK3-NEXT: store i32 0, ptr [[TMP6]], align 42039// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 22040// CHECK3-NEXT: store ptr null, ptr [[TMP7]], align 42041// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 32042// CHECK3-NEXT: store ptr null, ptr [[TMP8]], align 42043// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 42044// CHECK3-NEXT: store ptr null, ptr [[TMP9]], align 42045// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 52046// CHECK3-NEXT: store ptr null, ptr [[TMP10]], align 42047// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 62048// CHECK3-NEXT: store ptr null, ptr [[TMP11]], align 42049// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 72050// CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 42051// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 82052// CHECK3-NEXT: store i64 0, ptr [[TMP13]], align 82053// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 92054// CHECK3-NEXT: store i64 0, ptr [[TMP14]], align 82055// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 102056// CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP15]], align 42057// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 112058// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 42059// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 122060// CHECK3-NEXT: store i32 0, ptr [[TMP17]], align 42061// CHECK3-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, ptr [[KERNEL_ARGS]])2062// CHECK3-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 02063// CHECK3-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]2064// CHECK3: omp_offload.failed:2065// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR3:[0-9]+]]2066// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]2067// CHECK3: omp_offload.cont:2068// CHECK3-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()2069// CHECK3-NEXT: store i64 [[CALL]], ptr [[K]], align 82070// CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[A]], align 42071// CHECK3-NEXT: store i32 [[TMP20]], ptr [[A_CASTED]], align 42072// CHECK3-NEXT: [[TMP21:%.*]] = load i32, ptr [[A_CASTED]], align 42073// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP21]], ptr [[K]]) #[[ATTR3]]2074// CHECK3-NEXT: store i32 12, ptr [[LIN]], align 42075// CHECK3-NEXT: [[TMP22:%.*]] = load i16, ptr [[AA]], align 22076// CHECK3-NEXT: store i16 [[TMP22]], ptr [[AA_CASTED]], align 22077// CHECK3-NEXT: [[TMP23:%.*]] = load i32, ptr [[AA_CASTED]], align 42078// CHECK3-NEXT: [[TMP24:%.*]] = load i32, ptr [[LIN]], align 42079// CHECK3-NEXT: store i32 [[TMP24]], ptr [[LIN_CASTED]], align 42080// CHECK3-NEXT: [[TMP25:%.*]] = load i32, ptr [[LIN_CASTED]], align 42081// CHECK3-NEXT: [[TMP26:%.*]] = load i32, ptr [[A]], align 42082// CHECK3-NEXT: store i32 [[TMP26]], ptr [[A_CASTED2]], align 42083// CHECK3-NEXT: [[TMP27:%.*]] = load i32, ptr [[A_CASTED2]], align 42084// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 02085// CHECK3-NEXT: store i32 [[TMP23]], ptr [[TMP28]], align 42086// CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 02087// CHECK3-NEXT: store i32 [[TMP23]], ptr [[TMP29]], align 42088// CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 02089// CHECK3-NEXT: store ptr null, ptr [[TMP30]], align 42090// CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 12091// CHECK3-NEXT: store i32 [[TMP25]], ptr [[TMP31]], align 42092// CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 12093// CHECK3-NEXT: store i32 [[TMP25]], ptr [[TMP32]], align 42094// CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 12095// CHECK3-NEXT: store ptr null, ptr [[TMP33]], align 42096// CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 22097// CHECK3-NEXT: store i32 [[TMP27]], ptr [[TMP34]], align 42098// CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 22099// CHECK3-NEXT: store i32 [[TMP27]], ptr [[TMP35]], align 42100// CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 22101// CHECK3-NEXT: store ptr null, ptr [[TMP36]], align 42102// CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 02103// CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 02104// CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 02105// CHECK3-NEXT: [[TMP40:%.*]] = load i16, ptr [[AA]], align 22106// CHECK3-NEXT: store i16 [[TMP40]], ptr [[TMP39]], align 42107// CHECK3-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 12108// CHECK3-NEXT: [[TMP42:%.*]] = load i32, ptr [[LIN]], align 42109// CHECK3-NEXT: store i32 [[TMP42]], ptr [[TMP41]], align 42110// CHECK3-NEXT: [[TMP43:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 22111// CHECK3-NEXT: [[TMP44:%.*]] = load i32, ptr [[A]], align 42112// CHECK3-NEXT: store i32 [[TMP44]], ptr [[TMP43]], align 42113// CHECK3-NEXT: [[TMP45:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, ptr @.omp_task_entry., i64 -1)2114// CHECK3-NEXT: [[TMP46:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP45]], i32 0, i32 02115// CHECK3-NEXT: [[TMP47:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP46]], i32 0, i32 02116// CHECK3-NEXT: [[TMP48:%.*]] = load ptr, ptr [[TMP47]], align 42117// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP48]], ptr align 4 [[AGG_CAPTURED]], i32 12, i1 false)2118// CHECK3-NEXT: [[TMP49:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP45]], i32 0, i32 12119// CHECK3-NEXT: [[TMP50:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP49]], i32 0, i32 02120// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP50]], ptr align 4 @.offload_sizes, i32 24, i1 false)2121// CHECK3-NEXT: [[TMP51:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP49]], i32 0, i32 12122// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP51]], ptr align 4 [[TMP37]], i32 12, i1 false)2123// CHECK3-NEXT: [[TMP52:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP49]], i32 0, i32 22124// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP52]], ptr align 4 [[TMP38]], i32 12, i1 false)2125// CHECK3-NEXT: [[TMP53:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP49]], i32 0, i32 32126// CHECK3-NEXT: [[TMP54:%.*]] = load i16, ptr [[AA]], align 22127// CHECK3-NEXT: store i16 [[TMP54]], ptr [[TMP53]], align 42128// CHECK3-NEXT: [[TMP55:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB2]], i32 [[TMP0]], ptr [[TMP45]])2129// CHECK3-NEXT: [[TMP56:%.*]] = load i32, ptr [[A]], align 42130// CHECK3-NEXT: store i32 [[TMP56]], ptr [[A_CASTED3]], align 42131// CHECK3-NEXT: [[TMP57:%.*]] = load i32, ptr [[A_CASTED3]], align 42132// CHECK3-NEXT: [[TMP58:%.*]] = load i16, ptr [[AA]], align 22133// CHECK3-NEXT: store i16 [[TMP58]], ptr [[AA_CASTED4]], align 22134// CHECK3-NEXT: [[TMP59:%.*]] = load i32, ptr [[AA_CASTED4]], align 42135// CHECK3-NEXT: [[TMP60:%.*]] = load i32, ptr [[N_ADDR]], align 42136// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP60]], 102137// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]2138// CHECK3: omp_if.then:2139// CHECK3-NEXT: [[TMP61:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 02140// CHECK3-NEXT: store i32 [[TMP57]], ptr [[TMP61]], align 42141// CHECK3-NEXT: [[TMP62:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 02142// CHECK3-NEXT: store i32 [[TMP57]], ptr [[TMP62]], align 42143// CHECK3-NEXT: [[TMP63:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 02144// CHECK3-NEXT: store ptr null, ptr [[TMP63]], align 42145// CHECK3-NEXT: [[TMP64:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 12146// CHECK3-NEXT: store i32 [[TMP59]], ptr [[TMP64]], align 42147// CHECK3-NEXT: [[TMP65:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 12148// CHECK3-NEXT: store i32 [[TMP59]], ptr [[TMP65]], align 42149// CHECK3-NEXT: [[TMP66:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 12150// CHECK3-NEXT: store ptr null, ptr [[TMP66]], align 42151// CHECK3-NEXT: [[TMP67:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 02152// CHECK3-NEXT: [[TMP68:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 02153// CHECK3-NEXT: [[TMP69:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 02154// CHECK3-NEXT: store i32 3, ptr [[TMP69]], align 42155// CHECK3-NEXT: [[TMP70:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 12156// CHECK3-NEXT: store i32 2, ptr [[TMP70]], align 42157// CHECK3-NEXT: [[TMP71:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 22158// CHECK3-NEXT: store ptr [[TMP67]], ptr [[TMP71]], align 42159// CHECK3-NEXT: [[TMP72:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 32160// CHECK3-NEXT: store ptr [[TMP68]], ptr [[TMP72]], align 42161// CHECK3-NEXT: [[TMP73:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 42162// CHECK3-NEXT: store ptr @.offload_sizes.1, ptr [[TMP73]], align 42163// CHECK3-NEXT: [[TMP74:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 52164// CHECK3-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP74]], align 42165// CHECK3-NEXT: [[TMP75:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 62166// CHECK3-NEXT: store ptr null, ptr [[TMP75]], align 42167// CHECK3-NEXT: [[TMP76:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 72168// CHECK3-NEXT: store ptr null, ptr [[TMP76]], align 42169// CHECK3-NEXT: [[TMP77:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 82170// CHECK3-NEXT: store i64 0, ptr [[TMP77]], align 82171// CHECK3-NEXT: [[TMP78:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 92172// CHECK3-NEXT: store i64 0, ptr [[TMP78]], align 82173// CHECK3-NEXT: [[TMP79:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 102174// CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP79]], align 42175// CHECK3-NEXT: [[TMP80:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 112176// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP80]], align 42177// CHECK3-NEXT: [[TMP81:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 122178// CHECK3-NEXT: store i32 0, ptr [[TMP81]], align 42179// CHECK3-NEXT: [[TMP82:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.region_id, ptr [[KERNEL_ARGS8]])2180// CHECK3-NEXT: [[TMP83:%.*]] = icmp ne i32 [[TMP82]], 02181// CHECK3-NEXT: br i1 [[TMP83]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]]2182// CHECK3: omp_offload.failed9:2183// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136(i32 [[TMP57]], i32 [[TMP59]]) #[[ATTR3]]2184// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT10]]2185// CHECK3: omp_offload.cont10:2186// CHECK3-NEXT: br label [[OMP_IF_END:%.*]]2187// CHECK3: omp_if.else:2188// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136(i32 [[TMP57]], i32 [[TMP59]]) #[[ATTR3]]2189// CHECK3-NEXT: br label [[OMP_IF_END]]2190// CHECK3: omp_if.end:2191// CHECK3-NEXT: [[TMP84:%.*]] = load i32, ptr [[A]], align 42192// CHECK3-NEXT: store i32 [[TMP84]], ptr [[DOTCAPTURE_EXPR_]], align 42193// CHECK3-NEXT: [[TMP85:%.*]] = load i32, ptr [[A]], align 42194// CHECK3-NEXT: store i32 [[TMP85]], ptr [[A_CASTED11]], align 42195// CHECK3-NEXT: [[TMP86:%.*]] = load i32, ptr [[A_CASTED11]], align 42196// CHECK3-NEXT: [[TMP87:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 42197// CHECK3-NEXT: store i32 [[TMP87]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 42198// CHECK3-NEXT: [[TMP88:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 42199// CHECK3-NEXT: [[TMP89:%.*]] = load i32, ptr [[N_ADDR]], align 42200// CHECK3-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP89]], 202201// CHECK3-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE20:%.*]]2202// CHECK3: omp_if.then13:2203// CHECK3-NEXT: [[TMP90:%.*]] = mul nuw i32 [[TMP1]], 42204// CHECK3-NEXT: [[TMP91:%.*]] = sext i32 [[TMP90]] to i642205// CHECK3-NEXT: [[TMP92:%.*]] = mul nuw i32 5, [[TMP3]]2206// CHECK3-NEXT: [[TMP93:%.*]] = mul nuw i32 [[TMP92]], 82207// CHECK3-NEXT: [[TMP94:%.*]] = sext i32 [[TMP93]] to i642208// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.3, i32 80, i1 false)2209// CHECK3-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 02210// CHECK3-NEXT: store i32 [[TMP86]], ptr [[TMP95]], align 42211// CHECK3-NEXT: [[TMP96:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 02212// CHECK3-NEXT: store i32 [[TMP86]], ptr [[TMP96]], align 42213// CHECK3-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 02214// CHECK3-NEXT: store ptr null, ptr [[TMP97]], align 42215// CHECK3-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 12216// CHECK3-NEXT: store ptr [[B]], ptr [[TMP98]], align 42217// CHECK3-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 12218// CHECK3-NEXT: store ptr [[B]], ptr [[TMP99]], align 42219// CHECK3-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 12220// CHECK3-NEXT: store ptr null, ptr [[TMP100]], align 42221// CHECK3-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 22222// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP101]], align 42223// CHECK3-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 22224// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP102]], align 42225// CHECK3-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 22226// CHECK3-NEXT: store ptr null, ptr [[TMP103]], align 42227// CHECK3-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 32228// CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP104]], align 42229// CHECK3-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 32230// CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP105]], align 42231// CHECK3-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 32232// CHECK3-NEXT: store i64 [[TMP91]], ptr [[TMP106]], align 42233// CHECK3-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 32234// CHECK3-NEXT: store ptr null, ptr [[TMP107]], align 42235// CHECK3-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 42236// CHECK3-NEXT: store ptr [[C]], ptr [[TMP108]], align 42237// CHECK3-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 42238// CHECK3-NEXT: store ptr [[C]], ptr [[TMP109]], align 42239// CHECK3-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 42240// CHECK3-NEXT: store ptr null, ptr [[TMP110]], align 42241// CHECK3-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 52242// CHECK3-NEXT: store i32 5, ptr [[TMP111]], align 42243// CHECK3-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 52244// CHECK3-NEXT: store i32 5, ptr [[TMP112]], align 42245// CHECK3-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 52246// CHECK3-NEXT: store ptr null, ptr [[TMP113]], align 42247// CHECK3-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 62248// CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP114]], align 42249// CHECK3-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 62250// CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP115]], align 42251// CHECK3-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 62252// CHECK3-NEXT: store ptr null, ptr [[TMP116]], align 42253// CHECK3-NEXT: [[TMP117:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 72254// CHECK3-NEXT: store ptr [[VLA1]], ptr [[TMP117]], align 42255// CHECK3-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 72256// CHECK3-NEXT: store ptr [[VLA1]], ptr [[TMP118]], align 42257// CHECK3-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 72258// CHECK3-NEXT: store i64 [[TMP94]], ptr [[TMP119]], align 42259// CHECK3-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 72260// CHECK3-NEXT: store ptr null, ptr [[TMP120]], align 42261// CHECK3-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 82262// CHECK3-NEXT: store ptr [[D]], ptr [[TMP121]], align 42263// CHECK3-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 82264// CHECK3-NEXT: store ptr [[D]], ptr [[TMP122]], align 42265// CHECK3-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 82266// CHECK3-NEXT: store ptr null, ptr [[TMP123]], align 42267// CHECK3-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 92268// CHECK3-NEXT: store i32 [[TMP88]], ptr [[TMP124]], align 42269// CHECK3-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 92270// CHECK3-NEXT: store i32 [[TMP88]], ptr [[TMP125]], align 42271// CHECK3-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 92272// CHECK3-NEXT: store ptr null, ptr [[TMP126]], align 42273// CHECK3-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 02274// CHECK3-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 02275// CHECK3-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 02276// CHECK3-NEXT: [[TMP130:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 02277// CHECK3-NEXT: store i32 3, ptr [[TMP130]], align 42278// CHECK3-NEXT: [[TMP131:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 12279// CHECK3-NEXT: store i32 10, ptr [[TMP131]], align 42280// CHECK3-NEXT: [[TMP132:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 22281// CHECK3-NEXT: store ptr [[TMP127]], ptr [[TMP132]], align 42282// CHECK3-NEXT: [[TMP133:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 32283// CHECK3-NEXT: store ptr [[TMP128]], ptr [[TMP133]], align 42284// CHECK3-NEXT: [[TMP134:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 42285// CHECK3-NEXT: store ptr [[TMP129]], ptr [[TMP134]], align 42286// CHECK3-NEXT: [[TMP135:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 52287// CHECK3-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP135]], align 42288// CHECK3-NEXT: [[TMP136:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 62289// CHECK3-NEXT: store ptr null, ptr [[TMP136]], align 42290// CHECK3-NEXT: [[TMP137:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 72291// CHECK3-NEXT: store ptr null, ptr [[TMP137]], align 42292// CHECK3-NEXT: [[TMP138:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 82293// CHECK3-NEXT: store i64 0, ptr [[TMP138]], align 82294// CHECK3-NEXT: [[TMP139:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 92295// CHECK3-NEXT: store i64 0, ptr [[TMP139]], align 82296// CHECK3-NEXT: [[TMP140:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 102297// CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP140]], align 42298// CHECK3-NEXT: [[TMP141:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 112299// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP141]], align 42300// CHECK3-NEXT: [[TMP142:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 122301// CHECK3-NEXT: store i32 0, ptr [[TMP142]], align 42302// CHECK3-NEXT: [[TMP143:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.region_id, ptr [[KERNEL_ARGS17]])2303// CHECK3-NEXT: [[TMP144:%.*]] = icmp ne i32 [[TMP143]], 02304// CHECK3-NEXT: br i1 [[TMP144]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]]2305// CHECK3: omp_offload.failed18:2306// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i32 [[TMP86]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP88]]) #[[ATTR3]]2307// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT19]]2308// CHECK3: omp_offload.cont19:2309// CHECK3-NEXT: br label [[OMP_IF_END21:%.*]]2310// CHECK3: omp_if.else20:2311// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i32 [[TMP86]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP88]]) #[[ATTR3]]2312// CHECK3-NEXT: br label [[OMP_IF_END21]]2313// CHECK3: omp_if.end21:2314// CHECK3-NEXT: [[TMP145:%.*]] = load i32, ptr [[A]], align 42315// CHECK3-NEXT: [[TMP146:%.*]] = load ptr, ptr [[SAVED_STACK]], align 42316// CHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP146]])2317// CHECK3-NEXT: ret i32 [[TMP145]]2318//2319//2320// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1032321// CHECK3-SAME: () #[[ATTR2:[0-9]+]] {2322// CHECK3-NEXT: entry:2323// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined)2324// CHECK3-NEXT: ret void2325//2326//2327// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined2328// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] {2329// CHECK3-NEXT: entry:2330// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 42331// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 42332// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 42333// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 42334// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 42335// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 42336// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42337// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42338// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 42339// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 42340// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 42341// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 42342// CHECK3-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 42343// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 42344// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 42345// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 42346// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 42347// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)2348// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42349// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 52350// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2351// CHECK3: cond.true:2352// CHECK3-NEXT: br label [[COND_END:%.*]]2353// CHECK3: cond.false:2354// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42355// CHECK3-NEXT: br label [[COND_END]]2356// CHECK3: cond.end:2357// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]2358// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 42359// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42360// CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 42361// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]2362// CHECK3: omp.inner.for.cond:2363// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42364// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42365// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]2366// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2367// CHECK3: omp.inner.for.body:2368// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42369// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 52370// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]2371// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 42372// CHECK3-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(ptr @[[GLOB2]], i32 [[TMP1]], i32 2)2373// CHECK3-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 02374// CHECK3-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]2375// CHECK3: .cancel.exit:2376// CHECK3-NEXT: br label [[CANCEL_EXIT:%.*]]2377// CHECK3: .cancel.continue:2378// CHECK3-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(ptr @[[GLOB2]], i32 [[TMP1]], i32 2)2379// CHECK3-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 02380// CHECK3-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]2381// CHECK3: .cancel.exit2:2382// CHECK3-NEXT: br label [[CANCEL_EXIT]]2383// CHECK3: .cancel.continue3:2384// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]2385// CHECK3: omp.body.continue:2386// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]2387// CHECK3: omp.inner.for.inc:2388// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42389// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 12390// CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 42391// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]2392// CHECK3: omp.inner.for.end:2393// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]2394// CHECK3: omp.loop.exit:2395// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])2396// CHECK3-NEXT: br label [[CANCEL_CONT:%.*]]2397// CHECK3: cancel.cont:2398// CHECK3-NEXT: ret void2399// CHECK3: cancel.exit:2400// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])2401// CHECK3-NEXT: br label [[CANCEL_CONT]]2402//2403//2404// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1102405// CHECK3-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR2]] {2406// CHECK3-NEXT: entry:2407// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 42408// CHECK3-NEXT: [[K_ADDR:%.*]] = alloca ptr, align 42409// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 42410// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 42411// CHECK3-NEXT: store ptr [[K]], ptr [[K_ADDR]], align 42412// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[K_ADDR]], align 42413// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 42414// CHECK3-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 42415// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 42416// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined, i32 [[TMP2]], ptr [[TMP0]])2417// CHECK3-NEXT: ret void2418//2419//2420// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined2421// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR2]] {2422// CHECK3-NEXT: entry:2423// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 42424// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 42425// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 42426// CHECK3-NEXT: [[K_ADDR:%.*]] = alloca ptr, align 42427// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 42428// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 42429// CHECK3-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 82430// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 42431// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 42432// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42433// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42434// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 42435// CHECK3-NEXT: [[K1:%.*]] = alloca i64, align 82436// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 42437// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 42438// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 42439// CHECK3-NEXT: store ptr [[K]], ptr [[K_ADDR]], align 42440// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[K_ADDR]], align 42441// CHECK3-NEXT: [[TMP1:%.*]] = load i64, ptr [[TMP0]], align 82442// CHECK3-NEXT: store i64 [[TMP1]], ptr [[DOTLINEAR_START]], align 82443// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 42444// CHECK3-NEXT: store i32 8, ptr [[DOTOMP_UB]], align 42445// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 42446// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 42447// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 42448// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 42449// CHECK3-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP3]])2450// CHECK3-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 35, i32 0, i32 8, i32 1, i32 1)2451// CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]]2452// CHECK3: omp.dispatch.cond:2453// CHECK3-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB2]], i32 [[TMP3]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])2454// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 02455// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]2456// CHECK3: omp.dispatch.body:2457// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42458// CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 42459// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]2460// CHECK3: omp.inner.for.cond:2461// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13:![0-9]+]]2462// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP13]]2463// CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]2464// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2465// CHECK3: omp.inner.for.body:2466// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]2467// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 12468// CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]2469// CHECK3-NEXT: store i32 [[SUB]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]]2470// CHECK3-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP13]]2471// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]2472// CHECK3-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 32473// CHECK3-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i642474// CHECK3-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]]2475// CHECK3-NEXT: store i64 [[ADD]], ptr [[K1]], align 8, !llvm.access.group [[ACC_GRP13]]2476// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP13]]2477// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 12478// CHECK3-NEXT: store i32 [[ADD3]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP13]]2479// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]2480// CHECK3: omp.body.continue:2481// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]2482// CHECK3: omp.inner.for.inc:2483// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]2484// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 12485// CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]2486// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]2487// CHECK3: omp.inner.for.end:2488// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]2489// CHECK3: omp.dispatch.inc:2490// CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]2491// CHECK3: omp.dispatch.end:2492// CHECK3-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB2]], i32 [[TMP3]])2493// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 42494// CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 02495// CHECK3-NEXT: br i1 [[TMP14]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]2496// CHECK3: .omp.linear.pu:2497// CHECK3-NEXT: [[TMP15:%.*]] = load i64, ptr [[K1]], align 82498// CHECK3-NEXT: store i64 [[TMP15]], ptr [[TMP0]], align 82499// CHECK3-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]2500// CHECK3: .omp.linear.pu.done:2501// CHECK3-NEXT: ret void2502//2503//2504// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1282505// CHECK3-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] {2506// CHECK3-NEXT: entry:2507// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 42508// CHECK3-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 42509// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 42510// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 42511// CHECK3-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 42512// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 42513// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 42514// CHECK3-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 42515// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 42516// CHECK3-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 22517// CHECK3-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 22518// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 42519// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 42520// CHECK3-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 42521// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[LIN_CASTED]], align 42522// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 42523// CHECK3-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 42524// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[A_CASTED]], align 42525// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.omp_outlined, i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])2526// CHECK3-NEXT: ret void2527//2528//2529// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.omp_outlined2530// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] {2531// CHECK3-NEXT: entry:2532// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 42533// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 42534// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 42535// CHECK3-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 42536// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 42537// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 82538// CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 42539// CHECK3-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 42540// CHECK3-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 42541// CHECK3-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 82542// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 82543// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 82544// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 82545// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42546// CHECK3-NEXT: [[IT:%.*]] = alloca i64, align 82547// CHECK3-NEXT: [[LIN2:%.*]] = alloca i32, align 42548// CHECK3-NEXT: [[A3:%.*]] = alloca i32, align 42549// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 42550// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 42551// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 42552// CHECK3-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 42553// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 42554// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 42555// CHECK3-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 42556// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 42557// CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 42558// CHECK3-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()2559// CHECK3-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 82560// CHECK3-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 82561// CHECK3-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 82562// CHECK3-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 82563// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 42564// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 42565// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 42566// CHECK3-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP3]])2567// CHECK3-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)2568// CHECK3-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 82569// CHECK3-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 32570// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2571// CHECK3: cond.true:2572// CHECK3-NEXT: br label [[COND_END:%.*]]2573// CHECK3: cond.false:2574// CHECK3-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 82575// CHECK3-NEXT: br label [[COND_END]]2576// CHECK3: cond.end:2577// CHECK3-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]2578// CHECK3-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 82579// CHECK3-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 82580// CHECK3-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 82581// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]2582// CHECK3: omp.inner.for.cond:2583// CHECK3-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82584// CHECK3-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 82585// CHECK3-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]2586// CHECK3-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2587// CHECK3: omp.inner.for.body:2588// CHECK3-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82589// CHECK3-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 4002590// CHECK3-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]2591// CHECK3-NEXT: store i64 [[SUB]], ptr [[IT]], align 82592// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 42593// CHECK3-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i642594// CHECK3-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82595// CHECK3-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 82596// CHECK3-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]]2597// CHECK3-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]]2598// CHECK3-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i322599// CHECK3-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 42600// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 42601// CHECK3-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i642602// CHECK3-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82603// CHECK3-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 82604// CHECK3-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]]2605// CHECK3-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]]2606// CHECK3-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i322607// CHECK3-NEXT: store i32 [[CONV10]], ptr [[A3]], align 42608// CHECK3-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 22609// CHECK3-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i322610// CHECK3-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 12611// CHECK3-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i162612// CHECK3-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 22613// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]2614// CHECK3: omp.body.continue:2615// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]2616// CHECK3: omp.inner.for.inc:2617// CHECK3-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 82618// CHECK3-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 12619// CHECK3-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 82620// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]2621// CHECK3: omp.inner.for.end:2622// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]2623// CHECK3: omp.loop.exit:2624// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]])2625// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 42626// CHECK3-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 02627// CHECK3-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]2628// CHECK3: .omp.linear.pu:2629// CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[LIN2]], align 42630// CHECK3-NEXT: store i32 [[TMP20]], ptr [[LIN_ADDR]], align 42631// CHECK3-NEXT: [[TMP21:%.*]] = load i32, ptr [[A3]], align 42632// CHECK3-NEXT: store i32 [[TMP21]], ptr [[A_ADDR]], align 42633// CHECK3-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]2634// CHECK3: .omp.linear.pu.done:2635// CHECK3-NEXT: ret void2636//2637//2638// CHECK3-LABEL: define {{[^@]+}}@.omp_task_privates_map.2639// CHECK3-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] {2640// CHECK3-NEXT: entry:2641// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 42642// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 42643// CHECK3-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 42644// CHECK3-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 42645// CHECK3-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 42646// CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 42647// CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 42648// CHECK3-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 42649// CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3]], align 42650// CHECK3-NEXT: store ptr [[TMP4]], ptr [[DOTADDR4]], align 42651// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 42652// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP5]], i32 0, i32 02653// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTADDR4]], align 42654// CHECK3-NEXT: store ptr [[TMP6]], ptr [[TMP7]], align 42655// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 12656// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTADDR2]], align 42657// CHECK3-NEXT: store ptr [[TMP8]], ptr [[TMP9]], align 42658// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 22659// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTADDR3]], align 42660// CHECK3-NEXT: store ptr [[TMP10]], ptr [[TMP11]], align 42661// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 32662// CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTADDR1]], align 42663// CHECK3-NEXT: store ptr [[TMP12]], ptr [[TMP13]], align 42664// CHECK3-NEXT: ret void2665//2666//2667// CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry.2668// CHECK3-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] {2669// CHECK3-NEXT: entry:2670// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 42671// CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 42672// CHECK3-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 42673// CHECK3-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 42674// CHECK3-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 42675// CHECK3-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 42676// CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 42677// CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 42678// CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca ptr, align 42679// CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca ptr, align 42680// CHECK3-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 82681// CHECK3-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 42682// CHECK3-NEXT: [[LIN_CASTED_I:%.*]] = alloca i32, align 42683// CHECK3-NEXT: [[A_CASTED_I:%.*]] = alloca i32, align 42684// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i32, align 42685// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 42686// CHECK3-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 42687// CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 42688// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 42689// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 42690// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 02691// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 22692// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 02693// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 42694// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 12695// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])2696// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])2697// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])2698// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])2699// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META25:![0-9]+]]2700// CHECK3-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 4, !noalias [[META25]]2701// CHECK3-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias [[META25]]2702// CHECK3-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias [[META25]]2703// CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 4, !noalias [[META25]]2704// CHECK3-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 4, !noalias [[META25]]2705// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias [[META25]]2706// CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias [[META25]]2707// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias [[META25]]2708// CHECK3-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]2709// CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias [[META25]]2710// CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias [[META25]]2711// CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias [[META25]]2712// CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias [[META25]]2713// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP9]], i32 0, i32 12714// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 22715// CHECK3-NEXT: store i32 3, ptr [[KERNEL_ARGS_I]], align 4, !noalias [[META25]]2716// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 12717// CHECK3-NEXT: store i32 3, ptr [[TMP18]], align 4, !noalias [[META25]]2718// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 22719// CHECK3-NEXT: store ptr [[TMP13]], ptr [[TMP19]], align 4, !noalias [[META25]]2720// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 32721// CHECK3-NEXT: store ptr [[TMP14]], ptr [[TMP20]], align 4, !noalias [[META25]]2722// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 42723// CHECK3-NEXT: store ptr [[TMP15]], ptr [[TMP21]], align 4, !noalias [[META25]]2724// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 52725// CHECK3-NEXT: store ptr @.offload_maptypes, ptr [[TMP22]], align 4, !noalias [[META25]]2726// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 62727// CHECK3-NEXT: store ptr null, ptr [[TMP23]], align 4, !noalias [[META25]]2728// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 72729// CHECK3-NEXT: store ptr null, ptr [[TMP24]], align 4, !noalias [[META25]]2730// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 82731// CHECK3-NEXT: store i64 0, ptr [[TMP25]], align 8, !noalias [[META25]]2732// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 92733// CHECK3-NEXT: store i64 1, ptr [[TMP26]], align 8, !noalias [[META25]]2734// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 102735// CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP27]], align 4, !noalias [[META25]]2736// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 112737// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4, !noalias [[META25]]2738// CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 122739// CHECK3-NEXT: store i32 0, ptr [[TMP29]], align 4, !noalias [[META25]]2740// CHECK3-NEXT: [[TMP30:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.region_id, ptr [[KERNEL_ARGS_I]])2741// CHECK3-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 02742// CHECK3-NEXT: br i1 [[TMP31]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]]2743// CHECK3: omp_offload.failed.i:2744// CHECK3-NEXT: [[TMP32:%.*]] = load i16, ptr [[TMP12]], align 22745// CHECK3-NEXT: store i16 [[TMP32]], ptr [[AA_CASTED_I]], align 2, !noalias [[META25]]2746// CHECK3-NEXT: [[TMP33:%.*]] = load i32, ptr [[AA_CASTED_I]], align 4, !noalias [[META25]]2747// CHECK3-NEXT: [[TMP34:%.*]] = load i32, ptr [[TMP16]], align 42748// CHECK3-NEXT: store i32 [[TMP34]], ptr [[LIN_CASTED_I]], align 4, !noalias [[META25]]2749// CHECK3-NEXT: [[TMP35:%.*]] = load i32, ptr [[LIN_CASTED_I]], align 4, !noalias [[META25]]2750// CHECK3-NEXT: [[TMP36:%.*]] = load i32, ptr [[TMP17]], align 42751// CHECK3-NEXT: store i32 [[TMP36]], ptr [[A_CASTED_I]], align 4, !noalias [[META25]]2752// CHECK3-NEXT: [[TMP37:%.*]] = load i32, ptr [[A_CASTED_I]], align 4, !noalias [[META25]]2753// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128(i32 [[TMP33]], i32 [[TMP35]], i32 [[TMP37]]) #[[ATTR3]]2754// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__EXIT]]2755// CHECK3: .omp_outlined..exit:2756// CHECK3-NEXT: ret i32 02757//2758//2759// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1362760// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {2761// CHECK3-NEXT: entry:2762// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 42763// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 42764// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 42765// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 42766// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 42767// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 42768// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 42769// CHECK3-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 42770// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 42771// CHECK3-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 22772// CHECK3-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 22773// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 42774// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined, i32 [[TMP1]], i32 [[TMP3]])2775// CHECK3-NEXT: ret void2776//2777//2778// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined2779// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {2780// CHECK3-NEXT: entry:2781// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 42782// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 42783// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 42784// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 42785// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 42786// CHECK3-NEXT: [[TMP:%.*]] = alloca i16, align 22787// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 42788// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 42789// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42790// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42791// CHECK3-NEXT: [[IT:%.*]] = alloca i16, align 22792// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 42793// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 42794// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 42795// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 42796// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 42797// CHECK3-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 42798// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 42799// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 42800// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 42801// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 42802// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)2803// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42804// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 32805// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2806// CHECK3: cond.true:2807// CHECK3-NEXT: br label [[COND_END:%.*]]2808// CHECK3: cond.false:2809// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42810// CHECK3-NEXT: br label [[COND_END]]2811// CHECK3: cond.end:2812// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]2813// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 42814// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42815// CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 42816// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]2817// CHECK3: omp.inner.for.cond:2818// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42819// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42820// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]2821// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2822// CHECK3: omp.inner.for.body:2823// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42824// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 42825// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]2826// CHECK3-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i162827// CHECK3-NEXT: store i16 [[CONV]], ptr [[IT]], align 22828// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 42829// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 12830// CHECK3-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 42831// CHECK3-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 22832// CHECK3-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i322833// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 12834// CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i162835// CHECK3-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 22836// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]2837// CHECK3: omp.body.continue:2838// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]2839// CHECK3: omp.inner.for.inc:2840// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42841// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 12842// CHECK3-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 42843// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]2844// CHECK3: omp.inner.for.end:2845// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]2846// CHECK3: omp.loop.exit:2847// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])2848// CHECK3-NEXT: ret void2849//2850//2851// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1602852// CHECK3-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {2853// CHECK3-NEXT: entry:2854// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 42855// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 42856// CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 42857// CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 42858// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 42859// CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 42860// CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 42861// CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 42862// CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 42863// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 42864// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 42865// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 42866// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 42867// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 42868// CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 42869// CHECK3-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 42870// CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 42871// CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 42872// CHECK3-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 42873// CHECK3-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 42874// CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 42875// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 42876// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 42877// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 42878// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 42879// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 42880// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 42881// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 42882// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 42883// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 42884// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 42885// CHECK3-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 42886// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 42887// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 42888// CHECK3-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 42889// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 42890// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i32 [[TMP11]])2891// CHECK3-NEXT: ret void2892//2893//2894// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined2895// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {2896// CHECK3-NEXT: entry:2897// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 42898// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 42899// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 42900// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 42901// CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 42902// CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 42903// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 42904// CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 42905// CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 42906// CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 42907// CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 42908// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 42909// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 42910// CHECK3-NEXT: [[TMP:%.*]] = alloca i8, align 12911// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 42912// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 42913// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42914// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42915// CHECK3-NEXT: [[IT:%.*]] = alloca i8, align 12916// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 42917// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 42918// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 42919// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 42920// CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 42921// CHECK3-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 42922// CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 42923// CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 42924// CHECK3-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 42925// CHECK3-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 42926// CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 42927// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 42928// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 42929// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 42930// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 42931// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 42932// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 42933// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 42934// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 42935// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 42936// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 42937// CHECK3-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 42938// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 42939// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 42940// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 42941// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 42942// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 42943// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])2944// CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]]2945// CHECK3: omp.dispatch.cond:2946// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42947// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 252948// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2949// CHECK3: cond.true:2950// CHECK3-NEXT: br label [[COND_END:%.*]]2951// CHECK3: cond.false:2952// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42953// CHECK3-NEXT: br label [[COND_END]]2954// CHECK3: cond.end:2955// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]2956// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 42957// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42958// CHECK3-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 42959// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42960// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42961// CHECK3-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]2962// CHECK3-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]2963// CHECK3: omp.dispatch.body:2964// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]2965// CHECK3: omp.inner.for.cond:2966// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42967// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42968// CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]2969// CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2970// CHECK3: omp.inner.for.body:2971// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42972// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 12973// CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]2974// CHECK3-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i82975// CHECK3-NEXT: store i8 [[CONV]], ptr [[IT]], align 12976// CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 42977// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 12978// CHECK3-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 42979// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 22980// CHECK3-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 42981// CHECK3-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double2982// CHECK3-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+002983// CHECK3-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float2984// CHECK3-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 42985// CHECK3-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 32986// CHECK3-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 42987// CHECK3-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double2988// CHECK3-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+002989// CHECK3-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float2990// CHECK3-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 42991// CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 12992// CHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i32 0, i32 22993// CHECK3-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 82994// CHECK3-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+002995// CHECK3-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 82996// CHECK3-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]2997// CHECK3-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP23]]2998// CHECK3-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i32 32999// CHECK3-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 83000// CHECK3-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+003001// CHECK3-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 83002// CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 03003// CHECK3-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 43004// CHECK3-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 13005// CHECK3-NEXT: store i64 [[ADD20]], ptr [[X]], align 43006// CHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 13007// CHECK3-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 43008// CHECK3-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i323009// CHECK3-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 13010// CHECK3-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i83011// CHECK3-NEXT: store i8 [[CONV23]], ptr [[Y]], align 43012// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]3013// CHECK3: omp.body.continue:3014// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]3015// CHECK3: omp.inner.for.inc:3016// CHECK3-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43017// CHECK3-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 13018// CHECK3-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 43019// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]3020// CHECK3: omp.inner.for.end:3021// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]3022// CHECK3: omp.dispatch.inc:3023// CHECK3-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 43024// CHECK3-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 43025// CHECK3-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]3026// CHECK3-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 43027// CHECK3-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43028// CHECK3-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 43029// CHECK3-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]3030// CHECK3-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 43031// CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]3032// CHECK3: omp.dispatch.end:3033// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]])3034// CHECK3-NEXT: ret void3035//3036//3037// CHECK3-LABEL: define {{[^@]+}}@_Z3bari3038// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {3039// CHECK3-NEXT: entry:3040// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 43041// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 43042// CHECK3-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 43043// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 43044// CHECK3-NEXT: store i32 0, ptr [[A]], align 43045// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 43046// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]])3047// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 43048// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]3049// CHECK3-NEXT: store i32 [[ADD]], ptr [[A]], align 43050// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 43051// CHECK3-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]])3052// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 43053// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]3054// CHECK3-NEXT: store i32 [[ADD2]], ptr [[A]], align 43055// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 43056// CHECK3-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]])3057// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 43058// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]3059// CHECK3-NEXT: store i32 [[ADD4]], ptr [[A]], align 43060// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 43061// CHECK3-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]])3062// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 43063// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]3064// CHECK3-NEXT: store i32 [[ADD6]], ptr [[A]], align 43065// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 43066// CHECK3-NEXT: ret i32 [[TMP8]]3067//3068//3069// CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei3070// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {3071// CHECK3-NEXT: entry:3072// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 43073// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 43074// CHECK3-NEXT: [[B:%.*]] = alloca i32, align 43075// CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 43076// CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 43077// CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 43078// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 43079// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 43080// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 43081// CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 43082// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 83083// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 43084// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 43085// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 43086// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 43087// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 13088// CHECK3-NEXT: store i32 [[ADD]], ptr [[B]], align 43089// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 43090// CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()3091// CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 43092// CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]3093// CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 23094// CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 43095// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 43096// CHECK3-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 43097// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 43098// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 43099// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 603100// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]3101// CHECK3: omp_if.then:3102// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 03103// CHECK3-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]]3104// CHECK3-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 23105// CHECK3-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i643106// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.5, i32 40, i1 false)3107// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 03108// CHECK3-NEXT: store ptr [[THIS1]], ptr [[TMP10]], align 43109// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 03110// CHECK3-NEXT: store ptr [[A]], ptr [[TMP11]], align 43111// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 03112// CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 43113// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 13114// CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP13]], align 43115// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 13116// CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP14]], align 43117// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 13118// CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 43119// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 23120// CHECK3-NEXT: store i32 2, ptr [[TMP16]], align 43121// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 23122// CHECK3-NEXT: store i32 2, ptr [[TMP17]], align 43123// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 23124// CHECK3-NEXT: store ptr null, ptr [[TMP18]], align 43125// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 33126// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP19]], align 43127// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 33128// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP20]], align 43129// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 33130// CHECK3-NEXT: store ptr null, ptr [[TMP21]], align 43131// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 43132// CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP22]], align 43133// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 43134// CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP23]], align 43135// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 43136// CHECK3-NEXT: store i64 [[TMP9]], ptr [[TMP24]], align 43137// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 43138// CHECK3-NEXT: store ptr null, ptr [[TMP25]], align 43139// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 03140// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 03141// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 03142// CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 03143// CHECK3-NEXT: store i32 3, ptr [[TMP29]], align 43144// CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 13145// CHECK3-NEXT: store i32 5, ptr [[TMP30]], align 43146// CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 23147// CHECK3-NEXT: store ptr [[TMP26]], ptr [[TMP31]], align 43148// CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 33149// CHECK3-NEXT: store ptr [[TMP27]], ptr [[TMP32]], align 43150// CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 43151// CHECK3-NEXT: store ptr [[TMP28]], ptr [[TMP33]], align 43152// CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 53153// CHECK3-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP34]], align 43154// CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 63155// CHECK3-NEXT: store ptr null, ptr [[TMP35]], align 43156// CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 73157// CHECK3-NEXT: store ptr null, ptr [[TMP36]], align 43158// CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 83159// CHECK3-NEXT: store i64 0, ptr [[TMP37]], align 83160// CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 93161// CHECK3-NEXT: store i64 0, ptr [[TMP38]], align 83162// CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 103163// CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP39]], align 43164// CHECK3-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 113165// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP40]], align 43166// CHECK3-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 123167// CHECK3-NEXT: store i32 0, ptr [[TMP41]], align 43168// CHECK3-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.region_id, ptr [[KERNEL_ARGS]])3169// CHECK3-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 03170// CHECK3-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]3171// CHECK3: omp_offload.failed:3172// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3]]3173// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]3174// CHECK3: omp_offload.cont:3175// CHECK3-NEXT: br label [[OMP_IF_END:%.*]]3176// CHECK3: omp_if.else:3177// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3]]3178// CHECK3-NEXT: br label [[OMP_IF_END]]3179// CHECK3: omp_if.end:3180// CHECK3-NEXT: [[TMP44:%.*]] = mul nsw i32 1, [[TMP1]]3181// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP44]]3182// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 13183// CHECK3-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 23184// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i323185// CHECK3-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 43186// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]]3187// CHECK3-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 43188// CHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP47]])3189// CHECK3-NEXT: ret i32 [[ADD3]]3190//3191//3192// CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici3193// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {3194// CHECK3-NEXT: entry:3195// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 43196// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 43197// CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 23198// CHECK3-NEXT: [[AAA:%.*]] = alloca i8, align 13199// CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 43200// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 43201// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 43202// CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 43203// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 43204// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 43205// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 43206// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 83207// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 43208// CHECK3-NEXT: store i32 0, ptr [[A]], align 43209// CHECK3-NEXT: store i16 0, ptr [[AA]], align 23210// CHECK3-NEXT: store i8 0, ptr [[AAA]], align 13211// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 43212// CHECK3-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 43213// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 43214// CHECK3-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 23215// CHECK3-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 23216// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 43217// CHECK3-NEXT: [[TMP4:%.*]] = load i8, ptr [[AAA]], align 13218// CHECK3-NEXT: store i8 [[TMP4]], ptr [[AAA_CASTED]], align 13219// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[AAA_CASTED]], align 43220// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 43221// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 503222// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]3223// CHECK3: omp_if.then:3224// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 03225// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP7]], align 43226// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 03227// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP8]], align 43228// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 03229// CHECK3-NEXT: store ptr null, ptr [[TMP9]], align 43230// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 13231// CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP10]], align 43232// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 13233// CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP11]], align 43234// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 13235// CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 43236// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 23237// CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP13]], align 43238// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 23239// CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP14]], align 43240// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 23241// CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 43242// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 33243// CHECK3-NEXT: store ptr [[B]], ptr [[TMP16]], align 43244// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 33245// CHECK3-NEXT: store ptr [[B]], ptr [[TMP17]], align 43246// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 33247// CHECK3-NEXT: store ptr null, ptr [[TMP18]], align 43248// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 03249// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 03250// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 03251// CHECK3-NEXT: store i32 3, ptr [[TMP21]], align 43252// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 13253// CHECK3-NEXT: store i32 4, ptr [[TMP22]], align 43254// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 23255// CHECK3-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 43256// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 33257// CHECK3-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 43258// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 43259// CHECK3-NEXT: store ptr @.offload_sizes.7, ptr [[TMP25]], align 43260// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 53261// CHECK3-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP26]], align 43262// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 63263// CHECK3-NEXT: store ptr null, ptr [[TMP27]], align 43264// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 73265// CHECK3-NEXT: store ptr null, ptr [[TMP28]], align 43266// CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 83267// CHECK3-NEXT: store i64 0, ptr [[TMP29]], align 83268// CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 93269// CHECK3-NEXT: store i64 0, ptr [[TMP30]], align 83270// CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 103271// CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP31]], align 43272// CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 113273// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP32]], align 43274// CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 123275// CHECK3-NEXT: store i32 0, ptr [[TMP33]], align 43276// CHECK3-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.region_id, ptr [[KERNEL_ARGS]])3277// CHECK3-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 03278// CHECK3-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]3279// CHECK3: omp_offload.failed:3280// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR3]]3281// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]3282// CHECK3: omp_offload.cont:3283// CHECK3-NEXT: br label [[OMP_IF_END:%.*]]3284// CHECK3: omp_if.else:3285// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR3]]3286// CHECK3-NEXT: br label [[OMP_IF_END]]3287// CHECK3: omp_if.end:3288// CHECK3-NEXT: [[TMP36:%.*]] = load i32, ptr [[A]], align 43289// CHECK3-NEXT: ret i32 [[TMP36]]3290//3291//3292// CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i3293// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {3294// CHECK3-NEXT: entry:3295// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 43296// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 43297// CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 23298// CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 43299// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 43300// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 43301// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 43302// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 43303// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 43304// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 83305// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 43306// CHECK3-NEXT: store i32 0, ptr [[A]], align 43307// CHECK3-NEXT: store i16 0, ptr [[AA]], align 23308// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 43309// CHECK3-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 43310// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 43311// CHECK3-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 23312// CHECK3-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 23313// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 43314// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 43315// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 403316// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]3317// CHECK3: omp_if.then:3318// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 03319// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP5]], align 43320// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 03321// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP6]], align 43322// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 03323// CHECK3-NEXT: store ptr null, ptr [[TMP7]], align 43324// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 13325// CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP8]], align 43326// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 13327// CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP9]], align 43328// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 13329// CHECK3-NEXT: store ptr null, ptr [[TMP10]], align 43330// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 23331// CHECK3-NEXT: store ptr [[B]], ptr [[TMP11]], align 43332// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 23333// CHECK3-NEXT: store ptr [[B]], ptr [[TMP12]], align 43334// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 23335// CHECK3-NEXT: store ptr null, ptr [[TMP13]], align 43336// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 03337// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 03338// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 03339// CHECK3-NEXT: store i32 3, ptr [[TMP16]], align 43340// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 13341// CHECK3-NEXT: store i32 3, ptr [[TMP17]], align 43342// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 23343// CHECK3-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 43344// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 33345// CHECK3-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 43346// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 43347// CHECK3-NEXT: store ptr @.offload_sizes.9, ptr [[TMP20]], align 43348// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 53349// CHECK3-NEXT: store ptr @.offload_maptypes.10, ptr [[TMP21]], align 43350// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 63351// CHECK3-NEXT: store ptr null, ptr [[TMP22]], align 43352// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 73353// CHECK3-NEXT: store ptr null, ptr [[TMP23]], align 43354// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 83355// CHECK3-NEXT: store i64 0, ptr [[TMP24]], align 83356// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 93357// CHECK3-NEXT: store i64 0, ptr [[TMP25]], align 83358// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 103359// CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP26]], align 43360// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 113361// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP27]], align 43362// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 123363// CHECK3-NEXT: store i32 0, ptr [[TMP28]], align 43364// CHECK3-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.region_id, ptr [[KERNEL_ARGS]])3365// CHECK3-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 03366// CHECK3-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]3367// CHECK3: omp_offload.failed:3368// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]]3369// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]3370// CHECK3: omp_offload.cont:3371// CHECK3-NEXT: br label [[OMP_IF_END:%.*]]3372// CHECK3: omp_if.else:3373// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]]3374// CHECK3-NEXT: br label [[OMP_IF_END]]3375// CHECK3: omp_if.end:3376// CHECK3-NEXT: [[TMP31:%.*]] = load i32, ptr [[A]], align 43377// CHECK3-NEXT: ret i32 [[TMP31]]3378//3379//3380// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l2323381// CHECK3-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {3382// CHECK3-NEXT: entry:3383// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 43384// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 43385// CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 43386// CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 43387// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 43388// CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 43389// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 43390// CHECK3-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 43391// CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 43392// CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 43393// CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 43394// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 43395// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 43396// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 43397// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 43398// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 43399// CHECK3-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 43400// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 43401// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.omp_outlined, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]])3402// CHECK3-NEXT: ret void3403//3404//3405// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.omp_outlined3406// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {3407// CHECK3-NEXT: entry:3408// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 43409// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 43410// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 43411// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 43412// CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 43413// CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 43414// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 43415// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 83416// CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 43417// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 83418// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 83419// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 83420// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 43421// CHECK3-NEXT: [[IT:%.*]] = alloca i64, align 83422// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 43423// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 43424// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 43425// CHECK3-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 43426// CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 43427// CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 43428// CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 43429// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 43430// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 43431// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 43432// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 43433// CHECK3-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 83434// CHECK3-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 83435// CHECK3-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 83436// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 43437// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 43438// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 43439// CHECK3-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)3440// CHECK3-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_UB]], align 83441// CHECK3-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 33442// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]3443// CHECK3: cond.true:3444// CHECK3-NEXT: br label [[COND_END:%.*]]3445// CHECK3: cond.false:3446// CHECK3-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 83447// CHECK3-NEXT: br label [[COND_END]]3448// CHECK3: cond.end:3449// CHECK3-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]3450// CHECK3-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 83451// CHECK3-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_LB]], align 83452// CHECK3-NEXT: store i64 [[TMP8]], ptr [[DOTOMP_IV]], align 83453// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]3454// CHECK3: omp.inner.for.cond:3455// CHECK3-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 83456// CHECK3-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 83457// CHECK3-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]3458// CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]3459// CHECK3: omp.inner.for.body:3460// CHECK3-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 83461// CHECK3-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 4003462// CHECK3-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]3463// CHECK3-NEXT: store i64 [[SUB]], ptr [[IT]], align 83464// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 43465// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double3466// CHECK3-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+003467// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 03468// CHECK3-NEXT: store double [[ADD]], ptr [[A]], align 43469// CHECK3-NEXT: [[A4:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 03470// CHECK3-NEXT: [[TMP13:%.*]] = load double, ptr [[A4]], align 43471// CHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+003472// CHECK3-NEXT: store double [[INC]], ptr [[A4]], align 43473// CHECK3-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i163474// CHECK3-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]3475// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP14]]3476// CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 13477// CHECK3-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 23478// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]3479// CHECK3: omp.body.continue:3480// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]3481// CHECK3: omp.inner.for.inc:3482// CHECK3-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 83483// CHECK3-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 13484// CHECK3-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 83485// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]3486// CHECK3: omp.inner.for.end:3487// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]3488// CHECK3: omp.loop.exit:3489// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])3490// CHECK3-NEXT: ret void3491//3492//3493// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l2143494// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {3495// CHECK3-NEXT: entry:3496// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 43497// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 43498// CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 43499// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 43500// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 43501// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 43502// CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 43503// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 43504// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 43505// CHECK3-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 43506// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 43507// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 43508// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 43509// CHECK3-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 43510// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 43511// CHECK3-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 23512// CHECK3-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 23513// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 43514// CHECK3-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 13515// CHECK3-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 13516// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[AAA_CASTED]], align 43517// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], ptr [[TMP0]])3518// CHECK3-NEXT: ret void3519//3520//3521// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.omp_outlined3522// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {3523// CHECK3-NEXT: entry:3524// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 43525// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 43526// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 43527// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 43528// CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 43529// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 43530// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 43531// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 43532// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 43533// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 43534// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 43535// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 43536// CHECK3-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 43537// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 43538// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 43539// CHECK3-NEXT: ret void3540//3541//3542// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l1973543// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {3544// CHECK3-NEXT: entry:3545// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 43546// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 43547// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 43548// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 43549// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 43550// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 43551// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 43552// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 43553// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 43554// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 43555// CHECK3-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 43556// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 43557// CHECK3-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 23558// CHECK3-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 23559// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 43560// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]])3561// CHECK3-NEXT: ret void3562//3563//3564// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.omp_outlined3565// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {3566// CHECK3-NEXT: entry:3567// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 43568// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 43569// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 43570// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 43571// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 43572// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 83573// CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 43574// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 83575// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 83576// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 83577// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 43578// CHECK3-NEXT: [[I:%.*]] = alloca i64, align 83579// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 43580// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 43581// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 43582// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 43583// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 43584// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 43585// CHECK3-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 83586// CHECK3-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 83587// CHECK3-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 83588// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 43589// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 43590// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 43591// CHECK3-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)3592// CHECK3-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 83593// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 63594// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]3595// CHECK3: cond.true:3596// CHECK3-NEXT: br label [[COND_END:%.*]]3597// CHECK3: cond.false:3598// CHECK3-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 83599// CHECK3-NEXT: br label [[COND_END]]3600// CHECK3: cond.end:3601// CHECK3-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]3602// CHECK3-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 83603// CHECK3-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 83604// CHECK3-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 83605// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]3606// CHECK3: omp.inner.for.cond:3607// CHECK3-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 83608// CHECK3-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 83609// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]3610// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]3611// CHECK3: omp.inner.for.body:3612// CHECK3-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 83613// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 33614// CHECK3-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]3615// CHECK3-NEXT: store i64 [[ADD]], ptr [[I]], align 83616// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 43617// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 13618// CHECK3-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 43619// CHECK3-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 23620// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i323621// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 13622// CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i163623// CHECK3-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 23624// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 23625// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 43626// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 13627// CHECK3-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 43628// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]3629// CHECK3: omp.body.continue:3630// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]3631// CHECK3: omp.inner.for.inc:3632// CHECK3-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 83633// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 13634// CHECK3-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 83635// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]3636// CHECK3: omp.inner.for.end:3637// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]3638// CHECK3: omp.loop.exit:3639// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])3640// CHECK3-NEXT: ret void3641//3642//3643// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1033644// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {3645// CHECK9-NEXT: entry:3646// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 83647// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 83648// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined)3649// CHECK9-NEXT: ret void3650//3651//3652// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined3653// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {3654// CHECK9-NEXT: entry:3655// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 83656// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 83657// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 43658// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 43659// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 43660// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 43661// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 43662// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 43663// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 43664// CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 83665// CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 83666// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 43667// CHECK9-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 43668// CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 43669// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 43670// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 83671// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 43672// CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)3673// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43674// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 53675// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]3676// CHECK9: cond.true:3677// CHECK9-NEXT: br label [[COND_END:%.*]]3678// CHECK9: cond.false:3679// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43680// CHECK9-NEXT: br label [[COND_END]]3681// CHECK9: cond.end:3682// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]3683// CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 43684// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 43685// CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 43686// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]3687// CHECK9: omp.inner.for.cond:3688// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43689// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43690// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]3691// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]3692// CHECK9: omp.inner.for.body:3693// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43694// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 53695// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]3696// CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 43697// CHECK9-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(ptr @[[GLOB2]], i32 [[TMP1]], i32 2)3698// CHECK9-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 03699// CHECK9-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]3700// CHECK9: .cancel.exit:3701// CHECK9-NEXT: br label [[CANCEL_EXIT:%.*]]3702// CHECK9: .cancel.continue:3703// CHECK9-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(ptr @[[GLOB2]], i32 [[TMP1]], i32 2)3704// CHECK9-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 03705// CHECK9-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]3706// CHECK9: .cancel.exit2:3707// CHECK9-NEXT: br label [[CANCEL_EXIT]]3708// CHECK9: .cancel.continue3:3709// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]3710// CHECK9: omp.body.continue:3711// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]3712// CHECK9: omp.inner.for.inc:3713// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43714// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 13715// CHECK9-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 43716// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]3717// CHECK9: omp.inner.for.end:3718// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]3719// CHECK9: omp.loop.exit:3720// CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])3721// CHECK9-NEXT: br label [[CANCEL_CONT:%.*]]3722// CHECK9: cancel.cont:3723// CHECK9-NEXT: ret void3724// CHECK9: cancel.exit:3725// CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])3726// CHECK9-NEXT: br label [[CANCEL_CONT]]3727//3728//3729// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1283730// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] {3731// CHECK9-NEXT: entry:3732// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 83733// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 83734// CHECK9-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 83735// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 83736// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 83737// CHECK9-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 83738// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 83739// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 83740// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 83741// CHECK9-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 83742// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 83743// CHECK9-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 23744// CHECK9-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 23745// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 83746// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 43747// CHECK9-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 43748// CHECK9-NEXT: [[TMP3:%.*]] = load i64, ptr [[LIN_CASTED]], align 83749// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 43750// CHECK9-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 43751// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[A_CASTED]], align 83752// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.omp_outlined, i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])3753// CHECK9-NEXT: ret void3754//3755//3756// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.omp_outlined3757// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] {3758// CHECK9-NEXT: entry:3759// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 83760// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 83761// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 83762// CHECK9-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 83763// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 83764// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 83765// CHECK9-NEXT: [[TMP:%.*]] = alloca i64, align 83766// CHECK9-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 43767// CHECK9-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 43768// CHECK9-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 83769// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 83770// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 83771// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 83772// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 43773// CHECK9-NEXT: [[IT:%.*]] = alloca i64, align 83774// CHECK9-NEXT: [[LIN2:%.*]] = alloca i32, align 43775// CHECK9-NEXT: [[A3:%.*]] = alloca i32, align 43776// CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 83777// CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 83778// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 83779// CHECK9-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 83780// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 83781// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 43782// CHECK9-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 43783// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 43784// CHECK9-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 43785// CHECK9-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()3786// CHECK9-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 83787// CHECK9-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 83788// CHECK9-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 83789// CHECK9-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 83790// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 43791// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 83792// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 43793// CHECK9-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP3]])3794// CHECK9-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)3795// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 83796// CHECK9-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 33797// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]3798// CHECK9: cond.true:3799// CHECK9-NEXT: br label [[COND_END:%.*]]3800// CHECK9: cond.false:3801// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 83802// CHECK9-NEXT: br label [[COND_END]]3803// CHECK9: cond.end:3804// CHECK9-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]3805// CHECK9-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 83806// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 83807// CHECK9-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 83808// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]3809// CHECK9: omp.inner.for.cond:3810// CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 83811// CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 83812// CHECK9-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]3813// CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]3814// CHECK9: omp.inner.for.body:3815// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 83816// CHECK9-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 4003817// CHECK9-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]3818// CHECK9-NEXT: store i64 [[SUB]], ptr [[IT]], align 83819// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 43820// CHECK9-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i643821// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 83822// CHECK9-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 83823// CHECK9-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]]3824// CHECK9-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]]3825// CHECK9-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i323826// CHECK9-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 43827// CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 43828// CHECK9-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i643829// CHECK9-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 83830// CHECK9-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 83831// CHECK9-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]]3832// CHECK9-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]]3833// CHECK9-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i323834// CHECK9-NEXT: store i32 [[CONV10]], ptr [[A3]], align 43835// CHECK9-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 23836// CHECK9-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i323837// CHECK9-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 13838// CHECK9-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i163839// CHECK9-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 23840// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]3841// CHECK9: omp.body.continue:3842// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]3843// CHECK9: omp.inner.for.inc:3844// CHECK9-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 83845// CHECK9-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 13846// CHECK9-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 83847// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]3848// CHECK9: omp.inner.for.end:3849// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]3850// CHECK9: omp.loop.exit:3851// CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]])3852// CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 43853// CHECK9-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 03854// CHECK9-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]3855// CHECK9: .omp.linear.pu:3856// CHECK9-NEXT: [[TMP20:%.*]] = load i32, ptr [[LIN2]], align 43857// CHECK9-NEXT: store i32 [[TMP20]], ptr [[LIN_ADDR]], align 43858// CHECK9-NEXT: [[TMP21:%.*]] = load i32, ptr [[A3]], align 43859// CHECK9-NEXT: store i32 [[TMP21]], ptr [[A_ADDR]], align 43860// CHECK9-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]3861// CHECK9: .omp.linear.pu.done:3862// CHECK9-NEXT: ret void3863//3864//3865// CHECK9-LABEL: define {{[^@]+}}@_Z7get_valv3866// CHECK9-SAME: () #[[ATTR2:[0-9]+]] {3867// CHECK9-NEXT: entry:3868// CHECK9-NEXT: ret i64 03869//3870//3871// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1363872// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {3873// CHECK9-NEXT: entry:3874// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 83875// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 83876// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 83877// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 83878// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 83879// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 83880// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 83881// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 83882// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 43883// CHECK9-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 43884// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 83885// CHECK9-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 23886// CHECK9-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 23887// CHECK9-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 83888// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined, i64 [[TMP1]], i64 [[TMP3]])3889// CHECK9-NEXT: ret void3890//3891//3892// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined3893// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {3894// CHECK9-NEXT: entry:3895// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 83896// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 83897// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 83898// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 83899// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 43900// CHECK9-NEXT: [[TMP:%.*]] = alloca i16, align 23901// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 43902// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 43903// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 43904// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 43905// CHECK9-NEXT: [[IT:%.*]] = alloca i16, align 23906// CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 83907// CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 83908// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 83909// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 83910// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 43911// CHECK9-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 43912// CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 43913// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 43914// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 83915// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 43916// CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)3917// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43918// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 33919// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]3920// CHECK9: cond.true:3921// CHECK9-NEXT: br label [[COND_END:%.*]]3922// CHECK9: cond.false:3923// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43924// CHECK9-NEXT: br label [[COND_END]]3925// CHECK9: cond.end:3926// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]3927// CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 43928// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 43929// CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 43930// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]3931// CHECK9: omp.inner.for.cond:3932// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43933// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43934// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]3935// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]3936// CHECK9: omp.inner.for.body:3937// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43938// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 43939// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]3940// CHECK9-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i163941// CHECK9-NEXT: store i16 [[CONV]], ptr [[IT]], align 23942// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 43943// CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 13944// CHECK9-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 43945// CHECK9-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 23946// CHECK9-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i323947// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 13948// CHECK9-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i163949// CHECK9-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 23950// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]3951// CHECK9: omp.body.continue:3952// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]3953// CHECK9: omp.inner.for.inc:3954// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43955// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 13956// CHECK9-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 43957// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]3958// CHECK9: omp.inner.for.end:3959// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]3960// CHECK9: omp.loop.exit:3961// CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])3962// CHECK9-NEXT: ret void3963//3964//3965// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1603966// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {3967// CHECK9-NEXT: entry:3968// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 83969// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 83970// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 83971// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 83972// CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 83973// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 83974// CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 83975// CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 83976// CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 83977// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 83978// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 83979// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 83980// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 83981// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 83982// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 83983// CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 83984// CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 83985// CHECK9-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 83986// CHECK9-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 83987// CHECK9-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 83988// CHECK9-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 83989// CHECK9-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 83990// CHECK9-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 83991// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 83992// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 83993// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 83994// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 83995// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 83996// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 83997// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 83998// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 83999// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 84000// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 44001// CHECK9-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 44002// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 84003// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 44004// CHECK9-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 44005// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 84006// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i64 [[TMP11]])4007// CHECK9-NEXT: ret void4008//4009//4010// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined4011// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {4012// CHECK9-NEXT: entry:4013// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 84014// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 84015// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 84016// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 84017// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 84018// CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 84019// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 84020// CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 84021// CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 84022// CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 84023// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 84024// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 84025// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 44026// CHECK9-NEXT: [[TMP:%.*]] = alloca i8, align 14027// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 44028// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 44029// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 44030// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 44031// CHECK9-NEXT: [[IT:%.*]] = alloca i8, align 14032// CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 84033// CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 84034// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 84035// CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 84036// CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 84037// CHECK9-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 84038// CHECK9-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 84039// CHECK9-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 84040// CHECK9-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 84041// CHECK9-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 84042// CHECK9-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 84043// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 84044// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 84045// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 84046// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 84047// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 84048// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 84049// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 84050// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 84051// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 84052// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 44053// CHECK9-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 44054// CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 44055// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 44056// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 44057// CHECK9-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 84058// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 44059// CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])4060// CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]]4061// CHECK9: omp.dispatch.cond:4062// CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44063// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 254064// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]4065// CHECK9: cond.true:4066// CHECK9-NEXT: br label [[COND_END:%.*]]4067// CHECK9: cond.false:4068// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44069// CHECK9-NEXT: br label [[COND_END]]4070// CHECK9: cond.end:4071// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]4072// CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 44073// CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 44074// CHECK9-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 44075// CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44076// CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44077// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]4078// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]4079// CHECK9: omp.dispatch.body:4080// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]4081// CHECK9: omp.inner.for.cond:4082// CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44083// CHECK9-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44084// CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]4085// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]4086// CHECK9: omp.inner.for.body:4087// CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44088// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 14089// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]4090// CHECK9-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i84091// CHECK9-NEXT: store i8 [[CONV]], ptr [[IT]], align 14092// CHECK9-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 44093// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 14094// CHECK9-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 44095// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 24096// CHECK9-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 44097// CHECK9-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double4098// CHECK9-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+004099// CHECK9-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float4100// CHECK9-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 44101// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 34102// CHECK9-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 44103// CHECK9-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double4104// CHECK9-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+004105// CHECK9-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float4106// CHECK9-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 44107// CHECK9-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 14108// CHECK9-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i64 0, i64 24109// CHECK9-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 84110// CHECK9-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+004111// CHECK9-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 84112// CHECK9-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]4113// CHECK9-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP23]]4114// CHECK9-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i64 34115// CHECK9-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 84116// CHECK9-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+004117// CHECK9-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 84118// CHECK9-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 04119// CHECK9-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 84120// CHECK9-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 14121// CHECK9-NEXT: store i64 [[ADD20]], ptr [[X]], align 84122// CHECK9-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 14123// CHECK9-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 84124// CHECK9-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i324125// CHECK9-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 14126// CHECK9-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i84127// CHECK9-NEXT: store i8 [[CONV23]], ptr [[Y]], align 84128// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]4129// CHECK9: omp.body.continue:4130// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]4131// CHECK9: omp.inner.for.inc:4132// CHECK9-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44133// CHECK9-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 14134// CHECK9-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 44135// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]4136// CHECK9: omp.inner.for.end:4137// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]]4138// CHECK9: omp.dispatch.inc:4139// CHECK9-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 44140// CHECK9-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 44141// CHECK9-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]4142// CHECK9-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 44143// CHECK9-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44144// CHECK9-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 44145// CHECK9-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]4146// CHECK9-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 44147// CHECK9-NEXT: br label [[OMP_DISPATCH_COND]]4148// CHECK9: omp.dispatch.end:4149// CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]])4150// CHECK9-NEXT: ret void4151//4152//4153// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l2144154// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {4155// CHECK9-NEXT: entry:4156// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 84157// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 84158// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 84159// CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 84160// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 84161// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 84162// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 84163// CHECK9-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 84164// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 84165// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 84166// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 84167// CHECK9-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 84168// CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 84169// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 84170// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 44171// CHECK9-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 44172// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 84173// CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 24174// CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 24175// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 84176// CHECK9-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 14177// CHECK9-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 14178// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[AAA_CASTED]], align 84179// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], ptr [[TMP0]])4180// CHECK9-NEXT: ret void4181//4182//4183// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.omp_outlined4184// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {4185// CHECK9-NEXT: entry:4186// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 84187// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 84188// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 84189// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 84190// CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 84191// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 84192// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 44193// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 44194// CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 84195// CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 84196// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 84197// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 84198// CHECK9-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 84199// CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 84200// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 84201// CHECK9-NEXT: ret void4202//4203//4204// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l2324205// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {4206// CHECK9-NEXT: entry:4207// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 84208// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 84209// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 84210// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 84211// CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 84212// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 84213// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 84214// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 84215// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 84216// CHECK9-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 84217// CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 84218// CHECK9-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 84219// CHECK9-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 84220// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 84221// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 84222// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 84223// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 84224// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 44225// CHECK9-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 44226// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 84227// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.omp_outlined, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]])4228// CHECK9-NEXT: ret void4229//4230//4231// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.omp_outlined4232// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {4233// CHECK9-NEXT: entry:4234// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 84235// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 84236// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 84237// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 84238// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 84239// CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 84240// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 84241// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 84242// CHECK9-NEXT: [[TMP:%.*]] = alloca i64, align 84243// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 84244// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 84245// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 84246// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 44247// CHECK9-NEXT: [[IT:%.*]] = alloca i64, align 84248// CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 84249// CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 84250// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 84251// CHECK9-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 84252// CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 84253// CHECK9-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 84254// CHECK9-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 84255// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 84256// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 84257// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 84258// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 84259// CHECK9-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 84260// CHECK9-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 84261// CHECK9-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 84262// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 44263// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 84264// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 44265// CHECK9-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)4266// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_UB]], align 84267// CHECK9-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 34268// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]4269// CHECK9: cond.true:4270// CHECK9-NEXT: br label [[COND_END:%.*]]4271// CHECK9: cond.false:4272// CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 84273// CHECK9-NEXT: br label [[COND_END]]4274// CHECK9: cond.end:4275// CHECK9-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]4276// CHECK9-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 84277// CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_LB]], align 84278// CHECK9-NEXT: store i64 [[TMP8]], ptr [[DOTOMP_IV]], align 84279// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]4280// CHECK9: omp.inner.for.cond:4281// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 84282// CHECK9-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 84283// CHECK9-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]4284// CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]4285// CHECK9: omp.inner.for.body:4286// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 84287// CHECK9-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 4004288// CHECK9-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]4289// CHECK9-NEXT: store i64 [[SUB]], ptr [[IT]], align 84290// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 44291// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double4292// CHECK9-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+004293// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 04294// CHECK9-NEXT: store double [[ADD]], ptr [[A]], align 84295// CHECK9-NEXT: [[A4:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 04296// CHECK9-NEXT: [[TMP13:%.*]] = load double, ptr [[A4]], align 84297// CHECK9-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+004298// CHECK9-NEXT: store double [[INC]], ptr [[A4]], align 84299// CHECK9-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i164300// CHECK9-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]4301// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP14]]4302// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 14303// CHECK9-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 24304// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]4305// CHECK9: omp.body.continue:4306// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]4307// CHECK9: omp.inner.for.inc:4308// CHECK9-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 84309// CHECK9-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 14310// CHECK9-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 84311// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]4312// CHECK9: omp.inner.for.end:4313// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]4314// CHECK9: omp.loop.exit:4315// CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])4316// CHECK9-NEXT: ret void4317//4318//4319// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l1974320// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {4321// CHECK9-NEXT: entry:4322// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 84323// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 84324// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 84325// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 84326// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 84327// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 84328// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 84329// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 84330// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 84331// CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 84332// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 84333// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 44334// CHECK9-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 44335// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 84336// CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 24337// CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 24338// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 84339// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]])4340// CHECK9-NEXT: ret void4341//4342//4343// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.omp_outlined4344// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {4345// CHECK9-NEXT: entry:4346// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 84347// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 84348// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 84349// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 84350// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 84351// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 84352// CHECK9-NEXT: [[TMP:%.*]] = alloca i64, align 84353// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 84354// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 84355// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 84356// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 44357// CHECK9-NEXT: [[I:%.*]] = alloca i64, align 84358// CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 84359// CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 84360// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 84361// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 84362// CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 84363// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 84364// CHECK9-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 84365// CHECK9-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 84366// CHECK9-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 84367// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 44368// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 84369// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 44370// CHECK9-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)4371// CHECK9-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 84372// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 64373// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]4374// CHECK9: cond.true:4375// CHECK9-NEXT: br label [[COND_END:%.*]]4376// CHECK9: cond.false:4377// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 84378// CHECK9-NEXT: br label [[COND_END]]4379// CHECK9: cond.end:4380// CHECK9-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]4381// CHECK9-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 84382// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 84383// CHECK9-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 84384// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]4385// CHECK9: omp.inner.for.cond:4386// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 84387// CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 84388// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]4389// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]4390// CHECK9: omp.inner.for.body:4391// CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 84392// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 34393// CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]4394// CHECK9-NEXT: store i64 [[ADD]], ptr [[I]], align 84395// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 44396// CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 14397// CHECK9-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 44398// CHECK9-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 24399// CHECK9-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i324400// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 14401// CHECK9-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i164402// CHECK9-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 24403// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 24404// CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 44405// CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 14406// CHECK9-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 44407// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]4408// CHECK9: omp.body.continue:4409// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]4410// CHECK9: omp.inner.for.inc:4411// CHECK9-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 84412// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 14413// CHECK9-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 84414// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]4415// CHECK9: omp.inner.for.end:4416// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]4417// CHECK9: omp.loop.exit:4418// CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])4419// CHECK9-NEXT: ret void4420//4421//4422// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1034423// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {4424// CHECK11-NEXT: entry:4425// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 44426// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 44427// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined)4428// CHECK11-NEXT: ret void4429//4430//4431// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined4432// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {4433// CHECK11-NEXT: entry:4434// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 44435// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 44436// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 44437// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 44438// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 44439// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 44440// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 44441// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 44442// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 44443// CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 44444// CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 44445// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 44446// CHECK11-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 44447// CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 44448// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 44449// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 44450// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 44451// CHECK11-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)4452// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44453// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 54454// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]4455// CHECK11: cond.true:4456// CHECK11-NEXT: br label [[COND_END:%.*]]4457// CHECK11: cond.false:4458// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44459// CHECK11-NEXT: br label [[COND_END]]4460// CHECK11: cond.end:4461// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]4462// CHECK11-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 44463// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 44464// CHECK11-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 44465// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]4466// CHECK11: omp.inner.for.cond:4467// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44468// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44469// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]4470// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]4471// CHECK11: omp.inner.for.body:4472// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44473// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 54474// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]4475// CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 44476// CHECK11-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(ptr @[[GLOB2]], i32 [[TMP1]], i32 2)4477// CHECK11-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 04478// CHECK11-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]4479// CHECK11: .cancel.exit:4480// CHECK11-NEXT: br label [[CANCEL_EXIT:%.*]]4481// CHECK11: .cancel.continue:4482// CHECK11-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(ptr @[[GLOB2]], i32 [[TMP1]], i32 2)4483// CHECK11-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 04484// CHECK11-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]4485// CHECK11: .cancel.exit2:4486// CHECK11-NEXT: br label [[CANCEL_EXIT]]4487// CHECK11: .cancel.continue3:4488// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]4489// CHECK11: omp.body.continue:4490// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]4491// CHECK11: omp.inner.for.inc:4492// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44493// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 14494// CHECK11-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 44495// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]4496// CHECK11: omp.inner.for.end:4497// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]4498// CHECK11: omp.loop.exit:4499// CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])4500// CHECK11-NEXT: br label [[CANCEL_CONT:%.*]]4501// CHECK11: cancel.cont:4502// CHECK11-NEXT: ret void4503// CHECK11: cancel.exit:4504// CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])4505// CHECK11-NEXT: br label [[CANCEL_CONT]]4506//4507//4508// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1284509// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] {4510// CHECK11-NEXT: entry:4511// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 44512// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 44513// CHECK11-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 44514// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 44515// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 44516// CHECK11-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 44517// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 44518// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 44519// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 44520// CHECK11-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 44521// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 44522// CHECK11-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 24523// CHECK11-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 24524// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 44525// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 44526// CHECK11-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 44527// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[LIN_CASTED]], align 44528// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 44529// CHECK11-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 44530// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[A_CASTED]], align 44531// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.omp_outlined, i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])4532// CHECK11-NEXT: ret void4533//4534//4535// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.omp_outlined4536// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] {4537// CHECK11-NEXT: entry:4538// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 44539// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 44540// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 44541// CHECK11-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 44542// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 44543// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 84544// CHECK11-NEXT: [[TMP:%.*]] = alloca i64, align 44545// CHECK11-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 44546// CHECK11-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 44547// CHECK11-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 84548// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 84549// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 84550// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 84551// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 44552// CHECK11-NEXT: [[IT:%.*]] = alloca i64, align 84553// CHECK11-NEXT: [[LIN2:%.*]] = alloca i32, align 44554// CHECK11-NEXT: [[A3:%.*]] = alloca i32, align 44555// CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 44556// CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 44557// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 44558// CHECK11-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 44559// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 44560// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 44561// CHECK11-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 44562// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 44563// CHECK11-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 44564// CHECK11-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()4565// CHECK11-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 84566// CHECK11-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 84567// CHECK11-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 84568// CHECK11-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 84569// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 44570// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 44571// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 44572// CHECK11-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP3]])4573// CHECK11-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)4574// CHECK11-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 84575// CHECK11-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 34576// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]4577// CHECK11: cond.true:4578// CHECK11-NEXT: br label [[COND_END:%.*]]4579// CHECK11: cond.false:4580// CHECK11-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 84581// CHECK11-NEXT: br label [[COND_END]]4582// CHECK11: cond.end:4583// CHECK11-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]4584// CHECK11-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 84585// CHECK11-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 84586// CHECK11-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 84587// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]4588// CHECK11: omp.inner.for.cond:4589// CHECK11-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 84590// CHECK11-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 84591// CHECK11-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]4592// CHECK11-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]4593// CHECK11: omp.inner.for.body:4594// CHECK11-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 84595// CHECK11-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 4004596// CHECK11-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]4597// CHECK11-NEXT: store i64 [[SUB]], ptr [[IT]], align 84598// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 44599// CHECK11-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i644600// CHECK11-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 84601// CHECK11-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 84602// CHECK11-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]]4603// CHECK11-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]]4604// CHECK11-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i324605// CHECK11-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 44606// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 44607// CHECK11-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i644608// CHECK11-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 84609// CHECK11-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 84610// CHECK11-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]]4611// CHECK11-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]]4612// CHECK11-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i324613// CHECK11-NEXT: store i32 [[CONV10]], ptr [[A3]], align 44614// CHECK11-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 24615// CHECK11-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i324616// CHECK11-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 14617// CHECK11-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i164618// CHECK11-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 24619// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]4620// CHECK11: omp.body.continue:4621// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]4622// CHECK11: omp.inner.for.inc:4623// CHECK11-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 84624// CHECK11-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 14625// CHECK11-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 84626// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]4627// CHECK11: omp.inner.for.end:4628// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]4629// CHECK11: omp.loop.exit:4630// CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]])4631// CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 44632// CHECK11-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 04633// CHECK11-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]4634// CHECK11: .omp.linear.pu:4635// CHECK11-NEXT: [[TMP20:%.*]] = load i32, ptr [[LIN2]], align 44636// CHECK11-NEXT: store i32 [[TMP20]], ptr [[LIN_ADDR]], align 44637// CHECK11-NEXT: [[TMP21:%.*]] = load i32, ptr [[A3]], align 44638// CHECK11-NEXT: store i32 [[TMP21]], ptr [[A_ADDR]], align 44639// CHECK11-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]4640// CHECK11: .omp.linear.pu.done:4641// CHECK11-NEXT: ret void4642//4643//4644// CHECK11-LABEL: define {{[^@]+}}@_Z7get_valv4645// CHECK11-SAME: () #[[ATTR2:[0-9]+]] {4646// CHECK11-NEXT: entry:4647// CHECK11-NEXT: ret i64 04648//4649//4650// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1364651// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {4652// CHECK11-NEXT: entry:4653// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 44654// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 44655// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 44656// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 44657// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 44658// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 44659// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 44660// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 44661// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 44662// CHECK11-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 44663// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 44664// CHECK11-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 24665// CHECK11-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 24666// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 44667// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined, i32 [[TMP1]], i32 [[TMP3]])4668// CHECK11-NEXT: ret void4669//4670//4671// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined4672// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {4673// CHECK11-NEXT: entry:4674// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 44675// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 44676// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 44677// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 44678// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 44679// CHECK11-NEXT: [[TMP:%.*]] = alloca i16, align 24680// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 44681// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 44682// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 44683// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 44684// CHECK11-NEXT: [[IT:%.*]] = alloca i16, align 24685// CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 44686// CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 44687// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 44688// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 44689// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 44690// CHECK11-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 44691// CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 44692// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 44693// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 44694// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 44695// CHECK11-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)4696// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44697// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 34698// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]4699// CHECK11: cond.true:4700// CHECK11-NEXT: br label [[COND_END:%.*]]4701// CHECK11: cond.false:4702// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44703// CHECK11-NEXT: br label [[COND_END]]4704// CHECK11: cond.end:4705// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]4706// CHECK11-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 44707// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 44708// CHECK11-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 44709// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]4710// CHECK11: omp.inner.for.cond:4711// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44712// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44713// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]4714// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]4715// CHECK11: omp.inner.for.body:4716// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44717// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 44718// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]4719// CHECK11-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i164720// CHECK11-NEXT: store i16 [[CONV]], ptr [[IT]], align 24721// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 44722// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 14723// CHECK11-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 44724// CHECK11-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 24725// CHECK11-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i324726// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 14727// CHECK11-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i164728// CHECK11-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 24729// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]4730// CHECK11: omp.body.continue:4731// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]4732// CHECK11: omp.inner.for.inc:4733// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44734// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 14735// CHECK11-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 44736// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]4737// CHECK11: omp.inner.for.end:4738// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]4739// CHECK11: omp.loop.exit:4740// CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])4741// CHECK11-NEXT: ret void4742//4743//4744// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1604745// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {4746// CHECK11-NEXT: entry:4747// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 44748// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 44749// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 44750// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 44751// CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 44752// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 44753// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 44754// CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 44755// CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 44756// CHECK11-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 44757// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 44758// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 44759// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 44760// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 44761// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 44762// CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 44763// CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 44764// CHECK11-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 44765// CHECK11-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 44766// CHECK11-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 44767// CHECK11-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 44768// CHECK11-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 44769// CHECK11-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 44770// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 44771// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 44772// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 44773// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 44774// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 44775// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 44776// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 44777// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 44778// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 44779// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 44780// CHECK11-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 44781// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 44782// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 44783// CHECK11-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 44784// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 44785// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i32 [[TMP11]])4786// CHECK11-NEXT: ret void4787//4788//4789// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined4790// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {4791// CHECK11-NEXT: entry:4792// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 44793// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 44794// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 44795// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 44796// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 44797// CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 44798// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 44799// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 44800// CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 44801// CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 44802// CHECK11-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 44803// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 44804// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 44805// CHECK11-NEXT: [[TMP:%.*]] = alloca i8, align 14806// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 44807// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 44808// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 44809// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 44810// CHECK11-NEXT: [[IT:%.*]] = alloca i8, align 14811// CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 44812// CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 44813// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 44814// CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 44815// CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 44816// CHECK11-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 44817// CHECK11-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 44818// CHECK11-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 44819// CHECK11-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 44820// CHECK11-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 44821// CHECK11-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 44822// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 44823// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 44824// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 44825// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 44826// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 44827// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 44828// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 44829// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 44830// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 44831// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 44832// CHECK11-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 44833// CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 44834// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 44835// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 44836// CHECK11-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 44837// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 44838// CHECK11-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])4839// CHECK11-NEXT: br label [[OMP_DISPATCH_COND:%.*]]4840// CHECK11: omp.dispatch.cond:4841// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44842// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 254843// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]4844// CHECK11: cond.true:4845// CHECK11-NEXT: br label [[COND_END:%.*]]4846// CHECK11: cond.false:4847// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44848// CHECK11-NEXT: br label [[COND_END]]4849// CHECK11: cond.end:4850// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]4851// CHECK11-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 44852// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 44853// CHECK11-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 44854// CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44855// CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44856// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]4857// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]4858// CHECK11: omp.dispatch.body:4859// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]4860// CHECK11: omp.inner.for.cond:4861// CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44862// CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44863// CHECK11-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]4864// CHECK11-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]4865// CHECK11: omp.inner.for.body:4866// CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44867// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 14868// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]4869// CHECK11-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i84870// CHECK11-NEXT: store i8 [[CONV]], ptr [[IT]], align 14871// CHECK11-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 44872// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 14873// CHECK11-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 44874// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 24875// CHECK11-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 44876// CHECK11-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double4877// CHECK11-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+004878// CHECK11-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float4879// CHECK11-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 44880// CHECK11-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 34881// CHECK11-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 44882// CHECK11-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double4883// CHECK11-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+004884// CHECK11-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float4885// CHECK11-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 44886// CHECK11-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 14887// CHECK11-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i32 0, i32 24888// CHECK11-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 84889// CHECK11-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+004890// CHECK11-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 84891// CHECK11-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]4892// CHECK11-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP23]]4893// CHECK11-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i32 34894// CHECK11-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 84895// CHECK11-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+004896// CHECK11-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 84897// CHECK11-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 04898// CHECK11-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 44899// CHECK11-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 14900// CHECK11-NEXT: store i64 [[ADD20]], ptr [[X]], align 44901// CHECK11-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 14902// CHECK11-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 44903// CHECK11-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i324904// CHECK11-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 14905// CHECK11-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i84906// CHECK11-NEXT: store i8 [[CONV23]], ptr [[Y]], align 44907// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]4908// CHECK11: omp.body.continue:4909// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]4910// CHECK11: omp.inner.for.inc:4911// CHECK11-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44912// CHECK11-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 14913// CHECK11-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 44914// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]4915// CHECK11: omp.inner.for.end:4916// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]]4917// CHECK11: omp.dispatch.inc:4918// CHECK11-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 44919// CHECK11-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 44920// CHECK11-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]4921// CHECK11-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 44922// CHECK11-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44923// CHECK11-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 44924// CHECK11-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]4925// CHECK11-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 44926// CHECK11-NEXT: br label [[OMP_DISPATCH_COND]]4927// CHECK11: omp.dispatch.end:4928// CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]])4929// CHECK11-NEXT: ret void4930//4931//4932// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l2144933// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {4934// CHECK11-NEXT: entry:4935// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 44936// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 44937// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 44938// CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 44939// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 44940// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 44941// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 44942// CHECK11-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 44943// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 44944// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 44945// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 44946// CHECK11-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 44947// CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 44948// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 44949// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 44950// CHECK11-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 44951// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 44952// CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 24953// CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 24954// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 44955// CHECK11-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 14956// CHECK11-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 14957// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[AAA_CASTED]], align 44958// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], ptr [[TMP0]])4959// CHECK11-NEXT: ret void4960//4961//4962// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.omp_outlined4963// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {4964// CHECK11-NEXT: entry:4965// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 44966// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 44967// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 44968// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 44969// CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 44970// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 44971// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 44972// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 44973// CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 44974// CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 44975// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 44976// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 44977// CHECK11-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 44978// CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 44979// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 44980// CHECK11-NEXT: ret void4981//4982//4983// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l2324984// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {4985// CHECK11-NEXT: entry:4986// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 44987// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 44988// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 44989// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 44990// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 44991// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 44992// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 44993// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 44994// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 44995// CHECK11-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 44996// CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 44997// CHECK11-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 44998// CHECK11-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 44999// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 45000// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 45001// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 45002// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 45003// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 45004// CHECK11-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 45005// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 45006// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.omp_outlined, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]])5007// CHECK11-NEXT: ret void5008//5009//5010// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.omp_outlined5011// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {5012// CHECK11-NEXT: entry:5013// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 45014// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 45015// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 45016// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 45017// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 45018// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 45019// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 45020// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 85021// CHECK11-NEXT: [[TMP:%.*]] = alloca i64, align 45022// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 85023// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 85024// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 85025// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 45026// CHECK11-NEXT: [[IT:%.*]] = alloca i64, align 85027// CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 45028// CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 45029// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 45030// CHECK11-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 45031// CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 45032// CHECK11-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 45033// CHECK11-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 45034// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 45035// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 45036// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 45037// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 45038// CHECK11-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 85039// CHECK11-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 85040// CHECK11-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 85041// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 45042// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 45043// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 45044// CHECK11-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)5045// CHECK11-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_UB]], align 85046// CHECK11-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 35047// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]5048// CHECK11: cond.true:5049// CHECK11-NEXT: br label [[COND_END:%.*]]5050// CHECK11: cond.false:5051// CHECK11-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 85052// CHECK11-NEXT: br label [[COND_END]]5053// CHECK11: cond.end:5054// CHECK11-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]5055// CHECK11-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 85056// CHECK11-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_LB]], align 85057// CHECK11-NEXT: store i64 [[TMP8]], ptr [[DOTOMP_IV]], align 85058// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]5059// CHECK11: omp.inner.for.cond:5060// CHECK11-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 85061// CHECK11-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 85062// CHECK11-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]5063// CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]5064// CHECK11: omp.inner.for.body:5065// CHECK11-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 85066// CHECK11-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 4005067// CHECK11-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]5068// CHECK11-NEXT: store i64 [[SUB]], ptr [[IT]], align 85069// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 45070// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double5071// CHECK11-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+005072// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 05073// CHECK11-NEXT: store double [[ADD]], ptr [[A]], align 45074// CHECK11-NEXT: [[A4:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 05075// CHECK11-NEXT: [[TMP13:%.*]] = load double, ptr [[A4]], align 45076// CHECK11-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+005077// CHECK11-NEXT: store double [[INC]], ptr [[A4]], align 45078// CHECK11-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i165079// CHECK11-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]5080// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP14]]5081// CHECK11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 15082// CHECK11-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 25083// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]5084// CHECK11: omp.body.continue:5085// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]5086// CHECK11: omp.inner.for.inc:5087// CHECK11-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 85088// CHECK11-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 15089// CHECK11-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 85090// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]5091// CHECK11: omp.inner.for.end:5092// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]5093// CHECK11: omp.loop.exit:5094// CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])5095// CHECK11-NEXT: ret void5096//5097//5098// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l1975099// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {5100// CHECK11-NEXT: entry:5101// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 45102// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 45103// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 45104// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 45105// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 45106// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 45107// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 45108// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 45109// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 45110// CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 45111// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 45112// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 45113// CHECK11-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 45114// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 45115// CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 25116// CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 25117// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 45118// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]])5119// CHECK11-NEXT: ret void5120//5121//5122// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.omp_outlined5123// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {5124// CHECK11-NEXT: entry:5125// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 45126// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 45127// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 45128// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 45129// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 45130// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 85131// CHECK11-NEXT: [[TMP:%.*]] = alloca i64, align 45132// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 85133// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 85134// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 85135// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 45136// CHECK11-NEXT: [[I:%.*]] = alloca i64, align 85137// CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 45138// CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 45139// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 45140// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 45141// CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 45142// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 45143// CHECK11-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 85144// CHECK11-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 85145// CHECK11-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 85146// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 45147// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 45148// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 45149// CHECK11-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)5150// CHECK11-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 85151// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 65152// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]5153// CHECK11: cond.true:5154// CHECK11-NEXT: br label [[COND_END:%.*]]5155// CHECK11: cond.false:5156// CHECK11-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 85157// CHECK11-NEXT: br label [[COND_END]]5158// CHECK11: cond.end:5159// CHECK11-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]5160// CHECK11-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 85161// CHECK11-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 85162// CHECK11-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 85163// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]5164// CHECK11: omp.inner.for.cond:5165// CHECK11-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 85166// CHECK11-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 85167// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]5168// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]5169// CHECK11: omp.inner.for.body:5170// CHECK11-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 85171// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 35172// CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]5173// CHECK11-NEXT: store i64 [[ADD]], ptr [[I]], align 85174// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 45175// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 15176// CHECK11-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 45177// CHECK11-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 25178// CHECK11-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i325179// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 15180// CHECK11-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i165181// CHECK11-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 25182// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 25183// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 45184// CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 15185// CHECK11-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 45186// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]5187// CHECK11: omp.body.continue:5188// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]5189// CHECK11: omp.inner.for.inc:5190// CHECK11-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 85191// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 15192// CHECK11-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 85193// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]5194// CHECK11: omp.inner.for.end:5195// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]5196// CHECK11: omp.loop.exit:5197// CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])5198// CHECK11-NEXT: ret void5199//5200//5201// CHECK17-LABEL: define {{[^@]+}}@_Z7get_valv5202// CHECK17-SAME: () #[[ATTR0:[0-9]+]] {5203// CHECK17-NEXT: entry:5204// CHECK17-NEXT: ret i64 05205//5206//5207// CHECK17-LABEL: define {{[^@]+}}@_Z3fooi5208// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {5209// CHECK17-NEXT: entry:5210// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 45211// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 45212// CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 25213// CHECK17-NEXT: [[B:%.*]] = alloca [10 x float], align 45214// CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 85215// CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 85216// CHECK17-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 85217// CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 85218// CHECK17-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 85219// CHECK17-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 85220// CHECK17-NEXT: [[K:%.*]] = alloca i64, align 85221// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 85222// CHECK17-NEXT: [[K_CASTED:%.*]] = alloca i64, align 85223// CHECK17-NEXT: [[LIN:%.*]] = alloca i32, align 45224// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 85225// CHECK17-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 85226// CHECK17-NEXT: [[A_CASTED2:%.*]] = alloca i64, align 85227// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 85228// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 85229// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 85230// CHECK17-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 45231// CHECK17-NEXT: [[A_CASTED3:%.*]] = alloca i64, align 85232// CHECK17-NEXT: [[AA_CASTED4:%.*]] = alloca i64, align 85233// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x ptr], align 85234// CHECK17-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x ptr], align 85235// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x ptr], align 85236// CHECK17-NEXT: [[KERNEL_ARGS8:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 85237// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 45238// CHECK17-NEXT: [[A_CASTED11:%.*]] = alloca i64, align 85239// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 85240// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x ptr], align 85241// CHECK17-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x ptr], align 85242// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x ptr], align 85243// CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 85244// CHECK17-NEXT: [[KERNEL_ARGS17:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 85245// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])5246// CHECK17-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 45247// CHECK17-NEXT: store i32 0, ptr [[A]], align 45248// CHECK17-NEXT: store i16 0, ptr [[AA]], align 25249// CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 45250// CHECK17-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i645251// CHECK17-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()5252// CHECK17-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 85253// CHECK17-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 45254// CHECK17-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 85255// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 45256// CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i645257// CHECK17-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]5258// CHECK17-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 85259// CHECK17-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 85260// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 05261// CHECK17-NEXT: store i32 3, ptr [[TMP7]], align 45262// CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 15263// CHECK17-NEXT: store i32 0, ptr [[TMP8]], align 45264// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 25265// CHECK17-NEXT: store ptr null, ptr [[TMP9]], align 85266// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 35267// CHECK17-NEXT: store ptr null, ptr [[TMP10]], align 85268// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 45269// CHECK17-NEXT: store ptr null, ptr [[TMP11]], align 85270// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 55271// CHECK17-NEXT: store ptr null, ptr [[TMP12]], align 85272// CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 65273// CHECK17-NEXT: store ptr null, ptr [[TMP13]], align 85274// CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 75275// CHECK17-NEXT: store ptr null, ptr [[TMP14]], align 85276// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 85277// CHECK17-NEXT: store i64 0, ptr [[TMP15]], align 85278// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 95279// CHECK17-NEXT: store i64 0, ptr [[TMP16]], align 85280// CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 105281// CHECK17-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP17]], align 45282// CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 115283// CHECK17-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP18]], align 45284// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 125285// CHECK17-NEXT: store i32 0, ptr [[TMP19]], align 45286// CHECK17-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, ptr [[KERNEL_ARGS]])5287// CHECK17-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 05288// CHECK17-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]5289// CHECK17: omp_offload.failed:5290// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR3:[0-9]+]]5291// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]]5292// CHECK17: omp_offload.cont:5293// CHECK17-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()5294// CHECK17-NEXT: store i64 [[CALL]], ptr [[K]], align 85295// CHECK17-NEXT: [[TMP22:%.*]] = load i32, ptr [[A]], align 45296// CHECK17-NEXT: store i32 [[TMP22]], ptr [[A_CASTED]], align 45297// CHECK17-NEXT: [[TMP23:%.*]] = load i64, ptr [[A_CASTED]], align 85298// CHECK17-NEXT: [[TMP24:%.*]] = load i64, ptr [[K]], align 85299// CHECK17-NEXT: store i64 [[TMP24]], ptr [[K_CASTED]], align 85300// CHECK17-NEXT: [[TMP25:%.*]] = load i64, ptr [[K_CASTED]], align 85301// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP23]], i64 [[TMP25]]) #[[ATTR3]]5302// CHECK17-NEXT: store i32 12, ptr [[LIN]], align 45303// CHECK17-NEXT: [[TMP26:%.*]] = load i16, ptr [[AA]], align 25304// CHECK17-NEXT: store i16 [[TMP26]], ptr [[AA_CASTED]], align 25305// CHECK17-NEXT: [[TMP27:%.*]] = load i64, ptr [[AA_CASTED]], align 85306// CHECK17-NEXT: [[TMP28:%.*]] = load i32, ptr [[LIN]], align 45307// CHECK17-NEXT: store i32 [[TMP28]], ptr [[LIN_CASTED]], align 45308// CHECK17-NEXT: [[TMP29:%.*]] = load i64, ptr [[LIN_CASTED]], align 85309// CHECK17-NEXT: [[TMP30:%.*]] = load i32, ptr [[A]], align 45310// CHECK17-NEXT: store i32 [[TMP30]], ptr [[A_CASTED2]], align 45311// CHECK17-NEXT: [[TMP31:%.*]] = load i64, ptr [[A_CASTED2]], align 85312// CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 05313// CHECK17-NEXT: store i64 [[TMP27]], ptr [[TMP32]], align 85314// CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 05315// CHECK17-NEXT: store i64 [[TMP27]], ptr [[TMP33]], align 85316// CHECK17-NEXT: [[TMP34:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 05317// CHECK17-NEXT: store ptr null, ptr [[TMP34]], align 85318// CHECK17-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 15319// CHECK17-NEXT: store i64 [[TMP29]], ptr [[TMP35]], align 85320// CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 15321// CHECK17-NEXT: store i64 [[TMP29]], ptr [[TMP36]], align 85322// CHECK17-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 15323// CHECK17-NEXT: store ptr null, ptr [[TMP37]], align 85324// CHECK17-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 25325// CHECK17-NEXT: store i64 [[TMP31]], ptr [[TMP38]], align 85326// CHECK17-NEXT: [[TMP39:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 25327// CHECK17-NEXT: store i64 [[TMP31]], ptr [[TMP39]], align 85328// CHECK17-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 25329// CHECK17-NEXT: store ptr null, ptr [[TMP40]], align 85330// CHECK17-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 05331// CHECK17-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 05332// CHECK17-NEXT: [[TMP43:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 05333// CHECK17-NEXT: [[TMP44:%.*]] = load i16, ptr [[AA]], align 25334// CHECK17-NEXT: store i16 [[TMP44]], ptr [[TMP43]], align 45335// CHECK17-NEXT: [[TMP45:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 15336// CHECK17-NEXT: [[TMP46:%.*]] = load i32, ptr [[LIN]], align 45337// CHECK17-NEXT: store i32 [[TMP46]], ptr [[TMP45]], align 45338// CHECK17-NEXT: [[TMP47:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 25339// CHECK17-NEXT: [[TMP48:%.*]] = load i32, ptr [[A]], align 45340// CHECK17-NEXT: store i32 [[TMP48]], ptr [[TMP47]], align 45341// CHECK17-NEXT: [[TMP49:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, ptr @.omp_task_entry., i64 -1)5342// CHECK17-NEXT: [[TMP50:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP49]], i32 0, i32 05343// CHECK17-NEXT: [[TMP51:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP50]], i32 0, i32 05344// CHECK17-NEXT: [[TMP52:%.*]] = load ptr, ptr [[TMP51]], align 85345// CHECK17-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP52]], ptr align 4 [[AGG_CAPTURED]], i64 12, i1 false)5346// CHECK17-NEXT: [[TMP53:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP49]], i32 0, i32 15347// CHECK17-NEXT: [[TMP54:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP53]], i32 0, i32 05348// CHECK17-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP54]], ptr align 8 [[TMP41]], i64 24, i1 false)5349// CHECK17-NEXT: [[TMP55:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP53]], i32 0, i32 15350// CHECK17-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP55]], ptr align 8 [[TMP42]], i64 24, i1 false)5351// CHECK17-NEXT: [[TMP56:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP53]], i32 0, i32 25352// CHECK17-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP56]], ptr align 8 @.offload_sizes, i64 24, i1 false)5353// CHECK17-NEXT: [[TMP57:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP53]], i32 0, i32 35354// CHECK17-NEXT: [[TMP58:%.*]] = load i16, ptr [[AA]], align 25355// CHECK17-NEXT: store i16 [[TMP58]], ptr [[TMP57]], align 85356// CHECK17-NEXT: [[TMP59:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB2]], i32 [[TMP0]], ptr [[TMP49]])5357// CHECK17-NEXT: [[TMP60:%.*]] = load i32, ptr [[A]], align 45358// CHECK17-NEXT: store i32 [[TMP60]], ptr [[A_CASTED3]], align 45359// CHECK17-NEXT: [[TMP61:%.*]] = load i64, ptr [[A_CASTED3]], align 85360// CHECK17-NEXT: [[TMP62:%.*]] = load i16, ptr [[AA]], align 25361// CHECK17-NEXT: store i16 [[TMP62]], ptr [[AA_CASTED4]], align 25362// CHECK17-NEXT: [[TMP63:%.*]] = load i64, ptr [[AA_CASTED4]], align 85363// CHECK17-NEXT: [[TMP64:%.*]] = load i32, ptr [[N_ADDR]], align 45364// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP64]], 105365// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]5366// CHECK17: omp_if.then:5367// CHECK17-NEXT: [[TMP65:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 05368// CHECK17-NEXT: store i64 [[TMP61]], ptr [[TMP65]], align 85369// CHECK17-NEXT: [[TMP66:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 05370// CHECK17-NEXT: store i64 [[TMP61]], ptr [[TMP66]], align 85371// CHECK17-NEXT: [[TMP67:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 05372// CHECK17-NEXT: store ptr null, ptr [[TMP67]], align 85373// CHECK17-NEXT: [[TMP68:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 15374// CHECK17-NEXT: store i64 [[TMP63]], ptr [[TMP68]], align 85375// CHECK17-NEXT: [[TMP69:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 15376// CHECK17-NEXT: store i64 [[TMP63]], ptr [[TMP69]], align 85377// CHECK17-NEXT: [[TMP70:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 15378// CHECK17-NEXT: store ptr null, ptr [[TMP70]], align 85379// CHECK17-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 05380// CHECK17-NEXT: [[TMP72:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 05381// CHECK17-NEXT: [[TMP73:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 05382// CHECK17-NEXT: store i32 3, ptr [[TMP73]], align 45383// CHECK17-NEXT: [[TMP74:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 15384// CHECK17-NEXT: store i32 2, ptr [[TMP74]], align 45385// CHECK17-NEXT: [[TMP75:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 25386// CHECK17-NEXT: store ptr [[TMP71]], ptr [[TMP75]], align 85387// CHECK17-NEXT: [[TMP76:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 35388// CHECK17-NEXT: store ptr [[TMP72]], ptr [[TMP76]], align 85389// CHECK17-NEXT: [[TMP77:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 45390// CHECK17-NEXT: store ptr @.offload_sizes.1, ptr [[TMP77]], align 85391// CHECK17-NEXT: [[TMP78:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 55392// CHECK17-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP78]], align 85393// CHECK17-NEXT: [[TMP79:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 65394// CHECK17-NEXT: store ptr null, ptr [[TMP79]], align 85395// CHECK17-NEXT: [[TMP80:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 75396// CHECK17-NEXT: store ptr null, ptr [[TMP80]], align 85397// CHECK17-NEXT: [[TMP81:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 85398// CHECK17-NEXT: store i64 0, ptr [[TMP81]], align 85399// CHECK17-NEXT: [[TMP82:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 95400// CHECK17-NEXT: store i64 0, ptr [[TMP82]], align 85401// CHECK17-NEXT: [[TMP83:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 105402// CHECK17-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP83]], align 45403// CHECK17-NEXT: [[TMP84:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 115404// CHECK17-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP84]], align 45405// CHECK17-NEXT: [[TMP85:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 125406// CHECK17-NEXT: store i32 0, ptr [[TMP85]], align 45407// CHECK17-NEXT: [[TMP86:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.region_id, ptr [[KERNEL_ARGS8]])5408// CHECK17-NEXT: [[TMP87:%.*]] = icmp ne i32 [[TMP86]], 05409// CHECK17-NEXT: br i1 [[TMP87]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]]5410// CHECK17: omp_offload.failed9:5411// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136(i64 [[TMP61]], i64 [[TMP63]]) #[[ATTR3]]5412// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT10]]5413// CHECK17: omp_offload.cont10:5414// CHECK17-NEXT: br label [[OMP_IF_END:%.*]]5415// CHECK17: omp_if.else:5416// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136(i64 [[TMP61]], i64 [[TMP63]]) #[[ATTR3]]5417// CHECK17-NEXT: br label [[OMP_IF_END]]5418// CHECK17: omp_if.end:5419// CHECK17-NEXT: [[TMP88:%.*]] = load i32, ptr [[A]], align 45420// CHECK17-NEXT: store i32 [[TMP88]], ptr [[DOTCAPTURE_EXPR_]], align 45421// CHECK17-NEXT: [[TMP89:%.*]] = load i32, ptr [[A]], align 45422// CHECK17-NEXT: store i32 [[TMP89]], ptr [[A_CASTED11]], align 45423// CHECK17-NEXT: [[TMP90:%.*]] = load i64, ptr [[A_CASTED11]], align 85424// CHECK17-NEXT: [[TMP91:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 45425// CHECK17-NEXT: store i32 [[TMP91]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 45426// CHECK17-NEXT: [[TMP92:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 85427// CHECK17-NEXT: [[TMP93:%.*]] = load i32, ptr [[N_ADDR]], align 45428// CHECK17-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP93]], 205429// CHECK17-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE20:%.*]]5430// CHECK17: omp_if.then13:5431// CHECK17-NEXT: [[TMP94:%.*]] = mul nuw i64 [[TMP2]], 45432// CHECK17-NEXT: [[TMP95:%.*]] = mul nuw i64 5, [[TMP5]]5433// CHECK17-NEXT: [[TMP96:%.*]] = mul nuw i64 [[TMP95]], 85434// CHECK17-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.3, i64 80, i1 false)5435// CHECK17-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 05436// CHECK17-NEXT: store i64 [[TMP90]], ptr [[TMP97]], align 85437// CHECK17-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 05438// CHECK17-NEXT: store i64 [[TMP90]], ptr [[TMP98]], align 85439// CHECK17-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 05440// CHECK17-NEXT: store ptr null, ptr [[TMP99]], align 85441// CHECK17-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 15442// CHECK17-NEXT: store ptr [[B]], ptr [[TMP100]], align 85443// CHECK17-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 15444// CHECK17-NEXT: store ptr [[B]], ptr [[TMP101]], align 85445// CHECK17-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 15446// CHECK17-NEXT: store ptr null, ptr [[TMP102]], align 85447// CHECK17-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 25448// CHECK17-NEXT: store i64 [[TMP2]], ptr [[TMP103]], align 85449// CHECK17-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 25450// CHECK17-NEXT: store i64 [[TMP2]], ptr [[TMP104]], align 85451// CHECK17-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 25452// CHECK17-NEXT: store ptr null, ptr [[TMP105]], align 85453// CHECK17-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 35454// CHECK17-NEXT: store ptr [[VLA]], ptr [[TMP106]], align 85455// CHECK17-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 35456// CHECK17-NEXT: store ptr [[VLA]], ptr [[TMP107]], align 85457// CHECK17-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 35458// CHECK17-NEXT: store i64 [[TMP94]], ptr [[TMP108]], align 85459// CHECK17-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 35460// CHECK17-NEXT: store ptr null, ptr [[TMP109]], align 85461// CHECK17-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 45462// CHECK17-NEXT: store ptr [[C]], ptr [[TMP110]], align 85463// CHECK17-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 45464// CHECK17-NEXT: store ptr [[C]], ptr [[TMP111]], align 85465// CHECK17-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 45466// CHECK17-NEXT: store ptr null, ptr [[TMP112]], align 85467// CHECK17-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 55468// CHECK17-NEXT: store i64 5, ptr [[TMP113]], align 85469// CHECK17-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 55470// CHECK17-NEXT: store i64 5, ptr [[TMP114]], align 85471// CHECK17-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 55472// CHECK17-NEXT: store ptr null, ptr [[TMP115]], align 85473// CHECK17-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 65474// CHECK17-NEXT: store i64 [[TMP5]], ptr [[TMP116]], align 85475// CHECK17-NEXT: [[TMP117:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 65476// CHECK17-NEXT: store i64 [[TMP5]], ptr [[TMP117]], align 85477// CHECK17-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 65478// CHECK17-NEXT: store ptr null, ptr [[TMP118]], align 85479// CHECK17-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 75480// CHECK17-NEXT: store ptr [[VLA1]], ptr [[TMP119]], align 85481// CHECK17-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 75482// CHECK17-NEXT: store ptr [[VLA1]], ptr [[TMP120]], align 85483// CHECK17-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 75484// CHECK17-NEXT: store i64 [[TMP96]], ptr [[TMP121]], align 85485// CHECK17-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 75486// CHECK17-NEXT: store ptr null, ptr [[TMP122]], align 85487// CHECK17-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 85488// CHECK17-NEXT: store ptr [[D]], ptr [[TMP123]], align 85489// CHECK17-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 85490// CHECK17-NEXT: store ptr [[D]], ptr [[TMP124]], align 85491// CHECK17-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 85492// CHECK17-NEXT: store ptr null, ptr [[TMP125]], align 85493// CHECK17-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 95494// CHECK17-NEXT: store i64 [[TMP92]], ptr [[TMP126]], align 85495// CHECK17-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 95496// CHECK17-NEXT: store i64 [[TMP92]], ptr [[TMP127]], align 85497// CHECK17-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 95498// CHECK17-NEXT: store ptr null, ptr [[TMP128]], align 85499// CHECK17-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 05500// CHECK17-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 05501// CHECK17-NEXT: [[TMP131:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 05502// CHECK17-NEXT: [[TMP132:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 05503// CHECK17-NEXT: store i32 3, ptr [[TMP132]], align 45504// CHECK17-NEXT: [[TMP133:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 15505// CHECK17-NEXT: store i32 10, ptr [[TMP133]], align 45506// CHECK17-NEXT: [[TMP134:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 25507// CHECK17-NEXT: store ptr [[TMP129]], ptr [[TMP134]], align 85508// CHECK17-NEXT: [[TMP135:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 35509// CHECK17-NEXT: store ptr [[TMP130]], ptr [[TMP135]], align 85510// CHECK17-NEXT: [[TMP136:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 45511// CHECK17-NEXT: store ptr [[TMP131]], ptr [[TMP136]], align 85512// CHECK17-NEXT: [[TMP137:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 55513// CHECK17-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP137]], align 85514// CHECK17-NEXT: [[TMP138:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 65515// CHECK17-NEXT: store ptr null, ptr [[TMP138]], align 85516// CHECK17-NEXT: [[TMP139:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 75517// CHECK17-NEXT: store ptr null, ptr [[TMP139]], align 85518// CHECK17-NEXT: [[TMP140:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 85519// CHECK17-NEXT: store i64 0, ptr [[TMP140]], align 85520// CHECK17-NEXT: [[TMP141:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 95521// CHECK17-NEXT: store i64 0, ptr [[TMP141]], align 85522// CHECK17-NEXT: [[TMP142:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 105523// CHECK17-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP142]], align 45524// CHECK17-NEXT: [[TMP143:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 115525// CHECK17-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP143]], align 45526// CHECK17-NEXT: [[TMP144:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 125527// CHECK17-NEXT: store i32 0, ptr [[TMP144]], align 45528// CHECK17-NEXT: [[TMP145:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.region_id, ptr [[KERNEL_ARGS17]])5529// CHECK17-NEXT: [[TMP146:%.*]] = icmp ne i32 [[TMP145]], 05530// CHECK17-NEXT: br i1 [[TMP146]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]]5531// CHECK17: omp_offload.failed18:5532// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i64 [[TMP90]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP92]]) #[[ATTR3]]5533// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT19]]5534// CHECK17: omp_offload.cont19:5535// CHECK17-NEXT: br label [[OMP_IF_END21:%.*]]5536// CHECK17: omp_if.else20:5537// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i64 [[TMP90]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP92]]) #[[ATTR3]]5538// CHECK17-NEXT: br label [[OMP_IF_END21]]5539// CHECK17: omp_if.end21:5540// CHECK17-NEXT: [[TMP147:%.*]] = load i32, ptr [[A]], align 45541// CHECK17-NEXT: [[TMP148:%.*]] = load ptr, ptr [[SAVED_STACK]], align 85542// CHECK17-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP148]])5543// CHECK17-NEXT: ret i32 [[TMP147]]5544//5545//5546// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1035547// CHECK17-SAME: () #[[ATTR2:[0-9]+]] {5548// CHECK17-NEXT: entry:5549// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined)5550// CHECK17-NEXT: ret void5551//5552//5553// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined5554// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] {5555// CHECK17-NEXT: entry:5556// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 85557// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 85558// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 45559// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 45560// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 45561// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 45562// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 45563// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 45564// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 45565// CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 85566// CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 85567// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 45568// CHECK17-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 45569// CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 45570// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 45571// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 85572// CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 45573// CHECK17-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)5574// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 45575// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 55576// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]5577// CHECK17: cond.true:5578// CHECK17-NEXT: br label [[COND_END:%.*]]5579// CHECK17: cond.false:5580// CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 45581// CHECK17-NEXT: br label [[COND_END]]5582// CHECK17: cond.end:5583// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]5584// CHECK17-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 45585// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 45586// CHECK17-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 45587// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]5588// CHECK17: omp.inner.for.cond:5589// CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 45590// CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 45591// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]5592// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]5593// CHECK17: omp.inner.for.body:5594// CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 45595// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 55596// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]5597// CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 45598// CHECK17-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(ptr @[[GLOB2]], i32 [[TMP1]], i32 2)5599// CHECK17-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 05600// CHECK17-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]5601// CHECK17: .cancel.exit:5602// CHECK17-NEXT: br label [[CANCEL_EXIT:%.*]]5603// CHECK17: .cancel.continue:5604// CHECK17-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(ptr @[[GLOB2]], i32 [[TMP1]], i32 2)5605// CHECK17-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 05606// CHECK17-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]5607// CHECK17: .cancel.exit2:5608// CHECK17-NEXT: br label [[CANCEL_EXIT]]5609// CHECK17: .cancel.continue3:5610// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]5611// CHECK17: omp.body.continue:5612// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]5613// CHECK17: omp.inner.for.inc:5614// CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 45615// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 15616// CHECK17-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 45617// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]]5618// CHECK17: omp.inner.for.end:5619// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]5620// CHECK17: omp.loop.exit:5621// CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])5622// CHECK17-NEXT: br label [[CANCEL_CONT:%.*]]5623// CHECK17: cancel.cont:5624// CHECK17-NEXT: ret void5625// CHECK17: cancel.exit:5626// CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])5627// CHECK17-NEXT: br label [[CANCEL_CONT]]5628//5629//5630// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1105631// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR2]] {5632// CHECK17-NEXT: entry:5633// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 85634// CHECK17-NEXT: [[K_ADDR:%.*]] = alloca i64, align 85635// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 85636// CHECK17-NEXT: [[K_CASTED:%.*]] = alloca i64, align 85637// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 85638// CHECK17-NEXT: store i64 [[K]], ptr [[K_ADDR]], align 85639// CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 45640// CHECK17-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 45641// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 85642// CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[K_ADDR]], align 85643// CHECK17-NEXT: store i64 [[TMP2]], ptr [[K_CASTED]], align 85644// CHECK17-NEXT: [[TMP3:%.*]] = load i64, ptr [[K_CASTED]], align 85645// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined, i64 [[TMP1]], i64 [[TMP3]])5646// CHECK17-NEXT: ret void5647//5648//5649// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined5650// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR2]] {5651// CHECK17-NEXT: entry:5652// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 85653// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 85654// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 85655// CHECK17-NEXT: [[K_ADDR:%.*]] = alloca i64, align 85656// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 45657// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 45658// CHECK17-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 85659// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 45660// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 45661// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 45662// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 45663// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 45664// CHECK17-NEXT: [[K1:%.*]] = alloca i64, align 85665// CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 85666// CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 85667// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 85668// CHECK17-NEXT: store i64 [[K]], ptr [[K_ADDR]], align 85669// CHECK17-NEXT: [[TMP0:%.*]] = load i64, ptr [[K_ADDR]], align 85670// CHECK17-NEXT: store i64 [[TMP0]], ptr [[DOTLINEAR_START]], align 85671// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 45672// CHECK17-NEXT: store i32 8, ptr [[DOTOMP_UB]], align 45673// CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 45674// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 45675// CHECK17-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 85676// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 45677// CHECK17-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP2]])5678// CHECK17-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 1073741859, i32 0, i32 8, i32 1, i32 1)5679// CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]]5680// CHECK17: omp.dispatch.cond:5681// CHECK17-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB2]], i32 [[TMP2]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])5682// CHECK17-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 05683// CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]5684// CHECK17: omp.dispatch.body:5685// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 45686// CHECK17-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 45687// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]5688// CHECK17: omp.inner.for.cond:5689// CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]]5690// CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]]5691// CHECK17-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]5692// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]5693// CHECK17: omp.inner.for.body:5694// CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]5695// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 15696// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]5697// CHECK17-NEXT: store i32 [[SUB]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]]5698// CHECK17-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP12]]5699// CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]5700// CHECK17-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 35701// CHECK17-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i645702// CHECK17-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV]]5703// CHECK17-NEXT: store i64 [[ADD]], ptr [[K1]], align 8, !llvm.access.group [[ACC_GRP12]]5704// CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP12]]5705// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 15706// CHECK17-NEXT: store i32 [[ADD3]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP12]]5707// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]5708// CHECK17: omp.body.continue:5709// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]5710// CHECK17: omp.inner.for.inc:5711// CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]5712// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 15713// CHECK17-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]5714// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]5715// CHECK17: omp.inner.for.end:5716// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]]5717// CHECK17: omp.dispatch.inc:5718// CHECK17-NEXT: br label [[OMP_DISPATCH_COND]]5719// CHECK17: omp.dispatch.end:5720// CHECK17-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB2]], i32 [[TMP2]])5721// CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 45722// CHECK17-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 05723// CHECK17-NEXT: br i1 [[TMP13]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]5724// CHECK17: .omp.linear.pu:5725// CHECK17-NEXT: [[TMP14:%.*]] = load i64, ptr [[K1]], align 85726// CHECK17-NEXT: store i64 [[TMP14]], ptr [[K_ADDR]], align 85727// CHECK17-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]5728// CHECK17: .omp.linear.pu.done:5729// CHECK17-NEXT: ret void5730//5731//5732// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1285733// CHECK17-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] {5734// CHECK17-NEXT: entry:5735// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 85736// CHECK17-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 85737// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 85738// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 85739// CHECK17-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 85740// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 85741// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 85742// CHECK17-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 85743// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 85744// CHECK17-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 25745// CHECK17-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 25746// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 85747// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 45748// CHECK17-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 45749// CHECK17-NEXT: [[TMP3:%.*]] = load i64, ptr [[LIN_CASTED]], align 85750// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 45751// CHECK17-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 45752// CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[A_CASTED]], align 85753// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.omp_outlined, i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])5754// CHECK17-NEXT: ret void5755//5756//5757// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.omp_outlined5758// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] {5759// CHECK17-NEXT: entry:5760// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 85761// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 85762// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 85763// CHECK17-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 85764// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 85765// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 85766// CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 85767// CHECK17-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 45768// CHECK17-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 45769// CHECK17-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 85770// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 85771// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 85772// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 85773// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 45774// CHECK17-NEXT: [[IT:%.*]] = alloca i64, align 85775// CHECK17-NEXT: [[LIN2:%.*]] = alloca i32, align 45776// CHECK17-NEXT: [[A3:%.*]] = alloca i32, align 45777// CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 85778// CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 85779// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 85780// CHECK17-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 85781// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 85782// CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 45783// CHECK17-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 45784// CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 45785// CHECK17-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 45786// CHECK17-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()5787// CHECK17-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 85788// CHECK17-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 85789// CHECK17-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 85790// CHECK17-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 85791// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 45792// CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 85793// CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 45794// CHECK17-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP3]])5795// CHECK17-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)5796// CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 85797// CHECK17-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 35798// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]5799// CHECK17: cond.true:5800// CHECK17-NEXT: br label [[COND_END:%.*]]5801// CHECK17: cond.false:5802// CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 85803// CHECK17-NEXT: br label [[COND_END]]5804// CHECK17: cond.end:5805// CHECK17-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]5806// CHECK17-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 85807// CHECK17-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 85808// CHECK17-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 85809// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]5810// CHECK17: omp.inner.for.cond:5811// CHECK17-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 85812// CHECK17-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 85813// CHECK17-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]5814// CHECK17-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]5815// CHECK17: omp.inner.for.body:5816// CHECK17-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 85817// CHECK17-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 4005818// CHECK17-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]5819// CHECK17-NEXT: store i64 [[SUB]], ptr [[IT]], align 85820// CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 45821// CHECK17-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i645822// CHECK17-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 85823// CHECK17-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 85824// CHECK17-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]]5825// CHECK17-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]]5826// CHECK17-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i325827// CHECK17-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 45828// CHECK17-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 45829// CHECK17-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i645830// CHECK17-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 85831// CHECK17-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 85832// CHECK17-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]]5833// CHECK17-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]]5834// CHECK17-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i325835// CHECK17-NEXT: store i32 [[CONV10]], ptr [[A3]], align 45836// CHECK17-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 25837// CHECK17-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i325838// CHECK17-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 15839// CHECK17-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i165840// CHECK17-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 25841// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]5842// CHECK17: omp.body.continue:5843// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]5844// CHECK17: omp.inner.for.inc:5845// CHECK17-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 85846// CHECK17-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 15847// CHECK17-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 85848// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]]5849// CHECK17: omp.inner.for.end:5850// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]5851// CHECK17: omp.loop.exit:5852// CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]])5853// CHECK17-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 45854// CHECK17-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 05855// CHECK17-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]5856// CHECK17: .omp.linear.pu:5857// CHECK17-NEXT: [[TMP20:%.*]] = load i32, ptr [[LIN2]], align 45858// CHECK17-NEXT: store i32 [[TMP20]], ptr [[LIN_ADDR]], align 45859// CHECK17-NEXT: [[TMP21:%.*]] = load i32, ptr [[A3]], align 45860// CHECK17-NEXT: store i32 [[TMP21]], ptr [[A_ADDR]], align 45861// CHECK17-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]5862// CHECK17: .omp.linear.pu.done:5863// CHECK17-NEXT: ret void5864//5865//5866// CHECK17-LABEL: define {{[^@]+}}@.omp_task_privates_map.5867// CHECK17-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] {5868// CHECK17-NEXT: entry:5869// CHECK17-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 85870// CHECK17-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 85871// CHECK17-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 85872// CHECK17-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 85873// CHECK17-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 85874// CHECK17-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 85875// CHECK17-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 85876// CHECK17-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 85877// CHECK17-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3]], align 85878// CHECK17-NEXT: store ptr [[TMP4]], ptr [[DOTADDR4]], align 85879// CHECK17-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 85880// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP5]], i32 0, i32 05881// CHECK17-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTADDR2]], align 85882// CHECK17-NEXT: store ptr [[TMP6]], ptr [[TMP7]], align 85883// CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 15884// CHECK17-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTADDR3]], align 85885// CHECK17-NEXT: store ptr [[TMP8]], ptr [[TMP9]], align 85886// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 25887// CHECK17-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTADDR4]], align 85888// CHECK17-NEXT: store ptr [[TMP10]], ptr [[TMP11]], align 85889// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 35890// CHECK17-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTADDR1]], align 85891// CHECK17-NEXT: store ptr [[TMP12]], ptr [[TMP13]], align 85892// CHECK17-NEXT: ret void5893//5894//5895// CHECK17-LABEL: define {{[^@]+}}@.omp_task_entry.5896// CHECK17-SAME: (i32 noundef signext [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] {5897// CHECK17-NEXT: entry:5898// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 45899// CHECK17-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 85900// CHECK17-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 85901// CHECK17-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 85902// CHECK17-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 85903// CHECK17-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 85904// CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 85905// CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 85906// CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca ptr, align 85907// CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca ptr, align 85908// CHECK17-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 85909// CHECK17-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 85910// CHECK17-NEXT: [[LIN_CASTED_I:%.*]] = alloca i64, align 85911// CHECK17-NEXT: [[A_CASTED_I:%.*]] = alloca i64, align 85912// CHECK17-NEXT: [[DOTADDR:%.*]] = alloca i32, align 45913// CHECK17-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 85914// CHECK17-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 45915// CHECK17-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 85916// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 45917// CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 85918// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 05919// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 25920// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 05921// CHECK17-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 85922// CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 15923// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])5924// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])5925// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])5926// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])5927// CHECK17-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META24:![0-9]+]]5928// CHECK17-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META24]]5929// CHECK17-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META24]]5930// CHECK17-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META24]]5931// CHECK17-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META24]]5932// CHECK17-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META24]]5933// CHECK17-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META24]]5934// CHECK17-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META24]]5935// CHECK17-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META24]]5936// CHECK17-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]5937// CHECK17-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META24]]5938// CHECK17-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META24]]5939// CHECK17-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias [[META24]]5940// CHECK17-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias [[META24]]5941// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP9]], i32 0, i32 15942// CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 25943// CHECK17-NEXT: store i32 3, ptr [[KERNEL_ARGS_I]], align 4, !noalias [[META24]]5944// CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 15945// CHECK17-NEXT: store i32 3, ptr [[TMP18]], align 4, !noalias [[META24]]5946// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 25947// CHECK17-NEXT: store ptr [[TMP13]], ptr [[TMP19]], align 8, !noalias [[META24]]5948// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 35949// CHECK17-NEXT: store ptr [[TMP14]], ptr [[TMP20]], align 8, !noalias [[META24]]5950// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 45951// CHECK17-NEXT: store ptr [[TMP15]], ptr [[TMP21]], align 8, !noalias [[META24]]5952// CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 55953// CHECK17-NEXT: store ptr @.offload_maptypes, ptr [[TMP22]], align 8, !noalias [[META24]]5954// CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 65955// CHECK17-NEXT: store ptr null, ptr [[TMP23]], align 8, !noalias [[META24]]5956// CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 75957// CHECK17-NEXT: store ptr null, ptr [[TMP24]], align 8, !noalias [[META24]]5958// CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 85959// CHECK17-NEXT: store i64 0, ptr [[TMP25]], align 8, !noalias [[META24]]5960// CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 95961// CHECK17-NEXT: store i64 1, ptr [[TMP26]], align 8, !noalias [[META24]]5962// CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 105963// CHECK17-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP27]], align 4, !noalias [[META24]]5964// CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 115965// CHECK17-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4, !noalias [[META24]]5966// CHECK17-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 125967// CHECK17-NEXT: store i32 0, ptr [[TMP29]], align 4, !noalias [[META24]]5968// CHECK17-NEXT: [[TMP30:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.region_id, ptr [[KERNEL_ARGS_I]])5969// CHECK17-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 05970// CHECK17-NEXT: br i1 [[TMP31]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]]5971// CHECK17: omp_offload.failed.i:5972// CHECK17-NEXT: [[TMP32:%.*]] = load i16, ptr [[TMP12]], align 25973// CHECK17-NEXT: store i16 [[TMP32]], ptr [[AA_CASTED_I]], align 2, !noalias [[META24]]5974// CHECK17-NEXT: [[TMP33:%.*]] = load i64, ptr [[AA_CASTED_I]], align 8, !noalias [[META24]]5975// CHECK17-NEXT: [[TMP34:%.*]] = load i32, ptr [[TMP16]], align 45976// CHECK17-NEXT: store i32 [[TMP34]], ptr [[LIN_CASTED_I]], align 4, !noalias [[META24]]5977// CHECK17-NEXT: [[TMP35:%.*]] = load i64, ptr [[LIN_CASTED_I]], align 8, !noalias [[META24]]5978// CHECK17-NEXT: [[TMP36:%.*]] = load i32, ptr [[TMP17]], align 45979// CHECK17-NEXT: store i32 [[TMP36]], ptr [[A_CASTED_I]], align 4, !noalias [[META24]]5980// CHECK17-NEXT: [[TMP37:%.*]] = load i64, ptr [[A_CASTED_I]], align 8, !noalias [[META24]]5981// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128(i64 [[TMP33]], i64 [[TMP35]], i64 [[TMP37]]) #[[ATTR3]]5982// CHECK17-NEXT: br label [[DOTOMP_OUTLINED__EXIT]]5983// CHECK17: .omp_outlined..exit:5984// CHECK17-NEXT: ret i32 05985//5986//5987// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1365988// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {5989// CHECK17-NEXT: entry:5990// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 85991// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 85992// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 85993// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 85994// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 85995// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 85996// CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 45997// CHECK17-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 45998// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 85999// CHECK17-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 26000// CHECK17-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 26001// CHECK17-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 86002// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined, i64 [[TMP1]], i64 [[TMP3]])6003// CHECK17-NEXT: ret void6004//6005//6006// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined6007// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {6008// CHECK17-NEXT: entry:6009// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 86010// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 86011// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 86012// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 86013// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 46014// CHECK17-NEXT: [[TMP:%.*]] = alloca i16, align 26015// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 46016// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 46017// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 46018// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 46019// CHECK17-NEXT: [[IT:%.*]] = alloca i16, align 26020// CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 86021// CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 86022// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 86023// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 86024// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 46025// CHECK17-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 46026// CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 46027// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 46028// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 86029// CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 46030// CHECK17-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)6031// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 46032// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 36033// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]6034// CHECK17: cond.true:6035// CHECK17-NEXT: br label [[COND_END:%.*]]6036// CHECK17: cond.false:6037// CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 46038// CHECK17-NEXT: br label [[COND_END]]6039// CHECK17: cond.end:6040// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]6041// CHECK17-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 46042// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 46043// CHECK17-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 46044// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]6045// CHECK17: omp.inner.for.cond:6046// CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 46047// CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 46048// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]6049// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]6050// CHECK17: omp.inner.for.body:6051// CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 46052// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 46053// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]6054// CHECK17-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i166055// CHECK17-NEXT: store i16 [[CONV]], ptr [[IT]], align 26056// CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 46057// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 16058// CHECK17-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 46059// CHECK17-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 26060// CHECK17-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i326061// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 16062// CHECK17-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i166063// CHECK17-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 26064// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]6065// CHECK17: omp.body.continue:6066// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]6067// CHECK17: omp.inner.for.inc:6068// CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 46069// CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 16070// CHECK17-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 46071// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]]6072// CHECK17: omp.inner.for.end:6073// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]6074// CHECK17: omp.loop.exit:6075// CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])6076// CHECK17-NEXT: ret void6077//6078//6079// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1606080// CHECK17-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {6081// CHECK17-NEXT: entry:6082// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 86083// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 86084// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 86085// CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 86086// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 86087// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 86088// CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 86089// CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 86090// CHECK17-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 86091// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 86092// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 86093// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 86094// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 86095// CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 86096// CHECK17-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 86097// CHECK17-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 86098// CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 86099// CHECK17-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 86100// CHECK17-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 86101// CHECK17-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 86102// CHECK17-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 86103// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 86104// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 86105// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 86106// CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 86107// CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 86108// CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 86109// CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 86110// CHECK17-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 86111// CHECK17-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 86112// CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 46113// CHECK17-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 46114// CHECK17-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 86115// CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 46116// CHECK17-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 46117// CHECK17-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 86118// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i64 [[TMP11]])6119// CHECK17-NEXT: ret void6120//6121//6122// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined6123// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {6124// CHECK17-NEXT: entry:6125// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 86126// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 86127// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 86128// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 86129// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 86130// CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 86131// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 86132// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 86133// CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 86134// CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 86135// CHECK17-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 86136// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 86137// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 46138// CHECK17-NEXT: [[TMP:%.*]] = alloca i8, align 16139// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 46140// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 46141// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 46142// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 46143// CHECK17-NEXT: [[IT:%.*]] = alloca i8, align 16144// CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 86145// CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 86146// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 86147// CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 86148// CHECK17-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 86149// CHECK17-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 86150// CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 86151// CHECK17-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 86152// CHECK17-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 86153// CHECK17-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 86154// CHECK17-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 86155// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 86156// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 86157// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 86158// CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 86159// CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 86160// CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 86161// CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 86162// CHECK17-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 86163// CHECK17-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 86164// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 46165// CHECK17-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 46166// CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 46167// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 46168// CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 46169// CHECK17-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 86170// CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 46171// CHECK17-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])6172// CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]]6173// CHECK17: omp.dispatch.cond:6174// CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 46175// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 256176// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]6177// CHECK17: cond.true:6178// CHECK17-NEXT: br label [[COND_END:%.*]]6179// CHECK17: cond.false:6180// CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 46181// CHECK17-NEXT: br label [[COND_END]]6182// CHECK17: cond.end:6183// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]6184// CHECK17-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 46185// CHECK17-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 46186// CHECK17-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 46187// CHECK17-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 46188// CHECK17-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 46189// CHECK17-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]6190// CHECK17-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]6191// CHECK17: omp.dispatch.body:6192// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]6193// CHECK17: omp.inner.for.cond:6194// CHECK17-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 46195// CHECK17-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 46196// CHECK17-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]6197// CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]6198// CHECK17: omp.inner.for.body:6199// CHECK17-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 46200// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 16201// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]6202// CHECK17-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i86203// CHECK17-NEXT: store i8 [[CONV]], ptr [[IT]], align 16204// CHECK17-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 46205// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 16206// CHECK17-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 46207// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 26208// CHECK17-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 46209// CHECK17-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double6210// CHECK17-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+006211// CHECK17-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float6212// CHECK17-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 46213// CHECK17-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 36214// CHECK17-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 46215// CHECK17-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double6216// CHECK17-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+006217// CHECK17-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float6218// CHECK17-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 46219// CHECK17-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 16220// CHECK17-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i64 0, i64 26221// CHECK17-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 86222// CHECK17-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+006223// CHECK17-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 86224// CHECK17-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]6225// CHECK17-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP23]]6226// CHECK17-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i64 36227// CHECK17-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 86228// CHECK17-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+006229// CHECK17-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 86230// CHECK17-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 06231// CHECK17-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 86232// CHECK17-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 16233// CHECK17-NEXT: store i64 [[ADD20]], ptr [[X]], align 86234// CHECK17-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 16235// CHECK17-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 86236// CHECK17-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i326237// CHECK17-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 16238// CHECK17-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i86239// CHECK17-NEXT: store i8 [[CONV23]], ptr [[Y]], align 86240// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]6241// CHECK17: omp.body.continue:6242// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]6243// CHECK17: omp.inner.for.inc:6244// CHECK17-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 46245// CHECK17-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 16246// CHECK17-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 46247// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]]6248// CHECK17: omp.inner.for.end:6249// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]]6250// CHECK17: omp.dispatch.inc:6251// CHECK17-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 46252// CHECK17-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 46253// CHECK17-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]6254// CHECK17-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 46255// CHECK17-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 46256// CHECK17-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 46257// CHECK17-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]6258// CHECK17-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 46259// CHECK17-NEXT: br label [[OMP_DISPATCH_COND]]6260// CHECK17: omp.dispatch.end:6261// CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]])6262// CHECK17-NEXT: ret void6263//6264//6265// CHECK17-LABEL: define {{[^@]+}}@_Z3bari6266// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {6267// CHECK17-NEXT: entry:6268// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 46269// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 46270// CHECK17-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 86271// CHECK17-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 46272// CHECK17-NEXT: store i32 0, ptr [[A]], align 46273// CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 46274// CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]])6275// CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 46276// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]6277// CHECK17-NEXT: store i32 [[ADD]], ptr [[A]], align 46278// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 46279// CHECK17-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]])6280// CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 46281// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]6282// CHECK17-NEXT: store i32 [[ADD2]], ptr [[A]], align 46283// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 46284// CHECK17-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]])6285// CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 46286// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]6287// CHECK17-NEXT: store i32 [[ADD4]], ptr [[A]], align 46288// CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 46289// CHECK17-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]])6290// CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 46291// CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]6292// CHECK17-NEXT: store i32 [[ADD6]], ptr [[A]], align 46293// CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 46294// CHECK17-NEXT: ret i32 [[TMP8]]6295//6296//6297// CHECK17-LABEL: define {{[^@]+}}@_ZN2S12r1Ei6298// CHECK17-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {6299// CHECK17-NEXT: entry:6300// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 86301// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 46302// CHECK17-NEXT: [[B:%.*]] = alloca i32, align 46303// CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 86304// CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 86305// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 86306// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 86307// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 86308// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 86309// CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 86310// CHECK17-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 86311// CHECK17-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 86312// CHECK17-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 46313// CHECK17-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 86314// CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 46315// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 16316// CHECK17-NEXT: store i32 [[ADD]], ptr [[B]], align 46317// CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 46318// CHECK17-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i646319// CHECK17-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()6320// CHECK17-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 86321// CHECK17-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]6322// CHECK17-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 26323// CHECK17-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 86324// CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 46325// CHECK17-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 46326// CHECK17-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 86327// CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 46328// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 606329// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]6330// CHECK17: omp_if.then:6331// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 06332// CHECK17-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]]6333// CHECK17-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 26334// CHECK17-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.5, i64 40, i1 false)6335// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 06336// CHECK17-NEXT: store ptr [[THIS1]], ptr [[TMP10]], align 86337// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 06338// CHECK17-NEXT: store ptr [[A]], ptr [[TMP11]], align 86339// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 06340// CHECK17-NEXT: store ptr null, ptr [[TMP12]], align 86341// CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 16342// CHECK17-NEXT: store i64 [[TMP6]], ptr [[TMP13]], align 86343// CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 16344// CHECK17-NEXT: store i64 [[TMP6]], ptr [[TMP14]], align 86345// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 16346// CHECK17-NEXT: store ptr null, ptr [[TMP15]], align 86347// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 26348// CHECK17-NEXT: store i64 2, ptr [[TMP16]], align 86349// CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 26350// CHECK17-NEXT: store i64 2, ptr [[TMP17]], align 86351// CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 26352// CHECK17-NEXT: store ptr null, ptr [[TMP18]], align 86353// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 36354// CHECK17-NEXT: store i64 [[TMP2]], ptr [[TMP19]], align 86355// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 36356// CHECK17-NEXT: store i64 [[TMP2]], ptr [[TMP20]], align 86357// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 36358// CHECK17-NEXT: store ptr null, ptr [[TMP21]], align 86359// CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 46360// CHECK17-NEXT: store ptr [[VLA]], ptr [[TMP22]], align 86361// CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 46362// CHECK17-NEXT: store ptr [[VLA]], ptr [[TMP23]], align 86363// CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 46364// CHECK17-NEXT: store i64 [[TMP9]], ptr [[TMP24]], align 86365// CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 46366// CHECK17-NEXT: store ptr null, ptr [[TMP25]], align 86367// CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 06368// CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 06369// CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 06370// CHECK17-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 06371// CHECK17-NEXT: store i32 3, ptr [[TMP29]], align 46372// CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 16373// CHECK17-NEXT: store i32 5, ptr [[TMP30]], align 46374// CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 26375// CHECK17-NEXT: store ptr [[TMP26]], ptr [[TMP31]], align 86376// CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 36377// CHECK17-NEXT: store ptr [[TMP27]], ptr [[TMP32]], align 86378// CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 46379// CHECK17-NEXT: store ptr [[TMP28]], ptr [[TMP33]], align 86380// CHECK17-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 56381// CHECK17-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP34]], align 86382// CHECK17-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 66383// CHECK17-NEXT: store ptr null, ptr [[TMP35]], align 86384// CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 76385// CHECK17-NEXT: store ptr null, ptr [[TMP36]], align 86386// CHECK17-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 86387// CHECK17-NEXT: store i64 0, ptr [[TMP37]], align 86388// CHECK17-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 96389// CHECK17-NEXT: store i64 0, ptr [[TMP38]], align 86390// CHECK17-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 106391// CHECK17-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP39]], align 46392// CHECK17-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 116393// CHECK17-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP40]], align 46394// CHECK17-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 126395// CHECK17-NEXT: store i32 0, ptr [[TMP41]], align 46396// CHECK17-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.region_id, ptr [[KERNEL_ARGS]])6397// CHECK17-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 06398// CHECK17-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]6399// CHECK17: omp_offload.failed:6400// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR3]]6401// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]]6402// CHECK17: omp_offload.cont:6403// CHECK17-NEXT: br label [[OMP_IF_END:%.*]]6404// CHECK17: omp_if.else:6405// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR3]]6406// CHECK17-NEXT: br label [[OMP_IF_END]]6407// CHECK17: omp_if.end:6408// CHECK17-NEXT: [[TMP44:%.*]] = mul nsw i64 1, [[TMP2]]6409// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP44]]6410// CHECK17-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 16411// CHECK17-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 26412// CHECK17-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i326413// CHECK17-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 46414// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]]6415// CHECK17-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 86416// CHECK17-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP47]])6417// CHECK17-NEXT: ret i32 [[ADD3]]6418//6419//6420// CHECK17-LABEL: define {{[^@]+}}@_ZL7fstatici6421// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {6422// CHECK17-NEXT: entry:6423// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 46424// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 46425// CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 26426// CHECK17-NEXT: [[AAA:%.*]] = alloca i8, align 16427// CHECK17-NEXT: [[B:%.*]] = alloca [10 x i32], align 46428// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 86429// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 86430// CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 86431// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 86432// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 86433// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 86434// CHECK17-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 86435// CHECK17-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 46436// CHECK17-NEXT: store i32 0, ptr [[A]], align 46437// CHECK17-NEXT: store i16 0, ptr [[AA]], align 26438// CHECK17-NEXT: store i8 0, ptr [[AAA]], align 16439// CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 46440// CHECK17-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 46441// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 86442// CHECK17-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 26443// CHECK17-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 26444// CHECK17-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 86445// CHECK17-NEXT: [[TMP4:%.*]] = load i8, ptr [[AAA]], align 16446// CHECK17-NEXT: store i8 [[TMP4]], ptr [[AAA_CASTED]], align 16447// CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[AAA_CASTED]], align 86448// CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 46449// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 506450// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]6451// CHECK17: omp_if.then:6452// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 06453// CHECK17-NEXT: store i64 [[TMP1]], ptr [[TMP7]], align 86454// CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 06455// CHECK17-NEXT: store i64 [[TMP1]], ptr [[TMP8]], align 86456// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 06457// CHECK17-NEXT: store ptr null, ptr [[TMP9]], align 86458// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 16459// CHECK17-NEXT: store i64 [[TMP3]], ptr [[TMP10]], align 86460// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 16461// CHECK17-NEXT: store i64 [[TMP3]], ptr [[TMP11]], align 86462// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 16463// CHECK17-NEXT: store ptr null, ptr [[TMP12]], align 86464// CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 26465// CHECK17-NEXT: store i64 [[TMP5]], ptr [[TMP13]], align 86466// CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 26467// CHECK17-NEXT: store i64 [[TMP5]], ptr [[TMP14]], align 86468// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 26469// CHECK17-NEXT: store ptr null, ptr [[TMP15]], align 86470// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 36471// CHECK17-NEXT: store ptr [[B]], ptr [[TMP16]], align 86472// CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 36473// CHECK17-NEXT: store ptr [[B]], ptr [[TMP17]], align 86474// CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 36475// CHECK17-NEXT: store ptr null, ptr [[TMP18]], align 86476// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 06477// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 06478// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 06479// CHECK17-NEXT: store i32 3, ptr [[TMP21]], align 46480// CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 16481// CHECK17-NEXT: store i32 4, ptr [[TMP22]], align 46482// CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 26483// CHECK17-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 86484// CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 36485// CHECK17-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 86486// CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 46487// CHECK17-NEXT: store ptr @.offload_sizes.7, ptr [[TMP25]], align 86488// CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 56489// CHECK17-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP26]], align 86490// CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 66491// CHECK17-NEXT: store ptr null, ptr [[TMP27]], align 86492// CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 76493// CHECK17-NEXT: store ptr null, ptr [[TMP28]], align 86494// CHECK17-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 86495// CHECK17-NEXT: store i64 0, ptr [[TMP29]], align 86496// CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 96497// CHECK17-NEXT: store i64 0, ptr [[TMP30]], align 86498// CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 106499// CHECK17-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP31]], align 46500// CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 116501// CHECK17-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP32]], align 46502// CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 126503// CHECK17-NEXT: store i32 0, ptr [[TMP33]], align 46504// CHECK17-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.region_id, ptr [[KERNEL_ARGS]])6505// CHECK17-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 06506// CHECK17-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]6507// CHECK17: omp_offload.failed:6508// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR3]]6509// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]]6510// CHECK17: omp_offload.cont:6511// CHECK17-NEXT: br label [[OMP_IF_END:%.*]]6512// CHECK17: omp_if.else:6513// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR3]]6514// CHECK17-NEXT: br label [[OMP_IF_END]]6515// CHECK17: omp_if.end:6516// CHECK17-NEXT: [[TMP36:%.*]] = load i32, ptr [[A]], align 46517// CHECK17-NEXT: ret i32 [[TMP36]]6518//6519//6520// CHECK17-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i6521// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {6522// CHECK17-NEXT: entry:6523// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 46524// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 46525// CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 26526// CHECK17-NEXT: [[B:%.*]] = alloca [10 x i32], align 46527// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 86528// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 86529// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 86530// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 86531// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 86532// CHECK17-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 86533// CHECK17-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 46534// CHECK17-NEXT: store i32 0, ptr [[A]], align 46535// CHECK17-NEXT: store i16 0, ptr [[AA]], align 26536// CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 46537// CHECK17-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 46538// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 86539// CHECK17-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 26540// CHECK17-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 26541// CHECK17-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 86542// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 46543// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 406544// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]6545// CHECK17: omp_if.then:6546// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 06547// CHECK17-NEXT: store i64 [[TMP1]], ptr [[TMP5]], align 86548// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 06549// CHECK17-NEXT: store i64 [[TMP1]], ptr [[TMP6]], align 86550// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 06551// CHECK17-NEXT: store ptr null, ptr [[TMP7]], align 86552// CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 16553// CHECK17-NEXT: store i64 [[TMP3]], ptr [[TMP8]], align 86554// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 16555// CHECK17-NEXT: store i64 [[TMP3]], ptr [[TMP9]], align 86556// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 16557// CHECK17-NEXT: store ptr null, ptr [[TMP10]], align 86558// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 26559// CHECK17-NEXT: store ptr [[B]], ptr [[TMP11]], align 86560// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 26561// CHECK17-NEXT: store ptr [[B]], ptr [[TMP12]], align 86562// CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 26563// CHECK17-NEXT: store ptr null, ptr [[TMP13]], align 86564// CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 06565// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 06566// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 06567// CHECK17-NEXT: store i32 3, ptr [[TMP16]], align 46568// CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 16569// CHECK17-NEXT: store i32 3, ptr [[TMP17]], align 46570// CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 26571// CHECK17-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 86572// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 36573// CHECK17-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 86574// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 46575// CHECK17-NEXT: store ptr @.offload_sizes.9, ptr [[TMP20]], align 86576// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 56577// CHECK17-NEXT: store ptr @.offload_maptypes.10, ptr [[TMP21]], align 86578// CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 66579// CHECK17-NEXT: store ptr null, ptr [[TMP22]], align 86580// CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 76581// CHECK17-NEXT: store ptr null, ptr [[TMP23]], align 86582// CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 86583// CHECK17-NEXT: store i64 0, ptr [[TMP24]], align 86584// CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 96585// CHECK17-NEXT: store i64 0, ptr [[TMP25]], align 86586// CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 106587// CHECK17-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP26]], align 46588// CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 116589// CHECK17-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP27]], align 46590// CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 126591// CHECK17-NEXT: store i32 0, ptr [[TMP28]], align 46592// CHECK17-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.region_id, ptr [[KERNEL_ARGS]])6593// CHECK17-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 06594// CHECK17-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]6595// CHECK17: omp_offload.failed:6596// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]]6597// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]]6598// CHECK17: omp_offload.cont:6599// CHECK17-NEXT: br label [[OMP_IF_END:%.*]]6600// CHECK17: omp_if.else:6601// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]]6602// CHECK17-NEXT: br label [[OMP_IF_END]]6603// CHECK17: omp_if.end:6604// CHECK17-NEXT: [[TMP31:%.*]] = load i32, ptr [[A]], align 46605// CHECK17-NEXT: ret i32 [[TMP31]]6606//6607//6608// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l2326609// CHECK17-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {6610// CHECK17-NEXT: entry:6611// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 86612// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 86613// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 86614// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 86615// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 86616// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 86617// CHECK17-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 86618// CHECK17-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 86619// CHECK17-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 86620// CHECK17-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 86621// CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 86622// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 86623// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 86624// CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 86625// CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 86626// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 46627// CHECK17-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 46628// CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 86629// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.omp_outlined, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]])6630// CHECK17-NEXT: ret void6631//6632//6633// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.omp_outlined6634// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {6635// CHECK17-NEXT: entry:6636// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 86637// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 86638// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 86639// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 86640// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 86641// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 86642// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 86643// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 86644// CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 86645// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 86646// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 86647// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 86648// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 46649// CHECK17-NEXT: [[IT:%.*]] = alloca i64, align 86650// CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 86651// CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 86652// CHECK17-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 86653// CHECK17-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 86654// CHECK17-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 86655// CHECK17-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 86656// CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 86657// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 86658// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 86659// CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 86660// CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 86661// CHECK17-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 86662// CHECK17-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 86663// CHECK17-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 86664// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 46665// CHECK17-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 86666// CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 46667// CHECK17-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)6668// CHECK17-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_UB]], align 86669// CHECK17-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 36670// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]6671// CHECK17: cond.true:6672// CHECK17-NEXT: br label [[COND_END:%.*]]6673// CHECK17: cond.false:6674// CHECK17-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 86675// CHECK17-NEXT: br label [[COND_END]]6676// CHECK17: cond.end:6677// CHECK17-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]6678// CHECK17-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 86679// CHECK17-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_LB]], align 86680// CHECK17-NEXT: store i64 [[TMP8]], ptr [[DOTOMP_IV]], align 86681// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]6682// CHECK17: omp.inner.for.cond:6683// CHECK17-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 86684// CHECK17-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 86685// CHECK17-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]6686// CHECK17-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]6687// CHECK17: omp.inner.for.body:6688// CHECK17-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 86689// CHECK17-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 4006690// CHECK17-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]6691// CHECK17-NEXT: store i64 [[SUB]], ptr [[IT]], align 86692// CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 46693// CHECK17-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double6694// CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+006695// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 06696// CHECK17-NEXT: store double [[ADD]], ptr [[A]], align 86697// CHECK17-NEXT: [[A4:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 06698// CHECK17-NEXT: [[TMP13:%.*]] = load double, ptr [[A4]], align 86699// CHECK17-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+006700// CHECK17-NEXT: store double [[INC]], ptr [[A4]], align 86701// CHECK17-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i166702// CHECK17-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]6703// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP14]]6704// CHECK17-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 16705// CHECK17-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 26706// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]6707// CHECK17: omp.body.continue:6708// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]6709// CHECK17: omp.inner.for.inc:6710// CHECK17-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 86711// CHECK17-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 16712// CHECK17-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 86713// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]]6714// CHECK17: omp.inner.for.end:6715// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]6716// CHECK17: omp.loop.exit:6717// CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])6718// CHECK17-NEXT: ret void6719//6720//6721// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l2146722// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {6723// CHECK17-NEXT: entry:6724// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 86725// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 86726// CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 86727// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 86728// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 86729// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 86730// CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 86731// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 86732// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 86733// CHECK17-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 86734// CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 86735// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 86736// CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 46737// CHECK17-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 46738// CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 86739// CHECK17-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 26740// CHECK17-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 26741// CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 86742// CHECK17-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 16743// CHECK17-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 16744// CHECK17-NEXT: [[TMP6:%.*]] = load i64, ptr [[AAA_CASTED]], align 86745// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], ptr [[TMP0]])6746// CHECK17-NEXT: ret void6747//6748//6749// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.omp_outlined6750// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {6751// CHECK17-NEXT: entry:6752// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 86753// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 86754// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 86755// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 86756// CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 86757// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 86758// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 46759// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 46760// CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 86761// CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 86762// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 86763// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 86764// CHECK17-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 86765// CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 86766// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 86767// CHECK17-NEXT: ret void6768//6769//6770// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l1976771// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {6772// CHECK17-NEXT: entry:6773// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 86774// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 86775// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 86776// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 86777// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 86778// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 86779// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 86780// CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 86781// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 86782// CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 46783// CHECK17-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 46784// CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 86785// CHECK17-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 26786// CHECK17-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 26787// CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 86788// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]])6789// CHECK17-NEXT: ret void6790//6791//6792// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.omp_outlined6793// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {6794// CHECK17-NEXT: entry:6795// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 86796// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 86797// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 86798// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 86799// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 86800// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 86801// CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 86802// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 86803// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 86804// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 86805// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 46806// CHECK17-NEXT: [[I:%.*]] = alloca i64, align 86807// CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 86808// CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 86809// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 86810// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 86811// CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 86812// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 86813// CHECK17-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 86814// CHECK17-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 86815// CHECK17-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 86816// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 46817// CHECK17-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 86818// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 46819// CHECK17-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)6820// CHECK17-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 86821// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 66822// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]6823// CHECK17: cond.true:6824// CHECK17-NEXT: br label [[COND_END:%.*]]6825// CHECK17: cond.false:6826// CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 86827// CHECK17-NEXT: br label [[COND_END]]6828// CHECK17: cond.end:6829// CHECK17-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]6830// CHECK17-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 86831// CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 86832// CHECK17-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 86833// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]6834// CHECK17: omp.inner.for.cond:6835// CHECK17-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 86836// CHECK17-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 86837// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]6838// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]6839// CHECK17: omp.inner.for.body:6840// CHECK17-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 86841// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 36842// CHECK17-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]6843// CHECK17-NEXT: store i64 [[ADD]], ptr [[I]], align 86844// CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 46845// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 16846// CHECK17-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 46847// CHECK17-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 26848// CHECK17-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i326849// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 16850// CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i166851// CHECK17-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 26852// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 26853// CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 46854// CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 16855// CHECK17-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 46856// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]6857// CHECK17: omp.body.continue:6858// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]6859// CHECK17: omp.inner.for.inc:6860// CHECK17-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 86861// CHECK17-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 16862// CHECK17-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 86863// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]]6864// CHECK17: omp.inner.for.end:6865// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]6866// CHECK17: omp.loop.exit:6867// CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])6868// CHECK17-NEXT: ret void6869//6870//6871// CHECK19-LABEL: define {{[^@]+}}@_Z7get_valv6872// CHECK19-SAME: () #[[ATTR0:[0-9]+]] {6873// CHECK19-NEXT: entry:6874// CHECK19-NEXT: ret i64 06875//6876//6877// CHECK19-LABEL: define {{[^@]+}}@_Z3fooi6878// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {6879// CHECK19-NEXT: entry:6880// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 46881// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 46882// CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 26883// CHECK19-NEXT: [[B:%.*]] = alloca [10 x float], align 46884// CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 46885// CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 46886// CHECK19-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 86887// CHECK19-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 46888// CHECK19-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 46889// CHECK19-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 86890// CHECK19-NEXT: [[K:%.*]] = alloca i64, align 86891// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 46892// CHECK19-NEXT: [[LIN:%.*]] = alloca i32, align 46893// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 46894// CHECK19-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 46895// CHECK19-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 46896// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 46897// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 46898// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 46899// CHECK19-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 46900// CHECK19-NEXT: [[A_CASTED3:%.*]] = alloca i32, align 46901// CHECK19-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 46902// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x ptr], align 46903// CHECK19-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x ptr], align 46904// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x ptr], align 46905// CHECK19-NEXT: [[KERNEL_ARGS8:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 86906// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 46907// CHECK19-NEXT: [[A_CASTED11:%.*]] = alloca i32, align 46908// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 46909// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x ptr], align 46910// CHECK19-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x ptr], align 46911// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x ptr], align 46912// CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 46913// CHECK19-NEXT: [[KERNEL_ARGS17:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 86914// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])6915// CHECK19-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 46916// CHECK19-NEXT: store i32 0, ptr [[A]], align 46917// CHECK19-NEXT: store i16 0, ptr [[AA]], align 26918// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 46919// CHECK19-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()6920// CHECK19-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 46921// CHECK19-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 46922// CHECK19-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 46923// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 46924// CHECK19-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]6925// CHECK19-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 86926// CHECK19-NEXT: store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 46927// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 06928// CHECK19-NEXT: store i32 3, ptr [[TMP5]], align 46929// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 16930// CHECK19-NEXT: store i32 0, ptr [[TMP6]], align 46931// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 26932// CHECK19-NEXT: store ptr null, ptr [[TMP7]], align 46933// CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 36934// CHECK19-NEXT: store ptr null, ptr [[TMP8]], align 46935// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 46936// CHECK19-NEXT: store ptr null, ptr [[TMP9]], align 46937// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 56938// CHECK19-NEXT: store ptr null, ptr [[TMP10]], align 46939// CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 66940// CHECK19-NEXT: store ptr null, ptr [[TMP11]], align 46941// CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 76942// CHECK19-NEXT: store ptr null, ptr [[TMP12]], align 46943// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 86944// CHECK19-NEXT: store i64 0, ptr [[TMP13]], align 86945// CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 96946// CHECK19-NEXT: store i64 0, ptr [[TMP14]], align 86947// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 106948// CHECK19-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP15]], align 46949// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 116950// CHECK19-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 46951// CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 126952// CHECK19-NEXT: store i32 0, ptr [[TMP17]], align 46953// CHECK19-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, ptr [[KERNEL_ARGS]])6954// CHECK19-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 06955// CHECK19-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]6956// CHECK19: omp_offload.failed:6957// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR3:[0-9]+]]6958// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]]6959// CHECK19: omp_offload.cont:6960// CHECK19-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()6961// CHECK19-NEXT: store i64 [[CALL]], ptr [[K]], align 86962// CHECK19-NEXT: [[TMP20:%.*]] = load i32, ptr [[A]], align 46963// CHECK19-NEXT: store i32 [[TMP20]], ptr [[A_CASTED]], align 46964// CHECK19-NEXT: [[TMP21:%.*]] = load i32, ptr [[A_CASTED]], align 46965// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP21]], ptr [[K]]) #[[ATTR3]]6966// CHECK19-NEXT: store i32 12, ptr [[LIN]], align 46967// CHECK19-NEXT: [[TMP22:%.*]] = load i16, ptr [[AA]], align 26968// CHECK19-NEXT: store i16 [[TMP22]], ptr [[AA_CASTED]], align 26969// CHECK19-NEXT: [[TMP23:%.*]] = load i32, ptr [[AA_CASTED]], align 46970// CHECK19-NEXT: [[TMP24:%.*]] = load i32, ptr [[LIN]], align 46971// CHECK19-NEXT: store i32 [[TMP24]], ptr [[LIN_CASTED]], align 46972// CHECK19-NEXT: [[TMP25:%.*]] = load i32, ptr [[LIN_CASTED]], align 46973// CHECK19-NEXT: [[TMP26:%.*]] = load i32, ptr [[A]], align 46974// CHECK19-NEXT: store i32 [[TMP26]], ptr [[A_CASTED2]], align 46975// CHECK19-NEXT: [[TMP27:%.*]] = load i32, ptr [[A_CASTED2]], align 46976// CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 06977// CHECK19-NEXT: store i32 [[TMP23]], ptr [[TMP28]], align 46978// CHECK19-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 06979// CHECK19-NEXT: store i32 [[TMP23]], ptr [[TMP29]], align 46980// CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 06981// CHECK19-NEXT: store ptr null, ptr [[TMP30]], align 46982// CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 16983// CHECK19-NEXT: store i32 [[TMP25]], ptr [[TMP31]], align 46984// CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 16985// CHECK19-NEXT: store i32 [[TMP25]], ptr [[TMP32]], align 46986// CHECK19-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 16987// CHECK19-NEXT: store ptr null, ptr [[TMP33]], align 46988// CHECK19-NEXT: [[TMP34:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 26989// CHECK19-NEXT: store i32 [[TMP27]], ptr [[TMP34]], align 46990// CHECK19-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 26991// CHECK19-NEXT: store i32 [[TMP27]], ptr [[TMP35]], align 46992// CHECK19-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 26993// CHECK19-NEXT: store ptr null, ptr [[TMP36]], align 46994// CHECK19-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 06995// CHECK19-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 06996// CHECK19-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 06997// CHECK19-NEXT: [[TMP40:%.*]] = load i16, ptr [[AA]], align 26998// CHECK19-NEXT: store i16 [[TMP40]], ptr [[TMP39]], align 46999// CHECK19-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 17000// CHECK19-NEXT: [[TMP42:%.*]] = load i32, ptr [[LIN]], align 47001// CHECK19-NEXT: store i32 [[TMP42]], ptr [[TMP41]], align 47002// CHECK19-NEXT: [[TMP43:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 27003// CHECK19-NEXT: [[TMP44:%.*]] = load i32, ptr [[A]], align 47004// CHECK19-NEXT: store i32 [[TMP44]], ptr [[TMP43]], align 47005// CHECK19-NEXT: [[TMP45:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, ptr @.omp_task_entry., i64 -1)7006// CHECK19-NEXT: [[TMP46:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP45]], i32 0, i32 07007// CHECK19-NEXT: [[TMP47:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP46]], i32 0, i32 07008// CHECK19-NEXT: [[TMP48:%.*]] = load ptr, ptr [[TMP47]], align 47009// CHECK19-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP48]], ptr align 4 [[AGG_CAPTURED]], i32 12, i1 false)7010// CHECK19-NEXT: [[TMP49:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP45]], i32 0, i32 17011// CHECK19-NEXT: [[TMP50:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP49]], i32 0, i32 07012// CHECK19-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP50]], ptr align 4 @.offload_sizes, i32 24, i1 false)7013// CHECK19-NEXT: [[TMP51:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP49]], i32 0, i32 17014// CHECK19-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP51]], ptr align 4 [[TMP37]], i32 12, i1 false)7015// CHECK19-NEXT: [[TMP52:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP49]], i32 0, i32 27016// CHECK19-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP52]], ptr align 4 [[TMP38]], i32 12, i1 false)7017// CHECK19-NEXT: [[TMP53:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP49]], i32 0, i32 37018// CHECK19-NEXT: [[TMP54:%.*]] = load i16, ptr [[AA]], align 27019// CHECK19-NEXT: store i16 [[TMP54]], ptr [[TMP53]], align 47020// CHECK19-NEXT: [[TMP55:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB2]], i32 [[TMP0]], ptr [[TMP45]])7021// CHECK19-NEXT: [[TMP56:%.*]] = load i32, ptr [[A]], align 47022// CHECK19-NEXT: store i32 [[TMP56]], ptr [[A_CASTED3]], align 47023// CHECK19-NEXT: [[TMP57:%.*]] = load i32, ptr [[A_CASTED3]], align 47024// CHECK19-NEXT: [[TMP58:%.*]] = load i16, ptr [[AA]], align 27025// CHECK19-NEXT: store i16 [[TMP58]], ptr [[AA_CASTED4]], align 27026// CHECK19-NEXT: [[TMP59:%.*]] = load i32, ptr [[AA_CASTED4]], align 47027// CHECK19-NEXT: [[TMP60:%.*]] = load i32, ptr [[N_ADDR]], align 47028// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP60]], 107029// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]7030// CHECK19: omp_if.then:7031// CHECK19-NEXT: [[TMP61:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 07032// CHECK19-NEXT: store i32 [[TMP57]], ptr [[TMP61]], align 47033// CHECK19-NEXT: [[TMP62:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 07034// CHECK19-NEXT: store i32 [[TMP57]], ptr [[TMP62]], align 47035// CHECK19-NEXT: [[TMP63:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 07036// CHECK19-NEXT: store ptr null, ptr [[TMP63]], align 47037// CHECK19-NEXT: [[TMP64:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 17038// CHECK19-NEXT: store i32 [[TMP59]], ptr [[TMP64]], align 47039// CHECK19-NEXT: [[TMP65:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 17040// CHECK19-NEXT: store i32 [[TMP59]], ptr [[TMP65]], align 47041// CHECK19-NEXT: [[TMP66:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 17042// CHECK19-NEXT: store ptr null, ptr [[TMP66]], align 47043// CHECK19-NEXT: [[TMP67:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 07044// CHECK19-NEXT: [[TMP68:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 07045// CHECK19-NEXT: [[TMP69:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 07046// CHECK19-NEXT: store i32 3, ptr [[TMP69]], align 47047// CHECK19-NEXT: [[TMP70:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 17048// CHECK19-NEXT: store i32 2, ptr [[TMP70]], align 47049// CHECK19-NEXT: [[TMP71:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 27050// CHECK19-NEXT: store ptr [[TMP67]], ptr [[TMP71]], align 47051// CHECK19-NEXT: [[TMP72:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 37052// CHECK19-NEXT: store ptr [[TMP68]], ptr [[TMP72]], align 47053// CHECK19-NEXT: [[TMP73:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 47054// CHECK19-NEXT: store ptr @.offload_sizes.1, ptr [[TMP73]], align 47055// CHECK19-NEXT: [[TMP74:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 57056// CHECK19-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP74]], align 47057// CHECK19-NEXT: [[TMP75:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 67058// CHECK19-NEXT: store ptr null, ptr [[TMP75]], align 47059// CHECK19-NEXT: [[TMP76:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 77060// CHECK19-NEXT: store ptr null, ptr [[TMP76]], align 47061// CHECK19-NEXT: [[TMP77:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 87062// CHECK19-NEXT: store i64 0, ptr [[TMP77]], align 87063// CHECK19-NEXT: [[TMP78:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 97064// CHECK19-NEXT: store i64 0, ptr [[TMP78]], align 87065// CHECK19-NEXT: [[TMP79:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 107066// CHECK19-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP79]], align 47067// CHECK19-NEXT: [[TMP80:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 117068// CHECK19-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP80]], align 47069// CHECK19-NEXT: [[TMP81:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 127070// CHECK19-NEXT: store i32 0, ptr [[TMP81]], align 47071// CHECK19-NEXT: [[TMP82:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.region_id, ptr [[KERNEL_ARGS8]])7072// CHECK19-NEXT: [[TMP83:%.*]] = icmp ne i32 [[TMP82]], 07073// CHECK19-NEXT: br i1 [[TMP83]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]]7074// CHECK19: omp_offload.failed9:7075// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136(i32 [[TMP57]], i32 [[TMP59]]) #[[ATTR3]]7076// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT10]]7077// CHECK19: omp_offload.cont10:7078// CHECK19-NEXT: br label [[OMP_IF_END:%.*]]7079// CHECK19: omp_if.else:7080// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136(i32 [[TMP57]], i32 [[TMP59]]) #[[ATTR3]]7081// CHECK19-NEXT: br label [[OMP_IF_END]]7082// CHECK19: omp_if.end:7083// CHECK19-NEXT: [[TMP84:%.*]] = load i32, ptr [[A]], align 47084// CHECK19-NEXT: store i32 [[TMP84]], ptr [[DOTCAPTURE_EXPR_]], align 47085// CHECK19-NEXT: [[TMP85:%.*]] = load i32, ptr [[A]], align 47086// CHECK19-NEXT: store i32 [[TMP85]], ptr [[A_CASTED11]], align 47087// CHECK19-NEXT: [[TMP86:%.*]] = load i32, ptr [[A_CASTED11]], align 47088// CHECK19-NEXT: [[TMP87:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 47089// CHECK19-NEXT: store i32 [[TMP87]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 47090// CHECK19-NEXT: [[TMP88:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 47091// CHECK19-NEXT: [[TMP89:%.*]] = load i32, ptr [[N_ADDR]], align 47092// CHECK19-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP89]], 207093// CHECK19-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE20:%.*]]7094// CHECK19: omp_if.then13:7095// CHECK19-NEXT: [[TMP90:%.*]] = mul nuw i32 [[TMP1]], 47096// CHECK19-NEXT: [[TMP91:%.*]] = sext i32 [[TMP90]] to i647097// CHECK19-NEXT: [[TMP92:%.*]] = mul nuw i32 5, [[TMP3]]7098// CHECK19-NEXT: [[TMP93:%.*]] = mul nuw i32 [[TMP92]], 87099// CHECK19-NEXT: [[TMP94:%.*]] = sext i32 [[TMP93]] to i647100// CHECK19-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.3, i32 80, i1 false)7101// CHECK19-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 07102// CHECK19-NEXT: store i32 [[TMP86]], ptr [[TMP95]], align 47103// CHECK19-NEXT: [[TMP96:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 07104// CHECK19-NEXT: store i32 [[TMP86]], ptr [[TMP96]], align 47105// CHECK19-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 07106// CHECK19-NEXT: store ptr null, ptr [[TMP97]], align 47107// CHECK19-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 17108// CHECK19-NEXT: store ptr [[B]], ptr [[TMP98]], align 47109// CHECK19-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 17110// CHECK19-NEXT: store ptr [[B]], ptr [[TMP99]], align 47111// CHECK19-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 17112// CHECK19-NEXT: store ptr null, ptr [[TMP100]], align 47113// CHECK19-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 27114// CHECK19-NEXT: store i32 [[TMP1]], ptr [[TMP101]], align 47115// CHECK19-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 27116// CHECK19-NEXT: store i32 [[TMP1]], ptr [[TMP102]], align 47117// CHECK19-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 27118// CHECK19-NEXT: store ptr null, ptr [[TMP103]], align 47119// CHECK19-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 37120// CHECK19-NEXT: store ptr [[VLA]], ptr [[TMP104]], align 47121// CHECK19-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 37122// CHECK19-NEXT: store ptr [[VLA]], ptr [[TMP105]], align 47123// CHECK19-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 37124// CHECK19-NEXT: store i64 [[TMP91]], ptr [[TMP106]], align 47125// CHECK19-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 37126// CHECK19-NEXT: store ptr null, ptr [[TMP107]], align 47127// CHECK19-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 47128// CHECK19-NEXT: store ptr [[C]], ptr [[TMP108]], align 47129// CHECK19-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 47130// CHECK19-NEXT: store ptr [[C]], ptr [[TMP109]], align 47131// CHECK19-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 47132// CHECK19-NEXT: store ptr null, ptr [[TMP110]], align 47133// CHECK19-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 57134// CHECK19-NEXT: store i32 5, ptr [[TMP111]], align 47135// CHECK19-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 57136// CHECK19-NEXT: store i32 5, ptr [[TMP112]], align 47137// CHECK19-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 57138// CHECK19-NEXT: store ptr null, ptr [[TMP113]], align 47139// CHECK19-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 67140// CHECK19-NEXT: store i32 [[TMP3]], ptr [[TMP114]], align 47141// CHECK19-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 67142// CHECK19-NEXT: store i32 [[TMP3]], ptr [[TMP115]], align 47143// CHECK19-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 67144// CHECK19-NEXT: store ptr null, ptr [[TMP116]], align 47145// CHECK19-NEXT: [[TMP117:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 77146// CHECK19-NEXT: store ptr [[VLA1]], ptr [[TMP117]], align 47147// CHECK19-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 77148// CHECK19-NEXT: store ptr [[VLA1]], ptr [[TMP118]], align 47149// CHECK19-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 77150// CHECK19-NEXT: store i64 [[TMP94]], ptr [[TMP119]], align 47151// CHECK19-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 77152// CHECK19-NEXT: store ptr null, ptr [[TMP120]], align 47153// CHECK19-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 87154// CHECK19-NEXT: store ptr [[D]], ptr [[TMP121]], align 47155// CHECK19-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 87156// CHECK19-NEXT: store ptr [[D]], ptr [[TMP122]], align 47157// CHECK19-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 87158// CHECK19-NEXT: store ptr null, ptr [[TMP123]], align 47159// CHECK19-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 97160// CHECK19-NEXT: store i32 [[TMP88]], ptr [[TMP124]], align 47161// CHECK19-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 97162// CHECK19-NEXT: store i32 [[TMP88]], ptr [[TMP125]], align 47163// CHECK19-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 97164// CHECK19-NEXT: store ptr null, ptr [[TMP126]], align 47165// CHECK19-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 07166// CHECK19-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 07167// CHECK19-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 07168// CHECK19-NEXT: [[TMP130:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 07169// CHECK19-NEXT: store i32 3, ptr [[TMP130]], align 47170// CHECK19-NEXT: [[TMP131:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 17171// CHECK19-NEXT: store i32 10, ptr [[TMP131]], align 47172// CHECK19-NEXT: [[TMP132:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 27173// CHECK19-NEXT: store ptr [[TMP127]], ptr [[TMP132]], align 47174// CHECK19-NEXT: [[TMP133:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 37175// CHECK19-NEXT: store ptr [[TMP128]], ptr [[TMP133]], align 47176// CHECK19-NEXT: [[TMP134:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 47177// CHECK19-NEXT: store ptr [[TMP129]], ptr [[TMP134]], align 47178// CHECK19-NEXT: [[TMP135:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 57179// CHECK19-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP135]], align 47180// CHECK19-NEXT: [[TMP136:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 67181// CHECK19-NEXT: store ptr null, ptr [[TMP136]], align 47182// CHECK19-NEXT: [[TMP137:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 77183// CHECK19-NEXT: store ptr null, ptr [[TMP137]], align 47184// CHECK19-NEXT: [[TMP138:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 87185// CHECK19-NEXT: store i64 0, ptr [[TMP138]], align 87186// CHECK19-NEXT: [[TMP139:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 97187// CHECK19-NEXT: store i64 0, ptr [[TMP139]], align 87188// CHECK19-NEXT: [[TMP140:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 107189// CHECK19-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP140]], align 47190// CHECK19-NEXT: [[TMP141:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 117191// CHECK19-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP141]], align 47192// CHECK19-NEXT: [[TMP142:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 127193// CHECK19-NEXT: store i32 0, ptr [[TMP142]], align 47194// CHECK19-NEXT: [[TMP143:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.region_id, ptr [[KERNEL_ARGS17]])7195// CHECK19-NEXT: [[TMP144:%.*]] = icmp ne i32 [[TMP143]], 07196// CHECK19-NEXT: br i1 [[TMP144]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]]7197// CHECK19: omp_offload.failed18:7198// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i32 [[TMP86]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP88]]) #[[ATTR3]]7199// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT19]]7200// CHECK19: omp_offload.cont19:7201// CHECK19-NEXT: br label [[OMP_IF_END21:%.*]]7202// CHECK19: omp_if.else20:7203// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i32 [[TMP86]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP88]]) #[[ATTR3]]7204// CHECK19-NEXT: br label [[OMP_IF_END21]]7205// CHECK19: omp_if.end21:7206// CHECK19-NEXT: [[TMP145:%.*]] = load i32, ptr [[A]], align 47207// CHECK19-NEXT: [[TMP146:%.*]] = load ptr, ptr [[SAVED_STACK]], align 47208// CHECK19-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP146]])7209// CHECK19-NEXT: ret i32 [[TMP145]]7210//7211//7212// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1037213// CHECK19-SAME: () #[[ATTR2:[0-9]+]] {7214// CHECK19-NEXT: entry:7215// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined)7216// CHECK19-NEXT: ret void7217//7218//7219// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined7220// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] {7221// CHECK19-NEXT: entry:7222// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 47223// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 47224// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 47225// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 47226// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 47227// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 47228// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 47229// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 47230// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 47231// CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 47232// CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 47233// CHECK19-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 47234// CHECK19-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 47235// CHECK19-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 47236// CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 47237// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 47238// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 47239// CHECK19-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)7240// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 47241// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 57242// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]7243// CHECK19: cond.true:7244// CHECK19-NEXT: br label [[COND_END:%.*]]7245// CHECK19: cond.false:7246// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 47247// CHECK19-NEXT: br label [[COND_END]]7248// CHECK19: cond.end:7249// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]7250// CHECK19-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 47251// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 47252// CHECK19-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 47253// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]7254// CHECK19: omp.inner.for.cond:7255// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 47256// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 47257// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]7258// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]7259// CHECK19: omp.inner.for.body:7260// CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 47261// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 57262// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]7263// CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 47264// CHECK19-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(ptr @[[GLOB2]], i32 [[TMP1]], i32 2)7265// CHECK19-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 07266// CHECK19-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]7267// CHECK19: .cancel.exit:7268// CHECK19-NEXT: br label [[CANCEL_EXIT:%.*]]7269// CHECK19: .cancel.continue:7270// CHECK19-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(ptr @[[GLOB2]], i32 [[TMP1]], i32 2)7271// CHECK19-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 07272// CHECK19-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]7273// CHECK19: .cancel.exit2:7274// CHECK19-NEXT: br label [[CANCEL_EXIT]]7275// CHECK19: .cancel.continue3:7276// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]7277// CHECK19: omp.body.continue:7278// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]7279// CHECK19: omp.inner.for.inc:7280// CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 47281// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 17282// CHECK19-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 47283// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]]7284// CHECK19: omp.inner.for.end:7285// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]7286// CHECK19: omp.loop.exit:7287// CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])7288// CHECK19-NEXT: br label [[CANCEL_CONT:%.*]]7289// CHECK19: cancel.cont:7290// CHECK19-NEXT: ret void7291// CHECK19: cancel.exit:7292// CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])7293// CHECK19-NEXT: br label [[CANCEL_CONT]]7294//7295//7296// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1107297// CHECK19-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR2]] {7298// CHECK19-NEXT: entry:7299// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 47300// CHECK19-NEXT: [[K_ADDR:%.*]] = alloca ptr, align 47301// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 47302// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 47303// CHECK19-NEXT: store ptr [[K]], ptr [[K_ADDR]], align 47304// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[K_ADDR]], align 47305// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 47306// CHECK19-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 47307// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 47308// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined, i32 [[TMP2]], ptr [[TMP0]])7309// CHECK19-NEXT: ret void7310//7311//7312// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined7313// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR2]] {7314// CHECK19-NEXT: entry:7315// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 47316// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 47317// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 47318// CHECK19-NEXT: [[K_ADDR:%.*]] = alloca ptr, align 47319// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 47320// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 47321// CHECK19-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 87322// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 47323// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 47324// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 47325// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 47326// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 47327// CHECK19-NEXT: [[K1:%.*]] = alloca i64, align 87328// CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 47329// CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 47330// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 47331// CHECK19-NEXT: store ptr [[K]], ptr [[K_ADDR]], align 47332// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[K_ADDR]], align 47333// CHECK19-NEXT: [[TMP1:%.*]] = load i64, ptr [[TMP0]], align 87334// CHECK19-NEXT: store i64 [[TMP1]], ptr [[DOTLINEAR_START]], align 87335// CHECK19-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 47336// CHECK19-NEXT: store i32 8, ptr [[DOTOMP_UB]], align 47337// CHECK19-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 47338// CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 47339// CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 47340// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 47341// CHECK19-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP3]])7342// CHECK19-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 1073741859, i32 0, i32 8, i32 1, i32 1)7343// CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]]7344// CHECK19: omp.dispatch.cond:7345// CHECK19-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB2]], i32 [[TMP3]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])7346// CHECK19-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 07347// CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]7348// CHECK19: omp.dispatch.body:7349// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 47350// CHECK19-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 47351// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]7352// CHECK19: omp.inner.for.cond:7353// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13:![0-9]+]]7354// CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP13]]7355// CHECK19-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]7356// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]7357// CHECK19: omp.inner.for.body:7358// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]7359// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 17360// CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]7361// CHECK19-NEXT: store i32 [[SUB]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]]7362// CHECK19-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP13]]7363// CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]7364// CHECK19-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 37365// CHECK19-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i647366// CHECK19-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]]7367// CHECK19-NEXT: store i64 [[ADD]], ptr [[K1]], align 8, !llvm.access.group [[ACC_GRP13]]7368// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP13]]7369// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 17370// CHECK19-NEXT: store i32 [[ADD3]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP13]]7371// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]7372// CHECK19: omp.body.continue:7373// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]7374// CHECK19: omp.inner.for.inc:7375// CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]7376// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 17377// CHECK19-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]7378// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]7379// CHECK19: omp.inner.for.end:7380// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]]7381// CHECK19: omp.dispatch.inc:7382// CHECK19-NEXT: br label [[OMP_DISPATCH_COND]]7383// CHECK19: omp.dispatch.end:7384// CHECK19-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB2]], i32 [[TMP3]])7385// CHECK19-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 47386// CHECK19-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 07387// CHECK19-NEXT: br i1 [[TMP14]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]7388// CHECK19: .omp.linear.pu:7389// CHECK19-NEXT: [[TMP15:%.*]] = load i64, ptr [[K1]], align 87390// CHECK19-NEXT: store i64 [[TMP15]], ptr [[TMP0]], align 87391// CHECK19-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]7392// CHECK19: .omp.linear.pu.done:7393// CHECK19-NEXT: ret void7394//7395//7396// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1287397// CHECK19-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] {7398// CHECK19-NEXT: entry:7399// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 47400// CHECK19-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 47401// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 47402// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 47403// CHECK19-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 47404// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 47405// CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 47406// CHECK19-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 47407// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 47408// CHECK19-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 27409// CHECK19-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 27410// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 47411// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 47412// CHECK19-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 47413// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[LIN_CASTED]], align 47414// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 47415// CHECK19-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 47416// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[A_CASTED]], align 47417// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.omp_outlined, i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])7418// CHECK19-NEXT: ret void7419//7420//7421// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.omp_outlined7422// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] {7423// CHECK19-NEXT: entry:7424// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 47425// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 47426// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 47427// CHECK19-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 47428// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 47429// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 87430// CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 47431// CHECK19-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 47432// CHECK19-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 47433// CHECK19-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 87434// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 87435// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 87436// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 87437// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 47438// CHECK19-NEXT: [[IT:%.*]] = alloca i64, align 87439// CHECK19-NEXT: [[LIN2:%.*]] = alloca i32, align 47440// CHECK19-NEXT: [[A3:%.*]] = alloca i32, align 47441// CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 47442// CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 47443// CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 47444// CHECK19-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 47445// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 47446// CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 47447// CHECK19-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 47448// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 47449// CHECK19-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 47450// CHECK19-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()7451// CHECK19-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 87452// CHECK19-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 87453// CHECK19-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 87454// CHECK19-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 87455// CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 47456// CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 47457// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 47458// CHECK19-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP3]])7459// CHECK19-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)7460// CHECK19-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 87461// CHECK19-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 37462// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]7463// CHECK19: cond.true:7464// CHECK19-NEXT: br label [[COND_END:%.*]]7465// CHECK19: cond.false:7466// CHECK19-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 87467// CHECK19-NEXT: br label [[COND_END]]7468// CHECK19: cond.end:7469// CHECK19-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]7470// CHECK19-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 87471// CHECK19-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 87472// CHECK19-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 87473// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]7474// CHECK19: omp.inner.for.cond:7475// CHECK19-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 87476// CHECK19-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 87477// CHECK19-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]7478// CHECK19-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]7479// CHECK19: omp.inner.for.body:7480// CHECK19-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 87481// CHECK19-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 4007482// CHECK19-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]7483// CHECK19-NEXT: store i64 [[SUB]], ptr [[IT]], align 87484// CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 47485// CHECK19-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i647486// CHECK19-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 87487// CHECK19-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 87488// CHECK19-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]]7489// CHECK19-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]]7490// CHECK19-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i327491// CHECK19-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 47492// CHECK19-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 47493// CHECK19-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i647494// CHECK19-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 87495// CHECK19-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 87496// CHECK19-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]]7497// CHECK19-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]]7498// CHECK19-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i327499// CHECK19-NEXT: store i32 [[CONV10]], ptr [[A3]], align 47500// CHECK19-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 27501// CHECK19-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i327502// CHECK19-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 17503// CHECK19-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i167504// CHECK19-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 27505// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]7506// CHECK19: omp.body.continue:7507// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]7508// CHECK19: omp.inner.for.inc:7509// CHECK19-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 87510// CHECK19-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 17511// CHECK19-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 87512// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]]7513// CHECK19: omp.inner.for.end:7514// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]7515// CHECK19: omp.loop.exit:7516// CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]])7517// CHECK19-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 47518// CHECK19-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 07519// CHECK19-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]7520// CHECK19: .omp.linear.pu:7521// CHECK19-NEXT: [[TMP20:%.*]] = load i32, ptr [[LIN2]], align 47522// CHECK19-NEXT: store i32 [[TMP20]], ptr [[LIN_ADDR]], align 47523// CHECK19-NEXT: [[TMP21:%.*]] = load i32, ptr [[A3]], align 47524// CHECK19-NEXT: store i32 [[TMP21]], ptr [[A_ADDR]], align 47525// CHECK19-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]7526// CHECK19: .omp.linear.pu.done:7527// CHECK19-NEXT: ret void7528//7529//7530// CHECK19-LABEL: define {{[^@]+}}@.omp_task_privates_map.7531// CHECK19-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] {7532// CHECK19-NEXT: entry:7533// CHECK19-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 47534// CHECK19-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 47535// CHECK19-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 47536// CHECK19-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 47537// CHECK19-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 47538// CHECK19-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 47539// CHECK19-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 47540// CHECK19-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 47541// CHECK19-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3]], align 47542// CHECK19-NEXT: store ptr [[TMP4]], ptr [[DOTADDR4]], align 47543// CHECK19-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 47544// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP5]], i32 0, i32 07545// CHECK19-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTADDR4]], align 47546// CHECK19-NEXT: store ptr [[TMP6]], ptr [[TMP7]], align 47547// CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 17548// CHECK19-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTADDR2]], align 47549// CHECK19-NEXT: store ptr [[TMP8]], ptr [[TMP9]], align 47550// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 27551// CHECK19-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTADDR3]], align 47552// CHECK19-NEXT: store ptr [[TMP10]], ptr [[TMP11]], align 47553// CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 37554// CHECK19-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTADDR1]], align 47555// CHECK19-NEXT: store ptr [[TMP12]], ptr [[TMP13]], align 47556// CHECK19-NEXT: ret void7557//7558//7559// CHECK19-LABEL: define {{[^@]+}}@.omp_task_entry.7560// CHECK19-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] {7561// CHECK19-NEXT: entry:7562// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 47563// CHECK19-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 47564// CHECK19-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 47565// CHECK19-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 47566// CHECK19-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 47567// CHECK19-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 47568// CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 47569// CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 47570// CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca ptr, align 47571// CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca ptr, align 47572// CHECK19-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 87573// CHECK19-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 47574// CHECK19-NEXT: [[LIN_CASTED_I:%.*]] = alloca i32, align 47575// CHECK19-NEXT: [[A_CASTED_I:%.*]] = alloca i32, align 47576// CHECK19-NEXT: [[DOTADDR:%.*]] = alloca i32, align 47577// CHECK19-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 47578// CHECK19-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 47579// CHECK19-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 47580// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 47581// CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 47582// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 07583// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 27584// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 07585// CHECK19-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 47586// CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 17587// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])7588// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])7589// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])7590// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])7591// CHECK19-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META25:![0-9]+]]7592// CHECK19-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 4, !noalias [[META25]]7593// CHECK19-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias [[META25]]7594// CHECK19-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias [[META25]]7595// CHECK19-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 4, !noalias [[META25]]7596// CHECK19-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 4, !noalias [[META25]]7597// CHECK19-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias [[META25]]7598// CHECK19-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias [[META25]]7599// CHECK19-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias [[META25]]7600// CHECK19-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]7601// CHECK19-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias [[META25]]7602// CHECK19-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias [[META25]]7603// CHECK19-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias [[META25]]7604// CHECK19-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias [[META25]]7605// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP9]], i32 0, i32 17606// CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 27607// CHECK19-NEXT: store i32 3, ptr [[KERNEL_ARGS_I]], align 4, !noalias [[META25]]7608// CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 17609// CHECK19-NEXT: store i32 3, ptr [[TMP18]], align 4, !noalias [[META25]]7610// CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 27611// CHECK19-NEXT: store ptr [[TMP13]], ptr [[TMP19]], align 4, !noalias [[META25]]7612// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 37613// CHECK19-NEXT: store ptr [[TMP14]], ptr [[TMP20]], align 4, !noalias [[META25]]7614// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 47615// CHECK19-NEXT: store ptr [[TMP15]], ptr [[TMP21]], align 4, !noalias [[META25]]7616// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 57617// CHECK19-NEXT: store ptr @.offload_maptypes, ptr [[TMP22]], align 4, !noalias [[META25]]7618// CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 67619// CHECK19-NEXT: store ptr null, ptr [[TMP23]], align 4, !noalias [[META25]]7620// CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 77621// CHECK19-NEXT: store ptr null, ptr [[TMP24]], align 4, !noalias [[META25]]7622// CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 87623// CHECK19-NEXT: store i64 0, ptr [[TMP25]], align 8, !noalias [[META25]]7624// CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 97625// CHECK19-NEXT: store i64 1, ptr [[TMP26]], align 8, !noalias [[META25]]7626// CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 107627// CHECK19-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP27]], align 4, !noalias [[META25]]7628// CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 117629// CHECK19-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4, !noalias [[META25]]7630// CHECK19-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 127631// CHECK19-NEXT: store i32 0, ptr [[TMP29]], align 4, !noalias [[META25]]7632// CHECK19-NEXT: [[TMP30:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.region_id, ptr [[KERNEL_ARGS_I]])7633// CHECK19-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 07634// CHECK19-NEXT: br i1 [[TMP31]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]]7635// CHECK19: omp_offload.failed.i:7636// CHECK19-NEXT: [[TMP32:%.*]] = load i16, ptr [[TMP12]], align 27637// CHECK19-NEXT: store i16 [[TMP32]], ptr [[AA_CASTED_I]], align 2, !noalias [[META25]]7638// CHECK19-NEXT: [[TMP33:%.*]] = load i32, ptr [[AA_CASTED_I]], align 4, !noalias [[META25]]7639// CHECK19-NEXT: [[TMP34:%.*]] = load i32, ptr [[TMP16]], align 47640// CHECK19-NEXT: store i32 [[TMP34]], ptr [[LIN_CASTED_I]], align 4, !noalias [[META25]]7641// CHECK19-NEXT: [[TMP35:%.*]] = load i32, ptr [[LIN_CASTED_I]], align 4, !noalias [[META25]]7642// CHECK19-NEXT: [[TMP36:%.*]] = load i32, ptr [[TMP17]], align 47643// CHECK19-NEXT: store i32 [[TMP36]], ptr [[A_CASTED_I]], align 4, !noalias [[META25]]7644// CHECK19-NEXT: [[TMP37:%.*]] = load i32, ptr [[A_CASTED_I]], align 4, !noalias [[META25]]7645// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128(i32 [[TMP33]], i32 [[TMP35]], i32 [[TMP37]]) #[[ATTR3]]7646// CHECK19-NEXT: br label [[DOTOMP_OUTLINED__EXIT]]7647// CHECK19: .omp_outlined..exit:7648// CHECK19-NEXT: ret i32 07649//7650//7651// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1367652// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {7653// CHECK19-NEXT: entry:7654// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 47655// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 47656// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 47657// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 47658// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 47659// CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 47660// CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 47661// CHECK19-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 47662// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 47663// CHECK19-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 27664// CHECK19-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 27665// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 47666// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined, i32 [[TMP1]], i32 [[TMP3]])7667// CHECK19-NEXT: ret void7668//7669//7670// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined7671// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {7672// CHECK19-NEXT: entry:7673// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 47674// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 47675// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 47676// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 47677// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 47678// CHECK19-NEXT: [[TMP:%.*]] = alloca i16, align 27679// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 47680// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 47681// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 47682// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 47683// CHECK19-NEXT: [[IT:%.*]] = alloca i16, align 27684// CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 47685// CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 47686// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 47687// CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 47688// CHECK19-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 47689// CHECK19-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 47690// CHECK19-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 47691// CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 47692// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 47693// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 47694// CHECK19-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)7695// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 47696// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 37697// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]7698// CHECK19: cond.true:7699// CHECK19-NEXT: br label [[COND_END:%.*]]7700// CHECK19: cond.false:7701// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 47702// CHECK19-NEXT: br label [[COND_END]]7703// CHECK19: cond.end:7704// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]7705// CHECK19-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 47706// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 47707// CHECK19-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 47708// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]7709// CHECK19: omp.inner.for.cond:7710// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 47711// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 47712// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]7713// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]7714// CHECK19: omp.inner.for.body:7715// CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 47716// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 47717// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]7718// CHECK19-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i167719// CHECK19-NEXT: store i16 [[CONV]], ptr [[IT]], align 27720// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 47721// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 17722// CHECK19-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 47723// CHECK19-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 27724// CHECK19-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i327725// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 17726// CHECK19-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i167727// CHECK19-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 27728// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]7729// CHECK19: omp.body.continue:7730// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]7731// CHECK19: omp.inner.for.inc:7732// CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 47733// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 17734// CHECK19-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 47735// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]]7736// CHECK19: omp.inner.for.end:7737// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]7738// CHECK19: omp.loop.exit:7739// CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])7740// CHECK19-NEXT: ret void7741//7742//7743// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1607744// CHECK19-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {7745// CHECK19-NEXT: entry:7746// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 47747// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 47748// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 47749// CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 47750// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 47751// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 47752// CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 47753// CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 47754// CHECK19-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 47755// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 47756// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 47757// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 47758// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 47759// CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 47760// CHECK19-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 47761// CHECK19-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 47762// CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 47763// CHECK19-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 47764// CHECK19-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 47765// CHECK19-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 47766// CHECK19-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 47767// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 47768// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 47769// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 47770// CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 47771// CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 47772// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 47773// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 47774// CHECK19-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 47775// CHECK19-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 47776// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 47777// CHECK19-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 47778// CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 47779// CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 47780// CHECK19-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 47781// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 47782// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i32 [[TMP11]])7783// CHECK19-NEXT: ret void7784//7785//7786// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined7787// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {7788// CHECK19-NEXT: entry:7789// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 47790// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 47791// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 47792// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 47793// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 47794// CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 47795// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 47796// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 47797// CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 47798// CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 47799// CHECK19-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 47800// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 47801// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 47802// CHECK19-NEXT: [[TMP:%.*]] = alloca i8, align 17803// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 47804// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 47805// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 47806// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 47807// CHECK19-NEXT: [[IT:%.*]] = alloca i8, align 17808// CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 47809// CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 47810// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 47811// CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 47812// CHECK19-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 47813// CHECK19-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 47814// CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 47815// CHECK19-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 47816// CHECK19-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 47817// CHECK19-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 47818// CHECK19-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 47819// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 47820// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 47821// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 47822// CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 47823// CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 47824// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 47825// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 47826// CHECK19-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 47827// CHECK19-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 47828// CHECK19-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 47829// CHECK19-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 47830// CHECK19-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 47831// CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 47832// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 47833// CHECK19-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 47834// CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 47835// CHECK19-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])7836// CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]]7837// CHECK19: omp.dispatch.cond:7838// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 47839// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 257840// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]7841// CHECK19: cond.true:7842// CHECK19-NEXT: br label [[COND_END:%.*]]7843// CHECK19: cond.false:7844// CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 47845// CHECK19-NEXT: br label [[COND_END]]7846// CHECK19: cond.end:7847// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]7848// CHECK19-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 47849// CHECK19-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 47850// CHECK19-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 47851// CHECK19-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 47852// CHECK19-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 47853// CHECK19-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]7854// CHECK19-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]7855// CHECK19: omp.dispatch.body:7856// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]7857// CHECK19: omp.inner.for.cond:7858// CHECK19-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 47859// CHECK19-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 47860// CHECK19-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]7861// CHECK19-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]7862// CHECK19: omp.inner.for.body:7863// CHECK19-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 47864// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 17865// CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]7866// CHECK19-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i87867// CHECK19-NEXT: store i8 [[CONV]], ptr [[IT]], align 17868// CHECK19-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 47869// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 17870// CHECK19-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 47871// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 27872// CHECK19-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 47873// CHECK19-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double7874// CHECK19-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+007875// CHECK19-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float7876// CHECK19-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 47877// CHECK19-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 37878// CHECK19-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 47879// CHECK19-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double7880// CHECK19-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+007881// CHECK19-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float7882// CHECK19-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 47883// CHECK19-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 17884// CHECK19-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i32 0, i32 27885// CHECK19-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 87886// CHECK19-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+007887// CHECK19-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 87888// CHECK19-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]7889// CHECK19-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP23]]7890// CHECK19-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i32 37891// CHECK19-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 87892// CHECK19-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+007893// CHECK19-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 87894// CHECK19-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 07895// CHECK19-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 47896// CHECK19-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 17897// CHECK19-NEXT: store i64 [[ADD20]], ptr [[X]], align 47898// CHECK19-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 17899// CHECK19-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 47900// CHECK19-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i327901// CHECK19-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 17902// CHECK19-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i87903// CHECK19-NEXT: store i8 [[CONV23]], ptr [[Y]], align 47904// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]7905// CHECK19: omp.body.continue:7906// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]7907// CHECK19: omp.inner.for.inc:7908// CHECK19-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 47909// CHECK19-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 17910// CHECK19-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 47911// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]]7912// CHECK19: omp.inner.for.end:7913// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]]7914// CHECK19: omp.dispatch.inc:7915// CHECK19-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 47916// CHECK19-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 47917// CHECK19-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]7918// CHECK19-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 47919// CHECK19-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 47920// CHECK19-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 47921// CHECK19-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]7922// CHECK19-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 47923// CHECK19-NEXT: br label [[OMP_DISPATCH_COND]]7924// CHECK19: omp.dispatch.end:7925// CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]])7926// CHECK19-NEXT: ret void7927//7928//7929// CHECK19-LABEL: define {{[^@]+}}@_Z3bari7930// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {7931// CHECK19-NEXT: entry:7932// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 47933// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 47934// CHECK19-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 47935// CHECK19-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 47936// CHECK19-NEXT: store i32 0, ptr [[A]], align 47937// CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 47938// CHECK19-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]])7939// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 47940// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]7941// CHECK19-NEXT: store i32 [[ADD]], ptr [[A]], align 47942// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 47943// CHECK19-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]])7944// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 47945// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]7946// CHECK19-NEXT: store i32 [[ADD2]], ptr [[A]], align 47947// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 47948// CHECK19-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]])7949// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 47950// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]7951// CHECK19-NEXT: store i32 [[ADD4]], ptr [[A]], align 47952// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 47953// CHECK19-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]])7954// CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 47955// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]7956// CHECK19-NEXT: store i32 [[ADD6]], ptr [[A]], align 47957// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 47958// CHECK19-NEXT: ret i32 [[TMP8]]7959//7960//7961// CHECK19-LABEL: define {{[^@]+}}@_ZN2S12r1Ei7962// CHECK19-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {7963// CHECK19-NEXT: entry:7964// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 47965// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 47966// CHECK19-NEXT: [[B:%.*]] = alloca i32, align 47967// CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 47968// CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 47969// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 47970// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 47971// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 47972// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 47973// CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 47974// CHECK19-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 87975// CHECK19-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 47976// CHECK19-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 47977// CHECK19-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 47978// CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 47979// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 17980// CHECK19-NEXT: store i32 [[ADD]], ptr [[B]], align 47981// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 47982// CHECK19-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()7983// CHECK19-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 47984// CHECK19-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]7985// CHECK19-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 27986// CHECK19-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 47987// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 47988// CHECK19-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 47989// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 47990// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 47991// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 607992// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]7993// CHECK19: omp_if.then:7994// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 07995// CHECK19-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]]7996// CHECK19-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 27997// CHECK19-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i647998// CHECK19-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.5, i32 40, i1 false)7999// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 08000// CHECK19-NEXT: store ptr [[THIS1]], ptr [[TMP10]], align 48001// CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 08002// CHECK19-NEXT: store ptr [[A]], ptr [[TMP11]], align 48003// CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 08004// CHECK19-NEXT: store ptr null, ptr [[TMP12]], align 48005// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 18006// CHECK19-NEXT: store i32 [[TMP5]], ptr [[TMP13]], align 48007// CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 18008// CHECK19-NEXT: store i32 [[TMP5]], ptr [[TMP14]], align 48009// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 18010// CHECK19-NEXT: store ptr null, ptr [[TMP15]], align 48011// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 28012// CHECK19-NEXT: store i32 2, ptr [[TMP16]], align 48013// CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 28014// CHECK19-NEXT: store i32 2, ptr [[TMP17]], align 48015// CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 28016// CHECK19-NEXT: store ptr null, ptr [[TMP18]], align 48017// CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 38018// CHECK19-NEXT: store i32 [[TMP1]], ptr [[TMP19]], align 48019// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 38020// CHECK19-NEXT: store i32 [[TMP1]], ptr [[TMP20]], align 48021// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 38022// CHECK19-NEXT: store ptr null, ptr [[TMP21]], align 48023// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 48024// CHECK19-NEXT: store ptr [[VLA]], ptr [[TMP22]], align 48025// CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 48026// CHECK19-NEXT: store ptr [[VLA]], ptr [[TMP23]], align 48027// CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 48028// CHECK19-NEXT: store i64 [[TMP9]], ptr [[TMP24]], align 48029// CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 48030// CHECK19-NEXT: store ptr null, ptr [[TMP25]], align 48031// CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 08032// CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 08033// CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 08034// CHECK19-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 08035// CHECK19-NEXT: store i32 3, ptr [[TMP29]], align 48036// CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 18037// CHECK19-NEXT: store i32 5, ptr [[TMP30]], align 48038// CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 28039// CHECK19-NEXT: store ptr [[TMP26]], ptr [[TMP31]], align 48040// CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 38041// CHECK19-NEXT: store ptr [[TMP27]], ptr [[TMP32]], align 48042// CHECK19-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 48043// CHECK19-NEXT: store ptr [[TMP28]], ptr [[TMP33]], align 48044// CHECK19-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 58045// CHECK19-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP34]], align 48046// CHECK19-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 68047// CHECK19-NEXT: store ptr null, ptr [[TMP35]], align 48048// CHECK19-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 78049// CHECK19-NEXT: store ptr null, ptr [[TMP36]], align 48050// CHECK19-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 88051// CHECK19-NEXT: store i64 0, ptr [[TMP37]], align 88052// CHECK19-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 98053// CHECK19-NEXT: store i64 0, ptr [[TMP38]], align 88054// CHECK19-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 108055// CHECK19-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP39]], align 48056// CHECK19-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 118057// CHECK19-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP40]], align 48058// CHECK19-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 128059// CHECK19-NEXT: store i32 0, ptr [[TMP41]], align 48060// CHECK19-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.region_id, ptr [[KERNEL_ARGS]])8061// CHECK19-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 08062// CHECK19-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]8063// CHECK19: omp_offload.failed:8064// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3]]8065// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]]8066// CHECK19: omp_offload.cont:8067// CHECK19-NEXT: br label [[OMP_IF_END:%.*]]8068// CHECK19: omp_if.else:8069// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3]]8070// CHECK19-NEXT: br label [[OMP_IF_END]]8071// CHECK19: omp_if.end:8072// CHECK19-NEXT: [[TMP44:%.*]] = mul nsw i32 1, [[TMP1]]8073// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP44]]8074// CHECK19-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 18075// CHECK19-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 28076// CHECK19-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i328077// CHECK19-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 48078// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]]8079// CHECK19-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 48080// CHECK19-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP47]])8081// CHECK19-NEXT: ret i32 [[ADD3]]8082//8083//8084// CHECK19-LABEL: define {{[^@]+}}@_ZL7fstatici8085// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {8086// CHECK19-NEXT: entry:8087// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 48088// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 48089// CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 28090// CHECK19-NEXT: [[AAA:%.*]] = alloca i8, align 18091// CHECK19-NEXT: [[B:%.*]] = alloca [10 x i32], align 48092// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 48093// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 48094// CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 48095// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 48096// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 48097// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 48098// CHECK19-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 88099// CHECK19-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 48100// CHECK19-NEXT: store i32 0, ptr [[A]], align 48101// CHECK19-NEXT: store i16 0, ptr [[AA]], align 28102// CHECK19-NEXT: store i8 0, ptr [[AAA]], align 18103// CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 48104// CHECK19-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 48105// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 48106// CHECK19-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 28107// CHECK19-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 28108// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 48109// CHECK19-NEXT: [[TMP4:%.*]] = load i8, ptr [[AAA]], align 18110// CHECK19-NEXT: store i8 [[TMP4]], ptr [[AAA_CASTED]], align 18111// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[AAA_CASTED]], align 48112// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 48113// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 508114// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]8115// CHECK19: omp_if.then:8116// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 08117// CHECK19-NEXT: store i32 [[TMP1]], ptr [[TMP7]], align 48118// CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 08119// CHECK19-NEXT: store i32 [[TMP1]], ptr [[TMP8]], align 48120// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 08121// CHECK19-NEXT: store ptr null, ptr [[TMP9]], align 48122// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 18123// CHECK19-NEXT: store i32 [[TMP3]], ptr [[TMP10]], align 48124// CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 18125// CHECK19-NEXT: store i32 [[TMP3]], ptr [[TMP11]], align 48126// CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 18127// CHECK19-NEXT: store ptr null, ptr [[TMP12]], align 48128// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 28129// CHECK19-NEXT: store i32 [[TMP5]], ptr [[TMP13]], align 48130// CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 28131// CHECK19-NEXT: store i32 [[TMP5]], ptr [[TMP14]], align 48132// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 28133// CHECK19-NEXT: store ptr null, ptr [[TMP15]], align 48134// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 38135// CHECK19-NEXT: store ptr [[B]], ptr [[TMP16]], align 48136// CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 38137// CHECK19-NEXT: store ptr [[B]], ptr [[TMP17]], align 48138// CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 38139// CHECK19-NEXT: store ptr null, ptr [[TMP18]], align 48140// CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 08141// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 08142// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 08143// CHECK19-NEXT: store i32 3, ptr [[TMP21]], align 48144// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 18145// CHECK19-NEXT: store i32 4, ptr [[TMP22]], align 48146// CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 28147// CHECK19-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 48148// CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 38149// CHECK19-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 48150// CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 48151// CHECK19-NEXT: store ptr @.offload_sizes.7, ptr [[TMP25]], align 48152// CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 58153// CHECK19-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP26]], align 48154// CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 68155// CHECK19-NEXT: store ptr null, ptr [[TMP27]], align 48156// CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 78157// CHECK19-NEXT: store ptr null, ptr [[TMP28]], align 48158// CHECK19-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 88159// CHECK19-NEXT: store i64 0, ptr [[TMP29]], align 88160// CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 98161// CHECK19-NEXT: store i64 0, ptr [[TMP30]], align 88162// CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 108163// CHECK19-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP31]], align 48164// CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 118165// CHECK19-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP32]], align 48166// CHECK19-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 128167// CHECK19-NEXT: store i32 0, ptr [[TMP33]], align 48168// CHECK19-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.region_id, ptr [[KERNEL_ARGS]])8169// CHECK19-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 08170// CHECK19-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]8171// CHECK19: omp_offload.failed:8172// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR3]]8173// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]]8174// CHECK19: omp_offload.cont:8175// CHECK19-NEXT: br label [[OMP_IF_END:%.*]]8176// CHECK19: omp_if.else:8177// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR3]]8178// CHECK19-NEXT: br label [[OMP_IF_END]]8179// CHECK19: omp_if.end:8180// CHECK19-NEXT: [[TMP36:%.*]] = load i32, ptr [[A]], align 48181// CHECK19-NEXT: ret i32 [[TMP36]]8182//8183//8184// CHECK19-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i8185// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {8186// CHECK19-NEXT: entry:8187// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 48188// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 48189// CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 28190// CHECK19-NEXT: [[B:%.*]] = alloca [10 x i32], align 48191// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 48192// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 48193// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 48194// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 48195// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 48196// CHECK19-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 88197// CHECK19-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 48198// CHECK19-NEXT: store i32 0, ptr [[A]], align 48199// CHECK19-NEXT: store i16 0, ptr [[AA]], align 28200// CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 48201// CHECK19-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 48202// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 48203// CHECK19-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 28204// CHECK19-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 28205// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 48206// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 48207// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 408208// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]8209// CHECK19: omp_if.then:8210// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 08211// CHECK19-NEXT: store i32 [[TMP1]], ptr [[TMP5]], align 48212// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 08213// CHECK19-NEXT: store i32 [[TMP1]], ptr [[TMP6]], align 48214// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 08215// CHECK19-NEXT: store ptr null, ptr [[TMP7]], align 48216// CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 18217// CHECK19-NEXT: store i32 [[TMP3]], ptr [[TMP8]], align 48218// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 18219// CHECK19-NEXT: store i32 [[TMP3]], ptr [[TMP9]], align 48220// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 18221// CHECK19-NEXT: store ptr null, ptr [[TMP10]], align 48222// CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 28223// CHECK19-NEXT: store ptr [[B]], ptr [[TMP11]], align 48224// CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 28225// CHECK19-NEXT: store ptr [[B]], ptr [[TMP12]], align 48226// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 28227// CHECK19-NEXT: store ptr null, ptr [[TMP13]], align 48228// CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 08229// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 08230// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 08231// CHECK19-NEXT: store i32 3, ptr [[TMP16]], align 48232// CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 18233// CHECK19-NEXT: store i32 3, ptr [[TMP17]], align 48234// CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 28235// CHECK19-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 48236// CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 38237// CHECK19-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 48238// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 48239// CHECK19-NEXT: store ptr @.offload_sizes.9, ptr [[TMP20]], align 48240// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 58241// CHECK19-NEXT: store ptr @.offload_maptypes.10, ptr [[TMP21]], align 48242// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 68243// CHECK19-NEXT: store ptr null, ptr [[TMP22]], align 48244// CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 78245// CHECK19-NEXT: store ptr null, ptr [[TMP23]], align 48246// CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 88247// CHECK19-NEXT: store i64 0, ptr [[TMP24]], align 88248// CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 98249// CHECK19-NEXT: store i64 0, ptr [[TMP25]], align 88250// CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 108251// CHECK19-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP26]], align 48252// CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 118253// CHECK19-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP27]], align 48254// CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 128255// CHECK19-NEXT: store i32 0, ptr [[TMP28]], align 48256// CHECK19-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.region_id, ptr [[KERNEL_ARGS]])8257// CHECK19-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 08258// CHECK19-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]8259// CHECK19: omp_offload.failed:8260// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]]8261// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]]8262// CHECK19: omp_offload.cont:8263// CHECK19-NEXT: br label [[OMP_IF_END:%.*]]8264// CHECK19: omp_if.else:8265// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]]8266// CHECK19-NEXT: br label [[OMP_IF_END]]8267// CHECK19: omp_if.end:8268// CHECK19-NEXT: [[TMP31:%.*]] = load i32, ptr [[A]], align 48269// CHECK19-NEXT: ret i32 [[TMP31]]8270//8271//8272// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l2328273// CHECK19-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {8274// CHECK19-NEXT: entry:8275// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 48276// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 48277// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 48278// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 48279// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 48280// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 48281// CHECK19-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 48282// CHECK19-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 48283// CHECK19-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 48284// CHECK19-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 48285// CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 48286// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 48287// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 48288// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 48289// CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 48290// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 48291// CHECK19-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 48292// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 48293// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.omp_outlined, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]])8294// CHECK19-NEXT: ret void8295//8296//8297// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.omp_outlined8298// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {8299// CHECK19-NEXT: entry:8300// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 48301// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 48302// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 48303// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 48304// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 48305// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 48306// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 48307// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 88308// CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 48309// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 88310// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 88311// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 88312// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 48313// CHECK19-NEXT: [[IT:%.*]] = alloca i64, align 88314// CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 48315// CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 48316// CHECK19-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 48317// CHECK19-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 48318// CHECK19-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 48319// CHECK19-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 48320// CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 48321// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 48322// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 48323// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 48324// CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 48325// CHECK19-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 88326// CHECK19-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 88327// CHECK19-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 88328// CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 48329// CHECK19-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 48330// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 48331// CHECK19-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)8332// CHECK19-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_UB]], align 88333// CHECK19-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 38334// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]8335// CHECK19: cond.true:8336// CHECK19-NEXT: br label [[COND_END:%.*]]8337// CHECK19: cond.false:8338// CHECK19-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 88339// CHECK19-NEXT: br label [[COND_END]]8340// CHECK19: cond.end:8341// CHECK19-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]8342// CHECK19-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 88343// CHECK19-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_LB]], align 88344// CHECK19-NEXT: store i64 [[TMP8]], ptr [[DOTOMP_IV]], align 88345// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]8346// CHECK19: omp.inner.for.cond:8347// CHECK19-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 88348// CHECK19-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 88349// CHECK19-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]8350// CHECK19-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]8351// CHECK19: omp.inner.for.body:8352// CHECK19-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 88353// CHECK19-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 4008354// CHECK19-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]8355// CHECK19-NEXT: store i64 [[SUB]], ptr [[IT]], align 88356// CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 48357// CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double8358// CHECK19-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+008359// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 08360// CHECK19-NEXT: store double [[ADD]], ptr [[A]], align 48361// CHECK19-NEXT: [[A4:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 08362// CHECK19-NEXT: [[TMP13:%.*]] = load double, ptr [[A4]], align 48363// CHECK19-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+008364// CHECK19-NEXT: store double [[INC]], ptr [[A4]], align 48365// CHECK19-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i168366// CHECK19-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]8367// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP14]]8368// CHECK19-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 18369// CHECK19-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 28370// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]8371// CHECK19: omp.body.continue:8372// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]8373// CHECK19: omp.inner.for.inc:8374// CHECK19-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 88375// CHECK19-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 18376// CHECK19-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 88377// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]]8378// CHECK19: omp.inner.for.end:8379// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]8380// CHECK19: omp.loop.exit:8381// CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])8382// CHECK19-NEXT: ret void8383//8384//8385// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l2148386// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {8387// CHECK19-NEXT: entry:8388// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 48389// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 48390// CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 48391// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 48392// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 48393// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 48394// CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 48395// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 48396// CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 48397// CHECK19-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 48398// CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 48399// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 48400// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 48401// CHECK19-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 48402// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 48403// CHECK19-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 28404// CHECK19-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 28405// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 48406// CHECK19-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 18407// CHECK19-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 18408// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[AAA_CASTED]], align 48409// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], ptr [[TMP0]])8410// CHECK19-NEXT: ret void8411//8412//8413// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.omp_outlined8414// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {8415// CHECK19-NEXT: entry:8416// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 48417// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 48418// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 48419// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 48420// CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 48421// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 48422// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 48423// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 48424// CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 48425// CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 48426// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 48427// CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 48428// CHECK19-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 48429// CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 48430// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 48431// CHECK19-NEXT: ret void8432//8433//8434// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l1978435// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {8436// CHECK19-NEXT: entry:8437// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 48438// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 48439// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 48440// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 48441// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 48442// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 48443// CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 48444// CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 48445// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 48446// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 48447// CHECK19-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 48448// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 48449// CHECK19-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 28450// CHECK19-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 28451// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 48452// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]])8453// CHECK19-NEXT: ret void8454//8455//8456// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.omp_outlined8457// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {8458// CHECK19-NEXT: entry:8459// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 48460// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 48461// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 48462// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 48463// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 48464// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 88465// CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 48466// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 88467// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 88468// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 88469// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 48470// CHECK19-NEXT: [[I:%.*]] = alloca i64, align 88471// CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 48472// CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 48473// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 48474// CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 48475// CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 48476// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 48477// CHECK19-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 88478// CHECK19-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 88479// CHECK19-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 88480// CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 48481// CHECK19-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 48482// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 48483// CHECK19-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)8484// CHECK19-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 88485// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 68486// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]8487// CHECK19: cond.true:8488// CHECK19-NEXT: br label [[COND_END:%.*]]8489// CHECK19: cond.false:8490// CHECK19-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 88491// CHECK19-NEXT: br label [[COND_END]]8492// CHECK19: cond.end:8493// CHECK19-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]8494// CHECK19-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 88495// CHECK19-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 88496// CHECK19-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 88497// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]8498// CHECK19: omp.inner.for.cond:8499// CHECK19-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 88500// CHECK19-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 88501// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]8502// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]8503// CHECK19: omp.inner.for.body:8504// CHECK19-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 88505// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 38506// CHECK19-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]8507// CHECK19-NEXT: store i64 [[ADD]], ptr [[I]], align 88508// CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 48509// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 18510// CHECK19-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 48511// CHECK19-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 28512// CHECK19-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i328513// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 18514// CHECK19-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i168515// CHECK19-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 28516// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 28517// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 48518// CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 18519// CHECK19-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 48520// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]8521// CHECK19: omp.body.continue:8522// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]8523// CHECK19: omp.inner.for.inc:8524// CHECK19-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 88525// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 18526// CHECK19-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 88527// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]]8528// CHECK19: omp.inner.for.end:8529// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]8530// CHECK19: omp.loop.exit:8531// CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])8532// CHECK19-NEXT: ret void8533//8534