12389 lines · cpp
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _2// Test host codegen.3// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK14// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s5// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK16// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK37// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s8// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK39// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK510// RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s11// RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK512// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK713// RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s14// RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK715 16// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK917// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s18// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK919// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1120// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s21// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1122// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1323// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s24// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1325// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1526// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s27// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1528 29// Test target codegen - host bc file has to be created first.30// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc31// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1732// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s33// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1734// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc35// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1936// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s37// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1938// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc39// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK2140// RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s41// RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK2142// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc43// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK2344// RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s45// RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK2346 47// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc48// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK949// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s50// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK951// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc52// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1153// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s54// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1155// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc56// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1357// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s58// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1359// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc60// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1561// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s62// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1563 64// expected-no-diagnostics65#ifndef HEADER66#define HEADER67 68 69 70// We have 8 target regions, but only 7 that actually will generate offloading71// code, only 6 will have mapped arguments, and only 4 have all-constant map72// sizes.73 74 75 76// Check target registration is registered as a Ctor.77 78 79template<typename tx, typename ty>80struct TT{81 tx X;82 ty Y;83};84 85long long get_val() { return 0; }86 87int foo(int n) {88 int a = 0;89 short aa = 0;90 float b[10];91 float bn[n];92 double c[5][10];93 double cn[5][n];94 TT<long long, char> d;95 96 #pragma omp target parallel for simd nowait97 for (int i = 3; i < 32; i += 5) {98 }99 100 long long k = get_val();101 #pragma omp target parallel for simd if(target: 0) linear(k : 3) schedule(dynamic)102 for (int i = 10; i > 1; i--) {103 a += 1;104 }105 106 107 int lin = 12;108 #pragma omp target parallel for simd if(target: 1) linear(lin, a : get_val())109 for (unsigned long long it = 2000; it >= 600; it-=400) {110 aa += 1;111 }112 113 114 115 116 #pragma omp target parallel for simd if(target: n>10)117 for (short it = 6; it <= 20; it-=-4) {118 a += 1;119 aa += 1;120 }121 122 // We capture 3 VLA sizes in this target region123 124 125 126 127 128 // The names below are not necessarily consistent with the names used for the129 // addresses above as some are repeated.130 131 132 133 134 135 136 137 138 139 140 #pragma omp target parallel for simd if(target: n>20) schedule(static, a)141 for (unsigned char it = 'z'; it >= 'a'; it+=-1) {142 a += 1;143 b[2] += 1.0;144 bn[3] += 1.0;145 c[1][2] += 1.0;146 cn[1][3] += 1.0;147 d.X += 1;148 d.Y += 1;149 }150 151 return a;152}153 154// Check that the offloading functions are emitted and that the arguments are155// correct and loaded correctly for the target regions in foo().156 157 158 159 160// Create stack storage and store argument in there.161 162// Create stack storage and store argument in there.163 164// Create stack storage and store argument in there.165 166// Create local storage for each capture.167 168 169 170// To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.171 172template<typename tx>173tx ftemplate(int n) {174 tx a = 0;175 short aa = 0;176 tx b[10];177 178 #pragma omp target parallel for simd if(target: n>40)179 for (long long i = -10; i < 10; i += 3) {180 a += 1;181 aa += 1;182 b[2] += 1;183 }184 185 return a;186}187 188static189int fstatic(int n) {190 int a = 0;191 short aa = 0;192 char aaa = 0;193 int b[10];194 195 #pragma omp target parallel for simd if(target: n>50)196 for (unsigned i=100; i<10; i+=10) {197 a += 1;198 aa += 1;199 aaa += 1;200 b[2] += 1;201 }202 203 return a;204}205 206struct S1 {207 double a;208 209 int r1(int n){210 int b = n+1;211 short int c[2][n];212 213#ifdef OMP5214 #pragma omp target parallel for simd if(n>60) nontemporal(a)215#else216 #pragma omp target parallel for simd if(target: n>60)217#endif // OMP5218 for (unsigned long long it = 2000; it >= 600; it -= 400) {219 this->a = (double)b + 1.5;220 c[1][1] = ++a;221 }222 223 return c[1][1] + (int)b;224 }225};226 227int bar(int n){228 int a = 0;229 230 a += foo(n);231 232 S1 S;233 a += S.r1(n);234 235 a += fstatic(n);236 237 a += ftemplate<int>(n);238 239 return a;240}241 242 243 244// We capture 2 VLA sizes in this target region245 246 247// The names below are not necessarily consistent with the names used for the248// addresses above as some are repeated.249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268// Check that the offloading functions are emitted and that the arguments are269// correct and loaded correctly for the target regions of the callees of bar().270 271// Create local storage for each capture.272// Store captures in the context.273 274 275 276// To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.277 278 279// Create local storage for each capture.280// Store captures in the context.281 282 283 284 285// To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.286 287// Create local storage for each capture.288// Store captures in the context.289 290 291 292// To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.293 294 295#endif296// CHECK1-LABEL: define {{[^@]+}}@_Z7get_valv297// CHECK1-SAME: () #[[ATTR0:[0-9]+]] {298// CHECK1-NEXT: entry:299// CHECK1-NEXT: ret i64 0300//301//302// CHECK1-LABEL: define {{[^@]+}}@_Z3fooi303// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {304// CHECK1-NEXT: entry:305// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4306// CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4307// CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2308// CHECK1-NEXT: [[B:%.*]] = alloca [10 x float], align 4309// CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8310// CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8311// CHECK1-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8312// CHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8313// CHECK1-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8314// CHECK1-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1315// CHECK1-NEXT: [[K:%.*]] = alloca i64, align 8316// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8317// CHECK1-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8318// CHECK1-NEXT: [[LIN:%.*]] = alloca i32, align 4319// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8320// CHECK1-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8321// CHECK1-NEXT: [[A_CASTED2:%.*]] = alloca i64, align 8322// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8323// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8324// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8325// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8326// CHECK1-NEXT: [[A_CASTED3:%.*]] = alloca i64, align 8327// CHECK1-NEXT: [[AA_CASTED4:%.*]] = alloca i64, align 8328// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x ptr], align 8329// CHECK1-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x ptr], align 8330// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x ptr], align 8331// CHECK1-NEXT: [[KERNEL_ARGS8:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8332// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4333// CHECK1-NEXT: [[A_CASTED11:%.*]] = alloca i64, align 8334// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8335// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x ptr], align 8336// CHECK1-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x ptr], align 8337// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x ptr], align 8338// CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8339// CHECK1-NEXT: [[KERNEL_ARGS17:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8340// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])341// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4342// CHECK1-NEXT: store i32 0, ptr [[A]], align 4343// CHECK1-NEXT: store i16 0, ptr [[AA]], align 2344// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4345// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64346// CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()347// CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8348// CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4349// CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8350// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4351// CHECK1-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64352// CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]353// CHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8354// CHECK1-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8355// CHECK1-NEXT: [[TMP7:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i64 40, i64 1, ptr @.omp_task_entry., i64 -1)356// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP7]], i32 0, i32 0357// CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB2]], i32 [[TMP0]], ptr [[TMP7]])358// CHECK1-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()359// CHECK1-NEXT: store i64 [[CALL]], ptr [[K]], align 8360// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4361// CHECK1-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4362// CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[A_CASTED]], align 8363// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[K]], align 8364// CHECK1-NEXT: store i64 [[TMP12]], ptr [[K_CASTED]], align 8365// CHECK1-NEXT: [[TMP13:%.*]] = load i64, ptr [[K_CASTED]], align 8366// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP11]], i64 [[TMP13]]) #[[ATTR3:[0-9]+]]367// CHECK1-NEXT: store i32 12, ptr [[LIN]], align 4368// CHECK1-NEXT: [[TMP14:%.*]] = load i16, ptr [[AA]], align 2369// CHECK1-NEXT: store i16 [[TMP14]], ptr [[AA_CASTED]], align 2370// CHECK1-NEXT: [[TMP15:%.*]] = load i64, ptr [[AA_CASTED]], align 8371// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[LIN]], align 4372// CHECK1-NEXT: store i32 [[TMP16]], ptr [[LIN_CASTED]], align 4373// CHECK1-NEXT: [[TMP17:%.*]] = load i64, ptr [[LIN_CASTED]], align 8374// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[A]], align 4375// CHECK1-NEXT: store i32 [[TMP18]], ptr [[A_CASTED2]], align 4376// CHECK1-NEXT: [[TMP19:%.*]] = load i64, ptr [[A_CASTED2]], align 8377// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0378// CHECK1-NEXT: store i64 [[TMP15]], ptr [[TMP20]], align 8379// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0380// CHECK1-NEXT: store i64 [[TMP15]], ptr [[TMP21]], align 8381// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0382// CHECK1-NEXT: store ptr null, ptr [[TMP22]], align 8383// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1384// CHECK1-NEXT: store i64 [[TMP17]], ptr [[TMP23]], align 8385// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1386// CHECK1-NEXT: store i64 [[TMP17]], ptr [[TMP24]], align 8387// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1388// CHECK1-NEXT: store ptr null, ptr [[TMP25]], align 8389// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2390// CHECK1-NEXT: store i64 [[TMP19]], ptr [[TMP26]], align 8391// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2392// CHECK1-NEXT: store i64 [[TMP19]], ptr [[TMP27]], align 8393// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2394// CHECK1-NEXT: store ptr null, ptr [[TMP28]], align 8395// CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0396// CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0397// CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0398// CHECK1-NEXT: store i32 3, ptr [[TMP31]], align 4399// CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1400// CHECK1-NEXT: store i32 3, ptr [[TMP32]], align 4401// CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2402// CHECK1-NEXT: store ptr [[TMP29]], ptr [[TMP33]], align 8403// CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3404// CHECK1-NEXT: store ptr [[TMP30]], ptr [[TMP34]], align 8405// CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4406// CHECK1-NEXT: store ptr @.offload_sizes, ptr [[TMP35]], align 8407// CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5408// CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP36]], align 8409// CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6410// CHECK1-NEXT: store ptr null, ptr [[TMP37]], align 8411// CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7412// CHECK1-NEXT: store ptr null, ptr [[TMP38]], align 8413// CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8414// CHECK1-NEXT: store i64 0, ptr [[TMP39]], align 8415// CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9416// CHECK1-NEXT: store i64 0, ptr [[TMP40]], align 8417// CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10418// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP41]], align 4419// CHECK1-NEXT: [[TMP42:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11420// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP42]], align 4421// CHECK1-NEXT: [[TMP43:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12422// CHECK1-NEXT: store i32 0, ptr [[TMP43]], align 4423// CHECK1-NEXT: [[TMP44:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.region_id, ptr [[KERNEL_ARGS]])424// CHECK1-NEXT: [[TMP45:%.*]] = icmp ne i32 [[TMP44]], 0425// CHECK1-NEXT: br i1 [[TMP45]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]426// CHECK1: omp_offload.failed:427// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]]) #[[ATTR3]]428// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]429// CHECK1: omp_offload.cont:430// CHECK1-NEXT: [[TMP46:%.*]] = load i32, ptr [[A]], align 4431// CHECK1-NEXT: store i32 [[TMP46]], ptr [[A_CASTED3]], align 4432// CHECK1-NEXT: [[TMP47:%.*]] = load i64, ptr [[A_CASTED3]], align 8433// CHECK1-NEXT: [[TMP48:%.*]] = load i16, ptr [[AA]], align 2434// CHECK1-NEXT: store i16 [[TMP48]], ptr [[AA_CASTED4]], align 2435// CHECK1-NEXT: [[TMP49:%.*]] = load i64, ptr [[AA_CASTED4]], align 8436// CHECK1-NEXT: [[TMP50:%.*]] = load i32, ptr [[N_ADDR]], align 4437// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP50]], 10438// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]439// CHECK1: omp_if.then:440// CHECK1-NEXT: [[TMP51:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0441// CHECK1-NEXT: store i64 [[TMP47]], ptr [[TMP51]], align 8442// CHECK1-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0443// CHECK1-NEXT: store i64 [[TMP47]], ptr [[TMP52]], align 8444// CHECK1-NEXT: [[TMP53:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0445// CHECK1-NEXT: store ptr null, ptr [[TMP53]], align 8446// CHECK1-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1447// CHECK1-NEXT: store i64 [[TMP49]], ptr [[TMP54]], align 8448// CHECK1-NEXT: [[TMP55:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 1449// CHECK1-NEXT: store i64 [[TMP49]], ptr [[TMP55]], align 8450// CHECK1-NEXT: [[TMP56:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1451// CHECK1-NEXT: store ptr null, ptr [[TMP56]], align 8452// CHECK1-NEXT: [[TMP57:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0453// CHECK1-NEXT: [[TMP58:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0454// CHECK1-NEXT: [[TMP59:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 0455// CHECK1-NEXT: store i32 3, ptr [[TMP59]], align 4456// CHECK1-NEXT: [[TMP60:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 1457// CHECK1-NEXT: store i32 2, ptr [[TMP60]], align 4458// CHECK1-NEXT: [[TMP61:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 2459// CHECK1-NEXT: store ptr [[TMP57]], ptr [[TMP61]], align 8460// CHECK1-NEXT: [[TMP62:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 3461// CHECK1-NEXT: store ptr [[TMP58]], ptr [[TMP62]], align 8462// CHECK1-NEXT: [[TMP63:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 4463// CHECK1-NEXT: store ptr @.offload_sizes.1, ptr [[TMP63]], align 8464// CHECK1-NEXT: [[TMP64:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 5465// CHECK1-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP64]], align 8466// CHECK1-NEXT: [[TMP65:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 6467// CHECK1-NEXT: store ptr null, ptr [[TMP65]], align 8468// CHECK1-NEXT: [[TMP66:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 7469// CHECK1-NEXT: store ptr null, ptr [[TMP66]], align 8470// CHECK1-NEXT: [[TMP67:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 8471// CHECK1-NEXT: store i64 0, ptr [[TMP67]], align 8472// CHECK1-NEXT: [[TMP68:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 9473// CHECK1-NEXT: store i64 0, ptr [[TMP68]], align 8474// CHECK1-NEXT: [[TMP69:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 10475// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP69]], align 4476// CHECK1-NEXT: [[TMP70:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 11477// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP70]], align 4478// CHECK1-NEXT: [[TMP71:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 12479// CHECK1-NEXT: store i32 0, ptr [[TMP71]], align 4480// CHECK1-NEXT: [[TMP72:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.region_id, ptr [[KERNEL_ARGS8]])481// CHECK1-NEXT: [[TMP73:%.*]] = icmp ne i32 [[TMP72]], 0482// CHECK1-NEXT: br i1 [[TMP73]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]]483// CHECK1: omp_offload.failed9:484// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP47]], i64 [[TMP49]]) #[[ATTR3]]485// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT10]]486// CHECK1: omp_offload.cont10:487// CHECK1-NEXT: br label [[OMP_IF_END:%.*]]488// CHECK1: omp_if.else:489// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP47]], i64 [[TMP49]]) #[[ATTR3]]490// CHECK1-NEXT: br label [[OMP_IF_END]]491// CHECK1: omp_if.end:492// CHECK1-NEXT: [[TMP74:%.*]] = load i32, ptr [[A]], align 4493// CHECK1-NEXT: store i32 [[TMP74]], ptr [[DOTCAPTURE_EXPR_]], align 4494// CHECK1-NEXT: [[TMP75:%.*]] = load i32, ptr [[A]], align 4495// CHECK1-NEXT: store i32 [[TMP75]], ptr [[A_CASTED11]], align 4496// CHECK1-NEXT: [[TMP76:%.*]] = load i64, ptr [[A_CASTED11]], align 8497// CHECK1-NEXT: [[TMP77:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4498// CHECK1-NEXT: store i32 [[TMP77]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4499// CHECK1-NEXT: [[TMP78:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8500// CHECK1-NEXT: [[TMP79:%.*]] = load i32, ptr [[N_ADDR]], align 4501// CHECK1-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP79]], 20502// CHECK1-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE20:%.*]]503// CHECK1: omp_if.then13:504// CHECK1-NEXT: [[TMP80:%.*]] = mul nuw i64 [[TMP2]], 4505// CHECK1-NEXT: [[TMP81:%.*]] = mul nuw i64 5, [[TMP5]]506// CHECK1-NEXT: [[TMP82:%.*]] = mul nuw i64 [[TMP81]], 8507// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.3, i64 80, i1 false)508// CHECK1-NEXT: [[TMP83:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0509// CHECK1-NEXT: store i64 [[TMP76]], ptr [[TMP83]], align 8510// CHECK1-NEXT: [[TMP84:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 0511// CHECK1-NEXT: store i64 [[TMP76]], ptr [[TMP84]], align 8512// CHECK1-NEXT: [[TMP85:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 0513// CHECK1-NEXT: store ptr null, ptr [[TMP85]], align 8514// CHECK1-NEXT: [[TMP86:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1515// CHECK1-NEXT: store ptr [[B]], ptr [[TMP86]], align 8516// CHECK1-NEXT: [[TMP87:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 1517// CHECK1-NEXT: store ptr [[B]], ptr [[TMP87]], align 8518// CHECK1-NEXT: [[TMP88:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 1519// CHECK1-NEXT: store ptr null, ptr [[TMP88]], align 8520// CHECK1-NEXT: [[TMP89:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2521// CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP89]], align 8522// CHECK1-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 2523// CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP90]], align 8524// CHECK1-NEXT: [[TMP91:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 2525// CHECK1-NEXT: store ptr null, ptr [[TMP91]], align 8526// CHECK1-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3527// CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP92]], align 8528// CHECK1-NEXT: [[TMP93:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 3529// CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP93]], align 8530// CHECK1-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3531// CHECK1-NEXT: store i64 [[TMP80]], ptr [[TMP94]], align 8532// CHECK1-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 3533// CHECK1-NEXT: store ptr null, ptr [[TMP95]], align 8534// CHECK1-NEXT: [[TMP96:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4535// CHECK1-NEXT: store ptr [[C]], ptr [[TMP96]], align 8536// CHECK1-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 4537// CHECK1-NEXT: store ptr [[C]], ptr [[TMP97]], align 8538// CHECK1-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 4539// CHECK1-NEXT: store ptr null, ptr [[TMP98]], align 8540// CHECK1-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5541// CHECK1-NEXT: store i64 5, ptr [[TMP99]], align 8542// CHECK1-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 5543// CHECK1-NEXT: store i64 5, ptr [[TMP100]], align 8544// CHECK1-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 5545// CHECK1-NEXT: store ptr null, ptr [[TMP101]], align 8546// CHECK1-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6547// CHECK1-NEXT: store i64 [[TMP5]], ptr [[TMP102]], align 8548// CHECK1-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 6549// CHECK1-NEXT: store i64 [[TMP5]], ptr [[TMP103]], align 8550// CHECK1-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 6551// CHECK1-NEXT: store ptr null, ptr [[TMP104]], align 8552// CHECK1-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7553// CHECK1-NEXT: store ptr [[VLA1]], ptr [[TMP105]], align 8554// CHECK1-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 7555// CHECK1-NEXT: store ptr [[VLA1]], ptr [[TMP106]], align 8556// CHECK1-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 7557// CHECK1-NEXT: store i64 [[TMP82]], ptr [[TMP107]], align 8558// CHECK1-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 7559// CHECK1-NEXT: store ptr null, ptr [[TMP108]], align 8560// CHECK1-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8561// CHECK1-NEXT: store ptr [[D]], ptr [[TMP109]], align 8562// CHECK1-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 8563// CHECK1-NEXT: store ptr [[D]], ptr [[TMP110]], align 8564// CHECK1-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 8565// CHECK1-NEXT: store ptr null, ptr [[TMP111]], align 8566// CHECK1-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9567// CHECK1-NEXT: store i64 [[TMP78]], ptr [[TMP112]], align 8568// CHECK1-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 9569// CHECK1-NEXT: store i64 [[TMP78]], ptr [[TMP113]], align 8570// CHECK1-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 9571// CHECK1-NEXT: store ptr null, ptr [[TMP114]], align 8572// CHECK1-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0573// CHECK1-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 0574// CHECK1-NEXT: [[TMP117:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0575// CHECK1-NEXT: [[TMP118:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 0576// CHECK1-NEXT: store i32 3, ptr [[TMP118]], align 4577// CHECK1-NEXT: [[TMP119:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 1578// CHECK1-NEXT: store i32 10, ptr [[TMP119]], align 4579// CHECK1-NEXT: [[TMP120:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 2580// CHECK1-NEXT: store ptr [[TMP115]], ptr [[TMP120]], align 8581// CHECK1-NEXT: [[TMP121:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 3582// CHECK1-NEXT: store ptr [[TMP116]], ptr [[TMP121]], align 8583// CHECK1-NEXT: [[TMP122:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 4584// CHECK1-NEXT: store ptr [[TMP117]], ptr [[TMP122]], align 8585// CHECK1-NEXT: [[TMP123:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 5586// CHECK1-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP123]], align 8587// CHECK1-NEXT: [[TMP124:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 6588// CHECK1-NEXT: store ptr null, ptr [[TMP124]], align 8589// CHECK1-NEXT: [[TMP125:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 7590// CHECK1-NEXT: store ptr null, ptr [[TMP125]], align 8591// CHECK1-NEXT: [[TMP126:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 8592// CHECK1-NEXT: store i64 0, ptr [[TMP126]], align 8593// CHECK1-NEXT: [[TMP127:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 9594// CHECK1-NEXT: store i64 0, ptr [[TMP127]], align 8595// CHECK1-NEXT: [[TMP128:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 10596// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP128]], align 4597// CHECK1-NEXT: [[TMP129:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 11598// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP129]], align 4599// CHECK1-NEXT: [[TMP130:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 12600// CHECK1-NEXT: store i32 0, ptr [[TMP130]], align 4601// CHECK1-NEXT: [[TMP131:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.region_id, ptr [[KERNEL_ARGS17]])602// CHECK1-NEXT: [[TMP132:%.*]] = icmp ne i32 [[TMP131]], 0603// CHECK1-NEXT: br i1 [[TMP132]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]]604// CHECK1: omp_offload.failed18:605// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP76]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP78]]) #[[ATTR3]]606// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT19]]607// CHECK1: omp_offload.cont19:608// CHECK1-NEXT: br label [[OMP_IF_END21:%.*]]609// CHECK1: omp_if.else20:610// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP76]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP78]]) #[[ATTR3]]611// CHECK1-NEXT: br label [[OMP_IF_END21]]612// CHECK1: omp_if.end21:613// CHECK1-NEXT: [[TMP133:%.*]] = load i32, ptr [[A]], align 4614// CHECK1-NEXT: [[TMP134:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8615// CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP134]])616// CHECK1-NEXT: ret i32 [[TMP133]]617//618//619// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96620// CHECK1-SAME: () #[[ATTR2:[0-9]+]] {621// CHECK1-NEXT: entry:622// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined)623// CHECK1-NEXT: ret void624//625//626// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined627// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] {628// CHECK1-NEXT: entry:629// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8630// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8631// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4632// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4633// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4634// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4635// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4636// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4637// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4638// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8639// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8640// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4641// CHECK1-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 4642// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4643// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4644// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8645// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4646// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)647// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4648// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5649// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]650// CHECK1: cond.true:651// CHECK1-NEXT: br label [[COND_END:%.*]]652// CHECK1: cond.false:653// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4654// CHECK1-NEXT: br label [[COND_END]]655// CHECK1: cond.end:656// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]657// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4658// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4659// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4660// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]661// CHECK1: omp.inner.for.cond:662// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]]663// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP10]]664// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]665// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]666// CHECK1: omp.inner.for.body:667// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]668// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5669// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]670// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]671// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]672// CHECK1: omp.body.continue:673// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]674// CHECK1: omp.inner.for.inc:675// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]676// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1677// CHECK1-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]678// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]679// CHECK1: omp.inner.for.end:680// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]681// CHECK1: omp.loop.exit:682// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])683// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4684// CHECK1-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0685// CHECK1-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]686// CHECK1: .omp.final.then:687// CHECK1-NEXT: store i32 33, ptr [[I]], align 4688// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]689// CHECK1: .omp.final.done:690// CHECK1-NEXT: ret void691//692//693// CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry.694// CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] {695// CHECK1-NEXT: entry:696// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4697// CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8698// CHECK1-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8699// CHECK1-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8700// CHECK1-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8701// CHECK1-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8702// CHECK1-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8703// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4704// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8705// CHECK1-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4706// CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8707// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4708// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8709// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0710// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2711// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0712// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8713// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])714// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])715// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])716// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])717// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META25:![0-9]+]]718// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META25]]719// CHECK1-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META25]]720// CHECK1-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META25]]721// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META25]]722// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META25]]723// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META25]]724// CHECK1-NEXT: store i32 3, ptr [[KERNEL_ARGS_I]], align 4, !noalias [[META25]]725// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 1726// CHECK1-NEXT: store i32 0, ptr [[TMP9]], align 4, !noalias [[META25]]727// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 2728// CHECK1-NEXT: store ptr null, ptr [[TMP10]], align 8, !noalias [[META25]]729// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 3730// CHECK1-NEXT: store ptr null, ptr [[TMP11]], align 8, !noalias [[META25]]731// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 4732// CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8, !noalias [[META25]]733// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 5734// CHECK1-NEXT: store ptr null, ptr [[TMP13]], align 8, !noalias [[META25]]735// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 6736// CHECK1-NEXT: store ptr null, ptr [[TMP14]], align 8, !noalias [[META25]]737// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 7738// CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 8, !noalias [[META25]]739// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 8740// CHECK1-NEXT: store i64 0, ptr [[TMP16]], align 8, !noalias [[META25]]741// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 9742// CHECK1-NEXT: store i64 1, ptr [[TMP17]], align 8, !noalias [[META25]]743// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 10744// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP18]], align 4, !noalias [[META25]]745// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 11746// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP19]], align 4, !noalias [[META25]]747// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 12748// CHECK1-NEXT: store i32 0, ptr [[TMP20]], align 4, !noalias [[META25]]749// CHECK1-NEXT: [[TMP21:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, ptr [[KERNEL_ARGS_I]])750// CHECK1-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0751// CHECK1-NEXT: br i1 [[TMP22]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]]752// CHECK1: omp_offload.failed.i:753// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR3]]754// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__EXIT]]755// CHECK1: .omp_outlined..exit:756// CHECK1-NEXT: ret i32 0757//758//759// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101760// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR2]] {761// CHECK1-NEXT: entry:762// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8763// CHECK1-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8764// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8765// CHECK1-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8766// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8767// CHECK1-NEXT: store i64 [[K]], ptr [[K_ADDR]], align 8768// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4769// CHECK1-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4770// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8771// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[K_ADDR]], align 8772// CHECK1-NEXT: store i64 [[TMP2]], ptr [[K_CASTED]], align 8773// CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[K_CASTED]], align 8774// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined, i64 [[TMP1]], i64 [[TMP3]])775// CHECK1-NEXT: ret void776//777//778// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined779// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR2]] {780// CHECK1-NEXT: entry:781// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8782// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8783// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8784// CHECK1-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8785// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4786// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4787// CHECK1-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8788// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4789// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4790// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4791// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4792// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4793// CHECK1-NEXT: [[K1:%.*]] = alloca i64, align 8794// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8795// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8796// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8797// CHECK1-NEXT: store i64 [[K]], ptr [[K_ADDR]], align 8798// CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[K_ADDR]], align 8799// CHECK1-NEXT: store i64 [[TMP0]], ptr [[DOTLINEAR_START]], align 8800// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4801// CHECK1-NEXT: store i32 8, ptr [[DOTOMP_UB]], align 4802// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4803// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4804// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8805// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4806// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP2]])807// CHECK1-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 35, i32 0, i32 8, i32 1, i32 1)808// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]]809// CHECK1: omp.dispatch.cond:810// CHECK1-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB2]], i32 [[TMP2]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])811// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0812// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]813// CHECK1: omp.dispatch.body:814// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4815// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4816// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]817// CHECK1: omp.inner.for.cond:818// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26:![0-9]+]]819// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP26]]820// CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]821// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]822// CHECK1: omp.inner.for.body:823// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]]824// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1825// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]826// CHECK1-NEXT: store i32 [[SUB]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP26]]827// CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP26]]828// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]]829// CHECK1-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3830// CHECK1-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64831// CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV]]832// CHECK1-NEXT: store i64 [[ADD]], ptr [[K1]], align 8, !llvm.access.group [[ACC_GRP26]]833// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP26]]834// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1835// CHECK1-NEXT: store i32 [[ADD3]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP26]]836// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]837// CHECK1: omp.body.continue:838// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]839// CHECK1: omp.inner.for.inc:840// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]]841// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1842// CHECK1-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]]843// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]]844// CHECK1: omp.inner.for.end:845// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]846// CHECK1: omp.dispatch.inc:847// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]848// CHECK1: omp.dispatch.end:849// CHECK1-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB2]], i32 [[TMP2]])850// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4851// CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0852// CHECK1-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]853// CHECK1: .omp.final.then:854// CHECK1-NEXT: store i32 1, ptr [[I]], align 4855// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]856// CHECK1: .omp.final.done:857// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4858// CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0859// CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]860// CHECK1: .omp.linear.pu:861// CHECK1-NEXT: [[TMP16:%.*]] = load i64, ptr [[K1]], align 8862// CHECK1-NEXT: store i64 [[TMP16]], ptr [[K_ADDR]], align 8863// CHECK1-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]864// CHECK1: .omp.linear.pu.done:865// CHECK1-NEXT: ret void866//867//868// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108869// CHECK1-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] {870// CHECK1-NEXT: entry:871// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8872// CHECK1-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8873// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8874// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8875// CHECK1-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8876// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8877// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8878// CHECK1-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 8879// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8880// CHECK1-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2881// CHECK1-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2882// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8883// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 4884// CHECK1-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 4885// CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[LIN_CASTED]], align 8886// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4887// CHECK1-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 4888// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[A_CASTED]], align 8889// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined, i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])890// CHECK1-NEXT: ret void891//892//893// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined894// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] {895// CHECK1-NEXT: entry:896// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8897// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8898// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8899// CHECK1-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8900// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8901// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8902// CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8903// CHECK1-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4904// CHECK1-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4905// CHECK1-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8906// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8907// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8908// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8909// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4910// CHECK1-NEXT: [[IT:%.*]] = alloca i64, align 8911// CHECK1-NEXT: [[LIN2:%.*]] = alloca i32, align 4912// CHECK1-NEXT: [[A3:%.*]] = alloca i32, align 4913// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8914// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8915// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8916// CHECK1-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 8917// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8918// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 4919// CHECK1-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 4920// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4921// CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 4922// CHECK1-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()923// CHECK1-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 8924// CHECK1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8925// CHECK1-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8926// CHECK1-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8927// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4928// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8929// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4930// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP3]])931// CHECK1-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)932// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8933// CHECK1-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3934// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]935// CHECK1: cond.true:936// CHECK1-NEXT: br label [[COND_END:%.*]]937// CHECK1: cond.false:938// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8939// CHECK1-NEXT: br label [[COND_END]]940// CHECK1: cond.end:941// CHECK1-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]942// CHECK1-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8943// CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8944// CHECK1-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 8945// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]946// CHECK1: omp.inner.for.cond:947// CHECK1-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29:![0-9]+]]948// CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP29]]949// CHECK1-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]950// CHECK1-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]951// CHECK1: omp.inner.for.body:952// CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]]953// CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400954// CHECK1-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]955// CHECK1-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP29]]956// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP29]]957// CHECK1-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i64958// CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]]959// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP29]]960// CHECK1-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]]961// CHECK1-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]]962// CHECK1-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i32963// CHECK1-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 4, !llvm.access.group [[ACC_GRP29]]964// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4, !llvm.access.group [[ACC_GRP29]]965// CHECK1-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64966// CHECK1-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]]967// CHECK1-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP29]]968// CHECK1-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]]969// CHECK1-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]]970// CHECK1-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i32971// CHECK1-NEXT: store i32 [[CONV10]], ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP29]]972// CHECK1-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP29]]973// CHECK1-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i32974// CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 1975// CHECK1-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16976// CHECK1-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP29]]977// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]978// CHECK1: omp.body.continue:979// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]980// CHECK1: omp.inner.for.inc:981// CHECK1-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]]982// CHECK1-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 1983// CHECK1-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]]984// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]]985// CHECK1: omp.inner.for.end:986// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]987// CHECK1: omp.loop.exit:988// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]])989// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4990// CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0991// CHECK1-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]992// CHECK1: .omp.final.then:993// CHECK1-NEXT: store i64 400, ptr [[IT]], align 8994// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]995// CHECK1: .omp.final.done:996// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4997// CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0998// CHECK1-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]999// CHECK1: .omp.linear.pu:1000// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[LIN2]], align 41001// CHECK1-NEXT: store i32 [[TMP22]], ptr [[LIN_ADDR]], align 41002// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[A3]], align 41003// CHECK1-NEXT: store i32 [[TMP23]], ptr [[A_ADDR]], align 41004// CHECK1-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]1005// CHECK1: .omp.linear.pu.done:1006// CHECK1-NEXT: ret void1007//1008//1009// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1161010// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {1011// CHECK1-NEXT: entry:1012// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 81013// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 81014// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 81015// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 81016// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 81017// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 81018// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41019// CHECK1-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 41020// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 81021// CHECK1-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 21022// CHECK1-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 21023// CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 81024// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined, i64 [[TMP1]], i64 [[TMP3]])1025// CHECK1-NEXT: ret void1026//1027//1028// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined1029// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {1030// CHECK1-NEXT: entry:1031// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81032// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81033// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 81034// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 81035// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41036// CHECK1-NEXT: [[TMP:%.*]] = alloca i16, align 21037// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 41038// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 41039// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41040// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41041// CHECK1-NEXT: [[IT:%.*]] = alloca i16, align 21042// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81043// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81044// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 81045// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 81046// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 41047// CHECK1-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 41048// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 41049// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41050// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81051// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 41052// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1053// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41054// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 31055// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1056// CHECK1: cond.true:1057// CHECK1-NEXT: br label [[COND_END:%.*]]1058// CHECK1: cond.false:1059// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41060// CHECK1-NEXT: br label [[COND_END]]1061// CHECK1: cond.end:1062// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]1063// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 41064// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41065// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 41066// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1067// CHECK1: omp.inner.for.cond:1068// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32:![0-9]+]]1069// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP32]]1070// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]1071// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1072// CHECK1: omp.inner.for.body:1073// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]]1074// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 41075// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]1076// CHECK1-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i161077// CHECK1-NEXT: store i16 [[CONV]], ptr [[IT]], align 2, !llvm.access.group [[ACC_GRP32]]1078// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP32]]1079// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 11080// CHECK1-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP32]]1081// CHECK1-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP32]]1082// CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i321083// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 11084// CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i161085// CHECK1-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP32]]1086// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1087// CHECK1: omp.body.continue:1088// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1089// CHECK1: omp.inner.for.inc:1090// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]]1091// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 11092// CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]]1093// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]]1094// CHECK1: omp.inner.for.end:1095// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]1096// CHECK1: omp.loop.exit:1097// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])1098// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 41099// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 01100// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]1101// CHECK1: .omp.final.then:1102// CHECK1-NEXT: store i16 22, ptr [[IT]], align 21103// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]1104// CHECK1: .omp.final.done:1105// CHECK1-NEXT: ret void1106//1107//1108// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1401109// CHECK1-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {1110// CHECK1-NEXT: entry:1111// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 81112// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 81113// CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 81114// CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 81115// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 81116// CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 81117// CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 81118// CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 81119// CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 81120// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 81121// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 81122// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 81123// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 81124// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 81125// CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 81126// CHECK1-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 81127// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 81128// CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 81129// CHECK1-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 81130// CHECK1-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 81131// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 81132// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 81133// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 81134// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 81135// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 81136// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 81137// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 81138// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 81139// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 81140// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 81141// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 41142// CHECK1-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 41143// CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 81144// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 41145// CHECK1-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 41146// CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 81147// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i64 [[TMP11]])1148// CHECK1-NEXT: ret void1149//1150//1151// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined1152// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {1153// CHECK1-NEXT: entry:1154// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81155// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81156// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 81157// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 81158// CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 81159// CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 81160// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 81161// CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 81162// CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 81163// CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 81164// CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 81165// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 81166// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41167// CHECK1-NEXT: [[TMP:%.*]] = alloca i8, align 11168// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 41169// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 41170// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41171// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41172// CHECK1-NEXT: [[IT:%.*]] = alloca i8, align 11173// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81174// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81175// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 81176// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 81177// CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 81178// CHECK1-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 81179// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 81180// CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 81181// CHECK1-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 81182// CHECK1-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 81183// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 81184// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 81185// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 81186// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 81187// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 81188// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 81189// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 81190// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 81191// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 81192// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 81193// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 41194// CHECK1-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 41195// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 41196// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41197// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 41198// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81199// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 41200// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])1201// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]]1202// CHECK1: omp.dispatch.cond:1203// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41204// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 251205// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1206// CHECK1: cond.true:1207// CHECK1-NEXT: br label [[COND_END:%.*]]1208// CHECK1: cond.false:1209// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41210// CHECK1-NEXT: br label [[COND_END]]1211// CHECK1: cond.end:1212// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]1213// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 41214// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41215// CHECK1-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 41216// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41217// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41218// CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]1219// CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]1220// CHECK1: omp.dispatch.body:1221// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1222// CHECK1: omp.inner.for.cond:1223// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35:![0-9]+]]1224// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP35]]1225// CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]1226// CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1227// CHECK1: omp.inner.for.body:1228// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]]1229// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 11230// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]1231// CHECK1-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i81232// CHECK1-NEXT: store i8 [[CONV]], ptr [[IT]], align 1, !llvm.access.group [[ACC_GRP35]]1233// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP35]]1234// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 11235// CHECK1-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP35]]1236// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 21237// CHECK1-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP35]]1238// CHECK1-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double1239// CHECK1-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+001240// CHECK1-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float1241// CHECK1-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP35]]1242// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 31243// CHECK1-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP35]]1244// CHECK1-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double1245// CHECK1-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+001246// CHECK1-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float1247// CHECK1-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP35]]1248// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 11249// CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i64 0, i64 21250// CHECK1-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP35]]1251// CHECK1-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+001252// CHECK1-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP35]]1253// CHECK1-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]1254// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP23]]1255// CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i64 31256// CHECK1-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP35]]1257// CHECK1-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+001258// CHECK1-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP35]]1259// CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 01260// CHECK1-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP35]]1261// CHECK1-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 11262// CHECK1-NEXT: store i64 [[ADD20]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP35]]1263// CHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 11264// CHECK1-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP35]]1265// CHECK1-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i321266// CHECK1-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 11267// CHECK1-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i81268// CHECK1-NEXT: store i8 [[CONV23]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP35]]1269// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1270// CHECK1: omp.body.continue:1271// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1272// CHECK1: omp.inner.for.inc:1273// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]]1274// CHECK1-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 11275// CHECK1-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]]1276// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]]1277// CHECK1: omp.inner.for.end:1278// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]1279// CHECK1: omp.dispatch.inc:1280// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41281// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 41282// CHECK1-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]1283// CHECK1-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 41284// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41285// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 41286// CHECK1-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]1287// CHECK1-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 41288// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]1289// CHECK1: omp.dispatch.end:1290// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]])1291// CHECK1-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 41292// CHECK1-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 01293// CHECK1-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]1294// CHECK1: .omp.final.then:1295// CHECK1-NEXT: store i8 96, ptr [[IT]], align 11296// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]1297// CHECK1: .omp.final.done:1298// CHECK1-NEXT: ret void1299//1300//1301// CHECK1-LABEL: define {{[^@]+}}@_Z3bari1302// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {1303// CHECK1-NEXT: entry:1304// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 41305// CHECK1-NEXT: [[A:%.*]] = alloca i32, align 41306// CHECK1-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 81307// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 41308// CHECK1-NEXT: store i32 0, ptr [[A]], align 41309// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 41310// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]])1311// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 41312// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]1313// CHECK1-NEXT: store i32 [[ADD]], ptr [[A]], align 41314// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 41315// CHECK1-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]])1316// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 41317// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]1318// CHECK1-NEXT: store i32 [[ADD2]], ptr [[A]], align 41319// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 41320// CHECK1-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]])1321// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 41322// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]1323// CHECK1-NEXT: store i32 [[ADD4]], ptr [[A]], align 41324// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 41325// CHECK1-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]])1326// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 41327// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]1328// CHECK1-NEXT: store i32 [[ADD6]], ptr [[A]], align 41329// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 41330// CHECK1-NEXT: ret i32 [[TMP8]]1331//1332//1333// CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei1334// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {1335// CHECK1-NEXT: entry:1336// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81337// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 41338// CHECK1-NEXT: [[B:%.*]] = alloca i32, align 41339// CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 81340// CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 81341// CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 81342// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 81343// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 81344// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 81345// CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 81346// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81347// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81348// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 41349// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81350// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 41351// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 11352// CHECK1-NEXT: store i32 [[ADD]], ptr [[B]], align 41353// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 41354// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i641355// CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()1356// CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 81357// CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]1358// CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 21359// CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 81360// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 41361// CHECK1-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 41362// CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 81363// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 41364// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 601365// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]1366// CHECK1: omp_if.then:1367// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 01368// CHECK1-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]]1369// CHECK1-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 21370// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.5, i64 40, i1 false)1371// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01372// CHECK1-NEXT: store ptr [[THIS1]], ptr [[TMP10]], align 81373// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01374// CHECK1-NEXT: store ptr [[A]], ptr [[TMP11]], align 81375// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 01376// CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 81377// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 11378// CHECK1-NEXT: store i64 [[TMP6]], ptr [[TMP13]], align 81379// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 11380// CHECK1-NEXT: store i64 [[TMP6]], ptr [[TMP14]], align 81381// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 11382// CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 81383// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 21384// CHECK1-NEXT: store i64 2, ptr [[TMP16]], align 81385// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 21386// CHECK1-NEXT: store i64 2, ptr [[TMP17]], align 81387// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 21388// CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 81389// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 31390// CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP19]], align 81391// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 31392// CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP20]], align 81393// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 31394// CHECK1-NEXT: store ptr null, ptr [[TMP21]], align 81395// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 41396// CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP22]], align 81397// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 41398// CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP23]], align 81399// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 41400// CHECK1-NEXT: store i64 [[TMP9]], ptr [[TMP24]], align 81401// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 41402// CHECK1-NEXT: store ptr null, ptr [[TMP25]], align 81403// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01404// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01405// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 01406// CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 01407// CHECK1-NEXT: store i32 3, ptr [[TMP29]], align 41408// CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11409// CHECK1-NEXT: store i32 5, ptr [[TMP30]], align 41410// CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 21411// CHECK1-NEXT: store ptr [[TMP26]], ptr [[TMP31]], align 81412// CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 31413// CHECK1-NEXT: store ptr [[TMP27]], ptr [[TMP32]], align 81414// CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 41415// CHECK1-NEXT: store ptr [[TMP28]], ptr [[TMP33]], align 81416// CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 51417// CHECK1-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP34]], align 81418// CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 61419// CHECK1-NEXT: store ptr null, ptr [[TMP35]], align 81420// CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 71421// CHECK1-NEXT: store ptr null, ptr [[TMP36]], align 81422// CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 81423// CHECK1-NEXT: store i64 0, ptr [[TMP37]], align 81424// CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 91425// CHECK1-NEXT: store i64 0, ptr [[TMP38]], align 81426// CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 101427// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP39]], align 41428// CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 111429// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP40]], align 41430// CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 121431// CHECK1-NEXT: store i32 0, ptr [[TMP41]], align 41432// CHECK1-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, ptr [[KERNEL_ARGS]])1433// CHECK1-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 01434// CHECK1-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]1435// CHECK1: omp_offload.failed:1436// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR3]]1437// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]1438// CHECK1: omp_offload.cont:1439// CHECK1-NEXT: br label [[OMP_IF_END:%.*]]1440// CHECK1: omp_if.else:1441// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR3]]1442// CHECK1-NEXT: br label [[OMP_IF_END]]1443// CHECK1: omp_if.end:1444// CHECK1-NEXT: [[TMP44:%.*]] = mul nsw i64 1, [[TMP2]]1445// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP44]]1446// CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 11447// CHECK1-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 21448// CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i321449// CHECK1-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 41450// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]]1451// CHECK1-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 81452// CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP47]])1453// CHECK1-NEXT: ret i32 [[ADD3]]1454//1455//1456// CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici1457// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {1458// CHECK1-NEXT: entry:1459// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 41460// CHECK1-NEXT: [[A:%.*]] = alloca i32, align 41461// CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 21462// CHECK1-NEXT: [[AAA:%.*]] = alloca i8, align 11463// CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 41464// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 81465// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 81466// CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 81467// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 81468// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 81469// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 81470// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81471// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 41472// CHECK1-NEXT: store i32 0, ptr [[A]], align 41473// CHECK1-NEXT: store i16 0, ptr [[AA]], align 21474// CHECK1-NEXT: store i8 0, ptr [[AAA]], align 11475// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 41476// CHECK1-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 41477// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 81478// CHECK1-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 21479// CHECK1-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 21480// CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 81481// CHECK1-NEXT: [[TMP4:%.*]] = load i8, ptr [[AAA]], align 11482// CHECK1-NEXT: store i8 [[TMP4]], ptr [[AAA_CASTED]], align 11483// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[AAA_CASTED]], align 81484// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 41485// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 501486// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]1487// CHECK1: omp_if.then:1488// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01489// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP7]], align 81490// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01491// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP8]], align 81492// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 01493// CHECK1-NEXT: store ptr null, ptr [[TMP9]], align 81494// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 11495// CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP10]], align 81496// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 11497// CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP11]], align 81498// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 11499// CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 81500// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 21501// CHECK1-NEXT: store i64 [[TMP5]], ptr [[TMP13]], align 81502// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 21503// CHECK1-NEXT: store i64 [[TMP5]], ptr [[TMP14]], align 81504// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 21505// CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 81506// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 31507// CHECK1-NEXT: store ptr [[B]], ptr [[TMP16]], align 81508// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 31509// CHECK1-NEXT: store ptr [[B]], ptr [[TMP17]], align 81510// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 31511// CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 81512// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01513// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01514// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 01515// CHECK1-NEXT: store i32 3, ptr [[TMP21]], align 41516// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11517// CHECK1-NEXT: store i32 4, ptr [[TMP22]], align 41518// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 21519// CHECK1-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 81520// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 31521// CHECK1-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 81522// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 41523// CHECK1-NEXT: store ptr @.offload_sizes.7, ptr [[TMP25]], align 81524// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 51525// CHECK1-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP26]], align 81526// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 61527// CHECK1-NEXT: store ptr null, ptr [[TMP27]], align 81528// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 71529// CHECK1-NEXT: store ptr null, ptr [[TMP28]], align 81530// CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 81531// CHECK1-NEXT: store i64 0, ptr [[TMP29]], align 81532// CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 91533// CHECK1-NEXT: store i64 0, ptr [[TMP30]], align 81534// CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 101535// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP31]], align 41536// CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 111537// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP32]], align 41538// CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 121539// CHECK1-NEXT: store i32 0, ptr [[TMP33]], align 41540// CHECK1-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.region_id, ptr [[KERNEL_ARGS]])1541// CHECK1-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 01542// CHECK1-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]1543// CHECK1: omp_offload.failed:1544// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR3]]1545// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]1546// CHECK1: omp_offload.cont:1547// CHECK1-NEXT: br label [[OMP_IF_END:%.*]]1548// CHECK1: omp_if.else:1549// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR3]]1550// CHECK1-NEXT: br label [[OMP_IF_END]]1551// CHECK1: omp_if.end:1552// CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[A]], align 41553// CHECK1-NEXT: ret i32 [[TMP36]]1554//1555//1556// CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i1557// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {1558// CHECK1-NEXT: entry:1559// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 41560// CHECK1-NEXT: [[A:%.*]] = alloca i32, align 41561// CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 21562// CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 41563// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 81564// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 81565// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 81566// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 81567// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 81568// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81569// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 41570// CHECK1-NEXT: store i32 0, ptr [[A]], align 41571// CHECK1-NEXT: store i16 0, ptr [[AA]], align 21572// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 41573// CHECK1-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 41574// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 81575// CHECK1-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 21576// CHECK1-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 21577// CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 81578// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 41579// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 401580// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]1581// CHECK1: omp_if.then:1582// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01583// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP5]], align 81584// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01585// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP6]], align 81586// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 01587// CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 81588// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 11589// CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP8]], align 81590// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 11591// CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP9]], align 81592// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 11593// CHECK1-NEXT: store ptr null, ptr [[TMP10]], align 81594// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 21595// CHECK1-NEXT: store ptr [[B]], ptr [[TMP11]], align 81596// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 21597// CHECK1-NEXT: store ptr [[B]], ptr [[TMP12]], align 81598// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 21599// CHECK1-NEXT: store ptr null, ptr [[TMP13]], align 81600// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01601// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01602// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 01603// CHECK1-NEXT: store i32 3, ptr [[TMP16]], align 41604// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11605// CHECK1-NEXT: store i32 3, ptr [[TMP17]], align 41606// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 21607// CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 81608// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 31609// CHECK1-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 81610// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 41611// CHECK1-NEXT: store ptr @.offload_sizes.9, ptr [[TMP20]], align 81612// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 51613// CHECK1-NEXT: store ptr @.offload_maptypes.10, ptr [[TMP21]], align 81614// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 61615// CHECK1-NEXT: store ptr null, ptr [[TMP22]], align 81616// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 71617// CHECK1-NEXT: store ptr null, ptr [[TMP23]], align 81618// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 81619// CHECK1-NEXT: store i64 0, ptr [[TMP24]], align 81620// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 91621// CHECK1-NEXT: store i64 0, ptr [[TMP25]], align 81622// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 101623// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP26]], align 41624// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 111625// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP27]], align 41626// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 121627// CHECK1-NEXT: store i32 0, ptr [[TMP28]], align 41628// CHECK1-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.region_id, ptr [[KERNEL_ARGS]])1629// CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 01630// CHECK1-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]1631// CHECK1: omp_offload.failed:1632// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]]1633// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]1634// CHECK1: omp_offload.cont:1635// CHECK1-NEXT: br label [[OMP_IF_END:%.*]]1636// CHECK1: omp_if.else:1637// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]]1638// CHECK1-NEXT: br label [[OMP_IF_END]]1639// CHECK1: omp_if.end:1640// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[A]], align 41641// CHECK1-NEXT: ret i32 [[TMP31]]1642//1643//1644// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l2161645// CHECK1-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {1646// CHECK1-NEXT: entry:1647// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81648// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 81649// CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 81650// CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 81651// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 81652// CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 81653// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81654// CHECK1-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 81655// CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 81656// CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 81657// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 81658// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81659// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 81660// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 81661// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 81662// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 41663// CHECK1-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 41664// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 81665// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]])1666// CHECK1-NEXT: ret void1667//1668//1669// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined1670// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {1671// CHECK1-NEXT: entry:1672// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81673// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81674// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81675// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 81676// CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 81677// CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 81678// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 81679// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 81680// CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 81681// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 81682// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 81683// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 81684// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41685// CHECK1-NEXT: [[IT:%.*]] = alloca i64, align 81686// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81687// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81688// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81689// CHECK1-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 81690// CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 81691// CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 81692// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 81693// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81694// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 81695// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 81696// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 81697// CHECK1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 81698// CHECK1-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 81699// CHECK1-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 81700// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41701// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81702// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 41703// CHECK1-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)1704// CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_UB]], align 81705// CHECK1-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 31706// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1707// CHECK1: cond.true:1708// CHECK1-NEXT: br label [[COND_END:%.*]]1709// CHECK1: cond.false:1710// CHECK1-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 81711// CHECK1-NEXT: br label [[COND_END]]1712// CHECK1: cond.end:1713// CHECK1-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]1714// CHECK1-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 81715// CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_LB]], align 81716// CHECK1-NEXT: store i64 [[TMP8]], ptr [[DOTOMP_IV]], align 81717// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1718// CHECK1: omp.inner.for.cond:1719// CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38:![0-9]+]]1720// CHECK1-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP38]]1721// CHECK1-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]1722// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1723// CHECK1: omp.inner.for.body:1724// CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38]]1725// CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 4001726// CHECK1-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]1727// CHECK1-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP38]]1728// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP38]]1729// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double1730// CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+001731// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 01732// CHECK1-NEXT: store double [[ADD]], ptr [[A]], align 8, !llvm.access.group [[ACC_GRP38]]1733// CHECK1-NEXT: [[A4:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 01734// CHECK1-NEXT: [[TMP13:%.*]] = load double, ptr [[A4]], align 8, !llvm.access.group [[ACC_GRP38]]1735// CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+001736// CHECK1-NEXT: store double [[INC]], ptr [[A4]], align 8, !llvm.access.group [[ACC_GRP38]]1737// CHECK1-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i161738// CHECK1-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]1739// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP14]]1740// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 11741// CHECK1-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP38]]1742// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1743// CHECK1: omp.body.continue:1744// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1745// CHECK1: omp.inner.for.inc:1746// CHECK1-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38]]1747// CHECK1-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 11748// CHECK1-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38]]1749// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP39:![0-9]+]]1750// CHECK1: omp.inner.for.end:1751// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]1752// CHECK1: omp.loop.exit:1753// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])1754// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 41755// CHECK1-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 01756// CHECK1-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]1757// CHECK1: .omp.final.then:1758// CHECK1-NEXT: store i64 400, ptr [[IT]], align 81759// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]1760// CHECK1: .omp.final.done:1761// CHECK1-NEXT: ret void1762//1763//1764// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l1951765// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {1766// CHECK1-NEXT: entry:1767// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 81768// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 81769// CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 81770// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 81771// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 81772// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 81773// CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 81774// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 81775// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 81776// CHECK1-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 81777// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 81778// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 81779// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 41780// CHECK1-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 41781// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 81782// CHECK1-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 21783// CHECK1-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 21784// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 81785// CHECK1-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 11786// CHECK1-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 11787// CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[AAA_CASTED]], align 81788// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], ptr [[TMP0]])1789// CHECK1-NEXT: ret void1790//1791//1792// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined1793// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {1794// CHECK1-NEXT: entry:1795// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81796// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81797// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 81798// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 81799// CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 81800// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 81801// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41802// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 41803// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81804// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81805// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 81806// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 81807// CHECK1-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 81808// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 81809// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 81810// CHECK1-NEXT: ret void1811//1812//1813// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l1781814// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {1815// CHECK1-NEXT: entry:1816// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 81817// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 81818// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 81819// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 81820// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 81821// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 81822// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 81823// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 81824// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 81825// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 41826// CHECK1-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 41827// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 81828// CHECK1-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 21829// CHECK1-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 21830// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 81831// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]])1832// CHECK1-NEXT: ret void1833//1834//1835// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined1836// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {1837// CHECK1-NEXT: entry:1838// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81839// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81840// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 81841// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 81842// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 81843// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 81844// CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 81845// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 81846// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 81847// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 81848// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41849// CHECK1-NEXT: [[I:%.*]] = alloca i64, align 81850// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81851// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81852// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 81853// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 81854// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 81855// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 81856// CHECK1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 81857// CHECK1-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 81858// CHECK1-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 81859// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41860// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81861// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 41862// CHECK1-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)1863// CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 81864// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 61865// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1866// CHECK1: cond.true:1867// CHECK1-NEXT: br label [[COND_END:%.*]]1868// CHECK1: cond.false:1869// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 81870// CHECK1-NEXT: br label [[COND_END]]1871// CHECK1: cond.end:1872// CHECK1-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]1873// CHECK1-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 81874// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 81875// CHECK1-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 81876// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1877// CHECK1: omp.inner.for.cond:1878// CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP41:![0-9]+]]1879// CHECK1-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP41]]1880// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]1881// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1882// CHECK1: omp.inner.for.body:1883// CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP41]]1884// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 31885// CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]1886// CHECK1-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP41]]1887// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP41]]1888// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 11889// CHECK1-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP41]]1890// CHECK1-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP41]]1891// CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i321892// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 11893// CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i161894// CHECK1-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP41]]1895// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 21896// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP41]]1897// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 11898// CHECK1-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP41]]1899// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1900// CHECK1: omp.body.continue:1901// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1902// CHECK1: omp.inner.for.inc:1903// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP41]]1904// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 11905// CHECK1-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP41]]1906// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP42:![0-9]+]]1907// CHECK1: omp.inner.for.end:1908// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]1909// CHECK1: omp.loop.exit:1910// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])1911// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 41912// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 01913// CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]1914// CHECK1: .omp.final.then:1915// CHECK1-NEXT: store i64 11, ptr [[I]], align 81916// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]1917// CHECK1: .omp.final.done:1918// CHECK1-NEXT: ret void1919//1920//1921// CHECK3-LABEL: define {{[^@]+}}@_Z7get_valv1922// CHECK3-SAME: () #[[ATTR0:[0-9]+]] {1923// CHECK3-NEXT: entry:1924// CHECK3-NEXT: ret i64 01925//1926//1927// CHECK3-LABEL: define {{[^@]+}}@_Z3fooi1928// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {1929// CHECK3-NEXT: entry:1930// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 41931// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 41932// CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 21933// CHECK3-NEXT: [[B:%.*]] = alloca [10 x float], align 41934// CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 41935// CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 41936// CHECK3-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 81937// CHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 41938// CHECK3-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 41939// CHECK3-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 11940// CHECK3-NEXT: [[K:%.*]] = alloca i64, align 81941// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 41942// CHECK3-NEXT: [[LIN:%.*]] = alloca i32, align 41943// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 41944// CHECK3-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 41945// CHECK3-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 41946// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 41947// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 41948// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 41949// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81950// CHECK3-NEXT: [[A_CASTED3:%.*]] = alloca i32, align 41951// CHECK3-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 41952// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x ptr], align 41953// CHECK3-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x ptr], align 41954// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x ptr], align 41955// CHECK3-NEXT: [[KERNEL_ARGS8:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 81956// CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 41957// CHECK3-NEXT: [[A_CASTED11:%.*]] = alloca i32, align 41958// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 41959// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x ptr], align 41960// CHECK3-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x ptr], align 41961// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x ptr], align 41962// CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 41963// CHECK3-NEXT: [[KERNEL_ARGS17:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 81964// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])1965// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 41966// CHECK3-NEXT: store i32 0, ptr [[A]], align 41967// CHECK3-NEXT: store i16 0, ptr [[AA]], align 21968// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 41969// CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()1970// CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 41971// CHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 41972// CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 41973// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 41974// CHECK3-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]1975// CHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 81976// CHECK3-NEXT: store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 41977// CHECK3-NEXT: [[TMP5:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 20, i32 1, ptr @.omp_task_entry., i64 -1)1978// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP5]], i32 0, i32 01979// CHECK3-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB2]], i32 [[TMP0]], ptr [[TMP5]])1980// CHECK3-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()1981// CHECK3-NEXT: store i64 [[CALL]], ptr [[K]], align 81982// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 41983// CHECK3-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 41984// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 41985// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP9]], ptr [[K]]) #[[ATTR3:[0-9]+]]1986// CHECK3-NEXT: store i32 12, ptr [[LIN]], align 41987// CHECK3-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 21988// CHECK3-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 21989// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[AA_CASTED]], align 41990// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[LIN]], align 41991// CHECK3-NEXT: store i32 [[TMP12]], ptr [[LIN_CASTED]], align 41992// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[LIN_CASTED]], align 41993// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 41994// CHECK3-NEXT: store i32 [[TMP14]], ptr [[A_CASTED2]], align 41995// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[A_CASTED2]], align 41996// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01997// CHECK3-NEXT: store i32 [[TMP11]], ptr [[TMP16]], align 41998// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01999// CHECK3-NEXT: store i32 [[TMP11]], ptr [[TMP17]], align 42000// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 02001// CHECK3-NEXT: store ptr null, ptr [[TMP18]], align 42002// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 12003// CHECK3-NEXT: store i32 [[TMP13]], ptr [[TMP19]], align 42004// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 12005// CHECK3-NEXT: store i32 [[TMP13]], ptr [[TMP20]], align 42006// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 12007// CHECK3-NEXT: store ptr null, ptr [[TMP21]], align 42008// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 22009// CHECK3-NEXT: store i32 [[TMP15]], ptr [[TMP22]], align 42010// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 22011// CHECK3-NEXT: store i32 [[TMP15]], ptr [[TMP23]], align 42012// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 22013// CHECK3-NEXT: store ptr null, ptr [[TMP24]], align 42014// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 02015// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 02016// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 02017// CHECK3-NEXT: store i32 3, ptr [[TMP27]], align 42018// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12019// CHECK3-NEXT: store i32 3, ptr [[TMP28]], align 42020// CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 22021// CHECK3-NEXT: store ptr [[TMP25]], ptr [[TMP29]], align 42022// CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 32023// CHECK3-NEXT: store ptr [[TMP26]], ptr [[TMP30]], align 42024// CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 42025// CHECK3-NEXT: store ptr @.offload_sizes, ptr [[TMP31]], align 42026// CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 52027// CHECK3-NEXT: store ptr @.offload_maptypes, ptr [[TMP32]], align 42028// CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 62029// CHECK3-NEXT: store ptr null, ptr [[TMP33]], align 42030// CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 72031// CHECK3-NEXT: store ptr null, ptr [[TMP34]], align 42032// CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 82033// CHECK3-NEXT: store i64 0, ptr [[TMP35]], align 82034// CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 92035// CHECK3-NEXT: store i64 0, ptr [[TMP36]], align 82036// CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 102037// CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP37]], align 42038// CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 112039// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP38]], align 42040// CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 122041// CHECK3-NEXT: store i32 0, ptr [[TMP39]], align 42042// CHECK3-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.region_id, ptr [[KERNEL_ARGS]])2043// CHECK3-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 02044// CHECK3-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]2045// CHECK3: omp_offload.failed:2046// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i32 [[TMP11]], i32 [[TMP13]], i32 [[TMP15]]) #[[ATTR3]]2047// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]2048// CHECK3: omp_offload.cont:2049// CHECK3-NEXT: [[TMP42:%.*]] = load i32, ptr [[A]], align 42050// CHECK3-NEXT: store i32 [[TMP42]], ptr [[A_CASTED3]], align 42051// CHECK3-NEXT: [[TMP43:%.*]] = load i32, ptr [[A_CASTED3]], align 42052// CHECK3-NEXT: [[TMP44:%.*]] = load i16, ptr [[AA]], align 22053// CHECK3-NEXT: store i16 [[TMP44]], ptr [[AA_CASTED4]], align 22054// CHECK3-NEXT: [[TMP45:%.*]] = load i32, ptr [[AA_CASTED4]], align 42055// CHECK3-NEXT: [[TMP46:%.*]] = load i32, ptr [[N_ADDR]], align 42056// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP46]], 102057// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]2058// CHECK3: omp_if.then:2059// CHECK3-NEXT: [[TMP47:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 02060// CHECK3-NEXT: store i32 [[TMP43]], ptr [[TMP47]], align 42061// CHECK3-NEXT: [[TMP48:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 02062// CHECK3-NEXT: store i32 [[TMP43]], ptr [[TMP48]], align 42063// CHECK3-NEXT: [[TMP49:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 02064// CHECK3-NEXT: store ptr null, ptr [[TMP49]], align 42065// CHECK3-NEXT: [[TMP50:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 12066// CHECK3-NEXT: store i32 [[TMP45]], ptr [[TMP50]], align 42067// CHECK3-NEXT: [[TMP51:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 12068// CHECK3-NEXT: store i32 [[TMP45]], ptr [[TMP51]], align 42069// CHECK3-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 12070// CHECK3-NEXT: store ptr null, ptr [[TMP52]], align 42071// CHECK3-NEXT: [[TMP53:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 02072// CHECK3-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 02073// CHECK3-NEXT: [[TMP55:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 02074// CHECK3-NEXT: store i32 3, ptr [[TMP55]], align 42075// CHECK3-NEXT: [[TMP56:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 12076// CHECK3-NEXT: store i32 2, ptr [[TMP56]], align 42077// CHECK3-NEXT: [[TMP57:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 22078// CHECK3-NEXT: store ptr [[TMP53]], ptr [[TMP57]], align 42079// CHECK3-NEXT: [[TMP58:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 32080// CHECK3-NEXT: store ptr [[TMP54]], ptr [[TMP58]], align 42081// CHECK3-NEXT: [[TMP59:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 42082// CHECK3-NEXT: store ptr @.offload_sizes.1, ptr [[TMP59]], align 42083// CHECK3-NEXT: [[TMP60:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 52084// CHECK3-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP60]], align 42085// CHECK3-NEXT: [[TMP61:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 62086// CHECK3-NEXT: store ptr null, ptr [[TMP61]], align 42087// CHECK3-NEXT: [[TMP62:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 72088// CHECK3-NEXT: store ptr null, ptr [[TMP62]], align 42089// CHECK3-NEXT: [[TMP63:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 82090// CHECK3-NEXT: store i64 0, ptr [[TMP63]], align 82091// CHECK3-NEXT: [[TMP64:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 92092// CHECK3-NEXT: store i64 0, ptr [[TMP64]], align 82093// CHECK3-NEXT: [[TMP65:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 102094// CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP65]], align 42095// CHECK3-NEXT: [[TMP66:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 112096// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP66]], align 42097// CHECK3-NEXT: [[TMP67:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 122098// CHECK3-NEXT: store i32 0, ptr [[TMP67]], align 42099// CHECK3-NEXT: [[TMP68:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.region_id, ptr [[KERNEL_ARGS8]])2100// CHECK3-NEXT: [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 02101// CHECK3-NEXT: br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]]2102// CHECK3: omp_offload.failed9:2103// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP43]], i32 [[TMP45]]) #[[ATTR3]]2104// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT10]]2105// CHECK3: omp_offload.cont10:2106// CHECK3-NEXT: br label [[OMP_IF_END:%.*]]2107// CHECK3: omp_if.else:2108// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP43]], i32 [[TMP45]]) #[[ATTR3]]2109// CHECK3-NEXT: br label [[OMP_IF_END]]2110// CHECK3: omp_if.end:2111// CHECK3-NEXT: [[TMP70:%.*]] = load i32, ptr [[A]], align 42112// CHECK3-NEXT: store i32 [[TMP70]], ptr [[DOTCAPTURE_EXPR_]], align 42113// CHECK3-NEXT: [[TMP71:%.*]] = load i32, ptr [[A]], align 42114// CHECK3-NEXT: store i32 [[TMP71]], ptr [[A_CASTED11]], align 42115// CHECK3-NEXT: [[TMP72:%.*]] = load i32, ptr [[A_CASTED11]], align 42116// CHECK3-NEXT: [[TMP73:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 42117// CHECK3-NEXT: store i32 [[TMP73]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 42118// CHECK3-NEXT: [[TMP74:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 42119// CHECK3-NEXT: [[TMP75:%.*]] = load i32, ptr [[N_ADDR]], align 42120// CHECK3-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP75]], 202121// CHECK3-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE20:%.*]]2122// CHECK3: omp_if.then13:2123// CHECK3-NEXT: [[TMP76:%.*]] = mul nuw i32 [[TMP1]], 42124// CHECK3-NEXT: [[TMP77:%.*]] = sext i32 [[TMP76]] to i642125// CHECK3-NEXT: [[TMP78:%.*]] = mul nuw i32 5, [[TMP3]]2126// CHECK3-NEXT: [[TMP79:%.*]] = mul nuw i32 [[TMP78]], 82127// CHECK3-NEXT: [[TMP80:%.*]] = sext i32 [[TMP79]] to i642128// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.3, i32 80, i1 false)2129// CHECK3-NEXT: [[TMP81:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 02130// CHECK3-NEXT: store i32 [[TMP72]], ptr [[TMP81]], align 42131// CHECK3-NEXT: [[TMP82:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 02132// CHECK3-NEXT: store i32 [[TMP72]], ptr [[TMP82]], align 42133// CHECK3-NEXT: [[TMP83:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 02134// CHECK3-NEXT: store ptr null, ptr [[TMP83]], align 42135// CHECK3-NEXT: [[TMP84:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 12136// CHECK3-NEXT: store ptr [[B]], ptr [[TMP84]], align 42137// CHECK3-NEXT: [[TMP85:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 12138// CHECK3-NEXT: store ptr [[B]], ptr [[TMP85]], align 42139// CHECK3-NEXT: [[TMP86:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 12140// CHECK3-NEXT: store ptr null, ptr [[TMP86]], align 42141// CHECK3-NEXT: [[TMP87:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 22142// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP87]], align 42143// CHECK3-NEXT: [[TMP88:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 22144// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP88]], align 42145// CHECK3-NEXT: [[TMP89:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 22146// CHECK3-NEXT: store ptr null, ptr [[TMP89]], align 42147// CHECK3-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 32148// CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP90]], align 42149// CHECK3-NEXT: [[TMP91:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 32150// CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP91]], align 42151// CHECK3-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 32152// CHECK3-NEXT: store i64 [[TMP77]], ptr [[TMP92]], align 42153// CHECK3-NEXT: [[TMP93:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 32154// CHECK3-NEXT: store ptr null, ptr [[TMP93]], align 42155// CHECK3-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 42156// CHECK3-NEXT: store ptr [[C]], ptr [[TMP94]], align 42157// CHECK3-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 42158// CHECK3-NEXT: store ptr [[C]], ptr [[TMP95]], align 42159// CHECK3-NEXT: [[TMP96:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 42160// CHECK3-NEXT: store ptr null, ptr [[TMP96]], align 42161// CHECK3-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 52162// CHECK3-NEXT: store i32 5, ptr [[TMP97]], align 42163// CHECK3-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 52164// CHECK3-NEXT: store i32 5, ptr [[TMP98]], align 42165// CHECK3-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 52166// CHECK3-NEXT: store ptr null, ptr [[TMP99]], align 42167// CHECK3-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 62168// CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP100]], align 42169// CHECK3-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 62170// CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP101]], align 42171// CHECK3-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 62172// CHECK3-NEXT: store ptr null, ptr [[TMP102]], align 42173// CHECK3-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 72174// CHECK3-NEXT: store ptr [[VLA1]], ptr [[TMP103]], align 42175// CHECK3-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 72176// CHECK3-NEXT: store ptr [[VLA1]], ptr [[TMP104]], align 42177// CHECK3-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 72178// CHECK3-NEXT: store i64 [[TMP80]], ptr [[TMP105]], align 42179// CHECK3-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 72180// CHECK3-NEXT: store ptr null, ptr [[TMP106]], align 42181// CHECK3-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 82182// CHECK3-NEXT: store ptr [[D]], ptr [[TMP107]], align 42183// CHECK3-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 82184// CHECK3-NEXT: store ptr [[D]], ptr [[TMP108]], align 42185// CHECK3-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 82186// CHECK3-NEXT: store ptr null, ptr [[TMP109]], align 42187// CHECK3-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 92188// CHECK3-NEXT: store i32 [[TMP74]], ptr [[TMP110]], align 42189// CHECK3-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 92190// CHECK3-NEXT: store i32 [[TMP74]], ptr [[TMP111]], align 42191// CHECK3-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 92192// CHECK3-NEXT: store ptr null, ptr [[TMP112]], align 42193// CHECK3-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 02194// CHECK3-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 02195// CHECK3-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 02196// CHECK3-NEXT: [[TMP116:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 02197// CHECK3-NEXT: store i32 3, ptr [[TMP116]], align 42198// CHECK3-NEXT: [[TMP117:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 12199// CHECK3-NEXT: store i32 10, ptr [[TMP117]], align 42200// CHECK3-NEXT: [[TMP118:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 22201// CHECK3-NEXT: store ptr [[TMP113]], ptr [[TMP118]], align 42202// CHECK3-NEXT: [[TMP119:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 32203// CHECK3-NEXT: store ptr [[TMP114]], ptr [[TMP119]], align 42204// CHECK3-NEXT: [[TMP120:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 42205// CHECK3-NEXT: store ptr [[TMP115]], ptr [[TMP120]], align 42206// CHECK3-NEXT: [[TMP121:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 52207// CHECK3-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP121]], align 42208// CHECK3-NEXT: [[TMP122:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 62209// CHECK3-NEXT: store ptr null, ptr [[TMP122]], align 42210// CHECK3-NEXT: [[TMP123:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 72211// CHECK3-NEXT: store ptr null, ptr [[TMP123]], align 42212// CHECK3-NEXT: [[TMP124:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 82213// CHECK3-NEXT: store i64 0, ptr [[TMP124]], align 82214// CHECK3-NEXT: [[TMP125:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 92215// CHECK3-NEXT: store i64 0, ptr [[TMP125]], align 82216// CHECK3-NEXT: [[TMP126:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 102217// CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP126]], align 42218// CHECK3-NEXT: [[TMP127:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 112219// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP127]], align 42220// CHECK3-NEXT: [[TMP128:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 122221// CHECK3-NEXT: store i32 0, ptr [[TMP128]], align 42222// CHECK3-NEXT: [[TMP129:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.region_id, ptr [[KERNEL_ARGS17]])2223// CHECK3-NEXT: [[TMP130:%.*]] = icmp ne i32 [[TMP129]], 02224// CHECK3-NEXT: br i1 [[TMP130]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]]2225// CHECK3: omp_offload.failed18:2226// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP72]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP74]]) #[[ATTR3]]2227// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT19]]2228// CHECK3: omp_offload.cont19:2229// CHECK3-NEXT: br label [[OMP_IF_END21:%.*]]2230// CHECK3: omp_if.else20:2231// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP72]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP74]]) #[[ATTR3]]2232// CHECK3-NEXT: br label [[OMP_IF_END21]]2233// CHECK3: omp_if.end21:2234// CHECK3-NEXT: [[TMP131:%.*]] = load i32, ptr [[A]], align 42235// CHECK3-NEXT: [[TMP132:%.*]] = load ptr, ptr [[SAVED_STACK]], align 42236// CHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP132]])2237// CHECK3-NEXT: ret i32 [[TMP131]]2238//2239//2240// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l962241// CHECK3-SAME: () #[[ATTR2:[0-9]+]] {2242// CHECK3-NEXT: entry:2243// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined)2244// CHECK3-NEXT: ret void2245//2246//2247// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined2248// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] {2249// CHECK3-NEXT: entry:2250// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 42251// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 42252// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 42253// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 42254// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 42255// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 42256// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42257// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42258// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 42259// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 42260// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 42261// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 42262// CHECK3-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 42263// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 42264// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 42265// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 42266// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 42267// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)2268// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42269// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 52270// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2271// CHECK3: cond.true:2272// CHECK3-NEXT: br label [[COND_END:%.*]]2273// CHECK3: cond.false:2274// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42275// CHECK3-NEXT: br label [[COND_END]]2276// CHECK3: cond.end:2277// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]2278// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 42279// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42280// CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 42281// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]2282// CHECK3: omp.inner.for.cond:2283// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]]2284// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]]2285// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]2286// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2287// CHECK3: omp.inner.for.body:2288// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]2289// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 52290// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]2291// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]]2292// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]2293// CHECK3: omp.body.continue:2294// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]2295// CHECK3: omp.inner.for.inc:2296// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]2297// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 12298// CHECK3-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]2299// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]2300// CHECK3: omp.inner.for.end:2301// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]2302// CHECK3: omp.loop.exit:2303// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])2304// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 42305// CHECK3-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 02306// CHECK3-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]2307// CHECK3: .omp.final.then:2308// CHECK3-NEXT: store i32 33, ptr [[I]], align 42309// CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]2310// CHECK3: .omp.final.done:2311// CHECK3-NEXT: ret void2312//2313//2314// CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry.2315// CHECK3-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] {2316// CHECK3-NEXT: entry:2317// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 42318// CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 42319// CHECK3-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 42320// CHECK3-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 42321// CHECK3-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 42322// CHECK3-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 42323// CHECK3-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 82324// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i32, align 42325// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 42326// CHECK3-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 42327// CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 42328// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 42329// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 42330// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 02331// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 22332// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 02333// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 42334// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])2335// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])2336// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])2337// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]])2338// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META26:![0-9]+]]2339// CHECK3-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 4, !noalias [[META26]]2340// CHECK3-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias [[META26]]2341// CHECK3-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias [[META26]]2342// CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 4, !noalias [[META26]]2343// CHECK3-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 4, !noalias [[META26]]2344// CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias [[META26]]2345// CHECK3-NEXT: store i32 3, ptr [[KERNEL_ARGS_I]], align 4, !noalias [[META26]]2346// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 12347// CHECK3-NEXT: store i32 0, ptr [[TMP9]], align 4, !noalias [[META26]]2348// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 22349// CHECK3-NEXT: store ptr null, ptr [[TMP10]], align 4, !noalias [[META26]]2350// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 32351// CHECK3-NEXT: store ptr null, ptr [[TMP11]], align 4, !noalias [[META26]]2352// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 42353// CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 4, !noalias [[META26]]2354// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 52355// CHECK3-NEXT: store ptr null, ptr [[TMP13]], align 4, !noalias [[META26]]2356// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 62357// CHECK3-NEXT: store ptr null, ptr [[TMP14]], align 4, !noalias [[META26]]2358// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 72359// CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 4, !noalias [[META26]]2360// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 82361// CHECK3-NEXT: store i64 0, ptr [[TMP16]], align 8, !noalias [[META26]]2362// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 92363// CHECK3-NEXT: store i64 1, ptr [[TMP17]], align 8, !noalias [[META26]]2364// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 102365// CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP18]], align 4, !noalias [[META26]]2366// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 112367// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP19]], align 4, !noalias [[META26]]2368// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 122369// CHECK3-NEXT: store i32 0, ptr [[TMP20]], align 4, !noalias [[META26]]2370// CHECK3-NEXT: [[TMP21:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, ptr [[KERNEL_ARGS_I]])2371// CHECK3-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 02372// CHECK3-NEXT: br i1 [[TMP22]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]]2373// CHECK3: omp_offload.failed.i:2374// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR3]]2375// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__EXIT]]2376// CHECK3: .omp_outlined..exit:2377// CHECK3-NEXT: ret i32 02378//2379//2380// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1012381// CHECK3-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR2]] {2382// CHECK3-NEXT: entry:2383// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 42384// CHECK3-NEXT: [[K_ADDR:%.*]] = alloca ptr, align 42385// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 42386// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 42387// CHECK3-NEXT: store ptr [[K]], ptr [[K_ADDR]], align 42388// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[K_ADDR]], align 42389// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 42390// CHECK3-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 42391// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 42392// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined, i32 [[TMP2]], ptr [[TMP0]])2393// CHECK3-NEXT: ret void2394//2395//2396// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined2397// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR2]] {2398// CHECK3-NEXT: entry:2399// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 42400// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 42401// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 42402// CHECK3-NEXT: [[K_ADDR:%.*]] = alloca ptr, align 42403// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 42404// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 42405// CHECK3-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 82406// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 42407// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 42408// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42409// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42410// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 42411// CHECK3-NEXT: [[K1:%.*]] = alloca i64, align 82412// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 42413// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 42414// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 42415// CHECK3-NEXT: store ptr [[K]], ptr [[K_ADDR]], align 42416// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[K_ADDR]], align 42417// CHECK3-NEXT: [[TMP1:%.*]] = load i64, ptr [[TMP0]], align 82418// CHECK3-NEXT: store i64 [[TMP1]], ptr [[DOTLINEAR_START]], align 82419// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 42420// CHECK3-NEXT: store i32 8, ptr [[DOTOMP_UB]], align 42421// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 42422// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 42423// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 42424// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 42425// CHECK3-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP3]])2426// CHECK3-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 35, i32 0, i32 8, i32 1, i32 1)2427// CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]]2428// CHECK3: omp.dispatch.cond:2429// CHECK3-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB2]], i32 [[TMP3]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])2430// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 02431// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]2432// CHECK3: omp.dispatch.body:2433// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42434// CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 42435// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]2436// CHECK3: omp.inner.for.cond:2437// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27:![0-9]+]]2438// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP27]]2439// CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]2440// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2441// CHECK3: omp.inner.for.body:2442// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]]2443// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 12444// CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]2445// CHECK3-NEXT: store i32 [[SUB]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP27]]2446// CHECK3-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP27]]2447// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]]2448// CHECK3-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 32449// CHECK3-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i642450// CHECK3-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]]2451// CHECK3-NEXT: store i64 [[ADD]], ptr [[K1]], align 8, !llvm.access.group [[ACC_GRP27]]2452// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP27]]2453// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 12454// CHECK3-NEXT: store i32 [[ADD3]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP27]]2455// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]2456// CHECK3: omp.body.continue:2457// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]2458// CHECK3: omp.inner.for.inc:2459// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]]2460// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 12461// CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]]2462// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]2463// CHECK3: omp.inner.for.end:2464// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]2465// CHECK3: omp.dispatch.inc:2466// CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]2467// CHECK3: omp.dispatch.end:2468// CHECK3-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB2]], i32 [[TMP3]])2469// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 42470// CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 02471// CHECK3-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]2472// CHECK3: .omp.final.then:2473// CHECK3-NEXT: store i32 1, ptr [[I]], align 42474// CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]2475// CHECK3: .omp.final.done:2476// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 42477// CHECK3-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 02478// CHECK3-NEXT: br i1 [[TMP16]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]2479// CHECK3: .omp.linear.pu:2480// CHECK3-NEXT: [[TMP17:%.*]] = load i64, ptr [[K1]], align 82481// CHECK3-NEXT: store i64 [[TMP17]], ptr [[TMP0]], align 82482// CHECK3-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]2483// CHECK3: .omp.linear.pu.done:2484// CHECK3-NEXT: ret void2485//2486//2487// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1082488// CHECK3-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] {2489// CHECK3-NEXT: entry:2490// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 42491// CHECK3-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 42492// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 42493// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 42494// CHECK3-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 42495// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 42496// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 42497// CHECK3-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 42498// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 42499// CHECK3-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 22500// CHECK3-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 22501// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 42502// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 42503// CHECK3-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 42504// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[LIN_CASTED]], align 42505// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 42506// CHECK3-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 42507// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[A_CASTED]], align 42508// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined, i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])2509// CHECK3-NEXT: ret void2510//2511//2512// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined2513// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] {2514// CHECK3-NEXT: entry:2515// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 42516// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 42517// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 42518// CHECK3-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 42519// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 42520// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 82521// CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 42522// CHECK3-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 42523// CHECK3-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 42524// CHECK3-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 82525// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 82526// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 82527// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 82528// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42529// CHECK3-NEXT: [[IT:%.*]] = alloca i64, align 82530// CHECK3-NEXT: [[LIN2:%.*]] = alloca i32, align 42531// CHECK3-NEXT: [[A3:%.*]] = alloca i32, align 42532// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 42533// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 42534// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 42535// CHECK3-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 42536// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 42537// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 42538// CHECK3-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 42539// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 42540// CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 42541// CHECK3-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()2542// CHECK3-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 82543// CHECK3-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 82544// CHECK3-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 82545// CHECK3-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 82546// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 42547// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 42548// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 42549// CHECK3-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP3]])2550// CHECK3-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)2551// CHECK3-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 82552// CHECK3-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 32553// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2554// CHECK3: cond.true:2555// CHECK3-NEXT: br label [[COND_END:%.*]]2556// CHECK3: cond.false:2557// CHECK3-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 82558// CHECK3-NEXT: br label [[COND_END]]2559// CHECK3: cond.end:2560// CHECK3-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]2561// CHECK3-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 82562// CHECK3-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 82563// CHECK3-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 82564// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]2565// CHECK3: omp.inner.for.cond:2566// CHECK3-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30:![0-9]+]]2567// CHECK3-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP30]]2568// CHECK3-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]2569// CHECK3-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2570// CHECK3: omp.inner.for.body:2571// CHECK3-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]]2572// CHECK3-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 4002573// CHECK3-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]2574// CHECK3-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP30]]2575// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP30]]2576// CHECK3-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i642577// CHECK3-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]]2578// CHECK3-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP30]]2579// CHECK3-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]]2580// CHECK3-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]]2581// CHECK3-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i322582// CHECK3-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 4, !llvm.access.group [[ACC_GRP30]]2583// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4, !llvm.access.group [[ACC_GRP30]]2584// CHECK3-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i642585// CHECK3-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]]2586// CHECK3-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP30]]2587// CHECK3-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]]2588// CHECK3-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]]2589// CHECK3-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i322590// CHECK3-NEXT: store i32 [[CONV10]], ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP30]]2591// CHECK3-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP30]]2592// CHECK3-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i322593// CHECK3-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 12594// CHECK3-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i162595// CHECK3-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP30]]2596// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]2597// CHECK3: omp.body.continue:2598// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]2599// CHECK3: omp.inner.for.inc:2600// CHECK3-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]]2601// CHECK3-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 12602// CHECK3-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]]2603// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]2604// CHECK3: omp.inner.for.end:2605// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]2606// CHECK3: omp.loop.exit:2607// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]])2608// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 42609// CHECK3-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 02610// CHECK3-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]2611// CHECK3: .omp.final.then:2612// CHECK3-NEXT: store i64 400, ptr [[IT]], align 82613// CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]2614// CHECK3: .omp.final.done:2615// CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 42616// CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 02617// CHECK3-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]2618// CHECK3: .omp.linear.pu:2619// CHECK3-NEXT: [[TMP22:%.*]] = load i32, ptr [[LIN2]], align 42620// CHECK3-NEXT: store i32 [[TMP22]], ptr [[LIN_ADDR]], align 42621// CHECK3-NEXT: [[TMP23:%.*]] = load i32, ptr [[A3]], align 42622// CHECK3-NEXT: store i32 [[TMP23]], ptr [[A_ADDR]], align 42623// CHECK3-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]2624// CHECK3: .omp.linear.pu.done:2625// CHECK3-NEXT: ret void2626//2627//2628// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1162629// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {2630// CHECK3-NEXT: entry:2631// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 42632// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 42633// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 42634// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 42635// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 42636// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 42637// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 42638// CHECK3-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 42639// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 42640// CHECK3-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 22641// CHECK3-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 22642// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 42643// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined, i32 [[TMP1]], i32 [[TMP3]])2644// CHECK3-NEXT: ret void2645//2646//2647// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined2648// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {2649// CHECK3-NEXT: entry:2650// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 42651// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 42652// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 42653// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 42654// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 42655// CHECK3-NEXT: [[TMP:%.*]] = alloca i16, align 22656// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 42657// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 42658// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42659// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42660// CHECK3-NEXT: [[IT:%.*]] = alloca i16, align 22661// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 42662// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 42663// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 42664// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 42665// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 42666// CHECK3-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 42667// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 42668// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 42669// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 42670// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 42671// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)2672// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42673// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 32674// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2675// CHECK3: cond.true:2676// CHECK3-NEXT: br label [[COND_END:%.*]]2677// CHECK3: cond.false:2678// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42679// CHECK3-NEXT: br label [[COND_END]]2680// CHECK3: cond.end:2681// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]2682// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 42683// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42684// CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 42685// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]2686// CHECK3: omp.inner.for.cond:2687// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33:![0-9]+]]2688// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP33]]2689// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]2690// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2691// CHECK3: omp.inner.for.body:2692// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]]2693// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 42694// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]2695// CHECK3-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i162696// CHECK3-NEXT: store i16 [[CONV]], ptr [[IT]], align 2, !llvm.access.group [[ACC_GRP33]]2697// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]]2698// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 12699// CHECK3-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]]2700// CHECK3-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP33]]2701// CHECK3-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i322702// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 12703// CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i162704// CHECK3-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP33]]2705// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]2706// CHECK3: omp.body.continue:2707// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]2708// CHECK3: omp.inner.for.inc:2709// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]]2710// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 12711// CHECK3-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]]2712// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]2713// CHECK3: omp.inner.for.end:2714// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]2715// CHECK3: omp.loop.exit:2716// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])2717// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 42718// CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 02719// CHECK3-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]2720// CHECK3: .omp.final.then:2721// CHECK3-NEXT: store i16 22, ptr [[IT]], align 22722// CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]2723// CHECK3: .omp.final.done:2724// CHECK3-NEXT: ret void2725//2726//2727// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1402728// CHECK3-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {2729// CHECK3-NEXT: entry:2730// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 42731// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 42732// CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 42733// CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 42734// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 42735// CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 42736// CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 42737// CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 42738// CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 42739// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 42740// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 42741// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 42742// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 42743// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 42744// CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 42745// CHECK3-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 42746// CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 42747// CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 42748// CHECK3-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 42749// CHECK3-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 42750// CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 42751// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 42752// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 42753// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 42754// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 42755// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 42756// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 42757// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 42758// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 42759// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 42760// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 42761// CHECK3-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 42762// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 42763// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 42764// CHECK3-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 42765// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 42766// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i32 [[TMP11]])2767// CHECK3-NEXT: ret void2768//2769//2770// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined2771// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {2772// CHECK3-NEXT: entry:2773// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 42774// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 42775// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 42776// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 42777// CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 42778// CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 42779// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 42780// CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 42781// CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 42782// CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 42783// CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 42784// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 42785// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 42786// CHECK3-NEXT: [[TMP:%.*]] = alloca i8, align 12787// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 42788// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 42789// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42790// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42791// CHECK3-NEXT: [[IT:%.*]] = alloca i8, align 12792// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 42793// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 42794// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 42795// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 42796// CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 42797// CHECK3-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 42798// CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 42799// CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 42800// CHECK3-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 42801// CHECK3-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 42802// CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 42803// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 42804// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 42805// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 42806// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 42807// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 42808// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 42809// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 42810// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 42811// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 42812// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 42813// CHECK3-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 42814// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 42815// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 42816// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 42817// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 42818// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 42819// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])2820// CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]]2821// CHECK3: omp.dispatch.cond:2822// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42823// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 252824// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2825// CHECK3: cond.true:2826// CHECK3-NEXT: br label [[COND_END:%.*]]2827// CHECK3: cond.false:2828// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42829// CHECK3-NEXT: br label [[COND_END]]2830// CHECK3: cond.end:2831// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]2832// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 42833// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42834// CHECK3-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 42835// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42836// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42837// CHECK3-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]2838// CHECK3-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]2839// CHECK3: omp.dispatch.body:2840// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]2841// CHECK3: omp.inner.for.cond:2842// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36:![0-9]+]]2843// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP36]]2844// CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]2845// CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2846// CHECK3: omp.inner.for.body:2847// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]]2848// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 12849// CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]2850// CHECK3-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i82851// CHECK3-NEXT: store i8 [[CONV]], ptr [[IT]], align 1, !llvm.access.group [[ACC_GRP36]]2852// CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]]2853// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 12854// CHECK3-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]]2855// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 22856// CHECK3-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP36]]2857// CHECK3-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double2858// CHECK3-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+002859// CHECK3-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float2860// CHECK3-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP36]]2861// CHECK3-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 32862// CHECK3-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP36]]2863// CHECK3-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double2864// CHECK3-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+002865// CHECK3-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float2866// CHECK3-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP36]]2867// CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 12868// CHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i32 0, i32 22869// CHECK3-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP36]]2870// CHECK3-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+002871// CHECK3-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP36]]2872// CHECK3-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]2873// CHECK3-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP23]]2874// CHECK3-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i32 32875// CHECK3-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP36]]2876// CHECK3-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+002877// CHECK3-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP36]]2878// CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 02879// CHECK3-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP36]]2880// CHECK3-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 12881// CHECK3-NEXT: store i64 [[ADD20]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP36]]2882// CHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 12883// CHECK3-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP36]]2884// CHECK3-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i322885// CHECK3-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 12886// CHECK3-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i82887// CHECK3-NEXT: store i8 [[CONV23]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP36]]2888// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]2889// CHECK3: omp.body.continue:2890// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]2891// CHECK3: omp.inner.for.inc:2892// CHECK3-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]]2893// CHECK3-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 12894// CHECK3-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]]2895// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]]2896// CHECK3: omp.inner.for.end:2897// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]2898// CHECK3: omp.dispatch.inc:2899// CHECK3-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42900// CHECK3-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 42901// CHECK3-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]2902// CHECK3-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 42903// CHECK3-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42904// CHECK3-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 42905// CHECK3-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]2906// CHECK3-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 42907// CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]2908// CHECK3: omp.dispatch.end:2909// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]])2910// CHECK3-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 42911// CHECK3-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 02912// CHECK3-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]2913// CHECK3: .omp.final.then:2914// CHECK3-NEXT: store i8 96, ptr [[IT]], align 12915// CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]2916// CHECK3: .omp.final.done:2917// CHECK3-NEXT: ret void2918//2919//2920// CHECK3-LABEL: define {{[^@]+}}@_Z3bari2921// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {2922// CHECK3-NEXT: entry:2923// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 42924// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 42925// CHECK3-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 42926// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 42927// CHECK3-NEXT: store i32 0, ptr [[A]], align 42928// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 42929// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]])2930// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 42931// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]2932// CHECK3-NEXT: store i32 [[ADD]], ptr [[A]], align 42933// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 42934// CHECK3-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]])2935// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 42936// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]2937// CHECK3-NEXT: store i32 [[ADD2]], ptr [[A]], align 42938// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 42939// CHECK3-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]])2940// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 42941// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]2942// CHECK3-NEXT: store i32 [[ADD4]], ptr [[A]], align 42943// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 42944// CHECK3-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]])2945// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 42946// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]2947// CHECK3-NEXT: store i32 [[ADD6]], ptr [[A]], align 42948// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 42949// CHECK3-NEXT: ret i32 [[TMP8]]2950//2951//2952// CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei2953// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {2954// CHECK3-NEXT: entry:2955// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42956// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 42957// CHECK3-NEXT: [[B:%.*]] = alloca i32, align 42958// CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 42959// CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 42960// CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 42961// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 42962// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 42963// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 42964// CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 42965// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 82966// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42967// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 42968// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42969// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 42970// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 12971// CHECK3-NEXT: store i32 [[ADD]], ptr [[B]], align 42972// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 42973// CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()2974// CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 42975// CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]2976// CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 22977// CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 42978// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 42979// CHECK3-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 42980// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 42981// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 42982// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 602983// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]2984// CHECK3: omp_if.then:2985// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 02986// CHECK3-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]]2987// CHECK3-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 22988// CHECK3-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i642989// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.5, i32 40, i1 false)2990// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 02991// CHECK3-NEXT: store ptr [[THIS1]], ptr [[TMP10]], align 42992// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 02993// CHECK3-NEXT: store ptr [[A]], ptr [[TMP11]], align 42994// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 02995// CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 42996// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 12997// CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP13]], align 42998// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 12999// CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP14]], align 43000// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 13001// CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 43002// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 23003// CHECK3-NEXT: store i32 2, ptr [[TMP16]], align 43004// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 23005// CHECK3-NEXT: store i32 2, ptr [[TMP17]], align 43006// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 23007// CHECK3-NEXT: store ptr null, ptr [[TMP18]], align 43008// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 33009// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP19]], align 43010// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 33011// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP20]], align 43012// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 33013// CHECK3-NEXT: store ptr null, ptr [[TMP21]], align 43014// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 43015// CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP22]], align 43016// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 43017// CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP23]], align 43018// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 43019// CHECK3-NEXT: store i64 [[TMP9]], ptr [[TMP24]], align 43020// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 43021// CHECK3-NEXT: store ptr null, ptr [[TMP25]], align 43022// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 03023// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 03024// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 03025// CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 03026// CHECK3-NEXT: store i32 3, ptr [[TMP29]], align 43027// CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 13028// CHECK3-NEXT: store i32 5, ptr [[TMP30]], align 43029// CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 23030// CHECK3-NEXT: store ptr [[TMP26]], ptr [[TMP31]], align 43031// CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 33032// CHECK3-NEXT: store ptr [[TMP27]], ptr [[TMP32]], align 43033// CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 43034// CHECK3-NEXT: store ptr [[TMP28]], ptr [[TMP33]], align 43035// CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 53036// CHECK3-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP34]], align 43037// CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 63038// CHECK3-NEXT: store ptr null, ptr [[TMP35]], align 43039// CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 73040// CHECK3-NEXT: store ptr null, ptr [[TMP36]], align 43041// CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 83042// CHECK3-NEXT: store i64 0, ptr [[TMP37]], align 83043// CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 93044// CHECK3-NEXT: store i64 0, ptr [[TMP38]], align 83045// CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 103046// CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP39]], align 43047// CHECK3-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 113048// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP40]], align 43049// CHECK3-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 123050// CHECK3-NEXT: store i32 0, ptr [[TMP41]], align 43051// CHECK3-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, ptr [[KERNEL_ARGS]])3052// CHECK3-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 03053// CHECK3-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]3054// CHECK3: omp_offload.failed:3055// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3]]3056// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]3057// CHECK3: omp_offload.cont:3058// CHECK3-NEXT: br label [[OMP_IF_END:%.*]]3059// CHECK3: omp_if.else:3060// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3]]3061// CHECK3-NEXT: br label [[OMP_IF_END]]3062// CHECK3: omp_if.end:3063// CHECK3-NEXT: [[TMP44:%.*]] = mul nsw i32 1, [[TMP1]]3064// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP44]]3065// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 13066// CHECK3-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 23067// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i323068// CHECK3-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 43069// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]]3070// CHECK3-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 43071// CHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP47]])3072// CHECK3-NEXT: ret i32 [[ADD3]]3073//3074//3075// CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici3076// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {3077// CHECK3-NEXT: entry:3078// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 43079// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 43080// CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 23081// CHECK3-NEXT: [[AAA:%.*]] = alloca i8, align 13082// CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 43083// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 43084// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 43085// CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 43086// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 43087// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 43088// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 43089// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 83090// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 43091// CHECK3-NEXT: store i32 0, ptr [[A]], align 43092// CHECK3-NEXT: store i16 0, ptr [[AA]], align 23093// CHECK3-NEXT: store i8 0, ptr [[AAA]], align 13094// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 43095// CHECK3-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 43096// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 43097// CHECK3-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 23098// CHECK3-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 23099// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 43100// CHECK3-NEXT: [[TMP4:%.*]] = load i8, ptr [[AAA]], align 13101// CHECK3-NEXT: store i8 [[TMP4]], ptr [[AAA_CASTED]], align 13102// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[AAA_CASTED]], align 43103// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 43104// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 503105// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]3106// CHECK3: omp_if.then:3107// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 03108// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP7]], align 43109// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 03110// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP8]], align 43111// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 03112// CHECK3-NEXT: store ptr null, ptr [[TMP9]], align 43113// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 13114// CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP10]], align 43115// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 13116// CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP11]], align 43117// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 13118// CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 43119// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 23120// CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP13]], align 43121// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 23122// CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP14]], align 43123// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 23124// CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 43125// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 33126// CHECK3-NEXT: store ptr [[B]], ptr [[TMP16]], align 43127// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 33128// CHECK3-NEXT: store ptr [[B]], ptr [[TMP17]], align 43129// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 33130// CHECK3-NEXT: store ptr null, ptr [[TMP18]], align 43131// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 03132// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 03133// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 03134// CHECK3-NEXT: store i32 3, ptr [[TMP21]], align 43135// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 13136// CHECK3-NEXT: store i32 4, ptr [[TMP22]], align 43137// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 23138// CHECK3-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 43139// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 33140// CHECK3-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 43141// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 43142// CHECK3-NEXT: store ptr @.offload_sizes.7, ptr [[TMP25]], align 43143// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 53144// CHECK3-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP26]], align 43145// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 63146// CHECK3-NEXT: store ptr null, ptr [[TMP27]], align 43147// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 73148// CHECK3-NEXT: store ptr null, ptr [[TMP28]], align 43149// CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 83150// CHECK3-NEXT: store i64 0, ptr [[TMP29]], align 83151// CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 93152// CHECK3-NEXT: store i64 0, ptr [[TMP30]], align 83153// CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 103154// CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP31]], align 43155// CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 113156// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP32]], align 43157// CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 123158// CHECK3-NEXT: store i32 0, ptr [[TMP33]], align 43159// CHECK3-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.region_id, ptr [[KERNEL_ARGS]])3160// CHECK3-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 03161// CHECK3-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]3162// CHECK3: omp_offload.failed:3163// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR3]]3164// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]3165// CHECK3: omp_offload.cont:3166// CHECK3-NEXT: br label [[OMP_IF_END:%.*]]3167// CHECK3: omp_if.else:3168// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR3]]3169// CHECK3-NEXT: br label [[OMP_IF_END]]3170// CHECK3: omp_if.end:3171// CHECK3-NEXT: [[TMP36:%.*]] = load i32, ptr [[A]], align 43172// CHECK3-NEXT: ret i32 [[TMP36]]3173//3174//3175// CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i3176// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {3177// CHECK3-NEXT: entry:3178// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 43179// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 43180// CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 23181// CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 43182// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 43183// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 43184// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 43185// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 43186// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 43187// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 83188// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 43189// CHECK3-NEXT: store i32 0, ptr [[A]], align 43190// CHECK3-NEXT: store i16 0, ptr [[AA]], align 23191// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 43192// CHECK3-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 43193// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 43194// CHECK3-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 23195// CHECK3-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 23196// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 43197// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 43198// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 403199// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]3200// CHECK3: omp_if.then:3201// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 03202// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP5]], align 43203// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 03204// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP6]], align 43205// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 03206// CHECK3-NEXT: store ptr null, ptr [[TMP7]], align 43207// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 13208// CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP8]], align 43209// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 13210// CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP9]], align 43211// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 13212// CHECK3-NEXT: store ptr null, ptr [[TMP10]], align 43213// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 23214// CHECK3-NEXT: store ptr [[B]], ptr [[TMP11]], align 43215// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 23216// CHECK3-NEXT: store ptr [[B]], ptr [[TMP12]], align 43217// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 23218// CHECK3-NEXT: store ptr null, ptr [[TMP13]], align 43219// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 03220// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 03221// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 03222// CHECK3-NEXT: store i32 3, ptr [[TMP16]], align 43223// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 13224// CHECK3-NEXT: store i32 3, ptr [[TMP17]], align 43225// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 23226// CHECK3-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 43227// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 33228// CHECK3-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 43229// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 43230// CHECK3-NEXT: store ptr @.offload_sizes.9, ptr [[TMP20]], align 43231// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 53232// CHECK3-NEXT: store ptr @.offload_maptypes.10, ptr [[TMP21]], align 43233// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 63234// CHECK3-NEXT: store ptr null, ptr [[TMP22]], align 43235// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 73236// CHECK3-NEXT: store ptr null, ptr [[TMP23]], align 43237// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 83238// CHECK3-NEXT: store i64 0, ptr [[TMP24]], align 83239// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 93240// CHECK3-NEXT: store i64 0, ptr [[TMP25]], align 83241// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 103242// CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP26]], align 43243// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 113244// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP27]], align 43245// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 123246// CHECK3-NEXT: store i32 0, ptr [[TMP28]], align 43247// CHECK3-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.region_id, ptr [[KERNEL_ARGS]])3248// CHECK3-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 03249// CHECK3-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]3250// CHECK3: omp_offload.failed:3251// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]]3252// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]3253// CHECK3: omp_offload.cont:3254// CHECK3-NEXT: br label [[OMP_IF_END:%.*]]3255// CHECK3: omp_if.else:3256// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]]3257// CHECK3-NEXT: br label [[OMP_IF_END]]3258// CHECK3: omp_if.end:3259// CHECK3-NEXT: [[TMP31:%.*]] = load i32, ptr [[A]], align 43260// CHECK3-NEXT: ret i32 [[TMP31]]3261//3262//3263// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l2163264// CHECK3-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {3265// CHECK3-NEXT: entry:3266// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 43267// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 43268// CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 43269// CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 43270// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 43271// CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 43272// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 43273// CHECK3-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 43274// CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 43275// CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 43276// CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 43277// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 43278// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 43279// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 43280// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 43281// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 43282// CHECK3-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 43283// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 43284// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]])3285// CHECK3-NEXT: ret void3286//3287//3288// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined3289// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {3290// CHECK3-NEXT: entry:3291// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 43292// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 43293// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 43294// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 43295// CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 43296// CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 43297// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 43298// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 83299// CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 43300// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 83301// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 83302// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 83303// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 43304// CHECK3-NEXT: [[IT:%.*]] = alloca i64, align 83305// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 43306// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 43307// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 43308// CHECK3-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 43309// CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 43310// CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 43311// CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 43312// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 43313// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 43314// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 43315// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 43316// CHECK3-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 83317// CHECK3-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 83318// CHECK3-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 83319// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 43320// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 43321// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 43322// CHECK3-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)3323// CHECK3-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_UB]], align 83324// CHECK3-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 33325// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]3326// CHECK3: cond.true:3327// CHECK3-NEXT: br label [[COND_END:%.*]]3328// CHECK3: cond.false:3329// CHECK3-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 83330// CHECK3-NEXT: br label [[COND_END]]3331// CHECK3: cond.end:3332// CHECK3-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]3333// CHECK3-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 83334// CHECK3-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_LB]], align 83335// CHECK3-NEXT: store i64 [[TMP8]], ptr [[DOTOMP_IV]], align 83336// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]3337// CHECK3: omp.inner.for.cond:3338// CHECK3-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39:![0-9]+]]3339// CHECK3-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP39]]3340// CHECK3-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]3341// CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]3342// CHECK3: omp.inner.for.body:3343// CHECK3-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39]]3344// CHECK3-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 4003345// CHECK3-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]3346// CHECK3-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP39]]3347// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP39]]3348// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double3349// CHECK3-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+003350// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 03351// CHECK3-NEXT: store double [[ADD]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP39]]3352// CHECK3-NEXT: [[A4:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 03353// CHECK3-NEXT: [[TMP13:%.*]] = load double, ptr [[A4]], align 4, !llvm.access.group [[ACC_GRP39]]3354// CHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+003355// CHECK3-NEXT: store double [[INC]], ptr [[A4]], align 4, !llvm.access.group [[ACC_GRP39]]3356// CHECK3-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i163357// CHECK3-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]3358// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP14]]3359// CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 13360// CHECK3-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP39]]3361// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]3362// CHECK3: omp.body.continue:3363// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]3364// CHECK3: omp.inner.for.inc:3365// CHECK3-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39]]3366// CHECK3-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 13367// CHECK3-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39]]3368// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]]3369// CHECK3: omp.inner.for.end:3370// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]3371// CHECK3: omp.loop.exit:3372// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])3373// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 43374// CHECK3-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 03375// CHECK3-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]3376// CHECK3: .omp.final.then:3377// CHECK3-NEXT: store i64 400, ptr [[IT]], align 83378// CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]3379// CHECK3: .omp.final.done:3380// CHECK3-NEXT: ret void3381//3382//3383// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l1953384// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {3385// CHECK3-NEXT: entry:3386// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 43387// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 43388// CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 43389// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 43390// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 43391// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 43392// CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 43393// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 43394// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 43395// CHECK3-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 43396// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 43397// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 43398// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 43399// CHECK3-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 43400// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 43401// CHECK3-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 23402// CHECK3-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 23403// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 43404// CHECK3-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 13405// CHECK3-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 13406// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[AAA_CASTED]], align 43407// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], ptr [[TMP0]])3408// CHECK3-NEXT: ret void3409//3410//3411// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined3412// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {3413// CHECK3-NEXT: entry:3414// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 43415// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 43416// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 43417// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 43418// CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 43419// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 43420// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 43421// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 43422// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 43423// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 43424// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 43425// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 43426// CHECK3-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 43427// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 43428// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 43429// CHECK3-NEXT: ret void3430//3431//3432// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l1783433// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {3434// CHECK3-NEXT: entry:3435// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 43436// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 43437// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 43438// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 43439// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 43440// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 43441// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 43442// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 43443// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 43444// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 43445// CHECK3-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 43446// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 43447// CHECK3-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 23448// CHECK3-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 23449// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 43450// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]])3451// CHECK3-NEXT: ret void3452//3453//3454// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined3455// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {3456// CHECK3-NEXT: entry:3457// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 43458// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 43459// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 43460// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 43461// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 43462// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 83463// CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 43464// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 83465// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 83466// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 83467// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 43468// CHECK3-NEXT: [[I:%.*]] = alloca i64, align 83469// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 43470// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 43471// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 43472// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 43473// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 43474// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 43475// CHECK3-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 83476// CHECK3-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 83477// CHECK3-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 83478// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 43479// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 43480// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 43481// CHECK3-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)3482// CHECK3-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 83483// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 63484// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]3485// CHECK3: cond.true:3486// CHECK3-NEXT: br label [[COND_END:%.*]]3487// CHECK3: cond.false:3488// CHECK3-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 83489// CHECK3-NEXT: br label [[COND_END]]3490// CHECK3: cond.end:3491// CHECK3-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]3492// CHECK3-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 83493// CHECK3-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 83494// CHECK3-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 83495// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]3496// CHECK3: omp.inner.for.cond:3497// CHECK3-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP42:![0-9]+]]3498// CHECK3-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP42]]3499// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]3500// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]3501// CHECK3: omp.inner.for.body:3502// CHECK3-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP42]]3503// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 33504// CHECK3-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]3505// CHECK3-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP42]]3506// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP42]]3507// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 13508// CHECK3-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP42]]3509// CHECK3-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP42]]3510// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i323511// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 13512// CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i163513// CHECK3-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP42]]3514// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 23515// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP42]]3516// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 13517// CHECK3-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP42]]3518// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]3519// CHECK3: omp.body.continue:3520// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]3521// CHECK3: omp.inner.for.inc:3522// CHECK3-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP42]]3523// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 13524// CHECK3-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP42]]3525// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]]3526// CHECK3: omp.inner.for.end:3527// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]3528// CHECK3: omp.loop.exit:3529// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])3530// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 43531// CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 03532// CHECK3-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]3533// CHECK3: .omp.final.then:3534// CHECK3-NEXT: store i64 11, ptr [[I]], align 83535// CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]3536// CHECK3: .omp.final.done:3537// CHECK3-NEXT: ret void3538//3539//3540// CHECK5-LABEL: define {{[^@]+}}@_Z7get_valv3541// CHECK5-SAME: () #[[ATTR0:[0-9]+]] {3542// CHECK5-NEXT: entry:3543// CHECK5-NEXT: ret i64 03544//3545//3546// CHECK5-LABEL: define {{[^@]+}}@_Z3fooi3547// CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {3548// CHECK5-NEXT: entry:3549// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 43550// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 43551// CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 23552// CHECK5-NEXT: [[B:%.*]] = alloca [10 x float], align 43553// CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 83554// CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 83555// CHECK5-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 83556// CHECK5-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 83557// CHECK5-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 83558// CHECK5-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 13559// CHECK5-NEXT: [[K:%.*]] = alloca i64, align 83560// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 83561// CHECK5-NEXT: [[K_CASTED:%.*]] = alloca i64, align 83562// CHECK5-NEXT: [[LIN:%.*]] = alloca i32, align 43563// CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 83564// CHECK5-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 83565// CHECK5-NEXT: [[A_CASTED2:%.*]] = alloca i64, align 83566// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 83567// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 83568// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 83569// CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 83570// CHECK5-NEXT: [[A_CASTED3:%.*]] = alloca i64, align 83571// CHECK5-NEXT: [[AA_CASTED4:%.*]] = alloca i64, align 83572// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x ptr], align 83573// CHECK5-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x ptr], align 83574// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x ptr], align 83575// CHECK5-NEXT: [[KERNEL_ARGS8:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 83576// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 43577// CHECK5-NEXT: [[A_CASTED11:%.*]] = alloca i64, align 83578// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 83579// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x ptr], align 83580// CHECK5-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x ptr], align 83581// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x ptr], align 83582// CHECK5-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 83583// CHECK5-NEXT: [[KERNEL_ARGS17:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 83584// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])3585// CHECK5-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 43586// CHECK5-NEXT: store i32 0, ptr [[A]], align 43587// CHECK5-NEXT: store i16 0, ptr [[AA]], align 23588// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 43589// CHECK5-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i643590// CHECK5-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()3591// CHECK5-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 83592// CHECK5-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 43593// CHECK5-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 83594// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 43595// CHECK5-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i643596// CHECK5-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]3597// CHECK5-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 83598// CHECK5-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 83599// CHECK5-NEXT: [[TMP7:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i64 40, i64 1, ptr @.omp_task_entry., i64 -1)3600// CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP7]], i32 0, i32 03601// CHECK5-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB2]], i32 [[TMP0]], ptr [[TMP7]])3602// CHECK5-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()3603// CHECK5-NEXT: store i64 [[CALL]], ptr [[K]], align 83604// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 43605// CHECK5-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 43606// CHECK5-NEXT: [[TMP11:%.*]] = load i64, ptr [[A_CASTED]], align 83607// CHECK5-NEXT: [[TMP12:%.*]] = load i64, ptr [[K]], align 83608// CHECK5-NEXT: store i64 [[TMP12]], ptr [[K_CASTED]], align 83609// CHECK5-NEXT: [[TMP13:%.*]] = load i64, ptr [[K_CASTED]], align 83610// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP11]], i64 [[TMP13]]) #[[ATTR3:[0-9]+]]3611// CHECK5-NEXT: store i32 12, ptr [[LIN]], align 43612// CHECK5-NEXT: [[TMP14:%.*]] = load i16, ptr [[AA]], align 23613// CHECK5-NEXT: store i16 [[TMP14]], ptr [[AA_CASTED]], align 23614// CHECK5-NEXT: [[TMP15:%.*]] = load i64, ptr [[AA_CASTED]], align 83615// CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[LIN]], align 43616// CHECK5-NEXT: store i32 [[TMP16]], ptr [[LIN_CASTED]], align 43617// CHECK5-NEXT: [[TMP17:%.*]] = load i64, ptr [[LIN_CASTED]], align 83618// CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[A]], align 43619// CHECK5-NEXT: store i32 [[TMP18]], ptr [[A_CASTED2]], align 43620// CHECK5-NEXT: [[TMP19:%.*]] = load i64, ptr [[A_CASTED2]], align 83621// CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 03622// CHECK5-NEXT: store i64 [[TMP15]], ptr [[TMP20]], align 83623// CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 03624// CHECK5-NEXT: store i64 [[TMP15]], ptr [[TMP21]], align 83625// CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 03626// CHECK5-NEXT: store ptr null, ptr [[TMP22]], align 83627// CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 13628// CHECK5-NEXT: store i64 [[TMP17]], ptr [[TMP23]], align 83629// CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 13630// CHECK5-NEXT: store i64 [[TMP17]], ptr [[TMP24]], align 83631// CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 13632// CHECK5-NEXT: store ptr null, ptr [[TMP25]], align 83633// CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 23634// CHECK5-NEXT: store i64 [[TMP19]], ptr [[TMP26]], align 83635// CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 23636// CHECK5-NEXT: store i64 [[TMP19]], ptr [[TMP27]], align 83637// CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 23638// CHECK5-NEXT: store ptr null, ptr [[TMP28]], align 83639// CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 03640// CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 03641// CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 03642// CHECK5-NEXT: store i32 3, ptr [[TMP31]], align 43643// CHECK5-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 13644// CHECK5-NEXT: store i32 3, ptr [[TMP32]], align 43645// CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 23646// CHECK5-NEXT: store ptr [[TMP29]], ptr [[TMP33]], align 83647// CHECK5-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 33648// CHECK5-NEXT: store ptr [[TMP30]], ptr [[TMP34]], align 83649// CHECK5-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 43650// CHECK5-NEXT: store ptr @.offload_sizes, ptr [[TMP35]], align 83651// CHECK5-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 53652// CHECK5-NEXT: store ptr @.offload_maptypes, ptr [[TMP36]], align 83653// CHECK5-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 63654// CHECK5-NEXT: store ptr null, ptr [[TMP37]], align 83655// CHECK5-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 73656// CHECK5-NEXT: store ptr null, ptr [[TMP38]], align 83657// CHECK5-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 83658// CHECK5-NEXT: store i64 0, ptr [[TMP39]], align 83659// CHECK5-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 93660// CHECK5-NEXT: store i64 0, ptr [[TMP40]], align 83661// CHECK5-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 103662// CHECK5-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP41]], align 43663// CHECK5-NEXT: [[TMP42:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 113664// CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP42]], align 43665// CHECK5-NEXT: [[TMP43:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 123666// CHECK5-NEXT: store i32 0, ptr [[TMP43]], align 43667// CHECK5-NEXT: [[TMP44:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.region_id, ptr [[KERNEL_ARGS]])3668// CHECK5-NEXT: [[TMP45:%.*]] = icmp ne i32 [[TMP44]], 03669// CHECK5-NEXT: br i1 [[TMP45]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]3670// CHECK5: omp_offload.failed:3671// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]]) #[[ATTR3]]3672// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]]3673// CHECK5: omp_offload.cont:3674// CHECK5-NEXT: [[TMP46:%.*]] = load i32, ptr [[A]], align 43675// CHECK5-NEXT: store i32 [[TMP46]], ptr [[A_CASTED3]], align 43676// CHECK5-NEXT: [[TMP47:%.*]] = load i64, ptr [[A_CASTED3]], align 83677// CHECK5-NEXT: [[TMP48:%.*]] = load i16, ptr [[AA]], align 23678// CHECK5-NEXT: store i16 [[TMP48]], ptr [[AA_CASTED4]], align 23679// CHECK5-NEXT: [[TMP49:%.*]] = load i64, ptr [[AA_CASTED4]], align 83680// CHECK5-NEXT: [[TMP50:%.*]] = load i32, ptr [[N_ADDR]], align 43681// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP50]], 103682// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]3683// CHECK5: omp_if.then:3684// CHECK5-NEXT: [[TMP51:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 03685// CHECK5-NEXT: store i64 [[TMP47]], ptr [[TMP51]], align 83686// CHECK5-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 03687// CHECK5-NEXT: store i64 [[TMP47]], ptr [[TMP52]], align 83688// CHECK5-NEXT: [[TMP53:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 03689// CHECK5-NEXT: store ptr null, ptr [[TMP53]], align 83690// CHECK5-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 13691// CHECK5-NEXT: store i64 [[TMP49]], ptr [[TMP54]], align 83692// CHECK5-NEXT: [[TMP55:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 13693// CHECK5-NEXT: store i64 [[TMP49]], ptr [[TMP55]], align 83694// CHECK5-NEXT: [[TMP56:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 13695// CHECK5-NEXT: store ptr null, ptr [[TMP56]], align 83696// CHECK5-NEXT: [[TMP57:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 03697// CHECK5-NEXT: [[TMP58:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 03698// CHECK5-NEXT: [[TMP59:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 03699// CHECK5-NEXT: store i32 3, ptr [[TMP59]], align 43700// CHECK5-NEXT: [[TMP60:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 13701// CHECK5-NEXT: store i32 2, ptr [[TMP60]], align 43702// CHECK5-NEXT: [[TMP61:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 23703// CHECK5-NEXT: store ptr [[TMP57]], ptr [[TMP61]], align 83704// CHECK5-NEXT: [[TMP62:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 33705// CHECK5-NEXT: store ptr [[TMP58]], ptr [[TMP62]], align 83706// CHECK5-NEXT: [[TMP63:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 43707// CHECK5-NEXT: store ptr @.offload_sizes.1, ptr [[TMP63]], align 83708// CHECK5-NEXT: [[TMP64:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 53709// CHECK5-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP64]], align 83710// CHECK5-NEXT: [[TMP65:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 63711// CHECK5-NEXT: store ptr null, ptr [[TMP65]], align 83712// CHECK5-NEXT: [[TMP66:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 73713// CHECK5-NEXT: store ptr null, ptr [[TMP66]], align 83714// CHECK5-NEXT: [[TMP67:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 83715// CHECK5-NEXT: store i64 0, ptr [[TMP67]], align 83716// CHECK5-NEXT: [[TMP68:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 93717// CHECK5-NEXT: store i64 0, ptr [[TMP68]], align 83718// CHECK5-NEXT: [[TMP69:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 103719// CHECK5-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP69]], align 43720// CHECK5-NEXT: [[TMP70:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 113721// CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP70]], align 43722// CHECK5-NEXT: [[TMP71:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 123723// CHECK5-NEXT: store i32 0, ptr [[TMP71]], align 43724// CHECK5-NEXT: [[TMP72:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.region_id, ptr [[KERNEL_ARGS8]])3725// CHECK5-NEXT: [[TMP73:%.*]] = icmp ne i32 [[TMP72]], 03726// CHECK5-NEXT: br i1 [[TMP73]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]]3727// CHECK5: omp_offload.failed9:3728// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP47]], i64 [[TMP49]]) #[[ATTR3]]3729// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT10]]3730// CHECK5: omp_offload.cont10:3731// CHECK5-NEXT: br label [[OMP_IF_END:%.*]]3732// CHECK5: omp_if.else:3733// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP47]], i64 [[TMP49]]) #[[ATTR3]]3734// CHECK5-NEXT: br label [[OMP_IF_END]]3735// CHECK5: omp_if.end:3736// CHECK5-NEXT: [[TMP74:%.*]] = load i32, ptr [[A]], align 43737// CHECK5-NEXT: store i32 [[TMP74]], ptr [[DOTCAPTURE_EXPR_]], align 43738// CHECK5-NEXT: [[TMP75:%.*]] = load i32, ptr [[A]], align 43739// CHECK5-NEXT: store i32 [[TMP75]], ptr [[A_CASTED11]], align 43740// CHECK5-NEXT: [[TMP76:%.*]] = load i64, ptr [[A_CASTED11]], align 83741// CHECK5-NEXT: [[TMP77:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 43742// CHECK5-NEXT: store i32 [[TMP77]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 43743// CHECK5-NEXT: [[TMP78:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 83744// CHECK5-NEXT: [[TMP79:%.*]] = load i32, ptr [[N_ADDR]], align 43745// CHECK5-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP79]], 203746// CHECK5-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE20:%.*]]3747// CHECK5: omp_if.then13:3748// CHECK5-NEXT: [[TMP80:%.*]] = mul nuw i64 [[TMP2]], 43749// CHECK5-NEXT: [[TMP81:%.*]] = mul nuw i64 5, [[TMP5]]3750// CHECK5-NEXT: [[TMP82:%.*]] = mul nuw i64 [[TMP81]], 83751// CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.3, i64 80, i1 false)3752// CHECK5-NEXT: [[TMP83:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 03753// CHECK5-NEXT: store i64 [[TMP76]], ptr [[TMP83]], align 83754// CHECK5-NEXT: [[TMP84:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 03755// CHECK5-NEXT: store i64 [[TMP76]], ptr [[TMP84]], align 83756// CHECK5-NEXT: [[TMP85:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 03757// CHECK5-NEXT: store ptr null, ptr [[TMP85]], align 83758// CHECK5-NEXT: [[TMP86:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 13759// CHECK5-NEXT: store ptr [[B]], ptr [[TMP86]], align 83760// CHECK5-NEXT: [[TMP87:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 13761// CHECK5-NEXT: store ptr [[B]], ptr [[TMP87]], align 83762// CHECK5-NEXT: [[TMP88:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 13763// CHECK5-NEXT: store ptr null, ptr [[TMP88]], align 83764// CHECK5-NEXT: [[TMP89:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 23765// CHECK5-NEXT: store i64 [[TMP2]], ptr [[TMP89]], align 83766// CHECK5-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 23767// CHECK5-NEXT: store i64 [[TMP2]], ptr [[TMP90]], align 83768// CHECK5-NEXT: [[TMP91:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 23769// CHECK5-NEXT: store ptr null, ptr [[TMP91]], align 83770// CHECK5-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 33771// CHECK5-NEXT: store ptr [[VLA]], ptr [[TMP92]], align 83772// CHECK5-NEXT: [[TMP93:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 33773// CHECK5-NEXT: store ptr [[VLA]], ptr [[TMP93]], align 83774// CHECK5-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 33775// CHECK5-NEXT: store i64 [[TMP80]], ptr [[TMP94]], align 83776// CHECK5-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 33777// CHECK5-NEXT: store ptr null, ptr [[TMP95]], align 83778// CHECK5-NEXT: [[TMP96:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 43779// CHECK5-NEXT: store ptr [[C]], ptr [[TMP96]], align 83780// CHECK5-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 43781// CHECK5-NEXT: store ptr [[C]], ptr [[TMP97]], align 83782// CHECK5-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 43783// CHECK5-NEXT: store ptr null, ptr [[TMP98]], align 83784// CHECK5-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 53785// CHECK5-NEXT: store i64 5, ptr [[TMP99]], align 83786// CHECK5-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 53787// CHECK5-NEXT: store i64 5, ptr [[TMP100]], align 83788// CHECK5-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 53789// CHECK5-NEXT: store ptr null, ptr [[TMP101]], align 83790// CHECK5-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 63791// CHECK5-NEXT: store i64 [[TMP5]], ptr [[TMP102]], align 83792// CHECK5-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 63793// CHECK5-NEXT: store i64 [[TMP5]], ptr [[TMP103]], align 83794// CHECK5-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 63795// CHECK5-NEXT: store ptr null, ptr [[TMP104]], align 83796// CHECK5-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 73797// CHECK5-NEXT: store ptr [[VLA1]], ptr [[TMP105]], align 83798// CHECK5-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 73799// CHECK5-NEXT: store ptr [[VLA1]], ptr [[TMP106]], align 83800// CHECK5-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 73801// CHECK5-NEXT: store i64 [[TMP82]], ptr [[TMP107]], align 83802// CHECK5-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 73803// CHECK5-NEXT: store ptr null, ptr [[TMP108]], align 83804// CHECK5-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 83805// CHECK5-NEXT: store ptr [[D]], ptr [[TMP109]], align 83806// CHECK5-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 83807// CHECK5-NEXT: store ptr [[D]], ptr [[TMP110]], align 83808// CHECK5-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 83809// CHECK5-NEXT: store ptr null, ptr [[TMP111]], align 83810// CHECK5-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 93811// CHECK5-NEXT: store i64 [[TMP78]], ptr [[TMP112]], align 83812// CHECK5-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 93813// CHECK5-NEXT: store i64 [[TMP78]], ptr [[TMP113]], align 83814// CHECK5-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 93815// CHECK5-NEXT: store ptr null, ptr [[TMP114]], align 83816// CHECK5-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 03817// CHECK5-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 03818// CHECK5-NEXT: [[TMP117:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 03819// CHECK5-NEXT: [[TMP118:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 03820// CHECK5-NEXT: store i32 3, ptr [[TMP118]], align 43821// CHECK5-NEXT: [[TMP119:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 13822// CHECK5-NEXT: store i32 10, ptr [[TMP119]], align 43823// CHECK5-NEXT: [[TMP120:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 23824// CHECK5-NEXT: store ptr [[TMP115]], ptr [[TMP120]], align 83825// CHECK5-NEXT: [[TMP121:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 33826// CHECK5-NEXT: store ptr [[TMP116]], ptr [[TMP121]], align 83827// CHECK5-NEXT: [[TMP122:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 43828// CHECK5-NEXT: store ptr [[TMP117]], ptr [[TMP122]], align 83829// CHECK5-NEXT: [[TMP123:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 53830// CHECK5-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP123]], align 83831// CHECK5-NEXT: [[TMP124:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 63832// CHECK5-NEXT: store ptr null, ptr [[TMP124]], align 83833// CHECK5-NEXT: [[TMP125:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 73834// CHECK5-NEXT: store ptr null, ptr [[TMP125]], align 83835// CHECK5-NEXT: [[TMP126:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 83836// CHECK5-NEXT: store i64 0, ptr [[TMP126]], align 83837// CHECK5-NEXT: [[TMP127:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 93838// CHECK5-NEXT: store i64 0, ptr [[TMP127]], align 83839// CHECK5-NEXT: [[TMP128:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 103840// CHECK5-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP128]], align 43841// CHECK5-NEXT: [[TMP129:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 113842// CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP129]], align 43843// CHECK5-NEXT: [[TMP130:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 123844// CHECK5-NEXT: store i32 0, ptr [[TMP130]], align 43845// CHECK5-NEXT: [[TMP131:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.region_id, ptr [[KERNEL_ARGS17]])3846// CHECK5-NEXT: [[TMP132:%.*]] = icmp ne i32 [[TMP131]], 03847// CHECK5-NEXT: br i1 [[TMP132]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]]3848// CHECK5: omp_offload.failed18:3849// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP76]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP78]]) #[[ATTR3]]3850// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT19]]3851// CHECK5: omp_offload.cont19:3852// CHECK5-NEXT: br label [[OMP_IF_END21:%.*]]3853// CHECK5: omp_if.else20:3854// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP76]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP78]]) #[[ATTR3]]3855// CHECK5-NEXT: br label [[OMP_IF_END21]]3856// CHECK5: omp_if.end21:3857// CHECK5-NEXT: [[TMP133:%.*]] = load i32, ptr [[A]], align 43858// CHECK5-NEXT: [[TMP134:%.*]] = load ptr, ptr [[SAVED_STACK]], align 83859// CHECK5-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP134]])3860// CHECK5-NEXT: ret i32 [[TMP133]]3861//3862//3863// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l963864// CHECK5-SAME: () #[[ATTR2:[0-9]+]] {3865// CHECK5-NEXT: entry:3866// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined)3867// CHECK5-NEXT: ret void3868//3869//3870// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined3871// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] {3872// CHECK5-NEXT: entry:3873// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 83874// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 83875// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 43876// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 43877// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 43878// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 43879// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 43880// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 43881// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 43882// CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 83883// CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 83884// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 43885// CHECK5-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 43886// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 43887// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 43888// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 83889// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 43890// CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)3891// CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43892// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 53893// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]3894// CHECK5: cond.true:3895// CHECK5-NEXT: br label [[COND_END:%.*]]3896// CHECK5: cond.false:3897// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43898// CHECK5-NEXT: br label [[COND_END]]3899// CHECK5: cond.end:3900// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]3901// CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 43902// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 43903// CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 43904// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]3905// CHECK5: omp.inner.for.cond:3906// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]]3907// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP10]]3908// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]3909// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]3910// CHECK5: omp.inner.for.body:3911// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]3912// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 53913// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]3914// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]3915// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]3916// CHECK5: omp.body.continue:3917// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]3918// CHECK5: omp.inner.for.inc:3919// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]3920// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 13921// CHECK5-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]3922// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]3923// CHECK5: omp.inner.for.end:3924// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]3925// CHECK5: omp.loop.exit:3926// CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])3927// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 43928// CHECK5-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 03929// CHECK5-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]3930// CHECK5: .omp.final.then:3931// CHECK5-NEXT: store i32 33, ptr [[I]], align 43932// CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]3933// CHECK5: .omp.final.done:3934// CHECK5-NEXT: ret void3935//3936//3937// CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry.3938// CHECK5-SAME: (i32 noundef signext [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] {3939// CHECK5-NEXT: entry:3940// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 43941// CHECK5-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 83942// CHECK5-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 83943// CHECK5-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 83944// CHECK5-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 83945// CHECK5-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 83946// CHECK5-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 83947// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i32, align 43948// CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 83949// CHECK5-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 43950// CHECK5-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 83951// CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 43952// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 83953// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 03954// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 23955// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 03956// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 83957// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])3958// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])3959// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])3960// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])3961// CHECK5-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META25:![0-9]+]]3962// CHECK5-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META25]]3963// CHECK5-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META25]]3964// CHECK5-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META25]]3965// CHECK5-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META25]]3966// CHECK5-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META25]]3967// CHECK5-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META25]]3968// CHECK5-NEXT: store i32 3, ptr [[KERNEL_ARGS_I]], align 4, !noalias [[META25]]3969// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 13970// CHECK5-NEXT: store i32 0, ptr [[TMP9]], align 4, !noalias [[META25]]3971// CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 23972// CHECK5-NEXT: store ptr null, ptr [[TMP10]], align 8, !noalias [[META25]]3973// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 33974// CHECK5-NEXT: store ptr null, ptr [[TMP11]], align 8, !noalias [[META25]]3975// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 43976// CHECK5-NEXT: store ptr null, ptr [[TMP12]], align 8, !noalias [[META25]]3977// CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 53978// CHECK5-NEXT: store ptr null, ptr [[TMP13]], align 8, !noalias [[META25]]3979// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 63980// CHECK5-NEXT: store ptr null, ptr [[TMP14]], align 8, !noalias [[META25]]3981// CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 73982// CHECK5-NEXT: store ptr null, ptr [[TMP15]], align 8, !noalias [[META25]]3983// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 83984// CHECK5-NEXT: store i64 0, ptr [[TMP16]], align 8, !noalias [[META25]]3985// CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 93986// CHECK5-NEXT: store i64 1, ptr [[TMP17]], align 8, !noalias [[META25]]3987// CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 103988// CHECK5-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP18]], align 4, !noalias [[META25]]3989// CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 113990// CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP19]], align 4, !noalias [[META25]]3991// CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 123992// CHECK5-NEXT: store i32 0, ptr [[TMP20]], align 4, !noalias [[META25]]3993// CHECK5-NEXT: [[TMP21:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, ptr [[KERNEL_ARGS_I]])3994// CHECK5-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 03995// CHECK5-NEXT: br i1 [[TMP22]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]]3996// CHECK5: omp_offload.failed.i:3997// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR3]]3998// CHECK5-NEXT: br label [[DOTOMP_OUTLINED__EXIT]]3999// CHECK5: .omp_outlined..exit:4000// CHECK5-NEXT: ret i32 04001//4002//4003// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1014004// CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR2]] {4005// CHECK5-NEXT: entry:4006// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 84007// CHECK5-NEXT: [[K_ADDR:%.*]] = alloca i64, align 84008// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 84009// CHECK5-NEXT: [[K_CASTED:%.*]] = alloca i64, align 84010// CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 84011// CHECK5-NEXT: store i64 [[K]], ptr [[K_ADDR]], align 84012// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 44013// CHECK5-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 44014// CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 84015// CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[K_ADDR]], align 84016// CHECK5-NEXT: store i64 [[TMP2]], ptr [[K_CASTED]], align 84017// CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[K_CASTED]], align 84018// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined, i64 [[TMP1]], i64 [[TMP3]])4019// CHECK5-NEXT: ret void4020//4021//4022// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined4023// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR2]] {4024// CHECK5-NEXT: entry:4025// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 84026// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 84027// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 84028// CHECK5-NEXT: [[K_ADDR:%.*]] = alloca i64, align 84029// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 44030// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 44031// CHECK5-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 84032// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 44033// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 44034// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 44035// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 44036// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 44037// CHECK5-NEXT: [[K1:%.*]] = alloca i64, align 84038// CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 84039// CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 84040// CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 84041// CHECK5-NEXT: store i64 [[K]], ptr [[K_ADDR]], align 84042// CHECK5-NEXT: [[TMP0:%.*]] = load i64, ptr [[K_ADDR]], align 84043// CHECK5-NEXT: store i64 [[TMP0]], ptr [[DOTLINEAR_START]], align 84044// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 44045// CHECK5-NEXT: store i32 8, ptr [[DOTOMP_UB]], align 44046// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 44047// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 44048// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 84049// CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 44050// CHECK5-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP2]])4051// CHECK5-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 1073741859, i32 0, i32 8, i32 1, i32 1)4052// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]]4053// CHECK5: omp.dispatch.cond:4054// CHECK5-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB2]], i32 [[TMP2]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])4055// CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 04056// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]4057// CHECK5: omp.dispatch.body:4058// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 44059// CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 44060// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]4061// CHECK5: omp.inner.for.cond:4062// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26:![0-9]+]]4063// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP26]]4064// CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]4065// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]4066// CHECK5: omp.inner.for.body:4067// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]]4068// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 14069// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]4070// CHECK5-NEXT: store i32 [[SUB]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP26]]4071// CHECK5-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP26]]4072// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]]4073// CHECK5-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 34074// CHECK5-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i644075// CHECK5-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV]]4076// CHECK5-NEXT: store i64 [[ADD]], ptr [[K1]], align 8, !llvm.access.group [[ACC_GRP26]]4077// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP26]]4078// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 14079// CHECK5-NEXT: store i32 [[ADD3]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP26]]4080// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]4081// CHECK5: omp.body.continue:4082// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]4083// CHECK5: omp.inner.for.inc:4084// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]]4085// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 14086// CHECK5-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]]4087// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]]4088// CHECK5: omp.inner.for.end:4089// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]]4090// CHECK5: omp.dispatch.inc:4091// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]]4092// CHECK5: omp.dispatch.end:4093// CHECK5-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB2]], i32 [[TMP2]])4094// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 44095// CHECK5-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 04096// CHECK5-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]4097// CHECK5: .omp.final.then:4098// CHECK5-NEXT: store i32 1, ptr [[I]], align 44099// CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]4100// CHECK5: .omp.final.done:4101// CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 44102// CHECK5-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 04103// CHECK5-NEXT: br i1 [[TMP15]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]4104// CHECK5: .omp.linear.pu:4105// CHECK5-NEXT: [[TMP16:%.*]] = load i64, ptr [[K1]], align 84106// CHECK5-NEXT: store i64 [[TMP16]], ptr [[K_ADDR]], align 84107// CHECK5-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]4108// CHECK5: .omp.linear.pu.done:4109// CHECK5-NEXT: ret void4110//4111//4112// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1084113// CHECK5-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] {4114// CHECK5-NEXT: entry:4115// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 84116// CHECK5-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 84117// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 84118// CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 84119// CHECK5-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 84120// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 84121// CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 84122// CHECK5-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 84123// CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 84124// CHECK5-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 24125// CHECK5-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 24126// CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 84127// CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 44128// CHECK5-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 44129// CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[LIN_CASTED]], align 84130// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 44131// CHECK5-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 44132// CHECK5-NEXT: [[TMP5:%.*]] = load i64, ptr [[A_CASTED]], align 84133// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined, i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])4134// CHECK5-NEXT: ret void4135//4136//4137// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined4138// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] {4139// CHECK5-NEXT: entry:4140// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 84141// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 84142// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 84143// CHECK5-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 84144// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 84145// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 84146// CHECK5-NEXT: [[TMP:%.*]] = alloca i64, align 84147// CHECK5-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 44148// CHECK5-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 44149// CHECK5-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 84150// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 84151// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 84152// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 84153// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 44154// CHECK5-NEXT: [[IT:%.*]] = alloca i64, align 84155// CHECK5-NEXT: [[LIN2:%.*]] = alloca i32, align 44156// CHECK5-NEXT: [[A3:%.*]] = alloca i32, align 44157// CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 84158// CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 84159// CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 84160// CHECK5-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 84161// CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 84162// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 44163// CHECK5-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 44164// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 44165// CHECK5-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 44166// CHECK5-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()4167// CHECK5-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 84168// CHECK5-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 84169// CHECK5-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 84170// CHECK5-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 84171// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 44172// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 84173// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 44174// CHECK5-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP3]])4175// CHECK5-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)4176// CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 84177// CHECK5-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 34178// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]4179// CHECK5: cond.true:4180// CHECK5-NEXT: br label [[COND_END:%.*]]4181// CHECK5: cond.false:4182// CHECK5-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 84183// CHECK5-NEXT: br label [[COND_END]]4184// CHECK5: cond.end:4185// CHECK5-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]4186// CHECK5-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 84187// CHECK5-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 84188// CHECK5-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 84189// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]4190// CHECK5: omp.inner.for.cond:4191// CHECK5-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29:![0-9]+]]4192// CHECK5-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP29]]4193// CHECK5-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]4194// CHECK5-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]4195// CHECK5: omp.inner.for.body:4196// CHECK5-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]]4197// CHECK5-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 4004198// CHECK5-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]4199// CHECK5-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP29]]4200// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP29]]4201// CHECK5-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i644202// CHECK5-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]]4203// CHECK5-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP29]]4204// CHECK5-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]]4205// CHECK5-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]]4206// CHECK5-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i324207// CHECK5-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 4, !llvm.access.group [[ACC_GRP29]]4208// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4, !llvm.access.group [[ACC_GRP29]]4209// CHECK5-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i644210// CHECK5-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]]4211// CHECK5-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP29]]4212// CHECK5-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]]4213// CHECK5-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]]4214// CHECK5-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i324215// CHECK5-NEXT: store i32 [[CONV10]], ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP29]]4216// CHECK5-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP29]]4217// CHECK5-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i324218// CHECK5-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 14219// CHECK5-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i164220// CHECK5-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP29]]4221// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]4222// CHECK5: omp.body.continue:4223// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]4224// CHECK5: omp.inner.for.inc:4225// CHECK5-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]]4226// CHECK5-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 14227// CHECK5-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]]4228// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]]4229// CHECK5: omp.inner.for.end:4230// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]4231// CHECK5: omp.loop.exit:4232// CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]])4233// CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 44234// CHECK5-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 04235// CHECK5-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]4236// CHECK5: .omp.final.then:4237// CHECK5-NEXT: store i64 400, ptr [[IT]], align 84238// CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]4239// CHECK5: .omp.final.done:4240// CHECK5-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 44241// CHECK5-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 04242// CHECK5-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]4243// CHECK5: .omp.linear.pu:4244// CHECK5-NEXT: [[TMP22:%.*]] = load i32, ptr [[LIN2]], align 44245// CHECK5-NEXT: store i32 [[TMP22]], ptr [[LIN_ADDR]], align 44246// CHECK5-NEXT: [[TMP23:%.*]] = load i32, ptr [[A3]], align 44247// CHECK5-NEXT: store i32 [[TMP23]], ptr [[A_ADDR]], align 44248// CHECK5-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]4249// CHECK5: .omp.linear.pu.done:4250// CHECK5-NEXT: ret void4251//4252//4253// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1164254// CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {4255// CHECK5-NEXT: entry:4256// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 84257// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 84258// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 84259// CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 84260// CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 84261// CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 84262// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 44263// CHECK5-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 44264// CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 84265// CHECK5-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 24266// CHECK5-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 24267// CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 84268// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined, i64 [[TMP1]], i64 [[TMP3]])4269// CHECK5-NEXT: ret void4270//4271//4272// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined4273// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {4274// CHECK5-NEXT: entry:4275// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 84276// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 84277// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 84278// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 84279// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 44280// CHECK5-NEXT: [[TMP:%.*]] = alloca i16, align 24281// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 44282// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 44283// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 44284// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 44285// CHECK5-NEXT: [[IT:%.*]] = alloca i16, align 24286// CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 84287// CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 84288// CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 84289// CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 84290// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 44291// CHECK5-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 44292// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 44293// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 44294// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 84295// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 44296// CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)4297// CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44298// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 34299// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]4300// CHECK5: cond.true:4301// CHECK5-NEXT: br label [[COND_END:%.*]]4302// CHECK5: cond.false:4303// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44304// CHECK5-NEXT: br label [[COND_END]]4305// CHECK5: cond.end:4306// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]4307// CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 44308// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 44309// CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 44310// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]4311// CHECK5: omp.inner.for.cond:4312// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32:![0-9]+]]4313// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP32]]4314// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]4315// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]4316// CHECK5: omp.inner.for.body:4317// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]]4318// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 44319// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]4320// CHECK5-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i164321// CHECK5-NEXT: store i16 [[CONV]], ptr [[IT]], align 2, !llvm.access.group [[ACC_GRP32]]4322// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP32]]4323// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 14324// CHECK5-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP32]]4325// CHECK5-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP32]]4326// CHECK5-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i324327// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 14328// CHECK5-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i164329// CHECK5-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP32]]4330// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]4331// CHECK5: omp.body.continue:4332// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]4333// CHECK5: omp.inner.for.inc:4334// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]]4335// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 14336// CHECK5-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]]4337// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]]4338// CHECK5: omp.inner.for.end:4339// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]4340// CHECK5: omp.loop.exit:4341// CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])4342// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 44343// CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 04344// CHECK5-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]4345// CHECK5: .omp.final.then:4346// CHECK5-NEXT: store i16 22, ptr [[IT]], align 24347// CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]4348// CHECK5: .omp.final.done:4349// CHECK5-NEXT: ret void4350//4351//4352// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1404353// CHECK5-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {4354// CHECK5-NEXT: entry:4355// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 84356// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 84357// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 84358// CHECK5-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 84359// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 84360// CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 84361// CHECK5-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 84362// CHECK5-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 84363// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 84364// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 84365// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 84366// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 84367// CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 84368// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 84369// CHECK5-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 84370// CHECK5-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 84371// CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 84372// CHECK5-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 84373// CHECK5-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 84374// CHECK5-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 84375// CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 84376// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 84377// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 84378// CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 84379// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 84380// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 84381// CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 84382// CHECK5-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 84383// CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 84384// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 84385// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 44386// CHECK5-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 44387// CHECK5-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 84388// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 44389// CHECK5-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 44390// CHECK5-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 84391// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i64 [[TMP11]])4392// CHECK5-NEXT: ret void4393//4394//4395// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined4396// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {4397// CHECK5-NEXT: entry:4398// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 84399// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 84400// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 84401// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 84402// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 84403// CHECK5-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 84404// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 84405// CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 84406// CHECK5-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 84407// CHECK5-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 84408// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 84409// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 84410// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 44411// CHECK5-NEXT: [[TMP:%.*]] = alloca i8, align 14412// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 44413// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 44414// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 44415// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 44416// CHECK5-NEXT: [[IT:%.*]] = alloca i8, align 14417// CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 84418// CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 84419// CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 84420// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 84421// CHECK5-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 84422// CHECK5-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 84423// CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 84424// CHECK5-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 84425// CHECK5-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 84426// CHECK5-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 84427// CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 84428// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 84429// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 84430// CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 84431// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 84432// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 84433// CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 84434// CHECK5-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 84435// CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 84436// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 84437// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 44438// CHECK5-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 44439// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 44440// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 44441// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 44442// CHECK5-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 84443// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 44444// CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])4445// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]]4446// CHECK5: omp.dispatch.cond:4447// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44448// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 254449// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]4450// CHECK5: cond.true:4451// CHECK5-NEXT: br label [[COND_END:%.*]]4452// CHECK5: cond.false:4453// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44454// CHECK5-NEXT: br label [[COND_END]]4455// CHECK5: cond.end:4456// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]4457// CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 44458// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 44459// CHECK5-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 44460// CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44461// CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44462// CHECK5-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]4463// CHECK5-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]4464// CHECK5: omp.dispatch.body:4465// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]4466// CHECK5: omp.inner.for.cond:4467// CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35:![0-9]+]]4468// CHECK5-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP35]]4469// CHECK5-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]4470// CHECK5-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]4471// CHECK5: omp.inner.for.body:4472// CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]]4473// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 14474// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]4475// CHECK5-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i84476// CHECK5-NEXT: store i8 [[CONV]], ptr [[IT]], align 1, !llvm.access.group [[ACC_GRP35]]4477// CHECK5-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP35]]4478// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 14479// CHECK5-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP35]]4480// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 24481// CHECK5-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP35]]4482// CHECK5-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double4483// CHECK5-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+004484// CHECK5-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float4485// CHECK5-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP35]]4486// CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 34487// CHECK5-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP35]]4488// CHECK5-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double4489// CHECK5-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+004490// CHECK5-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float4491// CHECK5-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP35]]4492// CHECK5-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 14493// CHECK5-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i64 0, i64 24494// CHECK5-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP35]]4495// CHECK5-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+004496// CHECK5-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP35]]4497// CHECK5-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]4498// CHECK5-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP23]]4499// CHECK5-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i64 34500// CHECK5-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP35]]4501// CHECK5-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+004502// CHECK5-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP35]]4503// CHECK5-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 04504// CHECK5-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP35]]4505// CHECK5-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 14506// CHECK5-NEXT: store i64 [[ADD20]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP35]]4507// CHECK5-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 14508// CHECK5-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP35]]4509// CHECK5-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i324510// CHECK5-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 14511// CHECK5-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i84512// CHECK5-NEXT: store i8 [[CONV23]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP35]]4513// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]4514// CHECK5: omp.body.continue:4515// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]4516// CHECK5: omp.inner.for.inc:4517// CHECK5-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]]4518// CHECK5-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 14519// CHECK5-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]]4520// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]]4521// CHECK5: omp.inner.for.end:4522// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]]4523// CHECK5: omp.dispatch.inc:4524// CHECK5-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 44525// CHECK5-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 44526// CHECK5-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]4527// CHECK5-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 44528// CHECK5-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44529// CHECK5-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 44530// CHECK5-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]4531// CHECK5-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 44532// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]]4533// CHECK5: omp.dispatch.end:4534// CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]])4535// CHECK5-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 44536// CHECK5-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 04537// CHECK5-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]4538// CHECK5: .omp.final.then:4539// CHECK5-NEXT: store i8 96, ptr [[IT]], align 14540// CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]4541// CHECK5: .omp.final.done:4542// CHECK5-NEXT: ret void4543//4544//4545// CHECK5-LABEL: define {{[^@]+}}@_Z3bari4546// CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {4547// CHECK5-NEXT: entry:4548// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 44549// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 44550// CHECK5-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 84551// CHECK5-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 44552// CHECK5-NEXT: store i32 0, ptr [[A]], align 44553// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 44554// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]])4555// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 44556// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]4557// CHECK5-NEXT: store i32 [[ADD]], ptr [[A]], align 44558// CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 44559// CHECK5-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]])4560// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 44561// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]4562// CHECK5-NEXT: store i32 [[ADD2]], ptr [[A]], align 44563// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 44564// CHECK5-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]])4565// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 44566// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]4567// CHECK5-NEXT: store i32 [[ADD4]], ptr [[A]], align 44568// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 44569// CHECK5-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]])4570// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 44571// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]4572// CHECK5-NEXT: store i32 [[ADD6]], ptr [[A]], align 44573// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 44574// CHECK5-NEXT: ret i32 [[TMP8]]4575//4576//4577// CHECK5-LABEL: define {{[^@]+}}@_ZN2S12r1Ei4578// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {4579// CHECK5-NEXT: entry:4580// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 84581// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 44582// CHECK5-NEXT: [[B:%.*]] = alloca i32, align 44583// CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 84584// CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 84585// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 14586// CHECK5-NEXT: [[B_CASTED:%.*]] = alloca i64, align 84587// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 84588// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [6 x ptr], align 84589// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [6 x ptr], align 84590// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [6 x ptr], align 84591// CHECK5-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [6 x i64], align 84592// CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 84593// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 84594// CHECK5-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 44595// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 84596// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 44597// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 14598// CHECK5-NEXT: store i32 [[ADD]], ptr [[B]], align 44599// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 44600// CHECK5-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i644601// CHECK5-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()4602// CHECK5-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 84603// CHECK5-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]4604// CHECK5-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 24605// CHECK5-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 84606// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 44607// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 604608// CHECK5-NEXT: [[STOREDV:%.*]] = zext i1 [[CMP]] to i84609// CHECK5-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_]], align 14610// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[B]], align 44611// CHECK5-NEXT: store i32 [[TMP6]], ptr [[B_CASTED]], align 44612// CHECK5-NEXT: [[TMP7:%.*]] = load i64, ptr [[B_CASTED]], align 84613// CHECK5-NEXT: [[TMP8:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 14614// CHECK5-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP8]] to i14615// CHECK5-NEXT: [[STOREDV2:%.*]] = zext i1 [[LOADEDV]] to i84616// CHECK5-NEXT: store i8 [[STOREDV2]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 14617// CHECK5-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 84618// CHECK5-NEXT: [[TMP10:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 14619// CHECK5-NEXT: [[LOADEDV3:%.*]] = trunc i8 [[TMP10]] to i14620// CHECK5-NEXT: br i1 [[LOADEDV3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]4621// CHECK5: omp_if.then:4622// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 04623// CHECK5-NEXT: [[TMP11:%.*]] = mul nuw i64 2, [[TMP2]]4624// CHECK5-NEXT: [[TMP12:%.*]] = mul nuw i64 [[TMP11]], 24625// CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.5, i64 48, i1 false)4626// CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 04627// CHECK5-NEXT: store ptr [[THIS1]], ptr [[TMP13]], align 84628// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 04629// CHECK5-NEXT: store ptr [[A]], ptr [[TMP14]], align 84630// CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 04631// CHECK5-NEXT: store ptr null, ptr [[TMP15]], align 84632// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 14633// CHECK5-NEXT: store i64 [[TMP7]], ptr [[TMP16]], align 84634// CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 14635// CHECK5-NEXT: store i64 [[TMP7]], ptr [[TMP17]], align 84636// CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 14637// CHECK5-NEXT: store ptr null, ptr [[TMP18]], align 84638// CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 24639// CHECK5-NEXT: store i64 2, ptr [[TMP19]], align 84640// CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 24641// CHECK5-NEXT: store i64 2, ptr [[TMP20]], align 84642// CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 24643// CHECK5-NEXT: store ptr null, ptr [[TMP21]], align 84644// CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 34645// CHECK5-NEXT: store i64 [[TMP2]], ptr [[TMP22]], align 84646// CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 34647// CHECK5-NEXT: store i64 [[TMP2]], ptr [[TMP23]], align 84648// CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 34649// CHECK5-NEXT: store ptr null, ptr [[TMP24]], align 84650// CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 44651// CHECK5-NEXT: store ptr [[VLA]], ptr [[TMP25]], align 84652// CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 44653// CHECK5-NEXT: store ptr [[VLA]], ptr [[TMP26]], align 84654// CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [6 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 44655// CHECK5-NEXT: store i64 [[TMP12]], ptr [[TMP27]], align 84656// CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 44657// CHECK5-NEXT: store ptr null, ptr [[TMP28]], align 84658// CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 54659// CHECK5-NEXT: store i64 [[TMP9]], ptr [[TMP29]], align 84660// CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 54661// CHECK5-NEXT: store i64 [[TMP9]], ptr [[TMP30]], align 84662// CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 54663// CHECK5-NEXT: store ptr null, ptr [[TMP31]], align 84664// CHECK5-NEXT: [[TMP32:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 04665// CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 04666// CHECK5-NEXT: [[TMP34:%.*]] = getelementptr inbounds [6 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 04667// CHECK5-NEXT: [[TMP35:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 14668// CHECK5-NEXT: [[LOADEDV4:%.*]] = trunc i8 [[TMP35]] to i14669// CHECK5-NEXT: [[TMP36:%.*]] = select i1 [[LOADEDV4]], i32 0, i32 14670// CHECK5-NEXT: [[TMP37:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP36]], 04671// CHECK5-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 04672// CHECK5-NEXT: store i32 3, ptr [[TMP38]], align 44673// CHECK5-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 14674// CHECK5-NEXT: store i32 6, ptr [[TMP39]], align 44675// CHECK5-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 24676// CHECK5-NEXT: store ptr [[TMP32]], ptr [[TMP40]], align 84677// CHECK5-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 34678// CHECK5-NEXT: store ptr [[TMP33]], ptr [[TMP41]], align 84679// CHECK5-NEXT: [[TMP42:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 44680// CHECK5-NEXT: store ptr [[TMP34]], ptr [[TMP42]], align 84681// CHECK5-NEXT: [[TMP43:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 54682// CHECK5-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP43]], align 84683// CHECK5-NEXT: [[TMP44:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 64684// CHECK5-NEXT: store ptr null, ptr [[TMP44]], align 84685// CHECK5-NEXT: [[TMP45:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 74686// CHECK5-NEXT: store ptr null, ptr [[TMP45]], align 84687// CHECK5-NEXT: [[TMP46:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 84688// CHECK5-NEXT: store i64 0, ptr [[TMP46]], align 84689// CHECK5-NEXT: [[TMP47:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 94690// CHECK5-NEXT: store i64 0, ptr [[TMP47]], align 84691// CHECK5-NEXT: [[TMP48:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 104692// CHECK5-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP48]], align 44693// CHECK5-NEXT: [[TMP49:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 114694// CHECK5-NEXT: store [3 x i32] [[TMP37]], ptr [[TMP49]], align 44695// CHECK5-NEXT: [[TMP50:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 124696// CHECK5-NEXT: store i32 0, ptr [[TMP50]], align 44697// CHECK5-NEXT: [[TMP51:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 [[TMP36]], ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.region_id, ptr [[KERNEL_ARGS]])4698// CHECK5-NEXT: [[TMP52:%.*]] = icmp ne i32 [[TMP51]], 04699// CHECK5-NEXT: br i1 [[TMP52]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]4700// CHECK5: omp_offload.failed:4701// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(ptr [[THIS1]], i64 [[TMP7]], i64 2, i64 [[TMP2]], ptr [[VLA]], i64 [[TMP9]]) #[[ATTR3]]4702// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]]4703// CHECK5: omp_offload.cont:4704// CHECK5-NEXT: br label [[OMP_IF_END:%.*]]4705// CHECK5: omp_if.else:4706// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(ptr [[THIS1]], i64 [[TMP7]], i64 2, i64 [[TMP2]], ptr [[VLA]], i64 [[TMP9]]) #[[ATTR3]]4707// CHECK5-NEXT: br label [[OMP_IF_END]]4708// CHECK5: omp_if.end:4709// CHECK5-NEXT: [[TMP53:%.*]] = mul nsw i64 1, [[TMP2]]4710// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP53]]4711// CHECK5-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 14712// CHECK5-NEXT: [[TMP54:%.*]] = load i16, ptr [[ARRAYIDX5]], align 24713// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP54]] to i324714// CHECK5-NEXT: [[TMP55:%.*]] = load i32, ptr [[B]], align 44715// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV]], [[TMP55]]4716// CHECK5-NEXT: [[TMP56:%.*]] = load ptr, ptr [[SAVED_STACK]], align 84717// CHECK5-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP56]])4718// CHECK5-NEXT: ret i32 [[ADD6]]4719//4720//4721// CHECK5-LABEL: define {{[^@]+}}@_ZL7fstatici4722// CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {4723// CHECK5-NEXT: entry:4724// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 44725// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 44726// CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 24727// CHECK5-NEXT: [[AAA:%.*]] = alloca i8, align 14728// CHECK5-NEXT: [[B:%.*]] = alloca [10 x i32], align 44729// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 84730// CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 84731// CHECK5-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 84732// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 84733// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 84734// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 84735// CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 84736// CHECK5-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 44737// CHECK5-NEXT: store i32 0, ptr [[A]], align 44738// CHECK5-NEXT: store i16 0, ptr [[AA]], align 24739// CHECK5-NEXT: store i8 0, ptr [[AAA]], align 14740// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 44741// CHECK5-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 44742// CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 84743// CHECK5-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 24744// CHECK5-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 24745// CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 84746// CHECK5-NEXT: [[TMP4:%.*]] = load i8, ptr [[AAA]], align 14747// CHECK5-NEXT: store i8 [[TMP4]], ptr [[AAA_CASTED]], align 14748// CHECK5-NEXT: [[TMP5:%.*]] = load i64, ptr [[AAA_CASTED]], align 84749// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 44750// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 504751// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]4752// CHECK5: omp_if.then:4753// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 04754// CHECK5-NEXT: store i64 [[TMP1]], ptr [[TMP7]], align 84755// CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 04756// CHECK5-NEXT: store i64 [[TMP1]], ptr [[TMP8]], align 84757// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 04758// CHECK5-NEXT: store ptr null, ptr [[TMP9]], align 84759// CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 14760// CHECK5-NEXT: store i64 [[TMP3]], ptr [[TMP10]], align 84761// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 14762// CHECK5-NEXT: store i64 [[TMP3]], ptr [[TMP11]], align 84763// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 14764// CHECK5-NEXT: store ptr null, ptr [[TMP12]], align 84765// CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 24766// CHECK5-NEXT: store i64 [[TMP5]], ptr [[TMP13]], align 84767// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 24768// CHECK5-NEXT: store i64 [[TMP5]], ptr [[TMP14]], align 84769// CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 24770// CHECK5-NEXT: store ptr null, ptr [[TMP15]], align 84771// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 34772// CHECK5-NEXT: store ptr [[B]], ptr [[TMP16]], align 84773// CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 34774// CHECK5-NEXT: store ptr [[B]], ptr [[TMP17]], align 84775// CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 34776// CHECK5-NEXT: store ptr null, ptr [[TMP18]], align 84777// CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 04778// CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 04779// CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 04780// CHECK5-NEXT: store i32 3, ptr [[TMP21]], align 44781// CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 14782// CHECK5-NEXT: store i32 4, ptr [[TMP22]], align 44783// CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 24784// CHECK5-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 84785// CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 34786// CHECK5-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 84787// CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 44788// CHECK5-NEXT: store ptr @.offload_sizes.7, ptr [[TMP25]], align 84789// CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 54790// CHECK5-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP26]], align 84791// CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 64792// CHECK5-NEXT: store ptr null, ptr [[TMP27]], align 84793// CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 74794// CHECK5-NEXT: store ptr null, ptr [[TMP28]], align 84795// CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 84796// CHECK5-NEXT: store i64 0, ptr [[TMP29]], align 84797// CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 94798// CHECK5-NEXT: store i64 0, ptr [[TMP30]], align 84799// CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 104800// CHECK5-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP31]], align 44801// CHECK5-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 114802// CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP32]], align 44803// CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 124804// CHECK5-NEXT: store i32 0, ptr [[TMP33]], align 44805// CHECK5-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.region_id, ptr [[KERNEL_ARGS]])4806// CHECK5-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 04807// CHECK5-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]4808// CHECK5: omp_offload.failed:4809// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR3]]4810// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]]4811// CHECK5: omp_offload.cont:4812// CHECK5-NEXT: br label [[OMP_IF_END:%.*]]4813// CHECK5: omp_if.else:4814// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR3]]4815// CHECK5-NEXT: br label [[OMP_IF_END]]4816// CHECK5: omp_if.end:4817// CHECK5-NEXT: [[TMP36:%.*]] = load i32, ptr [[A]], align 44818// CHECK5-NEXT: ret i32 [[TMP36]]4819//4820//4821// CHECK5-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i4822// CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {4823// CHECK5-NEXT: entry:4824// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 44825// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 44826// CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 24827// CHECK5-NEXT: [[B:%.*]] = alloca [10 x i32], align 44828// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 84829// CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 84830// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 84831// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 84832// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 84833// CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 84834// CHECK5-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 44835// CHECK5-NEXT: store i32 0, ptr [[A]], align 44836// CHECK5-NEXT: store i16 0, ptr [[AA]], align 24837// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 44838// CHECK5-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 44839// CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 84840// CHECK5-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 24841// CHECK5-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 24842// CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 84843// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 44844// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 404845// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]4846// CHECK5: omp_if.then:4847// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 04848// CHECK5-NEXT: store i64 [[TMP1]], ptr [[TMP5]], align 84849// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 04850// CHECK5-NEXT: store i64 [[TMP1]], ptr [[TMP6]], align 84851// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 04852// CHECK5-NEXT: store ptr null, ptr [[TMP7]], align 84853// CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 14854// CHECK5-NEXT: store i64 [[TMP3]], ptr [[TMP8]], align 84855// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 14856// CHECK5-NEXT: store i64 [[TMP3]], ptr [[TMP9]], align 84857// CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 14858// CHECK5-NEXT: store ptr null, ptr [[TMP10]], align 84859// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 24860// CHECK5-NEXT: store ptr [[B]], ptr [[TMP11]], align 84861// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 24862// CHECK5-NEXT: store ptr [[B]], ptr [[TMP12]], align 84863// CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 24864// CHECK5-NEXT: store ptr null, ptr [[TMP13]], align 84865// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 04866// CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 04867// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 04868// CHECK5-NEXT: store i32 3, ptr [[TMP16]], align 44869// CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 14870// CHECK5-NEXT: store i32 3, ptr [[TMP17]], align 44871// CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 24872// CHECK5-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 84873// CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 34874// CHECK5-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 84875// CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 44876// CHECK5-NEXT: store ptr @.offload_sizes.9, ptr [[TMP20]], align 84877// CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 54878// CHECK5-NEXT: store ptr @.offload_maptypes.10, ptr [[TMP21]], align 84879// CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 64880// CHECK5-NEXT: store ptr null, ptr [[TMP22]], align 84881// CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 74882// CHECK5-NEXT: store ptr null, ptr [[TMP23]], align 84883// CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 84884// CHECK5-NEXT: store i64 0, ptr [[TMP24]], align 84885// CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 94886// CHECK5-NEXT: store i64 0, ptr [[TMP25]], align 84887// CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 104888// CHECK5-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP26]], align 44889// CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 114890// CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP27]], align 44891// CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 124892// CHECK5-NEXT: store i32 0, ptr [[TMP28]], align 44893// CHECK5-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.region_id, ptr [[KERNEL_ARGS]])4894// CHECK5-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 04895// CHECK5-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]4896// CHECK5: omp_offload.failed:4897// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]]4898// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]]4899// CHECK5: omp_offload.cont:4900// CHECK5-NEXT: br label [[OMP_IF_END:%.*]]4901// CHECK5: omp_if.else:4902// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]]4903// CHECK5-NEXT: br label [[OMP_IF_END]]4904// CHECK5: omp_if.end:4905// CHECK5-NEXT: [[TMP31:%.*]] = load i32, ptr [[A]], align 44906// CHECK5-NEXT: ret i32 [[TMP31]]4907//4908//4909// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l2144910// CHECK5-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {4911// CHECK5-NEXT: entry:4912// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 84913// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i64, align 84914// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 84915// CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 84916// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 84917// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 84918// CHECK5-NEXT: [[B_CASTED:%.*]] = alloca i64, align 84919// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 84920// CHECK5-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 44921// CHECK5-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 44922// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])4923// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 84924// CHECK5-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 84925// CHECK5-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 84926// CHECK5-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 84927// CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 84928// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 84929// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 84930// CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR]], align 84931// CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[VLA_ADDR2]], align 84932// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[C_ADDR]], align 84933// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_ADDR]], align 44934// CHECK5-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 44935// CHECK5-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 84936// CHECK5-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 14937// CHECK5-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP7]] to i14938// CHECK5-NEXT: [[STOREDV:%.*]] = zext i1 [[LOADEDV]] to i84939// CHECK5-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 14940// CHECK5-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 84941// CHECK5-NEXT: [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 14942// CHECK5-NEXT: [[LOADEDV3:%.*]] = trunc i8 [[TMP9]] to i14943// CHECK5-NEXT: br i1 [[LOADEDV3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]4944// CHECK5: omp_if.then:4945// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined, ptr [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], ptr [[TMP4]], i64 [[TMP8]])4946// CHECK5-NEXT: br label [[OMP_IF_END:%.*]]4947// CHECK5: omp_if.else:4948// CHECK5-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]])4949// CHECK5-NEXT: store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 44950// CHECK5-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 44951// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], ptr [[TMP4]], i64 [[TMP8]]) #[[ATTR3]]4952// CHECK5-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]])4953// CHECK5-NEXT: br label [[OMP_IF_END]]4954// CHECK5: omp_if.end:4955// CHECK5-NEXT: ret void4956//4957//4958// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined4959// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {4960// CHECK5-NEXT: entry:4961// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 84962// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 84963// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 84964// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i64, align 84965// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 84966// CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 84967// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 84968// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 84969// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 84970// CHECK5-NEXT: [[TMP:%.*]] = alloca i64, align 84971// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 84972// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 84973// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 84974// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 44975// CHECK5-NEXT: [[IT:%.*]] = alloca i64, align 84976// CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 84977// CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 84978// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 84979// CHECK5-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 84980// CHECK5-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 84981// CHECK5-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 84982// CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 84983// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 84984// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 84985// CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 84986// CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 84987// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 84988// CHECK5-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 84989// CHECK5-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 84990// CHECK5-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 84991// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 44992// CHECK5-NEXT: [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 14993// CHECK5-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP4]] to i14994// CHECK5-NEXT: br i1 [[LOADEDV]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]4995// CHECK5: omp_if.then:4996// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 84997// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 44998// CHECK5-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP6]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)4999// CHECK5-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 85000// CHECK5-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 35001// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]5002// CHECK5: cond.true:5003// CHECK5-NEXT: br label [[COND_END:%.*]]5004// CHECK5: cond.false:5005// CHECK5-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 85006// CHECK5-NEXT: br label [[COND_END]]5007// CHECK5: cond.end:5008// CHECK5-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]5009// CHECK5-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 85010// CHECK5-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_LB]], align 85011// CHECK5-NEXT: store i64 [[TMP9]], ptr [[DOTOMP_IV]], align 85012// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]5013// CHECK5: omp.inner.for.cond:5014// CHECK5-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38:![0-9]+]]5015// CHECK5-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP38]]5016// CHECK5-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]]5017// CHECK5-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]5018// CHECK5: omp.inner.for.body:5019// CHECK5-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38]]5020// CHECK5-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 4005021// CHECK5-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]5022// CHECK5-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP38]]5023// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP38]]5024// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP13]] to double5025// CHECK5-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+005026// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 05027// CHECK5-NEXT: store double [[ADD]], ptr [[A]], align 8, !nontemporal [[META39:![0-9]+]], !llvm.access.group [[ACC_GRP38]]5028// CHECK5-NEXT: [[A4:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 05029// CHECK5-NEXT: [[TMP14:%.*]] = load double, ptr [[A4]], align 8, !nontemporal [[META39]], !llvm.access.group [[ACC_GRP38]]5030// CHECK5-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+005031// CHECK5-NEXT: store double [[INC]], ptr [[A4]], align 8, !nontemporal [[META39]], !llvm.access.group [[ACC_GRP38]]5032// CHECK5-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i165033// CHECK5-NEXT: [[TMP15:%.*]] = mul nsw i64 1, [[TMP2]]5034// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP15]]5035// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 15036// CHECK5-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP38]]5037// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]5038// CHECK5: omp.body.continue:5039// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]5040// CHECK5: omp.inner.for.inc:5041// CHECK5-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38]]5042// CHECK5-NEXT: [[ADD7:%.*]] = add i64 [[TMP16]], 15043// CHECK5-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38]]5044// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]]5045// CHECK5: omp.inner.for.end:5046// CHECK5-NEXT: br label [[OMP_IF_END:%.*]]5047// CHECK5: omp_if.else:5048// CHECK5-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 85049// CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 45050// CHECK5-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP18]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)5051// CHECK5-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_UB]], align 85052// CHECK5-NEXT: [[CMP8:%.*]] = icmp ugt i64 [[TMP19]], 35053// CHECK5-NEXT: br i1 [[CMP8]], label [[COND_TRUE9:%.*]], label [[COND_FALSE10:%.*]]5054// CHECK5: cond.true9:5055// CHECK5-NEXT: br label [[COND_END11:%.*]]5056// CHECK5: cond.false10:5057// CHECK5-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_UB]], align 85058// CHECK5-NEXT: br label [[COND_END11]]5059// CHECK5: cond.end11:5060// CHECK5-NEXT: [[COND12:%.*]] = phi i64 [ 3, [[COND_TRUE9]] ], [ [[TMP20]], [[COND_FALSE10]] ]5061// CHECK5-NEXT: store i64 [[COND12]], ptr [[DOTOMP_UB]], align 85062// CHECK5-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_LB]], align 85063// CHECK5-NEXT: store i64 [[TMP21]], ptr [[DOTOMP_IV]], align 85064// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]]5065// CHECK5: omp.inner.for.cond13:5066// CHECK5-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 85067// CHECK5-NEXT: [[TMP23:%.*]] = load i64, ptr [[DOTOMP_UB]], align 85068// CHECK5-NEXT: [[CMP14:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]]5069// CHECK5-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END29:%.*]]5070// CHECK5: omp.inner.for.body15:5071// CHECK5-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_IV]], align 85072// CHECK5-NEXT: [[MUL16:%.*]] = mul i64 [[TMP24]], 4005073// CHECK5-NEXT: [[SUB17:%.*]] = sub i64 2000, [[MUL16]]5074// CHECK5-NEXT: store i64 [[SUB17]], ptr [[IT]], align 85075// CHECK5-NEXT: [[TMP25:%.*]] = load i32, ptr [[B_ADDR]], align 45076// CHECK5-NEXT: [[CONV18:%.*]] = sitofp i32 [[TMP25]] to double5077// CHECK5-NEXT: [[ADD19:%.*]] = fadd double [[CONV18]], 1.500000e+005078// CHECK5-NEXT: [[A20:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 05079// CHECK5-NEXT: store double [[ADD19]], ptr [[A20]], align 85080// CHECK5-NEXT: [[A21:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 05081// CHECK5-NEXT: [[TMP26:%.*]] = load double, ptr [[A21]], align 85082// CHECK5-NEXT: [[INC22:%.*]] = fadd double [[TMP26]], 1.000000e+005083// CHECK5-NEXT: store double [[INC22]], ptr [[A21]], align 85084// CHECK5-NEXT: [[CONV23:%.*]] = fptosi double [[INC22]] to i165085// CHECK5-NEXT: [[TMP27:%.*]] = mul nsw i64 1, [[TMP2]]5086// CHECK5-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP27]]5087// CHECK5-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX24]], i64 15088// CHECK5-NEXT: store i16 [[CONV23]], ptr [[ARRAYIDX25]], align 25089// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE26:%.*]]5090// CHECK5: omp.body.continue26:5091// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC27:%.*]]5092// CHECK5: omp.inner.for.inc27:5093// CHECK5-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTOMP_IV]], align 85094// CHECK5-NEXT: [[ADD28:%.*]] = add i64 [[TMP28]], 15095// CHECK5-NEXT: store i64 [[ADD28]], ptr [[DOTOMP_IV]], align 85096// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP42:![0-9]+]]5097// CHECK5: omp.inner.for.end29:5098// CHECK5-NEXT: br label [[OMP_IF_END]]5099// CHECK5: omp_if.end:5100// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]5101// CHECK5: omp.loop.exit:5102// CHECK5-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 85103// CHECK5-NEXT: [[TMP30:%.*]] = load i32, ptr [[TMP29]], align 45104// CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP30]])5105// CHECK5-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 45106// CHECK5-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 05107// CHECK5-NEXT: br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]5108// CHECK5: .omp.final.then:5109// CHECK5-NEXT: store i64 400, ptr [[IT]], align 85110// CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]5111// CHECK5: .omp.final.done:5112// CHECK5-NEXT: ret void5113//5114//5115// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l1955116// CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {5117// CHECK5-NEXT: entry:5118// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 85119// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 85120// CHECK5-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 85121// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 85122// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 85123// CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 85124// CHECK5-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 85125// CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 85126// CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 85127// CHECK5-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 85128// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 85129// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 85130// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 45131// CHECK5-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 45132// CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 85133// CHECK5-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 25134// CHECK5-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 25135// CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 85136// CHECK5-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 15137// CHECK5-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 15138// CHECK5-NEXT: [[TMP6:%.*]] = load i64, ptr [[AAA_CASTED]], align 85139// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], ptr [[TMP0]])5140// CHECK5-NEXT: ret void5141//5142//5143// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined5144// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {5145// CHECK5-NEXT: entry:5146// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 85147// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 85148// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 85149// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 85150// CHECK5-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 85151// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 85152// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 45153// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 45154// CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 85155// CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 85156// CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 85157// CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 85158// CHECK5-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 85159// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 85160// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 85161// CHECK5-NEXT: ret void5162//5163//5164// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l1785165// CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {5166// CHECK5-NEXT: entry:5167// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 85168// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 85169// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 85170// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 85171// CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 85172// CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 85173// CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 85174// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 85175// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 85176// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 45177// CHECK5-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 45178// CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 85179// CHECK5-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 25180// CHECK5-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 25181// CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 85182// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]])5183// CHECK5-NEXT: ret void5184//5185//5186// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined5187// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {5188// CHECK5-NEXT: entry:5189// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 85190// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 85191// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 85192// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 85193// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 85194// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 85195// CHECK5-NEXT: [[TMP:%.*]] = alloca i64, align 85196// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 85197// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 85198// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 85199// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 45200// CHECK5-NEXT: [[I:%.*]] = alloca i64, align 85201// CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 85202// CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 85203// CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 85204// CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 85205// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 85206// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 85207// CHECK5-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 85208// CHECK5-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 85209// CHECK5-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 85210// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 45211// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 85212// CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 45213// CHECK5-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)5214// CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 85215// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 65216// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]5217// CHECK5: cond.true:5218// CHECK5-NEXT: br label [[COND_END:%.*]]5219// CHECK5: cond.false:5220// CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 85221// CHECK5-NEXT: br label [[COND_END]]5222// CHECK5: cond.end:5223// CHECK5-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]5224// CHECK5-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 85225// CHECK5-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 85226// CHECK5-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 85227// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]5228// CHECK5: omp.inner.for.cond:5229// CHECK5-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP44:![0-9]+]]5230// CHECK5-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP44]]5231// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]5232// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]5233// CHECK5: omp.inner.for.body:5234// CHECK5-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP44]]5235// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 35236// CHECK5-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]5237// CHECK5-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP44]]5238// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP44]]5239// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 15240// CHECK5-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP44]]5241// CHECK5-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP44]]5242// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i325243// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 15244// CHECK5-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i165245// CHECK5-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP44]]5246// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 25247// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP44]]5248// CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 15249// CHECK5-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP44]]5250// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]5251// CHECK5: omp.body.continue:5252// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]5253// CHECK5: omp.inner.for.inc:5254// CHECK5-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP44]]5255// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 15256// CHECK5-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP44]]5257// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP45:![0-9]+]]5258// CHECK5: omp.inner.for.end:5259// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]5260// CHECK5: omp.loop.exit:5261// CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])5262// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 45263// CHECK5-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 05264// CHECK5-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]5265// CHECK5: .omp.final.then:5266// CHECK5-NEXT: store i64 11, ptr [[I]], align 85267// CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]5268// CHECK5: .omp.final.done:5269// CHECK5-NEXT: ret void5270//5271//5272// CHECK7-LABEL: define {{[^@]+}}@_Z7get_valv5273// CHECK7-SAME: () #[[ATTR0:[0-9]+]] {5274// CHECK7-NEXT: entry:5275// CHECK7-NEXT: ret i64 05276//5277//5278// CHECK7-LABEL: define {{[^@]+}}@_Z3fooi5279// CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {5280// CHECK7-NEXT: entry:5281// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 45282// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 45283// CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 25284// CHECK7-NEXT: [[B:%.*]] = alloca [10 x float], align 45285// CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 45286// CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 45287// CHECK7-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 85288// CHECK7-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 45289// CHECK7-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 45290// CHECK7-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 15291// CHECK7-NEXT: [[K:%.*]] = alloca i64, align 85292// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 45293// CHECK7-NEXT: [[LIN:%.*]] = alloca i32, align 45294// CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 45295// CHECK7-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 45296// CHECK7-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 45297// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 45298// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 45299// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 45300// CHECK7-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 85301// CHECK7-NEXT: [[A_CASTED3:%.*]] = alloca i32, align 45302// CHECK7-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 45303// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x ptr], align 45304// CHECK7-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x ptr], align 45305// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x ptr], align 45306// CHECK7-NEXT: [[KERNEL_ARGS8:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 85307// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 45308// CHECK7-NEXT: [[A_CASTED11:%.*]] = alloca i32, align 45309// CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 45310// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x ptr], align 45311// CHECK7-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x ptr], align 45312// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x ptr], align 45313// CHECK7-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 45314// CHECK7-NEXT: [[KERNEL_ARGS17:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 85315// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])5316// CHECK7-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 45317// CHECK7-NEXT: store i32 0, ptr [[A]], align 45318// CHECK7-NEXT: store i16 0, ptr [[AA]], align 25319// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 45320// CHECK7-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()5321// CHECK7-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 45322// CHECK7-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 45323// CHECK7-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 45324// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 45325// CHECK7-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]5326// CHECK7-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 85327// CHECK7-NEXT: store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 45328// CHECK7-NEXT: [[TMP5:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 20, i32 1, ptr @.omp_task_entry., i64 -1)5329// CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP5]], i32 0, i32 05330// CHECK7-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB2]], i32 [[TMP0]], ptr [[TMP5]])5331// CHECK7-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()5332// CHECK7-NEXT: store i64 [[CALL]], ptr [[K]], align 85333// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 45334// CHECK7-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 45335// CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 45336// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP9]], ptr [[K]]) #[[ATTR3:[0-9]+]]5337// CHECK7-NEXT: store i32 12, ptr [[LIN]], align 45338// CHECK7-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 25339// CHECK7-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 25340// CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[AA_CASTED]], align 45341// CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[LIN]], align 45342// CHECK7-NEXT: store i32 [[TMP12]], ptr [[LIN_CASTED]], align 45343// CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[LIN_CASTED]], align 45344// CHECK7-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 45345// CHECK7-NEXT: store i32 [[TMP14]], ptr [[A_CASTED2]], align 45346// CHECK7-NEXT: [[TMP15:%.*]] = load i32, ptr [[A_CASTED2]], align 45347// CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 05348// CHECK7-NEXT: store i32 [[TMP11]], ptr [[TMP16]], align 45349// CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 05350// CHECK7-NEXT: store i32 [[TMP11]], ptr [[TMP17]], align 45351// CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 05352// CHECK7-NEXT: store ptr null, ptr [[TMP18]], align 45353// CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 15354// CHECK7-NEXT: store i32 [[TMP13]], ptr [[TMP19]], align 45355// CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 15356// CHECK7-NEXT: store i32 [[TMP13]], ptr [[TMP20]], align 45357// CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 15358// CHECK7-NEXT: store ptr null, ptr [[TMP21]], align 45359// CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 25360// CHECK7-NEXT: store i32 [[TMP15]], ptr [[TMP22]], align 45361// CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 25362// CHECK7-NEXT: store i32 [[TMP15]], ptr [[TMP23]], align 45363// CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 25364// CHECK7-NEXT: store ptr null, ptr [[TMP24]], align 45365// CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 05366// CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 05367// CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 05368// CHECK7-NEXT: store i32 3, ptr [[TMP27]], align 45369// CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 15370// CHECK7-NEXT: store i32 3, ptr [[TMP28]], align 45371// CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 25372// CHECK7-NEXT: store ptr [[TMP25]], ptr [[TMP29]], align 45373// CHECK7-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 35374// CHECK7-NEXT: store ptr [[TMP26]], ptr [[TMP30]], align 45375// CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 45376// CHECK7-NEXT: store ptr @.offload_sizes, ptr [[TMP31]], align 45377// CHECK7-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 55378// CHECK7-NEXT: store ptr @.offload_maptypes, ptr [[TMP32]], align 45379// CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 65380// CHECK7-NEXT: store ptr null, ptr [[TMP33]], align 45381// CHECK7-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 75382// CHECK7-NEXT: store ptr null, ptr [[TMP34]], align 45383// CHECK7-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 85384// CHECK7-NEXT: store i64 0, ptr [[TMP35]], align 85385// CHECK7-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 95386// CHECK7-NEXT: store i64 0, ptr [[TMP36]], align 85387// CHECK7-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 105388// CHECK7-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP37]], align 45389// CHECK7-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 115390// CHECK7-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP38]], align 45391// CHECK7-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 125392// CHECK7-NEXT: store i32 0, ptr [[TMP39]], align 45393// CHECK7-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.region_id, ptr [[KERNEL_ARGS]])5394// CHECK7-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 05395// CHECK7-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]5396// CHECK7: omp_offload.failed:5397// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i32 [[TMP11]], i32 [[TMP13]], i32 [[TMP15]]) #[[ATTR3]]5398// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]]5399// CHECK7: omp_offload.cont:5400// CHECK7-NEXT: [[TMP42:%.*]] = load i32, ptr [[A]], align 45401// CHECK7-NEXT: store i32 [[TMP42]], ptr [[A_CASTED3]], align 45402// CHECK7-NEXT: [[TMP43:%.*]] = load i32, ptr [[A_CASTED3]], align 45403// CHECK7-NEXT: [[TMP44:%.*]] = load i16, ptr [[AA]], align 25404// CHECK7-NEXT: store i16 [[TMP44]], ptr [[AA_CASTED4]], align 25405// CHECK7-NEXT: [[TMP45:%.*]] = load i32, ptr [[AA_CASTED4]], align 45406// CHECK7-NEXT: [[TMP46:%.*]] = load i32, ptr [[N_ADDR]], align 45407// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP46]], 105408// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]5409// CHECK7: omp_if.then:5410// CHECK7-NEXT: [[TMP47:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 05411// CHECK7-NEXT: store i32 [[TMP43]], ptr [[TMP47]], align 45412// CHECK7-NEXT: [[TMP48:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 05413// CHECK7-NEXT: store i32 [[TMP43]], ptr [[TMP48]], align 45414// CHECK7-NEXT: [[TMP49:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 05415// CHECK7-NEXT: store ptr null, ptr [[TMP49]], align 45416// CHECK7-NEXT: [[TMP50:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 15417// CHECK7-NEXT: store i32 [[TMP45]], ptr [[TMP50]], align 45418// CHECK7-NEXT: [[TMP51:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 15419// CHECK7-NEXT: store i32 [[TMP45]], ptr [[TMP51]], align 45420// CHECK7-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 15421// CHECK7-NEXT: store ptr null, ptr [[TMP52]], align 45422// CHECK7-NEXT: [[TMP53:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 05423// CHECK7-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 05424// CHECK7-NEXT: [[TMP55:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 05425// CHECK7-NEXT: store i32 3, ptr [[TMP55]], align 45426// CHECK7-NEXT: [[TMP56:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 15427// CHECK7-NEXT: store i32 2, ptr [[TMP56]], align 45428// CHECK7-NEXT: [[TMP57:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 25429// CHECK7-NEXT: store ptr [[TMP53]], ptr [[TMP57]], align 45430// CHECK7-NEXT: [[TMP58:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 35431// CHECK7-NEXT: store ptr [[TMP54]], ptr [[TMP58]], align 45432// CHECK7-NEXT: [[TMP59:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 45433// CHECK7-NEXT: store ptr @.offload_sizes.1, ptr [[TMP59]], align 45434// CHECK7-NEXT: [[TMP60:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 55435// CHECK7-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP60]], align 45436// CHECK7-NEXT: [[TMP61:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 65437// CHECK7-NEXT: store ptr null, ptr [[TMP61]], align 45438// CHECK7-NEXT: [[TMP62:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 75439// CHECK7-NEXT: store ptr null, ptr [[TMP62]], align 45440// CHECK7-NEXT: [[TMP63:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 85441// CHECK7-NEXT: store i64 0, ptr [[TMP63]], align 85442// CHECK7-NEXT: [[TMP64:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 95443// CHECK7-NEXT: store i64 0, ptr [[TMP64]], align 85444// CHECK7-NEXT: [[TMP65:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 105445// CHECK7-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP65]], align 45446// CHECK7-NEXT: [[TMP66:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 115447// CHECK7-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP66]], align 45448// CHECK7-NEXT: [[TMP67:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 125449// CHECK7-NEXT: store i32 0, ptr [[TMP67]], align 45450// CHECK7-NEXT: [[TMP68:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.region_id, ptr [[KERNEL_ARGS8]])5451// CHECK7-NEXT: [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 05452// CHECK7-NEXT: br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]]5453// CHECK7: omp_offload.failed9:5454// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP43]], i32 [[TMP45]]) #[[ATTR3]]5455// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT10]]5456// CHECK7: omp_offload.cont10:5457// CHECK7-NEXT: br label [[OMP_IF_END:%.*]]5458// CHECK7: omp_if.else:5459// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP43]], i32 [[TMP45]]) #[[ATTR3]]5460// CHECK7-NEXT: br label [[OMP_IF_END]]5461// CHECK7: omp_if.end:5462// CHECK7-NEXT: [[TMP70:%.*]] = load i32, ptr [[A]], align 45463// CHECK7-NEXT: store i32 [[TMP70]], ptr [[DOTCAPTURE_EXPR_]], align 45464// CHECK7-NEXT: [[TMP71:%.*]] = load i32, ptr [[A]], align 45465// CHECK7-NEXT: store i32 [[TMP71]], ptr [[A_CASTED11]], align 45466// CHECK7-NEXT: [[TMP72:%.*]] = load i32, ptr [[A_CASTED11]], align 45467// CHECK7-NEXT: [[TMP73:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 45468// CHECK7-NEXT: store i32 [[TMP73]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 45469// CHECK7-NEXT: [[TMP74:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 45470// CHECK7-NEXT: [[TMP75:%.*]] = load i32, ptr [[N_ADDR]], align 45471// CHECK7-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP75]], 205472// CHECK7-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE20:%.*]]5473// CHECK7: omp_if.then13:5474// CHECK7-NEXT: [[TMP76:%.*]] = mul nuw i32 [[TMP1]], 45475// CHECK7-NEXT: [[TMP77:%.*]] = sext i32 [[TMP76]] to i645476// CHECK7-NEXT: [[TMP78:%.*]] = mul nuw i32 5, [[TMP3]]5477// CHECK7-NEXT: [[TMP79:%.*]] = mul nuw i32 [[TMP78]], 85478// CHECK7-NEXT: [[TMP80:%.*]] = sext i32 [[TMP79]] to i645479// CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.3, i32 80, i1 false)5480// CHECK7-NEXT: [[TMP81:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 05481// CHECK7-NEXT: store i32 [[TMP72]], ptr [[TMP81]], align 45482// CHECK7-NEXT: [[TMP82:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 05483// CHECK7-NEXT: store i32 [[TMP72]], ptr [[TMP82]], align 45484// CHECK7-NEXT: [[TMP83:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 05485// CHECK7-NEXT: store ptr null, ptr [[TMP83]], align 45486// CHECK7-NEXT: [[TMP84:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 15487// CHECK7-NEXT: store ptr [[B]], ptr [[TMP84]], align 45488// CHECK7-NEXT: [[TMP85:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 15489// CHECK7-NEXT: store ptr [[B]], ptr [[TMP85]], align 45490// CHECK7-NEXT: [[TMP86:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 15491// CHECK7-NEXT: store ptr null, ptr [[TMP86]], align 45492// CHECK7-NEXT: [[TMP87:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 25493// CHECK7-NEXT: store i32 [[TMP1]], ptr [[TMP87]], align 45494// CHECK7-NEXT: [[TMP88:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 25495// CHECK7-NEXT: store i32 [[TMP1]], ptr [[TMP88]], align 45496// CHECK7-NEXT: [[TMP89:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 25497// CHECK7-NEXT: store ptr null, ptr [[TMP89]], align 45498// CHECK7-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 35499// CHECK7-NEXT: store ptr [[VLA]], ptr [[TMP90]], align 45500// CHECK7-NEXT: [[TMP91:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 35501// CHECK7-NEXT: store ptr [[VLA]], ptr [[TMP91]], align 45502// CHECK7-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 35503// CHECK7-NEXT: store i64 [[TMP77]], ptr [[TMP92]], align 45504// CHECK7-NEXT: [[TMP93:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 35505// CHECK7-NEXT: store ptr null, ptr [[TMP93]], align 45506// CHECK7-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 45507// CHECK7-NEXT: store ptr [[C]], ptr [[TMP94]], align 45508// CHECK7-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 45509// CHECK7-NEXT: store ptr [[C]], ptr [[TMP95]], align 45510// CHECK7-NEXT: [[TMP96:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 45511// CHECK7-NEXT: store ptr null, ptr [[TMP96]], align 45512// CHECK7-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 55513// CHECK7-NEXT: store i32 5, ptr [[TMP97]], align 45514// CHECK7-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 55515// CHECK7-NEXT: store i32 5, ptr [[TMP98]], align 45516// CHECK7-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 55517// CHECK7-NEXT: store ptr null, ptr [[TMP99]], align 45518// CHECK7-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 65519// CHECK7-NEXT: store i32 [[TMP3]], ptr [[TMP100]], align 45520// CHECK7-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 65521// CHECK7-NEXT: store i32 [[TMP3]], ptr [[TMP101]], align 45522// CHECK7-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 65523// CHECK7-NEXT: store ptr null, ptr [[TMP102]], align 45524// CHECK7-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 75525// CHECK7-NEXT: store ptr [[VLA1]], ptr [[TMP103]], align 45526// CHECK7-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 75527// CHECK7-NEXT: store ptr [[VLA1]], ptr [[TMP104]], align 45528// CHECK7-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 75529// CHECK7-NEXT: store i64 [[TMP80]], ptr [[TMP105]], align 45530// CHECK7-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 75531// CHECK7-NEXT: store ptr null, ptr [[TMP106]], align 45532// CHECK7-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 85533// CHECK7-NEXT: store ptr [[D]], ptr [[TMP107]], align 45534// CHECK7-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 85535// CHECK7-NEXT: store ptr [[D]], ptr [[TMP108]], align 45536// CHECK7-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 85537// CHECK7-NEXT: store ptr null, ptr [[TMP109]], align 45538// CHECK7-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 95539// CHECK7-NEXT: store i32 [[TMP74]], ptr [[TMP110]], align 45540// CHECK7-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 95541// CHECK7-NEXT: store i32 [[TMP74]], ptr [[TMP111]], align 45542// CHECK7-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 95543// CHECK7-NEXT: store ptr null, ptr [[TMP112]], align 45544// CHECK7-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 05545// CHECK7-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 05546// CHECK7-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 05547// CHECK7-NEXT: [[TMP116:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 05548// CHECK7-NEXT: store i32 3, ptr [[TMP116]], align 45549// CHECK7-NEXT: [[TMP117:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 15550// CHECK7-NEXT: store i32 10, ptr [[TMP117]], align 45551// CHECK7-NEXT: [[TMP118:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 25552// CHECK7-NEXT: store ptr [[TMP113]], ptr [[TMP118]], align 45553// CHECK7-NEXT: [[TMP119:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 35554// CHECK7-NEXT: store ptr [[TMP114]], ptr [[TMP119]], align 45555// CHECK7-NEXT: [[TMP120:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 45556// CHECK7-NEXT: store ptr [[TMP115]], ptr [[TMP120]], align 45557// CHECK7-NEXT: [[TMP121:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 55558// CHECK7-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP121]], align 45559// CHECK7-NEXT: [[TMP122:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 65560// CHECK7-NEXT: store ptr null, ptr [[TMP122]], align 45561// CHECK7-NEXT: [[TMP123:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 75562// CHECK7-NEXT: store ptr null, ptr [[TMP123]], align 45563// CHECK7-NEXT: [[TMP124:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 85564// CHECK7-NEXT: store i64 0, ptr [[TMP124]], align 85565// CHECK7-NEXT: [[TMP125:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 95566// CHECK7-NEXT: store i64 0, ptr [[TMP125]], align 85567// CHECK7-NEXT: [[TMP126:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 105568// CHECK7-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP126]], align 45569// CHECK7-NEXT: [[TMP127:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 115570// CHECK7-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP127]], align 45571// CHECK7-NEXT: [[TMP128:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 125572// CHECK7-NEXT: store i32 0, ptr [[TMP128]], align 45573// CHECK7-NEXT: [[TMP129:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.region_id, ptr [[KERNEL_ARGS17]])5574// CHECK7-NEXT: [[TMP130:%.*]] = icmp ne i32 [[TMP129]], 05575// CHECK7-NEXT: br i1 [[TMP130]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]]5576// CHECK7: omp_offload.failed18:5577// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP72]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP74]]) #[[ATTR3]]5578// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT19]]5579// CHECK7: omp_offload.cont19:5580// CHECK7-NEXT: br label [[OMP_IF_END21:%.*]]5581// CHECK7: omp_if.else20:5582// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP72]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP74]]) #[[ATTR3]]5583// CHECK7-NEXT: br label [[OMP_IF_END21]]5584// CHECK7: omp_if.end21:5585// CHECK7-NEXT: [[TMP131:%.*]] = load i32, ptr [[A]], align 45586// CHECK7-NEXT: [[TMP132:%.*]] = load ptr, ptr [[SAVED_STACK]], align 45587// CHECK7-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP132]])5588// CHECK7-NEXT: ret i32 [[TMP131]]5589//5590//5591// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l965592// CHECK7-SAME: () #[[ATTR2:[0-9]+]] {5593// CHECK7-NEXT: entry:5594// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined)5595// CHECK7-NEXT: ret void5596//5597//5598// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined5599// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] {5600// CHECK7-NEXT: entry:5601// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 45602// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 45603// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 45604// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 45605// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 45606// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 45607// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 45608// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 45609// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 45610// CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 45611// CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 45612// CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 45613// CHECK7-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 45614// CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 45615// CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 45616// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 45617// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 45618// CHECK7-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)5619// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 45620// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 55621// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]5622// CHECK7: cond.true:5623// CHECK7-NEXT: br label [[COND_END:%.*]]5624// CHECK7: cond.false:5625// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 45626// CHECK7-NEXT: br label [[COND_END]]5627// CHECK7: cond.end:5628// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]5629// CHECK7-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 45630// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 45631// CHECK7-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 45632// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]5633// CHECK7: omp.inner.for.cond:5634// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]]5635// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]]5636// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]5637// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]5638// CHECK7: omp.inner.for.body:5639// CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]5640// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 55641// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]5642// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]]5643// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]5644// CHECK7: omp.body.continue:5645// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]5646// CHECK7: omp.inner.for.inc:5647// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]5648// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 15649// CHECK7-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]5650// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]5651// CHECK7: omp.inner.for.end:5652// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]5653// CHECK7: omp.loop.exit:5654// CHECK7-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])5655// CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 45656// CHECK7-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 05657// CHECK7-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]5658// CHECK7: .omp.final.then:5659// CHECK7-NEXT: store i32 33, ptr [[I]], align 45660// CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]]5661// CHECK7: .omp.final.done:5662// CHECK7-NEXT: ret void5663//5664//5665// CHECK7-LABEL: define {{[^@]+}}@.omp_task_entry.5666// CHECK7-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] {5667// CHECK7-NEXT: entry:5668// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 45669// CHECK7-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 45670// CHECK7-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 45671// CHECK7-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 45672// CHECK7-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 45673// CHECK7-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 45674// CHECK7-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 85675// CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i32, align 45676// CHECK7-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 45677// CHECK7-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 45678// CHECK7-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 45679// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 45680// CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 45681// CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 05682// CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 25683// CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 05684// CHECK7-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 45685// CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])5686// CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])5687// CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])5688// CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]])5689// CHECK7-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META26:![0-9]+]]5690// CHECK7-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 4, !noalias [[META26]]5691// CHECK7-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias [[META26]]5692// CHECK7-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias [[META26]]5693// CHECK7-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 4, !noalias [[META26]]5694// CHECK7-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 4, !noalias [[META26]]5695// CHECK7-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias [[META26]]5696// CHECK7-NEXT: store i32 3, ptr [[KERNEL_ARGS_I]], align 4, !noalias [[META26]]5697// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 15698// CHECK7-NEXT: store i32 0, ptr [[TMP9]], align 4, !noalias [[META26]]5699// CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 25700// CHECK7-NEXT: store ptr null, ptr [[TMP10]], align 4, !noalias [[META26]]5701// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 35702// CHECK7-NEXT: store ptr null, ptr [[TMP11]], align 4, !noalias [[META26]]5703// CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 45704// CHECK7-NEXT: store ptr null, ptr [[TMP12]], align 4, !noalias [[META26]]5705// CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 55706// CHECK7-NEXT: store ptr null, ptr [[TMP13]], align 4, !noalias [[META26]]5707// CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 65708// CHECK7-NEXT: store ptr null, ptr [[TMP14]], align 4, !noalias [[META26]]5709// CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 75710// CHECK7-NEXT: store ptr null, ptr [[TMP15]], align 4, !noalias [[META26]]5711// CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 85712// CHECK7-NEXT: store i64 0, ptr [[TMP16]], align 8, !noalias [[META26]]5713// CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 95714// CHECK7-NEXT: store i64 1, ptr [[TMP17]], align 8, !noalias [[META26]]5715// CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 105716// CHECK7-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP18]], align 4, !noalias [[META26]]5717// CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 115718// CHECK7-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP19]], align 4, !noalias [[META26]]5719// CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 125720// CHECK7-NEXT: store i32 0, ptr [[TMP20]], align 4, !noalias [[META26]]5721// CHECK7-NEXT: [[TMP21:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, ptr [[KERNEL_ARGS_I]])5722// CHECK7-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 05723// CHECK7-NEXT: br i1 [[TMP22]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]]5724// CHECK7: omp_offload.failed.i:5725// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR3]]5726// CHECK7-NEXT: br label [[DOTOMP_OUTLINED__EXIT]]5727// CHECK7: .omp_outlined..exit:5728// CHECK7-NEXT: ret i32 05729//5730//5731// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1015732// CHECK7-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR2]] {5733// CHECK7-NEXT: entry:5734// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 45735// CHECK7-NEXT: [[K_ADDR:%.*]] = alloca ptr, align 45736// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 45737// CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 45738// CHECK7-NEXT: store ptr [[K]], ptr [[K_ADDR]], align 45739// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[K_ADDR]], align 45740// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 45741// CHECK7-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 45742// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 45743// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined, i32 [[TMP2]], ptr [[TMP0]])5744// CHECK7-NEXT: ret void5745//5746//5747// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined5748// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR2]] {5749// CHECK7-NEXT: entry:5750// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 45751// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 45752// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 45753// CHECK7-NEXT: [[K_ADDR:%.*]] = alloca ptr, align 45754// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 45755// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 45756// CHECK7-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 85757// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 45758// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 45759// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 45760// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 45761// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 45762// CHECK7-NEXT: [[K1:%.*]] = alloca i64, align 85763// CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 45764// CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 45765// CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 45766// CHECK7-NEXT: store ptr [[K]], ptr [[K_ADDR]], align 45767// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[K_ADDR]], align 45768// CHECK7-NEXT: [[TMP1:%.*]] = load i64, ptr [[TMP0]], align 85769// CHECK7-NEXT: store i64 [[TMP1]], ptr [[DOTLINEAR_START]], align 85770// CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 45771// CHECK7-NEXT: store i32 8, ptr [[DOTOMP_UB]], align 45772// CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 45773// CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 45774// CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 45775// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 45776// CHECK7-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP3]])5777// CHECK7-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 1073741859, i32 0, i32 8, i32 1, i32 1)5778// CHECK7-NEXT: br label [[OMP_DISPATCH_COND:%.*]]5779// CHECK7: omp.dispatch.cond:5780// CHECK7-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB2]], i32 [[TMP3]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])5781// CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 05782// CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]5783// CHECK7: omp.dispatch.body:5784// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 45785// CHECK7-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 45786// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]5787// CHECK7: omp.inner.for.cond:5788// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27:![0-9]+]]5789// CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP27]]5790// CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]5791// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]5792// CHECK7: omp.inner.for.body:5793// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]]5794// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 15795// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]5796// CHECK7-NEXT: store i32 [[SUB]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP27]]5797// CHECK7-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP27]]5798// CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]]5799// CHECK7-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 35800// CHECK7-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i645801// CHECK7-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]]5802// CHECK7-NEXT: store i64 [[ADD]], ptr [[K1]], align 8, !llvm.access.group [[ACC_GRP27]]5803// CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP27]]5804// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 15805// CHECK7-NEXT: store i32 [[ADD3]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP27]]5806// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]5807// CHECK7: omp.body.continue:5808// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]5809// CHECK7: omp.inner.for.inc:5810// CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]]5811// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 15812// CHECK7-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]]5813// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]5814// CHECK7: omp.inner.for.end:5815// CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]]5816// CHECK7: omp.dispatch.inc:5817// CHECK7-NEXT: br label [[OMP_DISPATCH_COND]]5818// CHECK7: omp.dispatch.end:5819// CHECK7-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB2]], i32 [[TMP3]])5820// CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 45821// CHECK7-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 05822// CHECK7-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]5823// CHECK7: .omp.final.then:5824// CHECK7-NEXT: store i32 1, ptr [[I]], align 45825// CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]]5826// CHECK7: .omp.final.done:5827// CHECK7-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 45828// CHECK7-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 05829// CHECK7-NEXT: br i1 [[TMP16]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]5830// CHECK7: .omp.linear.pu:5831// CHECK7-NEXT: [[TMP17:%.*]] = load i64, ptr [[K1]], align 85832// CHECK7-NEXT: store i64 [[TMP17]], ptr [[TMP0]], align 85833// CHECK7-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]5834// CHECK7: .omp.linear.pu.done:5835// CHECK7-NEXT: ret void5836//5837//5838// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1085839// CHECK7-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] {5840// CHECK7-NEXT: entry:5841// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 45842// CHECK7-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 45843// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 45844// CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 45845// CHECK7-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 45846// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 45847// CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 45848// CHECK7-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 45849// CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 45850// CHECK7-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 25851// CHECK7-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 25852// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 45853// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 45854// CHECK7-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 45855// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[LIN_CASTED]], align 45856// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 45857// CHECK7-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 45858// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[A_CASTED]], align 45859// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined, i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])5860// CHECK7-NEXT: ret void5861//5862//5863// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined5864// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] {5865// CHECK7-NEXT: entry:5866// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 45867// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 45868// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 45869// CHECK7-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 45870// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 45871// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 85872// CHECK7-NEXT: [[TMP:%.*]] = alloca i64, align 45873// CHECK7-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 45874// CHECK7-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 45875// CHECK7-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 85876// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 85877// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 85878// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 85879// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 45880// CHECK7-NEXT: [[IT:%.*]] = alloca i64, align 85881// CHECK7-NEXT: [[LIN2:%.*]] = alloca i32, align 45882// CHECK7-NEXT: [[A3:%.*]] = alloca i32, align 45883// CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 45884// CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 45885// CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 45886// CHECK7-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 45887// CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 45888// CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 45889// CHECK7-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 45890// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 45891// CHECK7-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 45892// CHECK7-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()5893// CHECK7-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 85894// CHECK7-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 85895// CHECK7-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 85896// CHECK7-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 85897// CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 45898// CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 45899// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 45900// CHECK7-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP3]])5901// CHECK7-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)5902// CHECK7-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 85903// CHECK7-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 35904// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]5905// CHECK7: cond.true:5906// CHECK7-NEXT: br label [[COND_END:%.*]]5907// CHECK7: cond.false:5908// CHECK7-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 85909// CHECK7-NEXT: br label [[COND_END]]5910// CHECK7: cond.end:5911// CHECK7-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]5912// CHECK7-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 85913// CHECK7-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 85914// CHECK7-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 85915// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]5916// CHECK7: omp.inner.for.cond:5917// CHECK7-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30:![0-9]+]]5918// CHECK7-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP30]]5919// CHECK7-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]5920// CHECK7-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]5921// CHECK7: omp.inner.for.body:5922// CHECK7-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]]5923// CHECK7-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 4005924// CHECK7-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]5925// CHECK7-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP30]]5926// CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP30]]5927// CHECK7-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i645928// CHECK7-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]]5929// CHECK7-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP30]]5930// CHECK7-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]]5931// CHECK7-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]]5932// CHECK7-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i325933// CHECK7-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 4, !llvm.access.group [[ACC_GRP30]]5934// CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4, !llvm.access.group [[ACC_GRP30]]5935// CHECK7-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i645936// CHECK7-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]]5937// CHECK7-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP30]]5938// CHECK7-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]]5939// CHECK7-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]]5940// CHECK7-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i325941// CHECK7-NEXT: store i32 [[CONV10]], ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP30]]5942// CHECK7-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP30]]5943// CHECK7-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i325944// CHECK7-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 15945// CHECK7-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i165946// CHECK7-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP30]]5947// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]5948// CHECK7: omp.body.continue:5949// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]5950// CHECK7: omp.inner.for.inc:5951// CHECK7-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]]5952// CHECK7-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 15953// CHECK7-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]]5954// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]5955// CHECK7: omp.inner.for.end:5956// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]5957// CHECK7: omp.loop.exit:5958// CHECK7-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]])5959// CHECK7-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 45960// CHECK7-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 05961// CHECK7-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]5962// CHECK7: .omp.final.then:5963// CHECK7-NEXT: store i64 400, ptr [[IT]], align 85964// CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]]5965// CHECK7: .omp.final.done:5966// CHECK7-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 45967// CHECK7-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 05968// CHECK7-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]5969// CHECK7: .omp.linear.pu:5970// CHECK7-NEXT: [[TMP22:%.*]] = load i32, ptr [[LIN2]], align 45971// CHECK7-NEXT: store i32 [[TMP22]], ptr [[LIN_ADDR]], align 45972// CHECK7-NEXT: [[TMP23:%.*]] = load i32, ptr [[A3]], align 45973// CHECK7-NEXT: store i32 [[TMP23]], ptr [[A_ADDR]], align 45974// CHECK7-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]5975// CHECK7: .omp.linear.pu.done:5976// CHECK7-NEXT: ret void5977//5978//5979// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1165980// CHECK7-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {5981// CHECK7-NEXT: entry:5982// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 45983// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 45984// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 45985// CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 45986// CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 45987// CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 45988// CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 45989// CHECK7-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 45990// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 45991// CHECK7-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 25992// CHECK7-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 25993// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 45994// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined, i32 [[TMP1]], i32 [[TMP3]])5995// CHECK7-NEXT: ret void5996//5997//5998// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined5999// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {6000// CHECK7-NEXT: entry:6001// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 46002// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 46003// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 46004// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 46005// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 46006// CHECK7-NEXT: [[TMP:%.*]] = alloca i16, align 26007// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 46008// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 46009// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 46010// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 46011// CHECK7-NEXT: [[IT:%.*]] = alloca i16, align 26012// CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 46013// CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 46014// CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 46015// CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 46016// CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 46017// CHECK7-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 46018// CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 46019// CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 46020// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 46021// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 46022// CHECK7-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)6023// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 46024// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 36025// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]6026// CHECK7: cond.true:6027// CHECK7-NEXT: br label [[COND_END:%.*]]6028// CHECK7: cond.false:6029// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 46030// CHECK7-NEXT: br label [[COND_END]]6031// CHECK7: cond.end:6032// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]6033// CHECK7-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 46034// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 46035// CHECK7-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 46036// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]6037// CHECK7: omp.inner.for.cond:6038// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33:![0-9]+]]6039// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP33]]6040// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]6041// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]6042// CHECK7: omp.inner.for.body:6043// CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]]6044// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 46045// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]6046// CHECK7-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i166047// CHECK7-NEXT: store i16 [[CONV]], ptr [[IT]], align 2, !llvm.access.group [[ACC_GRP33]]6048// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]]6049// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 16050// CHECK7-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]]6051// CHECK7-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP33]]6052// CHECK7-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i326053// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 16054// CHECK7-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i166055// CHECK7-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP33]]6056// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]6057// CHECK7: omp.body.continue:6058// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]6059// CHECK7: omp.inner.for.inc:6060// CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]]6061// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 16062// CHECK7-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]]6063// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]6064// CHECK7: omp.inner.for.end:6065// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]6066// CHECK7: omp.loop.exit:6067// CHECK7-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])6068// CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 46069// CHECK7-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 06070// CHECK7-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]6071// CHECK7: .omp.final.then:6072// CHECK7-NEXT: store i16 22, ptr [[IT]], align 26073// CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]]6074// CHECK7: .omp.final.done:6075// CHECK7-NEXT: ret void6076//6077//6078// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1406079// CHECK7-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {6080// CHECK7-NEXT: entry:6081// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 46082// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 46083// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 46084// CHECK7-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 46085// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 46086// CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 46087// CHECK7-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 46088// CHECK7-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 46089// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 46090// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 46091// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 46092// CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 46093// CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 46094// CHECK7-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 46095// CHECK7-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 46096// CHECK7-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 46097// CHECK7-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 46098// CHECK7-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 46099// CHECK7-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 46100// CHECK7-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 46101// CHECK7-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 46102// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 46103// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 46104// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 46105// CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 46106// CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 46107// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 46108// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 46109// CHECK7-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 46110// CHECK7-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 46111// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 46112// CHECK7-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 46113// CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 46114// CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 46115// CHECK7-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 46116// CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 46117// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i32 [[TMP11]])6118// CHECK7-NEXT: ret void6119//6120//6121// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined6122// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {6123// CHECK7-NEXT: entry:6124// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 46125// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 46126// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 46127// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 46128// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 46129// CHECK7-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 46130// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 46131// CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 46132// CHECK7-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 46133// CHECK7-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 46134// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 46135// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 46136// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 46137// CHECK7-NEXT: [[TMP:%.*]] = alloca i8, align 16138// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 46139// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 46140// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 46141// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 46142// CHECK7-NEXT: [[IT:%.*]] = alloca i8, align 16143// CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 46144// CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 46145// CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 46146// CHECK7-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 46147// CHECK7-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 46148// CHECK7-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 46149// CHECK7-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 46150// CHECK7-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 46151// CHECK7-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 46152// CHECK7-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 46153// CHECK7-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 46154// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 46155// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 46156// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 46157// CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 46158// CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 46159// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 46160// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 46161// CHECK7-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 46162// CHECK7-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 46163// CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 46164// CHECK7-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 46165// CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 46166// CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 46167// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 46168// CHECK7-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 46169// CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 46170// CHECK7-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])6171// CHECK7-NEXT: br label [[OMP_DISPATCH_COND:%.*]]6172// CHECK7: omp.dispatch.cond:6173// CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 46174// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 256175// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]6176// CHECK7: cond.true:6177// CHECK7-NEXT: br label [[COND_END:%.*]]6178// CHECK7: cond.false:6179// CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 46180// CHECK7-NEXT: br label [[COND_END]]6181// CHECK7: cond.end:6182// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]6183// CHECK7-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 46184// CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 46185// CHECK7-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 46186// CHECK7-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 46187// CHECK7-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 46188// CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]6189// CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]6190// CHECK7: omp.dispatch.body:6191// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]6192// CHECK7: omp.inner.for.cond:6193// CHECK7-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36:![0-9]+]]6194// CHECK7-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP36]]6195// CHECK7-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]6196// CHECK7-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]6197// CHECK7: omp.inner.for.body:6198// CHECK7-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]]6199// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 16200// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]6201// CHECK7-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i86202// CHECK7-NEXT: store i8 [[CONV]], ptr [[IT]], align 1, !llvm.access.group [[ACC_GRP36]]6203// CHECK7-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]]6204// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 16205// CHECK7-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]]6206// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 26207// CHECK7-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP36]]6208// CHECK7-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double6209// CHECK7-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+006210// CHECK7-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float6211// CHECK7-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP36]]6212// CHECK7-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 36213// CHECK7-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP36]]6214// CHECK7-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double6215// CHECK7-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+006216// CHECK7-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float6217// CHECK7-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP36]]6218// CHECK7-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 16219// CHECK7-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i32 0, i32 26220// CHECK7-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP36]]6221// CHECK7-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+006222// CHECK7-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP36]]6223// CHECK7-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]6224// CHECK7-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP23]]6225// CHECK7-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i32 36226// CHECK7-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP36]]6227// CHECK7-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+006228// CHECK7-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP36]]6229// CHECK7-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 06230// CHECK7-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP36]]6231// CHECK7-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 16232// CHECK7-NEXT: store i64 [[ADD20]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP36]]6233// CHECK7-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 16234// CHECK7-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP36]]6235// CHECK7-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i326236// CHECK7-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 16237// CHECK7-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i86238// CHECK7-NEXT: store i8 [[CONV23]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP36]]6239// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]6240// CHECK7: omp.body.continue:6241// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]6242// CHECK7: omp.inner.for.inc:6243// CHECK7-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]]6244// CHECK7-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 16245// CHECK7-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]]6246// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]]6247// CHECK7: omp.inner.for.end:6248// CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]]6249// CHECK7: omp.dispatch.inc:6250// CHECK7-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 46251// CHECK7-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 46252// CHECK7-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]6253// CHECK7-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 46254// CHECK7-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 46255// CHECK7-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 46256// CHECK7-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]6257// CHECK7-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 46258// CHECK7-NEXT: br label [[OMP_DISPATCH_COND]]6259// CHECK7: omp.dispatch.end:6260// CHECK7-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]])6261// CHECK7-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 46262// CHECK7-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 06263// CHECK7-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]6264// CHECK7: .omp.final.then:6265// CHECK7-NEXT: store i8 96, ptr [[IT]], align 16266// CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]]6267// CHECK7: .omp.final.done:6268// CHECK7-NEXT: ret void6269//6270//6271// CHECK7-LABEL: define {{[^@]+}}@_Z3bari6272// CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {6273// CHECK7-NEXT: entry:6274// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 46275// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 46276// CHECK7-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 46277// CHECK7-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 46278// CHECK7-NEXT: store i32 0, ptr [[A]], align 46279// CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 46280// CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]])6281// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 46282// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]6283// CHECK7-NEXT: store i32 [[ADD]], ptr [[A]], align 46284// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 46285// CHECK7-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]])6286// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 46287// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]6288// CHECK7-NEXT: store i32 [[ADD2]], ptr [[A]], align 46289// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 46290// CHECK7-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]])6291// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 46292// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]6293// CHECK7-NEXT: store i32 [[ADD4]], ptr [[A]], align 46294// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 46295// CHECK7-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]])6296// CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 46297// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]6298// CHECK7-NEXT: store i32 [[ADD6]], ptr [[A]], align 46299// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 46300// CHECK7-NEXT: ret i32 [[TMP8]]6301//6302//6303// CHECK7-LABEL: define {{[^@]+}}@_ZN2S12r1Ei6304// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {6305// CHECK7-NEXT: entry:6306// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 46307// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 46308// CHECK7-NEXT: [[B:%.*]] = alloca i32, align 46309// CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 46310// CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 46311// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 16312// CHECK7-NEXT: [[B_CASTED:%.*]] = alloca i32, align 46313// CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 46314// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [6 x ptr], align 46315// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [6 x ptr], align 46316// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [6 x ptr], align 46317// CHECK7-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [6 x i64], align 46318// CHECK7-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 86319// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 46320// CHECK7-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 46321// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 46322// CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 46323// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 16324// CHECK7-NEXT: store i32 [[ADD]], ptr [[B]], align 46325// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 46326// CHECK7-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()6327// CHECK7-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 46328// CHECK7-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]6329// CHECK7-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 26330// CHECK7-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 46331// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 46332// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 606333// CHECK7-NEXT: [[STOREDV:%.*]] = zext i1 [[CMP]] to i86334// CHECK7-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_]], align 16335// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 46336// CHECK7-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 46337// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[B_CASTED]], align 46338// CHECK7-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 16339// CHECK7-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP7]] to i16340// CHECK7-NEXT: [[STOREDV2:%.*]] = zext i1 [[LOADEDV]] to i86341// CHECK7-NEXT: store i8 [[STOREDV2]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 16342// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 46343// CHECK7-NEXT: [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 16344// CHECK7-NEXT: [[LOADEDV3:%.*]] = trunc i8 [[TMP9]] to i16345// CHECK7-NEXT: br i1 [[LOADEDV3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]6346// CHECK7: omp_if.then:6347// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 06348// CHECK7-NEXT: [[TMP10:%.*]] = mul nuw i32 2, [[TMP1]]6349// CHECK7-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP10]], 26350// CHECK7-NEXT: [[TMP12:%.*]] = sext i32 [[TMP11]] to i646351// CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.5, i32 48, i1 false)6352// CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 06353// CHECK7-NEXT: store ptr [[THIS1]], ptr [[TMP13]], align 46354// CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 06355// CHECK7-NEXT: store ptr [[A]], ptr [[TMP14]], align 46356// CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 06357// CHECK7-NEXT: store ptr null, ptr [[TMP15]], align 46358// CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 16359// CHECK7-NEXT: store i32 [[TMP6]], ptr [[TMP16]], align 46360// CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 16361// CHECK7-NEXT: store i32 [[TMP6]], ptr [[TMP17]], align 46362// CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 16363// CHECK7-NEXT: store ptr null, ptr [[TMP18]], align 46364// CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 26365// CHECK7-NEXT: store i32 2, ptr [[TMP19]], align 46366// CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 26367// CHECK7-NEXT: store i32 2, ptr [[TMP20]], align 46368// CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 26369// CHECK7-NEXT: store ptr null, ptr [[TMP21]], align 46370// CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 36371// CHECK7-NEXT: store i32 [[TMP1]], ptr [[TMP22]], align 46372// CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 36373// CHECK7-NEXT: store i32 [[TMP1]], ptr [[TMP23]], align 46374// CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 36375// CHECK7-NEXT: store ptr null, ptr [[TMP24]], align 46376// CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 46377// CHECK7-NEXT: store ptr [[VLA]], ptr [[TMP25]], align 46378// CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 46379// CHECK7-NEXT: store ptr [[VLA]], ptr [[TMP26]], align 46380// CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [6 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 46381// CHECK7-NEXT: store i64 [[TMP12]], ptr [[TMP27]], align 46382// CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 46383// CHECK7-NEXT: store ptr null, ptr [[TMP28]], align 46384// CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 56385// CHECK7-NEXT: store i32 [[TMP8]], ptr [[TMP29]], align 46386// CHECK7-NEXT: [[TMP30:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 56387// CHECK7-NEXT: store i32 [[TMP8]], ptr [[TMP30]], align 46388// CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 56389// CHECK7-NEXT: store ptr null, ptr [[TMP31]], align 46390// CHECK7-NEXT: [[TMP32:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 06391// CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 06392// CHECK7-NEXT: [[TMP34:%.*]] = getelementptr inbounds [6 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 06393// CHECK7-NEXT: [[TMP35:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 16394// CHECK7-NEXT: [[LOADEDV4:%.*]] = trunc i8 [[TMP35]] to i16395// CHECK7-NEXT: [[TMP36:%.*]] = select i1 [[LOADEDV4]], i32 0, i32 16396// CHECK7-NEXT: [[TMP37:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP36]], 06397// CHECK7-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 06398// CHECK7-NEXT: store i32 3, ptr [[TMP38]], align 46399// CHECK7-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 16400// CHECK7-NEXT: store i32 6, ptr [[TMP39]], align 46401// CHECK7-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 26402// CHECK7-NEXT: store ptr [[TMP32]], ptr [[TMP40]], align 46403// CHECK7-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 36404// CHECK7-NEXT: store ptr [[TMP33]], ptr [[TMP41]], align 46405// CHECK7-NEXT: [[TMP42:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 46406// CHECK7-NEXT: store ptr [[TMP34]], ptr [[TMP42]], align 46407// CHECK7-NEXT: [[TMP43:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 56408// CHECK7-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP43]], align 46409// CHECK7-NEXT: [[TMP44:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 66410// CHECK7-NEXT: store ptr null, ptr [[TMP44]], align 46411// CHECK7-NEXT: [[TMP45:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 76412// CHECK7-NEXT: store ptr null, ptr [[TMP45]], align 46413// CHECK7-NEXT: [[TMP46:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 86414// CHECK7-NEXT: store i64 0, ptr [[TMP46]], align 86415// CHECK7-NEXT: [[TMP47:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 96416// CHECK7-NEXT: store i64 0, ptr [[TMP47]], align 86417// CHECK7-NEXT: [[TMP48:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 106418// CHECK7-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP48]], align 46419// CHECK7-NEXT: [[TMP49:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 116420// CHECK7-NEXT: store [3 x i32] [[TMP37]], ptr [[TMP49]], align 46421// CHECK7-NEXT: [[TMP50:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 126422// CHECK7-NEXT: store i32 0, ptr [[TMP50]], align 46423// CHECK7-NEXT: [[TMP51:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 [[TMP36]], ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.region_id, ptr [[KERNEL_ARGS]])6424// CHECK7-NEXT: [[TMP52:%.*]] = icmp ne i32 [[TMP51]], 06425// CHECK7-NEXT: br i1 [[TMP52]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]6426// CHECK7: omp_offload.failed:6427// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(ptr [[THIS1]], i32 [[TMP6]], i32 2, i32 [[TMP1]], ptr [[VLA]], i32 [[TMP8]]) #[[ATTR3]]6428// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]]6429// CHECK7: omp_offload.cont:6430// CHECK7-NEXT: br label [[OMP_IF_END:%.*]]6431// CHECK7: omp_if.else:6432// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(ptr [[THIS1]], i32 [[TMP6]], i32 2, i32 [[TMP1]], ptr [[VLA]], i32 [[TMP8]]) #[[ATTR3]]6433// CHECK7-NEXT: br label [[OMP_IF_END]]6434// CHECK7: omp_if.end:6435// CHECK7-NEXT: [[TMP53:%.*]] = mul nsw i32 1, [[TMP1]]6436// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP53]]6437// CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 16438// CHECK7-NEXT: [[TMP54:%.*]] = load i16, ptr [[ARRAYIDX5]], align 26439// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP54]] to i326440// CHECK7-NEXT: [[TMP55:%.*]] = load i32, ptr [[B]], align 46441// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV]], [[TMP55]]6442// CHECK7-NEXT: [[TMP56:%.*]] = load ptr, ptr [[SAVED_STACK]], align 46443// CHECK7-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP56]])6444// CHECK7-NEXT: ret i32 [[ADD6]]6445//6446//6447// CHECK7-LABEL: define {{[^@]+}}@_ZL7fstatici6448// CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {6449// CHECK7-NEXT: entry:6450// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 46451// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 46452// CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 26453// CHECK7-NEXT: [[AAA:%.*]] = alloca i8, align 16454// CHECK7-NEXT: [[B:%.*]] = alloca [10 x i32], align 46455// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 46456// CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 46457// CHECK7-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 46458// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 46459// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 46460// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 46461// CHECK7-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 86462// CHECK7-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 46463// CHECK7-NEXT: store i32 0, ptr [[A]], align 46464// CHECK7-NEXT: store i16 0, ptr [[AA]], align 26465// CHECK7-NEXT: store i8 0, ptr [[AAA]], align 16466// CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 46467// CHECK7-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 46468// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 46469// CHECK7-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 26470// CHECK7-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 26471// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 46472// CHECK7-NEXT: [[TMP4:%.*]] = load i8, ptr [[AAA]], align 16473// CHECK7-NEXT: store i8 [[TMP4]], ptr [[AAA_CASTED]], align 16474// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[AAA_CASTED]], align 46475// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 46476// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 506477// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]6478// CHECK7: omp_if.then:6479// CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 06480// CHECK7-NEXT: store i32 [[TMP1]], ptr [[TMP7]], align 46481// CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 06482// CHECK7-NEXT: store i32 [[TMP1]], ptr [[TMP8]], align 46483// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 06484// CHECK7-NEXT: store ptr null, ptr [[TMP9]], align 46485// CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 16486// CHECK7-NEXT: store i32 [[TMP3]], ptr [[TMP10]], align 46487// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 16488// CHECK7-NEXT: store i32 [[TMP3]], ptr [[TMP11]], align 46489// CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 16490// CHECK7-NEXT: store ptr null, ptr [[TMP12]], align 46491// CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 26492// CHECK7-NEXT: store i32 [[TMP5]], ptr [[TMP13]], align 46493// CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 26494// CHECK7-NEXT: store i32 [[TMP5]], ptr [[TMP14]], align 46495// CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 26496// CHECK7-NEXT: store ptr null, ptr [[TMP15]], align 46497// CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 36498// CHECK7-NEXT: store ptr [[B]], ptr [[TMP16]], align 46499// CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 36500// CHECK7-NEXT: store ptr [[B]], ptr [[TMP17]], align 46501// CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 36502// CHECK7-NEXT: store ptr null, ptr [[TMP18]], align 46503// CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 06504// CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 06505// CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 06506// CHECK7-NEXT: store i32 3, ptr [[TMP21]], align 46507// CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 16508// CHECK7-NEXT: store i32 4, ptr [[TMP22]], align 46509// CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 26510// CHECK7-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 46511// CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 36512// CHECK7-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 46513// CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 46514// CHECK7-NEXT: store ptr @.offload_sizes.7, ptr [[TMP25]], align 46515// CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 56516// CHECK7-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP26]], align 46517// CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 66518// CHECK7-NEXT: store ptr null, ptr [[TMP27]], align 46519// CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 76520// CHECK7-NEXT: store ptr null, ptr [[TMP28]], align 46521// CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 86522// CHECK7-NEXT: store i64 0, ptr [[TMP29]], align 86523// CHECK7-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 96524// CHECK7-NEXT: store i64 0, ptr [[TMP30]], align 86525// CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 106526// CHECK7-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP31]], align 46527// CHECK7-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 116528// CHECK7-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP32]], align 46529// CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 126530// CHECK7-NEXT: store i32 0, ptr [[TMP33]], align 46531// CHECK7-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.region_id, ptr [[KERNEL_ARGS]])6532// CHECK7-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 06533// CHECK7-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]6534// CHECK7: omp_offload.failed:6535// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR3]]6536// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]]6537// CHECK7: omp_offload.cont:6538// CHECK7-NEXT: br label [[OMP_IF_END:%.*]]6539// CHECK7: omp_if.else:6540// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR3]]6541// CHECK7-NEXT: br label [[OMP_IF_END]]6542// CHECK7: omp_if.end:6543// CHECK7-NEXT: [[TMP36:%.*]] = load i32, ptr [[A]], align 46544// CHECK7-NEXT: ret i32 [[TMP36]]6545//6546//6547// CHECK7-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i6548// CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {6549// CHECK7-NEXT: entry:6550// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 46551// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 46552// CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 26553// CHECK7-NEXT: [[B:%.*]] = alloca [10 x i32], align 46554// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 46555// CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 46556// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 46557// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 46558// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 46559// CHECK7-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 86560// CHECK7-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 46561// CHECK7-NEXT: store i32 0, ptr [[A]], align 46562// CHECK7-NEXT: store i16 0, ptr [[AA]], align 26563// CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 46564// CHECK7-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 46565// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 46566// CHECK7-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 26567// CHECK7-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 26568// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 46569// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 46570// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 406571// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]6572// CHECK7: omp_if.then:6573// CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 06574// CHECK7-NEXT: store i32 [[TMP1]], ptr [[TMP5]], align 46575// CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 06576// CHECK7-NEXT: store i32 [[TMP1]], ptr [[TMP6]], align 46577// CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 06578// CHECK7-NEXT: store ptr null, ptr [[TMP7]], align 46579// CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 16580// CHECK7-NEXT: store i32 [[TMP3]], ptr [[TMP8]], align 46581// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 16582// CHECK7-NEXT: store i32 [[TMP3]], ptr [[TMP9]], align 46583// CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 16584// CHECK7-NEXT: store ptr null, ptr [[TMP10]], align 46585// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 26586// CHECK7-NEXT: store ptr [[B]], ptr [[TMP11]], align 46587// CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 26588// CHECK7-NEXT: store ptr [[B]], ptr [[TMP12]], align 46589// CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 26590// CHECK7-NEXT: store ptr null, ptr [[TMP13]], align 46591// CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 06592// CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 06593// CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 06594// CHECK7-NEXT: store i32 3, ptr [[TMP16]], align 46595// CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 16596// CHECK7-NEXT: store i32 3, ptr [[TMP17]], align 46597// CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 26598// CHECK7-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 46599// CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 36600// CHECK7-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 46601// CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 46602// CHECK7-NEXT: store ptr @.offload_sizes.9, ptr [[TMP20]], align 46603// CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 56604// CHECK7-NEXT: store ptr @.offload_maptypes.10, ptr [[TMP21]], align 46605// CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 66606// CHECK7-NEXT: store ptr null, ptr [[TMP22]], align 46607// CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 76608// CHECK7-NEXT: store ptr null, ptr [[TMP23]], align 46609// CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 86610// CHECK7-NEXT: store i64 0, ptr [[TMP24]], align 86611// CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 96612// CHECK7-NEXT: store i64 0, ptr [[TMP25]], align 86613// CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 106614// CHECK7-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP26]], align 46615// CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 116616// CHECK7-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP27]], align 46617// CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 126618// CHECK7-NEXT: store i32 0, ptr [[TMP28]], align 46619// CHECK7-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.region_id, ptr [[KERNEL_ARGS]])6620// CHECK7-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 06621// CHECK7-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]6622// CHECK7: omp_offload.failed:6623// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]]6624// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]]6625// CHECK7: omp_offload.cont:6626// CHECK7-NEXT: br label [[OMP_IF_END:%.*]]6627// CHECK7: omp_if.else:6628// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]]6629// CHECK7-NEXT: br label [[OMP_IF_END]]6630// CHECK7: omp_if.end:6631// CHECK7-NEXT: [[TMP31:%.*]] = load i32, ptr [[A]], align 46632// CHECK7-NEXT: ret i32 [[TMP31]]6633//6634//6635// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l2146636// CHECK7-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {6637// CHECK7-NEXT: entry:6638// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 46639// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32, align 46640// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 46641// CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 46642// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 46643// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 46644// CHECK7-NEXT: [[B_CASTED:%.*]] = alloca i32, align 46645// CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 46646// CHECK7-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 46647// CHECK7-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 46648// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])6649// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 46650// CHECK7-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 46651// CHECK7-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 46652// CHECK7-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 46653// CHECK7-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 46654// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 46655// CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 46656// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR]], align 46657// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[VLA_ADDR2]], align 46658// CHECK7-NEXT: [[TMP4:%.*]] = load ptr, ptr [[C_ADDR]], align 46659// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_ADDR]], align 46660// CHECK7-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 46661// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[B_CASTED]], align 46662// CHECK7-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 16663// CHECK7-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP7]] to i16664// CHECK7-NEXT: [[STOREDV:%.*]] = zext i1 [[LOADEDV]] to i86665// CHECK7-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 16666// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 46667// CHECK7-NEXT: [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 16668// CHECK7-NEXT: [[LOADEDV3:%.*]] = trunc i8 [[TMP9]] to i16669// CHECK7-NEXT: br i1 [[LOADEDV3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]6670// CHECK7: omp_if.then:6671// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined, ptr [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], ptr [[TMP4]], i32 [[TMP8]])6672// CHECK7-NEXT: br label [[OMP_IF_END:%.*]]6673// CHECK7: omp_if.else:6674// CHECK7-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]])6675// CHECK7-NEXT: store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 46676// CHECK7-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 46677// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], ptr [[TMP4]], i32 [[TMP8]]) #[[ATTR3]]6678// CHECK7-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]])6679// CHECK7-NEXT: br label [[OMP_IF_END]]6680// CHECK7: omp_if.end:6681// CHECK7-NEXT: ret void6682//6683//6684// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined6685// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {6686// CHECK7-NEXT: entry:6687// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 46688// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 46689// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 46690// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32, align 46691// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 46692// CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 46693// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 46694// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 46695// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 86696// CHECK7-NEXT: [[TMP:%.*]] = alloca i64, align 46697// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 86698// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 86699// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 86700// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 46701// CHECK7-NEXT: [[IT:%.*]] = alloca i64, align 86702// CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 46703// CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 46704// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 46705// CHECK7-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 46706// CHECK7-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 46707// CHECK7-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 46708// CHECK7-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 46709// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 46710// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 46711// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 46712// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 46713// CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 46714// CHECK7-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 86715// CHECK7-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 86716// CHECK7-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 86717// CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 46718// CHECK7-NEXT: [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 16719// CHECK7-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP4]] to i16720// CHECK7-NEXT: br i1 [[LOADEDV]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]6721// CHECK7: omp_if.then:6722// CHECK7-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 46723// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 46724// CHECK7-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP6]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)6725// CHECK7-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 86726// CHECK7-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 36727// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]6728// CHECK7: cond.true:6729// CHECK7-NEXT: br label [[COND_END:%.*]]6730// CHECK7: cond.false:6731// CHECK7-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 86732// CHECK7-NEXT: br label [[COND_END]]6733// CHECK7: cond.end:6734// CHECK7-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]6735// CHECK7-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 86736// CHECK7-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_LB]], align 86737// CHECK7-NEXT: store i64 [[TMP9]], ptr [[DOTOMP_IV]], align 86738// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]6739// CHECK7: omp.inner.for.cond:6740// CHECK7-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39:![0-9]+]]6741// CHECK7-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP39]]6742// CHECK7-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]]6743// CHECK7-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]6744// CHECK7: omp.inner.for.body:6745// CHECK7-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39]]6746// CHECK7-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 4006747// CHECK7-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]6748// CHECK7-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP39]]6749// CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP39]]6750// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP13]] to double6751// CHECK7-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+006752// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 06753// CHECK7-NEXT: store double [[ADD]], ptr [[A]], align 4, !nontemporal [[META40:![0-9]+]], !llvm.access.group [[ACC_GRP39]]6754// CHECK7-NEXT: [[A4:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 06755// CHECK7-NEXT: [[TMP14:%.*]] = load double, ptr [[A4]], align 4, !nontemporal [[META40]], !llvm.access.group [[ACC_GRP39]]6756// CHECK7-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+006757// CHECK7-NEXT: store double [[INC]], ptr [[A4]], align 4, !nontemporal [[META40]], !llvm.access.group [[ACC_GRP39]]6758// CHECK7-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i166759// CHECK7-NEXT: [[TMP15:%.*]] = mul nsw i32 1, [[TMP2]]6760// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP15]]6761// CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 16762// CHECK7-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP39]]6763// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]6764// CHECK7: omp.body.continue:6765// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]6766// CHECK7: omp.inner.for.inc:6767// CHECK7-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39]]6768// CHECK7-NEXT: [[ADD7:%.*]] = add i64 [[TMP16]], 16769// CHECK7-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39]]6770// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP41:![0-9]+]]6771// CHECK7: omp.inner.for.end:6772// CHECK7-NEXT: br label [[OMP_IF_END:%.*]]6773// CHECK7: omp_if.else:6774// CHECK7-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 46775// CHECK7-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 46776// CHECK7-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP18]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)6777// CHECK7-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_UB]], align 86778// CHECK7-NEXT: [[CMP8:%.*]] = icmp ugt i64 [[TMP19]], 36779// CHECK7-NEXT: br i1 [[CMP8]], label [[COND_TRUE9:%.*]], label [[COND_FALSE10:%.*]]6780// CHECK7: cond.true9:6781// CHECK7-NEXT: br label [[COND_END11:%.*]]6782// CHECK7: cond.false10:6783// CHECK7-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_UB]], align 86784// CHECK7-NEXT: br label [[COND_END11]]6785// CHECK7: cond.end11:6786// CHECK7-NEXT: [[COND12:%.*]] = phi i64 [ 3, [[COND_TRUE9]] ], [ [[TMP20]], [[COND_FALSE10]] ]6787// CHECK7-NEXT: store i64 [[COND12]], ptr [[DOTOMP_UB]], align 86788// CHECK7-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_LB]], align 86789// CHECK7-NEXT: store i64 [[TMP21]], ptr [[DOTOMP_IV]], align 86790// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]]6791// CHECK7: omp.inner.for.cond13:6792// CHECK7-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 86793// CHECK7-NEXT: [[TMP23:%.*]] = load i64, ptr [[DOTOMP_UB]], align 86794// CHECK7-NEXT: [[CMP14:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]]6795// CHECK7-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END29:%.*]]6796// CHECK7: omp.inner.for.body15:6797// CHECK7-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_IV]], align 86798// CHECK7-NEXT: [[MUL16:%.*]] = mul i64 [[TMP24]], 4006799// CHECK7-NEXT: [[SUB17:%.*]] = sub i64 2000, [[MUL16]]6800// CHECK7-NEXT: store i64 [[SUB17]], ptr [[IT]], align 86801// CHECK7-NEXT: [[TMP25:%.*]] = load i32, ptr [[B_ADDR]], align 46802// CHECK7-NEXT: [[CONV18:%.*]] = sitofp i32 [[TMP25]] to double6803// CHECK7-NEXT: [[ADD19:%.*]] = fadd double [[CONV18]], 1.500000e+006804// CHECK7-NEXT: [[A20:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 06805// CHECK7-NEXT: store double [[ADD19]], ptr [[A20]], align 46806// CHECK7-NEXT: [[A21:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 06807// CHECK7-NEXT: [[TMP26:%.*]] = load double, ptr [[A21]], align 46808// CHECK7-NEXT: [[INC22:%.*]] = fadd double [[TMP26]], 1.000000e+006809// CHECK7-NEXT: store double [[INC22]], ptr [[A21]], align 46810// CHECK7-NEXT: [[CONV23:%.*]] = fptosi double [[INC22]] to i166811// CHECK7-NEXT: [[TMP27:%.*]] = mul nsw i32 1, [[TMP2]]6812// CHECK7-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP27]]6813// CHECK7-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX24]], i32 16814// CHECK7-NEXT: store i16 [[CONV23]], ptr [[ARRAYIDX25]], align 26815// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE26:%.*]]6816// CHECK7: omp.body.continue26:6817// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC27:%.*]]6818// CHECK7: omp.inner.for.inc27:6819// CHECK7-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTOMP_IV]], align 86820// CHECK7-NEXT: [[ADD28:%.*]] = add i64 [[TMP28]], 16821// CHECK7-NEXT: store i64 [[ADD28]], ptr [[DOTOMP_IV]], align 86822// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP43:![0-9]+]]6823// CHECK7: omp.inner.for.end29:6824// CHECK7-NEXT: br label [[OMP_IF_END]]6825// CHECK7: omp_if.end:6826// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]6827// CHECK7: omp.loop.exit:6828// CHECK7-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 46829// CHECK7-NEXT: [[TMP30:%.*]] = load i32, ptr [[TMP29]], align 46830// CHECK7-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP30]])6831// CHECK7-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 46832// CHECK7-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 06833// CHECK7-NEXT: br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]6834// CHECK7: .omp.final.then:6835// CHECK7-NEXT: store i64 400, ptr [[IT]], align 86836// CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]]6837// CHECK7: .omp.final.done:6838// CHECK7-NEXT: ret void6839//6840//6841// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l1956842// CHECK7-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {6843// CHECK7-NEXT: entry:6844// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 46845// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 46846// CHECK7-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 46847// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 46848// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 46849// CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 46850// CHECK7-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 46851// CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 46852// CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 46853// CHECK7-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 46854// CHECK7-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 46855// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 46856// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 46857// CHECK7-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 46858// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 46859// CHECK7-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 26860// CHECK7-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 26861// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 46862// CHECK7-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 16863// CHECK7-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 16864// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[AAA_CASTED]], align 46865// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], ptr [[TMP0]])6866// CHECK7-NEXT: ret void6867//6868//6869// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined6870// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {6871// CHECK7-NEXT: entry:6872// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 46873// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 46874// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 46875// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 46876// CHECK7-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 46877// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 46878// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 46879// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 46880// CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 46881// CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 46882// CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 46883// CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 46884// CHECK7-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 46885// CHECK7-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 46886// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 46887// CHECK7-NEXT: ret void6888//6889//6890// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l1786891// CHECK7-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {6892// CHECK7-NEXT: entry:6893// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 46894// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 46895// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 46896// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 46897// CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 46898// CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 46899// CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 46900// CHECK7-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 46901// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 46902// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 46903// CHECK7-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 46904// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 46905// CHECK7-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 26906// CHECK7-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 26907// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 46908// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]])6909// CHECK7-NEXT: ret void6910//6911//6912// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined6913// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {6914// CHECK7-NEXT: entry:6915// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 46916// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 46917// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 46918// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 46919// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 46920// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 86921// CHECK7-NEXT: [[TMP:%.*]] = alloca i64, align 46922// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 86923// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 86924// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 86925// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 46926// CHECK7-NEXT: [[I:%.*]] = alloca i64, align 86927// CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 46928// CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 46929// CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 46930// CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 46931// CHECK7-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 46932// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 46933// CHECK7-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 86934// CHECK7-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 86935// CHECK7-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 86936// CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 46937// CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 46938// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 46939// CHECK7-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)6940// CHECK7-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 86941// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 66942// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]6943// CHECK7: cond.true:6944// CHECK7-NEXT: br label [[COND_END:%.*]]6945// CHECK7: cond.false:6946// CHECK7-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 86947// CHECK7-NEXT: br label [[COND_END]]6948// CHECK7: cond.end:6949// CHECK7-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]6950// CHECK7-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 86951// CHECK7-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 86952// CHECK7-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 86953// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]6954// CHECK7: omp.inner.for.cond:6955// CHECK7-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP45:![0-9]+]]6956// CHECK7-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP45]]6957// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]6958// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]6959// CHECK7: omp.inner.for.body:6960// CHECK7-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP45]]6961// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 36962// CHECK7-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]6963// CHECK7-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP45]]6964// CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP45]]6965// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 16966// CHECK7-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP45]]6967// CHECK7-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP45]]6968// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i326969// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 16970// CHECK7-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i166971// CHECK7-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP45]]6972// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 26973// CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP45]]6974// CHECK7-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 16975// CHECK7-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP45]]6976// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]6977// CHECK7: omp.body.continue:6978// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]6979// CHECK7: omp.inner.for.inc:6980// CHECK7-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP45]]6981// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 16982// CHECK7-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP45]]6983// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]]6984// CHECK7: omp.inner.for.end:6985// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]6986// CHECK7: omp.loop.exit:6987// CHECK7-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])6988// CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 46989// CHECK7-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 06990// CHECK7-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]6991// CHECK7: .omp.final.then:6992// CHECK7-NEXT: store i64 11, ptr [[I]], align 86993// CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]]6994// CHECK7: .omp.final.done:6995// CHECK7-NEXT: ret void6996//6997//6998// CHECK9-LABEL: define {{[^@]+}}@_Z7get_valv6999// CHECK9-SAME: () #[[ATTR0:[0-9]+]] {7000// CHECK9-NEXT: entry:7001// CHECK9-NEXT: ret i64 07002//7003//7004// CHECK9-LABEL: define {{[^@]+}}@_Z3fooi7005// CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {7006// CHECK9-NEXT: entry:7007// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 47008// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 47009// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 27010// CHECK9-NEXT: [[B:%.*]] = alloca [10 x float], align 47011// CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 87012// CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 87013// CHECK9-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 87014// CHECK9-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 87015// CHECK9-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 87016// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 47017// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 47018// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 47019// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 47020// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 47021// CHECK9-NEXT: [[K:%.*]] = alloca i64, align 87022// CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32, align 47023// CHECK9-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 47024// CHECK9-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 47025// CHECK9-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 47026// CHECK9-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 87027// CHECK9-NEXT: [[I7:%.*]] = alloca i32, align 47028// CHECK9-NEXT: [[K8:%.*]] = alloca i64, align 87029// CHECK9-NEXT: [[LIN:%.*]] = alloca i32, align 47030// CHECK9-NEXT: [[_TMP20:%.*]] = alloca i64, align 87031// CHECK9-NEXT: [[DOTOMP_LB21:%.*]] = alloca i64, align 87032// CHECK9-NEXT: [[DOTOMP_UB22:%.*]] = alloca i64, align 87033// CHECK9-NEXT: [[DOTOMP_IV23:%.*]] = alloca i64, align 87034// CHECK9-NEXT: [[DOTLINEAR_START24:%.*]] = alloca i32, align 47035// CHECK9-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 47036// CHECK9-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 87037// CHECK9-NEXT: [[IT:%.*]] = alloca i64, align 87038// CHECK9-NEXT: [[LIN27:%.*]] = alloca i32, align 47039// CHECK9-NEXT: [[A28:%.*]] = alloca i32, align 47040// CHECK9-NEXT: [[_TMP49:%.*]] = alloca i16, align 27041// CHECK9-NEXT: [[DOTOMP_LB50:%.*]] = alloca i32, align 47042// CHECK9-NEXT: [[DOTOMP_UB51:%.*]] = alloca i32, align 47043// CHECK9-NEXT: [[DOTOMP_IV52:%.*]] = alloca i32, align 47044// CHECK9-NEXT: [[IT53:%.*]] = alloca i16, align 27045// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 47046// CHECK9-NEXT: [[_TMP68:%.*]] = alloca i8, align 17047// CHECK9-NEXT: [[DOTOMP_LB69:%.*]] = alloca i32, align 47048// CHECK9-NEXT: [[DOTOMP_UB70:%.*]] = alloca i32, align 47049// CHECK9-NEXT: [[DOTOMP_IV71:%.*]] = alloca i32, align 47050// CHECK9-NEXT: [[IT72:%.*]] = alloca i8, align 17051// CHECK9-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 47052// CHECK9-NEXT: store i32 0, ptr [[A]], align 47053// CHECK9-NEXT: store i16 0, ptr [[AA]], align 27054// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 47055// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i647056// CHECK9-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()7057// CHECK9-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 87058// CHECK9-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 47059// CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 87060// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 47061// CHECK9-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i647062// CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]7063// CHECK9-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 87064// CHECK9-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 87065// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 47066// CHECK9-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 47067// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 47068// CHECK9-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 47069// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]7070// CHECK9: omp.inner.for.cond:7071// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]]7072// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]]7073// CHECK9-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]7074// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]7075// CHECK9: omp.inner.for.body:7076// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]7077// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 57078// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]7079// CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]7080// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]7081// CHECK9: omp.body.continue:7082// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]7083// CHECK9: omp.inner.for.inc:7084// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]7085// CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 17086// CHECK9-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]7087// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]7088// CHECK9: omp.inner.for.end:7089// CHECK9-NEXT: store i32 33, ptr [[I]], align 47090// CHECK9-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()7091// CHECK9-NEXT: store i64 [[CALL]], ptr [[K]], align 87092// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB4]], align 47093// CHECK9-NEXT: store i32 8, ptr [[DOTOMP_UB5]], align 47094// CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB4]], align 47095// CHECK9-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV6]], align 47096// CHECK9-NEXT: [[TMP12:%.*]] = load i64, ptr [[K]], align 87097// CHECK9-NEXT: store i64 [[TMP12]], ptr [[DOTLINEAR_START]], align 87098// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]]7099// CHECK9: omp.inner.for.cond9:7100// CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]]7101// CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB5]], align 4, !llvm.access.group [[ACC_GRP6]]7102// CHECK9-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]7103// CHECK9-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]]7104// CHECK9: omp.inner.for.body11:7105// CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6]]7106// CHECK9-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP15]], 17107// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]]7108// CHECK9-NEXT: store i32 [[SUB]], ptr [[I7]], align 4, !llvm.access.group [[ACC_GRP6]]7109// CHECK9-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP6]]7110// CHECK9-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6]]7111// CHECK9-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 37112// CHECK9-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i647113// CHECK9-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP16]], [[CONV]]7114// CHECK9-NEXT: store i64 [[ADD14]], ptr [[K8]], align 8, !llvm.access.group [[ACC_GRP6]]7115// CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP6]]7116// CHECK9-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP18]], 17117// CHECK9-NEXT: store i32 [[ADD15]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP6]]7118// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]]7119// CHECK9: omp.body.continue16:7120// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]]7121// CHECK9: omp.inner.for.inc17:7122// CHECK9-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6]]7123// CHECK9-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP19]], 17124// CHECK9-NEXT: store i32 [[ADD18]], ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6]]7125// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]]7126// CHECK9: omp.inner.for.end19:7127// CHECK9-NEXT: store i32 1, ptr [[I7]], align 47128// CHECK9-NEXT: [[TMP20:%.*]] = load i64, ptr [[K8]], align 87129// CHECK9-NEXT: store i64 [[TMP20]], ptr [[K]], align 87130// CHECK9-NEXT: store i32 12, ptr [[LIN]], align 47131// CHECK9-NEXT: store i64 0, ptr [[DOTOMP_LB21]], align 87132// CHECK9-NEXT: store i64 3, ptr [[DOTOMP_UB22]], align 87133// CHECK9-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_LB21]], align 87134// CHECK9-NEXT: store i64 [[TMP21]], ptr [[DOTOMP_IV23]], align 87135// CHECK9-NEXT: [[TMP22:%.*]] = load i32, ptr [[LIN]], align 47136// CHECK9-NEXT: store i32 [[TMP22]], ptr [[DOTLINEAR_START24]], align 47137// CHECK9-NEXT: [[TMP23:%.*]] = load i32, ptr [[A]], align 47138// CHECK9-NEXT: store i32 [[TMP23]], ptr [[DOTLINEAR_START25]], align 47139// CHECK9-NEXT: [[CALL26:%.*]] = call noundef i64 @_Z7get_valv()7140// CHECK9-NEXT: store i64 [[CALL26]], ptr [[DOTLINEAR_STEP]], align 87141// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]]7142// CHECK9: omp.inner.for.cond29:7143// CHECK9-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9:![0-9]+]]7144// CHECK9-NEXT: [[TMP25:%.*]] = load i64, ptr [[DOTOMP_UB22]], align 8, !llvm.access.group [[ACC_GRP9]]7145// CHECK9-NEXT: [[CMP30:%.*]] = icmp ule i64 [[TMP24]], [[TMP25]]7146// CHECK9-NEXT: br i1 [[CMP30]], label [[OMP_INNER_FOR_BODY31:%.*]], label [[OMP_INNER_FOR_END48:%.*]]7147// CHECK9: omp.inner.for.body31:7148// CHECK9-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]]7149// CHECK9-NEXT: [[MUL32:%.*]] = mul i64 [[TMP26]], 4007150// CHECK9-NEXT: [[SUB33:%.*]] = sub i64 2000, [[MUL32]]7151// CHECK9-NEXT: store i64 [[SUB33]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP9]]7152// CHECK9-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTLINEAR_START24]], align 4, !llvm.access.group [[ACC_GRP9]]7153// CHECK9-NEXT: [[CONV34:%.*]] = sext i32 [[TMP27]] to i647154// CHECK9-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]]7155// CHECK9-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP9]]7156// CHECK9-NEXT: [[MUL35:%.*]] = mul i64 [[TMP28]], [[TMP29]]7157// CHECK9-NEXT: [[ADD36:%.*]] = add i64 [[CONV34]], [[MUL35]]7158// CHECK9-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i327159// CHECK9-NEXT: store i32 [[CONV37]], ptr [[LIN27]], align 4, !llvm.access.group [[ACC_GRP9]]7160// CHECK9-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTLINEAR_START25]], align 4, !llvm.access.group [[ACC_GRP9]]7161// CHECK9-NEXT: [[CONV38:%.*]] = sext i32 [[TMP30]] to i647162// CHECK9-NEXT: [[TMP31:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]]7163// CHECK9-NEXT: [[TMP32:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP9]]7164// CHECK9-NEXT: [[MUL39:%.*]] = mul i64 [[TMP31]], [[TMP32]]7165// CHECK9-NEXT: [[ADD40:%.*]] = add i64 [[CONV38]], [[MUL39]]7166// CHECK9-NEXT: [[CONV41:%.*]] = trunc i64 [[ADD40]] to i327167// CHECK9-NEXT: store i32 [[CONV41]], ptr [[A28]], align 4, !llvm.access.group [[ACC_GRP9]]7168// CHECK9-NEXT: [[TMP33:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP9]]7169// CHECK9-NEXT: [[CONV42:%.*]] = sext i16 [[TMP33]] to i327170// CHECK9-NEXT: [[ADD43:%.*]] = add nsw i32 [[CONV42]], 17171// CHECK9-NEXT: [[CONV44:%.*]] = trunc i32 [[ADD43]] to i167172// CHECK9-NEXT: store i16 [[CONV44]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP9]]7173// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE45:%.*]]7174// CHECK9: omp.body.continue45:7175// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC46:%.*]]7176// CHECK9: omp.inner.for.inc46:7177// CHECK9-NEXT: [[TMP34:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]]7178// CHECK9-NEXT: [[ADD47:%.*]] = add i64 [[TMP34]], 17179// CHECK9-NEXT: store i64 [[ADD47]], ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]]7180// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP10:![0-9]+]]7181// CHECK9: omp.inner.for.end48:7182// CHECK9-NEXT: store i64 400, ptr [[IT]], align 87183// CHECK9-NEXT: [[TMP35:%.*]] = load i32, ptr [[LIN27]], align 47184// CHECK9-NEXT: store i32 [[TMP35]], ptr [[LIN]], align 47185// CHECK9-NEXT: [[TMP36:%.*]] = load i32, ptr [[A28]], align 47186// CHECK9-NEXT: store i32 [[TMP36]], ptr [[A]], align 47187// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB50]], align 47188// CHECK9-NEXT: store i32 3, ptr [[DOTOMP_UB51]], align 47189// CHECK9-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTOMP_LB50]], align 47190// CHECK9-NEXT: store i32 [[TMP37]], ptr [[DOTOMP_IV52]], align 47191// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND54:%.*]]7192// CHECK9: omp.inner.for.cond54:7193// CHECK9-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]]7194// CHECK9-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTOMP_UB51]], align 4, !llvm.access.group [[ACC_GRP12]]7195// CHECK9-NEXT: [[CMP55:%.*]] = icmp sle i32 [[TMP38]], [[TMP39]]7196// CHECK9-NEXT: br i1 [[CMP55]], label [[OMP_INNER_FOR_BODY56:%.*]], label [[OMP_INNER_FOR_END67:%.*]]7197// CHECK9: omp.inner.for.body56:7198// CHECK9-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP12]]7199// CHECK9-NEXT: [[MUL57:%.*]] = mul nsw i32 [[TMP40]], 47200// CHECK9-NEXT: [[ADD58:%.*]] = add nsw i32 6, [[MUL57]]7201// CHECK9-NEXT: [[CONV59:%.*]] = trunc i32 [[ADD58]] to i167202// CHECK9-NEXT: store i16 [[CONV59]], ptr [[IT53]], align 2, !llvm.access.group [[ACC_GRP12]]7203// CHECK9-NEXT: [[TMP41:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP12]]7204// CHECK9-NEXT: [[ADD60:%.*]] = add nsw i32 [[TMP41]], 17205// CHECK9-NEXT: store i32 [[ADD60]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP12]]7206// CHECK9-NEXT: [[TMP42:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP12]]7207// CHECK9-NEXT: [[CONV61:%.*]] = sext i16 [[TMP42]] to i327208// CHECK9-NEXT: [[ADD62:%.*]] = add nsw i32 [[CONV61]], 17209// CHECK9-NEXT: [[CONV63:%.*]] = trunc i32 [[ADD62]] to i167210// CHECK9-NEXT: store i16 [[CONV63]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP12]]7211// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE64:%.*]]7212// CHECK9: omp.body.continue64:7213// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC65:%.*]]7214// CHECK9: omp.inner.for.inc65:7215// CHECK9-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP12]]7216// CHECK9-NEXT: [[ADD66:%.*]] = add nsw i32 [[TMP43]], 17217// CHECK9-NEXT: store i32 [[ADD66]], ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP12]]7218// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND54]], !llvm.loop [[LOOP13:![0-9]+]]7219// CHECK9: omp.inner.for.end67:7220// CHECK9-NEXT: store i16 22, ptr [[IT53]], align 27221// CHECK9-NEXT: [[TMP44:%.*]] = load i32, ptr [[A]], align 47222// CHECK9-NEXT: store i32 [[TMP44]], ptr [[DOTCAPTURE_EXPR_]], align 47223// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB69]], align 47224// CHECK9-NEXT: store i32 25, ptr [[DOTOMP_UB70]], align 47225// CHECK9-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTOMP_LB69]], align 47226// CHECK9-NEXT: store i32 [[TMP45]], ptr [[DOTOMP_IV71]], align 47227// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND73:%.*]]7228// CHECK9: omp.inner.for.cond73:7229// CHECK9-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15:![0-9]+]]7230// CHECK9-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTOMP_UB70]], align 4, !llvm.access.group [[ACC_GRP15]]7231// CHECK9-NEXT: [[CMP74:%.*]] = icmp sle i32 [[TMP46]], [[TMP47]]7232// CHECK9-NEXT: br i1 [[CMP74]], label [[OMP_INNER_FOR_BODY75:%.*]], label [[OMP_INNER_FOR_END100:%.*]]7233// CHECK9: omp.inner.for.body75:7234// CHECK9-NEXT: [[TMP48:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15]]7235// CHECK9-NEXT: [[MUL76:%.*]] = mul nsw i32 [[TMP48]], 17236// CHECK9-NEXT: [[SUB77:%.*]] = sub nsw i32 122, [[MUL76]]7237// CHECK9-NEXT: [[CONV78:%.*]] = trunc i32 [[SUB77]] to i87238// CHECK9-NEXT: store i8 [[CONV78]], ptr [[IT72]], align 1, !llvm.access.group [[ACC_GRP15]]7239// CHECK9-NEXT: [[TMP49:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP15]]7240// CHECK9-NEXT: [[ADD79:%.*]] = add nsw i32 [[TMP49]], 17241// CHECK9-NEXT: store i32 [[ADD79]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP15]]7242// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i64 0, i64 27243// CHECK9-NEXT: [[TMP50:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP15]]7244// CHECK9-NEXT: [[CONV80:%.*]] = fpext float [[TMP50]] to double7245// CHECK9-NEXT: [[ADD81:%.*]] = fadd double [[CONV80]], 1.000000e+007246// CHECK9-NEXT: [[CONV82:%.*]] = fptrunc double [[ADD81]] to float7247// CHECK9-NEXT: store float [[CONV82]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP15]]7248// CHECK9-NEXT: [[ARRAYIDX83:%.*]] = getelementptr inbounds float, ptr [[VLA]], i64 37249// CHECK9-NEXT: [[TMP51:%.*]] = load float, ptr [[ARRAYIDX83]], align 4, !llvm.access.group [[ACC_GRP15]]7250// CHECK9-NEXT: [[CONV84:%.*]] = fpext float [[TMP51]] to double7251// CHECK9-NEXT: [[ADD85:%.*]] = fadd double [[CONV84]], 1.000000e+007252// CHECK9-NEXT: [[CONV86:%.*]] = fptrunc double [[ADD85]] to float7253// CHECK9-NEXT: store float [[CONV86]], ptr [[ARRAYIDX83]], align 4, !llvm.access.group [[ACC_GRP15]]7254// CHECK9-NEXT: [[ARRAYIDX87:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i64 0, i64 17255// CHECK9-NEXT: [[ARRAYIDX88:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX87]], i64 0, i64 27256// CHECK9-NEXT: [[TMP52:%.*]] = load double, ptr [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP15]]7257// CHECK9-NEXT: [[ADD89:%.*]] = fadd double [[TMP52]], 1.000000e+007258// CHECK9-NEXT: store double [[ADD89]], ptr [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP15]]7259// CHECK9-NEXT: [[TMP53:%.*]] = mul nsw i64 1, [[TMP4]]7260// CHECK9-NEXT: [[ARRAYIDX90:%.*]] = getelementptr inbounds double, ptr [[VLA1]], i64 [[TMP53]]7261// CHECK9-NEXT: [[ARRAYIDX91:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX90]], i64 37262// CHECK9-NEXT: [[TMP54:%.*]] = load double, ptr [[ARRAYIDX91]], align 8, !llvm.access.group [[ACC_GRP15]]7263// CHECK9-NEXT: [[ADD92:%.*]] = fadd double [[TMP54]], 1.000000e+007264// CHECK9-NEXT: store double [[ADD92]], ptr [[ARRAYIDX91]], align 8, !llvm.access.group [[ACC_GRP15]]7265// CHECK9-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D]], i32 0, i32 07266// CHECK9-NEXT: [[TMP55:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP15]]7267// CHECK9-NEXT: [[ADD93:%.*]] = add nsw i64 [[TMP55]], 17268// CHECK9-NEXT: store i64 [[ADD93]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP15]]7269// CHECK9-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D]], i32 0, i32 17270// CHECK9-NEXT: [[TMP56:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP15]]7271// CHECK9-NEXT: [[CONV94:%.*]] = sext i8 [[TMP56]] to i327272// CHECK9-NEXT: [[ADD95:%.*]] = add nsw i32 [[CONV94]], 17273// CHECK9-NEXT: [[CONV96:%.*]] = trunc i32 [[ADD95]] to i87274// CHECK9-NEXT: store i8 [[CONV96]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP15]]7275// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE97:%.*]]7276// CHECK9: omp.body.continue97:7277// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC98:%.*]]7278// CHECK9: omp.inner.for.inc98:7279// CHECK9-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15]]7280// CHECK9-NEXT: [[ADD99:%.*]] = add nsw i32 [[TMP57]], 17281// CHECK9-NEXT: store i32 [[ADD99]], ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15]]7282// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND73]], !llvm.loop [[LOOP16:![0-9]+]]7283// CHECK9: omp.inner.for.end100:7284// CHECK9-NEXT: store i8 96, ptr [[IT72]], align 17285// CHECK9-NEXT: [[TMP58:%.*]] = load i32, ptr [[A]], align 47286// CHECK9-NEXT: [[TMP59:%.*]] = load ptr, ptr [[SAVED_STACK]], align 87287// CHECK9-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP59]])7288// CHECK9-NEXT: ret i32 [[TMP58]]7289//7290//7291// CHECK9-LABEL: define {{[^@]+}}@_Z3bari7292// CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {7293// CHECK9-NEXT: entry:7294// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 47295// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 47296// CHECK9-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 87297// CHECK9-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 47298// CHECK9-NEXT: store i32 0, ptr [[A]], align 47299// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 47300// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]])7301// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 47302// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]7303// CHECK9-NEXT: store i32 [[ADD]], ptr [[A]], align 47304// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 47305// CHECK9-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]])7306// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 47307// CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]7308// CHECK9-NEXT: store i32 [[ADD2]], ptr [[A]], align 47309// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 47310// CHECK9-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]])7311// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 47312// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]7313// CHECK9-NEXT: store i32 [[ADD4]], ptr [[A]], align 47314// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 47315// CHECK9-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]])7316// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 47317// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]7318// CHECK9-NEXT: store i32 [[ADD6]], ptr [[A]], align 47319// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 47320// CHECK9-NEXT: ret i32 [[TMP8]]7321//7322//7323// CHECK9-LABEL: define {{[^@]+}}@_ZN2S12r1Ei7324// CHECK9-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {7325// CHECK9-NEXT: entry:7326// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 87327// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 47328// CHECK9-NEXT: [[B:%.*]] = alloca i32, align 47329// CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 87330// CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 87331// CHECK9-NEXT: [[TMP:%.*]] = alloca i64, align 87332// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 87333// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 87334// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 87335// CHECK9-NEXT: [[IT:%.*]] = alloca i64, align 87336// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 87337// CHECK9-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 47338// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 87339// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 47340// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 17341// CHECK9-NEXT: store i32 [[ADD]], ptr [[B]], align 47342// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 47343// CHECK9-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i647344// CHECK9-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()7345// CHECK9-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 87346// CHECK9-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]7347// CHECK9-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 27348// CHECK9-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 87349// CHECK9-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 87350// CHECK9-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 87351// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 87352// CHECK9-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 87353// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]7354// CHECK9: omp.inner.for.cond:7355// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18:![0-9]+]]7356// CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP18]]7357// CHECK9-NEXT: [[CMP:%.*]] = icmp ule i64 [[TMP6]], [[TMP7]]7358// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]7359// CHECK9: omp.inner.for.body:7360// CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]]7361// CHECK9-NEXT: [[MUL:%.*]] = mul i64 [[TMP8]], 4007362// CHECK9-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]7363// CHECK9-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP18]]7364// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4, !llvm.access.group [[ACC_GRP18]]7365// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP9]] to double7366// CHECK9-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+007367// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 07368// CHECK9-NEXT: store double [[ADD2]], ptr [[A]], align 8, !llvm.access.group [[ACC_GRP18]]7369// CHECK9-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 07370// CHECK9-NEXT: [[TMP10:%.*]] = load double, ptr [[A3]], align 8, !llvm.access.group [[ACC_GRP18]]7371// CHECK9-NEXT: [[INC:%.*]] = fadd double [[TMP10]], 1.000000e+007372// CHECK9-NEXT: store double [[INC]], ptr [[A3]], align 8, !llvm.access.group [[ACC_GRP18]]7373// CHECK9-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i167374// CHECK9-NEXT: [[TMP11:%.*]] = mul nsw i64 1, [[TMP2]]7375// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP11]]7376// CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 17377// CHECK9-NEXT: store i16 [[CONV4]], ptr [[ARRAYIDX5]], align 2, !llvm.access.group [[ACC_GRP18]]7378// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]7379// CHECK9: omp.body.continue:7380// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]7381// CHECK9: omp.inner.for.inc:7382// CHECK9-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]]7383// CHECK9-NEXT: [[ADD6:%.*]] = add i64 [[TMP12]], 17384// CHECK9-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]]7385// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]7386// CHECK9: omp.inner.for.end:7387// CHECK9-NEXT: store i64 400, ptr [[IT]], align 87388// CHECK9-NEXT: [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]]7389// CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP13]]7390// CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX7]], i64 17391// CHECK9-NEXT: [[TMP14:%.*]] = load i16, ptr [[ARRAYIDX8]], align 27392// CHECK9-NEXT: [[CONV9:%.*]] = sext i16 [[TMP14]] to i327393// CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[B]], align 47394// CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP15]]7395// CHECK9-NEXT: [[TMP16:%.*]] = load ptr, ptr [[SAVED_STACK]], align 87396// CHECK9-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP16]])7397// CHECK9-NEXT: ret i32 [[ADD10]]7398//7399//7400// CHECK9-LABEL: define {{[^@]+}}@_ZL7fstatici7401// CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {7402// CHECK9-NEXT: entry:7403// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 47404// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 47405// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 27406// CHECK9-NEXT: [[AAA:%.*]] = alloca i8, align 17407// CHECK9-NEXT: [[B:%.*]] = alloca [10 x i32], align 47408// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 47409// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 47410// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 47411// CHECK9-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 47412// CHECK9-NEXT: store i32 0, ptr [[A]], align 47413// CHECK9-NEXT: store i16 0, ptr [[AA]], align 27414// CHECK9-NEXT: store i8 0, ptr [[AAA]], align 17415// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 47416// CHECK9-NEXT: store i32 429496720, ptr [[DOTOMP_UB]], align 47417// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 47418// CHECK9-NEXT: ret i32 [[TMP0]]7419//7420//7421// CHECK9-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i7422// CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {7423// CHECK9-NEXT: entry:7424// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 47425// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 47426// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 27427// CHECK9-NEXT: [[B:%.*]] = alloca [10 x i32], align 47428// CHECK9-NEXT: [[TMP:%.*]] = alloca i64, align 87429// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 87430// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 87431// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 87432// CHECK9-NEXT: [[I:%.*]] = alloca i64, align 87433// CHECK9-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 47434// CHECK9-NEXT: store i32 0, ptr [[A]], align 47435// CHECK9-NEXT: store i16 0, ptr [[AA]], align 27436// CHECK9-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 87437// CHECK9-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 87438// CHECK9-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTOMP_LB]], align 87439// CHECK9-NEXT: store i64 [[TMP0]], ptr [[DOTOMP_IV]], align 87440// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]7441// CHECK9: omp.inner.for.cond:7442// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP21:![0-9]+]]7443// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP21]]7444// CHECK9-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]]7445// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]7446// CHECK9: omp.inner.for.body:7447// CHECK9-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP21]]7448// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 37449// CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]7450// CHECK9-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP21]]7451// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP21]]7452// CHECK9-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 17453// CHECK9-NEXT: store i32 [[ADD1]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP21]]7454// CHECK9-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP21]]7455// CHECK9-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i327456// CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 17457// CHECK9-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i167458// CHECK9-NEXT: store i16 [[CONV3]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP21]]7459// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i64 0, i64 27460// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP21]]7461// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 17462// CHECK9-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP21]]7463// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]7464// CHECK9: omp.body.continue:7465// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]7466// CHECK9: omp.inner.for.inc:7467// CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP21]]7468// CHECK9-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 17469// CHECK9-NEXT: store i64 [[ADD5]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP21]]7470// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]7471// CHECK9: omp.inner.for.end:7472// CHECK9-NEXT: store i64 11, ptr [[I]], align 87473// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 47474// CHECK9-NEXT: ret i32 [[TMP8]]7475//7476//7477// CHECK11-LABEL: define {{[^@]+}}@_Z7get_valv7478// CHECK11-SAME: () #[[ATTR0:[0-9]+]] {7479// CHECK11-NEXT: entry:7480// CHECK11-NEXT: ret i64 07481//7482//7483// CHECK11-LABEL: define {{[^@]+}}@_Z3fooi7484// CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {7485// CHECK11-NEXT: entry:7486// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 47487// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 47488// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 27489// CHECK11-NEXT: [[B:%.*]] = alloca [10 x float], align 47490// CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 47491// CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 47492// CHECK11-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 87493// CHECK11-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 47494// CHECK11-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 47495// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 47496// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 47497// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 47498// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 47499// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 47500// CHECK11-NEXT: [[K:%.*]] = alloca i64, align 87501// CHECK11-NEXT: [[_TMP3:%.*]] = alloca i32, align 47502// CHECK11-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 47503// CHECK11-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 47504// CHECK11-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 47505// CHECK11-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 87506// CHECK11-NEXT: [[I7:%.*]] = alloca i32, align 47507// CHECK11-NEXT: [[K8:%.*]] = alloca i64, align 87508// CHECK11-NEXT: [[LIN:%.*]] = alloca i32, align 47509// CHECK11-NEXT: [[_TMP20:%.*]] = alloca i64, align 47510// CHECK11-NEXT: [[DOTOMP_LB21:%.*]] = alloca i64, align 87511// CHECK11-NEXT: [[DOTOMP_UB22:%.*]] = alloca i64, align 87512// CHECK11-NEXT: [[DOTOMP_IV23:%.*]] = alloca i64, align 87513// CHECK11-NEXT: [[DOTLINEAR_START24:%.*]] = alloca i32, align 47514// CHECK11-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 47515// CHECK11-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 87516// CHECK11-NEXT: [[IT:%.*]] = alloca i64, align 87517// CHECK11-NEXT: [[LIN27:%.*]] = alloca i32, align 47518// CHECK11-NEXT: [[A28:%.*]] = alloca i32, align 47519// CHECK11-NEXT: [[_TMP49:%.*]] = alloca i16, align 27520// CHECK11-NEXT: [[DOTOMP_LB50:%.*]] = alloca i32, align 47521// CHECK11-NEXT: [[DOTOMP_UB51:%.*]] = alloca i32, align 47522// CHECK11-NEXT: [[DOTOMP_IV52:%.*]] = alloca i32, align 47523// CHECK11-NEXT: [[IT53:%.*]] = alloca i16, align 27524// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 47525// CHECK11-NEXT: [[_TMP68:%.*]] = alloca i8, align 17526// CHECK11-NEXT: [[DOTOMP_LB69:%.*]] = alloca i32, align 47527// CHECK11-NEXT: [[DOTOMP_UB70:%.*]] = alloca i32, align 47528// CHECK11-NEXT: [[DOTOMP_IV71:%.*]] = alloca i32, align 47529// CHECK11-NEXT: [[IT72:%.*]] = alloca i8, align 17530// CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 47531// CHECK11-NEXT: store i32 0, ptr [[A]], align 47532// CHECK11-NEXT: store i16 0, ptr [[AA]], align 27533// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 47534// CHECK11-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()7535// CHECK11-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 47536// CHECK11-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 47537// CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 47538// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 47539// CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]7540// CHECK11-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 87541// CHECK11-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 47542// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 47543// CHECK11-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 47544// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 47545// CHECK11-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 47546// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]7547// CHECK11: omp.inner.for.cond:7548// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]]7549// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]]7550// CHECK11-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]7551// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]7552// CHECK11: omp.inner.for.body:7553// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]7554// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 57555// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]7556// CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]7557// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]7558// CHECK11: omp.body.continue:7559// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]7560// CHECK11: omp.inner.for.inc:7561// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]7562// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 17563// CHECK11-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]7564// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]7565// CHECK11: omp.inner.for.end:7566// CHECK11-NEXT: store i32 33, ptr [[I]], align 47567// CHECK11-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()7568// CHECK11-NEXT: store i64 [[CALL]], ptr [[K]], align 87569// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB4]], align 47570// CHECK11-NEXT: store i32 8, ptr [[DOTOMP_UB5]], align 47571// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB4]], align 47572// CHECK11-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV6]], align 47573// CHECK11-NEXT: [[TMP10:%.*]] = load i64, ptr [[K]], align 87574// CHECK11-NEXT: store i64 [[TMP10]], ptr [[DOTLINEAR_START]], align 87575// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]]7576// CHECK11: omp.inner.for.cond9:7577// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]]7578// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB5]], align 4, !llvm.access.group [[ACC_GRP7]]7579// CHECK11-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]7580// CHECK11-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]]7581// CHECK11: omp.inner.for.body11:7582// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7]]7583// CHECK11-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP13]], 17584// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]]7585// CHECK11-NEXT: store i32 [[SUB]], ptr [[I7]], align 4, !llvm.access.group [[ACC_GRP7]]7586// CHECK11-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP7]]7587// CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7]]7588// CHECK11-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 37589// CHECK11-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i647590// CHECK11-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP14]], [[CONV]]7591// CHECK11-NEXT: store i64 [[ADD14]], ptr [[K8]], align 8, !llvm.access.group [[ACC_GRP7]]7592// CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP7]]7593// CHECK11-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 17594// CHECK11-NEXT: store i32 [[ADD15]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP7]]7595// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]]7596// CHECK11: omp.body.continue16:7597// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]]7598// CHECK11: omp.inner.for.inc17:7599// CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7]]7600// CHECK11-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP17]], 17601// CHECK11-NEXT: store i32 [[ADD18]], ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7]]7602// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP8:![0-9]+]]7603// CHECK11: omp.inner.for.end19:7604// CHECK11-NEXT: store i32 1, ptr [[I7]], align 47605// CHECK11-NEXT: [[TMP18:%.*]] = load i64, ptr [[K8]], align 87606// CHECK11-NEXT: store i64 [[TMP18]], ptr [[K]], align 87607// CHECK11-NEXT: store i32 12, ptr [[LIN]], align 47608// CHECK11-NEXT: store i64 0, ptr [[DOTOMP_LB21]], align 87609// CHECK11-NEXT: store i64 3, ptr [[DOTOMP_UB22]], align 87610// CHECK11-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_LB21]], align 87611// CHECK11-NEXT: store i64 [[TMP19]], ptr [[DOTOMP_IV23]], align 87612// CHECK11-NEXT: [[TMP20:%.*]] = load i32, ptr [[LIN]], align 47613// CHECK11-NEXT: store i32 [[TMP20]], ptr [[DOTLINEAR_START24]], align 47614// CHECK11-NEXT: [[TMP21:%.*]] = load i32, ptr [[A]], align 47615// CHECK11-NEXT: store i32 [[TMP21]], ptr [[DOTLINEAR_START25]], align 47616// CHECK11-NEXT: [[CALL26:%.*]] = call noundef i64 @_Z7get_valv()7617// CHECK11-NEXT: store i64 [[CALL26]], ptr [[DOTLINEAR_STEP]], align 87618// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]]7619// CHECK11: omp.inner.for.cond29:7620// CHECK11-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10:![0-9]+]]7621// CHECK11-NEXT: [[TMP23:%.*]] = load i64, ptr [[DOTOMP_UB22]], align 8, !llvm.access.group [[ACC_GRP10]]7622// CHECK11-NEXT: [[CMP30:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]]7623// CHECK11-NEXT: br i1 [[CMP30]], label [[OMP_INNER_FOR_BODY31:%.*]], label [[OMP_INNER_FOR_END48:%.*]]7624// CHECK11: omp.inner.for.body31:7625// CHECK11-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]]7626// CHECK11-NEXT: [[MUL32:%.*]] = mul i64 [[TMP24]], 4007627// CHECK11-NEXT: [[SUB33:%.*]] = sub i64 2000, [[MUL32]]7628// CHECK11-NEXT: store i64 [[SUB33]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP10]]7629// CHECK11-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTLINEAR_START24]], align 4, !llvm.access.group [[ACC_GRP10]]7630// CHECK11-NEXT: [[CONV34:%.*]] = sext i32 [[TMP25]] to i647631// CHECK11-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]]7632// CHECK11-NEXT: [[TMP27:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP10]]7633// CHECK11-NEXT: [[MUL35:%.*]] = mul i64 [[TMP26]], [[TMP27]]7634// CHECK11-NEXT: [[ADD36:%.*]] = add i64 [[CONV34]], [[MUL35]]7635// CHECK11-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i327636// CHECK11-NEXT: store i32 [[CONV37]], ptr [[LIN27]], align 4, !llvm.access.group [[ACC_GRP10]]7637// CHECK11-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTLINEAR_START25]], align 4, !llvm.access.group [[ACC_GRP10]]7638// CHECK11-NEXT: [[CONV38:%.*]] = sext i32 [[TMP28]] to i647639// CHECK11-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]]7640// CHECK11-NEXT: [[TMP30:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP10]]7641// CHECK11-NEXT: [[MUL39:%.*]] = mul i64 [[TMP29]], [[TMP30]]7642// CHECK11-NEXT: [[ADD40:%.*]] = add i64 [[CONV38]], [[MUL39]]7643// CHECK11-NEXT: [[CONV41:%.*]] = trunc i64 [[ADD40]] to i327644// CHECK11-NEXT: store i32 [[CONV41]], ptr [[A28]], align 4, !llvm.access.group [[ACC_GRP10]]7645// CHECK11-NEXT: [[TMP31:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP10]]7646// CHECK11-NEXT: [[CONV42:%.*]] = sext i16 [[TMP31]] to i327647// CHECK11-NEXT: [[ADD43:%.*]] = add nsw i32 [[CONV42]], 17648// CHECK11-NEXT: [[CONV44:%.*]] = trunc i32 [[ADD43]] to i167649// CHECK11-NEXT: store i16 [[CONV44]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP10]]7650// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE45:%.*]]7651// CHECK11: omp.body.continue45:7652// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC46:%.*]]7653// CHECK11: omp.inner.for.inc46:7654// CHECK11-NEXT: [[TMP32:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]]7655// CHECK11-NEXT: [[ADD47:%.*]] = add i64 [[TMP32]], 17656// CHECK11-NEXT: store i64 [[ADD47]], ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]]7657// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP11:![0-9]+]]7658// CHECK11: omp.inner.for.end48:7659// CHECK11-NEXT: store i64 400, ptr [[IT]], align 87660// CHECK11-NEXT: [[TMP33:%.*]] = load i32, ptr [[LIN27]], align 47661// CHECK11-NEXT: store i32 [[TMP33]], ptr [[LIN]], align 47662// CHECK11-NEXT: [[TMP34:%.*]] = load i32, ptr [[A28]], align 47663// CHECK11-NEXT: store i32 [[TMP34]], ptr [[A]], align 47664// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB50]], align 47665// CHECK11-NEXT: store i32 3, ptr [[DOTOMP_UB51]], align 47666// CHECK11-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_LB50]], align 47667// CHECK11-NEXT: store i32 [[TMP35]], ptr [[DOTOMP_IV52]], align 47668// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND54:%.*]]7669// CHECK11: omp.inner.for.cond54:7670// CHECK11-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP13:![0-9]+]]7671// CHECK11-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTOMP_UB51]], align 4, !llvm.access.group [[ACC_GRP13]]7672// CHECK11-NEXT: [[CMP55:%.*]] = icmp sle i32 [[TMP36]], [[TMP37]]7673// CHECK11-NEXT: br i1 [[CMP55]], label [[OMP_INNER_FOR_BODY56:%.*]], label [[OMP_INNER_FOR_END67:%.*]]7674// CHECK11: omp.inner.for.body56:7675// CHECK11-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP13]]7676// CHECK11-NEXT: [[MUL57:%.*]] = mul nsw i32 [[TMP38]], 47677// CHECK11-NEXT: [[ADD58:%.*]] = add nsw i32 6, [[MUL57]]7678// CHECK11-NEXT: [[CONV59:%.*]] = trunc i32 [[ADD58]] to i167679// CHECK11-NEXT: store i16 [[CONV59]], ptr [[IT53]], align 2, !llvm.access.group [[ACC_GRP13]]7680// CHECK11-NEXT: [[TMP39:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP13]]7681// CHECK11-NEXT: [[ADD60:%.*]] = add nsw i32 [[TMP39]], 17682// CHECK11-NEXT: store i32 [[ADD60]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP13]]7683// CHECK11-NEXT: [[TMP40:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP13]]7684// CHECK11-NEXT: [[CONV61:%.*]] = sext i16 [[TMP40]] to i327685// CHECK11-NEXT: [[ADD62:%.*]] = add nsw i32 [[CONV61]], 17686// CHECK11-NEXT: [[CONV63:%.*]] = trunc i32 [[ADD62]] to i167687// CHECK11-NEXT: store i16 [[CONV63]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP13]]7688// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE64:%.*]]7689// CHECK11: omp.body.continue64:7690// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC65:%.*]]7691// CHECK11: omp.inner.for.inc65:7692// CHECK11-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP13]]7693// CHECK11-NEXT: [[ADD66:%.*]] = add nsw i32 [[TMP41]], 17694// CHECK11-NEXT: store i32 [[ADD66]], ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP13]]7695// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND54]], !llvm.loop [[LOOP14:![0-9]+]]7696// CHECK11: omp.inner.for.end67:7697// CHECK11-NEXT: store i16 22, ptr [[IT53]], align 27698// CHECK11-NEXT: [[TMP42:%.*]] = load i32, ptr [[A]], align 47699// CHECK11-NEXT: store i32 [[TMP42]], ptr [[DOTCAPTURE_EXPR_]], align 47700// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB69]], align 47701// CHECK11-NEXT: store i32 25, ptr [[DOTOMP_UB70]], align 47702// CHECK11-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTOMP_LB69]], align 47703// CHECK11-NEXT: store i32 [[TMP43]], ptr [[DOTOMP_IV71]], align 47704// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND73:%.*]]7705// CHECK11: omp.inner.for.cond73:7706// CHECK11-NEXT: [[TMP44:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16:![0-9]+]]7707// CHECK11-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTOMP_UB70]], align 4, !llvm.access.group [[ACC_GRP16]]7708// CHECK11-NEXT: [[CMP74:%.*]] = icmp sle i32 [[TMP44]], [[TMP45]]7709// CHECK11-NEXT: br i1 [[CMP74]], label [[OMP_INNER_FOR_BODY75:%.*]], label [[OMP_INNER_FOR_END100:%.*]]7710// CHECK11: omp.inner.for.body75:7711// CHECK11-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16]]7712// CHECK11-NEXT: [[MUL76:%.*]] = mul nsw i32 [[TMP46]], 17713// CHECK11-NEXT: [[SUB77:%.*]] = sub nsw i32 122, [[MUL76]]7714// CHECK11-NEXT: [[CONV78:%.*]] = trunc i32 [[SUB77]] to i87715// CHECK11-NEXT: store i8 [[CONV78]], ptr [[IT72]], align 1, !llvm.access.group [[ACC_GRP16]]7716// CHECK11-NEXT: [[TMP47:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP16]]7717// CHECK11-NEXT: [[ADD79:%.*]] = add nsw i32 [[TMP47]], 17718// CHECK11-NEXT: store i32 [[ADD79]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP16]]7719// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i32 0, i32 27720// CHECK11-NEXT: [[TMP48:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]]7721// CHECK11-NEXT: [[CONV80:%.*]] = fpext float [[TMP48]] to double7722// CHECK11-NEXT: [[ADD81:%.*]] = fadd double [[CONV80]], 1.000000e+007723// CHECK11-NEXT: [[CONV82:%.*]] = fptrunc double [[ADD81]] to float7724// CHECK11-NEXT: store float [[CONV82]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]]7725// CHECK11-NEXT: [[ARRAYIDX83:%.*]] = getelementptr inbounds float, ptr [[VLA]], i32 37726// CHECK11-NEXT: [[TMP49:%.*]] = load float, ptr [[ARRAYIDX83]], align 4, !llvm.access.group [[ACC_GRP16]]7727// CHECK11-NEXT: [[CONV84:%.*]] = fpext float [[TMP49]] to double7728// CHECK11-NEXT: [[ADD85:%.*]] = fadd double [[CONV84]], 1.000000e+007729// CHECK11-NEXT: [[CONV86:%.*]] = fptrunc double [[ADD85]] to float7730// CHECK11-NEXT: store float [[CONV86]], ptr [[ARRAYIDX83]], align 4, !llvm.access.group [[ACC_GRP16]]7731// CHECK11-NEXT: [[ARRAYIDX87:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i32 0, i32 17732// CHECK11-NEXT: [[ARRAYIDX88:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX87]], i32 0, i32 27733// CHECK11-NEXT: [[TMP50:%.*]] = load double, ptr [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP16]]7734// CHECK11-NEXT: [[ADD89:%.*]] = fadd double [[TMP50]], 1.000000e+007735// CHECK11-NEXT: store double [[ADD89]], ptr [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP16]]7736// CHECK11-NEXT: [[TMP51:%.*]] = mul nsw i32 1, [[TMP2]]7737// CHECK11-NEXT: [[ARRAYIDX90:%.*]] = getelementptr inbounds double, ptr [[VLA1]], i32 [[TMP51]]7738// CHECK11-NEXT: [[ARRAYIDX91:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX90]], i32 37739// CHECK11-NEXT: [[TMP52:%.*]] = load double, ptr [[ARRAYIDX91]], align 8, !llvm.access.group [[ACC_GRP16]]7740// CHECK11-NEXT: [[ADD92:%.*]] = fadd double [[TMP52]], 1.000000e+007741// CHECK11-NEXT: store double [[ADD92]], ptr [[ARRAYIDX91]], align 8, !llvm.access.group [[ACC_GRP16]]7742// CHECK11-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D]], i32 0, i32 07743// CHECK11-NEXT: [[TMP53:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP16]]7744// CHECK11-NEXT: [[ADD93:%.*]] = add nsw i64 [[TMP53]], 17745// CHECK11-NEXT: store i64 [[ADD93]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP16]]7746// CHECK11-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D]], i32 0, i32 17747// CHECK11-NEXT: [[TMP54:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP16]]7748// CHECK11-NEXT: [[CONV94:%.*]] = sext i8 [[TMP54]] to i327749// CHECK11-NEXT: [[ADD95:%.*]] = add nsw i32 [[CONV94]], 17750// CHECK11-NEXT: [[CONV96:%.*]] = trunc i32 [[ADD95]] to i87751// CHECK11-NEXT: store i8 [[CONV96]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP16]]7752// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE97:%.*]]7753// CHECK11: omp.body.continue97:7754// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC98:%.*]]7755// CHECK11: omp.inner.for.inc98:7756// CHECK11-NEXT: [[TMP55:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16]]7757// CHECK11-NEXT: [[ADD99:%.*]] = add nsw i32 [[TMP55]], 17758// CHECK11-NEXT: store i32 [[ADD99]], ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16]]7759// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND73]], !llvm.loop [[LOOP17:![0-9]+]]7760// CHECK11: omp.inner.for.end100:7761// CHECK11-NEXT: store i8 96, ptr [[IT72]], align 17762// CHECK11-NEXT: [[TMP56:%.*]] = load i32, ptr [[A]], align 47763// CHECK11-NEXT: [[TMP57:%.*]] = load ptr, ptr [[SAVED_STACK]], align 47764// CHECK11-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP57]])7765// CHECK11-NEXT: ret i32 [[TMP56]]7766//7767//7768// CHECK11-LABEL: define {{[^@]+}}@_Z3bari7769// CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {7770// CHECK11-NEXT: entry:7771// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 47772// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 47773// CHECK11-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 47774// CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 47775// CHECK11-NEXT: store i32 0, ptr [[A]], align 47776// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 47777// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]])7778// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 47779// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]7780// CHECK11-NEXT: store i32 [[ADD]], ptr [[A]], align 47781// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 47782// CHECK11-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]])7783// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 47784// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]7785// CHECK11-NEXT: store i32 [[ADD2]], ptr [[A]], align 47786// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 47787// CHECK11-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]])7788// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 47789// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]7790// CHECK11-NEXT: store i32 [[ADD4]], ptr [[A]], align 47791// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 47792// CHECK11-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]])7793// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 47794// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]7795// CHECK11-NEXT: store i32 [[ADD6]], ptr [[A]], align 47796// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 47797// CHECK11-NEXT: ret i32 [[TMP8]]7798//7799//7800// CHECK11-LABEL: define {{[^@]+}}@_ZN2S12r1Ei7801// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {7802// CHECK11-NEXT: entry:7803// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 47804// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 47805// CHECK11-NEXT: [[B:%.*]] = alloca i32, align 47806// CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 47807// CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 47808// CHECK11-NEXT: [[TMP:%.*]] = alloca i64, align 47809// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 87810// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 87811// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 87812// CHECK11-NEXT: [[IT:%.*]] = alloca i64, align 87813// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 47814// CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 47815// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 47816// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 47817// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 17818// CHECK11-NEXT: store i32 [[ADD]], ptr [[B]], align 47819// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 47820// CHECK11-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()7821// CHECK11-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 47822// CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]7823// CHECK11-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 27824// CHECK11-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 47825// CHECK11-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 87826// CHECK11-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 87827// CHECK11-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_LB]], align 87828// CHECK11-NEXT: store i64 [[TMP4]], ptr [[DOTOMP_IV]], align 87829// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]7830// CHECK11: omp.inner.for.cond:7831// CHECK11-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP19:![0-9]+]]7832// CHECK11-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP19]]7833// CHECK11-NEXT: [[CMP:%.*]] = icmp ule i64 [[TMP5]], [[TMP6]]7834// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]7835// CHECK11: omp.inner.for.body:7836// CHECK11-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP19]]7837// CHECK11-NEXT: [[MUL:%.*]] = mul i64 [[TMP7]], 4007838// CHECK11-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]7839// CHECK11-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP19]]7840// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[B]], align 4, !llvm.access.group [[ACC_GRP19]]7841// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double7842// CHECK11-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+007843// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 07844// CHECK11-NEXT: store double [[ADD2]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP19]]7845// CHECK11-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 07846// CHECK11-NEXT: [[TMP9:%.*]] = load double, ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP19]]7847// CHECK11-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+007848// CHECK11-NEXT: store double [[INC]], ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP19]]7849// CHECK11-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i167850// CHECK11-NEXT: [[TMP10:%.*]] = mul nsw i32 1, [[TMP1]]7851// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP10]]7852// CHECK11-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 17853// CHECK11-NEXT: store i16 [[CONV4]], ptr [[ARRAYIDX5]], align 2, !llvm.access.group [[ACC_GRP19]]7854// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]7855// CHECK11: omp.body.continue:7856// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]7857// CHECK11: omp.inner.for.inc:7858// CHECK11-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP19]]7859// CHECK11-NEXT: [[ADD6:%.*]] = add i64 [[TMP11]], 17860// CHECK11-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP19]]7861// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]7862// CHECK11: omp.inner.for.end:7863// CHECK11-NEXT: store i64 400, ptr [[IT]], align 87864// CHECK11-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]]7865// CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP12]]7866// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX7]], i32 17867// CHECK11-NEXT: [[TMP13:%.*]] = load i16, ptr [[ARRAYIDX8]], align 27868// CHECK11-NEXT: [[CONV9:%.*]] = sext i16 [[TMP13]] to i327869// CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[B]], align 47870// CHECK11-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP14]]7871// CHECK11-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 47872// CHECK11-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP15]])7873// CHECK11-NEXT: ret i32 [[ADD10]]7874//7875//7876// CHECK11-LABEL: define {{[^@]+}}@_ZL7fstatici7877// CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {7878// CHECK11-NEXT: entry:7879// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 47880// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 47881// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 27882// CHECK11-NEXT: [[AAA:%.*]] = alloca i8, align 17883// CHECK11-NEXT: [[B:%.*]] = alloca [10 x i32], align 47884// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 47885// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 47886// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 47887// CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 47888// CHECK11-NEXT: store i32 0, ptr [[A]], align 47889// CHECK11-NEXT: store i16 0, ptr [[AA]], align 27890// CHECK11-NEXT: store i8 0, ptr [[AAA]], align 17891// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 47892// CHECK11-NEXT: store i32 429496720, ptr [[DOTOMP_UB]], align 47893// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 47894// CHECK11-NEXT: ret i32 [[TMP0]]7895//7896//7897// CHECK11-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i7898// CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {7899// CHECK11-NEXT: entry:7900// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 47901// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 47902// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 27903// CHECK11-NEXT: [[B:%.*]] = alloca [10 x i32], align 47904// CHECK11-NEXT: [[TMP:%.*]] = alloca i64, align 47905// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 87906// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 87907// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 87908// CHECK11-NEXT: [[I:%.*]] = alloca i64, align 87909// CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 47910// CHECK11-NEXT: store i32 0, ptr [[A]], align 47911// CHECK11-NEXT: store i16 0, ptr [[AA]], align 27912// CHECK11-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 87913// CHECK11-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 87914// CHECK11-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTOMP_LB]], align 87915// CHECK11-NEXT: store i64 [[TMP0]], ptr [[DOTOMP_IV]], align 87916// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]7917// CHECK11: omp.inner.for.cond:7918// CHECK11-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP22:![0-9]+]]7919// CHECK11-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP22]]7920// CHECK11-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]]7921// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]7922// CHECK11: omp.inner.for.body:7923// CHECK11-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP22]]7924// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 37925// CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]7926// CHECK11-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP22]]7927// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP22]]7928// CHECK11-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 17929// CHECK11-NEXT: store i32 [[ADD1]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP22]]7930// CHECK11-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP22]]7931// CHECK11-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i327932// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 17933// CHECK11-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i167934// CHECK11-NEXT: store i16 [[CONV3]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP22]]7935// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i32 0, i32 27936// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]]7937// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 17938// CHECK11-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]]7939// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]7940// CHECK11: omp.body.continue:7941// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]7942// CHECK11: omp.inner.for.inc:7943// CHECK11-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP22]]7944// CHECK11-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 17945// CHECK11-NEXT: store i64 [[ADD5]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP22]]7946// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]7947// CHECK11: omp.inner.for.end:7948// CHECK11-NEXT: store i64 11, ptr [[I]], align 87949// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 47950// CHECK11-NEXT: ret i32 [[TMP8]]7951//7952//7953// CHECK13-LABEL: define {{[^@]+}}@_Z7get_valv7954// CHECK13-SAME: () #[[ATTR0:[0-9]+]] {7955// CHECK13-NEXT: entry:7956// CHECK13-NEXT: ret i64 07957//7958//7959// CHECK13-LABEL: define {{[^@]+}}@_Z3fooi7960// CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {7961// CHECK13-NEXT: entry:7962// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 47963// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 47964// CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 27965// CHECK13-NEXT: [[B:%.*]] = alloca [10 x float], align 47966// CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 87967// CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 87968// CHECK13-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 87969// CHECK13-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 87970// CHECK13-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 87971// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 47972// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 47973// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 47974// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 47975// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 47976// CHECK13-NEXT: [[K:%.*]] = alloca i64, align 87977// CHECK13-NEXT: [[_TMP3:%.*]] = alloca i32, align 47978// CHECK13-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 47979// CHECK13-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 47980// CHECK13-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 47981// CHECK13-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 87982// CHECK13-NEXT: [[I7:%.*]] = alloca i32, align 47983// CHECK13-NEXT: [[K8:%.*]] = alloca i64, align 87984// CHECK13-NEXT: [[LIN:%.*]] = alloca i32, align 47985// CHECK13-NEXT: [[_TMP20:%.*]] = alloca i64, align 87986// CHECK13-NEXT: [[DOTOMP_LB21:%.*]] = alloca i64, align 87987// CHECK13-NEXT: [[DOTOMP_UB22:%.*]] = alloca i64, align 87988// CHECK13-NEXT: [[DOTOMP_IV23:%.*]] = alloca i64, align 87989// CHECK13-NEXT: [[DOTLINEAR_START24:%.*]] = alloca i32, align 47990// CHECK13-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 47991// CHECK13-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 87992// CHECK13-NEXT: [[IT:%.*]] = alloca i64, align 87993// CHECK13-NEXT: [[LIN27:%.*]] = alloca i32, align 47994// CHECK13-NEXT: [[A28:%.*]] = alloca i32, align 47995// CHECK13-NEXT: [[_TMP49:%.*]] = alloca i16, align 27996// CHECK13-NEXT: [[DOTOMP_LB50:%.*]] = alloca i32, align 47997// CHECK13-NEXT: [[DOTOMP_UB51:%.*]] = alloca i32, align 47998// CHECK13-NEXT: [[DOTOMP_IV52:%.*]] = alloca i32, align 47999// CHECK13-NEXT: [[IT53:%.*]] = alloca i16, align 28000// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 48001// CHECK13-NEXT: [[_TMP68:%.*]] = alloca i8, align 18002// CHECK13-NEXT: [[DOTOMP_LB69:%.*]] = alloca i32, align 48003// CHECK13-NEXT: [[DOTOMP_UB70:%.*]] = alloca i32, align 48004// CHECK13-NEXT: [[DOTOMP_IV71:%.*]] = alloca i32, align 48005// CHECK13-NEXT: [[IT72:%.*]] = alloca i8, align 18006// CHECK13-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 48007// CHECK13-NEXT: store i32 0, ptr [[A]], align 48008// CHECK13-NEXT: store i16 0, ptr [[AA]], align 28009// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 48010// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i648011// CHECK13-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()8012// CHECK13-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 88013// CHECK13-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 48014// CHECK13-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 88015// CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 48016// CHECK13-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i648017// CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]8018// CHECK13-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 88019// CHECK13-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 88020// CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 48021// CHECK13-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 48022// CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 48023// CHECK13-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 48024// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]8025// CHECK13: omp.inner.for.cond:8026// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]]8027// CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]]8028// CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]8029// CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]8030// CHECK13: omp.inner.for.body:8031// CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]8032// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 58033// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]8034// CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]8035// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]8036// CHECK13: omp.body.continue:8037// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]8038// CHECK13: omp.inner.for.inc:8039// CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]8040// CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 18041// CHECK13-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]8042// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]8043// CHECK13: omp.inner.for.end:8044// CHECK13-NEXT: store i32 33, ptr [[I]], align 48045// CHECK13-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()8046// CHECK13-NEXT: store i64 [[CALL]], ptr [[K]], align 88047// CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB4]], align 48048// CHECK13-NEXT: store i32 8, ptr [[DOTOMP_UB5]], align 48049// CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB4]], align 48050// CHECK13-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV6]], align 48051// CHECK13-NEXT: [[TMP12:%.*]] = load i64, ptr [[K]], align 88052// CHECK13-NEXT: store i64 [[TMP12]], ptr [[DOTLINEAR_START]], align 88053// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]]8054// CHECK13: omp.inner.for.cond9:8055// CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]]8056// CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB5]], align 4, !llvm.access.group [[ACC_GRP6]]8057// CHECK13-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]8058// CHECK13-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]]8059// CHECK13: omp.inner.for.body11:8060// CHECK13-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6]]8061// CHECK13-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP15]], 18062// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]]8063// CHECK13-NEXT: store i32 [[SUB]], ptr [[I7]], align 4, !llvm.access.group [[ACC_GRP6]]8064// CHECK13-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP6]]8065// CHECK13-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6]]8066// CHECK13-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 38067// CHECK13-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i648068// CHECK13-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP16]], [[CONV]]8069// CHECK13-NEXT: store i64 [[ADD14]], ptr [[K8]], align 8, !llvm.access.group [[ACC_GRP6]]8070// CHECK13-NEXT: [[TMP18:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP6]]8071// CHECK13-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP18]], 18072// CHECK13-NEXT: store i32 [[ADD15]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP6]]8073// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]]8074// CHECK13: omp.body.continue16:8075// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]]8076// CHECK13: omp.inner.for.inc17:8077// CHECK13-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6]]8078// CHECK13-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP19]], 18079// CHECK13-NEXT: store i32 [[ADD18]], ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6]]8080// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]]8081// CHECK13: omp.inner.for.end19:8082// CHECK13-NEXT: store i32 1, ptr [[I7]], align 48083// CHECK13-NEXT: [[TMP20:%.*]] = load i64, ptr [[K8]], align 88084// CHECK13-NEXT: store i64 [[TMP20]], ptr [[K]], align 88085// CHECK13-NEXT: store i32 12, ptr [[LIN]], align 48086// CHECK13-NEXT: store i64 0, ptr [[DOTOMP_LB21]], align 88087// CHECK13-NEXT: store i64 3, ptr [[DOTOMP_UB22]], align 88088// CHECK13-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_LB21]], align 88089// CHECK13-NEXT: store i64 [[TMP21]], ptr [[DOTOMP_IV23]], align 88090// CHECK13-NEXT: [[TMP22:%.*]] = load i32, ptr [[LIN]], align 48091// CHECK13-NEXT: store i32 [[TMP22]], ptr [[DOTLINEAR_START24]], align 48092// CHECK13-NEXT: [[TMP23:%.*]] = load i32, ptr [[A]], align 48093// CHECK13-NEXT: store i32 [[TMP23]], ptr [[DOTLINEAR_START25]], align 48094// CHECK13-NEXT: [[CALL26:%.*]] = call noundef i64 @_Z7get_valv()8095// CHECK13-NEXT: store i64 [[CALL26]], ptr [[DOTLINEAR_STEP]], align 88096// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]]8097// CHECK13: omp.inner.for.cond29:8098// CHECK13-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9:![0-9]+]]8099// CHECK13-NEXT: [[TMP25:%.*]] = load i64, ptr [[DOTOMP_UB22]], align 8, !llvm.access.group [[ACC_GRP9]]8100// CHECK13-NEXT: [[CMP30:%.*]] = icmp ule i64 [[TMP24]], [[TMP25]]8101// CHECK13-NEXT: br i1 [[CMP30]], label [[OMP_INNER_FOR_BODY31:%.*]], label [[OMP_INNER_FOR_END48:%.*]]8102// CHECK13: omp.inner.for.body31:8103// CHECK13-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]]8104// CHECK13-NEXT: [[MUL32:%.*]] = mul i64 [[TMP26]], 4008105// CHECK13-NEXT: [[SUB33:%.*]] = sub i64 2000, [[MUL32]]8106// CHECK13-NEXT: store i64 [[SUB33]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP9]]8107// CHECK13-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTLINEAR_START24]], align 4, !llvm.access.group [[ACC_GRP9]]8108// CHECK13-NEXT: [[CONV34:%.*]] = sext i32 [[TMP27]] to i648109// CHECK13-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]]8110// CHECK13-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP9]]8111// CHECK13-NEXT: [[MUL35:%.*]] = mul i64 [[TMP28]], [[TMP29]]8112// CHECK13-NEXT: [[ADD36:%.*]] = add i64 [[CONV34]], [[MUL35]]8113// CHECK13-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i328114// CHECK13-NEXT: store i32 [[CONV37]], ptr [[LIN27]], align 4, !llvm.access.group [[ACC_GRP9]]8115// CHECK13-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTLINEAR_START25]], align 4, !llvm.access.group [[ACC_GRP9]]8116// CHECK13-NEXT: [[CONV38:%.*]] = sext i32 [[TMP30]] to i648117// CHECK13-NEXT: [[TMP31:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]]8118// CHECK13-NEXT: [[TMP32:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP9]]8119// CHECK13-NEXT: [[MUL39:%.*]] = mul i64 [[TMP31]], [[TMP32]]8120// CHECK13-NEXT: [[ADD40:%.*]] = add i64 [[CONV38]], [[MUL39]]8121// CHECK13-NEXT: [[CONV41:%.*]] = trunc i64 [[ADD40]] to i328122// CHECK13-NEXT: store i32 [[CONV41]], ptr [[A28]], align 4, !llvm.access.group [[ACC_GRP9]]8123// CHECK13-NEXT: [[TMP33:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP9]]8124// CHECK13-NEXT: [[CONV42:%.*]] = sext i16 [[TMP33]] to i328125// CHECK13-NEXT: [[ADD43:%.*]] = add nsw i32 [[CONV42]], 18126// CHECK13-NEXT: [[CONV44:%.*]] = trunc i32 [[ADD43]] to i168127// CHECK13-NEXT: store i16 [[CONV44]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP9]]8128// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE45:%.*]]8129// CHECK13: omp.body.continue45:8130// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC46:%.*]]8131// CHECK13: omp.inner.for.inc46:8132// CHECK13-NEXT: [[TMP34:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]]8133// CHECK13-NEXT: [[ADD47:%.*]] = add i64 [[TMP34]], 18134// CHECK13-NEXT: store i64 [[ADD47]], ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]]8135// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP10:![0-9]+]]8136// CHECK13: omp.inner.for.end48:8137// CHECK13-NEXT: store i64 400, ptr [[IT]], align 88138// CHECK13-NEXT: [[TMP35:%.*]] = load i32, ptr [[LIN27]], align 48139// CHECK13-NEXT: store i32 [[TMP35]], ptr [[LIN]], align 48140// CHECK13-NEXT: [[TMP36:%.*]] = load i32, ptr [[A28]], align 48141// CHECK13-NEXT: store i32 [[TMP36]], ptr [[A]], align 48142// CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB50]], align 48143// CHECK13-NEXT: store i32 3, ptr [[DOTOMP_UB51]], align 48144// CHECK13-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTOMP_LB50]], align 48145// CHECK13-NEXT: store i32 [[TMP37]], ptr [[DOTOMP_IV52]], align 48146// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND54:%.*]]8147// CHECK13: omp.inner.for.cond54:8148// CHECK13-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]]8149// CHECK13-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTOMP_UB51]], align 4, !llvm.access.group [[ACC_GRP12]]8150// CHECK13-NEXT: [[CMP55:%.*]] = icmp sle i32 [[TMP38]], [[TMP39]]8151// CHECK13-NEXT: br i1 [[CMP55]], label [[OMP_INNER_FOR_BODY56:%.*]], label [[OMP_INNER_FOR_END67:%.*]]8152// CHECK13: omp.inner.for.body56:8153// CHECK13-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP12]]8154// CHECK13-NEXT: [[MUL57:%.*]] = mul nsw i32 [[TMP40]], 48155// CHECK13-NEXT: [[ADD58:%.*]] = add nsw i32 6, [[MUL57]]8156// CHECK13-NEXT: [[CONV59:%.*]] = trunc i32 [[ADD58]] to i168157// CHECK13-NEXT: store i16 [[CONV59]], ptr [[IT53]], align 2, !llvm.access.group [[ACC_GRP12]]8158// CHECK13-NEXT: [[TMP41:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP12]]8159// CHECK13-NEXT: [[ADD60:%.*]] = add nsw i32 [[TMP41]], 18160// CHECK13-NEXT: store i32 [[ADD60]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP12]]8161// CHECK13-NEXT: [[TMP42:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP12]]8162// CHECK13-NEXT: [[CONV61:%.*]] = sext i16 [[TMP42]] to i328163// CHECK13-NEXT: [[ADD62:%.*]] = add nsw i32 [[CONV61]], 18164// CHECK13-NEXT: [[CONV63:%.*]] = trunc i32 [[ADD62]] to i168165// CHECK13-NEXT: store i16 [[CONV63]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP12]]8166// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE64:%.*]]8167// CHECK13: omp.body.continue64:8168// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC65:%.*]]8169// CHECK13: omp.inner.for.inc65:8170// CHECK13-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP12]]8171// CHECK13-NEXT: [[ADD66:%.*]] = add nsw i32 [[TMP43]], 18172// CHECK13-NEXT: store i32 [[ADD66]], ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP12]]8173// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND54]], !llvm.loop [[LOOP13:![0-9]+]]8174// CHECK13: omp.inner.for.end67:8175// CHECK13-NEXT: store i16 22, ptr [[IT53]], align 28176// CHECK13-NEXT: [[TMP44:%.*]] = load i32, ptr [[A]], align 48177// CHECK13-NEXT: store i32 [[TMP44]], ptr [[DOTCAPTURE_EXPR_]], align 48178// CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB69]], align 48179// CHECK13-NEXT: store i32 25, ptr [[DOTOMP_UB70]], align 48180// CHECK13-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTOMP_LB69]], align 48181// CHECK13-NEXT: store i32 [[TMP45]], ptr [[DOTOMP_IV71]], align 48182// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND73:%.*]]8183// CHECK13: omp.inner.for.cond73:8184// CHECK13-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15:![0-9]+]]8185// CHECK13-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTOMP_UB70]], align 4, !llvm.access.group [[ACC_GRP15]]8186// CHECK13-NEXT: [[CMP74:%.*]] = icmp sle i32 [[TMP46]], [[TMP47]]8187// CHECK13-NEXT: br i1 [[CMP74]], label [[OMP_INNER_FOR_BODY75:%.*]], label [[OMP_INNER_FOR_END100:%.*]]8188// CHECK13: omp.inner.for.body75:8189// CHECK13-NEXT: [[TMP48:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15]]8190// CHECK13-NEXT: [[MUL76:%.*]] = mul nsw i32 [[TMP48]], 18191// CHECK13-NEXT: [[SUB77:%.*]] = sub nsw i32 122, [[MUL76]]8192// CHECK13-NEXT: [[CONV78:%.*]] = trunc i32 [[SUB77]] to i88193// CHECK13-NEXT: store i8 [[CONV78]], ptr [[IT72]], align 1, !llvm.access.group [[ACC_GRP15]]8194// CHECK13-NEXT: [[TMP49:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP15]]8195// CHECK13-NEXT: [[ADD79:%.*]] = add nsw i32 [[TMP49]], 18196// CHECK13-NEXT: store i32 [[ADD79]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP15]]8197// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i64 0, i64 28198// CHECK13-NEXT: [[TMP50:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP15]]8199// CHECK13-NEXT: [[CONV80:%.*]] = fpext float [[TMP50]] to double8200// CHECK13-NEXT: [[ADD81:%.*]] = fadd double [[CONV80]], 1.000000e+008201// CHECK13-NEXT: [[CONV82:%.*]] = fptrunc double [[ADD81]] to float8202// CHECK13-NEXT: store float [[CONV82]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP15]]8203// CHECK13-NEXT: [[ARRAYIDX83:%.*]] = getelementptr inbounds float, ptr [[VLA]], i64 38204// CHECK13-NEXT: [[TMP51:%.*]] = load float, ptr [[ARRAYIDX83]], align 4, !llvm.access.group [[ACC_GRP15]]8205// CHECK13-NEXT: [[CONV84:%.*]] = fpext float [[TMP51]] to double8206// CHECK13-NEXT: [[ADD85:%.*]] = fadd double [[CONV84]], 1.000000e+008207// CHECK13-NEXT: [[CONV86:%.*]] = fptrunc double [[ADD85]] to float8208// CHECK13-NEXT: store float [[CONV86]], ptr [[ARRAYIDX83]], align 4, !llvm.access.group [[ACC_GRP15]]8209// CHECK13-NEXT: [[ARRAYIDX87:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i64 0, i64 18210// CHECK13-NEXT: [[ARRAYIDX88:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX87]], i64 0, i64 28211// CHECK13-NEXT: [[TMP52:%.*]] = load double, ptr [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP15]]8212// CHECK13-NEXT: [[ADD89:%.*]] = fadd double [[TMP52]], 1.000000e+008213// CHECK13-NEXT: store double [[ADD89]], ptr [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP15]]8214// CHECK13-NEXT: [[TMP53:%.*]] = mul nsw i64 1, [[TMP4]]8215// CHECK13-NEXT: [[ARRAYIDX90:%.*]] = getelementptr inbounds double, ptr [[VLA1]], i64 [[TMP53]]8216// CHECK13-NEXT: [[ARRAYIDX91:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX90]], i64 38217// CHECK13-NEXT: [[TMP54:%.*]] = load double, ptr [[ARRAYIDX91]], align 8, !llvm.access.group [[ACC_GRP15]]8218// CHECK13-NEXT: [[ADD92:%.*]] = fadd double [[TMP54]], 1.000000e+008219// CHECK13-NEXT: store double [[ADD92]], ptr [[ARRAYIDX91]], align 8, !llvm.access.group [[ACC_GRP15]]8220// CHECK13-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D]], i32 0, i32 08221// CHECK13-NEXT: [[TMP55:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP15]]8222// CHECK13-NEXT: [[ADD93:%.*]] = add nsw i64 [[TMP55]], 18223// CHECK13-NEXT: store i64 [[ADD93]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP15]]8224// CHECK13-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D]], i32 0, i32 18225// CHECK13-NEXT: [[TMP56:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP15]]8226// CHECK13-NEXT: [[CONV94:%.*]] = sext i8 [[TMP56]] to i328227// CHECK13-NEXT: [[ADD95:%.*]] = add nsw i32 [[CONV94]], 18228// CHECK13-NEXT: [[CONV96:%.*]] = trunc i32 [[ADD95]] to i88229// CHECK13-NEXT: store i8 [[CONV96]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP15]]8230// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE97:%.*]]8231// CHECK13: omp.body.continue97:8232// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC98:%.*]]8233// CHECK13: omp.inner.for.inc98:8234// CHECK13-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15]]8235// CHECK13-NEXT: [[ADD99:%.*]] = add nsw i32 [[TMP57]], 18236// CHECK13-NEXT: store i32 [[ADD99]], ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15]]8237// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND73]], !llvm.loop [[LOOP16:![0-9]+]]8238// CHECK13: omp.inner.for.end100:8239// CHECK13-NEXT: store i8 96, ptr [[IT72]], align 18240// CHECK13-NEXT: [[TMP58:%.*]] = load i32, ptr [[A]], align 48241// CHECK13-NEXT: [[TMP59:%.*]] = load ptr, ptr [[SAVED_STACK]], align 88242// CHECK13-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP59]])8243// CHECK13-NEXT: ret i32 [[TMP58]]8244//8245//8246// CHECK13-LABEL: define {{[^@]+}}@_Z3bari8247// CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {8248// CHECK13-NEXT: entry:8249// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 48250// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 48251// CHECK13-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 88252// CHECK13-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 48253// CHECK13-NEXT: store i32 0, ptr [[A]], align 48254// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 48255// CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]])8256// CHECK13-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 48257// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]8258// CHECK13-NEXT: store i32 [[ADD]], ptr [[A]], align 48259// CHECK13-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 48260// CHECK13-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]])8261// CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 48262// CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]8263// CHECK13-NEXT: store i32 [[ADD2]], ptr [[A]], align 48264// CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 48265// CHECK13-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]])8266// CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 48267// CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]8268// CHECK13-NEXT: store i32 [[ADD4]], ptr [[A]], align 48269// CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 48270// CHECK13-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]])8271// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 48272// CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]8273// CHECK13-NEXT: store i32 [[ADD6]], ptr [[A]], align 48274// CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 48275// CHECK13-NEXT: ret i32 [[TMP8]]8276//8277//8278// CHECK13-LABEL: define {{[^@]+}}@_ZN2S12r1Ei8279// CHECK13-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {8280// CHECK13-NEXT: entry:8281// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 88282// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 48283// CHECK13-NEXT: [[B:%.*]] = alloca i32, align 48284// CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 88285// CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 88286// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 18287// CHECK13-NEXT: [[TMP:%.*]] = alloca i64, align 88288// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 88289// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 88290// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 88291// CHECK13-NEXT: [[IT:%.*]] = alloca i64, align 88292// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 88293// CHECK13-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 48294// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 88295// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 48296// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 18297// CHECK13-NEXT: store i32 [[ADD]], ptr [[B]], align 48298// CHECK13-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 48299// CHECK13-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i648300// CHECK13-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()8301// CHECK13-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 88302// CHECK13-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]8303// CHECK13-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 28304// CHECK13-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 88305// CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 48306// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 608307// CHECK13-NEXT: [[STOREDV:%.*]] = zext i1 [[CMP]] to i88308// CHECK13-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_]], align 18309// CHECK13-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 88310// CHECK13-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 88311// CHECK13-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 88312// CHECK13-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 88313// CHECK13-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 18314// CHECK13-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP7]] to i18315// CHECK13-NEXT: br i1 [[LOADEDV]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]8316// CHECK13: omp_if.then:8317// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]8318// CHECK13: omp.inner.for.cond:8319// CHECK13-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18:![0-9]+]]8320// CHECK13-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP18]]8321// CHECK13-NEXT: [[CMP2:%.*]] = icmp ule i64 [[TMP8]], [[TMP9]]8322// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]8323// CHECK13: omp.inner.for.body:8324// CHECK13-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]]8325// CHECK13-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 4008326// CHECK13-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]8327// CHECK13-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP18]]8328// CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[B]], align 4, !llvm.access.group [[ACC_GRP18]]8329// CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP11]] to double8330// CHECK13-NEXT: [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+008331// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 08332// CHECK13-NEXT: store double [[ADD3]], ptr [[A]], align 8, !nontemporal [[META19:![0-9]+]], !llvm.access.group [[ACC_GRP18]]8333// CHECK13-NEXT: [[A4:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 08334// CHECK13-NEXT: [[TMP12:%.*]] = load double, ptr [[A4]], align 8, !nontemporal [[META19]], !llvm.access.group [[ACC_GRP18]]8335// CHECK13-NEXT: [[INC:%.*]] = fadd double [[TMP12]], 1.000000e+008336// CHECK13-NEXT: store double [[INC]], ptr [[A4]], align 8, !nontemporal [[META19]], !llvm.access.group [[ACC_GRP18]]8337// CHECK13-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i168338// CHECK13-NEXT: [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]]8339// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP13]]8340// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 18341// CHECK13-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP18]]8342// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]8343// CHECK13: omp.body.continue:8344// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]8345// CHECK13: omp.inner.for.inc:8346// CHECK13-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]]8347// CHECK13-NEXT: [[ADD7:%.*]] = add i64 [[TMP14]], 18348// CHECK13-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]]8349// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]8350// CHECK13: omp.inner.for.end:8351// CHECK13-NEXT: br label [[OMP_IF_END:%.*]]8352// CHECK13: omp_if.else:8353// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND8:%.*]]8354// CHECK13: omp.inner.for.cond8:8355// CHECK13-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 88356// CHECK13-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_UB]], align 88357// CHECK13-NEXT: [[CMP9:%.*]] = icmp ule i64 [[TMP15]], [[TMP16]]8358// CHECK13-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY10:%.*]], label [[OMP_INNER_FOR_END24:%.*]]8359// CHECK13: omp.inner.for.body10:8360// CHECK13-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 88361// CHECK13-NEXT: [[MUL11:%.*]] = mul i64 [[TMP17]], 4008362// CHECK13-NEXT: [[SUB12:%.*]] = sub i64 2000, [[MUL11]]8363// CHECK13-NEXT: store i64 [[SUB12]], ptr [[IT]], align 88364// CHECK13-NEXT: [[TMP18:%.*]] = load i32, ptr [[B]], align 48365// CHECK13-NEXT: [[CONV13:%.*]] = sitofp i32 [[TMP18]] to double8366// CHECK13-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.500000e+008367// CHECK13-NEXT: [[A15:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 08368// CHECK13-NEXT: store double [[ADD14]], ptr [[A15]], align 88369// CHECK13-NEXT: [[A16:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 08370// CHECK13-NEXT: [[TMP19:%.*]] = load double, ptr [[A16]], align 88371// CHECK13-NEXT: [[INC17:%.*]] = fadd double [[TMP19]], 1.000000e+008372// CHECK13-NEXT: store double [[INC17]], ptr [[A16]], align 88373// CHECK13-NEXT: [[CONV18:%.*]] = fptosi double [[INC17]] to i168374// CHECK13-NEXT: [[TMP20:%.*]] = mul nsw i64 1, [[TMP2]]8375// CHECK13-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP20]]8376// CHECK13-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX19]], i64 18377// CHECK13-NEXT: store i16 [[CONV18]], ptr [[ARRAYIDX20]], align 28378// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE21:%.*]]8379// CHECK13: omp.body.continue21:8380// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC22:%.*]]8381// CHECK13: omp.inner.for.inc22:8382// CHECK13-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_IV]], align 88383// CHECK13-NEXT: [[ADD23:%.*]] = add i64 [[TMP21]], 18384// CHECK13-NEXT: store i64 [[ADD23]], ptr [[DOTOMP_IV]], align 88385// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP22:![0-9]+]]8386// CHECK13: omp.inner.for.end24:8387// CHECK13-NEXT: br label [[OMP_IF_END]]8388// CHECK13: omp_if.end:8389// CHECK13-NEXT: store i64 400, ptr [[IT]], align 88390// CHECK13-NEXT: [[TMP22:%.*]] = mul nsw i64 1, [[TMP2]]8391// CHECK13-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP22]]8392// CHECK13-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX25]], i64 18393// CHECK13-NEXT: [[TMP23:%.*]] = load i16, ptr [[ARRAYIDX26]], align 28394// CHECK13-NEXT: [[CONV27:%.*]] = sext i16 [[TMP23]] to i328395// CHECK13-NEXT: [[TMP24:%.*]] = load i32, ptr [[B]], align 48396// CHECK13-NEXT: [[ADD28:%.*]] = add nsw i32 [[CONV27]], [[TMP24]]8397// CHECK13-NEXT: [[TMP25:%.*]] = load ptr, ptr [[SAVED_STACK]], align 88398// CHECK13-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP25]])8399// CHECK13-NEXT: ret i32 [[ADD28]]8400//8401//8402// CHECK13-LABEL: define {{[^@]+}}@_ZL7fstatici8403// CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {8404// CHECK13-NEXT: entry:8405// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 48406// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 48407// CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 28408// CHECK13-NEXT: [[AAA:%.*]] = alloca i8, align 18409// CHECK13-NEXT: [[B:%.*]] = alloca [10 x i32], align 48410// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 48411// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 48412// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 48413// CHECK13-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 48414// CHECK13-NEXT: store i32 0, ptr [[A]], align 48415// CHECK13-NEXT: store i16 0, ptr [[AA]], align 28416// CHECK13-NEXT: store i8 0, ptr [[AAA]], align 18417// CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 48418// CHECK13-NEXT: store i32 429496720, ptr [[DOTOMP_UB]], align 48419// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 48420// CHECK13-NEXT: ret i32 [[TMP0]]8421//8422//8423// CHECK13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i8424// CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {8425// CHECK13-NEXT: entry:8426// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 48427// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 48428// CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 28429// CHECK13-NEXT: [[B:%.*]] = alloca [10 x i32], align 48430// CHECK13-NEXT: [[TMP:%.*]] = alloca i64, align 88431// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 88432// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 88433// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 88434// CHECK13-NEXT: [[I:%.*]] = alloca i64, align 88435// CHECK13-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 48436// CHECK13-NEXT: store i32 0, ptr [[A]], align 48437// CHECK13-NEXT: store i16 0, ptr [[AA]], align 28438// CHECK13-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 88439// CHECK13-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 88440// CHECK13-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTOMP_LB]], align 88441// CHECK13-NEXT: store i64 [[TMP0]], ptr [[DOTOMP_IV]], align 88442// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]8443// CHECK13: omp.inner.for.cond:8444// CHECK13-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP24:![0-9]+]]8445// CHECK13-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP24]]8446// CHECK13-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]]8447// CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]8448// CHECK13: omp.inner.for.body:8449// CHECK13-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP24]]8450// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 38451// CHECK13-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]8452// CHECK13-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP24]]8453// CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP24]]8454// CHECK13-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 18455// CHECK13-NEXT: store i32 [[ADD1]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP24]]8456// CHECK13-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP24]]8457// CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i328458// CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 18459// CHECK13-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i168460// CHECK13-NEXT: store i16 [[CONV3]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP24]]8461// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i64 0, i64 28462// CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]]8463// CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 18464// CHECK13-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]]8465// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]8466// CHECK13: omp.body.continue:8467// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]8468// CHECK13: omp.inner.for.inc:8469// CHECK13-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP24]]8470// CHECK13-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 18471// CHECK13-NEXT: store i64 [[ADD5]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP24]]8472// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]8473// CHECK13: omp.inner.for.end:8474// CHECK13-NEXT: store i64 11, ptr [[I]], align 88475// CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 48476// CHECK13-NEXT: ret i32 [[TMP8]]8477//8478//8479// CHECK15-LABEL: define {{[^@]+}}@_Z7get_valv8480// CHECK15-SAME: () #[[ATTR0:[0-9]+]] {8481// CHECK15-NEXT: entry:8482// CHECK15-NEXT: ret i64 08483//8484//8485// CHECK15-LABEL: define {{[^@]+}}@_Z3fooi8486// CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {8487// CHECK15-NEXT: entry:8488// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 48489// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 48490// CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 28491// CHECK15-NEXT: [[B:%.*]] = alloca [10 x float], align 48492// CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 48493// CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 48494// CHECK15-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 88495// CHECK15-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 48496// CHECK15-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 48497// CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 48498// CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 48499// CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 48500// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 48501// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 48502// CHECK15-NEXT: [[K:%.*]] = alloca i64, align 88503// CHECK15-NEXT: [[_TMP3:%.*]] = alloca i32, align 48504// CHECK15-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 48505// CHECK15-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 48506// CHECK15-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 48507// CHECK15-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 88508// CHECK15-NEXT: [[I7:%.*]] = alloca i32, align 48509// CHECK15-NEXT: [[K8:%.*]] = alloca i64, align 88510// CHECK15-NEXT: [[LIN:%.*]] = alloca i32, align 48511// CHECK15-NEXT: [[_TMP20:%.*]] = alloca i64, align 48512// CHECK15-NEXT: [[DOTOMP_LB21:%.*]] = alloca i64, align 88513// CHECK15-NEXT: [[DOTOMP_UB22:%.*]] = alloca i64, align 88514// CHECK15-NEXT: [[DOTOMP_IV23:%.*]] = alloca i64, align 88515// CHECK15-NEXT: [[DOTLINEAR_START24:%.*]] = alloca i32, align 48516// CHECK15-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 48517// CHECK15-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 88518// CHECK15-NEXT: [[IT:%.*]] = alloca i64, align 88519// CHECK15-NEXT: [[LIN27:%.*]] = alloca i32, align 48520// CHECK15-NEXT: [[A28:%.*]] = alloca i32, align 48521// CHECK15-NEXT: [[_TMP49:%.*]] = alloca i16, align 28522// CHECK15-NEXT: [[DOTOMP_LB50:%.*]] = alloca i32, align 48523// CHECK15-NEXT: [[DOTOMP_UB51:%.*]] = alloca i32, align 48524// CHECK15-NEXT: [[DOTOMP_IV52:%.*]] = alloca i32, align 48525// CHECK15-NEXT: [[IT53:%.*]] = alloca i16, align 28526// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 48527// CHECK15-NEXT: [[_TMP68:%.*]] = alloca i8, align 18528// CHECK15-NEXT: [[DOTOMP_LB69:%.*]] = alloca i32, align 48529// CHECK15-NEXT: [[DOTOMP_UB70:%.*]] = alloca i32, align 48530// CHECK15-NEXT: [[DOTOMP_IV71:%.*]] = alloca i32, align 48531// CHECK15-NEXT: [[IT72:%.*]] = alloca i8, align 18532// CHECK15-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 48533// CHECK15-NEXT: store i32 0, ptr [[A]], align 48534// CHECK15-NEXT: store i16 0, ptr [[AA]], align 28535// CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 48536// CHECK15-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()8537// CHECK15-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 48538// CHECK15-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 48539// CHECK15-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 48540// CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 48541// CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]8542// CHECK15-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 88543// CHECK15-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 48544// CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 48545// CHECK15-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 48546// CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 48547// CHECK15-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 48548// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]8549// CHECK15: omp.inner.for.cond:8550// CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]]8551// CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]]8552// CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]8553// CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]8554// CHECK15: omp.inner.for.body:8555// CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]8556// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 58557// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]8558// CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]8559// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]8560// CHECK15: omp.body.continue:8561// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]8562// CHECK15: omp.inner.for.inc:8563// CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]8564// CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 18565// CHECK15-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]8566// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]8567// CHECK15: omp.inner.for.end:8568// CHECK15-NEXT: store i32 33, ptr [[I]], align 48569// CHECK15-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()8570// CHECK15-NEXT: store i64 [[CALL]], ptr [[K]], align 88571// CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB4]], align 48572// CHECK15-NEXT: store i32 8, ptr [[DOTOMP_UB5]], align 48573// CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB4]], align 48574// CHECK15-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV6]], align 48575// CHECK15-NEXT: [[TMP10:%.*]] = load i64, ptr [[K]], align 88576// CHECK15-NEXT: store i64 [[TMP10]], ptr [[DOTLINEAR_START]], align 88577// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]]8578// CHECK15: omp.inner.for.cond9:8579// CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]]8580// CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB5]], align 4, !llvm.access.group [[ACC_GRP7]]8581// CHECK15-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]8582// CHECK15-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]]8583// CHECK15: omp.inner.for.body11:8584// CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7]]8585// CHECK15-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP13]], 18586// CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]]8587// CHECK15-NEXT: store i32 [[SUB]], ptr [[I7]], align 4, !llvm.access.group [[ACC_GRP7]]8588// CHECK15-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP7]]8589// CHECK15-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7]]8590// CHECK15-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 38591// CHECK15-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i648592// CHECK15-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP14]], [[CONV]]8593// CHECK15-NEXT: store i64 [[ADD14]], ptr [[K8]], align 8, !llvm.access.group [[ACC_GRP7]]8594// CHECK15-NEXT: [[TMP16:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP7]]8595// CHECK15-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 18596// CHECK15-NEXT: store i32 [[ADD15]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP7]]8597// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]]8598// CHECK15: omp.body.continue16:8599// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]]8600// CHECK15: omp.inner.for.inc17:8601// CHECK15-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7]]8602// CHECK15-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP17]], 18603// CHECK15-NEXT: store i32 [[ADD18]], ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7]]8604// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP8:![0-9]+]]8605// CHECK15: omp.inner.for.end19:8606// CHECK15-NEXT: store i32 1, ptr [[I7]], align 48607// CHECK15-NEXT: [[TMP18:%.*]] = load i64, ptr [[K8]], align 88608// CHECK15-NEXT: store i64 [[TMP18]], ptr [[K]], align 88609// CHECK15-NEXT: store i32 12, ptr [[LIN]], align 48610// CHECK15-NEXT: store i64 0, ptr [[DOTOMP_LB21]], align 88611// CHECK15-NEXT: store i64 3, ptr [[DOTOMP_UB22]], align 88612// CHECK15-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_LB21]], align 88613// CHECK15-NEXT: store i64 [[TMP19]], ptr [[DOTOMP_IV23]], align 88614// CHECK15-NEXT: [[TMP20:%.*]] = load i32, ptr [[LIN]], align 48615// CHECK15-NEXT: store i32 [[TMP20]], ptr [[DOTLINEAR_START24]], align 48616// CHECK15-NEXT: [[TMP21:%.*]] = load i32, ptr [[A]], align 48617// CHECK15-NEXT: store i32 [[TMP21]], ptr [[DOTLINEAR_START25]], align 48618// CHECK15-NEXT: [[CALL26:%.*]] = call noundef i64 @_Z7get_valv()8619// CHECK15-NEXT: store i64 [[CALL26]], ptr [[DOTLINEAR_STEP]], align 88620// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]]8621// CHECK15: omp.inner.for.cond29:8622// CHECK15-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10:![0-9]+]]8623// CHECK15-NEXT: [[TMP23:%.*]] = load i64, ptr [[DOTOMP_UB22]], align 8, !llvm.access.group [[ACC_GRP10]]8624// CHECK15-NEXT: [[CMP30:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]]8625// CHECK15-NEXT: br i1 [[CMP30]], label [[OMP_INNER_FOR_BODY31:%.*]], label [[OMP_INNER_FOR_END48:%.*]]8626// CHECK15: omp.inner.for.body31:8627// CHECK15-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]]8628// CHECK15-NEXT: [[MUL32:%.*]] = mul i64 [[TMP24]], 4008629// CHECK15-NEXT: [[SUB33:%.*]] = sub i64 2000, [[MUL32]]8630// CHECK15-NEXT: store i64 [[SUB33]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP10]]8631// CHECK15-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTLINEAR_START24]], align 4, !llvm.access.group [[ACC_GRP10]]8632// CHECK15-NEXT: [[CONV34:%.*]] = sext i32 [[TMP25]] to i648633// CHECK15-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]]8634// CHECK15-NEXT: [[TMP27:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP10]]8635// CHECK15-NEXT: [[MUL35:%.*]] = mul i64 [[TMP26]], [[TMP27]]8636// CHECK15-NEXT: [[ADD36:%.*]] = add i64 [[CONV34]], [[MUL35]]8637// CHECK15-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i328638// CHECK15-NEXT: store i32 [[CONV37]], ptr [[LIN27]], align 4, !llvm.access.group [[ACC_GRP10]]8639// CHECK15-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTLINEAR_START25]], align 4, !llvm.access.group [[ACC_GRP10]]8640// CHECK15-NEXT: [[CONV38:%.*]] = sext i32 [[TMP28]] to i648641// CHECK15-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]]8642// CHECK15-NEXT: [[TMP30:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP10]]8643// CHECK15-NEXT: [[MUL39:%.*]] = mul i64 [[TMP29]], [[TMP30]]8644// CHECK15-NEXT: [[ADD40:%.*]] = add i64 [[CONV38]], [[MUL39]]8645// CHECK15-NEXT: [[CONV41:%.*]] = trunc i64 [[ADD40]] to i328646// CHECK15-NEXT: store i32 [[CONV41]], ptr [[A28]], align 4, !llvm.access.group [[ACC_GRP10]]8647// CHECK15-NEXT: [[TMP31:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP10]]8648// CHECK15-NEXT: [[CONV42:%.*]] = sext i16 [[TMP31]] to i328649// CHECK15-NEXT: [[ADD43:%.*]] = add nsw i32 [[CONV42]], 18650// CHECK15-NEXT: [[CONV44:%.*]] = trunc i32 [[ADD43]] to i168651// CHECK15-NEXT: store i16 [[CONV44]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP10]]8652// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE45:%.*]]8653// CHECK15: omp.body.continue45:8654// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC46:%.*]]8655// CHECK15: omp.inner.for.inc46:8656// CHECK15-NEXT: [[TMP32:%.*]] = load i64, ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]]8657// CHECK15-NEXT: [[ADD47:%.*]] = add i64 [[TMP32]], 18658// CHECK15-NEXT: store i64 [[ADD47]], ptr [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]]8659// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP11:![0-9]+]]8660// CHECK15: omp.inner.for.end48:8661// CHECK15-NEXT: store i64 400, ptr [[IT]], align 88662// CHECK15-NEXT: [[TMP33:%.*]] = load i32, ptr [[LIN27]], align 48663// CHECK15-NEXT: store i32 [[TMP33]], ptr [[LIN]], align 48664// CHECK15-NEXT: [[TMP34:%.*]] = load i32, ptr [[A28]], align 48665// CHECK15-NEXT: store i32 [[TMP34]], ptr [[A]], align 48666// CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB50]], align 48667// CHECK15-NEXT: store i32 3, ptr [[DOTOMP_UB51]], align 48668// CHECK15-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_LB50]], align 48669// CHECK15-NEXT: store i32 [[TMP35]], ptr [[DOTOMP_IV52]], align 48670// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND54:%.*]]8671// CHECK15: omp.inner.for.cond54:8672// CHECK15-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP13:![0-9]+]]8673// CHECK15-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTOMP_UB51]], align 4, !llvm.access.group [[ACC_GRP13]]8674// CHECK15-NEXT: [[CMP55:%.*]] = icmp sle i32 [[TMP36]], [[TMP37]]8675// CHECK15-NEXT: br i1 [[CMP55]], label [[OMP_INNER_FOR_BODY56:%.*]], label [[OMP_INNER_FOR_END67:%.*]]8676// CHECK15: omp.inner.for.body56:8677// CHECK15-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP13]]8678// CHECK15-NEXT: [[MUL57:%.*]] = mul nsw i32 [[TMP38]], 48679// CHECK15-NEXT: [[ADD58:%.*]] = add nsw i32 6, [[MUL57]]8680// CHECK15-NEXT: [[CONV59:%.*]] = trunc i32 [[ADD58]] to i168681// CHECK15-NEXT: store i16 [[CONV59]], ptr [[IT53]], align 2, !llvm.access.group [[ACC_GRP13]]8682// CHECK15-NEXT: [[TMP39:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP13]]8683// CHECK15-NEXT: [[ADD60:%.*]] = add nsw i32 [[TMP39]], 18684// CHECK15-NEXT: store i32 [[ADD60]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP13]]8685// CHECK15-NEXT: [[TMP40:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP13]]8686// CHECK15-NEXT: [[CONV61:%.*]] = sext i16 [[TMP40]] to i328687// CHECK15-NEXT: [[ADD62:%.*]] = add nsw i32 [[CONV61]], 18688// CHECK15-NEXT: [[CONV63:%.*]] = trunc i32 [[ADD62]] to i168689// CHECK15-NEXT: store i16 [[CONV63]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP13]]8690// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE64:%.*]]8691// CHECK15: omp.body.continue64:8692// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC65:%.*]]8693// CHECK15: omp.inner.for.inc65:8694// CHECK15-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP13]]8695// CHECK15-NEXT: [[ADD66:%.*]] = add nsw i32 [[TMP41]], 18696// CHECK15-NEXT: store i32 [[ADD66]], ptr [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP13]]8697// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND54]], !llvm.loop [[LOOP14:![0-9]+]]8698// CHECK15: omp.inner.for.end67:8699// CHECK15-NEXT: store i16 22, ptr [[IT53]], align 28700// CHECK15-NEXT: [[TMP42:%.*]] = load i32, ptr [[A]], align 48701// CHECK15-NEXT: store i32 [[TMP42]], ptr [[DOTCAPTURE_EXPR_]], align 48702// CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB69]], align 48703// CHECK15-NEXT: store i32 25, ptr [[DOTOMP_UB70]], align 48704// CHECK15-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTOMP_LB69]], align 48705// CHECK15-NEXT: store i32 [[TMP43]], ptr [[DOTOMP_IV71]], align 48706// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND73:%.*]]8707// CHECK15: omp.inner.for.cond73:8708// CHECK15-NEXT: [[TMP44:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16:![0-9]+]]8709// CHECK15-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTOMP_UB70]], align 4, !llvm.access.group [[ACC_GRP16]]8710// CHECK15-NEXT: [[CMP74:%.*]] = icmp sle i32 [[TMP44]], [[TMP45]]8711// CHECK15-NEXT: br i1 [[CMP74]], label [[OMP_INNER_FOR_BODY75:%.*]], label [[OMP_INNER_FOR_END100:%.*]]8712// CHECK15: omp.inner.for.body75:8713// CHECK15-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16]]8714// CHECK15-NEXT: [[MUL76:%.*]] = mul nsw i32 [[TMP46]], 18715// CHECK15-NEXT: [[SUB77:%.*]] = sub nsw i32 122, [[MUL76]]8716// CHECK15-NEXT: [[CONV78:%.*]] = trunc i32 [[SUB77]] to i88717// CHECK15-NEXT: store i8 [[CONV78]], ptr [[IT72]], align 1, !llvm.access.group [[ACC_GRP16]]8718// CHECK15-NEXT: [[TMP47:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP16]]8719// CHECK15-NEXT: [[ADD79:%.*]] = add nsw i32 [[TMP47]], 18720// CHECK15-NEXT: store i32 [[ADD79]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP16]]8721// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i32 0, i32 28722// CHECK15-NEXT: [[TMP48:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]]8723// CHECK15-NEXT: [[CONV80:%.*]] = fpext float [[TMP48]] to double8724// CHECK15-NEXT: [[ADD81:%.*]] = fadd double [[CONV80]], 1.000000e+008725// CHECK15-NEXT: [[CONV82:%.*]] = fptrunc double [[ADD81]] to float8726// CHECK15-NEXT: store float [[CONV82]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]]8727// CHECK15-NEXT: [[ARRAYIDX83:%.*]] = getelementptr inbounds float, ptr [[VLA]], i32 38728// CHECK15-NEXT: [[TMP49:%.*]] = load float, ptr [[ARRAYIDX83]], align 4, !llvm.access.group [[ACC_GRP16]]8729// CHECK15-NEXT: [[CONV84:%.*]] = fpext float [[TMP49]] to double8730// CHECK15-NEXT: [[ADD85:%.*]] = fadd double [[CONV84]], 1.000000e+008731// CHECK15-NEXT: [[CONV86:%.*]] = fptrunc double [[ADD85]] to float8732// CHECK15-NEXT: store float [[CONV86]], ptr [[ARRAYIDX83]], align 4, !llvm.access.group [[ACC_GRP16]]8733// CHECK15-NEXT: [[ARRAYIDX87:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i32 0, i32 18734// CHECK15-NEXT: [[ARRAYIDX88:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX87]], i32 0, i32 28735// CHECK15-NEXT: [[TMP50:%.*]] = load double, ptr [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP16]]8736// CHECK15-NEXT: [[ADD89:%.*]] = fadd double [[TMP50]], 1.000000e+008737// CHECK15-NEXT: store double [[ADD89]], ptr [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP16]]8738// CHECK15-NEXT: [[TMP51:%.*]] = mul nsw i32 1, [[TMP2]]8739// CHECK15-NEXT: [[ARRAYIDX90:%.*]] = getelementptr inbounds double, ptr [[VLA1]], i32 [[TMP51]]8740// CHECK15-NEXT: [[ARRAYIDX91:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX90]], i32 38741// CHECK15-NEXT: [[TMP52:%.*]] = load double, ptr [[ARRAYIDX91]], align 8, !llvm.access.group [[ACC_GRP16]]8742// CHECK15-NEXT: [[ADD92:%.*]] = fadd double [[TMP52]], 1.000000e+008743// CHECK15-NEXT: store double [[ADD92]], ptr [[ARRAYIDX91]], align 8, !llvm.access.group [[ACC_GRP16]]8744// CHECK15-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D]], i32 0, i32 08745// CHECK15-NEXT: [[TMP53:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP16]]8746// CHECK15-NEXT: [[ADD93:%.*]] = add nsw i64 [[TMP53]], 18747// CHECK15-NEXT: store i64 [[ADD93]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP16]]8748// CHECK15-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D]], i32 0, i32 18749// CHECK15-NEXT: [[TMP54:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP16]]8750// CHECK15-NEXT: [[CONV94:%.*]] = sext i8 [[TMP54]] to i328751// CHECK15-NEXT: [[ADD95:%.*]] = add nsw i32 [[CONV94]], 18752// CHECK15-NEXT: [[CONV96:%.*]] = trunc i32 [[ADD95]] to i88753// CHECK15-NEXT: store i8 [[CONV96]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP16]]8754// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE97:%.*]]8755// CHECK15: omp.body.continue97:8756// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC98:%.*]]8757// CHECK15: omp.inner.for.inc98:8758// CHECK15-NEXT: [[TMP55:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16]]8759// CHECK15-NEXT: [[ADD99:%.*]] = add nsw i32 [[TMP55]], 18760// CHECK15-NEXT: store i32 [[ADD99]], ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16]]8761// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND73]], !llvm.loop [[LOOP17:![0-9]+]]8762// CHECK15: omp.inner.for.end100:8763// CHECK15-NEXT: store i8 96, ptr [[IT72]], align 18764// CHECK15-NEXT: [[TMP56:%.*]] = load i32, ptr [[A]], align 48765// CHECK15-NEXT: [[TMP57:%.*]] = load ptr, ptr [[SAVED_STACK]], align 48766// CHECK15-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP57]])8767// CHECK15-NEXT: ret i32 [[TMP56]]8768//8769//8770// CHECK15-LABEL: define {{[^@]+}}@_Z3bari8771// CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {8772// CHECK15-NEXT: entry:8773// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 48774// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 48775// CHECK15-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 48776// CHECK15-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 48777// CHECK15-NEXT: store i32 0, ptr [[A]], align 48778// CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 48779// CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]])8780// CHECK15-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 48781// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]8782// CHECK15-NEXT: store i32 [[ADD]], ptr [[A]], align 48783// CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 48784// CHECK15-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]])8785// CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 48786// CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]8787// CHECK15-NEXT: store i32 [[ADD2]], ptr [[A]], align 48788// CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 48789// CHECK15-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]])8790// CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 48791// CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]8792// CHECK15-NEXT: store i32 [[ADD4]], ptr [[A]], align 48793// CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 48794// CHECK15-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]])8795// CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 48796// CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]8797// CHECK15-NEXT: store i32 [[ADD6]], ptr [[A]], align 48798// CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 48799// CHECK15-NEXT: ret i32 [[TMP8]]8800//8801//8802// CHECK15-LABEL: define {{[^@]+}}@_ZN2S12r1Ei8803// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {8804// CHECK15-NEXT: entry:8805// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 48806// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 48807// CHECK15-NEXT: [[B:%.*]] = alloca i32, align 48808// CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 48809// CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 48810// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 18811// CHECK15-NEXT: [[TMP:%.*]] = alloca i64, align 48812// CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 88813// CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 88814// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 88815// CHECK15-NEXT: [[IT:%.*]] = alloca i64, align 88816// CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 48817// CHECK15-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 48818// CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 48819// CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 48820// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 18821// CHECK15-NEXT: store i32 [[ADD]], ptr [[B]], align 48822// CHECK15-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 48823// CHECK15-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()8824// CHECK15-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 48825// CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]8826// CHECK15-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 28827// CHECK15-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 48828// CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 48829// CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 608830// CHECK15-NEXT: [[STOREDV:%.*]] = zext i1 [[CMP]] to i88831// CHECK15-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_]], align 18832// CHECK15-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 88833// CHECK15-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 88834// CHECK15-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 88835// CHECK15-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 88836// CHECK15-NEXT: [[TMP6:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 18837// CHECK15-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP6]] to i18838// CHECK15-NEXT: br i1 [[LOADEDV]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]8839// CHECK15: omp_if.then:8840// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]8841// CHECK15: omp.inner.for.cond:8842// CHECK15-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP19:![0-9]+]]8843// CHECK15-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP19]]8844// CHECK15-NEXT: [[CMP2:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]8845// CHECK15-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]8846// CHECK15: omp.inner.for.body:8847// CHECK15-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP19]]8848// CHECK15-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 4008849// CHECK15-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]8850// CHECK15-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP19]]8851// CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[B]], align 4, !llvm.access.group [[ACC_GRP19]]8852// CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP10]] to double8853// CHECK15-NEXT: [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+008854// CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 08855// CHECK15-NEXT: store double [[ADD3]], ptr [[A]], align 4, !nontemporal [[META20:![0-9]+]], !llvm.access.group [[ACC_GRP19]]8856// CHECK15-NEXT: [[A4:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 08857// CHECK15-NEXT: [[TMP11:%.*]] = load double, ptr [[A4]], align 4, !nontemporal [[META20]], !llvm.access.group [[ACC_GRP19]]8858// CHECK15-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+008859// CHECK15-NEXT: store double [[INC]], ptr [[A4]], align 4, !nontemporal [[META20]], !llvm.access.group [[ACC_GRP19]]8860// CHECK15-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i168861// CHECK15-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]]8862// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP12]]8863// CHECK15-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 18864// CHECK15-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP19]]8865// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]8866// CHECK15: omp.body.continue:8867// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]8868// CHECK15: omp.inner.for.inc:8869// CHECK15-NEXT: [[TMP13:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP19]]8870// CHECK15-NEXT: [[ADD7:%.*]] = add i64 [[TMP13]], 18871// CHECK15-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP19]]8872// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]8873// CHECK15: omp.inner.for.end:8874// CHECK15-NEXT: br label [[OMP_IF_END:%.*]]8875// CHECK15: omp_if.else:8876// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND8:%.*]]8877// CHECK15: omp.inner.for.cond8:8878// CHECK15-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 88879// CHECK15-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_UB]], align 88880// CHECK15-NEXT: [[CMP9:%.*]] = icmp ule i64 [[TMP14]], [[TMP15]]8881// CHECK15-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY10:%.*]], label [[OMP_INNER_FOR_END24:%.*]]8882// CHECK15: omp.inner.for.body10:8883// CHECK15-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 88884// CHECK15-NEXT: [[MUL11:%.*]] = mul i64 [[TMP16]], 4008885// CHECK15-NEXT: [[SUB12:%.*]] = sub i64 2000, [[MUL11]]8886// CHECK15-NEXT: store i64 [[SUB12]], ptr [[IT]], align 88887// CHECK15-NEXT: [[TMP17:%.*]] = load i32, ptr [[B]], align 48888// CHECK15-NEXT: [[CONV13:%.*]] = sitofp i32 [[TMP17]] to double8889// CHECK15-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.500000e+008890// CHECK15-NEXT: [[A15:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 08891// CHECK15-NEXT: store double [[ADD14]], ptr [[A15]], align 48892// CHECK15-NEXT: [[A16:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 08893// CHECK15-NEXT: [[TMP18:%.*]] = load double, ptr [[A16]], align 48894// CHECK15-NEXT: [[INC17:%.*]] = fadd double [[TMP18]], 1.000000e+008895// CHECK15-NEXT: store double [[INC17]], ptr [[A16]], align 48896// CHECK15-NEXT: [[CONV18:%.*]] = fptosi double [[INC17]] to i168897// CHECK15-NEXT: [[TMP19:%.*]] = mul nsw i32 1, [[TMP1]]8898// CHECK15-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP19]]8899// CHECK15-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX19]], i32 18900// CHECK15-NEXT: store i16 [[CONV18]], ptr [[ARRAYIDX20]], align 28901// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE21:%.*]]8902// CHECK15: omp.body.continue21:8903// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC22:%.*]]8904// CHECK15: omp.inner.for.inc22:8905// CHECK15-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_IV]], align 88906// CHECK15-NEXT: [[ADD23:%.*]] = add i64 [[TMP20]], 18907// CHECK15-NEXT: store i64 [[ADD23]], ptr [[DOTOMP_IV]], align 88908// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP23:![0-9]+]]8909// CHECK15: omp.inner.for.end24:8910// CHECK15-NEXT: br label [[OMP_IF_END]]8911// CHECK15: omp_if.end:8912// CHECK15-NEXT: store i64 400, ptr [[IT]], align 88913// CHECK15-NEXT: [[TMP21:%.*]] = mul nsw i32 1, [[TMP1]]8914// CHECK15-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP21]]8915// CHECK15-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX25]], i32 18916// CHECK15-NEXT: [[TMP22:%.*]] = load i16, ptr [[ARRAYIDX26]], align 28917// CHECK15-NEXT: [[CONV27:%.*]] = sext i16 [[TMP22]] to i328918// CHECK15-NEXT: [[TMP23:%.*]] = load i32, ptr [[B]], align 48919// CHECK15-NEXT: [[ADD28:%.*]] = add nsw i32 [[CONV27]], [[TMP23]]8920// CHECK15-NEXT: [[TMP24:%.*]] = load ptr, ptr [[SAVED_STACK]], align 48921// CHECK15-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP24]])8922// CHECK15-NEXT: ret i32 [[ADD28]]8923//8924//8925// CHECK15-LABEL: define {{[^@]+}}@_ZL7fstatici8926// CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {8927// CHECK15-NEXT: entry:8928// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 48929// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 48930// CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 28931// CHECK15-NEXT: [[AAA:%.*]] = alloca i8, align 18932// CHECK15-NEXT: [[B:%.*]] = alloca [10 x i32], align 48933// CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 48934// CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 48935// CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 48936// CHECK15-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 48937// CHECK15-NEXT: store i32 0, ptr [[A]], align 48938// CHECK15-NEXT: store i16 0, ptr [[AA]], align 28939// CHECK15-NEXT: store i8 0, ptr [[AAA]], align 18940// CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 48941// CHECK15-NEXT: store i32 429496720, ptr [[DOTOMP_UB]], align 48942// CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 48943// CHECK15-NEXT: ret i32 [[TMP0]]8944//8945//8946// CHECK15-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i8947// CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {8948// CHECK15-NEXT: entry:8949// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 48950// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 48951// CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 28952// CHECK15-NEXT: [[B:%.*]] = alloca [10 x i32], align 48953// CHECK15-NEXT: [[TMP:%.*]] = alloca i64, align 48954// CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 88955// CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 88956// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 88957// CHECK15-NEXT: [[I:%.*]] = alloca i64, align 88958// CHECK15-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 48959// CHECK15-NEXT: store i32 0, ptr [[A]], align 48960// CHECK15-NEXT: store i16 0, ptr [[AA]], align 28961// CHECK15-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 88962// CHECK15-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 88963// CHECK15-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTOMP_LB]], align 88964// CHECK15-NEXT: store i64 [[TMP0]], ptr [[DOTOMP_IV]], align 88965// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]8966// CHECK15: omp.inner.for.cond:8967// CHECK15-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP25:![0-9]+]]8968// CHECK15-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP25]]8969// CHECK15-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]]8970// CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]8971// CHECK15: omp.inner.for.body:8972// CHECK15-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP25]]8973// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 38974// CHECK15-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]8975// CHECK15-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP25]]8976// CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP25]]8977// CHECK15-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 18978// CHECK15-NEXT: store i32 [[ADD1]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP25]]8979// CHECK15-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP25]]8980// CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i328981// CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 18982// CHECK15-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i168983// CHECK15-NEXT: store i16 [[CONV3]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP25]]8984// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i32 0, i32 28985// CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]]8986// CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 18987// CHECK15-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]]8988// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]8989// CHECK15: omp.body.continue:8990// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]8991// CHECK15: omp.inner.for.inc:8992// CHECK15-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP25]]8993// CHECK15-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 18994// CHECK15-NEXT: store i64 [[ADD5]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP25]]8995// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]8996// CHECK15: omp.inner.for.end:8997// CHECK15-NEXT: store i64 11, ptr [[I]], align 88998// CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 48999// CHECK15-NEXT: ret i32 [[TMP8]]9000//9001//9002// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l969003// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {9004// CHECK17-NEXT: entry:9005// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 89006// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 89007// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined)9008// CHECK17-NEXT: ret void9009//9010//9011// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined9012// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {9013// CHECK17-NEXT: entry:9014// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 89015// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 89016// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 49017// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 49018// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 49019// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 49020// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 49021// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 49022// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 49023// CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 89024// CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 89025// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 49026// CHECK17-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 49027// CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 49028// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 49029// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 89030// CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 49031// CHECK17-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)9032// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 49033// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 59034// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]9035// CHECK17: cond.true:9036// CHECK17-NEXT: br label [[COND_END:%.*]]9037// CHECK17: cond.false:9038// CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 49039// CHECK17-NEXT: br label [[COND_END]]9040// CHECK17: cond.end:9041// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]9042// CHECK17-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 49043// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 49044// CHECK17-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 49045// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]9046// CHECK17: omp.inner.for.cond:9047// CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]]9048// CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]]9049// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]9050// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]9051// CHECK17: omp.inner.for.body:9052// CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]9053// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 59054// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]9055// CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]]9056// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]9057// CHECK17: omp.body.continue:9058// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]9059// CHECK17: omp.inner.for.inc:9060// CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]9061// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 19062// CHECK17-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]9063// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]9064// CHECK17: omp.inner.for.end:9065// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]9066// CHECK17: omp.loop.exit:9067// CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])9068// CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 49069// CHECK17-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 09070// CHECK17-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]9071// CHECK17: .omp.final.then:9072// CHECK17-NEXT: store i32 33, ptr [[I]], align 49073// CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]]9074// CHECK17: .omp.final.done:9075// CHECK17-NEXT: ret void9076//9077//9078// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1089079// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] {9080// CHECK17-NEXT: entry:9081// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 89082// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 89083// CHECK17-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 89084// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 89085// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 89086// CHECK17-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 89087// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 89088// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 89089// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 89090// CHECK17-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 89091// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 89092// CHECK17-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 29093// CHECK17-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 29094// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 89095// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 49096// CHECK17-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 49097// CHECK17-NEXT: [[TMP3:%.*]] = load i64, ptr [[LIN_CASTED]], align 89098// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 49099// CHECK17-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 49100// CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[A_CASTED]], align 89101// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined, i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])9102// CHECK17-NEXT: ret void9103//9104//9105// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined9106// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] {9107// CHECK17-NEXT: entry:9108// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 89109// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 89110// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 89111// CHECK17-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 89112// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 89113// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 89114// CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 89115// CHECK17-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 49116// CHECK17-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 49117// CHECK17-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 89118// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 89119// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 89120// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 89121// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 49122// CHECK17-NEXT: [[IT:%.*]] = alloca i64, align 89123// CHECK17-NEXT: [[LIN2:%.*]] = alloca i32, align 49124// CHECK17-NEXT: [[A3:%.*]] = alloca i32, align 49125// CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 89126// CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 89127// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 89128// CHECK17-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 89129// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 89130// CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 49131// CHECK17-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 49132// CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 49133// CHECK17-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 49134// CHECK17-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()9135// CHECK17-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 89136// CHECK17-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 89137// CHECK17-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 89138// CHECK17-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 89139// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 49140// CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 89141// CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 49142// CHECK17-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP3]])9143// CHECK17-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)9144// CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 89145// CHECK17-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 39146// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]9147// CHECK17: cond.true:9148// CHECK17-NEXT: br label [[COND_END:%.*]]9149// CHECK17: cond.false:9150// CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 89151// CHECK17-NEXT: br label [[COND_END]]9152// CHECK17: cond.end:9153// CHECK17-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]9154// CHECK17-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 89155// CHECK17-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 89156// CHECK17-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 89157// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]9158// CHECK17: omp.inner.for.cond:9159// CHECK17-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17:![0-9]+]]9160// CHECK17-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP17]]9161// CHECK17-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]9162// CHECK17-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]9163// CHECK17: omp.inner.for.body:9164// CHECK17-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]]9165// CHECK17-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 4009166// CHECK17-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]9167// CHECK17-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP17]]9168// CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP17]]9169// CHECK17-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i649170// CHECK17-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]]9171// CHECK17-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP17]]9172// CHECK17-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]]9173// CHECK17-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]]9174// CHECK17-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i329175// CHECK17-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 4, !llvm.access.group [[ACC_GRP17]]9176// CHECK17-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4, !llvm.access.group [[ACC_GRP17]]9177// CHECK17-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i649178// CHECK17-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]]9179// CHECK17-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP17]]9180// CHECK17-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]]9181// CHECK17-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]]9182// CHECK17-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i329183// CHECK17-NEXT: store i32 [[CONV10]], ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP17]]9184// CHECK17-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP17]]9185// CHECK17-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i329186// CHECK17-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 19187// CHECK17-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i169188// CHECK17-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP17]]9189// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]9190// CHECK17: omp.body.continue:9191// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]9192// CHECK17: omp.inner.for.inc:9193// CHECK17-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]]9194// CHECK17-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 19195// CHECK17-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]]9196// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]9197// CHECK17: omp.inner.for.end:9198// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]9199// CHECK17: omp.loop.exit:9200// CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]])9201// CHECK17-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 49202// CHECK17-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 09203// CHECK17-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]9204// CHECK17: .omp.final.then:9205// CHECK17-NEXT: store i64 400, ptr [[IT]], align 89206// CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]]9207// CHECK17: .omp.final.done:9208// CHECK17-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 49209// CHECK17-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 09210// CHECK17-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]9211// CHECK17: .omp.linear.pu:9212// CHECK17-NEXT: [[TMP22:%.*]] = load i32, ptr [[LIN2]], align 49213// CHECK17-NEXT: store i32 [[TMP22]], ptr [[LIN_ADDR]], align 49214// CHECK17-NEXT: [[TMP23:%.*]] = load i32, ptr [[A3]], align 49215// CHECK17-NEXT: store i32 [[TMP23]], ptr [[A_ADDR]], align 49216// CHECK17-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]9217// CHECK17: .omp.linear.pu.done:9218// CHECK17-NEXT: ret void9219//9220//9221// CHECK17-LABEL: define {{[^@]+}}@_Z7get_valv9222// CHECK17-SAME: () #[[ATTR2:[0-9]+]] {9223// CHECK17-NEXT: entry:9224// CHECK17-NEXT: ret i64 09225//9226//9227// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1169228// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {9229// CHECK17-NEXT: entry:9230// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 89231// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 89232// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 89233// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 89234// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 89235// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 89236// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 89237// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 89238// CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 49239// CHECK17-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 49240// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 89241// CHECK17-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 29242// CHECK17-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 29243// CHECK17-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 89244// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined, i64 [[TMP1]], i64 [[TMP3]])9245// CHECK17-NEXT: ret void9246//9247//9248// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined9249// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {9250// CHECK17-NEXT: entry:9251// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 89252// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 89253// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 89254// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 89255// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 49256// CHECK17-NEXT: [[TMP:%.*]] = alloca i16, align 29257// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 49258// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 49259// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 49260// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 49261// CHECK17-NEXT: [[IT:%.*]] = alloca i16, align 29262// CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 89263// CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 89264// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 89265// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 89266// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 49267// CHECK17-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 49268// CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 49269// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 49270// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 89271// CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 49272// CHECK17-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)9273// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 49274// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 39275// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]9276// CHECK17: cond.true:9277// CHECK17-NEXT: br label [[COND_END:%.*]]9278// CHECK17: cond.false:9279// CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 49280// CHECK17-NEXT: br label [[COND_END]]9281// CHECK17: cond.end:9282// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]9283// CHECK17-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 49284// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 49285// CHECK17-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 49286// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]9287// CHECK17: omp.inner.for.cond:9288// CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20:![0-9]+]]9289// CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP20]]9290// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]9291// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]9292// CHECK17: omp.inner.for.body:9293// CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]]9294// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 49295// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]9296// CHECK17-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i169297// CHECK17-NEXT: store i16 [[CONV]], ptr [[IT]], align 2, !llvm.access.group [[ACC_GRP20]]9298// CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP20]]9299// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 19300// CHECK17-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP20]]9301// CHECK17-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP20]]9302// CHECK17-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i329303// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 19304// CHECK17-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i169305// CHECK17-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP20]]9306// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]9307// CHECK17: omp.body.continue:9308// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]9309// CHECK17: omp.inner.for.inc:9310// CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]]9311// CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 19312// CHECK17-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]]9313// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]9314// CHECK17: omp.inner.for.end:9315// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]9316// CHECK17: omp.loop.exit:9317// CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])9318// CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 49319// CHECK17-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 09320// CHECK17-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]9321// CHECK17: .omp.final.then:9322// CHECK17-NEXT: store i16 22, ptr [[IT]], align 29323// CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]]9324// CHECK17: .omp.final.done:9325// CHECK17-NEXT: ret void9326//9327//9328// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1409329// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {9330// CHECK17-NEXT: entry:9331// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 89332// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 89333// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 89334// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 89335// CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 89336// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 89337// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 89338// CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 89339// CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 89340// CHECK17-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 89341// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 89342// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 89343// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 89344// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 89345// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 89346// CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 89347// CHECK17-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 89348// CHECK17-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 89349// CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 89350// CHECK17-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 89351// CHECK17-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 89352// CHECK17-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 89353// CHECK17-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 89354// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 89355// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 89356// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 89357// CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 89358// CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 89359// CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 89360// CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 89361// CHECK17-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 89362// CHECK17-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 89363// CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 49364// CHECK17-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 49365// CHECK17-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 89366// CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 49367// CHECK17-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 49368// CHECK17-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 89369// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i64 [[TMP11]])9370// CHECK17-NEXT: ret void9371//9372//9373// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined9374// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {9375// CHECK17-NEXT: entry:9376// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 89377// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 89378// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 89379// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 89380// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 89381// CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 89382// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 89383// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 89384// CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 89385// CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 89386// CHECK17-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 89387// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 89388// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 49389// CHECK17-NEXT: [[TMP:%.*]] = alloca i8, align 19390// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 49391// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 49392// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 49393// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 49394// CHECK17-NEXT: [[IT:%.*]] = alloca i8, align 19395// CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 89396// CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 89397// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 89398// CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 89399// CHECK17-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 89400// CHECK17-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 89401// CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 89402// CHECK17-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 89403// CHECK17-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 89404// CHECK17-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 89405// CHECK17-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 89406// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 89407// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 89408// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 89409// CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 89410// CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 89411// CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 89412// CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 89413// CHECK17-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 89414// CHECK17-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 89415// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 49416// CHECK17-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 49417// CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 49418// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 49419// CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 49420// CHECK17-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 89421// CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 49422// CHECK17-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])9423// CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]]9424// CHECK17: omp.dispatch.cond:9425// CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 49426// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 259427// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]9428// CHECK17: cond.true:9429// CHECK17-NEXT: br label [[COND_END:%.*]]9430// CHECK17: cond.false:9431// CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 49432// CHECK17-NEXT: br label [[COND_END]]9433// CHECK17: cond.end:9434// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]9435// CHECK17-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 49436// CHECK17-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 49437// CHECK17-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 49438// CHECK17-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 49439// CHECK17-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 49440// CHECK17-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]9441// CHECK17-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]9442// CHECK17: omp.dispatch.body:9443// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]9444// CHECK17: omp.inner.for.cond:9445// CHECK17-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23:![0-9]+]]9446// CHECK17-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP23]]9447// CHECK17-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]9448// CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]9449// CHECK17: omp.inner.for.body:9450// CHECK17-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]]9451// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 19452// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]9453// CHECK17-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i89454// CHECK17-NEXT: store i8 [[CONV]], ptr [[IT]], align 1, !llvm.access.group [[ACC_GRP23]]9455// CHECK17-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP23]]9456// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 19457// CHECK17-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP23]]9458// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 29459// CHECK17-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP23]]9460// CHECK17-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double9461// CHECK17-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+009462// CHECK17-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float9463// CHECK17-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP23]]9464// CHECK17-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 39465// CHECK17-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP23]]9466// CHECK17-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double9467// CHECK17-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+009468// CHECK17-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float9469// CHECK17-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP23]]9470// CHECK17-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 19471// CHECK17-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i64 0, i64 29472// CHECK17-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP23]]9473// CHECK17-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+009474// CHECK17-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP23]]9475// CHECK17-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]9476// CHECK17-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP23]]9477// CHECK17-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i64 39478// CHECK17-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP23]]9479// CHECK17-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+009480// CHECK17-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP23]]9481// CHECK17-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 09482// CHECK17-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP23]]9483// CHECK17-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 19484// CHECK17-NEXT: store i64 [[ADD20]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP23]]9485// CHECK17-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 19486// CHECK17-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP23]]9487// CHECK17-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i329488// CHECK17-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 19489// CHECK17-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i89490// CHECK17-NEXT: store i8 [[CONV23]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP23]]9491// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]9492// CHECK17: omp.body.continue:9493// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]9494// CHECK17: omp.inner.for.inc:9495// CHECK17-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]]9496// CHECK17-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 19497// CHECK17-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]]9498// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]9499// CHECK17: omp.inner.for.end:9500// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]]9501// CHECK17: omp.dispatch.inc:9502// CHECK17-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 49503// CHECK17-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 49504// CHECK17-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]9505// CHECK17-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 49506// CHECK17-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 49507// CHECK17-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 49508// CHECK17-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]9509// CHECK17-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 49510// CHECK17-NEXT: br label [[OMP_DISPATCH_COND]]9511// CHECK17: omp.dispatch.end:9512// CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]])9513// CHECK17-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 49514// CHECK17-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 09515// CHECK17-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]9516// CHECK17: .omp.final.then:9517// CHECK17-NEXT: store i8 96, ptr [[IT]], align 19518// CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]]9519// CHECK17: .omp.final.done:9520// CHECK17-NEXT: ret void9521//9522//9523// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l1959524// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {9525// CHECK17-NEXT: entry:9526// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 89527// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 89528// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 89529// CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 89530// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 89531// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 89532// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 89533// CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 89534// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 89535// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 89536// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 89537// CHECK17-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 89538// CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 89539// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 89540// CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 49541// CHECK17-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 49542// CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 89543// CHECK17-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 29544// CHECK17-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 29545// CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 89546// CHECK17-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 19547// CHECK17-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 19548// CHECK17-NEXT: [[TMP6:%.*]] = load i64, ptr [[AAA_CASTED]], align 89549// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], ptr [[TMP0]])9550// CHECK17-NEXT: ret void9551//9552//9553// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined9554// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {9555// CHECK17-NEXT: entry:9556// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 89557// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 89558// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 89559// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 89560// CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 89561// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 89562// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 49563// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 49564// CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 89565// CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 89566// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 89567// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 89568// CHECK17-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 89569// CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 89570// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 89571// CHECK17-NEXT: ret void9572//9573//9574// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l2169575// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {9576// CHECK17-NEXT: entry:9577// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 89578// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 89579// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 89580// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 89581// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 89582// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 89583// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 89584// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 89585// CHECK17-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 89586// CHECK17-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 89587// CHECK17-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 89588// CHECK17-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 89589// CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 89590// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 89591// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 89592// CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 89593// CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 89594// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 49595// CHECK17-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 49596// CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 89597// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]])9598// CHECK17-NEXT: ret void9599//9600//9601// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined9602// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {9603// CHECK17-NEXT: entry:9604// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 89605// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 89606// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 89607// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 89608// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 89609// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 89610// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 89611// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 89612// CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 89613// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 89614// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 89615// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 89616// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 49617// CHECK17-NEXT: [[IT:%.*]] = alloca i64, align 89618// CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 89619// CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 89620// CHECK17-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 89621// CHECK17-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 89622// CHECK17-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 89623// CHECK17-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 89624// CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 89625// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 89626// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 89627// CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 89628// CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 89629// CHECK17-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 89630// CHECK17-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 89631// CHECK17-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 89632// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 49633// CHECK17-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 89634// CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 49635// CHECK17-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)9636// CHECK17-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_UB]], align 89637// CHECK17-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 39638// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]9639// CHECK17: cond.true:9640// CHECK17-NEXT: br label [[COND_END:%.*]]9641// CHECK17: cond.false:9642// CHECK17-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 89643// CHECK17-NEXT: br label [[COND_END]]9644// CHECK17: cond.end:9645// CHECK17-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]9646// CHECK17-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 89647// CHECK17-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_LB]], align 89648// CHECK17-NEXT: store i64 [[TMP8]], ptr [[DOTOMP_IV]], align 89649// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]9650// CHECK17: omp.inner.for.cond:9651// CHECK17-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP26:![0-9]+]]9652// CHECK17-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP26]]9653// CHECK17-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]9654// CHECK17-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]9655// CHECK17: omp.inner.for.body:9656// CHECK17-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP26]]9657// CHECK17-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 4009658// CHECK17-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]9659// CHECK17-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP26]]9660// CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP26]]9661// CHECK17-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double9662// CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+009663// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 09664// CHECK17-NEXT: store double [[ADD]], ptr [[A]], align 8, !llvm.access.group [[ACC_GRP26]]9665// CHECK17-NEXT: [[A4:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 09666// CHECK17-NEXT: [[TMP13:%.*]] = load double, ptr [[A4]], align 8, !llvm.access.group [[ACC_GRP26]]9667// CHECK17-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+009668// CHECK17-NEXT: store double [[INC]], ptr [[A4]], align 8, !llvm.access.group [[ACC_GRP26]]9669// CHECK17-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i169670// CHECK17-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]9671// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP14]]9672// CHECK17-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 19673// CHECK17-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP26]]9674// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]9675// CHECK17: omp.body.continue:9676// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]9677// CHECK17: omp.inner.for.inc:9678// CHECK17-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP26]]9679// CHECK17-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 19680// CHECK17-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP26]]9681// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]]9682// CHECK17: omp.inner.for.end:9683// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]9684// CHECK17: omp.loop.exit:9685// CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])9686// CHECK17-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 49687// CHECK17-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 09688// CHECK17-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]9689// CHECK17: .omp.final.then:9690// CHECK17-NEXT: store i64 400, ptr [[IT]], align 89691// CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]]9692// CHECK17: .omp.final.done:9693// CHECK17-NEXT: ret void9694//9695//9696// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l1789697// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {9698// CHECK17-NEXT: entry:9699// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 89700// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 89701// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 89702// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 89703// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 89704// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 89705// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 89706// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 89707// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 89708// CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 89709// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 89710// CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 49711// CHECK17-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 49712// CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 89713// CHECK17-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 29714// CHECK17-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 29715// CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 89716// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]])9717// CHECK17-NEXT: ret void9718//9719//9720// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined9721// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {9722// CHECK17-NEXT: entry:9723// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 89724// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 89725// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 89726// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 89727// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 89728// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 89729// CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 89730// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 89731// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 89732// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 89733// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 49734// CHECK17-NEXT: [[I:%.*]] = alloca i64, align 89735// CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 89736// CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 89737// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 89738// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 89739// CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 89740// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 89741// CHECK17-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 89742// CHECK17-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 89743// CHECK17-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 89744// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 49745// CHECK17-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 89746// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 49747// CHECK17-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)9748// CHECK17-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 89749// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 69750// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]9751// CHECK17: cond.true:9752// CHECK17-NEXT: br label [[COND_END:%.*]]9753// CHECK17: cond.false:9754// CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 89755// CHECK17-NEXT: br label [[COND_END]]9756// CHECK17: cond.end:9757// CHECK17-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]9758// CHECK17-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 89759// CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 89760// CHECK17-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 89761// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]9762// CHECK17: omp.inner.for.cond:9763// CHECK17-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29:![0-9]+]]9764// CHECK17-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP29]]9765// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]9766// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]9767// CHECK17: omp.inner.for.body:9768// CHECK17-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]]9769// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 39770// CHECK17-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]9771// CHECK17-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP29]]9772// CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP29]]9773// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 19774// CHECK17-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP29]]9775// CHECK17-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP29]]9776// CHECK17-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i329777// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 19778// CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i169779// CHECK17-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP29]]9780// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 29781// CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP29]]9782// CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 19783// CHECK17-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP29]]9784// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]9785// CHECK17: omp.body.continue:9786// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]9787// CHECK17: omp.inner.for.inc:9788// CHECK17-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]]9789// CHECK17-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 19790// CHECK17-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]]9791// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]]9792// CHECK17: omp.inner.for.end:9793// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]9794// CHECK17: omp.loop.exit:9795// CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])9796// CHECK17-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 49797// CHECK17-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 09798// CHECK17-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]9799// CHECK17: .omp.final.then:9800// CHECK17-NEXT: store i64 11, ptr [[I]], align 89801// CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]]9802// CHECK17: .omp.final.done:9803// CHECK17-NEXT: ret void9804//9805//9806// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l969807// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {9808// CHECK19-NEXT: entry:9809// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 49810// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 49811// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined)9812// CHECK19-NEXT: ret void9813//9814//9815// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined9816// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {9817// CHECK19-NEXT: entry:9818// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 49819// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 49820// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 49821// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 49822// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 49823// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 49824// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 49825// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 49826// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 49827// CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 49828// CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 49829// CHECK19-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 49830// CHECK19-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 49831// CHECK19-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 49832// CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 49833// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 49834// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 49835// CHECK19-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)9836// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 49837// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 59838// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]9839// CHECK19: cond.true:9840// CHECK19-NEXT: br label [[COND_END:%.*]]9841// CHECK19: cond.false:9842// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 49843// CHECK19-NEXT: br label [[COND_END]]9844// CHECK19: cond.end:9845// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]9846// CHECK19-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 49847// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 49848// CHECK19-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 49849// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]9850// CHECK19: omp.inner.for.cond:9851// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]]9852// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]]9853// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]9854// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]9855// CHECK19: omp.inner.for.body:9856// CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]9857// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 59858// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]9859// CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]]9860// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]9861// CHECK19: omp.body.continue:9862// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]9863// CHECK19: omp.inner.for.inc:9864// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]9865// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 19866// CHECK19-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]9867// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]9868// CHECK19: omp.inner.for.end:9869// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]9870// CHECK19: omp.loop.exit:9871// CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])9872// CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 49873// CHECK19-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 09874// CHECK19-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]9875// CHECK19: .omp.final.then:9876// CHECK19-NEXT: store i32 33, ptr [[I]], align 49877// CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]]9878// CHECK19: .omp.final.done:9879// CHECK19-NEXT: ret void9880//9881//9882// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1089883// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] {9884// CHECK19-NEXT: entry:9885// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 49886// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 49887// CHECK19-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 49888// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 49889// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 49890// CHECK19-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 49891// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 49892// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 49893// CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 49894// CHECK19-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 49895// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 49896// CHECK19-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 29897// CHECK19-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 29898// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 49899// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 49900// CHECK19-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 49901// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[LIN_CASTED]], align 49902// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 49903// CHECK19-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 49904// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[A_CASTED]], align 49905// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined, i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])9906// CHECK19-NEXT: ret void9907//9908//9909// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined9910// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] {9911// CHECK19-NEXT: entry:9912// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 49913// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 49914// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 49915// CHECK19-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 49916// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 49917// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 89918// CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 49919// CHECK19-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 49920// CHECK19-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 49921// CHECK19-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 89922// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 89923// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 89924// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 89925// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 49926// CHECK19-NEXT: [[IT:%.*]] = alloca i64, align 89927// CHECK19-NEXT: [[LIN2:%.*]] = alloca i32, align 49928// CHECK19-NEXT: [[A3:%.*]] = alloca i32, align 49929// CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 49930// CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 49931// CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 49932// CHECK19-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 49933// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 49934// CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 49935// CHECK19-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 49936// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 49937// CHECK19-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 49938// CHECK19-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()9939// CHECK19-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 89940// CHECK19-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 89941// CHECK19-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 89942// CHECK19-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 89943// CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 49944// CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 49945// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 49946// CHECK19-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP3]])9947// CHECK19-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)9948// CHECK19-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 89949// CHECK19-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 39950// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]9951// CHECK19: cond.true:9952// CHECK19-NEXT: br label [[COND_END:%.*]]9953// CHECK19: cond.false:9954// CHECK19-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 89955// CHECK19-NEXT: br label [[COND_END]]9956// CHECK19: cond.end:9957// CHECK19-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]9958// CHECK19-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 89959// CHECK19-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 89960// CHECK19-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 89961// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]9962// CHECK19: omp.inner.for.cond:9963// CHECK19-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18:![0-9]+]]9964// CHECK19-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP18]]9965// CHECK19-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]9966// CHECK19-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]9967// CHECK19: omp.inner.for.body:9968// CHECK19-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]]9969// CHECK19-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 4009970// CHECK19-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]9971// CHECK19-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP18]]9972// CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP18]]9973// CHECK19-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i649974// CHECK19-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]]9975// CHECK19-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP18]]9976// CHECK19-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]]9977// CHECK19-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]]9978// CHECK19-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i329979// CHECK19-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 4, !llvm.access.group [[ACC_GRP18]]9980// CHECK19-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4, !llvm.access.group [[ACC_GRP18]]9981// CHECK19-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i649982// CHECK19-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]]9983// CHECK19-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP18]]9984// CHECK19-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]]9985// CHECK19-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]]9986// CHECK19-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i329987// CHECK19-NEXT: store i32 [[CONV10]], ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP18]]9988// CHECK19-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP18]]9989// CHECK19-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i329990// CHECK19-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 19991// CHECK19-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i169992// CHECK19-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP18]]9993// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]9994// CHECK19: omp.body.continue:9995// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]9996// CHECK19: omp.inner.for.inc:9997// CHECK19-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]]9998// CHECK19-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 19999// CHECK19-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]]10000// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]10001// CHECK19: omp.inner.for.end:10002// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]10003// CHECK19: omp.loop.exit:10004// CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]])10005// CHECK19-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 410006// CHECK19-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 010007// CHECK19-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]10008// CHECK19: .omp.final.then:10009// CHECK19-NEXT: store i64 400, ptr [[IT]], align 810010// CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]]10011// CHECK19: .omp.final.done:10012// CHECK19-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 410013// CHECK19-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 010014// CHECK19-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]10015// CHECK19: .omp.linear.pu:10016// CHECK19-NEXT: [[TMP22:%.*]] = load i32, ptr [[LIN2]], align 410017// CHECK19-NEXT: store i32 [[TMP22]], ptr [[LIN_ADDR]], align 410018// CHECK19-NEXT: [[TMP23:%.*]] = load i32, ptr [[A3]], align 410019// CHECK19-NEXT: store i32 [[TMP23]], ptr [[A_ADDR]], align 410020// CHECK19-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]10021// CHECK19: .omp.linear.pu.done:10022// CHECK19-NEXT: ret void10023//10024//10025// CHECK19-LABEL: define {{[^@]+}}@_Z7get_valv10026// CHECK19-SAME: () #[[ATTR2:[0-9]+]] {10027// CHECK19-NEXT: entry:10028// CHECK19-NEXT: ret i64 010029//10030//10031// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l11610032// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {10033// CHECK19-NEXT: entry:10034// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 410035// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 410036// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 410037// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 410038// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 410039// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 410040// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 410041// CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 410042// CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 410043// CHECK19-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 410044// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 410045// CHECK19-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 210046// CHECK19-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 210047// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 410048// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined, i32 [[TMP1]], i32 [[TMP3]])10049// CHECK19-NEXT: ret void10050//10051//10052// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined10053// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {10054// CHECK19-NEXT: entry:10055// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 410056// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 410057// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 410058// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 410059// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 410060// CHECK19-NEXT: [[TMP:%.*]] = alloca i16, align 210061// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 410062// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 410063// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 410064// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 410065// CHECK19-NEXT: [[IT:%.*]] = alloca i16, align 210066// CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 410067// CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 410068// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 410069// CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 410070// CHECK19-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 410071// CHECK19-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 410072// CHECK19-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 410073// CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 410074// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 410075// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 410076// CHECK19-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)10077// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 410078// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 310079// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]10080// CHECK19: cond.true:10081// CHECK19-NEXT: br label [[COND_END:%.*]]10082// CHECK19: cond.false:10083// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 410084// CHECK19-NEXT: br label [[COND_END]]10085// CHECK19: cond.end:10086// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]10087// CHECK19-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 410088// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 410089// CHECK19-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 410090// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]10091// CHECK19: omp.inner.for.cond:10092// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21:![0-9]+]]10093// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP21]]10094// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]10095// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]10096// CHECK19: omp.inner.for.body:10097// CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]]10098// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 410099// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]10100// CHECK19-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i1610101// CHECK19-NEXT: store i16 [[CONV]], ptr [[IT]], align 2, !llvm.access.group [[ACC_GRP21]]10102// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP21]]10103// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 110104// CHECK19-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP21]]10105// CHECK19-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP21]]10106// CHECK19-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i3210107// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 110108// CHECK19-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i1610109// CHECK19-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP21]]10110// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]10111// CHECK19: omp.body.continue:10112// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]10113// CHECK19: omp.inner.for.inc:10114// CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]]10115// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 110116// CHECK19-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]]10117// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]10118// CHECK19: omp.inner.for.end:10119// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]10120// CHECK19: omp.loop.exit:10121// CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])10122// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 410123// CHECK19-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 010124// CHECK19-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]10125// CHECK19: .omp.final.then:10126// CHECK19-NEXT: store i16 22, ptr [[IT]], align 210127// CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]]10128// CHECK19: .omp.final.done:10129// CHECK19-NEXT: ret void10130//10131//10132// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l14010133// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {10134// CHECK19-NEXT: entry:10135// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 410136// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 410137// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 410138// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 410139// CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 410140// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 410141// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 410142// CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 410143// CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 410144// CHECK19-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 410145// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 410146// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 410147// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 410148// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 410149// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 410150// CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 410151// CHECK19-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 410152// CHECK19-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 410153// CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 410154// CHECK19-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 410155// CHECK19-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 410156// CHECK19-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 410157// CHECK19-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 410158// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 410159// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 410160// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 410161// CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 410162// CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 410163// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 410164// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 410165// CHECK19-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 410166// CHECK19-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 410167// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 410168// CHECK19-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 410169// CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 410170// CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 410171// CHECK19-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 410172// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 410173// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i32 [[TMP11]])10174// CHECK19-NEXT: ret void10175//10176//10177// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined10178// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {10179// CHECK19-NEXT: entry:10180// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 410181// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 410182// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 410183// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 410184// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 410185// CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 410186// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 410187// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 410188// CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 410189// CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 410190// CHECK19-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 410191// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 410192// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 410193// CHECK19-NEXT: [[TMP:%.*]] = alloca i8, align 110194// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 410195// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 410196// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 410197// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 410198// CHECK19-NEXT: [[IT:%.*]] = alloca i8, align 110199// CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 410200// CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 410201// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 410202// CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 410203// CHECK19-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 410204// CHECK19-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 410205// CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 410206// CHECK19-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 410207// CHECK19-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 410208// CHECK19-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 410209// CHECK19-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 410210// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 410211// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 410212// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 410213// CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 410214// CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 410215// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 410216// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 410217// CHECK19-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 410218// CHECK19-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 410219// CHECK19-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 410220// CHECK19-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 410221// CHECK19-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 410222// CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 410223// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 410224// CHECK19-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 410225// CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 410226// CHECK19-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])10227// CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]]10228// CHECK19: omp.dispatch.cond:10229// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 410230// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 2510231// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]10232// CHECK19: cond.true:10233// CHECK19-NEXT: br label [[COND_END:%.*]]10234// CHECK19: cond.false:10235// CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 410236// CHECK19-NEXT: br label [[COND_END]]10237// CHECK19: cond.end:10238// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]10239// CHECK19-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 410240// CHECK19-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 410241// CHECK19-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 410242// CHECK19-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 410243// CHECK19-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 410244// CHECK19-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]10245// CHECK19-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]10246// CHECK19: omp.dispatch.body:10247// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]10248// CHECK19: omp.inner.for.cond:10249// CHECK19-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24:![0-9]+]]10250// CHECK19-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP24]]10251// CHECK19-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]10252// CHECK19-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]10253// CHECK19: omp.inner.for.body:10254// CHECK19-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]]10255// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 110256// CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]10257// CHECK19-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i810258// CHECK19-NEXT: store i8 [[CONV]], ptr [[IT]], align 1, !llvm.access.group [[ACC_GRP24]]10259// CHECK19-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP24]]10260// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 110261// CHECK19-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP24]]10262// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 210263// CHECK19-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]]10264// CHECK19-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double10265// CHECK19-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+0010266// CHECK19-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float10267// CHECK19-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]]10268// CHECK19-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 310269// CHECK19-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP24]]10270// CHECK19-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double10271// CHECK19-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+0010272// CHECK19-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float10273// CHECK19-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP24]]10274// CHECK19-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 110275// CHECK19-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i32 0, i32 210276// CHECK19-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP24]]10277// CHECK19-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+0010278// CHECK19-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP24]]10279// CHECK19-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]10280// CHECK19-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP23]]10281// CHECK19-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i32 310282// CHECK19-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP24]]10283// CHECK19-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+0010284// CHECK19-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP24]]10285// CHECK19-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 010286// CHECK19-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP24]]10287// CHECK19-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 110288// CHECK19-NEXT: store i64 [[ADD20]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP24]]10289// CHECK19-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 110290// CHECK19-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP24]]10291// CHECK19-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i3210292// CHECK19-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 110293// CHECK19-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i810294// CHECK19-NEXT: store i8 [[CONV23]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP24]]10295// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]10296// CHECK19: omp.body.continue:10297// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]10298// CHECK19: omp.inner.for.inc:10299// CHECK19-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]]10300// CHECK19-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 110301// CHECK19-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]]10302// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]10303// CHECK19: omp.inner.for.end:10304// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]]10305// CHECK19: omp.dispatch.inc:10306// CHECK19-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 410307// CHECK19-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 410308// CHECK19-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]10309// CHECK19-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 410310// CHECK19-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 410311// CHECK19-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 410312// CHECK19-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]10313// CHECK19-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 410314// CHECK19-NEXT: br label [[OMP_DISPATCH_COND]]10315// CHECK19: omp.dispatch.end:10316// CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]])10317// CHECK19-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 410318// CHECK19-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 010319// CHECK19-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]10320// CHECK19: .omp.final.then:10321// CHECK19-NEXT: store i8 96, ptr [[IT]], align 110322// CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]]10323// CHECK19: .omp.final.done:10324// CHECK19-NEXT: ret void10325//10326//10327// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l19510328// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {10329// CHECK19-NEXT: entry:10330// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 410331// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 410332// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 410333// CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 410334// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 410335// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 410336// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 410337// CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 410338// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 410339// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 410340// CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 410341// CHECK19-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 410342// CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 410343// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 410344// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 410345// CHECK19-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 410346// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 410347// CHECK19-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 210348// CHECK19-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 210349// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 410350// CHECK19-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 110351// CHECK19-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 110352// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[AAA_CASTED]], align 410353// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], ptr [[TMP0]])10354// CHECK19-NEXT: ret void10355//10356//10357// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined10358// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {10359// CHECK19-NEXT: entry:10360// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 410361// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 410362// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 410363// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 410364// CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 410365// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 410366// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 410367// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 410368// CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 410369// CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 410370// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 410371// CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 410372// CHECK19-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 410373// CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 410374// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 410375// CHECK19-NEXT: ret void10376//10377//10378// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l21610379// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {10380// CHECK19-NEXT: entry:10381// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 410382// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 410383// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 410384// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 410385// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 410386// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 410387// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 410388// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 410389// CHECK19-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 410390// CHECK19-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 410391// CHECK19-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 410392// CHECK19-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 410393// CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 410394// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 410395// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 410396// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 410397// CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 410398// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 410399// CHECK19-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 410400// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 410401// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]])10402// CHECK19-NEXT: ret void10403//10404//10405// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined10406// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {10407// CHECK19-NEXT: entry:10408// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 410409// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 410410// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 410411// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 410412// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 410413// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 410414// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 410415// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 810416// CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 410417// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 810418// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 810419// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 810420// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 410421// CHECK19-NEXT: [[IT:%.*]] = alloca i64, align 810422// CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 410423// CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 410424// CHECK19-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 410425// CHECK19-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 410426// CHECK19-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 410427// CHECK19-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 410428// CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 410429// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 410430// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 410431// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 410432// CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 410433// CHECK19-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 810434// CHECK19-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 810435// CHECK19-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 810436// CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 410437// CHECK19-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 410438// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 410439// CHECK19-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)10440// CHECK19-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_UB]], align 810441// CHECK19-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 310442// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]10443// CHECK19: cond.true:10444// CHECK19-NEXT: br label [[COND_END:%.*]]10445// CHECK19: cond.false:10446// CHECK19-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 810447// CHECK19-NEXT: br label [[COND_END]]10448// CHECK19: cond.end:10449// CHECK19-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]10450// CHECK19-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 810451// CHECK19-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_LB]], align 810452// CHECK19-NEXT: store i64 [[TMP8]], ptr [[DOTOMP_IV]], align 810453// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]10454// CHECK19: omp.inner.for.cond:10455// CHECK19-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP27:![0-9]+]]10456// CHECK19-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP27]]10457// CHECK19-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]10458// CHECK19-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]10459// CHECK19: omp.inner.for.body:10460// CHECK19-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP27]]10461// CHECK19-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 40010462// CHECK19-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]10463// CHECK19-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP27]]10464// CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP27]]10465// CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double10466// CHECK19-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+0010467// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 010468// CHECK19-NEXT: store double [[ADD]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP27]]10469// CHECK19-NEXT: [[A4:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 010470// CHECK19-NEXT: [[TMP13:%.*]] = load double, ptr [[A4]], align 4, !llvm.access.group [[ACC_GRP27]]10471// CHECK19-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+0010472// CHECK19-NEXT: store double [[INC]], ptr [[A4]], align 4, !llvm.access.group [[ACC_GRP27]]10473// CHECK19-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i1610474// CHECK19-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]10475// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP14]]10476// CHECK19-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 110477// CHECK19-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP27]]10478// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]10479// CHECK19: omp.body.continue:10480// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]10481// CHECK19: omp.inner.for.inc:10482// CHECK19-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP27]]10483// CHECK19-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 110484// CHECK19-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP27]]10485// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]10486// CHECK19: omp.inner.for.end:10487// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]10488// CHECK19: omp.loop.exit:10489// CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])10490// CHECK19-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 410491// CHECK19-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 010492// CHECK19-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]10493// CHECK19: .omp.final.then:10494// CHECK19-NEXT: store i64 400, ptr [[IT]], align 810495// CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]]10496// CHECK19: .omp.final.done:10497// CHECK19-NEXT: ret void10498//10499//10500// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l17810501// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {10502// CHECK19-NEXT: entry:10503// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 410504// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 410505// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 410506// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 410507// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 410508// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 410509// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 410510// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 410511// CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 410512// CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 410513// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 410514// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 410515// CHECK19-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 410516// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 410517// CHECK19-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 210518// CHECK19-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 210519// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 410520// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]])10521// CHECK19-NEXT: ret void10522//10523//10524// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined10525// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {10526// CHECK19-NEXT: entry:10527// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 410528// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 410529// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 410530// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 410531// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 410532// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 810533// CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 410534// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 810535// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 810536// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 810537// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 410538// CHECK19-NEXT: [[I:%.*]] = alloca i64, align 810539// CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 410540// CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 410541// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 410542// CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 410543// CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 410544// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 410545// CHECK19-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 810546// CHECK19-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 810547// CHECK19-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 810548// CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 410549// CHECK19-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 410550// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 410551// CHECK19-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)10552// CHECK19-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 810553// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 610554// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]10555// CHECK19: cond.true:10556// CHECK19-NEXT: br label [[COND_END:%.*]]10557// CHECK19: cond.false:10558// CHECK19-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 810559// CHECK19-NEXT: br label [[COND_END]]10560// CHECK19: cond.end:10561// CHECK19-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]10562// CHECK19-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 810563// CHECK19-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 810564// CHECK19-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 810565// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]10566// CHECK19: omp.inner.for.cond:10567// CHECK19-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30:![0-9]+]]10568// CHECK19-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP30]]10569// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]10570// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]10571// CHECK19: omp.inner.for.body:10572// CHECK19-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]]10573// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 310574// CHECK19-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]10575// CHECK19-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP30]]10576// CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP30]]10577// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 110578// CHECK19-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP30]]10579// CHECK19-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP30]]10580// CHECK19-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i3210581// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 110582// CHECK19-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i1610583// CHECK19-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP30]]10584// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 210585// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP30]]10586// CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 110587// CHECK19-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP30]]10588// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]10589// CHECK19: omp.body.continue:10590// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]10591// CHECK19: omp.inner.for.inc:10592// CHECK19-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]]10593// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 110594// CHECK19-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]]10595// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]10596// CHECK19: omp.inner.for.end:10597// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]10598// CHECK19: omp.loop.exit:10599// CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])10600// CHECK19-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 410601// CHECK19-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 010602// CHECK19-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]10603// CHECK19: .omp.final.then:10604// CHECK19-NEXT: store i64 11, ptr [[I]], align 810605// CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]]10606// CHECK19: .omp.final.done:10607// CHECK19-NEXT: ret void10608//10609//10610// CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l9610611// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {10612// CHECK21-NEXT: entry:10613// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 810614// CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 810615// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined)10616// CHECK21-NEXT: ret void10617//10618//10619// CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined10620// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {10621// CHECK21-NEXT: entry:10622// CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 810623// CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 810624// CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 410625// CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 410626// CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 410627// CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 410628// CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 410629// CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 410630// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 410631// CHECK21-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 810632// CHECK21-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 810633// CHECK21-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 410634// CHECK21-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 410635// CHECK21-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 410636// CHECK21-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 410637// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 810638// CHECK21-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 410639// CHECK21-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)10640// CHECK21-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 410641// CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 510642// CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]10643// CHECK21: cond.true:10644// CHECK21-NEXT: br label [[COND_END:%.*]]10645// CHECK21: cond.false:10646// CHECK21-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 410647// CHECK21-NEXT: br label [[COND_END]]10648// CHECK21: cond.end:10649// CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]10650// CHECK21-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 410651// CHECK21-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 410652// CHECK21-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 410653// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]10654// CHECK21: omp.inner.for.cond:10655// CHECK21-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]]10656// CHECK21-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]]10657// CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]10658// CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]10659// CHECK21: omp.inner.for.body:10660// CHECK21-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]10661// CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 510662// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]10663// CHECK21-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]]10664// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]10665// CHECK21: omp.body.continue:10666// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]10667// CHECK21: omp.inner.for.inc:10668// CHECK21-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]10669// CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 110670// CHECK21-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]10671// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]10672// CHECK21: omp.inner.for.end:10673// CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]]10674// CHECK21: omp.loop.exit:10675// CHECK21-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])10676// CHECK21-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 410677// CHECK21-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 010678// CHECK21-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]10679// CHECK21: .omp.final.then:10680// CHECK21-NEXT: store i32 33, ptr [[I]], align 410681// CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]]10682// CHECK21: .omp.final.done:10683// CHECK21-NEXT: ret void10684//10685//10686// CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l10810687// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] {10688// CHECK21-NEXT: entry:10689// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 810690// CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 810691// CHECK21-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 810692// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 810693// CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 810694// CHECK21-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 810695// CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 810696// CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 810697// CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 810698// CHECK21-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 810699// CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 810700// CHECK21-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 210701// CHECK21-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 210702// CHECK21-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 810703// CHECK21-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 410704// CHECK21-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 410705// CHECK21-NEXT: [[TMP3:%.*]] = load i64, ptr [[LIN_CASTED]], align 810706// CHECK21-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 410707// CHECK21-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 410708// CHECK21-NEXT: [[TMP5:%.*]] = load i64, ptr [[A_CASTED]], align 810709// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined, i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])10710// CHECK21-NEXT: ret void10711//10712//10713// CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined10714// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] {10715// CHECK21-NEXT: entry:10716// CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 810717// CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 810718// CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 810719// CHECK21-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 810720// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 810721// CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 810722// CHECK21-NEXT: [[TMP:%.*]] = alloca i64, align 810723// CHECK21-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 410724// CHECK21-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 410725// CHECK21-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 810726// CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 810727// CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 810728// CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 810729// CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 410730// CHECK21-NEXT: [[IT:%.*]] = alloca i64, align 810731// CHECK21-NEXT: [[LIN2:%.*]] = alloca i32, align 410732// CHECK21-NEXT: [[A3:%.*]] = alloca i32, align 410733// CHECK21-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 810734// CHECK21-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 810735// CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 810736// CHECK21-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 810737// CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 810738// CHECK21-NEXT: [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 410739// CHECK21-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 410740// CHECK21-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 410741// CHECK21-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 410742// CHECK21-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()10743// CHECK21-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 810744// CHECK21-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 810745// CHECK21-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 810746// CHECK21-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 810747// CHECK21-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 410748// CHECK21-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 810749// CHECK21-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 410750// CHECK21-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP3]])10751// CHECK21-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)10752// CHECK21-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 810753// CHECK21-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 310754// CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]10755// CHECK21: cond.true:10756// CHECK21-NEXT: br label [[COND_END:%.*]]10757// CHECK21: cond.false:10758// CHECK21-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 810759// CHECK21-NEXT: br label [[COND_END]]10760// CHECK21: cond.end:10761// CHECK21-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]10762// CHECK21-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 810763// CHECK21-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 810764// CHECK21-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 810765// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]10766// CHECK21: omp.inner.for.cond:10767// CHECK21-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17:![0-9]+]]10768// CHECK21-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP17]]10769// CHECK21-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]10770// CHECK21-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]10771// CHECK21: omp.inner.for.body:10772// CHECK21-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]]10773// CHECK21-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 40010774// CHECK21-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]10775// CHECK21-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP17]]10776// CHECK21-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP17]]10777// CHECK21-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i6410778// CHECK21-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]]10779// CHECK21-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP17]]10780// CHECK21-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]]10781// CHECK21-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]]10782// CHECK21-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i3210783// CHECK21-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 4, !llvm.access.group [[ACC_GRP17]]10784// CHECK21-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4, !llvm.access.group [[ACC_GRP17]]10785// CHECK21-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i6410786// CHECK21-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]]10787// CHECK21-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP17]]10788// CHECK21-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]]10789// CHECK21-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]]10790// CHECK21-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i3210791// CHECK21-NEXT: store i32 [[CONV10]], ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP17]]10792// CHECK21-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP17]]10793// CHECK21-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i3210794// CHECK21-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 110795// CHECK21-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i1610796// CHECK21-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP17]]10797// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]10798// CHECK21: omp.body.continue:10799// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]10800// CHECK21: omp.inner.for.inc:10801// CHECK21-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]]10802// CHECK21-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 110803// CHECK21-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]]10804// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]10805// CHECK21: omp.inner.for.end:10806// CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]]10807// CHECK21: omp.loop.exit:10808// CHECK21-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]])10809// CHECK21-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 410810// CHECK21-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 010811// CHECK21-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]10812// CHECK21: .omp.final.then:10813// CHECK21-NEXT: store i64 400, ptr [[IT]], align 810814// CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]]10815// CHECK21: .omp.final.done:10816// CHECK21-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 410817// CHECK21-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 010818// CHECK21-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]10819// CHECK21: .omp.linear.pu:10820// CHECK21-NEXT: [[TMP22:%.*]] = load i32, ptr [[LIN2]], align 410821// CHECK21-NEXT: store i32 [[TMP22]], ptr [[LIN_ADDR]], align 410822// CHECK21-NEXT: [[TMP23:%.*]] = load i32, ptr [[A3]], align 410823// CHECK21-NEXT: store i32 [[TMP23]], ptr [[A_ADDR]], align 410824// CHECK21-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]10825// CHECK21: .omp.linear.pu.done:10826// CHECK21-NEXT: ret void10827//10828//10829// CHECK21-LABEL: define {{[^@]+}}@_Z7get_valv10830// CHECK21-SAME: () #[[ATTR2:[0-9]+]] {10831// CHECK21-NEXT: entry:10832// CHECK21-NEXT: ret i64 010833//10834//10835// CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l11610836// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {10837// CHECK21-NEXT: entry:10838// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 810839// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 810840// CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 810841// CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 810842// CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 810843// CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 810844// CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 810845// CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 810846// CHECK21-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 410847// CHECK21-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 410848// CHECK21-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 810849// CHECK21-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 210850// CHECK21-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 210851// CHECK21-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 810852// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined, i64 [[TMP1]], i64 [[TMP3]])10853// CHECK21-NEXT: ret void10854//10855//10856// CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined10857// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {10858// CHECK21-NEXT: entry:10859// CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 810860// CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 810861// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 810862// CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 810863// CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 410864// CHECK21-NEXT: [[TMP:%.*]] = alloca i16, align 210865// CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 410866// CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 410867// CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 410868// CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 410869// CHECK21-NEXT: [[IT:%.*]] = alloca i16, align 210870// CHECK21-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 810871// CHECK21-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 810872// CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 810873// CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 810874// CHECK21-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 410875// CHECK21-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 410876// CHECK21-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 410877// CHECK21-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 410878// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 810879// CHECK21-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 410880// CHECK21-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)10881// CHECK21-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 410882// CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 310883// CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]10884// CHECK21: cond.true:10885// CHECK21-NEXT: br label [[COND_END:%.*]]10886// CHECK21: cond.false:10887// CHECK21-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 410888// CHECK21-NEXT: br label [[COND_END]]10889// CHECK21: cond.end:10890// CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]10891// CHECK21-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 410892// CHECK21-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 410893// CHECK21-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 410894// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]10895// CHECK21: omp.inner.for.cond:10896// CHECK21-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20:![0-9]+]]10897// CHECK21-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP20]]10898// CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]10899// CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]10900// CHECK21: omp.inner.for.body:10901// CHECK21-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]]10902// CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 410903// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]10904// CHECK21-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i1610905// CHECK21-NEXT: store i16 [[CONV]], ptr [[IT]], align 2, !llvm.access.group [[ACC_GRP20]]10906// CHECK21-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP20]]10907// CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 110908// CHECK21-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP20]]10909// CHECK21-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP20]]10910// CHECK21-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i3210911// CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 110912// CHECK21-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i1610913// CHECK21-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP20]]10914// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]10915// CHECK21: omp.body.continue:10916// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]10917// CHECK21: omp.inner.for.inc:10918// CHECK21-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]]10919// CHECK21-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 110920// CHECK21-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]]10921// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]10922// CHECK21: omp.inner.for.end:10923// CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]]10924// CHECK21: omp.loop.exit:10925// CHECK21-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])10926// CHECK21-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 410927// CHECK21-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 010928// CHECK21-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]10929// CHECK21: .omp.final.then:10930// CHECK21-NEXT: store i16 22, ptr [[IT]], align 210931// CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]]10932// CHECK21: .omp.final.done:10933// CHECK21-NEXT: ret void10934//10935//10936// CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l14010937// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {10938// CHECK21-NEXT: entry:10939// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 810940// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 810941// CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 810942// CHECK21-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 810943// CHECK21-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 810944// CHECK21-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 810945// CHECK21-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 810946// CHECK21-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 810947// CHECK21-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 810948// CHECK21-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 810949// CHECK21-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 810950// CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 810951// CHECK21-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 810952// CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 810953// CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 810954// CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 810955// CHECK21-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 810956// CHECK21-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 810957// CHECK21-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 810958// CHECK21-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 810959// CHECK21-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 810960// CHECK21-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 810961// CHECK21-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 810962// CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 810963// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 810964// CHECK21-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 810965// CHECK21-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 810966// CHECK21-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 810967// CHECK21-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 810968// CHECK21-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 810969// CHECK21-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 810970// CHECK21-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 810971// CHECK21-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 410972// CHECK21-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 410973// CHECK21-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 810974// CHECK21-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 410975// CHECK21-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 410976// CHECK21-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 810977// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i64 [[TMP11]])10978// CHECK21-NEXT: ret void10979//10980//10981// CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined10982// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {10983// CHECK21-NEXT: entry:10984// CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 810985// CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 810986// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 810987// CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 810988// CHECK21-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 810989// CHECK21-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 810990// CHECK21-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 810991// CHECK21-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 810992// CHECK21-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 810993// CHECK21-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 810994// CHECK21-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 810995// CHECK21-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 810996// CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 410997// CHECK21-NEXT: [[TMP:%.*]] = alloca i8, align 110998// CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 410999// CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 411000// CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 411001// CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 411002// CHECK21-NEXT: [[IT:%.*]] = alloca i8, align 111003// CHECK21-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 811004// CHECK21-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 811005// CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 811006// CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 811007// CHECK21-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 811008// CHECK21-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 811009// CHECK21-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 811010// CHECK21-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 811011// CHECK21-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 811012// CHECK21-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 811013// CHECK21-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 811014// CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 811015// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 811016// CHECK21-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 811017// CHECK21-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 811018// CHECK21-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 811019// CHECK21-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 811020// CHECK21-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 811021// CHECK21-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 811022// CHECK21-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 811023// CHECK21-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 411024// CHECK21-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 411025// CHECK21-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 411026// CHECK21-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 411027// CHECK21-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 411028// CHECK21-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 811029// CHECK21-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 411030// CHECK21-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])11031// CHECK21-NEXT: br label [[OMP_DISPATCH_COND:%.*]]11032// CHECK21: omp.dispatch.cond:11033// CHECK21-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 411034// CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 2511035// CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]11036// CHECK21: cond.true:11037// CHECK21-NEXT: br label [[COND_END:%.*]]11038// CHECK21: cond.false:11039// CHECK21-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 411040// CHECK21-NEXT: br label [[COND_END]]11041// CHECK21: cond.end:11042// CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]11043// CHECK21-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 411044// CHECK21-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 411045// CHECK21-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 411046// CHECK21-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 411047// CHECK21-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 411048// CHECK21-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]11049// CHECK21-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]11050// CHECK21: omp.dispatch.body:11051// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]11052// CHECK21: omp.inner.for.cond:11053// CHECK21-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23:![0-9]+]]11054// CHECK21-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP23]]11055// CHECK21-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]11056// CHECK21-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]11057// CHECK21: omp.inner.for.body:11058// CHECK21-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]]11059// CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 111060// CHECK21-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]11061// CHECK21-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i811062// CHECK21-NEXT: store i8 [[CONV]], ptr [[IT]], align 1, !llvm.access.group [[ACC_GRP23]]11063// CHECK21-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP23]]11064// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 111065// CHECK21-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP23]]11066// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 211067// CHECK21-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP23]]11068// CHECK21-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double11069// CHECK21-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+0011070// CHECK21-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float11071// CHECK21-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP23]]11072// CHECK21-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 311073// CHECK21-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP23]]11074// CHECK21-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double11075// CHECK21-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+0011076// CHECK21-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float11077// CHECK21-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP23]]11078// CHECK21-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 111079// CHECK21-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i64 0, i64 211080// CHECK21-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP23]]11081// CHECK21-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+0011082// CHECK21-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP23]]11083// CHECK21-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]11084// CHECK21-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP23]]11085// CHECK21-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i64 311086// CHECK21-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP23]]11087// CHECK21-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+0011088// CHECK21-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP23]]11089// CHECK21-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 011090// CHECK21-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP23]]11091// CHECK21-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 111092// CHECK21-NEXT: store i64 [[ADD20]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP23]]11093// CHECK21-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 111094// CHECK21-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP23]]11095// CHECK21-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i3211096// CHECK21-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 111097// CHECK21-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i811098// CHECK21-NEXT: store i8 [[CONV23]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP23]]11099// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]11100// CHECK21: omp.body.continue:11101// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]11102// CHECK21: omp.inner.for.inc:11103// CHECK21-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]]11104// CHECK21-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 111105// CHECK21-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]]11106// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]11107// CHECK21: omp.inner.for.end:11108// CHECK21-NEXT: br label [[OMP_DISPATCH_INC:%.*]]11109// CHECK21: omp.dispatch.inc:11110// CHECK21-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 411111// CHECK21-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 411112// CHECK21-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]11113// CHECK21-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 411114// CHECK21-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 411115// CHECK21-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 411116// CHECK21-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]11117// CHECK21-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 411118// CHECK21-NEXT: br label [[OMP_DISPATCH_COND]]11119// CHECK21: omp.dispatch.end:11120// CHECK21-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]])11121// CHECK21-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 411122// CHECK21-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 011123// CHECK21-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]11124// CHECK21: .omp.final.then:11125// CHECK21-NEXT: store i8 96, ptr [[IT]], align 111126// CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]]11127// CHECK21: .omp.final.done:11128// CHECK21-NEXT: ret void11129//11130//11131// CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l19511132// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {11133// CHECK21-NEXT: entry:11134// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 811135// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 811136// CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 811137// CHECK21-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 811138// CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 811139// CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 811140// CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 811141// CHECK21-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 811142// CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 811143// CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 811144// CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 811145// CHECK21-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 811146// CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 811147// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 811148// CHECK21-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 411149// CHECK21-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 411150// CHECK21-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 811151// CHECK21-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 211152// CHECK21-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 211153// CHECK21-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 811154// CHECK21-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 111155// CHECK21-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 111156// CHECK21-NEXT: [[TMP6:%.*]] = load i64, ptr [[AAA_CASTED]], align 811157// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], ptr [[TMP0]])11158// CHECK21-NEXT: ret void11159//11160//11161// CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined11162// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {11163// CHECK21-NEXT: entry:11164// CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 811165// CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 811166// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 811167// CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 811168// CHECK21-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 811169// CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 811170// CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 411171// CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 411172// CHECK21-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 811173// CHECK21-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 811174// CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 811175// CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 811176// CHECK21-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 811177// CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 811178// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 811179// CHECK21-NEXT: ret void11180//11181//11182// CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l21411183// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {11184// CHECK21-NEXT: entry:11185// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 811186// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 811187// CHECK21-NEXT: [[B_ADDR:%.*]] = alloca i64, align 811188// CHECK21-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 811189// CHECK21-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 811190// CHECK21-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 811191// CHECK21-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 811192// CHECK21-NEXT: [[B_CASTED:%.*]] = alloca i64, align 811193// CHECK21-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 811194// CHECK21-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 411195// CHECK21-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 411196// CHECK21-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])11197// CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 811198// CHECK21-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 811199// CHECK21-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 811200// CHECK21-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 811201// CHECK21-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 811202// CHECK21-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 811203// CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 811204// CHECK21-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 811205// CHECK21-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR]], align 811206// CHECK21-NEXT: [[TMP3:%.*]] = load i64, ptr [[VLA_ADDR2]], align 811207// CHECK21-NEXT: [[TMP4:%.*]] = load ptr, ptr [[C_ADDR]], align 811208// CHECK21-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_ADDR]], align 411209// CHECK21-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 411210// CHECK21-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 811211// CHECK21-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 111212// CHECK21-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP7]] to i111213// CHECK21-NEXT: [[STOREDV:%.*]] = zext i1 [[LOADEDV]] to i811214// CHECK21-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 111215// CHECK21-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 811216// CHECK21-NEXT: [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 111217// CHECK21-NEXT: [[LOADEDV3:%.*]] = trunc i8 [[TMP9]] to i111218// CHECK21-NEXT: br i1 [[LOADEDV3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]11219// CHECK21: omp_if.then:11220// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined, ptr [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], ptr [[TMP4]], i64 [[TMP8]])11221// CHECK21-NEXT: br label [[OMP_IF_END:%.*]]11222// CHECK21: omp_if.else:11223// CHECK21-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]])11224// CHECK21-NEXT: store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 411225// CHECK21-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 411226// CHECK21-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], ptr [[TMP4]], i64 [[TMP8]]) #[[ATTR1:[0-9]+]]11227// CHECK21-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]])11228// CHECK21-NEXT: br label [[OMP_IF_END]]11229// CHECK21: omp_if.end:11230// CHECK21-NEXT: ret void11231//11232//11233// CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined11234// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {11235// CHECK21-NEXT: entry:11236// CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 811237// CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 811238// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 811239// CHECK21-NEXT: [[B_ADDR:%.*]] = alloca i64, align 811240// CHECK21-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 811241// CHECK21-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 811242// CHECK21-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 811243// CHECK21-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 811244// CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 811245// CHECK21-NEXT: [[TMP:%.*]] = alloca i64, align 811246// CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 811247// CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 811248// CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 811249// CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 411250// CHECK21-NEXT: [[IT:%.*]] = alloca i64, align 811251// CHECK21-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 811252// CHECK21-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 811253// CHECK21-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 811254// CHECK21-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 811255// CHECK21-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 811256// CHECK21-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 811257// CHECK21-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 811258// CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 811259// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 811260// CHECK21-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 811261// CHECK21-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 811262// CHECK21-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 811263// CHECK21-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 811264// CHECK21-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 811265// CHECK21-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 811266// CHECK21-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 411267// CHECK21-NEXT: [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 111268// CHECK21-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP4]] to i111269// CHECK21-NEXT: br i1 [[LOADEDV]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]11270// CHECK21: omp_if.then:11271// CHECK21-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 811272// CHECK21-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 411273// CHECK21-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP6]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)11274// CHECK21-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 811275// CHECK21-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 311276// CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]11277// CHECK21: cond.true:11278// CHECK21-NEXT: br label [[COND_END:%.*]]11279// CHECK21: cond.false:11280// CHECK21-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 811281// CHECK21-NEXT: br label [[COND_END]]11282// CHECK21: cond.end:11283// CHECK21-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]11284// CHECK21-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 811285// CHECK21-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_LB]], align 811286// CHECK21-NEXT: store i64 [[TMP9]], ptr [[DOTOMP_IV]], align 811287// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]11288// CHECK21: omp.inner.for.cond:11289// CHECK21-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP26:![0-9]+]]11290// CHECK21-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP26]]11291// CHECK21-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]]11292// CHECK21-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]11293// CHECK21: omp.inner.for.body:11294// CHECK21-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP26]]11295// CHECK21-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 40011296// CHECK21-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]11297// CHECK21-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP26]]11298// CHECK21-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP26]]11299// CHECK21-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP13]] to double11300// CHECK21-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+0011301// CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 011302// CHECK21-NEXT: store double [[ADD]], ptr [[A]], align 8, !nontemporal [[META27:![0-9]+]], !llvm.access.group [[ACC_GRP26]]11303// CHECK21-NEXT: [[A4:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 011304// CHECK21-NEXT: [[TMP14:%.*]] = load double, ptr [[A4]], align 8, !nontemporal [[META27]], !llvm.access.group [[ACC_GRP26]]11305// CHECK21-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+0011306// CHECK21-NEXT: store double [[INC]], ptr [[A4]], align 8, !nontemporal [[META27]], !llvm.access.group [[ACC_GRP26]]11307// CHECK21-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i1611308// CHECK21-NEXT: [[TMP15:%.*]] = mul nsw i64 1, [[TMP2]]11309// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP15]]11310// CHECK21-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 111311// CHECK21-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP26]]11312// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]11313// CHECK21: omp.body.continue:11314// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]11315// CHECK21: omp.inner.for.inc:11316// CHECK21-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP26]]11317// CHECK21-NEXT: [[ADD7:%.*]] = add i64 [[TMP16]], 111318// CHECK21-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP26]]11319// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]11320// CHECK21: omp.inner.for.end:11321// CHECK21-NEXT: br label [[OMP_IF_END:%.*]]11322// CHECK21: omp_if.else:11323// CHECK21-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 811324// CHECK21-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 411325// CHECK21-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP18]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)11326// CHECK21-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_UB]], align 811327// CHECK21-NEXT: [[CMP8:%.*]] = icmp ugt i64 [[TMP19]], 311328// CHECK21-NEXT: br i1 [[CMP8]], label [[COND_TRUE9:%.*]], label [[COND_FALSE10:%.*]]11329// CHECK21: cond.true9:11330// CHECK21-NEXT: br label [[COND_END11:%.*]]11331// CHECK21: cond.false10:11332// CHECK21-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_UB]], align 811333// CHECK21-NEXT: br label [[COND_END11]]11334// CHECK21: cond.end11:11335// CHECK21-NEXT: [[COND12:%.*]] = phi i64 [ 3, [[COND_TRUE9]] ], [ [[TMP20]], [[COND_FALSE10]] ]11336// CHECK21-NEXT: store i64 [[COND12]], ptr [[DOTOMP_UB]], align 811337// CHECK21-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_LB]], align 811338// CHECK21-NEXT: store i64 [[TMP21]], ptr [[DOTOMP_IV]], align 811339// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]]11340// CHECK21: omp.inner.for.cond13:11341// CHECK21-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 811342// CHECK21-NEXT: [[TMP23:%.*]] = load i64, ptr [[DOTOMP_UB]], align 811343// CHECK21-NEXT: [[CMP14:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]]11344// CHECK21-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END29:%.*]]11345// CHECK21: omp.inner.for.body15:11346// CHECK21-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_IV]], align 811347// CHECK21-NEXT: [[MUL16:%.*]] = mul i64 [[TMP24]], 40011348// CHECK21-NEXT: [[SUB17:%.*]] = sub i64 2000, [[MUL16]]11349// CHECK21-NEXT: store i64 [[SUB17]], ptr [[IT]], align 811350// CHECK21-NEXT: [[TMP25:%.*]] = load i32, ptr [[B_ADDR]], align 411351// CHECK21-NEXT: [[CONV18:%.*]] = sitofp i32 [[TMP25]] to double11352// CHECK21-NEXT: [[ADD19:%.*]] = fadd double [[CONV18]], 1.500000e+0011353// CHECK21-NEXT: [[A20:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 011354// CHECK21-NEXT: store double [[ADD19]], ptr [[A20]], align 811355// CHECK21-NEXT: [[A21:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 011356// CHECK21-NEXT: [[TMP26:%.*]] = load double, ptr [[A21]], align 811357// CHECK21-NEXT: [[INC22:%.*]] = fadd double [[TMP26]], 1.000000e+0011358// CHECK21-NEXT: store double [[INC22]], ptr [[A21]], align 811359// CHECK21-NEXT: [[CONV23:%.*]] = fptosi double [[INC22]] to i1611360// CHECK21-NEXT: [[TMP27:%.*]] = mul nsw i64 1, [[TMP2]]11361// CHECK21-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP27]]11362// CHECK21-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX24]], i64 111363// CHECK21-NEXT: store i16 [[CONV23]], ptr [[ARRAYIDX25]], align 211364// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE26:%.*]]11365// CHECK21: omp.body.continue26:11366// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC27:%.*]]11367// CHECK21: omp.inner.for.inc27:11368// CHECK21-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTOMP_IV]], align 811369// CHECK21-NEXT: [[ADD28:%.*]] = add i64 [[TMP28]], 111370// CHECK21-NEXT: store i64 [[ADD28]], ptr [[DOTOMP_IV]], align 811371// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP30:![0-9]+]]11372// CHECK21: omp.inner.for.end29:11373// CHECK21-NEXT: br label [[OMP_IF_END]]11374// CHECK21: omp_if.end:11375// CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]]11376// CHECK21: omp.loop.exit:11377// CHECK21-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 811378// CHECK21-NEXT: [[TMP30:%.*]] = load i32, ptr [[TMP29]], align 411379// CHECK21-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP30]])11380// CHECK21-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 411381// CHECK21-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 011382// CHECK21-NEXT: br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]11383// CHECK21: .omp.final.then:11384// CHECK21-NEXT: store i64 400, ptr [[IT]], align 811385// CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]]11386// CHECK21: .omp.final.done:11387// CHECK21-NEXT: ret void11388//11389//11390// CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l17811391// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {11392// CHECK21-NEXT: entry:11393// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 811394// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 811395// CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 811396// CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 811397// CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 811398// CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 811399// CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 811400// CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 811401// CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 811402// CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 811403// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 811404// CHECK21-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 411405// CHECK21-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 411406// CHECK21-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 811407// CHECK21-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 211408// CHECK21-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 211409// CHECK21-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 811410// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]])11411// CHECK21-NEXT: ret void11412//11413//11414// CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined11415// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {11416// CHECK21-NEXT: entry:11417// CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 811418// CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 811419// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 811420// CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 811421// CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 811422// CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 811423// CHECK21-NEXT: [[TMP:%.*]] = alloca i64, align 811424// CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 811425// CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 811426// CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 811427// CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 411428// CHECK21-NEXT: [[I:%.*]] = alloca i64, align 811429// CHECK21-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 811430// CHECK21-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 811431// CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 811432// CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 811433// CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 811434// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 811435// CHECK21-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 811436// CHECK21-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 811437// CHECK21-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 811438// CHECK21-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 411439// CHECK21-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 811440// CHECK21-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 411441// CHECK21-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)11442// CHECK21-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 811443// CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 611444// CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]11445// CHECK21: cond.true:11446// CHECK21-NEXT: br label [[COND_END:%.*]]11447// CHECK21: cond.false:11448// CHECK21-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 811449// CHECK21-NEXT: br label [[COND_END]]11450// CHECK21: cond.end:11451// CHECK21-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]11452// CHECK21-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 811453// CHECK21-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 811454// CHECK21-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 811455// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]11456// CHECK21: omp.inner.for.cond:11457// CHECK21-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP32:![0-9]+]]11458// CHECK21-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP32]]11459// CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]11460// CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]11461// CHECK21: omp.inner.for.body:11462// CHECK21-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP32]]11463// CHECK21-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 311464// CHECK21-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]11465// CHECK21-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP32]]11466// CHECK21-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP32]]11467// CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 111468// CHECK21-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP32]]11469// CHECK21-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP32]]11470// CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i3211471// CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 111472// CHECK21-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i1611473// CHECK21-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP32]]11474// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 211475// CHECK21-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP32]]11476// CHECK21-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 111477// CHECK21-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP32]]11478// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]11479// CHECK21: omp.body.continue:11480// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]11481// CHECK21: omp.inner.for.inc:11482// CHECK21-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP32]]11483// CHECK21-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 111484// CHECK21-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP32]]11485// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]]11486// CHECK21: omp.inner.for.end:11487// CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]]11488// CHECK21: omp.loop.exit:11489// CHECK21-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])11490// CHECK21-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 411491// CHECK21-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 011492// CHECK21-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]11493// CHECK21: .omp.final.then:11494// CHECK21-NEXT: store i64 11, ptr [[I]], align 811495// CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]]11496// CHECK21: .omp.final.done:11497// CHECK21-NEXT: ret void11498//11499//11500// CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l9611501// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {11502// CHECK23-NEXT: entry:11503// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 411504// CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 411505// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined)11506// CHECK23-NEXT: ret void11507//11508//11509// CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined11510// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {11511// CHECK23-NEXT: entry:11512// CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 411513// CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 411514// CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 411515// CHECK23-NEXT: [[TMP:%.*]] = alloca i32, align 411516// CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 411517// CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 411518// CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 411519// CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 411520// CHECK23-NEXT: [[I:%.*]] = alloca i32, align 411521// CHECK23-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 411522// CHECK23-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 411523// CHECK23-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 411524// CHECK23-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 411525// CHECK23-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 411526// CHECK23-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 411527// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 411528// CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 411529// CHECK23-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)11530// CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 411531// CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 511532// CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]11533// CHECK23: cond.true:11534// CHECK23-NEXT: br label [[COND_END:%.*]]11535// CHECK23: cond.false:11536// CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 411537// CHECK23-NEXT: br label [[COND_END]]11538// CHECK23: cond.end:11539// CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]11540// CHECK23-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 411541// CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 411542// CHECK23-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 411543// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]11544// CHECK23: omp.inner.for.cond:11545// CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]]11546// CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]]11547// CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]11548// CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]11549// CHECK23: omp.inner.for.body:11550// CHECK23-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]11551// CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 511552// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]11553// CHECK23-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]]11554// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]11555// CHECK23: omp.body.continue:11556// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]11557// CHECK23: omp.inner.for.inc:11558// CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]11559// CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 111560// CHECK23-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]11561// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]11562// CHECK23: omp.inner.for.end:11563// CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]]11564// CHECK23: omp.loop.exit:11565// CHECK23-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])11566// CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 411567// CHECK23-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 011568// CHECK23-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]11569// CHECK23: .omp.final.then:11570// CHECK23-NEXT: store i32 33, ptr [[I]], align 411571// CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]]11572// CHECK23: .omp.final.done:11573// CHECK23-NEXT: ret void11574//11575//11576// CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l10811577// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] {11578// CHECK23-NEXT: entry:11579// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 411580// CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 411581// CHECK23-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 411582// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 411583// CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 411584// CHECK23-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 411585// CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 411586// CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 411587// CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 411588// CHECK23-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 411589// CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 411590// CHECK23-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 211591// CHECK23-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 211592// CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 411593// CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 411594// CHECK23-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 411595// CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[LIN_CASTED]], align 411596// CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 411597// CHECK23-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 411598// CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[A_CASTED]], align 411599// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined, i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])11600// CHECK23-NEXT: ret void11601//11602//11603// CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined11604// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] {11605// CHECK23-NEXT: entry:11606// CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 411607// CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 411608// CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 411609// CHECK23-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 411610// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 411611// CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 811612// CHECK23-NEXT: [[TMP:%.*]] = alloca i64, align 411613// CHECK23-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 411614// CHECK23-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 411615// CHECK23-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 811616// CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 811617// CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 811618// CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 811619// CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 411620// CHECK23-NEXT: [[IT:%.*]] = alloca i64, align 811621// CHECK23-NEXT: [[LIN2:%.*]] = alloca i32, align 411622// CHECK23-NEXT: [[A3:%.*]] = alloca i32, align 411623// CHECK23-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 411624// CHECK23-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 411625// CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 411626// CHECK23-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 411627// CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 411628// CHECK23-NEXT: [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 411629// CHECK23-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 411630// CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 411631// CHECK23-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 411632// CHECK23-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()11633// CHECK23-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 811634// CHECK23-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 811635// CHECK23-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 811636// CHECK23-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 811637// CHECK23-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 411638// CHECK23-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 411639// CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 411640// CHECK23-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP3]])11641// CHECK23-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)11642// CHECK23-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 811643// CHECK23-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 311644// CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]11645// CHECK23: cond.true:11646// CHECK23-NEXT: br label [[COND_END:%.*]]11647// CHECK23: cond.false:11648// CHECK23-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 811649// CHECK23-NEXT: br label [[COND_END]]11650// CHECK23: cond.end:11651// CHECK23-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]11652// CHECK23-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 811653// CHECK23-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 811654// CHECK23-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 811655// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]11656// CHECK23: omp.inner.for.cond:11657// CHECK23-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18:![0-9]+]]11658// CHECK23-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP18]]11659// CHECK23-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]11660// CHECK23-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]11661// CHECK23: omp.inner.for.body:11662// CHECK23-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]]11663// CHECK23-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 40011664// CHECK23-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]11665// CHECK23-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP18]]11666// CHECK23-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP18]]11667// CHECK23-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i6411668// CHECK23-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]]11669// CHECK23-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP18]]11670// CHECK23-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]]11671// CHECK23-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]]11672// CHECK23-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i3211673// CHECK23-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 4, !llvm.access.group [[ACC_GRP18]]11674// CHECK23-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4, !llvm.access.group [[ACC_GRP18]]11675// CHECK23-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i6411676// CHECK23-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]]11677// CHECK23-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP18]]11678// CHECK23-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]]11679// CHECK23-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]]11680// CHECK23-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i3211681// CHECK23-NEXT: store i32 [[CONV10]], ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP18]]11682// CHECK23-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP18]]11683// CHECK23-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i3211684// CHECK23-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 111685// CHECK23-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i1611686// CHECK23-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP18]]11687// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]11688// CHECK23: omp.body.continue:11689// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]11690// CHECK23: omp.inner.for.inc:11691// CHECK23-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]]11692// CHECK23-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 111693// CHECK23-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]]11694// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]11695// CHECK23: omp.inner.for.end:11696// CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]]11697// CHECK23: omp.loop.exit:11698// CHECK23-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]])11699// CHECK23-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 411700// CHECK23-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 011701// CHECK23-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]11702// CHECK23: .omp.final.then:11703// CHECK23-NEXT: store i64 400, ptr [[IT]], align 811704// CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]]11705// CHECK23: .omp.final.done:11706// CHECK23-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 411707// CHECK23-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 011708// CHECK23-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]11709// CHECK23: .omp.linear.pu:11710// CHECK23-NEXT: [[TMP22:%.*]] = load i32, ptr [[LIN2]], align 411711// CHECK23-NEXT: store i32 [[TMP22]], ptr [[LIN_ADDR]], align 411712// CHECK23-NEXT: [[TMP23:%.*]] = load i32, ptr [[A3]], align 411713// CHECK23-NEXT: store i32 [[TMP23]], ptr [[A_ADDR]], align 411714// CHECK23-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]11715// CHECK23: .omp.linear.pu.done:11716// CHECK23-NEXT: ret void11717//11718//11719// CHECK23-LABEL: define {{[^@]+}}@_Z7get_valv11720// CHECK23-SAME: () #[[ATTR2:[0-9]+]] {11721// CHECK23-NEXT: entry:11722// CHECK23-NEXT: ret i64 011723//11724//11725// CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l11611726// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {11727// CHECK23-NEXT: entry:11728// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 411729// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 411730// CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 411731// CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 411732// CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 411733// CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 411734// CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 411735// CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 411736// CHECK23-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 411737// CHECK23-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 411738// CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 411739// CHECK23-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 211740// CHECK23-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 211741// CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 411742// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined, i32 [[TMP1]], i32 [[TMP3]])11743// CHECK23-NEXT: ret void11744//11745//11746// CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined11747// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {11748// CHECK23-NEXT: entry:11749// CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 411750// CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 411751// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 411752// CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 411753// CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 411754// CHECK23-NEXT: [[TMP:%.*]] = alloca i16, align 211755// CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 411756// CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 411757// CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 411758// CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 411759// CHECK23-NEXT: [[IT:%.*]] = alloca i16, align 211760// CHECK23-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 411761// CHECK23-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 411762// CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 411763// CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 411764// CHECK23-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 411765// CHECK23-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 411766// CHECK23-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 411767// CHECK23-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 411768// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 411769// CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 411770// CHECK23-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)11771// CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 411772// CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 311773// CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]11774// CHECK23: cond.true:11775// CHECK23-NEXT: br label [[COND_END:%.*]]11776// CHECK23: cond.false:11777// CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 411778// CHECK23-NEXT: br label [[COND_END]]11779// CHECK23: cond.end:11780// CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]11781// CHECK23-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 411782// CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 411783// CHECK23-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 411784// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]11785// CHECK23: omp.inner.for.cond:11786// CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21:![0-9]+]]11787// CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP21]]11788// CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]11789// CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]11790// CHECK23: omp.inner.for.body:11791// CHECK23-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]]11792// CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 411793// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]11794// CHECK23-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i1611795// CHECK23-NEXT: store i16 [[CONV]], ptr [[IT]], align 2, !llvm.access.group [[ACC_GRP21]]11796// CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP21]]11797// CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 111798// CHECK23-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP21]]11799// CHECK23-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP21]]11800// CHECK23-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i3211801// CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 111802// CHECK23-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i1611803// CHECK23-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP21]]11804// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]11805// CHECK23: omp.body.continue:11806// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]11807// CHECK23: omp.inner.for.inc:11808// CHECK23-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]]11809// CHECK23-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 111810// CHECK23-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]]11811// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]11812// CHECK23: omp.inner.for.end:11813// CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]]11814// CHECK23: omp.loop.exit:11815// CHECK23-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])11816// CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 411817// CHECK23-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 011818// CHECK23-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]11819// CHECK23: .omp.final.then:11820// CHECK23-NEXT: store i16 22, ptr [[IT]], align 211821// CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]]11822// CHECK23: .omp.final.done:11823// CHECK23-NEXT: ret void11824//11825//11826// CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l14011827// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {11828// CHECK23-NEXT: entry:11829// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 411830// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 411831// CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 411832// CHECK23-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 411833// CHECK23-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 411834// CHECK23-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 411835// CHECK23-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 411836// CHECK23-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 411837// CHECK23-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 411838// CHECK23-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 411839// CHECK23-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 411840// CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 411841// CHECK23-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 411842// CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 411843// CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 411844// CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 411845// CHECK23-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 411846// CHECK23-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 411847// CHECK23-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 411848// CHECK23-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 411849// CHECK23-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 411850// CHECK23-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 411851// CHECK23-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 411852// CHECK23-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 411853// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 411854// CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 411855// CHECK23-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 411856// CHECK23-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 411857// CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 411858// CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 411859// CHECK23-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 411860// CHECK23-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 411861// CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 411862// CHECK23-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 411863// CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 411864// CHECK23-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 411865// CHECK23-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 411866// CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 411867// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i32 [[TMP11]])11868// CHECK23-NEXT: ret void11869//11870//11871// CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined11872// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {11873// CHECK23-NEXT: entry:11874// CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 411875// CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 411876// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 411877// CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 411878// CHECK23-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 411879// CHECK23-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 411880// CHECK23-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 411881// CHECK23-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 411882// CHECK23-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 411883// CHECK23-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 411884// CHECK23-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 411885// CHECK23-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 411886// CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 411887// CHECK23-NEXT: [[TMP:%.*]] = alloca i8, align 111888// CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 411889// CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 411890// CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 411891// CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 411892// CHECK23-NEXT: [[IT:%.*]] = alloca i8, align 111893// CHECK23-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 411894// CHECK23-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 411895// CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 411896// CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 411897// CHECK23-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 411898// CHECK23-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 411899// CHECK23-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 411900// CHECK23-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 411901// CHECK23-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 411902// CHECK23-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 411903// CHECK23-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 411904// CHECK23-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 411905// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 411906// CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 411907// CHECK23-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 411908// CHECK23-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 411909// CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 411910// CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 411911// CHECK23-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 411912// CHECK23-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 411913// CHECK23-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 411914// CHECK23-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 411915// CHECK23-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 411916// CHECK23-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 411917// CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 411918// CHECK23-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 411919// CHECK23-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 411920// CHECK23-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])11921// CHECK23-NEXT: br label [[OMP_DISPATCH_COND:%.*]]11922// CHECK23: omp.dispatch.cond:11923// CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 411924// CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 2511925// CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]11926// CHECK23: cond.true:11927// CHECK23-NEXT: br label [[COND_END:%.*]]11928// CHECK23: cond.false:11929// CHECK23-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 411930// CHECK23-NEXT: br label [[COND_END]]11931// CHECK23: cond.end:11932// CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]11933// CHECK23-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 411934// CHECK23-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 411935// CHECK23-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 411936// CHECK23-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 411937// CHECK23-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 411938// CHECK23-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]11939// CHECK23-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]11940// CHECK23: omp.dispatch.body:11941// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]11942// CHECK23: omp.inner.for.cond:11943// CHECK23-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24:![0-9]+]]11944// CHECK23-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP24]]11945// CHECK23-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]11946// CHECK23-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]11947// CHECK23: omp.inner.for.body:11948// CHECK23-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]]11949// CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 111950// CHECK23-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]11951// CHECK23-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i811952// CHECK23-NEXT: store i8 [[CONV]], ptr [[IT]], align 1, !llvm.access.group [[ACC_GRP24]]11953// CHECK23-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP24]]11954// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 111955// CHECK23-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP24]]11956// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 211957// CHECK23-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]]11958// CHECK23-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double11959// CHECK23-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+0011960// CHECK23-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float11961// CHECK23-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]]11962// CHECK23-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 311963// CHECK23-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP24]]11964// CHECK23-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double11965// CHECK23-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+0011966// CHECK23-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float11967// CHECK23-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP24]]11968// CHECK23-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 111969// CHECK23-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i32 0, i32 211970// CHECK23-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP24]]11971// CHECK23-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+0011972// CHECK23-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP24]]11973// CHECK23-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]11974// CHECK23-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP23]]11975// CHECK23-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i32 311976// CHECK23-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP24]]11977// CHECK23-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+0011978// CHECK23-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP24]]11979// CHECK23-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 011980// CHECK23-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP24]]11981// CHECK23-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 111982// CHECK23-NEXT: store i64 [[ADD20]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP24]]11983// CHECK23-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 111984// CHECK23-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP24]]11985// CHECK23-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i3211986// CHECK23-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 111987// CHECK23-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i811988// CHECK23-NEXT: store i8 [[CONV23]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP24]]11989// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]11990// CHECK23: omp.body.continue:11991// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]11992// CHECK23: omp.inner.for.inc:11993// CHECK23-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]]11994// CHECK23-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 111995// CHECK23-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]]11996// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]11997// CHECK23: omp.inner.for.end:11998// CHECK23-NEXT: br label [[OMP_DISPATCH_INC:%.*]]11999// CHECK23: omp.dispatch.inc:12000// CHECK23-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 412001// CHECK23-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 412002// CHECK23-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]12003// CHECK23-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 412004// CHECK23-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 412005// CHECK23-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 412006// CHECK23-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]12007// CHECK23-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 412008// CHECK23-NEXT: br label [[OMP_DISPATCH_COND]]12009// CHECK23: omp.dispatch.end:12010// CHECK23-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]])12011// CHECK23-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 412012// CHECK23-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 012013// CHECK23-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]12014// CHECK23: .omp.final.then:12015// CHECK23-NEXT: store i8 96, ptr [[IT]], align 112016// CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]]12017// CHECK23: .omp.final.done:12018// CHECK23-NEXT: ret void12019//12020//12021// CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l19512022// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {12023// CHECK23-NEXT: entry:12024// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 412025// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 412026// CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 412027// CHECK23-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 412028// CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 412029// CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 412030// CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 412031// CHECK23-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 412032// CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 412033// CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 412034// CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 412035// CHECK23-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 412036// CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 412037// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 412038// CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 412039// CHECK23-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 412040// CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 412041// CHECK23-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 212042// CHECK23-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 212043// CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 412044// CHECK23-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 112045// CHECK23-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 112046// CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[AAA_CASTED]], align 412047// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], ptr [[TMP0]])12048// CHECK23-NEXT: ret void12049//12050//12051// CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined12052// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {12053// CHECK23-NEXT: entry:12054// CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 412055// CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 412056// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 412057// CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 412058// CHECK23-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 412059// CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 412060// CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 412061// CHECK23-NEXT: [[TMP:%.*]] = alloca i32, align 412062// CHECK23-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 412063// CHECK23-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 412064// CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 412065// CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 412066// CHECK23-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 412067// CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 412068// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 412069// CHECK23-NEXT: ret void12070//12071//12072// CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l21412073// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {12074// CHECK23-NEXT: entry:12075// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 412076// CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 412077// CHECK23-NEXT: [[B_ADDR:%.*]] = alloca i32, align 412078// CHECK23-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 412079// CHECK23-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 412080// CHECK23-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 412081// CHECK23-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 412082// CHECK23-NEXT: [[B_CASTED:%.*]] = alloca i32, align 412083// CHECK23-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 412084// CHECK23-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 412085// CHECK23-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 412086// CHECK23-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])12087// CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 412088// CHECK23-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 412089// CHECK23-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 412090// CHECK23-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 412091// CHECK23-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 412092// CHECK23-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 412093// CHECK23-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 412094// CHECK23-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 412095// CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR]], align 412096// CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[VLA_ADDR2]], align 412097// CHECK23-NEXT: [[TMP4:%.*]] = load ptr, ptr [[C_ADDR]], align 412098// CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_ADDR]], align 412099// CHECK23-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 412100// CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[B_CASTED]], align 412101// CHECK23-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 112102// CHECK23-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP7]] to i112103// CHECK23-NEXT: [[STOREDV:%.*]] = zext i1 [[LOADEDV]] to i812104// CHECK23-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 112105// CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 412106// CHECK23-NEXT: [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 112107// CHECK23-NEXT: [[LOADEDV3:%.*]] = trunc i8 [[TMP9]] to i112108// CHECK23-NEXT: br i1 [[LOADEDV3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]12109// CHECK23: omp_if.then:12110// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined, ptr [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], ptr [[TMP4]], i32 [[TMP8]])12111// CHECK23-NEXT: br label [[OMP_IF_END:%.*]]12112// CHECK23: omp_if.else:12113// CHECK23-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]])12114// CHECK23-NEXT: store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 412115// CHECK23-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 412116// CHECK23-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], ptr [[TMP4]], i32 [[TMP8]]) #[[ATTR1:[0-9]+]]12117// CHECK23-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]])12118// CHECK23-NEXT: br label [[OMP_IF_END]]12119// CHECK23: omp_if.end:12120// CHECK23-NEXT: ret void12121//12122//12123// CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined12124// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {12125// CHECK23-NEXT: entry:12126// CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 412127// CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 412128// CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 412129// CHECK23-NEXT: [[B_ADDR:%.*]] = alloca i32, align 412130// CHECK23-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 412131// CHECK23-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 412132// CHECK23-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 412133// CHECK23-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 412134// CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 812135// CHECK23-NEXT: [[TMP:%.*]] = alloca i64, align 412136// CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 812137// CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 812138// CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 812139// CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 412140// CHECK23-NEXT: [[IT:%.*]] = alloca i64, align 812141// CHECK23-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 412142// CHECK23-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 412143// CHECK23-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 412144// CHECK23-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 412145// CHECK23-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 412146// CHECK23-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 412147// CHECK23-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 412148// CHECK23-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 412149// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 412150// CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 412151// CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 412152// CHECK23-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 412153// CHECK23-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 812154// CHECK23-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 812155// CHECK23-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 812156// CHECK23-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 412157// CHECK23-NEXT: [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 112158// CHECK23-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP4]] to i112159// CHECK23-NEXT: br i1 [[LOADEDV]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]12160// CHECK23: omp_if.then:12161// CHECK23-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 412162// CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 412163// CHECK23-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP6]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)12164// CHECK23-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 812165// CHECK23-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 312166// CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]12167// CHECK23: cond.true:12168// CHECK23-NEXT: br label [[COND_END:%.*]]12169// CHECK23: cond.false:12170// CHECK23-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 812171// CHECK23-NEXT: br label [[COND_END]]12172// CHECK23: cond.end:12173// CHECK23-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]12174// CHECK23-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 812175// CHECK23-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_LB]], align 812176// CHECK23-NEXT: store i64 [[TMP9]], ptr [[DOTOMP_IV]], align 812177// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]12178// CHECK23: omp.inner.for.cond:12179// CHECK23-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP27:![0-9]+]]12180// CHECK23-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP27]]12181// CHECK23-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]]12182// CHECK23-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]12183// CHECK23: omp.inner.for.body:12184// CHECK23-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP27]]12185// CHECK23-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 40012186// CHECK23-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]12187// CHECK23-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP27]]12188// CHECK23-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP27]]12189// CHECK23-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP13]] to double12190// CHECK23-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+0012191// CHECK23-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 012192// CHECK23-NEXT: store double [[ADD]], ptr [[A]], align 4, !nontemporal [[META28:![0-9]+]], !llvm.access.group [[ACC_GRP27]]12193// CHECK23-NEXT: [[A4:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 012194// CHECK23-NEXT: [[TMP14:%.*]] = load double, ptr [[A4]], align 4, !nontemporal [[META28]], !llvm.access.group [[ACC_GRP27]]12195// CHECK23-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+0012196// CHECK23-NEXT: store double [[INC]], ptr [[A4]], align 4, !nontemporal [[META28]], !llvm.access.group [[ACC_GRP27]]12197// CHECK23-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i1612198// CHECK23-NEXT: [[TMP15:%.*]] = mul nsw i32 1, [[TMP2]]12199// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP15]]12200// CHECK23-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 112201// CHECK23-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP27]]12202// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]12203// CHECK23: omp.body.continue:12204// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]12205// CHECK23: omp.inner.for.inc:12206// CHECK23-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP27]]12207// CHECK23-NEXT: [[ADD7:%.*]] = add i64 [[TMP16]], 112208// CHECK23-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP27]]12209// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]12210// CHECK23: omp.inner.for.end:12211// CHECK23-NEXT: br label [[OMP_IF_END:%.*]]12212// CHECK23: omp_if.else:12213// CHECK23-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 412214// CHECK23-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 412215// CHECK23-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP18]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)12216// CHECK23-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_UB]], align 812217// CHECK23-NEXT: [[CMP8:%.*]] = icmp ugt i64 [[TMP19]], 312218// CHECK23-NEXT: br i1 [[CMP8]], label [[COND_TRUE9:%.*]], label [[COND_FALSE10:%.*]]12219// CHECK23: cond.true9:12220// CHECK23-NEXT: br label [[COND_END11:%.*]]12221// CHECK23: cond.false10:12222// CHECK23-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_UB]], align 812223// CHECK23-NEXT: br label [[COND_END11]]12224// CHECK23: cond.end11:12225// CHECK23-NEXT: [[COND12:%.*]] = phi i64 [ 3, [[COND_TRUE9]] ], [ [[TMP20]], [[COND_FALSE10]] ]12226// CHECK23-NEXT: store i64 [[COND12]], ptr [[DOTOMP_UB]], align 812227// CHECK23-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_LB]], align 812228// CHECK23-NEXT: store i64 [[TMP21]], ptr [[DOTOMP_IV]], align 812229// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]]12230// CHECK23: omp.inner.for.cond13:12231// CHECK23-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 812232// CHECK23-NEXT: [[TMP23:%.*]] = load i64, ptr [[DOTOMP_UB]], align 812233// CHECK23-NEXT: [[CMP14:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]]12234// CHECK23-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END29:%.*]]12235// CHECK23: omp.inner.for.body15:12236// CHECK23-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_IV]], align 812237// CHECK23-NEXT: [[MUL16:%.*]] = mul i64 [[TMP24]], 40012238// CHECK23-NEXT: [[SUB17:%.*]] = sub i64 2000, [[MUL16]]12239// CHECK23-NEXT: store i64 [[SUB17]], ptr [[IT]], align 812240// CHECK23-NEXT: [[TMP25:%.*]] = load i32, ptr [[B_ADDR]], align 412241// CHECK23-NEXT: [[CONV18:%.*]] = sitofp i32 [[TMP25]] to double12242// CHECK23-NEXT: [[ADD19:%.*]] = fadd double [[CONV18]], 1.500000e+0012243// CHECK23-NEXT: [[A20:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 012244// CHECK23-NEXT: store double [[ADD19]], ptr [[A20]], align 412245// CHECK23-NEXT: [[A21:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 012246// CHECK23-NEXT: [[TMP26:%.*]] = load double, ptr [[A21]], align 412247// CHECK23-NEXT: [[INC22:%.*]] = fadd double [[TMP26]], 1.000000e+0012248// CHECK23-NEXT: store double [[INC22]], ptr [[A21]], align 412249// CHECK23-NEXT: [[CONV23:%.*]] = fptosi double [[INC22]] to i1612250// CHECK23-NEXT: [[TMP27:%.*]] = mul nsw i32 1, [[TMP2]]12251// CHECK23-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP27]]12252// CHECK23-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX24]], i32 112253// CHECK23-NEXT: store i16 [[CONV23]], ptr [[ARRAYIDX25]], align 212254// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE26:%.*]]12255// CHECK23: omp.body.continue26:12256// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC27:%.*]]12257// CHECK23: omp.inner.for.inc27:12258// CHECK23-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTOMP_IV]], align 812259// CHECK23-NEXT: [[ADD28:%.*]] = add i64 [[TMP28]], 112260// CHECK23-NEXT: store i64 [[ADD28]], ptr [[DOTOMP_IV]], align 812261// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP31:![0-9]+]]12262// CHECK23: omp.inner.for.end29:12263// CHECK23-NEXT: br label [[OMP_IF_END]]12264// CHECK23: omp_if.end:12265// CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]]12266// CHECK23: omp.loop.exit:12267// CHECK23-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 412268// CHECK23-NEXT: [[TMP30:%.*]] = load i32, ptr [[TMP29]], align 412269// CHECK23-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP30]])12270// CHECK23-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 412271// CHECK23-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 012272// CHECK23-NEXT: br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]12273// CHECK23: .omp.final.then:12274// CHECK23-NEXT: store i64 400, ptr [[IT]], align 812275// CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]]12276// CHECK23: .omp.final.done:12277// CHECK23-NEXT: ret void12278//12279//12280// CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l17812281// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {12282// CHECK23-NEXT: entry:12283// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 412284// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 412285// CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 412286// CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 412287// CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 412288// CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 412289// CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 412290// CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 412291// CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 412292// CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 412293// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 412294// CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 412295// CHECK23-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 412296// CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 412297// CHECK23-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 212298// CHECK23-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 212299// CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 412300// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]])12301// CHECK23-NEXT: ret void12302//12303//12304// CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined12305// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {12306// CHECK23-NEXT: entry:12307// CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 412308// CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 412309// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 412310// CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 412311// CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 412312// CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 812313// CHECK23-NEXT: [[TMP:%.*]] = alloca i64, align 412314// CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 812315// CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 812316// CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 812317// CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 412318// CHECK23-NEXT: [[I:%.*]] = alloca i64, align 812319// CHECK23-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 412320// CHECK23-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 412321// CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 412322// CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 412323// CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 412324// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 412325// CHECK23-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 812326// CHECK23-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 812327// CHECK23-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 812328// CHECK23-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 412329// CHECK23-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 412330// CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 412331// CHECK23-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)12332// CHECK23-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 812333// CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 612334// CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]12335// CHECK23: cond.true:12336// CHECK23-NEXT: br label [[COND_END:%.*]]12337// CHECK23: cond.false:12338// CHECK23-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 812339// CHECK23-NEXT: br label [[COND_END]]12340// CHECK23: cond.end:12341// CHECK23-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]12342// CHECK23-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 812343// CHECK23-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 812344// CHECK23-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 812345// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]12346// CHECK23: omp.inner.for.cond:12347// CHECK23-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP33:![0-9]+]]12348// CHECK23-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP33]]12349// CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]12350// CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]12351// CHECK23: omp.inner.for.body:12352// CHECK23-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP33]]12353// CHECK23-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 312354// CHECK23-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]12355// CHECK23-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP33]]12356// CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]]12357// CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 112358// CHECK23-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]]12359// CHECK23-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP33]]12360// CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i3212361// CHECK23-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 112362// CHECK23-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i1612363// CHECK23-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP33]]12364// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 212365// CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP33]]12366// CHECK23-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 112367// CHECK23-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP33]]12368// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]12369// CHECK23: omp.body.continue:12370// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]12371// CHECK23: omp.inner.for.inc:12372// CHECK23-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP33]]12373// CHECK23-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 112374// CHECK23-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP33]]12375// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]12376// CHECK23: omp.inner.for.end:12377// CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]]12378// CHECK23: omp.loop.exit:12379// CHECK23-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])12380// CHECK23-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 412381// CHECK23-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 012382// CHECK23-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]12383// CHECK23: .omp.final.then:12384// CHECK23-NEXT: store i64 11, ptr [[I]], align 812385// CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]]12386// CHECK23: .omp.final.done:12387// CHECK23-NEXT: ret void12388//12389