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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _2// Test host codegen.3// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s4// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s5// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s6// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s7// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s8// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s9 10// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s11// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s12// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s13// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s14// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s15// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s16 17// Test target parallel for codegen - host bc file has to be created first.18// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc19// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s -check-prefix=TCHECK20// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s21// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s -check-prefix=TCHECK22// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc23// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s -check-prefix=TCHECK24// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s25// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s -check-prefix=TCHECK26 27// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc28// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s29// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s30// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s31// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc32// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s33// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s34// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s35 36// Check that no target code is emitted if no omptests flag was provided.37// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK-NTARGET38 39// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY2 %s40 41// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix OMP-DEFAULT42// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s43// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix OMP-DEFAULT44// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix OMP-DEfAULT45// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s46// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix OMP-DEFAULT47 48// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s49// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s50// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s51// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s52// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s53// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s54 55// Test target parallel for codegen - host bc file has to be created first.56// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc57// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s -check-prefix=TCHECK58// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s59// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s -check-prefix=TCHECK60 61// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc62// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s -check-prefix=TCHECK63// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s64// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s -check-prefix=TCHECK65 66// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc67// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s68// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s69// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s70// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc71// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s72// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s73// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s74 75// Check that no target code is emitted if no omptests flag was provided.76// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK-NTARGET-OMP-DEFAULT77 78// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY2 %s79 80// expected-no-diagnostics81#ifndef HEADER82#define HEADER83 84 85 86 87 88// We have 7 target regions89 90 91 92 93 94// We have 4 initializers, one for the 500 priority, another one for 501, or more for the default priority, and the last one for the offloading registration function.95 96 97extern int *R;98 99struct SA {100  int arr[4];101  void foo() {102    int a = *R;103    a += 1;104    *R = a;105  }106  SA() {107    int a = *R;108    a += 2;109    *R = a;110  }111  ~SA() {112    int a = *R;113    a += 3;114    *R = a;115  }116};117 118struct SB {119  int arr[8];120  void foo() {121    int a = *R;122    #pragma omp target parallel loop123    for (int i = 0; i < 10; ++i)124      a += 4;125    *R = a;126  }127  SB() {128    int a = *R;129    a += 5;130    *R = a;131  }132  ~SB() {133    int a = *R;134    a += 6;135    *R = a;136  }137};138 139struct SC {140  int arr[16];141  void foo() {142    int a = *R;143    a += 7;144    *R = a;145  }146  SC() {147    int a = *R;148    #pragma omp target parallel loop149    for (int i = 0; i < 10; ++i)150      a += 8;151    *R = a;152  }153  ~SC() {154    int a = *R;155    a += 9;156    *R = a;157  }158};159 160struct SD {161  int arr[32];162  void foo() {163    int a = *R;164    a += 10;165    *R = a;166  }167  SD() {168    int a = *R;169    a += 11;170    *R = a;171  }172  ~SD() {173    int a = *R;174    #pragma omp target parallel loop175    for (int i = 0; i < 10; ++i)176      a += 12;177    *R = a;178  }179};180 181struct SE {182  int arr[64];183  void foo() {184    int a = *R;185    #pragma omp target parallel loop if(target: 0)186    for (int i = 0; i < 10; ++i)187      a += 13;188    *R = a;189  }190  SE() {191    int a = *R;192    #pragma omp target parallel loop193    for (int i = 0; i < 10; ++i)194      a += 14;195    *R = a;196  }197  ~SE() {198    int a = *R;199    #pragma omp target parallel loop200    for (int i = 0; i < 10; ++i)201      a += 15;202    *R = a;203  }204};205 206template <int x>207struct ST {208  int arr[128 + x];209  void foo() {210    int a = *R;211    #pragma omp target parallel loop212    for (int i = 0; i < 10; ++i)213      a += 16 + x;214    *R = a;215  }216  ST() {217    int a = *R;218    #pragma omp target parallel loop219    for (int i = 0; i < 10; ++i)220      a += 17 + x;221    *R = a;222  }223  ~ST() {224    int a = *R;225    #pragma omp target parallel loop226    for (int i = 0; i < 10; ++i)227      a += 18 + x;228    *R = a;229  }230};231 232// We have to make sure we us all the target regions:233 234 235 236 237// We have 2 initializers with priority 500238 239// We have 1 initializers with priority 501240 241// We have 6 initializers with default priority242 243static __attribute__((init_priority(500))) SA a1;244SA a2;245SB __attribute__((init_priority(500))) b1;246SB __attribute__((init_priority(501))) b2;247static SC c1;248SD d1;249SE e1;250ST<100> t1;251ST<1000> t2;252 253 254int bar(int a){255  int r = a;256 257  a1.foo();258  a2.foo();259  b1.foo();260  b2.foo();261  c1.foo();262  d1.foo();263  e1.foo();264  t1.foo();265  t2.foo();266 267  #pragma omp target parallel loop268  for (int i = 0; i < 10; ++i)269    ++r;270 271  return r + *R;272}273 274// Check metadata is properly generated:275 276 277#endif278// CHECK-LABEL: define {{[^@]+}}@__cxx_global_var_init279// CHECK-SAME: () #[[ATTR3:[0-9]+]] {280// CHECK-NEXT:  entry:281// CHECK-NEXT:    call void @_ZN2SAC1Ev(ptr noundef nonnull align 4 dereferenceable(16) @_ZL2a1)282// CHECK-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SAD1Ev, ptr @_ZL2a1, ptr @__dso_handle) #[[ATTR2:[0-9]+]]283// CHECK-NEXT:    ret void284//285//286//287//288//289//290// CHECK-LABEL: define {{[^@]+}}@__cxx_global_var_init.1291// CHECK-SAME: () #[[ATTR3]] {292// CHECK-NEXT:  entry:293// CHECK-NEXT:    call void @_ZN2SAC1Ev(ptr noundef nonnull align 4 dereferenceable(16) @a2)294// CHECK-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SAD1Ev, ptr @a2, ptr @__dso_handle) #[[ATTR2]]295// CHECK-NEXT:    ret void296//297//298// CHECK-LABEL: define {{[^@]+}}@__cxx_global_var_init.2299// CHECK-SAME: () #[[ATTR3]] {300// CHECK-NEXT:  entry:301// CHECK-NEXT:    call void @_ZN2SBC1Ev(ptr noundef nonnull align 4 dereferenceable(32) @b1)302// CHECK-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SBD1Ev, ptr @b1, ptr @__dso_handle) #[[ATTR2]]303// CHECK-NEXT:    ret void304//305//306//307//308//309//310// CHECK-LABEL: define {{[^@]+}}@__cxx_global_var_init.3311// CHECK-SAME: () #[[ATTR3]] {312// CHECK-NEXT:  entry:313// CHECK-NEXT:    call void @_ZN2SBC1Ev(ptr noundef nonnull align 4 dereferenceable(32) @b2)314// CHECK-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SBD1Ev, ptr @b2, ptr @__dso_handle) #[[ATTR2]]315// CHECK-NEXT:    ret void316//317//318// CHECK-LABEL: define {{[^@]+}}@__cxx_global_var_init.4319// CHECK-SAME: () #[[ATTR3]] {320// CHECK-NEXT:  entry:321// CHECK-NEXT:    call void @_ZN2SCC1Ev(ptr noundef nonnull align 4 dereferenceable(64) @_ZL2c1)322// CHECK-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SCD1Ev, ptr @_ZL2c1, ptr @__dso_handle) #[[ATTR2]]323// CHECK-NEXT:    ret void324//325//326//327//328//329//330//331//332// CHECK-LABEL: define {{[^@]+}}@__cxx_global_var_init.7333// CHECK-SAME: () #[[ATTR3]] {334// CHECK-NEXT:  entry:335// CHECK-NEXT:    call void @_ZN2SDC1Ev(ptr noundef nonnull align 4 dereferenceable(128) @d1)336// CHECK-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SDD1Ev, ptr @d1, ptr @__dso_handle) #[[ATTR2]]337// CHECK-NEXT:    ret void338//339//340//341//342//343//344//345//346// CHECK-LABEL: define {{[^@]+}}@__cxx_global_var_init.10347// CHECK-SAME: () #[[ATTR3]] {348// CHECK-NEXT:  entry:349// CHECK-NEXT:    call void @_ZN2SEC1Ev(ptr noundef nonnull align 4 dereferenceable(256) @e1)350// CHECK-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SED1Ev, ptr @e1, ptr @__dso_handle) #[[ATTR2]]351// CHECK-NEXT:    ret void352//353//354//355//356//357//358//359//360//361//362// CHECK-LABEL: define {{[^@]+}}@__cxx_global_var_init.15363// CHECK-SAME: () #[[ATTR3]] {364// CHECK-NEXT:  entry:365// CHECK-NEXT:    call void @_ZN2STILi100EEC1Ev(ptr noundef nonnull align 4 dereferenceable(912) @t1)366// CHECK-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2STILi100EED1Ev, ptr @t1, ptr @__dso_handle) #[[ATTR2]]367// CHECK-NEXT:    ret void368//369//370//371//372//373//374//375//376//377//378// CHECK-LABEL: define {{[^@]+}}@__cxx_global_var_init.20379// CHECK-SAME: () #[[ATTR3]] {380// CHECK-NEXT:  entry:381// CHECK-NEXT:    call void @_ZN2STILi1000EEC1Ev(ptr noundef nonnull align 4 dereferenceable(4512) @t2)382// CHECK-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2STILi1000EED1Ev, ptr @t2, ptr @__dso_handle) #[[ATTR2]]383// CHECK-NEXT:    ret void384//385//386//387//388//389//390//391//392//393//394//395//396//397//398//399//400//401//402// CHECK-LABEL: define {{[^@]+}}@_GLOBAL__I_000500403// CHECK-SAME: () #[[ATTR3]] {404// CHECK-NEXT:  entry:405// CHECK-NEXT:    call void @__cxx_global_var_init()406// CHECK-NEXT:    call void @__cxx_global_var_init.2()407// CHECK-NEXT:    ret void408//409//410// CHECK-LABEL: define {{[^@]+}}@_GLOBAL__I_000501411// CHECK-SAME: () #[[ATTR3]] {412// CHECK-NEXT:  entry:413// CHECK-NEXT:    call void @__cxx_global_var_init.3()414// CHECK-NEXT:    ret void415//416//417// CHECK-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_parallel_generic_loop_codegen_1.cpp418// CHECK-SAME: () #[[ATTR3]] {419// CHECK-NEXT:  entry:420// CHECK-NEXT:    call void @__cxx_global_var_init.1()421// CHECK-NEXT:    call void @__cxx_global_var_init.4()422// CHECK-NEXT:    call void @__cxx_global_var_init.7()423// CHECK-NEXT:    call void @__cxx_global_var_init.10()424// CHECK-NEXT:    call void @__cxx_global_var_init.15()425// CHECK-NEXT:    call void @__cxx_global_var_init.20()426// CHECK-NEXT:    ret void427//428//429//430//431//432//433//434//435//436//437//438//439//440//441//442//443//444//445//446//447//448//449//450//451//452//453//454//455//456//457//458//459//460//461//462//463//464//465//466//467//468//469//470//471//472//473//474//475//476//477//478//479//480//481//482//483//484//485//486//487//488//489//490//491//492//493//494//495//496//497//498//499//500//501//502//503//504//505//506//507//508//509//510//511//512//513//514//515//516//517//518//519//520//521//522//523//524//525//526//527//528//529//530//531//532//533//534//535//536//537//538//539//540//541//542//543//544//545//546//547//548//549//550//551//552//553//554//555//556//557//558//559//560//561//562//563//564//565//566//567//568//569//570//571//572//573//574//575//576//577//578//579//580//581//582//583//584//585//586//587//588//589//590//591//592//593//594//595//596//597//598//599//600//601//602//603//604//605//606//607//608//609//610//611//612//613//614//615// SIMD-ONLY0-LABEL: define {{[^@]+}}@__cxx_global_var_init616// SIMD-ONLY0-SAME: () #[[ATTR0:[0-9]+]] {617// SIMD-ONLY0-NEXT:  entry:618// SIMD-ONLY0-NEXT:    call void @_ZN2SAC1Ev(ptr noundef nonnull align 4 dereferenceable(16) @_ZL2a1)619// SIMD-ONLY0-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SAD1Ev, ptr @_ZL2a1, ptr @__dso_handle) #[[ATTR2:[0-9]+]]620// SIMD-ONLY0-NEXT:    ret void621//622//623//624//625// SIMD-ONLY0-LABEL: define {{[^@]+}}@__cxx_global_var_init.1626// SIMD-ONLY0-SAME: () #[[ATTR0]] {627// SIMD-ONLY0-NEXT:  entry:628// SIMD-ONLY0-NEXT:    call void @_ZN2SAC1Ev(ptr noundef nonnull align 4 dereferenceable(16) @a2)629// SIMD-ONLY0-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SAD1Ev, ptr @a2, ptr @__dso_handle) #[[ATTR2]]630// SIMD-ONLY0-NEXT:    ret void631//632//633// SIMD-ONLY0-LABEL: define {{[^@]+}}@__cxx_global_var_init.2634// SIMD-ONLY0-SAME: () #[[ATTR0]] {635// SIMD-ONLY0-NEXT:  entry:636// SIMD-ONLY0-NEXT:    call void @_ZN2SBC1Ev(ptr noundef nonnull align 4 dereferenceable(32) @b1)637// SIMD-ONLY0-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SBD1Ev, ptr @b1, ptr @__dso_handle) #[[ATTR2]]638// SIMD-ONLY0-NEXT:    ret void639//640//641//642//643// SIMD-ONLY0-LABEL: define {{[^@]+}}@__cxx_global_var_init.3644// SIMD-ONLY0-SAME: () #[[ATTR0]] {645// SIMD-ONLY0-NEXT:  entry:646// SIMD-ONLY0-NEXT:    call void @_ZN2SBC1Ev(ptr noundef nonnull align 4 dereferenceable(32) @b2)647// SIMD-ONLY0-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SBD1Ev, ptr @b2, ptr @__dso_handle) #[[ATTR2]]648// SIMD-ONLY0-NEXT:    ret void649//650//651// SIMD-ONLY0-LABEL: define {{[^@]+}}@__cxx_global_var_init.4652// SIMD-ONLY0-SAME: () #[[ATTR0]] {653// SIMD-ONLY0-NEXT:  entry:654// SIMD-ONLY0-NEXT:    call void @_ZN2SCC1Ev(ptr noundef nonnull align 4 dereferenceable(64) @_ZL2c1)655// SIMD-ONLY0-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SCD1Ev, ptr @_ZL2c1, ptr @__dso_handle) #[[ATTR2]]656// SIMD-ONLY0-NEXT:    ret void657//658//659//660//661// SIMD-ONLY0-LABEL: define {{[^@]+}}@__cxx_global_var_init.5662// SIMD-ONLY0-SAME: () #[[ATTR0]] {663// SIMD-ONLY0-NEXT:  entry:664// SIMD-ONLY0-NEXT:    call void @_ZN2SDC1Ev(ptr noundef nonnull align 4 dereferenceable(128) @d1)665// SIMD-ONLY0-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SDD1Ev, ptr @d1, ptr @__dso_handle) #[[ATTR2]]666// SIMD-ONLY0-NEXT:    ret void667//668//669//670//671// SIMD-ONLY0-LABEL: define {{[^@]+}}@__cxx_global_var_init.6672// SIMD-ONLY0-SAME: () #[[ATTR0]] {673// SIMD-ONLY0-NEXT:  entry:674// SIMD-ONLY0-NEXT:    call void @_ZN2SEC1Ev(ptr noundef nonnull align 4 dereferenceable(256) @e1)675// SIMD-ONLY0-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SED1Ev, ptr @e1, ptr @__dso_handle) #[[ATTR2]]676// SIMD-ONLY0-NEXT:    ret void677//678//679//680//681// SIMD-ONLY0-LABEL: define {{[^@]+}}@__cxx_global_var_init.7682// SIMD-ONLY0-SAME: () #[[ATTR0]] {683// SIMD-ONLY0-NEXT:  entry:684// SIMD-ONLY0-NEXT:    call void @_ZN2STILi100EEC1Ev(ptr noundef nonnull align 4 dereferenceable(912) @t1)685// SIMD-ONLY0-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2STILi100EED1Ev, ptr @t1, ptr @__dso_handle) #[[ATTR2]]686// SIMD-ONLY0-NEXT:    ret void687//688//689//690//691// SIMD-ONLY0-LABEL: define {{[^@]+}}@__cxx_global_var_init.8692// SIMD-ONLY0-SAME: () #[[ATTR0]] {693// SIMD-ONLY0-NEXT:  entry:694// SIMD-ONLY0-NEXT:    call void @_ZN2STILi1000EEC1Ev(ptr noundef nonnull align 4 dereferenceable(4512) @t2)695// SIMD-ONLY0-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2STILi1000EED1Ev, ptr @t2, ptr @__dso_handle) #[[ATTR2]]696// SIMD-ONLY0-NEXT:    ret void697//698//699//700//701//702//703//704//705//706//707//708//709//710//711//712//713//714//715//716//717//718//719//720//721//722//723// SIMD-ONLY0-LABEL: define {{[^@]+}}@_GLOBAL__I_000500724// SIMD-ONLY0-SAME: () #[[ATTR0]] {725// SIMD-ONLY0-NEXT:  entry:726// SIMD-ONLY0-NEXT:    call void @__cxx_global_var_init()727// SIMD-ONLY0-NEXT:    call void @__cxx_global_var_init.2()728// SIMD-ONLY0-NEXT:    ret void729//730//731// SIMD-ONLY0-LABEL: define {{[^@]+}}@_GLOBAL__I_000501732// SIMD-ONLY0-SAME: () #[[ATTR0]] {733// SIMD-ONLY0-NEXT:  entry:734// SIMD-ONLY0-NEXT:    call void @__cxx_global_var_init.3()735// SIMD-ONLY0-NEXT:    ret void736//737//738// SIMD-ONLY0-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_parallel_generic_loop_codegen_1.cpp739// SIMD-ONLY0-SAME: () #[[ATTR0]] {740// SIMD-ONLY0-NEXT:  entry:741// SIMD-ONLY0-NEXT:    call void @__cxx_global_var_init.1()742// SIMD-ONLY0-NEXT:    call void @__cxx_global_var_init.4()743// SIMD-ONLY0-NEXT:    call void @__cxx_global_var_init.5()744// SIMD-ONLY0-NEXT:    call void @__cxx_global_var_init.6()745// SIMD-ONLY0-NEXT:    call void @__cxx_global_var_init.7()746// SIMD-ONLY0-NEXT:    call void @__cxx_global_var_init.8()747// SIMD-ONLY0-NEXT:    ret void748//749//750//751//752//753//754//755//756//757//758//759//760//761//762//763//764//765//766//767//768//769//770//771//772//773//774//775//776//777//778//779//780//781//782//783//784//785//786//787//788//789//790//791//792//793//794//795//796//797//798//799//800//801//802//803//804//805//806//807//808//809//810//811//812//813//814//815//816//817//818//819//820//821//822//823//824//825//826//827//828//829//830//831//832//833//834//835//836//837//838//839//840//841//842//843//844//845//846//847//848//849//850//851//852//853//854//855//856//857//858//859//860//861//862//863//864//865//866//867//868//869//870//871//872//873//874//875//876//877//878//879//880//881//882//883//884//885//886//887//888//889//890//891//892//893//894//895//896//897//898//899//900//901//902//903//904//905//906//907//908//909//910//911//912//913//914//915//916//917//918//919//920//921//922//923//924//925//926//927//928//929//930//931//932//933//934//935//936//937//938//939//940//941//942//943//944//945//946//947//948//949//950//951//952//953//954// SIMD-ONLY1-LABEL: define {{[^@]+}}@__cxx_global_var_init955// SIMD-ONLY1-SAME: () #[[ATTR0:[0-9]+]] {956// SIMD-ONLY1-NEXT:  entry:957// SIMD-ONLY1-NEXT:    call void @_ZN2SAC1Ev(ptr noundef nonnull align 4 dereferenceable(16) @_ZL2a1)958// SIMD-ONLY1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SAD1Ev, ptr @_ZL2a1, ptr @__dso_handle) #[[ATTR2:[0-9]+]]959// SIMD-ONLY1-NEXT:    ret void960//961//962//963//964// SIMD-ONLY1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1965// SIMD-ONLY1-SAME: () #[[ATTR0]] {966// SIMD-ONLY1-NEXT:  entry:967// SIMD-ONLY1-NEXT:    call void @_ZN2SAC1Ev(ptr noundef nonnull align 4 dereferenceable(16) @a2)968// SIMD-ONLY1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SAD1Ev, ptr @a2, ptr @__dso_handle) #[[ATTR2]]969// SIMD-ONLY1-NEXT:    ret void970//971//972// SIMD-ONLY1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2973// SIMD-ONLY1-SAME: () #[[ATTR0]] {974// SIMD-ONLY1-NEXT:  entry:975// SIMD-ONLY1-NEXT:    call void @_ZN2SBC1Ev(ptr noundef nonnull align 4 dereferenceable(32) @b1)976// SIMD-ONLY1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SBD1Ev, ptr @b1, ptr @__dso_handle) #[[ATTR2]]977// SIMD-ONLY1-NEXT:    ret void978//979//980//981//982// SIMD-ONLY1-LABEL: define {{[^@]+}}@__cxx_global_var_init.3983// SIMD-ONLY1-SAME: () #[[ATTR0]] {984// SIMD-ONLY1-NEXT:  entry:985// SIMD-ONLY1-NEXT:    call void @_ZN2SBC1Ev(ptr noundef nonnull align 4 dereferenceable(32) @b2)986// SIMD-ONLY1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SBD1Ev, ptr @b2, ptr @__dso_handle) #[[ATTR2]]987// SIMD-ONLY1-NEXT:    ret void988//989//990// SIMD-ONLY1-LABEL: define {{[^@]+}}@__cxx_global_var_init.4991// SIMD-ONLY1-SAME: () #[[ATTR0]] {992// SIMD-ONLY1-NEXT:  entry:993// SIMD-ONLY1-NEXT:    call void @_ZN2SCC1Ev(ptr noundef nonnull align 4 dereferenceable(64) @_ZL2c1)994// SIMD-ONLY1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SCD1Ev, ptr @_ZL2c1, ptr @__dso_handle) #[[ATTR2]]995// SIMD-ONLY1-NEXT:    ret void996//997//998//999//1000// SIMD-ONLY1-LABEL: define {{[^@]+}}@__cxx_global_var_init.51001// SIMD-ONLY1-SAME: () #[[ATTR0]] {1002// SIMD-ONLY1-NEXT:  entry:1003// SIMD-ONLY1-NEXT:    call void @_ZN2SDC1Ev(ptr noundef nonnull align 4 dereferenceable(128) @d1)1004// SIMD-ONLY1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SDD1Ev, ptr @d1, ptr @__dso_handle) #[[ATTR2]]1005// SIMD-ONLY1-NEXT:    ret void1006//1007//1008//1009//1010// SIMD-ONLY1-LABEL: define {{[^@]+}}@__cxx_global_var_init.61011// SIMD-ONLY1-SAME: () #[[ATTR0]] {1012// SIMD-ONLY1-NEXT:  entry:1013// SIMD-ONLY1-NEXT:    call void @_ZN2SEC1Ev(ptr noundef nonnull align 4 dereferenceable(256) @e1)1014// SIMD-ONLY1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SED1Ev, ptr @e1, ptr @__dso_handle) #[[ATTR2]]1015// SIMD-ONLY1-NEXT:    ret void1016//1017//1018//1019//1020// SIMD-ONLY1-LABEL: define {{[^@]+}}@__cxx_global_var_init.71021// SIMD-ONLY1-SAME: () #[[ATTR0]] {1022// SIMD-ONLY1-NEXT:  entry:1023// SIMD-ONLY1-NEXT:    call void @_ZN2STILi100EEC1Ev(ptr noundef nonnull align 4 dereferenceable(912) @t1)1024// SIMD-ONLY1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2STILi100EED1Ev, ptr @t1, ptr @__dso_handle) #[[ATTR2]]1025// SIMD-ONLY1-NEXT:    ret void1026//1027//1028//1029//1030// SIMD-ONLY1-LABEL: define {{[^@]+}}@__cxx_global_var_init.81031// SIMD-ONLY1-SAME: () #[[ATTR0]] {1032// SIMD-ONLY1-NEXT:  entry:1033// SIMD-ONLY1-NEXT:    call void @_ZN2STILi1000EEC1Ev(ptr noundef nonnull align 4 dereferenceable(4512) @t2)1034// SIMD-ONLY1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2STILi1000EED1Ev, ptr @t2, ptr @__dso_handle) #[[ATTR2]]1035// SIMD-ONLY1-NEXT:    ret void1036//1037//1038//1039//1040//1041//1042//1043//1044//1045//1046//1047//1048//1049//1050//1051//1052//1053//1054//1055//1056//1057//1058//1059//1060//1061//1062// SIMD-ONLY1-LABEL: define {{[^@]+}}@_GLOBAL__I_0005001063// SIMD-ONLY1-SAME: () #[[ATTR0]] {1064// SIMD-ONLY1-NEXT:  entry:1065// SIMD-ONLY1-NEXT:    call void @__cxx_global_var_init()1066// SIMD-ONLY1-NEXT:    call void @__cxx_global_var_init.2()1067// SIMD-ONLY1-NEXT:    ret void1068//1069//1070// SIMD-ONLY1-LABEL: define {{[^@]+}}@_GLOBAL__I_0005011071// SIMD-ONLY1-SAME: () #[[ATTR0]] {1072// SIMD-ONLY1-NEXT:  entry:1073// SIMD-ONLY1-NEXT:    call void @__cxx_global_var_init.3()1074// SIMD-ONLY1-NEXT:    ret void1075//1076//1077// SIMD-ONLY1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_parallel_generic_loop_codegen_1.cpp1078// SIMD-ONLY1-SAME: () #[[ATTR0]] {1079// SIMD-ONLY1-NEXT:  entry:1080// SIMD-ONLY1-NEXT:    call void @__cxx_global_var_init.1()1081// SIMD-ONLY1-NEXT:    call void @__cxx_global_var_init.4()1082// SIMD-ONLY1-NEXT:    call void @__cxx_global_var_init.5()1083// SIMD-ONLY1-NEXT:    call void @__cxx_global_var_init.6()1084// SIMD-ONLY1-NEXT:    call void @__cxx_global_var_init.7()1085// SIMD-ONLY1-NEXT:    call void @__cxx_global_var_init.8()1086// SIMD-ONLY1-NEXT:    ret void1087//1088//1089//1090//1091//1092//1093//1094//1095//1096//1097//1098//1099//1100//1101//1102//1103//1104//1105//1106//1107//1108//1109//1110//1111//1112//1113//1114//1115//1116//1117//1118//1119//1120//1121//1122//1123//1124//1125//1126//1127//1128//1129//1130//1131//1132//1133//1134//1135//1136//1137//1138//1139//1140//1141//1142//1143//1144//1145//1146//1147//1148//1149//1150//1151//1152//1153//1154//1155//1156//1157//1158//1159//1160//1161//1162//1163//1164//1165//1166//1167//1168//1169//1170//1171//1172//1173//1174//1175//1176//1177//1178//1179//1180//1181//1182//1183//1184//1185//1186//1187//1188//1189//1190//1191//1192//1193//1194//1195//1196//1197// CHECK-NTARGET-LABEL: define {{[^@]+}}@_Z3bari1198// CHECK-NTARGET-SAME: (i32 noundef signext [[A:%.*]]) #[[ATTR0:[0-9]+]] {1199// CHECK-NTARGET-NEXT:  entry:1200// CHECK-NTARGET-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 41201// CHECK-NTARGET-NEXT:    [[R:%.*]] = alloca i32, align 41202// CHECK-NTARGET-NEXT:    [[R_CASTED:%.*]] = alloca i64, align 81203// CHECK-NTARGET-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 41204// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41205// CHECK-NTARGET-NEXT:    store i32 [[TMP0]], ptr [[R]], align 41206// CHECK-NTARGET-NEXT:    call void @_ZN2SA3fooEv(ptr noundef nonnull align 4 dereferenceable(16) @_ZL2a1)1207// CHECK-NTARGET-NEXT:    call void @_ZN2SA3fooEv(ptr noundef nonnull align 4 dereferenceable(16) @a2)1208// CHECK-NTARGET-NEXT:    call void @_ZN2SB3fooEv(ptr noundef nonnull align 4 dereferenceable(32) @b1)1209// CHECK-NTARGET-NEXT:    call void @_ZN2SB3fooEv(ptr noundef nonnull align 4 dereferenceable(32) @b2)1210// CHECK-NTARGET-NEXT:    call void @_ZN2SC3fooEv(ptr noundef nonnull align 4 dereferenceable(64) @_ZL2c1)1211// CHECK-NTARGET-NEXT:    call void @_ZN2SD3fooEv(ptr noundef nonnull align 4 dereferenceable(128) @d1)1212// CHECK-NTARGET-NEXT:    call void @_ZN2SE3fooEv(ptr noundef nonnull align 4 dereferenceable(256) @e1)1213// CHECK-NTARGET-NEXT:    call void @_ZN2STILi100EE3fooEv(ptr noundef nonnull align 4 dereferenceable(912) @t1)1214// CHECK-NTARGET-NEXT:    call void @_ZN2STILi1000EE3fooEv(ptr noundef nonnull align 4 dereferenceable(4512) @t2)1215// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i32, ptr [[R]], align 41216// CHECK-NTARGET-NEXT:    store i32 [[TMP1]], ptr [[R_CASTED]], align 41217// CHECK-NTARGET-NEXT:    [[TMP2:%.*]] = load i64, ptr [[R_CASTED]], align 81218// CHECK-NTARGET-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3bari_l267(i64 [[TMP2]]) #[[ATTR2:[0-9]+]]1219// CHECK-NTARGET-NEXT:    [[TMP3:%.*]] = load i32, ptr [[R]], align 41220// CHECK-NTARGET-NEXT:    [[TMP4:%.*]] = load ptr, ptr @R, align 81221// CHECK-NTARGET-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 41222// CHECK-NTARGET-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP5]]1223// CHECK-NTARGET-NEXT:    ret i32 [[ADD]]1224//1225//1226// CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2SA3fooEv1227// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(16) [[THIS:%.*]]) #[[ATTR0]] comdat {1228// CHECK-NTARGET-NEXT:  entry:1229// CHECK-NTARGET-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81230// CHECK-NTARGET-NEXT:    [[A:%.*]] = alloca i32, align 41231// CHECK-NTARGET-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81232// CHECK-NTARGET-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81233// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 81234// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 41235// CHECK-NTARGET-NEXT:    store i32 [[TMP1]], ptr [[A]], align 41236// CHECK-NTARGET-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 41237// CHECK-NTARGET-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP2]], 11238// CHECK-NTARGET-NEXT:    store i32 [[ADD]], ptr [[A]], align 41239// CHECK-NTARGET-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 41240// CHECK-NTARGET-NEXT:    [[TMP4:%.*]] = load ptr, ptr @R, align 81241// CHECK-NTARGET-NEXT:    store i32 [[TMP3]], ptr [[TMP4]], align 41242// CHECK-NTARGET-NEXT:    ret void1243//1244//1245// CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2SB3fooEv1246// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(32) [[THIS:%.*]]) #[[ATTR0]] comdat {1247// CHECK-NTARGET-NEXT:  entry:1248// CHECK-NTARGET-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81249// CHECK-NTARGET-NEXT:    [[A:%.*]] = alloca i32, align 41250// CHECK-NTARGET-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 81251// CHECK-NTARGET-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81252// CHECK-NTARGET-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81253// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 81254// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 41255// CHECK-NTARGET-NEXT:    store i32 [[TMP1]], ptr [[A]], align 41256// CHECK-NTARGET-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 41257// CHECK-NTARGET-NEXT:    store i32 [[TMP2]], ptr [[A_CASTED]], align 41258// CHECK-NTARGET-NEXT:    [[TMP3:%.*]] = load i64, ptr [[A_CASTED]], align 81259// CHECK-NTARGET-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SB3fooEv_l122(i64 [[TMP3]]) #[[ATTR2]]1260// CHECK-NTARGET-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A]], align 41261// CHECK-NTARGET-NEXT:    [[TMP5:%.*]] = load ptr, ptr @R, align 81262// CHECK-NTARGET-NEXT:    store i32 [[TMP4]], ptr [[TMP5]], align 41263// CHECK-NTARGET-NEXT:    ret void1264//1265//1266// CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2SC3fooEv1267// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(64) [[THIS:%.*]]) #[[ATTR0]] comdat {1268// CHECK-NTARGET-NEXT:  entry:1269// CHECK-NTARGET-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81270// CHECK-NTARGET-NEXT:    [[A:%.*]] = alloca i32, align 41271// CHECK-NTARGET-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81272// CHECK-NTARGET-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81273// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 81274// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 41275// CHECK-NTARGET-NEXT:    store i32 [[TMP1]], ptr [[A]], align 41276// CHECK-NTARGET-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 41277// CHECK-NTARGET-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP2]], 71278// CHECK-NTARGET-NEXT:    store i32 [[ADD]], ptr [[A]], align 41279// CHECK-NTARGET-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 41280// CHECK-NTARGET-NEXT:    [[TMP4:%.*]] = load ptr, ptr @R, align 81281// CHECK-NTARGET-NEXT:    store i32 [[TMP3]], ptr [[TMP4]], align 41282// CHECK-NTARGET-NEXT:    ret void1283//1284//1285// CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2SD3fooEv1286// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(128) [[THIS:%.*]]) #[[ATTR0]] comdat {1287// CHECK-NTARGET-NEXT:  entry:1288// CHECK-NTARGET-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81289// CHECK-NTARGET-NEXT:    [[A:%.*]] = alloca i32, align 41290// CHECK-NTARGET-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81291// CHECK-NTARGET-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81292// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 81293// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 41294// CHECK-NTARGET-NEXT:    store i32 [[TMP1]], ptr [[A]], align 41295// CHECK-NTARGET-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 41296// CHECK-NTARGET-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP2]], 101297// CHECK-NTARGET-NEXT:    store i32 [[ADD]], ptr [[A]], align 41298// CHECK-NTARGET-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 41299// CHECK-NTARGET-NEXT:    [[TMP4:%.*]] = load ptr, ptr @R, align 81300// CHECK-NTARGET-NEXT:    store i32 [[TMP3]], ptr [[TMP4]], align 41301// CHECK-NTARGET-NEXT:    ret void1302//1303//1304// CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2SE3fooEv1305// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(256) [[THIS:%.*]]) #[[ATTR0]] comdat {1306// CHECK-NTARGET-NEXT:  entry:1307// CHECK-NTARGET-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81308// CHECK-NTARGET-NEXT:    [[A:%.*]] = alloca i32, align 41309// CHECK-NTARGET-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 81310// CHECK-NTARGET-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81311// CHECK-NTARGET-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81312// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 81313// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 41314// CHECK-NTARGET-NEXT:    store i32 [[TMP1]], ptr [[A]], align 41315// CHECK-NTARGET-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 41316// CHECK-NTARGET-NEXT:    store i32 [[TMP2]], ptr [[A_CASTED]], align 41317// CHECK-NTARGET-NEXT:    [[TMP3:%.*]] = load i64, ptr [[A_CASTED]], align 81318// CHECK-NTARGET-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SE3fooEv_l185(i64 [[TMP3]]) #[[ATTR2]]1319// CHECK-NTARGET-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A]], align 41320// CHECK-NTARGET-NEXT:    [[TMP5:%.*]] = load ptr, ptr @R, align 81321// CHECK-NTARGET-NEXT:    store i32 [[TMP4]], ptr [[TMP5]], align 41322// CHECK-NTARGET-NEXT:    ret void1323//1324//1325// CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2STILi100EE3fooEv1326// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(912) [[THIS:%.*]]) #[[ATTR0]] comdat {1327// CHECK-NTARGET-NEXT:  entry:1328// CHECK-NTARGET-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81329// CHECK-NTARGET-NEXT:    [[A:%.*]] = alloca i32, align 41330// CHECK-NTARGET-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 81331// CHECK-NTARGET-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81332// CHECK-NTARGET-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81333// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 81334// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 41335// CHECK-NTARGET-NEXT:    store i32 [[TMP1]], ptr [[A]], align 41336// CHECK-NTARGET-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 41337// CHECK-NTARGET-NEXT:    store i32 [[TMP2]], ptr [[A_CASTED]], align 41338// CHECK-NTARGET-NEXT:    [[TMP3:%.*]] = load i64, ptr [[A_CASTED]], align 81339// CHECK-NTARGET-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi100EE3fooEv_l211(i64 [[TMP3]]) #[[ATTR2]]1340// CHECK-NTARGET-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A]], align 41341// CHECK-NTARGET-NEXT:    [[TMP5:%.*]] = load ptr, ptr @R, align 81342// CHECK-NTARGET-NEXT:    store i32 [[TMP4]], ptr [[TMP5]], align 41343// CHECK-NTARGET-NEXT:    ret void1344//1345//1346// CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2STILi1000EE3fooEv1347// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(4512) [[THIS:%.*]]) #[[ATTR0]] comdat {1348// CHECK-NTARGET-NEXT:  entry:1349// CHECK-NTARGET-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81350// CHECK-NTARGET-NEXT:    [[A:%.*]] = alloca i32, align 41351// CHECK-NTARGET-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 81352// CHECK-NTARGET-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81353// CHECK-NTARGET-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81354// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 81355// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 41356// CHECK-NTARGET-NEXT:    store i32 [[TMP1]], ptr [[A]], align 41357// CHECK-NTARGET-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 41358// CHECK-NTARGET-NEXT:    store i32 [[TMP2]], ptr [[A_CASTED]], align 41359// CHECK-NTARGET-NEXT:    [[TMP3:%.*]] = load i64, ptr [[A_CASTED]], align 81360// CHECK-NTARGET-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi1000EE3fooEv_l211(i64 [[TMP3]]) #[[ATTR2]]1361// CHECK-NTARGET-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A]], align 41362// CHECK-NTARGET-NEXT:    [[TMP5:%.*]] = load ptr, ptr @R, align 81363// CHECK-NTARGET-NEXT:    store i32 [[TMP4]], ptr [[TMP5]], align 41364// CHECK-NTARGET-NEXT:    ret void1365//1366//1367// CHECK-NTARGET-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3bari_l2671368// CHECK-NTARGET-SAME: (i64 noundef [[R:%.*]]) #[[ATTR1:[0-9]+]] {1369// CHECK-NTARGET-NEXT:  entry:1370// CHECK-NTARGET-NEXT:    [[R_ADDR:%.*]] = alloca i64, align 81371// CHECK-NTARGET-NEXT:    [[R_CASTED:%.*]] = alloca i64, align 81372// CHECK-NTARGET-NEXT:    store i64 [[R]], ptr [[R_ADDR]], align 81373// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load i32, ptr [[R_ADDR]], align 41374// CHECK-NTARGET-NEXT:    store i32 [[TMP0]], ptr [[R_CASTED]], align 41375// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i64, ptr [[R_CASTED]], align 81376// CHECK-NTARGET-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3bari_l267.omp_outlined, i64 [[TMP1]])1377// CHECK-NTARGET-NEXT:    ret void1378//1379//1380// CHECK-NTARGET-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3bari_l267.omp_outlined1381// CHECK-NTARGET-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[R:%.*]]) #[[ATTR1]] {1382// CHECK-NTARGET-NEXT:  entry:1383// CHECK-NTARGET-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81384// CHECK-NTARGET-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81385// CHECK-NTARGET-NEXT:    [[R_ADDR:%.*]] = alloca i64, align 81386// CHECK-NTARGET-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 41387// CHECK-NTARGET-NEXT:    [[TMP:%.*]] = alloca i32, align 41388// CHECK-NTARGET-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 41389// CHECK-NTARGET-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 41390// CHECK-NTARGET-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41391// CHECK-NTARGET-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41392// CHECK-NTARGET-NEXT:    [[I:%.*]] = alloca i32, align 41393// CHECK-NTARGET-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81394// CHECK-NTARGET-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81395// CHECK-NTARGET-NEXT:    store i64 [[R]], ptr [[R_ADDR]], align 81396// CHECK-NTARGET-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 41397// CHECK-NTARGET-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 41398// CHECK-NTARGET-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 41399// CHECK-NTARGET-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 41400// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81401// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 41402// CHECK-NTARGET-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1403// CHECK-NTARGET-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41404// CHECK-NTARGET-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 91405// CHECK-NTARGET-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1406// CHECK-NTARGET:       cond.true:1407// CHECK-NTARGET-NEXT:    br label [[COND_END:%.*]]1408// CHECK-NTARGET:       cond.false:1409// CHECK-NTARGET-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41410// CHECK-NTARGET-NEXT:    br label [[COND_END]]1411// CHECK-NTARGET:       cond.end:1412// CHECK-NTARGET-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]1413// CHECK-NTARGET-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 41414// CHECK-NTARGET-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41415// CHECK-NTARGET-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 41416// CHECK-NTARGET-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]1417// CHECK-NTARGET:       omp.inner.for.cond:1418// CHECK-NTARGET-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41419// CHECK-NTARGET-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41420// CHECK-NTARGET-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]1421// CHECK-NTARGET-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1422// CHECK-NTARGET:       omp.inner.for.body:1423// CHECK-NTARGET-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41424// CHECK-NTARGET-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 11425// CHECK-NTARGET-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]1426// CHECK-NTARGET-NEXT:    store i32 [[ADD]], ptr [[I]], align 41427// CHECK-NTARGET-NEXT:    [[TMP8:%.*]] = load i32, ptr [[R_ADDR]], align 41428// CHECK-NTARGET-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP8]], 11429// CHECK-NTARGET-NEXT:    store i32 [[INC]], ptr [[R_ADDR]], align 41430// CHECK-NTARGET-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]1431// CHECK-NTARGET:       omp.body.continue:1432// CHECK-NTARGET-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]1433// CHECK-NTARGET:       omp.inner.for.inc:1434// CHECK-NTARGET-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41435// CHECK-NTARGET-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 11436// CHECK-NTARGET-NEXT:    store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 41437// CHECK-NTARGET-NEXT:    br label [[OMP_INNER_FOR_COND]]1438// CHECK-NTARGET:       omp.inner.for.end:1439// CHECK-NTARGET-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]1440// CHECK-NTARGET:       omp.loop.exit:1441// CHECK-NTARGET-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])1442// CHECK-NTARGET-NEXT:    ret void1443//1444//1445// CHECK-NTARGET-LABEL: define {{[^@]+}}@__cxx_global_var_init1446// CHECK-NTARGET-SAME: () #[[ATTR3:[0-9]+]] {1447// CHECK-NTARGET-NEXT:  entry:1448// CHECK-NTARGET-NEXT:    call void @_ZN2SAC1Ev(ptr noundef nonnull align 4 dereferenceable(16) @_ZL2a1)1449// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SAD1Ev, ptr @_ZL2a1, ptr @__dso_handle) #[[ATTR2]]1450// CHECK-NTARGET-NEXT:    ret void1451//1452//1453// CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2SAC1Ev1454// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat {1455// CHECK-NTARGET-NEXT:  entry:1456// CHECK-NTARGET-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81457// CHECK-NTARGET-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81458// CHECK-NTARGET-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81459// CHECK-NTARGET-NEXT:    call void @_ZN2SAC2Ev(ptr noundef nonnull align 4 dereferenceable(16) [[THIS1]])1460// CHECK-NTARGET-NEXT:    ret void1461//1462//1463// CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2SAD1Ev1464// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat {1465// CHECK-NTARGET-NEXT:  entry:1466// CHECK-NTARGET-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81467// CHECK-NTARGET-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81468// CHECK-NTARGET-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81469// CHECK-NTARGET-NEXT:    call void @_ZN2SAD2Ev(ptr noundef nonnull align 4 dereferenceable(16) [[THIS1]]) #[[ATTR2]]1470// CHECK-NTARGET-NEXT:    ret void1471//1472//1473// CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2SAC2Ev1474// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat {1475// CHECK-NTARGET-NEXT:  entry:1476// CHECK-NTARGET-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81477// CHECK-NTARGET-NEXT:    [[A:%.*]] = alloca i32, align 41478// CHECK-NTARGET-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81479// CHECK-NTARGET-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81480// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 81481// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 41482// CHECK-NTARGET-NEXT:    store i32 [[TMP1]], ptr [[A]], align 41483// CHECK-NTARGET-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 41484// CHECK-NTARGET-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP2]], 21485// CHECK-NTARGET-NEXT:    store i32 [[ADD]], ptr [[A]], align 41486// CHECK-NTARGET-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 41487// CHECK-NTARGET-NEXT:    [[TMP4:%.*]] = load ptr, ptr @R, align 81488// CHECK-NTARGET-NEXT:    store i32 [[TMP3]], ptr [[TMP4]], align 41489// CHECK-NTARGET-NEXT:    ret void1490//1491//1492// CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2SAD2Ev1493// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat {1494// CHECK-NTARGET-NEXT:  entry:1495// CHECK-NTARGET-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81496// CHECK-NTARGET-NEXT:    [[A:%.*]] = alloca i32, align 41497// CHECK-NTARGET-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81498// CHECK-NTARGET-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81499// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 81500// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 41501// CHECK-NTARGET-NEXT:    store i32 [[TMP1]], ptr [[A]], align 41502// CHECK-NTARGET-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 41503// CHECK-NTARGET-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP2]], 31504// CHECK-NTARGET-NEXT:    store i32 [[ADD]], ptr [[A]], align 41505// CHECK-NTARGET-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 41506// CHECK-NTARGET-NEXT:    [[TMP4:%.*]] = load ptr, ptr @R, align 81507// CHECK-NTARGET-NEXT:    store i32 [[TMP3]], ptr [[TMP4]], align 41508// CHECK-NTARGET-NEXT:    ret void1509//1510//1511// CHECK-NTARGET-LABEL: define {{[^@]+}}@__cxx_global_var_init.11512// CHECK-NTARGET-SAME: () #[[ATTR3]] {1513// CHECK-NTARGET-NEXT:  entry:1514// CHECK-NTARGET-NEXT:    call void @_ZN2SAC1Ev(ptr noundef nonnull align 4 dereferenceable(16) @a2)1515// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SAD1Ev, ptr @a2, ptr @__dso_handle) #[[ATTR2]]1516// CHECK-NTARGET-NEXT:    ret void1517//1518//1519// CHECK-NTARGET-LABEL: define {{[^@]+}}@__cxx_global_var_init.21520// CHECK-NTARGET-SAME: () #[[ATTR3]] {1521// CHECK-NTARGET-NEXT:  entry:1522// CHECK-NTARGET-NEXT:    call void @_ZN2SBC1Ev(ptr noundef nonnull align 4 dereferenceable(32) @b1)1523// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SBD1Ev, ptr @b1, ptr @__dso_handle) #[[ATTR2]]1524// CHECK-NTARGET-NEXT:    ret void1525//1526//1527// CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2SBC1Ev1528// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(32) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat {1529// CHECK-NTARGET-NEXT:  entry:1530// CHECK-NTARGET-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81531// CHECK-NTARGET-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81532// CHECK-NTARGET-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81533// CHECK-NTARGET-NEXT:    call void @_ZN2SBC2Ev(ptr noundef nonnull align 4 dereferenceable(32) [[THIS1]])1534// CHECK-NTARGET-NEXT:    ret void1535//1536//1537// CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2SBD1Ev1538// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(32) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat {1539// CHECK-NTARGET-NEXT:  entry:1540// CHECK-NTARGET-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81541// CHECK-NTARGET-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81542// CHECK-NTARGET-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81543// CHECK-NTARGET-NEXT:    call void @_ZN2SBD2Ev(ptr noundef nonnull align 4 dereferenceable(32) [[THIS1]]) #[[ATTR2]]1544// CHECK-NTARGET-NEXT:    ret void1545//1546//1547// CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2SBC2Ev1548// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(32) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat {1549// CHECK-NTARGET-NEXT:  entry:1550// CHECK-NTARGET-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81551// CHECK-NTARGET-NEXT:    [[A:%.*]] = alloca i32, align 41552// CHECK-NTARGET-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81553// CHECK-NTARGET-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81554// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 81555// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 41556// CHECK-NTARGET-NEXT:    store i32 [[TMP1]], ptr [[A]], align 41557// CHECK-NTARGET-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 41558// CHECK-NTARGET-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP2]], 51559// CHECK-NTARGET-NEXT:    store i32 [[ADD]], ptr [[A]], align 41560// CHECK-NTARGET-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 41561// CHECK-NTARGET-NEXT:    [[TMP4:%.*]] = load ptr, ptr @R, align 81562// CHECK-NTARGET-NEXT:    store i32 [[TMP3]], ptr [[TMP4]], align 41563// CHECK-NTARGET-NEXT:    ret void1564//1565//1566// CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2SBD2Ev1567// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(32) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat {1568// CHECK-NTARGET-NEXT:  entry:1569// CHECK-NTARGET-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81570// CHECK-NTARGET-NEXT:    [[A:%.*]] = alloca i32, align 41571// CHECK-NTARGET-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81572// CHECK-NTARGET-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81573// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 81574// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 41575// CHECK-NTARGET-NEXT:    store i32 [[TMP1]], ptr [[A]], align 41576// CHECK-NTARGET-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 41577// CHECK-NTARGET-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP2]], 61578// CHECK-NTARGET-NEXT:    store i32 [[ADD]], ptr [[A]], align 41579// CHECK-NTARGET-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 41580// CHECK-NTARGET-NEXT:    [[TMP4:%.*]] = load ptr, ptr @R, align 81581// CHECK-NTARGET-NEXT:    store i32 [[TMP3]], ptr [[TMP4]], align 41582// CHECK-NTARGET-NEXT:    ret void1583//1584//1585// CHECK-NTARGET-LABEL: define {{[^@]+}}@__cxx_global_var_init.31586// CHECK-NTARGET-SAME: () #[[ATTR3]] {1587// CHECK-NTARGET-NEXT:  entry:1588// CHECK-NTARGET-NEXT:    call void @_ZN2SBC1Ev(ptr noundef nonnull align 4 dereferenceable(32) @b2)1589// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SBD1Ev, ptr @b2, ptr @__dso_handle) #[[ATTR2]]1590// CHECK-NTARGET-NEXT:    ret void1591//1592//1593// CHECK-NTARGET-LABEL: define {{[^@]+}}@__cxx_global_var_init.41594// CHECK-NTARGET-SAME: () #[[ATTR3]] {1595// CHECK-NTARGET-NEXT:  entry:1596// CHECK-NTARGET-NEXT:    call void @_ZN2SCC1Ev(ptr noundef nonnull align 4 dereferenceable(64) @_ZL2c1)1597// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SCD1Ev, ptr @_ZL2c1, ptr @__dso_handle) #[[ATTR2]]1598// CHECK-NTARGET-NEXT:    ret void1599//1600//1601// CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2SCC1Ev1602// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(64) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat {1603// CHECK-NTARGET-NEXT:  entry:1604// CHECK-NTARGET-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81605// CHECK-NTARGET-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81606// CHECK-NTARGET-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81607// CHECK-NTARGET-NEXT:    call void @_ZN2SCC2Ev(ptr noundef nonnull align 4 dereferenceable(64) [[THIS1]])1608// CHECK-NTARGET-NEXT:    ret void1609//1610//1611// CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2SCD1Ev1612// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(64) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat {1613// CHECK-NTARGET-NEXT:  entry:1614// CHECK-NTARGET-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81615// CHECK-NTARGET-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81616// CHECK-NTARGET-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81617// CHECK-NTARGET-NEXT:    call void @_ZN2SCD2Ev(ptr noundef nonnull align 4 dereferenceable(64) [[THIS1]]) #[[ATTR2]]1618// CHECK-NTARGET-NEXT:    ret void1619//1620//1621// CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2SCC2Ev1622// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(64) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat {1623// CHECK-NTARGET-NEXT:  entry:1624// CHECK-NTARGET-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81625// CHECK-NTARGET-NEXT:    [[A:%.*]] = alloca i32, align 41626// CHECK-NTARGET-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 81627// CHECK-NTARGET-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81628// CHECK-NTARGET-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81629// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 81630// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 41631// CHECK-NTARGET-NEXT:    store i32 [[TMP1]], ptr [[A]], align 41632// CHECK-NTARGET-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 41633// CHECK-NTARGET-NEXT:    store i32 [[TMP2]], ptr [[A_CASTED]], align 41634// CHECK-NTARGET-NEXT:    [[TMP3:%.*]] = load i64, ptr [[A_CASTED]], align 81635// CHECK-NTARGET-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SCC1Ev_l148(i64 [[TMP3]]) #[[ATTR2]]1636// CHECK-NTARGET-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A]], align 41637// CHECK-NTARGET-NEXT:    [[TMP5:%.*]] = load ptr, ptr @R, align 81638// CHECK-NTARGET-NEXT:    store i32 [[TMP4]], ptr [[TMP5]], align 41639// CHECK-NTARGET-NEXT:    ret void1640//1641//1642// CHECK-NTARGET-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SCC1Ev_l1481643// CHECK-NTARGET-SAME: (i64 noundef [[A:%.*]]) #[[ATTR1]] {1644// CHECK-NTARGET-NEXT:  entry:1645// CHECK-NTARGET-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 81646// CHECK-NTARGET-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 81647// CHECK-NTARGET-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 81648// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41649// CHECK-NTARGET-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 41650// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 81651// CHECK-NTARGET-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SCC1Ev_l148.omp_outlined, i64 [[TMP1]])1652// CHECK-NTARGET-NEXT:    ret void1653//1654//1655// CHECK-NTARGET-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SCC1Ev_l148.omp_outlined1656// CHECK-NTARGET-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] {1657// CHECK-NTARGET-NEXT:  entry:1658// CHECK-NTARGET-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81659// CHECK-NTARGET-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81660// CHECK-NTARGET-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 81661// CHECK-NTARGET-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 41662// CHECK-NTARGET-NEXT:    [[TMP:%.*]] = alloca i32, align 41663// CHECK-NTARGET-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 41664// CHECK-NTARGET-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 41665// CHECK-NTARGET-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41666// CHECK-NTARGET-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41667// CHECK-NTARGET-NEXT:    [[I:%.*]] = alloca i32, align 41668// CHECK-NTARGET-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81669// CHECK-NTARGET-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81670// CHECK-NTARGET-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 81671// CHECK-NTARGET-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 41672// CHECK-NTARGET-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 41673// CHECK-NTARGET-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 41674// CHECK-NTARGET-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 41675// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81676// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 41677// CHECK-NTARGET-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1678// CHECK-NTARGET-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41679// CHECK-NTARGET-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 91680// CHECK-NTARGET-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1681// CHECK-NTARGET:       cond.true:1682// CHECK-NTARGET-NEXT:    br label [[COND_END:%.*]]1683// CHECK-NTARGET:       cond.false:1684// CHECK-NTARGET-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41685// CHECK-NTARGET-NEXT:    br label [[COND_END]]1686// CHECK-NTARGET:       cond.end:1687// CHECK-NTARGET-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]1688// CHECK-NTARGET-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 41689// CHECK-NTARGET-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41690// CHECK-NTARGET-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 41691// CHECK-NTARGET-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]1692// CHECK-NTARGET:       omp.inner.for.cond:1693// CHECK-NTARGET-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41694// CHECK-NTARGET-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41695// CHECK-NTARGET-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]1696// CHECK-NTARGET-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1697// CHECK-NTARGET:       omp.inner.for.body:1698// CHECK-NTARGET-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41699// CHECK-NTARGET-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 11700// CHECK-NTARGET-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]1701// CHECK-NTARGET-NEXT:    store i32 [[ADD]], ptr [[I]], align 41702// CHECK-NTARGET-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 41703// CHECK-NTARGET-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 81704// CHECK-NTARGET-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 41705// CHECK-NTARGET-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]1706// CHECK-NTARGET:       omp.body.continue:1707// CHECK-NTARGET-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]1708// CHECK-NTARGET:       omp.inner.for.inc:1709// CHECK-NTARGET-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41710// CHECK-NTARGET-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 11711// CHECK-NTARGET-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 41712// CHECK-NTARGET-NEXT:    br label [[OMP_INNER_FOR_COND]]1713// CHECK-NTARGET:       omp.inner.for.end:1714// CHECK-NTARGET-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]1715// CHECK-NTARGET:       omp.loop.exit:1716// CHECK-NTARGET-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])1717// CHECK-NTARGET-NEXT:    ret void1718//1719//1720// CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2SCD2Ev1721// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(64) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat {1722// CHECK-NTARGET-NEXT:  entry:1723// CHECK-NTARGET-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81724// CHECK-NTARGET-NEXT:    [[A:%.*]] = alloca i32, align 41725// CHECK-NTARGET-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81726// CHECK-NTARGET-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81727// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 81728// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 41729// CHECK-NTARGET-NEXT:    store i32 [[TMP1]], ptr [[A]], align 41730// CHECK-NTARGET-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 41731// CHECK-NTARGET-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP2]], 91732// CHECK-NTARGET-NEXT:    store i32 [[ADD]], ptr [[A]], align 41733// CHECK-NTARGET-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 41734// CHECK-NTARGET-NEXT:    [[TMP4:%.*]] = load ptr, ptr @R, align 81735// CHECK-NTARGET-NEXT:    store i32 [[TMP3]], ptr [[TMP4]], align 41736// CHECK-NTARGET-NEXT:    ret void1737//1738//1739// CHECK-NTARGET-LABEL: define {{[^@]+}}@__cxx_global_var_init.51740// CHECK-NTARGET-SAME: () #[[ATTR3]] {1741// CHECK-NTARGET-NEXT:  entry:1742// CHECK-NTARGET-NEXT:    call void @_ZN2SDC1Ev(ptr noundef nonnull align 4 dereferenceable(128) @d1)1743// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SDD1Ev, ptr @d1, ptr @__dso_handle) #[[ATTR2]]1744// CHECK-NTARGET-NEXT:    ret void1745//1746//1747// CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2SDC1Ev1748// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(128) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat {1749// CHECK-NTARGET-NEXT:  entry:1750// CHECK-NTARGET-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81751// CHECK-NTARGET-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81752// CHECK-NTARGET-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81753// CHECK-NTARGET-NEXT:    call void @_ZN2SDC2Ev(ptr noundef nonnull align 4 dereferenceable(128) [[THIS1]])1754// CHECK-NTARGET-NEXT:    ret void1755//1756//1757// CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2SDD1Ev1758// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(128) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat {1759// CHECK-NTARGET-NEXT:  entry:1760// CHECK-NTARGET-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81761// CHECK-NTARGET-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81762// CHECK-NTARGET-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81763// CHECK-NTARGET-NEXT:    call void @_ZN2SDD2Ev(ptr noundef nonnull align 4 dereferenceable(128) [[THIS1]]) #[[ATTR2]]1764// CHECK-NTARGET-NEXT:    ret void1765//1766//1767// CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2SDC2Ev1768// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(128) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat {1769// CHECK-NTARGET-NEXT:  entry:1770// CHECK-NTARGET-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81771// CHECK-NTARGET-NEXT:    [[A:%.*]] = alloca i32, align 41772// CHECK-NTARGET-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81773// CHECK-NTARGET-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81774// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 81775// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 41776// CHECK-NTARGET-NEXT:    store i32 [[TMP1]], ptr [[A]], align 41777// CHECK-NTARGET-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 41778// CHECK-NTARGET-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP2]], 111779// CHECK-NTARGET-NEXT:    store i32 [[ADD]], ptr [[A]], align 41780// CHECK-NTARGET-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 41781// CHECK-NTARGET-NEXT:    [[TMP4:%.*]] = load ptr, ptr @R, align 81782// CHECK-NTARGET-NEXT:    store i32 [[TMP3]], ptr [[TMP4]], align 41783// CHECK-NTARGET-NEXT:    ret void1784//1785//1786// CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2SDD2Ev1787// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(128) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat {1788// CHECK-NTARGET-NEXT:  entry:1789// CHECK-NTARGET-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81790// CHECK-NTARGET-NEXT:    [[A:%.*]] = alloca i32, align 41791// CHECK-NTARGET-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 81792// CHECK-NTARGET-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81793// CHECK-NTARGET-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81794// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 81795// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 41796// CHECK-NTARGET-NEXT:    store i32 [[TMP1]], ptr [[A]], align 41797// CHECK-NTARGET-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 41798// CHECK-NTARGET-NEXT:    store i32 [[TMP2]], ptr [[A_CASTED]], align 41799// CHECK-NTARGET-NEXT:    [[TMP3:%.*]] = load i64, ptr [[A_CASTED]], align 81800// CHECK-NTARGET-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SDD1Ev_l174(i64 [[TMP3]]) #[[ATTR2]]1801// CHECK-NTARGET-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A]], align 41802// CHECK-NTARGET-NEXT:    [[TMP5:%.*]] = load ptr, ptr @R, align 81803// CHECK-NTARGET-NEXT:    store i32 [[TMP4]], ptr [[TMP5]], align 41804// CHECK-NTARGET-NEXT:    ret void1805//1806//1807// CHECK-NTARGET-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SDD1Ev_l1741808// CHECK-NTARGET-SAME: (i64 noundef [[A:%.*]]) #[[ATTR1]] {1809// CHECK-NTARGET-NEXT:  entry:1810// CHECK-NTARGET-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 81811// CHECK-NTARGET-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 81812// CHECK-NTARGET-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 81813// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41814// CHECK-NTARGET-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 41815// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 81816// CHECK-NTARGET-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SDD1Ev_l174.omp_outlined, i64 [[TMP1]])1817// CHECK-NTARGET-NEXT:    ret void1818//1819//1820// CHECK-NTARGET-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SDD1Ev_l174.omp_outlined1821// CHECK-NTARGET-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] {1822// CHECK-NTARGET-NEXT:  entry:1823// CHECK-NTARGET-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81824// CHECK-NTARGET-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81825// CHECK-NTARGET-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 81826// CHECK-NTARGET-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 41827// CHECK-NTARGET-NEXT:    [[TMP:%.*]] = alloca i32, align 41828// CHECK-NTARGET-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 41829// CHECK-NTARGET-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 41830// CHECK-NTARGET-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41831// CHECK-NTARGET-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41832// CHECK-NTARGET-NEXT:    [[I:%.*]] = alloca i32, align 41833// CHECK-NTARGET-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81834// CHECK-NTARGET-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81835// CHECK-NTARGET-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 81836// CHECK-NTARGET-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 41837// CHECK-NTARGET-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 41838// CHECK-NTARGET-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 41839// CHECK-NTARGET-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 41840// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81841// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 41842// CHECK-NTARGET-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1843// CHECK-NTARGET-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41844// CHECK-NTARGET-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 91845// CHECK-NTARGET-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1846// CHECK-NTARGET:       cond.true:1847// CHECK-NTARGET-NEXT:    br label [[COND_END:%.*]]1848// CHECK-NTARGET:       cond.false:1849// CHECK-NTARGET-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41850// CHECK-NTARGET-NEXT:    br label [[COND_END]]1851// CHECK-NTARGET:       cond.end:1852// CHECK-NTARGET-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]1853// CHECK-NTARGET-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 41854// CHECK-NTARGET-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41855// CHECK-NTARGET-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 41856// CHECK-NTARGET-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]1857// CHECK-NTARGET:       omp.inner.for.cond:1858// CHECK-NTARGET-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41859// CHECK-NTARGET-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41860// CHECK-NTARGET-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]1861// CHECK-NTARGET-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1862// CHECK-NTARGET:       omp.inner.for.body:1863// CHECK-NTARGET-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41864// CHECK-NTARGET-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 11865// CHECK-NTARGET-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]1866// CHECK-NTARGET-NEXT:    store i32 [[ADD]], ptr [[I]], align 41867// CHECK-NTARGET-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 41868// CHECK-NTARGET-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 121869// CHECK-NTARGET-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 41870// CHECK-NTARGET-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]1871// CHECK-NTARGET:       omp.body.continue:1872// CHECK-NTARGET-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]1873// CHECK-NTARGET:       omp.inner.for.inc:1874// CHECK-NTARGET-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41875// CHECK-NTARGET-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 11876// CHECK-NTARGET-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 41877// CHECK-NTARGET-NEXT:    br label [[OMP_INNER_FOR_COND]]1878// CHECK-NTARGET:       omp.inner.for.end:1879// CHECK-NTARGET-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]1880// CHECK-NTARGET:       omp.loop.exit:1881// CHECK-NTARGET-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])1882// CHECK-NTARGET-NEXT:    ret void1883//1884//1885// CHECK-NTARGET-LABEL: define {{[^@]+}}@__cxx_global_var_init.61886// CHECK-NTARGET-SAME: () #[[ATTR3]] {1887// CHECK-NTARGET-NEXT:  entry:1888// CHECK-NTARGET-NEXT:    call void @_ZN2SEC1Ev(ptr noundef nonnull align 4 dereferenceable(256) @e1)1889// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SED1Ev, ptr @e1, ptr @__dso_handle) #[[ATTR2]]1890// CHECK-NTARGET-NEXT:    ret void1891//1892//1893// CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2SEC1Ev1894// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(256) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat {1895// CHECK-NTARGET-NEXT:  entry:1896// CHECK-NTARGET-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81897// CHECK-NTARGET-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81898// CHECK-NTARGET-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81899// CHECK-NTARGET-NEXT:    call void @_ZN2SEC2Ev(ptr noundef nonnull align 4 dereferenceable(256) [[THIS1]])1900// CHECK-NTARGET-NEXT:    ret void1901//1902//1903// CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2SED1Ev1904// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(256) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat {1905// CHECK-NTARGET-NEXT:  entry:1906// CHECK-NTARGET-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81907// CHECK-NTARGET-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81908// CHECK-NTARGET-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81909// CHECK-NTARGET-NEXT:    call void @_ZN2SED2Ev(ptr noundef nonnull align 4 dereferenceable(256) [[THIS1]]) #[[ATTR2]]1910// CHECK-NTARGET-NEXT:    ret void1911//1912//1913// CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2SEC2Ev1914// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(256) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat {1915// CHECK-NTARGET-NEXT:  entry:1916// CHECK-NTARGET-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81917// CHECK-NTARGET-NEXT:    [[A:%.*]] = alloca i32, align 41918// CHECK-NTARGET-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 81919// CHECK-NTARGET-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81920// CHECK-NTARGET-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81921// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 81922// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 41923// CHECK-NTARGET-NEXT:    store i32 [[TMP1]], ptr [[A]], align 41924// CHECK-NTARGET-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 41925// CHECK-NTARGET-NEXT:    store i32 [[TMP2]], ptr [[A_CASTED]], align 41926// CHECK-NTARGET-NEXT:    [[TMP3:%.*]] = load i64, ptr [[A_CASTED]], align 81927// CHECK-NTARGET-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SEC1Ev_l192(i64 [[TMP3]]) #[[ATTR2]]1928// CHECK-NTARGET-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A]], align 41929// CHECK-NTARGET-NEXT:    [[TMP5:%.*]] = load ptr, ptr @R, align 81930// CHECK-NTARGET-NEXT:    store i32 [[TMP4]], ptr [[TMP5]], align 41931// CHECK-NTARGET-NEXT:    ret void1932//1933//1934// CHECK-NTARGET-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SEC1Ev_l1921935// CHECK-NTARGET-SAME: (i64 noundef [[A:%.*]]) #[[ATTR1]] {1936// CHECK-NTARGET-NEXT:  entry:1937// CHECK-NTARGET-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 81938// CHECK-NTARGET-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 81939// CHECK-NTARGET-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 81940// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41941// CHECK-NTARGET-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 41942// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 81943// CHECK-NTARGET-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SEC1Ev_l192.omp_outlined, i64 [[TMP1]])1944// CHECK-NTARGET-NEXT:    ret void1945//1946//1947// CHECK-NTARGET-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SEC1Ev_l192.omp_outlined1948// CHECK-NTARGET-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] {1949// CHECK-NTARGET-NEXT:  entry:1950// CHECK-NTARGET-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81951// CHECK-NTARGET-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81952// CHECK-NTARGET-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 81953// CHECK-NTARGET-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 41954// CHECK-NTARGET-NEXT:    [[TMP:%.*]] = alloca i32, align 41955// CHECK-NTARGET-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 41956// CHECK-NTARGET-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 41957// CHECK-NTARGET-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41958// CHECK-NTARGET-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41959// CHECK-NTARGET-NEXT:    [[I:%.*]] = alloca i32, align 41960// CHECK-NTARGET-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81961// CHECK-NTARGET-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81962// CHECK-NTARGET-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 81963// CHECK-NTARGET-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 41964// CHECK-NTARGET-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 41965// CHECK-NTARGET-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 41966// CHECK-NTARGET-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 41967// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81968// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 41969// CHECK-NTARGET-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1970// CHECK-NTARGET-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41971// CHECK-NTARGET-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 91972// CHECK-NTARGET-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1973// CHECK-NTARGET:       cond.true:1974// CHECK-NTARGET-NEXT:    br label [[COND_END:%.*]]1975// CHECK-NTARGET:       cond.false:1976// CHECK-NTARGET-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41977// CHECK-NTARGET-NEXT:    br label [[COND_END]]1978// CHECK-NTARGET:       cond.end:1979// CHECK-NTARGET-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]1980// CHECK-NTARGET-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 41981// CHECK-NTARGET-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41982// CHECK-NTARGET-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 41983// CHECK-NTARGET-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]1984// CHECK-NTARGET:       omp.inner.for.cond:1985// CHECK-NTARGET-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41986// CHECK-NTARGET-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41987// CHECK-NTARGET-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]1988// CHECK-NTARGET-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1989// CHECK-NTARGET:       omp.inner.for.body:1990// CHECK-NTARGET-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41991// CHECK-NTARGET-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 11992// CHECK-NTARGET-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]1993// CHECK-NTARGET-NEXT:    store i32 [[ADD]], ptr [[I]], align 41994// CHECK-NTARGET-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 41995// CHECK-NTARGET-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 141996// CHECK-NTARGET-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 41997// CHECK-NTARGET-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]1998// CHECK-NTARGET:       omp.body.continue:1999// CHECK-NTARGET-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]2000// CHECK-NTARGET:       omp.inner.for.inc:2001// CHECK-NTARGET-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42002// CHECK-NTARGET-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 12003// CHECK-NTARGET-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 42004// CHECK-NTARGET-NEXT:    br label [[OMP_INNER_FOR_COND]]2005// CHECK-NTARGET:       omp.inner.for.end:2006// CHECK-NTARGET-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]2007// CHECK-NTARGET:       omp.loop.exit:2008// CHECK-NTARGET-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])2009// CHECK-NTARGET-NEXT:    ret void2010//2011//2012// CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2SED2Ev2013// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(256) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat {2014// CHECK-NTARGET-NEXT:  entry:2015// CHECK-NTARGET-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82016// CHECK-NTARGET-NEXT:    [[A:%.*]] = alloca i32, align 42017// CHECK-NTARGET-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 82018// CHECK-NTARGET-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82019// CHECK-NTARGET-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82020// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 82021// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 42022// CHECK-NTARGET-NEXT:    store i32 [[TMP1]], ptr [[A]], align 42023// CHECK-NTARGET-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 42024// CHECK-NTARGET-NEXT:    store i32 [[TMP2]], ptr [[A_CASTED]], align 42025// CHECK-NTARGET-NEXT:    [[TMP3:%.*]] = load i64, ptr [[A_CASTED]], align 82026// CHECK-NTARGET-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SED1Ev_l199(i64 [[TMP3]]) #[[ATTR2]]2027// CHECK-NTARGET-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A]], align 42028// CHECK-NTARGET-NEXT:    [[TMP5:%.*]] = load ptr, ptr @R, align 82029// CHECK-NTARGET-NEXT:    store i32 [[TMP4]], ptr [[TMP5]], align 42030// CHECK-NTARGET-NEXT:    ret void2031//2032//2033// CHECK-NTARGET-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SED1Ev_l1992034// CHECK-NTARGET-SAME: (i64 noundef [[A:%.*]]) #[[ATTR1]] {2035// CHECK-NTARGET-NEXT:  entry:2036// CHECK-NTARGET-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 82037// CHECK-NTARGET-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 82038// CHECK-NTARGET-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 82039// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 42040// CHECK-NTARGET-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 42041// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 82042// CHECK-NTARGET-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SED1Ev_l199.omp_outlined, i64 [[TMP1]])2043// CHECK-NTARGET-NEXT:    ret void2044//2045//2046// CHECK-NTARGET-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SED1Ev_l199.omp_outlined2047// CHECK-NTARGET-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] {2048// CHECK-NTARGET-NEXT:  entry:2049// CHECK-NTARGET-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 82050// CHECK-NTARGET-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 82051// CHECK-NTARGET-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 82052// CHECK-NTARGET-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 42053// CHECK-NTARGET-NEXT:    [[TMP:%.*]] = alloca i32, align 42054// CHECK-NTARGET-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 42055// CHECK-NTARGET-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 42056// CHECK-NTARGET-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42057// CHECK-NTARGET-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42058// CHECK-NTARGET-NEXT:    [[I:%.*]] = alloca i32, align 42059// CHECK-NTARGET-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 82060// CHECK-NTARGET-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 82061// CHECK-NTARGET-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 82062// CHECK-NTARGET-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 42063// CHECK-NTARGET-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 42064// CHECK-NTARGET-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 42065// CHECK-NTARGET-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 42066// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 82067// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 42068// CHECK-NTARGET-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)2069// CHECK-NTARGET-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42070// CHECK-NTARGET-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 92071// CHECK-NTARGET-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2072// CHECK-NTARGET:       cond.true:2073// CHECK-NTARGET-NEXT:    br label [[COND_END:%.*]]2074// CHECK-NTARGET:       cond.false:2075// CHECK-NTARGET-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42076// CHECK-NTARGET-NEXT:    br label [[COND_END]]2077// CHECK-NTARGET:       cond.end:2078// CHECK-NTARGET-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]2079// CHECK-NTARGET-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 42080// CHECK-NTARGET-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42081// CHECK-NTARGET-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 42082// CHECK-NTARGET-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]2083// CHECK-NTARGET:       omp.inner.for.cond:2084// CHECK-NTARGET-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42085// CHECK-NTARGET-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42086// CHECK-NTARGET-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]2087// CHECK-NTARGET-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2088// CHECK-NTARGET:       omp.inner.for.body:2089// CHECK-NTARGET-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42090// CHECK-NTARGET-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 12091// CHECK-NTARGET-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]2092// CHECK-NTARGET-NEXT:    store i32 [[ADD]], ptr [[I]], align 42093// CHECK-NTARGET-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 42094// CHECK-NTARGET-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 152095// CHECK-NTARGET-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 42096// CHECK-NTARGET-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]2097// CHECK-NTARGET:       omp.body.continue:2098// CHECK-NTARGET-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]2099// CHECK-NTARGET:       omp.inner.for.inc:2100// CHECK-NTARGET-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42101// CHECK-NTARGET-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 12102// CHECK-NTARGET-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 42103// CHECK-NTARGET-NEXT:    br label [[OMP_INNER_FOR_COND]]2104// CHECK-NTARGET:       omp.inner.for.end:2105// CHECK-NTARGET-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]2106// CHECK-NTARGET:       omp.loop.exit:2107// CHECK-NTARGET-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])2108// CHECK-NTARGET-NEXT:    ret void2109//2110//2111// CHECK-NTARGET-LABEL: define {{[^@]+}}@__cxx_global_var_init.72112// CHECK-NTARGET-SAME: () #[[ATTR3]] {2113// CHECK-NTARGET-NEXT:  entry:2114// CHECK-NTARGET-NEXT:    call void @_ZN2STILi100EEC1Ev(ptr noundef nonnull align 4 dereferenceable(912) @t1)2115// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2STILi100EED1Ev, ptr @t1, ptr @__dso_handle) #[[ATTR2]]2116// CHECK-NTARGET-NEXT:    ret void2117//2118//2119// CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2STILi100EEC1Ev2120// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(912) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat {2121// CHECK-NTARGET-NEXT:  entry:2122// CHECK-NTARGET-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82123// CHECK-NTARGET-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82124// CHECK-NTARGET-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82125// CHECK-NTARGET-NEXT:    call void @_ZN2STILi100EEC2Ev(ptr noundef nonnull align 4 dereferenceable(912) [[THIS1]])2126// CHECK-NTARGET-NEXT:    ret void2127//2128//2129// CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2STILi100EED1Ev2130// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(912) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat {2131// CHECK-NTARGET-NEXT:  entry:2132// CHECK-NTARGET-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82133// CHECK-NTARGET-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82134// CHECK-NTARGET-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82135// CHECK-NTARGET-NEXT:    call void @_ZN2STILi100EED2Ev(ptr noundef nonnull align 4 dereferenceable(912) [[THIS1]]) #[[ATTR2]]2136// CHECK-NTARGET-NEXT:    ret void2137//2138//2139// CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2STILi100EEC2Ev2140// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(912) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat {2141// CHECK-NTARGET-NEXT:  entry:2142// CHECK-NTARGET-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82143// CHECK-NTARGET-NEXT:    [[A:%.*]] = alloca i32, align 42144// CHECK-NTARGET-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 82145// CHECK-NTARGET-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82146// CHECK-NTARGET-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82147// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 82148// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 42149// CHECK-NTARGET-NEXT:    store i32 [[TMP1]], ptr [[A]], align 42150// CHECK-NTARGET-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 42151// CHECK-NTARGET-NEXT:    store i32 [[TMP2]], ptr [[A_CASTED]], align 42152// CHECK-NTARGET-NEXT:    [[TMP3:%.*]] = load i64, ptr [[A_CASTED]], align 82153// CHECK-NTARGET-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi100EEC1Ev_l218(i64 [[TMP3]]) #[[ATTR2]]2154// CHECK-NTARGET-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A]], align 42155// CHECK-NTARGET-NEXT:    [[TMP5:%.*]] = load ptr, ptr @R, align 82156// CHECK-NTARGET-NEXT:    store i32 [[TMP4]], ptr [[TMP5]], align 42157// CHECK-NTARGET-NEXT:    ret void2158//2159//2160// CHECK-NTARGET-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi100EEC1Ev_l2182161// CHECK-NTARGET-SAME: (i64 noundef [[A:%.*]]) #[[ATTR1]] {2162// CHECK-NTARGET-NEXT:  entry:2163// CHECK-NTARGET-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 82164// CHECK-NTARGET-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 82165// CHECK-NTARGET-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 82166// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 42167// CHECK-NTARGET-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 42168// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 82169// CHECK-NTARGET-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi100EEC1Ev_l218.omp_outlined, i64 [[TMP1]])2170// CHECK-NTARGET-NEXT:    ret void2171//2172//2173// CHECK-NTARGET-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi100EEC1Ev_l218.omp_outlined2174// CHECK-NTARGET-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] {2175// CHECK-NTARGET-NEXT:  entry:2176// CHECK-NTARGET-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 82177// CHECK-NTARGET-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 82178// CHECK-NTARGET-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 82179// CHECK-NTARGET-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 42180// CHECK-NTARGET-NEXT:    [[TMP:%.*]] = alloca i32, align 42181// CHECK-NTARGET-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 42182// CHECK-NTARGET-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 42183// CHECK-NTARGET-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42184// CHECK-NTARGET-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42185// CHECK-NTARGET-NEXT:    [[I:%.*]] = alloca i32, align 42186// CHECK-NTARGET-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 82187// CHECK-NTARGET-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 82188// CHECK-NTARGET-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 82189// CHECK-NTARGET-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 42190// CHECK-NTARGET-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 42191// CHECK-NTARGET-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 42192// CHECK-NTARGET-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 42193// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 82194// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 42195// CHECK-NTARGET-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)2196// CHECK-NTARGET-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42197// CHECK-NTARGET-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 92198// CHECK-NTARGET-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2199// CHECK-NTARGET:       cond.true:2200// CHECK-NTARGET-NEXT:    br label [[COND_END:%.*]]2201// CHECK-NTARGET:       cond.false:2202// CHECK-NTARGET-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42203// CHECK-NTARGET-NEXT:    br label [[COND_END]]2204// CHECK-NTARGET:       cond.end:2205// CHECK-NTARGET-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]2206// CHECK-NTARGET-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 42207// CHECK-NTARGET-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42208// CHECK-NTARGET-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 42209// CHECK-NTARGET-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]2210// CHECK-NTARGET:       omp.inner.for.cond:2211// CHECK-NTARGET-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42212// CHECK-NTARGET-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42213// CHECK-NTARGET-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]2214// CHECK-NTARGET-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2215// CHECK-NTARGET:       omp.inner.for.body:2216// CHECK-NTARGET-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42217// CHECK-NTARGET-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 12218// CHECK-NTARGET-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]2219// CHECK-NTARGET-NEXT:    store i32 [[ADD]], ptr [[I]], align 42220// CHECK-NTARGET-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 42221// CHECK-NTARGET-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1172222// CHECK-NTARGET-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 42223// CHECK-NTARGET-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]2224// CHECK-NTARGET:       omp.body.continue:2225// CHECK-NTARGET-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]2226// CHECK-NTARGET:       omp.inner.for.inc:2227// CHECK-NTARGET-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42228// CHECK-NTARGET-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 12229// CHECK-NTARGET-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 42230// CHECK-NTARGET-NEXT:    br label [[OMP_INNER_FOR_COND]]2231// CHECK-NTARGET:       omp.inner.for.end:2232// CHECK-NTARGET-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]2233// CHECK-NTARGET:       omp.loop.exit:2234// CHECK-NTARGET-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])2235// CHECK-NTARGET-NEXT:    ret void2236//2237//2238// CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2STILi100EED2Ev2239// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(912) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat {2240// CHECK-NTARGET-NEXT:  entry:2241// CHECK-NTARGET-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82242// CHECK-NTARGET-NEXT:    [[A:%.*]] = alloca i32, align 42243// CHECK-NTARGET-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 82244// CHECK-NTARGET-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82245// CHECK-NTARGET-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82246// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 82247// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 42248// CHECK-NTARGET-NEXT:    store i32 [[TMP1]], ptr [[A]], align 42249// CHECK-NTARGET-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 42250// CHECK-NTARGET-NEXT:    store i32 [[TMP2]], ptr [[A_CASTED]], align 42251// CHECK-NTARGET-NEXT:    [[TMP3:%.*]] = load i64, ptr [[A_CASTED]], align 82252// CHECK-NTARGET-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi100EED1Ev_l225(i64 [[TMP3]]) #[[ATTR2]]2253// CHECK-NTARGET-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A]], align 42254// CHECK-NTARGET-NEXT:    [[TMP5:%.*]] = load ptr, ptr @R, align 82255// CHECK-NTARGET-NEXT:    store i32 [[TMP4]], ptr [[TMP5]], align 42256// CHECK-NTARGET-NEXT:    ret void2257//2258//2259// CHECK-NTARGET-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi100EED1Ev_l2252260// CHECK-NTARGET-SAME: (i64 noundef [[A:%.*]]) #[[ATTR1]] {2261// CHECK-NTARGET-NEXT:  entry:2262// CHECK-NTARGET-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 82263// CHECK-NTARGET-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 82264// CHECK-NTARGET-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 82265// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 42266// CHECK-NTARGET-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 42267// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 82268// CHECK-NTARGET-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi100EED1Ev_l225.omp_outlined, i64 [[TMP1]])2269// CHECK-NTARGET-NEXT:    ret void2270//2271//2272// CHECK-NTARGET-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi100EED1Ev_l225.omp_outlined2273// CHECK-NTARGET-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] {2274// CHECK-NTARGET-NEXT:  entry:2275// CHECK-NTARGET-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 82276// CHECK-NTARGET-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 82277// CHECK-NTARGET-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 82278// CHECK-NTARGET-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 42279// CHECK-NTARGET-NEXT:    [[TMP:%.*]] = alloca i32, align 42280// CHECK-NTARGET-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 42281// CHECK-NTARGET-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 42282// CHECK-NTARGET-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42283// CHECK-NTARGET-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42284// CHECK-NTARGET-NEXT:    [[I:%.*]] = alloca i32, align 42285// CHECK-NTARGET-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 82286// CHECK-NTARGET-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 82287// CHECK-NTARGET-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 82288// CHECK-NTARGET-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 42289// CHECK-NTARGET-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 42290// CHECK-NTARGET-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 42291// CHECK-NTARGET-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 42292// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 82293// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 42294// CHECK-NTARGET-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)2295// CHECK-NTARGET-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42296// CHECK-NTARGET-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 92297// CHECK-NTARGET-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2298// CHECK-NTARGET:       cond.true:2299// CHECK-NTARGET-NEXT:    br label [[COND_END:%.*]]2300// CHECK-NTARGET:       cond.false:2301// CHECK-NTARGET-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42302// CHECK-NTARGET-NEXT:    br label [[COND_END]]2303// CHECK-NTARGET:       cond.end:2304// CHECK-NTARGET-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]2305// CHECK-NTARGET-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 42306// CHECK-NTARGET-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42307// CHECK-NTARGET-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 42308// CHECK-NTARGET-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]2309// CHECK-NTARGET:       omp.inner.for.cond:2310// CHECK-NTARGET-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42311// CHECK-NTARGET-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42312// CHECK-NTARGET-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]2313// CHECK-NTARGET-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2314// CHECK-NTARGET:       omp.inner.for.body:2315// CHECK-NTARGET-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42316// CHECK-NTARGET-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 12317// CHECK-NTARGET-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]2318// CHECK-NTARGET-NEXT:    store i32 [[ADD]], ptr [[I]], align 42319// CHECK-NTARGET-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 42320// CHECK-NTARGET-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1182321// CHECK-NTARGET-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 42322// CHECK-NTARGET-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]2323// CHECK-NTARGET:       omp.body.continue:2324// CHECK-NTARGET-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]2325// CHECK-NTARGET:       omp.inner.for.inc:2326// CHECK-NTARGET-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42327// CHECK-NTARGET-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 12328// CHECK-NTARGET-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 42329// CHECK-NTARGET-NEXT:    br label [[OMP_INNER_FOR_COND]]2330// CHECK-NTARGET:       omp.inner.for.end:2331// CHECK-NTARGET-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]2332// CHECK-NTARGET:       omp.loop.exit:2333// CHECK-NTARGET-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])2334// CHECK-NTARGET-NEXT:    ret void2335//2336//2337// CHECK-NTARGET-LABEL: define {{[^@]+}}@__cxx_global_var_init.82338// CHECK-NTARGET-SAME: () #[[ATTR3]] {2339// CHECK-NTARGET-NEXT:  entry:2340// CHECK-NTARGET-NEXT:    call void @_ZN2STILi1000EEC1Ev(ptr noundef nonnull align 4 dereferenceable(4512) @t2)2341// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2STILi1000EED1Ev, ptr @t2, ptr @__dso_handle) #[[ATTR2]]2342// CHECK-NTARGET-NEXT:    ret void2343//2344//2345// CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2STILi1000EEC1Ev2346// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(4512) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat {2347// CHECK-NTARGET-NEXT:  entry:2348// CHECK-NTARGET-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82349// CHECK-NTARGET-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82350// CHECK-NTARGET-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82351// CHECK-NTARGET-NEXT:    call void @_ZN2STILi1000EEC2Ev(ptr noundef nonnull align 4 dereferenceable(4512) [[THIS1]])2352// CHECK-NTARGET-NEXT:    ret void2353//2354//2355// CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2STILi1000EED1Ev2356// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(4512) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat {2357// CHECK-NTARGET-NEXT:  entry:2358// CHECK-NTARGET-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82359// CHECK-NTARGET-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82360// CHECK-NTARGET-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82361// CHECK-NTARGET-NEXT:    call void @_ZN2STILi1000EED2Ev(ptr noundef nonnull align 4 dereferenceable(4512) [[THIS1]]) #[[ATTR2]]2362// CHECK-NTARGET-NEXT:    ret void2363//2364//2365// CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2STILi1000EEC2Ev2366// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(4512) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat {2367// CHECK-NTARGET-NEXT:  entry:2368// CHECK-NTARGET-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82369// CHECK-NTARGET-NEXT:    [[A:%.*]] = alloca i32, align 42370// CHECK-NTARGET-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 82371// CHECK-NTARGET-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82372// CHECK-NTARGET-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82373// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 82374// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 42375// CHECK-NTARGET-NEXT:    store i32 [[TMP1]], ptr [[A]], align 42376// CHECK-NTARGET-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 42377// CHECK-NTARGET-NEXT:    store i32 [[TMP2]], ptr [[A_CASTED]], align 42378// CHECK-NTARGET-NEXT:    [[TMP3:%.*]] = load i64, ptr [[A_CASTED]], align 82379// CHECK-NTARGET-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi1000EEC1Ev_l218(i64 [[TMP3]]) #[[ATTR2]]2380// CHECK-NTARGET-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A]], align 42381// CHECK-NTARGET-NEXT:    [[TMP5:%.*]] = load ptr, ptr @R, align 82382// CHECK-NTARGET-NEXT:    store i32 [[TMP4]], ptr [[TMP5]], align 42383// CHECK-NTARGET-NEXT:    ret void2384//2385//2386// CHECK-NTARGET-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi1000EEC1Ev_l2182387// CHECK-NTARGET-SAME: (i64 noundef [[A:%.*]]) #[[ATTR1]] {2388// CHECK-NTARGET-NEXT:  entry:2389// CHECK-NTARGET-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 82390// CHECK-NTARGET-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 82391// CHECK-NTARGET-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 82392// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 42393// CHECK-NTARGET-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 42394// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 82395// CHECK-NTARGET-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi1000EEC1Ev_l218.omp_outlined, i64 [[TMP1]])2396// CHECK-NTARGET-NEXT:    ret void2397//2398//2399// CHECK-NTARGET-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi1000EEC1Ev_l218.omp_outlined2400// CHECK-NTARGET-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] {2401// CHECK-NTARGET-NEXT:  entry:2402// CHECK-NTARGET-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 82403// CHECK-NTARGET-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 82404// CHECK-NTARGET-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 82405// CHECK-NTARGET-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 42406// CHECK-NTARGET-NEXT:    [[TMP:%.*]] = alloca i32, align 42407// CHECK-NTARGET-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 42408// CHECK-NTARGET-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 42409// CHECK-NTARGET-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42410// CHECK-NTARGET-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42411// CHECK-NTARGET-NEXT:    [[I:%.*]] = alloca i32, align 42412// CHECK-NTARGET-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 82413// CHECK-NTARGET-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 82414// CHECK-NTARGET-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 82415// CHECK-NTARGET-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 42416// CHECK-NTARGET-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 42417// CHECK-NTARGET-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 42418// CHECK-NTARGET-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 42419// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 82420// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 42421// CHECK-NTARGET-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)2422// CHECK-NTARGET-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42423// CHECK-NTARGET-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 92424// CHECK-NTARGET-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2425// CHECK-NTARGET:       cond.true:2426// CHECK-NTARGET-NEXT:    br label [[COND_END:%.*]]2427// CHECK-NTARGET:       cond.false:2428// CHECK-NTARGET-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42429// CHECK-NTARGET-NEXT:    br label [[COND_END]]2430// CHECK-NTARGET:       cond.end:2431// CHECK-NTARGET-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]2432// CHECK-NTARGET-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 42433// CHECK-NTARGET-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42434// CHECK-NTARGET-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 42435// CHECK-NTARGET-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]2436// CHECK-NTARGET:       omp.inner.for.cond:2437// CHECK-NTARGET-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42438// CHECK-NTARGET-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42439// CHECK-NTARGET-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]2440// CHECK-NTARGET-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2441// CHECK-NTARGET:       omp.inner.for.body:2442// CHECK-NTARGET-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42443// CHECK-NTARGET-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 12444// CHECK-NTARGET-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]2445// CHECK-NTARGET-NEXT:    store i32 [[ADD]], ptr [[I]], align 42446// CHECK-NTARGET-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 42447// CHECK-NTARGET-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 10172448// CHECK-NTARGET-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 42449// CHECK-NTARGET-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]2450// CHECK-NTARGET:       omp.body.continue:2451// CHECK-NTARGET-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]2452// CHECK-NTARGET:       omp.inner.for.inc:2453// CHECK-NTARGET-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42454// CHECK-NTARGET-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 12455// CHECK-NTARGET-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 42456// CHECK-NTARGET-NEXT:    br label [[OMP_INNER_FOR_COND]]2457// CHECK-NTARGET:       omp.inner.for.end:2458// CHECK-NTARGET-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]2459// CHECK-NTARGET:       omp.loop.exit:2460// CHECK-NTARGET-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])2461// CHECK-NTARGET-NEXT:    ret void2462//2463//2464// CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2STILi1000EED2Ev2465// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(4512) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat {2466// CHECK-NTARGET-NEXT:  entry:2467// CHECK-NTARGET-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82468// CHECK-NTARGET-NEXT:    [[A:%.*]] = alloca i32, align 42469// CHECK-NTARGET-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 82470// CHECK-NTARGET-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82471// CHECK-NTARGET-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82472// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 82473// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 42474// CHECK-NTARGET-NEXT:    store i32 [[TMP1]], ptr [[A]], align 42475// CHECK-NTARGET-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 42476// CHECK-NTARGET-NEXT:    store i32 [[TMP2]], ptr [[A_CASTED]], align 42477// CHECK-NTARGET-NEXT:    [[TMP3:%.*]] = load i64, ptr [[A_CASTED]], align 82478// CHECK-NTARGET-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi1000EED1Ev_l225(i64 [[TMP3]]) #[[ATTR2]]2479// CHECK-NTARGET-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A]], align 42480// CHECK-NTARGET-NEXT:    [[TMP5:%.*]] = load ptr, ptr @R, align 82481// CHECK-NTARGET-NEXT:    store i32 [[TMP4]], ptr [[TMP5]], align 42482// CHECK-NTARGET-NEXT:    ret void2483//2484//2485// CHECK-NTARGET-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi1000EED1Ev_l2252486// CHECK-NTARGET-SAME: (i64 noundef [[A:%.*]]) #[[ATTR1]] {2487// CHECK-NTARGET-NEXT:  entry:2488// CHECK-NTARGET-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 82489// CHECK-NTARGET-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 82490// CHECK-NTARGET-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 82491// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 42492// CHECK-NTARGET-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 42493// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 82494// CHECK-NTARGET-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi1000EED1Ev_l225.omp_outlined, i64 [[TMP1]])2495// CHECK-NTARGET-NEXT:    ret void2496//2497//2498// CHECK-NTARGET-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi1000EED1Ev_l225.omp_outlined2499// CHECK-NTARGET-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] {2500// CHECK-NTARGET-NEXT:  entry:2501// CHECK-NTARGET-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 82502// CHECK-NTARGET-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 82503// CHECK-NTARGET-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 82504// CHECK-NTARGET-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 42505// CHECK-NTARGET-NEXT:    [[TMP:%.*]] = alloca i32, align 42506// CHECK-NTARGET-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 42507// CHECK-NTARGET-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 42508// CHECK-NTARGET-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42509// CHECK-NTARGET-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42510// CHECK-NTARGET-NEXT:    [[I:%.*]] = alloca i32, align 42511// CHECK-NTARGET-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 82512// CHECK-NTARGET-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 82513// CHECK-NTARGET-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 82514// CHECK-NTARGET-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 42515// CHECK-NTARGET-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 42516// CHECK-NTARGET-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 42517// CHECK-NTARGET-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 42518// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 82519// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 42520// CHECK-NTARGET-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)2521// CHECK-NTARGET-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42522// CHECK-NTARGET-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 92523// CHECK-NTARGET-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2524// CHECK-NTARGET:       cond.true:2525// CHECK-NTARGET-NEXT:    br label [[COND_END:%.*]]2526// CHECK-NTARGET:       cond.false:2527// CHECK-NTARGET-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42528// CHECK-NTARGET-NEXT:    br label [[COND_END]]2529// CHECK-NTARGET:       cond.end:2530// CHECK-NTARGET-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]2531// CHECK-NTARGET-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 42532// CHECK-NTARGET-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42533// CHECK-NTARGET-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 42534// CHECK-NTARGET-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]2535// CHECK-NTARGET:       omp.inner.for.cond:2536// CHECK-NTARGET-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42537// CHECK-NTARGET-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42538// CHECK-NTARGET-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]2539// CHECK-NTARGET-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2540// CHECK-NTARGET:       omp.inner.for.body:2541// CHECK-NTARGET-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42542// CHECK-NTARGET-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 12543// CHECK-NTARGET-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]2544// CHECK-NTARGET-NEXT:    store i32 [[ADD]], ptr [[I]], align 42545// CHECK-NTARGET-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 42546// CHECK-NTARGET-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 10182547// CHECK-NTARGET-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 42548// CHECK-NTARGET-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]2549// CHECK-NTARGET:       omp.body.continue:2550// CHECK-NTARGET-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]2551// CHECK-NTARGET:       omp.inner.for.inc:2552// CHECK-NTARGET-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42553// CHECK-NTARGET-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 12554// CHECK-NTARGET-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 42555// CHECK-NTARGET-NEXT:    br label [[OMP_INNER_FOR_COND]]2556// CHECK-NTARGET:       omp.inner.for.end:2557// CHECK-NTARGET-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]2558// CHECK-NTARGET:       omp.loop.exit:2559// CHECK-NTARGET-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])2560// CHECK-NTARGET-NEXT:    ret void2561//2562//2563// CHECK-NTARGET-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SB3fooEv_l1222564// CHECK-NTARGET-SAME: (i64 noundef [[A:%.*]]) #[[ATTR1]] {2565// CHECK-NTARGET-NEXT:  entry:2566// CHECK-NTARGET-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 82567// CHECK-NTARGET-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 82568// CHECK-NTARGET-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 82569// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 42570// CHECK-NTARGET-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 42571// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 82572// CHECK-NTARGET-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SB3fooEv_l122.omp_outlined, i64 [[TMP1]])2573// CHECK-NTARGET-NEXT:    ret void2574//2575//2576// CHECK-NTARGET-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SB3fooEv_l122.omp_outlined2577// CHECK-NTARGET-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] {2578// CHECK-NTARGET-NEXT:  entry:2579// CHECK-NTARGET-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 82580// CHECK-NTARGET-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 82581// CHECK-NTARGET-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 82582// CHECK-NTARGET-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 42583// CHECK-NTARGET-NEXT:    [[TMP:%.*]] = alloca i32, align 42584// CHECK-NTARGET-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 42585// CHECK-NTARGET-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 42586// CHECK-NTARGET-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42587// CHECK-NTARGET-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42588// CHECK-NTARGET-NEXT:    [[I:%.*]] = alloca i32, align 42589// CHECK-NTARGET-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 82590// CHECK-NTARGET-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 82591// CHECK-NTARGET-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 82592// CHECK-NTARGET-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 42593// CHECK-NTARGET-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 42594// CHECK-NTARGET-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 42595// CHECK-NTARGET-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 42596// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 82597// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 42598// CHECK-NTARGET-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)2599// CHECK-NTARGET-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42600// CHECK-NTARGET-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 92601// CHECK-NTARGET-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2602// CHECK-NTARGET:       cond.true:2603// CHECK-NTARGET-NEXT:    br label [[COND_END:%.*]]2604// CHECK-NTARGET:       cond.false:2605// CHECK-NTARGET-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42606// CHECK-NTARGET-NEXT:    br label [[COND_END]]2607// CHECK-NTARGET:       cond.end:2608// CHECK-NTARGET-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]2609// CHECK-NTARGET-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 42610// CHECK-NTARGET-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42611// CHECK-NTARGET-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 42612// CHECK-NTARGET-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]2613// CHECK-NTARGET:       omp.inner.for.cond:2614// CHECK-NTARGET-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42615// CHECK-NTARGET-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42616// CHECK-NTARGET-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]2617// CHECK-NTARGET-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2618// CHECK-NTARGET:       omp.inner.for.body:2619// CHECK-NTARGET-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42620// CHECK-NTARGET-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 12621// CHECK-NTARGET-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]2622// CHECK-NTARGET-NEXT:    store i32 [[ADD]], ptr [[I]], align 42623// CHECK-NTARGET-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 42624// CHECK-NTARGET-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 42625// CHECK-NTARGET-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 42626// CHECK-NTARGET-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]2627// CHECK-NTARGET:       omp.body.continue:2628// CHECK-NTARGET-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]2629// CHECK-NTARGET:       omp.inner.for.inc:2630// CHECK-NTARGET-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42631// CHECK-NTARGET-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 12632// CHECK-NTARGET-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 42633// CHECK-NTARGET-NEXT:    br label [[OMP_INNER_FOR_COND]]2634// CHECK-NTARGET:       omp.inner.for.end:2635// CHECK-NTARGET-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]2636// CHECK-NTARGET:       omp.loop.exit:2637// CHECK-NTARGET-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])2638// CHECK-NTARGET-NEXT:    ret void2639//2640//2641// CHECK-NTARGET-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SE3fooEv_l1852642// CHECK-NTARGET-SAME: (i64 noundef [[A:%.*]]) #[[ATTR1]] {2643// CHECK-NTARGET-NEXT:  entry:2644// CHECK-NTARGET-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 82645// CHECK-NTARGET-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 82646// CHECK-NTARGET-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 82647// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 42648// CHECK-NTARGET-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 42649// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 82650// CHECK-NTARGET-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SE3fooEv_l185.omp_outlined, i64 [[TMP1]])2651// CHECK-NTARGET-NEXT:    ret void2652//2653//2654// CHECK-NTARGET-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SE3fooEv_l185.omp_outlined2655// CHECK-NTARGET-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] {2656// CHECK-NTARGET-NEXT:  entry:2657// CHECK-NTARGET-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 82658// CHECK-NTARGET-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 82659// CHECK-NTARGET-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 82660// CHECK-NTARGET-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 42661// CHECK-NTARGET-NEXT:    [[TMP:%.*]] = alloca i32, align 42662// CHECK-NTARGET-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 42663// CHECK-NTARGET-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 42664// CHECK-NTARGET-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42665// CHECK-NTARGET-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42666// CHECK-NTARGET-NEXT:    [[I:%.*]] = alloca i32, align 42667// CHECK-NTARGET-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 82668// CHECK-NTARGET-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 82669// CHECK-NTARGET-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 82670// CHECK-NTARGET-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 42671// CHECK-NTARGET-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 42672// CHECK-NTARGET-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 42673// CHECK-NTARGET-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 42674// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 82675// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 42676// CHECK-NTARGET-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)2677// CHECK-NTARGET-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42678// CHECK-NTARGET-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 92679// CHECK-NTARGET-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2680// CHECK-NTARGET:       cond.true:2681// CHECK-NTARGET-NEXT:    br label [[COND_END:%.*]]2682// CHECK-NTARGET:       cond.false:2683// CHECK-NTARGET-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42684// CHECK-NTARGET-NEXT:    br label [[COND_END]]2685// CHECK-NTARGET:       cond.end:2686// CHECK-NTARGET-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]2687// CHECK-NTARGET-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 42688// CHECK-NTARGET-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42689// CHECK-NTARGET-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 42690// CHECK-NTARGET-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]2691// CHECK-NTARGET:       omp.inner.for.cond:2692// CHECK-NTARGET-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42693// CHECK-NTARGET-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42694// CHECK-NTARGET-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]2695// CHECK-NTARGET-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2696// CHECK-NTARGET:       omp.inner.for.body:2697// CHECK-NTARGET-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42698// CHECK-NTARGET-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 12699// CHECK-NTARGET-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]2700// CHECK-NTARGET-NEXT:    store i32 [[ADD]], ptr [[I]], align 42701// CHECK-NTARGET-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 42702// CHECK-NTARGET-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 132703// CHECK-NTARGET-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 42704// CHECK-NTARGET-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]2705// CHECK-NTARGET:       omp.body.continue:2706// CHECK-NTARGET-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]2707// CHECK-NTARGET:       omp.inner.for.inc:2708// CHECK-NTARGET-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42709// CHECK-NTARGET-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 12710// CHECK-NTARGET-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 42711// CHECK-NTARGET-NEXT:    br label [[OMP_INNER_FOR_COND]]2712// CHECK-NTARGET:       omp.inner.for.end:2713// CHECK-NTARGET-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]2714// CHECK-NTARGET:       omp.loop.exit:2715// CHECK-NTARGET-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])2716// CHECK-NTARGET-NEXT:    ret void2717//2718//2719// CHECK-NTARGET-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi100EE3fooEv_l2112720// CHECK-NTARGET-SAME: (i64 noundef [[A:%.*]]) #[[ATTR1]] {2721// CHECK-NTARGET-NEXT:  entry:2722// CHECK-NTARGET-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 82723// CHECK-NTARGET-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 82724// CHECK-NTARGET-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 82725// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 42726// CHECK-NTARGET-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 42727// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 82728// CHECK-NTARGET-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi100EE3fooEv_l211.omp_outlined, i64 [[TMP1]])2729// CHECK-NTARGET-NEXT:    ret void2730//2731//2732// CHECK-NTARGET-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi100EE3fooEv_l211.omp_outlined2733// CHECK-NTARGET-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] {2734// CHECK-NTARGET-NEXT:  entry:2735// CHECK-NTARGET-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 82736// CHECK-NTARGET-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 82737// CHECK-NTARGET-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 82738// CHECK-NTARGET-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 42739// CHECK-NTARGET-NEXT:    [[TMP:%.*]] = alloca i32, align 42740// CHECK-NTARGET-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 42741// CHECK-NTARGET-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 42742// CHECK-NTARGET-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42743// CHECK-NTARGET-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42744// CHECK-NTARGET-NEXT:    [[I:%.*]] = alloca i32, align 42745// CHECK-NTARGET-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 82746// CHECK-NTARGET-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 82747// CHECK-NTARGET-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 82748// CHECK-NTARGET-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 42749// CHECK-NTARGET-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 42750// CHECK-NTARGET-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 42751// CHECK-NTARGET-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 42752// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 82753// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 42754// CHECK-NTARGET-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)2755// CHECK-NTARGET-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42756// CHECK-NTARGET-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 92757// CHECK-NTARGET-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2758// CHECK-NTARGET:       cond.true:2759// CHECK-NTARGET-NEXT:    br label [[COND_END:%.*]]2760// CHECK-NTARGET:       cond.false:2761// CHECK-NTARGET-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42762// CHECK-NTARGET-NEXT:    br label [[COND_END]]2763// CHECK-NTARGET:       cond.end:2764// CHECK-NTARGET-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]2765// CHECK-NTARGET-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 42766// CHECK-NTARGET-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42767// CHECK-NTARGET-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 42768// CHECK-NTARGET-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]2769// CHECK-NTARGET:       omp.inner.for.cond:2770// CHECK-NTARGET-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42771// CHECK-NTARGET-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42772// CHECK-NTARGET-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]2773// CHECK-NTARGET-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2774// CHECK-NTARGET:       omp.inner.for.body:2775// CHECK-NTARGET-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42776// CHECK-NTARGET-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 12777// CHECK-NTARGET-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]2778// CHECK-NTARGET-NEXT:    store i32 [[ADD]], ptr [[I]], align 42779// CHECK-NTARGET-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 42780// CHECK-NTARGET-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1162781// CHECK-NTARGET-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 42782// CHECK-NTARGET-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]2783// CHECK-NTARGET:       omp.body.continue:2784// CHECK-NTARGET-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]2785// CHECK-NTARGET:       omp.inner.for.inc:2786// CHECK-NTARGET-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42787// CHECK-NTARGET-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 12788// CHECK-NTARGET-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 42789// CHECK-NTARGET-NEXT:    br label [[OMP_INNER_FOR_COND]]2790// CHECK-NTARGET:       omp.inner.for.end:2791// CHECK-NTARGET-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]2792// CHECK-NTARGET:       omp.loop.exit:2793// CHECK-NTARGET-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])2794// CHECK-NTARGET-NEXT:    ret void2795//2796//2797// CHECK-NTARGET-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi1000EE3fooEv_l2112798// CHECK-NTARGET-SAME: (i64 noundef [[A:%.*]]) #[[ATTR1]] {2799// CHECK-NTARGET-NEXT:  entry:2800// CHECK-NTARGET-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 82801// CHECK-NTARGET-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 82802// CHECK-NTARGET-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 82803// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 42804// CHECK-NTARGET-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 42805// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 82806// CHECK-NTARGET-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi1000EE3fooEv_l211.omp_outlined, i64 [[TMP1]])2807// CHECK-NTARGET-NEXT:    ret void2808//2809//2810// CHECK-NTARGET-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi1000EE3fooEv_l211.omp_outlined2811// CHECK-NTARGET-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] {2812// CHECK-NTARGET-NEXT:  entry:2813// CHECK-NTARGET-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 82814// CHECK-NTARGET-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 82815// CHECK-NTARGET-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 82816// CHECK-NTARGET-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 42817// CHECK-NTARGET-NEXT:    [[TMP:%.*]] = alloca i32, align 42818// CHECK-NTARGET-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 42819// CHECK-NTARGET-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 42820// CHECK-NTARGET-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42821// CHECK-NTARGET-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42822// CHECK-NTARGET-NEXT:    [[I:%.*]] = alloca i32, align 42823// CHECK-NTARGET-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 82824// CHECK-NTARGET-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 82825// CHECK-NTARGET-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 82826// CHECK-NTARGET-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 42827// CHECK-NTARGET-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 42828// CHECK-NTARGET-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 42829// CHECK-NTARGET-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 42830// CHECK-NTARGET-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 82831// CHECK-NTARGET-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 42832// CHECK-NTARGET-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)2833// CHECK-NTARGET-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42834// CHECK-NTARGET-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 92835// CHECK-NTARGET-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2836// CHECK-NTARGET:       cond.true:2837// CHECK-NTARGET-NEXT:    br label [[COND_END:%.*]]2838// CHECK-NTARGET:       cond.false:2839// CHECK-NTARGET-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42840// CHECK-NTARGET-NEXT:    br label [[COND_END]]2841// CHECK-NTARGET:       cond.end:2842// CHECK-NTARGET-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]2843// CHECK-NTARGET-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 42844// CHECK-NTARGET-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42845// CHECK-NTARGET-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 42846// CHECK-NTARGET-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]2847// CHECK-NTARGET:       omp.inner.for.cond:2848// CHECK-NTARGET-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42849// CHECK-NTARGET-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42850// CHECK-NTARGET-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]2851// CHECK-NTARGET-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2852// CHECK-NTARGET:       omp.inner.for.body:2853// CHECK-NTARGET-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42854// CHECK-NTARGET-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 12855// CHECK-NTARGET-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]2856// CHECK-NTARGET-NEXT:    store i32 [[ADD]], ptr [[I]], align 42857// CHECK-NTARGET-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 42858// CHECK-NTARGET-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 10162859// CHECK-NTARGET-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 42860// CHECK-NTARGET-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]2861// CHECK-NTARGET:       omp.body.continue:2862// CHECK-NTARGET-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]2863// CHECK-NTARGET:       omp.inner.for.inc:2864// CHECK-NTARGET-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42865// CHECK-NTARGET-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 12866// CHECK-NTARGET-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 42867// CHECK-NTARGET-NEXT:    br label [[OMP_INNER_FOR_COND]]2868// CHECK-NTARGET:       omp.inner.for.end:2869// CHECK-NTARGET-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]2870// CHECK-NTARGET:       omp.loop.exit:2871// CHECK-NTARGET-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])2872// CHECK-NTARGET-NEXT:    ret void2873//2874//2875// CHECK-NTARGET-LABEL: define {{[^@]+}}@_GLOBAL__I_0005002876// CHECK-NTARGET-SAME: () #[[ATTR3]] {2877// CHECK-NTARGET-NEXT:  entry:2878// CHECK-NTARGET-NEXT:    call void @__cxx_global_var_init()2879// CHECK-NTARGET-NEXT:    call void @__cxx_global_var_init.2()2880// CHECK-NTARGET-NEXT:    ret void2881//2882//2883// CHECK-NTARGET-LABEL: define {{[^@]+}}@_GLOBAL__I_0005012884// CHECK-NTARGET-SAME: () #[[ATTR3]] {2885// CHECK-NTARGET-NEXT:  entry:2886// CHECK-NTARGET-NEXT:    call void @__cxx_global_var_init.3()2887// CHECK-NTARGET-NEXT:    ret void2888//2889//2890// CHECK-NTARGET-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_parallel_generic_loop_codegen_1.cpp2891// CHECK-NTARGET-SAME: () #[[ATTR3]] {2892// CHECK-NTARGET-NEXT:  entry:2893// CHECK-NTARGET-NEXT:    call void @__cxx_global_var_init.1()2894// CHECK-NTARGET-NEXT:    call void @__cxx_global_var_init.4()2895// CHECK-NTARGET-NEXT:    call void @__cxx_global_var_init.5()2896// CHECK-NTARGET-NEXT:    call void @__cxx_global_var_init.6()2897// CHECK-NTARGET-NEXT:    call void @__cxx_global_var_init.7()2898// CHECK-NTARGET-NEXT:    call void @__cxx_global_var_init.8()2899// CHECK-NTARGET-NEXT:    ret void2900//2901//2902// SIMD-ONLY2-LABEL: define {{[^@]+}}@__cxx_global_var_init2903// SIMD-ONLY2-SAME: () #[[ATTR0:[0-9]+]] {2904// SIMD-ONLY2-NEXT:  entry:2905// SIMD-ONLY2-NEXT:    call void @_ZN2SAC1Ev(ptr noundef nonnull align 4 dereferenceable(16) @_ZL2a1)2906// SIMD-ONLY2-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SAD1Ev, ptr @_ZL2a1, ptr @__dso_handle) #[[ATTR2:[0-9]+]]2907// SIMD-ONLY2-NEXT:    ret void2908//2909//2910// SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2SAC1Ev2911// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {2912// SIMD-ONLY2-NEXT:  entry:2913// SIMD-ONLY2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82914// SIMD-ONLY2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82915// SIMD-ONLY2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82916// SIMD-ONLY2-NEXT:    call void @_ZN2SAC2Ev(ptr noundef nonnull align 4 dereferenceable(16) [[THIS1]])2917// SIMD-ONLY2-NEXT:    ret void2918//2919//2920// SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2SAD1Ev2921// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {2922// SIMD-ONLY2-NEXT:  entry:2923// SIMD-ONLY2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82924// SIMD-ONLY2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82925// SIMD-ONLY2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82926// SIMD-ONLY2-NEXT:    call void @_ZN2SAD2Ev(ptr noundef nonnull align 4 dereferenceable(16) [[THIS1]]) #[[ATTR2]]2927// SIMD-ONLY2-NEXT:    ret void2928//2929//2930// SIMD-ONLY2-LABEL: define {{[^@]+}}@__cxx_global_var_init.12931// SIMD-ONLY2-SAME: () #[[ATTR0]] {2932// SIMD-ONLY2-NEXT:  entry:2933// SIMD-ONLY2-NEXT:    call void @_ZN2SAC1Ev(ptr noundef nonnull align 4 dereferenceable(16) @a2)2934// SIMD-ONLY2-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SAD1Ev, ptr @a2, ptr @__dso_handle) #[[ATTR2]]2935// SIMD-ONLY2-NEXT:    ret void2936//2937//2938// SIMD-ONLY2-LABEL: define {{[^@]+}}@__cxx_global_var_init.22939// SIMD-ONLY2-SAME: () #[[ATTR0]] {2940// SIMD-ONLY2-NEXT:  entry:2941// SIMD-ONLY2-NEXT:    call void @_ZN2SBC1Ev(ptr noundef nonnull align 4 dereferenceable(32) @b1)2942// SIMD-ONLY2-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SBD1Ev, ptr @b1, ptr @__dso_handle) #[[ATTR2]]2943// SIMD-ONLY2-NEXT:    ret void2944//2945//2946// SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2SBC1Ev2947// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(32) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {2948// SIMD-ONLY2-NEXT:  entry:2949// SIMD-ONLY2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82950// SIMD-ONLY2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82951// SIMD-ONLY2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82952// SIMD-ONLY2-NEXT:    call void @_ZN2SBC2Ev(ptr noundef nonnull align 4 dereferenceable(32) [[THIS1]])2953// SIMD-ONLY2-NEXT:    ret void2954//2955//2956// SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2SBD1Ev2957// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(32) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {2958// SIMD-ONLY2-NEXT:  entry:2959// SIMD-ONLY2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82960// SIMD-ONLY2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82961// SIMD-ONLY2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82962// SIMD-ONLY2-NEXT:    call void @_ZN2SBD2Ev(ptr noundef nonnull align 4 dereferenceable(32) [[THIS1]]) #[[ATTR2]]2963// SIMD-ONLY2-NEXT:    ret void2964//2965//2966// SIMD-ONLY2-LABEL: define {{[^@]+}}@__cxx_global_var_init.32967// SIMD-ONLY2-SAME: () #[[ATTR0]] {2968// SIMD-ONLY2-NEXT:  entry:2969// SIMD-ONLY2-NEXT:    call void @_ZN2SBC1Ev(ptr noundef nonnull align 4 dereferenceable(32) @b2)2970// SIMD-ONLY2-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SBD1Ev, ptr @b2, ptr @__dso_handle) #[[ATTR2]]2971// SIMD-ONLY2-NEXT:    ret void2972//2973//2974// SIMD-ONLY2-LABEL: define {{[^@]+}}@__cxx_global_var_init.42975// SIMD-ONLY2-SAME: () #[[ATTR0]] {2976// SIMD-ONLY2-NEXT:  entry:2977// SIMD-ONLY2-NEXT:    call void @_ZN2SCC1Ev(ptr noundef nonnull align 4 dereferenceable(64) @_ZL2c1)2978// SIMD-ONLY2-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SCD1Ev, ptr @_ZL2c1, ptr @__dso_handle) #[[ATTR2]]2979// SIMD-ONLY2-NEXT:    ret void2980//2981//2982// SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2SCC1Ev2983// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(64) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {2984// SIMD-ONLY2-NEXT:  entry:2985// SIMD-ONLY2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82986// SIMD-ONLY2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82987// SIMD-ONLY2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82988// SIMD-ONLY2-NEXT:    call void @_ZN2SCC2Ev(ptr noundef nonnull align 4 dereferenceable(64) [[THIS1]])2989// SIMD-ONLY2-NEXT:    ret void2990//2991//2992// SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2SCD1Ev2993// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(64) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {2994// SIMD-ONLY2-NEXT:  entry:2995// SIMD-ONLY2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82996// SIMD-ONLY2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82997// SIMD-ONLY2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82998// SIMD-ONLY2-NEXT:    call void @_ZN2SCD2Ev(ptr noundef nonnull align 4 dereferenceable(64) [[THIS1]]) #[[ATTR2]]2999// SIMD-ONLY2-NEXT:    ret void3000//3001//3002// SIMD-ONLY2-LABEL: define {{[^@]+}}@__cxx_global_var_init.53003// SIMD-ONLY2-SAME: () #[[ATTR0]] {3004// SIMD-ONLY2-NEXT:  entry:3005// SIMD-ONLY2-NEXT:    call void @_ZN2SDC1Ev(ptr noundef nonnull align 4 dereferenceable(128) @d1)3006// SIMD-ONLY2-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SDD1Ev, ptr @d1, ptr @__dso_handle) #[[ATTR2]]3007// SIMD-ONLY2-NEXT:    ret void3008//3009//3010// SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2SDC1Ev3011// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(128) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {3012// SIMD-ONLY2-NEXT:  entry:3013// SIMD-ONLY2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 83014// SIMD-ONLY2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 83015// SIMD-ONLY2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 83016// SIMD-ONLY2-NEXT:    call void @_ZN2SDC2Ev(ptr noundef nonnull align 4 dereferenceable(128) [[THIS1]])3017// SIMD-ONLY2-NEXT:    ret void3018//3019//3020// SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2SDD1Ev3021// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(128) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {3022// SIMD-ONLY2-NEXT:  entry:3023// SIMD-ONLY2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 83024// SIMD-ONLY2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 83025// SIMD-ONLY2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 83026// SIMD-ONLY2-NEXT:    call void @_ZN2SDD2Ev(ptr noundef nonnull align 4 dereferenceable(128) [[THIS1]]) #[[ATTR2]]3027// SIMD-ONLY2-NEXT:    ret void3028//3029//3030// SIMD-ONLY2-LABEL: define {{[^@]+}}@__cxx_global_var_init.63031// SIMD-ONLY2-SAME: () #[[ATTR0]] {3032// SIMD-ONLY2-NEXT:  entry:3033// SIMD-ONLY2-NEXT:    call void @_ZN2SEC1Ev(ptr noundef nonnull align 4 dereferenceable(256) @e1)3034// SIMD-ONLY2-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SED1Ev, ptr @e1, ptr @__dso_handle) #[[ATTR2]]3035// SIMD-ONLY2-NEXT:    ret void3036//3037//3038// SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2SEC1Ev3039// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(256) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {3040// SIMD-ONLY2-NEXT:  entry:3041// SIMD-ONLY2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 83042// SIMD-ONLY2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 83043// SIMD-ONLY2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 83044// SIMD-ONLY2-NEXT:    call void @_ZN2SEC2Ev(ptr noundef nonnull align 4 dereferenceable(256) [[THIS1]])3045// SIMD-ONLY2-NEXT:    ret void3046//3047//3048// SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2SED1Ev3049// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(256) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {3050// SIMD-ONLY2-NEXT:  entry:3051// SIMD-ONLY2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 83052// SIMD-ONLY2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 83053// SIMD-ONLY2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 83054// SIMD-ONLY2-NEXT:    call void @_ZN2SED2Ev(ptr noundef nonnull align 4 dereferenceable(256) [[THIS1]]) #[[ATTR2]]3055// SIMD-ONLY2-NEXT:    ret void3056//3057//3058// SIMD-ONLY2-LABEL: define {{[^@]+}}@__cxx_global_var_init.73059// SIMD-ONLY2-SAME: () #[[ATTR0]] {3060// SIMD-ONLY2-NEXT:  entry:3061// SIMD-ONLY2-NEXT:    call void @_ZN2STILi100EEC1Ev(ptr noundef nonnull align 4 dereferenceable(912) @t1)3062// SIMD-ONLY2-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2STILi100EED1Ev, ptr @t1, ptr @__dso_handle) #[[ATTR2]]3063// SIMD-ONLY2-NEXT:    ret void3064//3065//3066// SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2STILi100EEC1Ev3067// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(912) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {3068// SIMD-ONLY2-NEXT:  entry:3069// SIMD-ONLY2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 83070// SIMD-ONLY2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 83071// SIMD-ONLY2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 83072// SIMD-ONLY2-NEXT:    call void @_ZN2STILi100EEC2Ev(ptr noundef nonnull align 4 dereferenceable(912) [[THIS1]])3073// SIMD-ONLY2-NEXT:    ret void3074//3075//3076// SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2STILi100EED1Ev3077// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(912) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {3078// SIMD-ONLY2-NEXT:  entry:3079// SIMD-ONLY2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 83080// SIMD-ONLY2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 83081// SIMD-ONLY2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 83082// SIMD-ONLY2-NEXT:    call void @_ZN2STILi100EED2Ev(ptr noundef nonnull align 4 dereferenceable(912) [[THIS1]]) #[[ATTR2]]3083// SIMD-ONLY2-NEXT:    ret void3084//3085//3086// SIMD-ONLY2-LABEL: define {{[^@]+}}@__cxx_global_var_init.83087// SIMD-ONLY2-SAME: () #[[ATTR0]] {3088// SIMD-ONLY2-NEXT:  entry:3089// SIMD-ONLY2-NEXT:    call void @_ZN2STILi1000EEC1Ev(ptr noundef nonnull align 4 dereferenceable(4512) @t2)3090// SIMD-ONLY2-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2STILi1000EED1Ev, ptr @t2, ptr @__dso_handle) #[[ATTR2]]3091// SIMD-ONLY2-NEXT:    ret void3092//3093//3094// SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2STILi1000EEC1Ev3095// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(4512) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {3096// SIMD-ONLY2-NEXT:  entry:3097// SIMD-ONLY2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 83098// SIMD-ONLY2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 83099// SIMD-ONLY2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 83100// SIMD-ONLY2-NEXT:    call void @_ZN2STILi1000EEC2Ev(ptr noundef nonnull align 4 dereferenceable(4512) [[THIS1]])3101// SIMD-ONLY2-NEXT:    ret void3102//3103//3104// SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2STILi1000EED1Ev3105// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(4512) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {3106// SIMD-ONLY2-NEXT:  entry:3107// SIMD-ONLY2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 83108// SIMD-ONLY2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 83109// SIMD-ONLY2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 83110// SIMD-ONLY2-NEXT:    call void @_ZN2STILi1000EED2Ev(ptr noundef nonnull align 4 dereferenceable(4512) [[THIS1]]) #[[ATTR2]]3111// SIMD-ONLY2-NEXT:    ret void3112//3113//3114// SIMD-ONLY2-LABEL: define {{[^@]+}}@_Z3bari3115// SIMD-ONLY2-SAME: (i32 noundef signext [[A:%.*]]) #[[ATTR1]] {3116// SIMD-ONLY2-NEXT:  entry:3117// SIMD-ONLY2-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 43118// SIMD-ONLY2-NEXT:    [[R:%.*]] = alloca i32, align 43119// SIMD-ONLY2-NEXT:    [[I:%.*]] = alloca i32, align 43120// SIMD-ONLY2-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 43121// SIMD-ONLY2-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 43122// SIMD-ONLY2-NEXT:    store i32 [[TMP0]], ptr [[R]], align 43123// SIMD-ONLY2-NEXT:    call void @_ZN2SA3fooEv(ptr noundef nonnull align 4 dereferenceable(16) @_ZL2a1)3124// SIMD-ONLY2-NEXT:    call void @_ZN2SA3fooEv(ptr noundef nonnull align 4 dereferenceable(16) @a2)3125// SIMD-ONLY2-NEXT:    call void @_ZN2SB3fooEv(ptr noundef nonnull align 4 dereferenceable(32) @b1)3126// SIMD-ONLY2-NEXT:    call void @_ZN2SB3fooEv(ptr noundef nonnull align 4 dereferenceable(32) @b2)3127// SIMD-ONLY2-NEXT:    call void @_ZN2SC3fooEv(ptr noundef nonnull align 4 dereferenceable(64) @_ZL2c1)3128// SIMD-ONLY2-NEXT:    call void @_ZN2SD3fooEv(ptr noundef nonnull align 4 dereferenceable(128) @d1)3129// SIMD-ONLY2-NEXT:    call void @_ZN2SE3fooEv(ptr noundef nonnull align 4 dereferenceable(256) @e1)3130// SIMD-ONLY2-NEXT:    call void @_ZN2STILi100EE3fooEv(ptr noundef nonnull align 4 dereferenceable(912) @t1)3131// SIMD-ONLY2-NEXT:    call void @_ZN2STILi1000EE3fooEv(ptr noundef nonnull align 4 dereferenceable(4512) @t2)3132// SIMD-ONLY2-NEXT:    store i32 0, ptr [[I]], align 43133// SIMD-ONLY2-NEXT:    br label [[FOR_COND:%.*]]3134// SIMD-ONLY2:       for.cond:3135// SIMD-ONLY2-NEXT:    [[TMP1:%.*]] = load i32, ptr [[I]], align 43136// SIMD-ONLY2-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP1]], 103137// SIMD-ONLY2-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]3138// SIMD-ONLY2:       for.body:3139// SIMD-ONLY2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[R]], align 43140// SIMD-ONLY2-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP2]], 13141// SIMD-ONLY2-NEXT:    store i32 [[INC]], ptr [[R]], align 43142// SIMD-ONLY2-NEXT:    br label [[FOR_INC:%.*]]3143// SIMD-ONLY2:       for.inc:3144// SIMD-ONLY2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[I]], align 43145// SIMD-ONLY2-NEXT:    [[INC1:%.*]] = add nsw i32 [[TMP3]], 13146// SIMD-ONLY2-NEXT:    store i32 [[INC1]], ptr [[I]], align 43147// SIMD-ONLY2-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]3148// SIMD-ONLY2:       for.end:3149// SIMD-ONLY2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[R]], align 43150// SIMD-ONLY2-NEXT:    [[TMP5:%.*]] = load ptr, ptr @R, align 83151// SIMD-ONLY2-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 43152// SIMD-ONLY2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP4]], [[TMP6]]3153// SIMD-ONLY2-NEXT:    ret i32 [[ADD]]3154//3155//3156// SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2SA3fooEv3157// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(16) [[THIS:%.*]]) #[[ATTR1]] comdat {3158// SIMD-ONLY2-NEXT:  entry:3159// SIMD-ONLY2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 83160// SIMD-ONLY2-NEXT:    [[A:%.*]] = alloca i32, align 43161// SIMD-ONLY2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 83162// SIMD-ONLY2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 83163// SIMD-ONLY2-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 83164// SIMD-ONLY2-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 43165// SIMD-ONLY2-NEXT:    store i32 [[TMP1]], ptr [[A]], align 43166// SIMD-ONLY2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 43167// SIMD-ONLY2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP2]], 13168// SIMD-ONLY2-NEXT:    store i32 [[ADD]], ptr [[A]], align 43169// SIMD-ONLY2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 43170// SIMD-ONLY2-NEXT:    [[TMP4:%.*]] = load ptr, ptr @R, align 83171// SIMD-ONLY2-NEXT:    store i32 [[TMP3]], ptr [[TMP4]], align 43172// SIMD-ONLY2-NEXT:    ret void3173//3174//3175// SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2SB3fooEv3176// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(32) [[THIS:%.*]]) #[[ATTR1]] comdat {3177// SIMD-ONLY2-NEXT:  entry:3178// SIMD-ONLY2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 83179// SIMD-ONLY2-NEXT:    [[A:%.*]] = alloca i32, align 43180// SIMD-ONLY2-NEXT:    [[I:%.*]] = alloca i32, align 43181// SIMD-ONLY2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 83182// SIMD-ONLY2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 83183// SIMD-ONLY2-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 83184// SIMD-ONLY2-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 43185// SIMD-ONLY2-NEXT:    store i32 [[TMP1]], ptr [[A]], align 43186// SIMD-ONLY2-NEXT:    store i32 0, ptr [[I]], align 43187// SIMD-ONLY2-NEXT:    br label [[FOR_COND:%.*]]3188// SIMD-ONLY2:       for.cond:3189// SIMD-ONLY2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[I]], align 43190// SIMD-ONLY2-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP2]], 103191// SIMD-ONLY2-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]3192// SIMD-ONLY2:       for.body:3193// SIMD-ONLY2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 43194// SIMD-ONLY2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 43195// SIMD-ONLY2-NEXT:    store i32 [[ADD]], ptr [[A]], align 43196// SIMD-ONLY2-NEXT:    br label [[FOR_INC:%.*]]3197// SIMD-ONLY2:       for.inc:3198// SIMD-ONLY2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[I]], align 43199// SIMD-ONLY2-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP4]], 13200// SIMD-ONLY2-NEXT:    store i32 [[INC]], ptr [[I]], align 43201// SIMD-ONLY2-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]3202// SIMD-ONLY2:       for.end:3203// SIMD-ONLY2-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A]], align 43204// SIMD-ONLY2-NEXT:    [[TMP6:%.*]] = load ptr, ptr @R, align 83205// SIMD-ONLY2-NEXT:    store i32 [[TMP5]], ptr [[TMP6]], align 43206// SIMD-ONLY2-NEXT:    ret void3207//3208//3209// SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2SC3fooEv3210// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(64) [[THIS:%.*]]) #[[ATTR1]] comdat {3211// SIMD-ONLY2-NEXT:  entry:3212// SIMD-ONLY2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 83213// SIMD-ONLY2-NEXT:    [[A:%.*]] = alloca i32, align 43214// SIMD-ONLY2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 83215// SIMD-ONLY2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 83216// SIMD-ONLY2-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 83217// SIMD-ONLY2-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 43218// SIMD-ONLY2-NEXT:    store i32 [[TMP1]], ptr [[A]], align 43219// SIMD-ONLY2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 43220// SIMD-ONLY2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP2]], 73221// SIMD-ONLY2-NEXT:    store i32 [[ADD]], ptr [[A]], align 43222// SIMD-ONLY2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 43223// SIMD-ONLY2-NEXT:    [[TMP4:%.*]] = load ptr, ptr @R, align 83224// SIMD-ONLY2-NEXT:    store i32 [[TMP3]], ptr [[TMP4]], align 43225// SIMD-ONLY2-NEXT:    ret void3226//3227//3228// SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2SD3fooEv3229// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(128) [[THIS:%.*]]) #[[ATTR1]] comdat {3230// SIMD-ONLY2-NEXT:  entry:3231// SIMD-ONLY2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 83232// SIMD-ONLY2-NEXT:    [[A:%.*]] = alloca i32, align 43233// SIMD-ONLY2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 83234// SIMD-ONLY2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 83235// SIMD-ONLY2-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 83236// SIMD-ONLY2-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 43237// SIMD-ONLY2-NEXT:    store i32 [[TMP1]], ptr [[A]], align 43238// SIMD-ONLY2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 43239// SIMD-ONLY2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP2]], 103240// SIMD-ONLY2-NEXT:    store i32 [[ADD]], ptr [[A]], align 43241// SIMD-ONLY2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 43242// SIMD-ONLY2-NEXT:    [[TMP4:%.*]] = load ptr, ptr @R, align 83243// SIMD-ONLY2-NEXT:    store i32 [[TMP3]], ptr [[TMP4]], align 43244// SIMD-ONLY2-NEXT:    ret void3245//3246//3247// SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2SE3fooEv3248// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(256) [[THIS:%.*]]) #[[ATTR1]] comdat {3249// SIMD-ONLY2-NEXT:  entry:3250// SIMD-ONLY2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 83251// SIMD-ONLY2-NEXT:    [[A:%.*]] = alloca i32, align 43252// SIMD-ONLY2-NEXT:    [[I:%.*]] = alloca i32, align 43253// SIMD-ONLY2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 83254// SIMD-ONLY2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 83255// SIMD-ONLY2-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 83256// SIMD-ONLY2-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 43257// SIMD-ONLY2-NEXT:    store i32 [[TMP1]], ptr [[A]], align 43258// SIMD-ONLY2-NEXT:    store i32 0, ptr [[I]], align 43259// SIMD-ONLY2-NEXT:    br label [[FOR_COND:%.*]]3260// SIMD-ONLY2:       for.cond:3261// SIMD-ONLY2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[I]], align 43262// SIMD-ONLY2-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP2]], 103263// SIMD-ONLY2-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]3264// SIMD-ONLY2:       for.body:3265// SIMD-ONLY2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 43266// SIMD-ONLY2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 133267// SIMD-ONLY2-NEXT:    store i32 [[ADD]], ptr [[A]], align 43268// SIMD-ONLY2-NEXT:    br label [[FOR_INC:%.*]]3269// SIMD-ONLY2:       for.inc:3270// SIMD-ONLY2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[I]], align 43271// SIMD-ONLY2-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP4]], 13272// SIMD-ONLY2-NEXT:    store i32 [[INC]], ptr [[I]], align 43273// SIMD-ONLY2-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]3274// SIMD-ONLY2:       for.end:3275// SIMD-ONLY2-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A]], align 43276// SIMD-ONLY2-NEXT:    [[TMP6:%.*]] = load ptr, ptr @R, align 83277// SIMD-ONLY2-NEXT:    store i32 [[TMP5]], ptr [[TMP6]], align 43278// SIMD-ONLY2-NEXT:    ret void3279//3280//3281// SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2STILi100EE3fooEv3282// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(912) [[THIS:%.*]]) #[[ATTR1]] comdat {3283// SIMD-ONLY2-NEXT:  entry:3284// SIMD-ONLY2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 83285// SIMD-ONLY2-NEXT:    [[A:%.*]] = alloca i32, align 43286// SIMD-ONLY2-NEXT:    [[I:%.*]] = alloca i32, align 43287// SIMD-ONLY2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 83288// SIMD-ONLY2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 83289// SIMD-ONLY2-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 83290// SIMD-ONLY2-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 43291// SIMD-ONLY2-NEXT:    store i32 [[TMP1]], ptr [[A]], align 43292// SIMD-ONLY2-NEXT:    store i32 0, ptr [[I]], align 43293// SIMD-ONLY2-NEXT:    br label [[FOR_COND:%.*]]3294// SIMD-ONLY2:       for.cond:3295// SIMD-ONLY2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[I]], align 43296// SIMD-ONLY2-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP2]], 103297// SIMD-ONLY2-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]3298// SIMD-ONLY2:       for.body:3299// SIMD-ONLY2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 43300// SIMD-ONLY2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1163301// SIMD-ONLY2-NEXT:    store i32 [[ADD]], ptr [[A]], align 43302// SIMD-ONLY2-NEXT:    br label [[FOR_INC:%.*]]3303// SIMD-ONLY2:       for.inc:3304// SIMD-ONLY2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[I]], align 43305// SIMD-ONLY2-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP4]], 13306// SIMD-ONLY2-NEXT:    store i32 [[INC]], ptr [[I]], align 43307// SIMD-ONLY2-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]3308// SIMD-ONLY2:       for.end:3309// SIMD-ONLY2-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A]], align 43310// SIMD-ONLY2-NEXT:    [[TMP6:%.*]] = load ptr, ptr @R, align 83311// SIMD-ONLY2-NEXT:    store i32 [[TMP5]], ptr [[TMP6]], align 43312// SIMD-ONLY2-NEXT:    ret void3313//3314//3315// SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2STILi1000EE3fooEv3316// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(4512) [[THIS:%.*]]) #[[ATTR1]] comdat {3317// SIMD-ONLY2-NEXT:  entry:3318// SIMD-ONLY2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 83319// SIMD-ONLY2-NEXT:    [[A:%.*]] = alloca i32, align 43320// SIMD-ONLY2-NEXT:    [[I:%.*]] = alloca i32, align 43321// SIMD-ONLY2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 83322// SIMD-ONLY2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 83323// SIMD-ONLY2-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 83324// SIMD-ONLY2-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 43325// SIMD-ONLY2-NEXT:    store i32 [[TMP1]], ptr [[A]], align 43326// SIMD-ONLY2-NEXT:    store i32 0, ptr [[I]], align 43327// SIMD-ONLY2-NEXT:    br label [[FOR_COND:%.*]]3328// SIMD-ONLY2:       for.cond:3329// SIMD-ONLY2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[I]], align 43330// SIMD-ONLY2-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP2]], 103331// SIMD-ONLY2-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]3332// SIMD-ONLY2:       for.body:3333// SIMD-ONLY2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 43334// SIMD-ONLY2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 10163335// SIMD-ONLY2-NEXT:    store i32 [[ADD]], ptr [[A]], align 43336// SIMD-ONLY2-NEXT:    br label [[FOR_INC:%.*]]3337// SIMD-ONLY2:       for.inc:3338// SIMD-ONLY2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[I]], align 43339// SIMD-ONLY2-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP4]], 13340// SIMD-ONLY2-NEXT:    store i32 [[INC]], ptr [[I]], align 43341// SIMD-ONLY2-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]3342// SIMD-ONLY2:       for.end:3343// SIMD-ONLY2-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A]], align 43344// SIMD-ONLY2-NEXT:    [[TMP6:%.*]] = load ptr, ptr @R, align 83345// SIMD-ONLY2-NEXT:    store i32 [[TMP5]], ptr [[TMP6]], align 43346// SIMD-ONLY2-NEXT:    ret void3347//3348//3349// SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2SAC2Ev3350// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {3351// SIMD-ONLY2-NEXT:  entry:3352// SIMD-ONLY2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 83353// SIMD-ONLY2-NEXT:    [[A:%.*]] = alloca i32, align 43354// SIMD-ONLY2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 83355// SIMD-ONLY2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 83356// SIMD-ONLY2-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 83357// SIMD-ONLY2-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 43358// SIMD-ONLY2-NEXT:    store i32 [[TMP1]], ptr [[A]], align 43359// SIMD-ONLY2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 43360// SIMD-ONLY2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP2]], 23361// SIMD-ONLY2-NEXT:    store i32 [[ADD]], ptr [[A]], align 43362// SIMD-ONLY2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 43363// SIMD-ONLY2-NEXT:    [[TMP4:%.*]] = load ptr, ptr @R, align 83364// SIMD-ONLY2-NEXT:    store i32 [[TMP3]], ptr [[TMP4]], align 43365// SIMD-ONLY2-NEXT:    ret void3366//3367//3368// SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2SAD2Ev3369// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {3370// SIMD-ONLY2-NEXT:  entry:3371// SIMD-ONLY2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 83372// SIMD-ONLY2-NEXT:    [[A:%.*]] = alloca i32, align 43373// SIMD-ONLY2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 83374// SIMD-ONLY2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 83375// SIMD-ONLY2-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 83376// SIMD-ONLY2-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 43377// SIMD-ONLY2-NEXT:    store i32 [[TMP1]], ptr [[A]], align 43378// SIMD-ONLY2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 43379// SIMD-ONLY2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP2]], 33380// SIMD-ONLY2-NEXT:    store i32 [[ADD]], ptr [[A]], align 43381// SIMD-ONLY2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 43382// SIMD-ONLY2-NEXT:    [[TMP4:%.*]] = load ptr, ptr @R, align 83383// SIMD-ONLY2-NEXT:    store i32 [[TMP3]], ptr [[TMP4]], align 43384// SIMD-ONLY2-NEXT:    ret void3385//3386//3387// SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2SBC2Ev3388// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(32) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {3389// SIMD-ONLY2-NEXT:  entry:3390// SIMD-ONLY2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 83391// SIMD-ONLY2-NEXT:    [[A:%.*]] = alloca i32, align 43392// SIMD-ONLY2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 83393// SIMD-ONLY2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 83394// SIMD-ONLY2-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 83395// SIMD-ONLY2-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 43396// SIMD-ONLY2-NEXT:    store i32 [[TMP1]], ptr [[A]], align 43397// SIMD-ONLY2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 43398// SIMD-ONLY2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP2]], 53399// SIMD-ONLY2-NEXT:    store i32 [[ADD]], ptr [[A]], align 43400// SIMD-ONLY2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 43401// SIMD-ONLY2-NEXT:    [[TMP4:%.*]] = load ptr, ptr @R, align 83402// SIMD-ONLY2-NEXT:    store i32 [[TMP3]], ptr [[TMP4]], align 43403// SIMD-ONLY2-NEXT:    ret void3404//3405//3406// SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2SBD2Ev3407// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(32) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {3408// SIMD-ONLY2-NEXT:  entry:3409// SIMD-ONLY2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 83410// SIMD-ONLY2-NEXT:    [[A:%.*]] = alloca i32, align 43411// SIMD-ONLY2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 83412// SIMD-ONLY2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 83413// SIMD-ONLY2-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 83414// SIMD-ONLY2-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 43415// SIMD-ONLY2-NEXT:    store i32 [[TMP1]], ptr [[A]], align 43416// SIMD-ONLY2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 43417// SIMD-ONLY2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP2]], 63418// SIMD-ONLY2-NEXT:    store i32 [[ADD]], ptr [[A]], align 43419// SIMD-ONLY2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 43420// SIMD-ONLY2-NEXT:    [[TMP4:%.*]] = load ptr, ptr @R, align 83421// SIMD-ONLY2-NEXT:    store i32 [[TMP3]], ptr [[TMP4]], align 43422// SIMD-ONLY2-NEXT:    ret void3423//3424//3425// SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2SCC2Ev3426// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(64) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {3427// SIMD-ONLY2-NEXT:  entry:3428// SIMD-ONLY2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 83429// SIMD-ONLY2-NEXT:    [[A:%.*]] = alloca i32, align 43430// SIMD-ONLY2-NEXT:    [[I:%.*]] = alloca i32, align 43431// SIMD-ONLY2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 83432// SIMD-ONLY2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 83433// SIMD-ONLY2-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 83434// SIMD-ONLY2-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 43435// SIMD-ONLY2-NEXT:    store i32 [[TMP1]], ptr [[A]], align 43436// SIMD-ONLY2-NEXT:    store i32 0, ptr [[I]], align 43437// SIMD-ONLY2-NEXT:    br label [[FOR_COND:%.*]]3438// SIMD-ONLY2:       for.cond:3439// SIMD-ONLY2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[I]], align 43440// SIMD-ONLY2-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP2]], 103441// SIMD-ONLY2-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]3442// SIMD-ONLY2:       for.body:3443// SIMD-ONLY2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 43444// SIMD-ONLY2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 83445// SIMD-ONLY2-NEXT:    store i32 [[ADD]], ptr [[A]], align 43446// SIMD-ONLY2-NEXT:    br label [[FOR_INC:%.*]]3447// SIMD-ONLY2:       for.inc:3448// SIMD-ONLY2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[I]], align 43449// SIMD-ONLY2-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP4]], 13450// SIMD-ONLY2-NEXT:    store i32 [[INC]], ptr [[I]], align 43451// SIMD-ONLY2-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]3452// SIMD-ONLY2:       for.end:3453// SIMD-ONLY2-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A]], align 43454// SIMD-ONLY2-NEXT:    [[TMP6:%.*]] = load ptr, ptr @R, align 83455// SIMD-ONLY2-NEXT:    store i32 [[TMP5]], ptr [[TMP6]], align 43456// SIMD-ONLY2-NEXT:    ret void3457//3458//3459// SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2SCD2Ev3460// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(64) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {3461// SIMD-ONLY2-NEXT:  entry:3462// SIMD-ONLY2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 83463// SIMD-ONLY2-NEXT:    [[A:%.*]] = alloca i32, align 43464// SIMD-ONLY2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 83465// SIMD-ONLY2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 83466// SIMD-ONLY2-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 83467// SIMD-ONLY2-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 43468// SIMD-ONLY2-NEXT:    store i32 [[TMP1]], ptr [[A]], align 43469// SIMD-ONLY2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 43470// SIMD-ONLY2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP2]], 93471// SIMD-ONLY2-NEXT:    store i32 [[ADD]], ptr [[A]], align 43472// SIMD-ONLY2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 43473// SIMD-ONLY2-NEXT:    [[TMP4:%.*]] = load ptr, ptr @R, align 83474// SIMD-ONLY2-NEXT:    store i32 [[TMP3]], ptr [[TMP4]], align 43475// SIMD-ONLY2-NEXT:    ret void3476//3477//3478// SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2SDC2Ev3479// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(128) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {3480// SIMD-ONLY2-NEXT:  entry:3481// SIMD-ONLY2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 83482// SIMD-ONLY2-NEXT:    [[A:%.*]] = alloca i32, align 43483// SIMD-ONLY2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 83484// SIMD-ONLY2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 83485// SIMD-ONLY2-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 83486// SIMD-ONLY2-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 43487// SIMD-ONLY2-NEXT:    store i32 [[TMP1]], ptr [[A]], align 43488// SIMD-ONLY2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 43489// SIMD-ONLY2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP2]], 113490// SIMD-ONLY2-NEXT:    store i32 [[ADD]], ptr [[A]], align 43491// SIMD-ONLY2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 43492// SIMD-ONLY2-NEXT:    [[TMP4:%.*]] = load ptr, ptr @R, align 83493// SIMD-ONLY2-NEXT:    store i32 [[TMP3]], ptr [[TMP4]], align 43494// SIMD-ONLY2-NEXT:    ret void3495//3496//3497// SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2SDD2Ev3498// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(128) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {3499// SIMD-ONLY2-NEXT:  entry:3500// SIMD-ONLY2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 83501// SIMD-ONLY2-NEXT:    [[A:%.*]] = alloca i32, align 43502// SIMD-ONLY2-NEXT:    [[I:%.*]] = alloca i32, align 43503// SIMD-ONLY2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 83504// SIMD-ONLY2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 83505// SIMD-ONLY2-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 83506// SIMD-ONLY2-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 43507// SIMD-ONLY2-NEXT:    store i32 [[TMP1]], ptr [[A]], align 43508// SIMD-ONLY2-NEXT:    store i32 0, ptr [[I]], align 43509// SIMD-ONLY2-NEXT:    br label [[FOR_COND:%.*]]3510// SIMD-ONLY2:       for.cond:3511// SIMD-ONLY2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[I]], align 43512// SIMD-ONLY2-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP2]], 103513// SIMD-ONLY2-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]3514// SIMD-ONLY2:       for.body:3515// SIMD-ONLY2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 43516// SIMD-ONLY2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 123517// SIMD-ONLY2-NEXT:    store i32 [[ADD]], ptr [[A]], align 43518// SIMD-ONLY2-NEXT:    br label [[FOR_INC:%.*]]3519// SIMD-ONLY2:       for.inc:3520// SIMD-ONLY2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[I]], align 43521// SIMD-ONLY2-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP4]], 13522// SIMD-ONLY2-NEXT:    store i32 [[INC]], ptr [[I]], align 43523// SIMD-ONLY2-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]3524// SIMD-ONLY2:       for.end:3525// SIMD-ONLY2-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A]], align 43526// SIMD-ONLY2-NEXT:    [[TMP6:%.*]] = load ptr, ptr @R, align 83527// SIMD-ONLY2-NEXT:    store i32 [[TMP5]], ptr [[TMP6]], align 43528// SIMD-ONLY2-NEXT:    ret void3529//3530//3531// SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2SEC2Ev3532// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(256) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {3533// SIMD-ONLY2-NEXT:  entry:3534// SIMD-ONLY2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 83535// SIMD-ONLY2-NEXT:    [[A:%.*]] = alloca i32, align 43536// SIMD-ONLY2-NEXT:    [[I:%.*]] = alloca i32, align 43537// SIMD-ONLY2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 83538// SIMD-ONLY2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 83539// SIMD-ONLY2-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 83540// SIMD-ONLY2-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 43541// SIMD-ONLY2-NEXT:    store i32 [[TMP1]], ptr [[A]], align 43542// SIMD-ONLY2-NEXT:    store i32 0, ptr [[I]], align 43543// SIMD-ONLY2-NEXT:    br label [[FOR_COND:%.*]]3544// SIMD-ONLY2:       for.cond:3545// SIMD-ONLY2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[I]], align 43546// SIMD-ONLY2-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP2]], 103547// SIMD-ONLY2-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]3548// SIMD-ONLY2:       for.body:3549// SIMD-ONLY2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 43550// SIMD-ONLY2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 143551// SIMD-ONLY2-NEXT:    store i32 [[ADD]], ptr [[A]], align 43552// SIMD-ONLY2-NEXT:    br label [[FOR_INC:%.*]]3553// SIMD-ONLY2:       for.inc:3554// SIMD-ONLY2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[I]], align 43555// SIMD-ONLY2-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP4]], 13556// SIMD-ONLY2-NEXT:    store i32 [[INC]], ptr [[I]], align 43557// SIMD-ONLY2-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]3558// SIMD-ONLY2:       for.end:3559// SIMD-ONLY2-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A]], align 43560// SIMD-ONLY2-NEXT:    [[TMP6:%.*]] = load ptr, ptr @R, align 83561// SIMD-ONLY2-NEXT:    store i32 [[TMP5]], ptr [[TMP6]], align 43562// SIMD-ONLY2-NEXT:    ret void3563//3564//3565// SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2SED2Ev3566// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(256) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {3567// SIMD-ONLY2-NEXT:  entry:3568// SIMD-ONLY2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 83569// SIMD-ONLY2-NEXT:    [[A:%.*]] = alloca i32, align 43570// SIMD-ONLY2-NEXT:    [[I:%.*]] = alloca i32, align 43571// SIMD-ONLY2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 83572// SIMD-ONLY2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 83573// SIMD-ONLY2-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 83574// SIMD-ONLY2-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 43575// SIMD-ONLY2-NEXT:    store i32 [[TMP1]], ptr [[A]], align 43576// SIMD-ONLY2-NEXT:    store i32 0, ptr [[I]], align 43577// SIMD-ONLY2-NEXT:    br label [[FOR_COND:%.*]]3578// SIMD-ONLY2:       for.cond:3579// SIMD-ONLY2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[I]], align 43580// SIMD-ONLY2-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP2]], 103581// SIMD-ONLY2-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]3582// SIMD-ONLY2:       for.body:3583// SIMD-ONLY2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 43584// SIMD-ONLY2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 153585// SIMD-ONLY2-NEXT:    store i32 [[ADD]], ptr [[A]], align 43586// SIMD-ONLY2-NEXT:    br label [[FOR_INC:%.*]]3587// SIMD-ONLY2:       for.inc:3588// SIMD-ONLY2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[I]], align 43589// SIMD-ONLY2-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP4]], 13590// SIMD-ONLY2-NEXT:    store i32 [[INC]], ptr [[I]], align 43591// SIMD-ONLY2-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]3592// SIMD-ONLY2:       for.end:3593// SIMD-ONLY2-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A]], align 43594// SIMD-ONLY2-NEXT:    [[TMP6:%.*]] = load ptr, ptr @R, align 83595// SIMD-ONLY2-NEXT:    store i32 [[TMP5]], ptr [[TMP6]], align 43596// SIMD-ONLY2-NEXT:    ret void3597//3598//3599// SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2STILi100EEC2Ev3600// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(912) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {3601// SIMD-ONLY2-NEXT:  entry:3602// SIMD-ONLY2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 83603// SIMD-ONLY2-NEXT:    [[A:%.*]] = alloca i32, align 43604// SIMD-ONLY2-NEXT:    [[I:%.*]] = alloca i32, align 43605// SIMD-ONLY2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 83606// SIMD-ONLY2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 83607// SIMD-ONLY2-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 83608// SIMD-ONLY2-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 43609// SIMD-ONLY2-NEXT:    store i32 [[TMP1]], ptr [[A]], align 43610// SIMD-ONLY2-NEXT:    store i32 0, ptr [[I]], align 43611// SIMD-ONLY2-NEXT:    br label [[FOR_COND:%.*]]3612// SIMD-ONLY2:       for.cond:3613// SIMD-ONLY2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[I]], align 43614// SIMD-ONLY2-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP2]], 103615// SIMD-ONLY2-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]3616// SIMD-ONLY2:       for.body:3617// SIMD-ONLY2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 43618// SIMD-ONLY2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1173619// SIMD-ONLY2-NEXT:    store i32 [[ADD]], ptr [[A]], align 43620// SIMD-ONLY2-NEXT:    br label [[FOR_INC:%.*]]3621// SIMD-ONLY2:       for.inc:3622// SIMD-ONLY2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[I]], align 43623// SIMD-ONLY2-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP4]], 13624// SIMD-ONLY2-NEXT:    store i32 [[INC]], ptr [[I]], align 43625// SIMD-ONLY2-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]3626// SIMD-ONLY2:       for.end:3627// SIMD-ONLY2-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A]], align 43628// SIMD-ONLY2-NEXT:    [[TMP6:%.*]] = load ptr, ptr @R, align 83629// SIMD-ONLY2-NEXT:    store i32 [[TMP5]], ptr [[TMP6]], align 43630// SIMD-ONLY2-NEXT:    ret void3631//3632//3633// SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2STILi100EED2Ev3634// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(912) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {3635// SIMD-ONLY2-NEXT:  entry:3636// SIMD-ONLY2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 83637// SIMD-ONLY2-NEXT:    [[A:%.*]] = alloca i32, align 43638// SIMD-ONLY2-NEXT:    [[I:%.*]] = alloca i32, align 43639// SIMD-ONLY2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 83640// SIMD-ONLY2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 83641// SIMD-ONLY2-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 83642// SIMD-ONLY2-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 43643// SIMD-ONLY2-NEXT:    store i32 [[TMP1]], ptr [[A]], align 43644// SIMD-ONLY2-NEXT:    store i32 0, ptr [[I]], align 43645// SIMD-ONLY2-NEXT:    br label [[FOR_COND:%.*]]3646// SIMD-ONLY2:       for.cond:3647// SIMD-ONLY2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[I]], align 43648// SIMD-ONLY2-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP2]], 103649// SIMD-ONLY2-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]3650// SIMD-ONLY2:       for.body:3651// SIMD-ONLY2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 43652// SIMD-ONLY2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1183653// SIMD-ONLY2-NEXT:    store i32 [[ADD]], ptr [[A]], align 43654// SIMD-ONLY2-NEXT:    br label [[FOR_INC:%.*]]3655// SIMD-ONLY2:       for.inc:3656// SIMD-ONLY2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[I]], align 43657// SIMD-ONLY2-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP4]], 13658// SIMD-ONLY2-NEXT:    store i32 [[INC]], ptr [[I]], align 43659// SIMD-ONLY2-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]3660// SIMD-ONLY2:       for.end:3661// SIMD-ONLY2-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A]], align 43662// SIMD-ONLY2-NEXT:    [[TMP6:%.*]] = load ptr, ptr @R, align 83663// SIMD-ONLY2-NEXT:    store i32 [[TMP5]], ptr [[TMP6]], align 43664// SIMD-ONLY2-NEXT:    ret void3665//3666//3667// SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2STILi1000EEC2Ev3668// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(4512) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {3669// SIMD-ONLY2-NEXT:  entry:3670// SIMD-ONLY2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 83671// SIMD-ONLY2-NEXT:    [[A:%.*]] = alloca i32, align 43672// SIMD-ONLY2-NEXT:    [[I:%.*]] = alloca i32, align 43673// SIMD-ONLY2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 83674// SIMD-ONLY2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 83675// SIMD-ONLY2-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 83676// SIMD-ONLY2-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 43677// SIMD-ONLY2-NEXT:    store i32 [[TMP1]], ptr [[A]], align 43678// SIMD-ONLY2-NEXT:    store i32 0, ptr [[I]], align 43679// SIMD-ONLY2-NEXT:    br label [[FOR_COND:%.*]]3680// SIMD-ONLY2:       for.cond:3681// SIMD-ONLY2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[I]], align 43682// SIMD-ONLY2-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP2]], 103683// SIMD-ONLY2-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]3684// SIMD-ONLY2:       for.body:3685// SIMD-ONLY2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 43686// SIMD-ONLY2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 10173687// SIMD-ONLY2-NEXT:    store i32 [[ADD]], ptr [[A]], align 43688// SIMD-ONLY2-NEXT:    br label [[FOR_INC:%.*]]3689// SIMD-ONLY2:       for.inc:3690// SIMD-ONLY2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[I]], align 43691// SIMD-ONLY2-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP4]], 13692// SIMD-ONLY2-NEXT:    store i32 [[INC]], ptr [[I]], align 43693// SIMD-ONLY2-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]3694// SIMD-ONLY2:       for.end:3695// SIMD-ONLY2-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A]], align 43696// SIMD-ONLY2-NEXT:    [[TMP6:%.*]] = load ptr, ptr @R, align 83697// SIMD-ONLY2-NEXT:    store i32 [[TMP5]], ptr [[TMP6]], align 43698// SIMD-ONLY2-NEXT:    ret void3699//3700//3701// SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2STILi1000EED2Ev3702// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(4512) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {3703// SIMD-ONLY2-NEXT:  entry:3704// SIMD-ONLY2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 83705// SIMD-ONLY2-NEXT:    [[A:%.*]] = alloca i32, align 43706// SIMD-ONLY2-NEXT:    [[I:%.*]] = alloca i32, align 43707// SIMD-ONLY2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 83708// SIMD-ONLY2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 83709// SIMD-ONLY2-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 83710// SIMD-ONLY2-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 43711// SIMD-ONLY2-NEXT:    store i32 [[TMP1]], ptr [[A]], align 43712// SIMD-ONLY2-NEXT:    store i32 0, ptr [[I]], align 43713// SIMD-ONLY2-NEXT:    br label [[FOR_COND:%.*]]3714// SIMD-ONLY2:       for.cond:3715// SIMD-ONLY2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[I]], align 43716// SIMD-ONLY2-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP2]], 103717// SIMD-ONLY2-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]3718// SIMD-ONLY2:       for.body:3719// SIMD-ONLY2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 43720// SIMD-ONLY2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 10183721// SIMD-ONLY2-NEXT:    store i32 [[ADD]], ptr [[A]], align 43722// SIMD-ONLY2-NEXT:    br label [[FOR_INC:%.*]]3723// SIMD-ONLY2:       for.inc:3724// SIMD-ONLY2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[I]], align 43725// SIMD-ONLY2-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP4]], 13726// SIMD-ONLY2-NEXT:    store i32 [[INC]], ptr [[I]], align 43727// SIMD-ONLY2-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]3728// SIMD-ONLY2:       for.end:3729// SIMD-ONLY2-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A]], align 43730// SIMD-ONLY2-NEXT:    [[TMP6:%.*]] = load ptr, ptr @R, align 83731// SIMD-ONLY2-NEXT:    store i32 [[TMP5]], ptr [[TMP6]], align 43732// SIMD-ONLY2-NEXT:    ret void3733//3734//3735// SIMD-ONLY2-LABEL: define {{[^@]+}}@_GLOBAL__I_0005003736// SIMD-ONLY2-SAME: () #[[ATTR0]] {3737// SIMD-ONLY2-NEXT:  entry:3738// SIMD-ONLY2-NEXT:    call void @__cxx_global_var_init()3739// SIMD-ONLY2-NEXT:    call void @__cxx_global_var_init.2()3740// SIMD-ONLY2-NEXT:    ret void3741//3742//3743// SIMD-ONLY2-LABEL: define {{[^@]+}}@_GLOBAL__I_0005013744// SIMD-ONLY2-SAME: () #[[ATTR0]] {3745// SIMD-ONLY2-NEXT:  entry:3746// SIMD-ONLY2-NEXT:    call void @__cxx_global_var_init.3()3747// SIMD-ONLY2-NEXT:    ret void3748//3749//3750// SIMD-ONLY2-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_parallel_generic_loop_codegen_1.cpp3751// SIMD-ONLY2-SAME: () #[[ATTR0]] {3752// SIMD-ONLY2-NEXT:  entry:3753// SIMD-ONLY2-NEXT:    call void @__cxx_global_var_init.1()3754// SIMD-ONLY2-NEXT:    call void @__cxx_global_var_init.4()3755// SIMD-ONLY2-NEXT:    call void @__cxx_global_var_init.5()3756// SIMD-ONLY2-NEXT:    call void @__cxx_global_var_init.6()3757// SIMD-ONLY2-NEXT:    call void @__cxx_global_var_init.7()3758// SIMD-ONLY2-NEXT:    call void @__cxx_global_var_init.8()3759// SIMD-ONLY2-NEXT:    ret void3760//3761//3762// OMP-DEFAULT-LABEL: define {{[^@]+}}@__cxx_global_var_init3763// OMP-DEFAULT-SAME: () #[[ATTR0:[0-9]+]] {3764// OMP-DEFAULT-NEXT:  entry:3765// OMP-DEFAULT-NEXT:    call void @_ZN2SAC1Ev(ptr noundef nonnull align 4 dereferenceable(16) @_ZL2a1)3766// OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SAD1Ev, ptr @_ZL2a1, ptr @__dso_handle) #[[ATTR2:[0-9]+]]3767// OMP-DEFAULT-NEXT:    ret void3768//3769//3770//3771//3772//3773//3774// OMP-DEFAULT-LABEL: define {{[^@]+}}@__cxx_global_var_init.13775// OMP-DEFAULT-SAME: () #[[ATTR0]] {3776// OMP-DEFAULT-NEXT:  entry:3777// OMP-DEFAULT-NEXT:    call void @_ZN2SAC1Ev(ptr noundef nonnull align 4 dereferenceable(16) @a2)3778// OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SAD1Ev, ptr @a2, ptr @__dso_handle) #[[ATTR2]]3779// OMP-DEFAULT-NEXT:    ret void3780//3781//3782// OMP-DEFAULT-LABEL: define {{[^@]+}}@__cxx_global_var_init.23783// OMP-DEFAULT-SAME: () #[[ATTR0]] {3784// OMP-DEFAULT-NEXT:  entry:3785// OMP-DEFAULT-NEXT:    call void @_ZN2SBC1Ev(ptr noundef nonnull align 4 dereferenceable(32) @b1)3786// OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SBD1Ev, ptr @b1, ptr @__dso_handle) #[[ATTR2]]3787// OMP-DEFAULT-NEXT:    ret void3788//3789//3790//3791//3792//3793//3794// OMP-DEFAULT-LABEL: define {{[^@]+}}@__cxx_global_var_init.33795// OMP-DEFAULT-SAME: () #[[ATTR0]] {3796// OMP-DEFAULT-NEXT:  entry:3797// OMP-DEFAULT-NEXT:    call void @_ZN2SBC1Ev(ptr noundef nonnull align 4 dereferenceable(32) @b2)3798// OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SBD1Ev, ptr @b2, ptr @__dso_handle) #[[ATTR2]]3799// OMP-DEFAULT-NEXT:    ret void3800//3801//3802// OMP-DEFAULT-LABEL: define {{[^@]+}}@__cxx_global_var_init.43803// OMP-DEFAULT-SAME: () #[[ATTR0]] {3804// OMP-DEFAULT-NEXT:  entry:3805// OMP-DEFAULT-NEXT:    call void @_ZN2SCC1Ev(ptr noundef nonnull align 4 dereferenceable(64) @_ZL2c1)3806// OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SCD1Ev, ptr @_ZL2c1, ptr @__dso_handle) #[[ATTR2]]3807// OMP-DEFAULT-NEXT:    ret void3808//3809//3810//3811//3812//3813//3814//3815//3816// OMP-DEFAULT-LABEL: define {{[^@]+}}@__cxx_global_var_init.53817// OMP-DEFAULT-SAME: () #[[ATTR0]] {3818// OMP-DEFAULT-NEXT:  entry:3819// OMP-DEFAULT-NEXT:    call void @_ZN2SDC1Ev(ptr noundef nonnull align 4 dereferenceable(128) @d1)3820// OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SDD1Ev, ptr @d1, ptr @__dso_handle) #[[ATTR2]]3821// OMP-DEFAULT-NEXT:    ret void3822//3823//3824//3825//3826//3827//3828//3829//3830// OMP-DEFAULT-LABEL: define {{[^@]+}}@__cxx_global_var_init.83831// OMP-DEFAULT-SAME: () #[[ATTR0]] {3832// OMP-DEFAULT-NEXT:  entry:3833// OMP-DEFAULT-NEXT:    call void @_ZN2SEC1Ev(ptr noundef nonnull align 4 dereferenceable(256) @e1)3834// OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SED1Ev, ptr @e1, ptr @__dso_handle) #[[ATTR2]]3835// OMP-DEFAULT-NEXT:    ret void3836//3837//3838//3839//3840//3841//3842//3843//3844//3845//3846// OMP-DEFAULT-LABEL: define {{[^@]+}}@__cxx_global_var_init.133847// OMP-DEFAULT-SAME: () #[[ATTR0]] {3848// OMP-DEFAULT-NEXT:  entry:3849// OMP-DEFAULT-NEXT:    call void @_ZN2STILi100EEC1Ev(ptr noundef nonnull align 4 dereferenceable(912) @t1)3850// OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2STILi100EED1Ev, ptr @t1, ptr @__dso_handle) #[[ATTR2]]3851// OMP-DEFAULT-NEXT:    ret void3852//3853//3854//3855//3856//3857//3858//3859//3860//3861//3862// OMP-DEFAULT-LABEL: define {{[^@]+}}@__cxx_global_var_init.183863// OMP-DEFAULT-SAME: () #[[ATTR0]] {3864// OMP-DEFAULT-NEXT:  entry:3865// OMP-DEFAULT-NEXT:    call void @_ZN2STILi1000EEC1Ev(ptr noundef nonnull align 4 dereferenceable(4512) @t2)3866// OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2STILi1000EED1Ev, ptr @t2, ptr @__dso_handle) #[[ATTR2]]3867// OMP-DEFAULT-NEXT:    ret void3868//3869//3870//3871//3872//3873//3874//3875//3876//3877//3878//3879//3880//3881//3882//3883//3884//3885//3886//3887//3888//3889//3890//3891//3892//3893//3894//3895//3896// OMP-DEFAULT-LABEL: define {{[^@]+}}@_GLOBAL__I_0005003897// OMP-DEFAULT-SAME: () #[[ATTR0]] {3898// OMP-DEFAULT-NEXT:  entry:3899// OMP-DEFAULT-NEXT:    call void @__cxx_global_var_init()3900// OMP-DEFAULT-NEXT:    call void @__cxx_global_var_init.2()3901// OMP-DEFAULT-NEXT:    ret void3902//3903//3904// OMP-DEFAULT-LABEL: define {{[^@]+}}@_GLOBAL__I_0005013905// OMP-DEFAULT-SAME: () #[[ATTR0]] {3906// OMP-DEFAULT-NEXT:  entry:3907// OMP-DEFAULT-NEXT:    call void @__cxx_global_var_init.3()3908// OMP-DEFAULT-NEXT:    ret void3909//3910//3911// OMP-DEFAULT-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_parallel_generic_loop_codegen_1.cpp3912// OMP-DEFAULT-SAME: () #[[ATTR0]] {3913// OMP-DEFAULT-NEXT:  entry:3914// OMP-DEFAULT-NEXT:    call void @__cxx_global_var_init.1()3915// OMP-DEFAULT-NEXT:    call void @__cxx_global_var_init.4()3916// OMP-DEFAULT-NEXT:    call void @__cxx_global_var_init.5()3917// OMP-DEFAULT-NEXT:    call void @__cxx_global_var_init.8()3918// OMP-DEFAULT-NEXT:    call void @__cxx_global_var_init.13()3919// OMP-DEFAULT-NEXT:    call void @__cxx_global_var_init.18()3920// OMP-DEFAULT-NEXT:    ret void3921//3922//3923//3924//3925//3926//3927//3928//3929//3930//3931//3932//3933//3934//3935//3936//3937//3938//3939//3940//3941//3942//3943//3944//3945//3946//3947//3948//3949//3950//3951//3952//3953//3954//3955//3956//3957//3958//3959//3960//3961//3962//3963//3964//3965//3966//3967//3968//3969//3970//3971//3972//3973//3974//3975//3976//3977//3978//3979//3980//3981//3982//3983//3984//3985// OMP-DEfAULT-LABEL: define {{[^@]+}}@__cxx_global_var_init3986// OMP-DEfAULT-SAME: () #[[ATTR0:[0-9]+]] {3987// OMP-DEfAULT-NEXT:  entry:3988// OMP-DEfAULT-NEXT:    call void @_ZN2SAC1Ev(ptr noundef nonnull align 4 dereferenceable(16) @_ZL2a1)3989// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SAD1Ev, ptr @_ZL2a1, ptr @__dso_handle) #[[ATTR2:[0-9]+]]3990// OMP-DEfAULT-NEXT:    ret void3991//3992//3993// OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2SAC1Ev3994// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {3995// OMP-DEfAULT-NEXT:  entry:3996// OMP-DEfAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 43997// OMP-DEfAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 43998// OMP-DEfAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 43999// OMP-DEfAULT-NEXT:    call void @_ZN2SAC2Ev(ptr noundef nonnull align 4 dereferenceable(16) [[THIS1]])4000// OMP-DEfAULT-NEXT:    ret void4001//4002//4003// OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2SAD1Ev4004// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {4005// OMP-DEfAULT-NEXT:  entry:4006// OMP-DEfAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 44007// OMP-DEfAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 44008// OMP-DEfAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 44009// OMP-DEfAULT-NEXT:    call void @_ZN2SAD2Ev(ptr noundef nonnull align 4 dereferenceable(16) [[THIS1]]) #[[ATTR2]]4010// OMP-DEfAULT-NEXT:    ret void4011//4012//4013// OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2SAC2Ev4014// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {4015// OMP-DEfAULT-NEXT:  entry:4016// OMP-DEfAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 44017// OMP-DEfAULT-NEXT:    [[A:%.*]] = alloca i32, align 44018// OMP-DEfAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 44019// OMP-DEfAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 44020// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 44021// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 44022// OMP-DEfAULT-NEXT:    store i32 [[TMP1]], ptr [[A]], align 44023// OMP-DEfAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 44024// OMP-DEfAULT-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP2]], 24025// OMP-DEfAULT-NEXT:    store i32 [[ADD]], ptr [[A]], align 44026// OMP-DEfAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 44027// OMP-DEfAULT-NEXT:    [[TMP4:%.*]] = load ptr, ptr @R, align 44028// OMP-DEfAULT-NEXT:    store i32 [[TMP3]], ptr [[TMP4]], align 44029// OMP-DEfAULT-NEXT:    ret void4030//4031//4032// OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2SAD2Ev4033// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {4034// OMP-DEfAULT-NEXT:  entry:4035// OMP-DEfAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 44036// OMP-DEfAULT-NEXT:    [[A:%.*]] = alloca i32, align 44037// OMP-DEfAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 44038// OMP-DEfAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 44039// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 44040// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 44041// OMP-DEfAULT-NEXT:    store i32 [[TMP1]], ptr [[A]], align 44042// OMP-DEfAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 44043// OMP-DEfAULT-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP2]], 34044// OMP-DEfAULT-NEXT:    store i32 [[ADD]], ptr [[A]], align 44045// OMP-DEfAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 44046// OMP-DEfAULT-NEXT:    [[TMP4:%.*]] = load ptr, ptr @R, align 44047// OMP-DEfAULT-NEXT:    store i32 [[TMP3]], ptr [[TMP4]], align 44048// OMP-DEfAULT-NEXT:    ret void4049//4050//4051// OMP-DEfAULT-LABEL: define {{[^@]+}}@__cxx_global_var_init.14052// OMP-DEfAULT-SAME: () #[[ATTR0]] {4053// OMP-DEfAULT-NEXT:  entry:4054// OMP-DEfAULT-NEXT:    call void @_ZN2SAC1Ev(ptr noundef nonnull align 4 dereferenceable(16) @a2)4055// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SAD1Ev, ptr @a2, ptr @__dso_handle) #[[ATTR2]]4056// OMP-DEfAULT-NEXT:    ret void4057//4058//4059// OMP-DEfAULT-LABEL: define {{[^@]+}}@__cxx_global_var_init.24060// OMP-DEfAULT-SAME: () #[[ATTR0]] {4061// OMP-DEfAULT-NEXT:  entry:4062// OMP-DEfAULT-NEXT:    call void @_ZN2SBC1Ev(ptr noundef nonnull align 4 dereferenceable(32) @b1)4063// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SBD1Ev, ptr @b1, ptr @__dso_handle) #[[ATTR2]]4064// OMP-DEfAULT-NEXT:    ret void4065//4066//4067// OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2SBC1Ev4068// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(32) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {4069// OMP-DEfAULT-NEXT:  entry:4070// OMP-DEfAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 44071// OMP-DEfAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 44072// OMP-DEfAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 44073// OMP-DEfAULT-NEXT:    call void @_ZN2SBC2Ev(ptr noundef nonnull align 4 dereferenceable(32) [[THIS1]])4074// OMP-DEfAULT-NEXT:    ret void4075//4076//4077// OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2SBD1Ev4078// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(32) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {4079// OMP-DEfAULT-NEXT:  entry:4080// OMP-DEfAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 44081// OMP-DEfAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 44082// OMP-DEfAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 44083// OMP-DEfAULT-NEXT:    call void @_ZN2SBD2Ev(ptr noundef nonnull align 4 dereferenceable(32) [[THIS1]]) #[[ATTR2]]4084// OMP-DEfAULT-NEXT:    ret void4085//4086//4087// OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2SBC2Ev4088// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(32) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {4089// OMP-DEfAULT-NEXT:  entry:4090// OMP-DEfAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 44091// OMP-DEfAULT-NEXT:    [[A:%.*]] = alloca i32, align 44092// OMP-DEfAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 44093// OMP-DEfAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 44094// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 44095// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 44096// OMP-DEfAULT-NEXT:    store i32 [[TMP1]], ptr [[A]], align 44097// OMP-DEfAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 44098// OMP-DEfAULT-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP2]], 54099// OMP-DEfAULT-NEXT:    store i32 [[ADD]], ptr [[A]], align 44100// OMP-DEfAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 44101// OMP-DEfAULT-NEXT:    [[TMP4:%.*]] = load ptr, ptr @R, align 44102// OMP-DEfAULT-NEXT:    store i32 [[TMP3]], ptr [[TMP4]], align 44103// OMP-DEfAULT-NEXT:    ret void4104//4105//4106// OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2SBD2Ev4107// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(32) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {4108// OMP-DEfAULT-NEXT:  entry:4109// OMP-DEfAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 44110// OMP-DEfAULT-NEXT:    [[A:%.*]] = alloca i32, align 44111// OMP-DEfAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 44112// OMP-DEfAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 44113// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 44114// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 44115// OMP-DEfAULT-NEXT:    store i32 [[TMP1]], ptr [[A]], align 44116// OMP-DEfAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 44117// OMP-DEfAULT-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP2]], 64118// OMP-DEfAULT-NEXT:    store i32 [[ADD]], ptr [[A]], align 44119// OMP-DEfAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 44120// OMP-DEfAULT-NEXT:    [[TMP4:%.*]] = load ptr, ptr @R, align 44121// OMP-DEfAULT-NEXT:    store i32 [[TMP3]], ptr [[TMP4]], align 44122// OMP-DEfAULT-NEXT:    ret void4123//4124//4125// OMP-DEfAULT-LABEL: define {{[^@]+}}@__cxx_global_var_init.34126// OMP-DEfAULT-SAME: () #[[ATTR0]] {4127// OMP-DEfAULT-NEXT:  entry:4128// OMP-DEfAULT-NEXT:    call void @_ZN2SBC1Ev(ptr noundef nonnull align 4 dereferenceable(32) @b2)4129// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SBD1Ev, ptr @b2, ptr @__dso_handle) #[[ATTR2]]4130// OMP-DEfAULT-NEXT:    ret void4131//4132//4133// OMP-DEfAULT-LABEL: define {{[^@]+}}@__cxx_global_var_init.44134// OMP-DEfAULT-SAME: () #[[ATTR0]] {4135// OMP-DEfAULT-NEXT:  entry:4136// OMP-DEfAULT-NEXT:    call void @_ZN2SCC1Ev(ptr noundef nonnull align 4 dereferenceable(64) @_ZL2c1)4137// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SCD1Ev, ptr @_ZL2c1, ptr @__dso_handle) #[[ATTR2]]4138// OMP-DEfAULT-NEXT:    ret void4139//4140//4141// OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2SCC1Ev4142// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(64) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {4143// OMP-DEfAULT-NEXT:  entry:4144// OMP-DEfAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 44145// OMP-DEfAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 44146// OMP-DEfAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 44147// OMP-DEfAULT-NEXT:    call void @_ZN2SCC2Ev(ptr noundef nonnull align 4 dereferenceable(64) [[THIS1]])4148// OMP-DEfAULT-NEXT:    ret void4149//4150//4151// OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2SCD1Ev4152// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(64) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {4153// OMP-DEfAULT-NEXT:  entry:4154// OMP-DEfAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 44155// OMP-DEfAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 44156// OMP-DEfAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 44157// OMP-DEfAULT-NEXT:    call void @_ZN2SCD2Ev(ptr noundef nonnull align 4 dereferenceable(64) [[THIS1]]) #[[ATTR2]]4158// OMP-DEfAULT-NEXT:    ret void4159//4160//4161// OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2SCC2Ev4162// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(64) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {4163// OMP-DEfAULT-NEXT:  entry:4164// OMP-DEfAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 44165// OMP-DEfAULT-NEXT:    [[A:%.*]] = alloca i32, align 44166// OMP-DEfAULT-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 44167// OMP-DEfAULT-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 44168// OMP-DEfAULT-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 44169// OMP-DEfAULT-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 44170// OMP-DEfAULT-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 84171// OMP-DEfAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 44172// OMP-DEfAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 44173// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 44174// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 44175// OMP-DEfAULT-NEXT:    store i32 [[TMP1]], ptr [[A]], align 44176// OMP-DEfAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 44177// OMP-DEfAULT-NEXT:    store i32 [[TMP2]], ptr [[A_CASTED]], align 44178// OMP-DEfAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A_CASTED]], align 44179// OMP-DEfAULT-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 04180// OMP-DEfAULT-NEXT:    store i32 [[TMP3]], ptr [[TMP4]], align 44181// OMP-DEfAULT-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 04182// OMP-DEfAULT-NEXT:    store i32 [[TMP3]], ptr [[TMP5]], align 44183// OMP-DEfAULT-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 04184// OMP-DEfAULT-NEXT:    store ptr null, ptr [[TMP6]], align 44185// OMP-DEfAULT-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 04186// OMP-DEfAULT-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 04187// OMP-DEfAULT-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 04188// OMP-DEfAULT-NEXT:    store i32 3, ptr [[TMP9]], align 44189// OMP-DEfAULT-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 14190// OMP-DEfAULT-NEXT:    store i32 1, ptr [[TMP10]], align 44191// OMP-DEfAULT-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 24192// OMP-DEfAULT-NEXT:    store ptr [[TMP7]], ptr [[TMP11]], align 44193// OMP-DEfAULT-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 34194// OMP-DEfAULT-NEXT:    store ptr [[TMP8]], ptr [[TMP12]], align 44195// OMP-DEfAULT-NEXT:    [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 44196// OMP-DEfAULT-NEXT:    store ptr @.offload_sizes, ptr [[TMP13]], align 44197// OMP-DEfAULT-NEXT:    [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 54198// OMP-DEfAULT-NEXT:    store ptr @.offload_maptypes, ptr [[TMP14]], align 44199// OMP-DEfAULT-NEXT:    [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 64200// OMP-DEfAULT-NEXT:    store ptr null, ptr [[TMP15]], align 44201// OMP-DEfAULT-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 74202// OMP-DEfAULT-NEXT:    store ptr null, ptr [[TMP16]], align 44203// OMP-DEfAULT-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 84204// OMP-DEfAULT-NEXT:    store i64 0, ptr [[TMP17]], align 84205// OMP-DEfAULT-NEXT:    [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 94206// OMP-DEfAULT-NEXT:    store i64 0, ptr [[TMP18]], align 84207// OMP-DEfAULT-NEXT:    [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 104208// OMP-DEfAULT-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP19]], align 44209// OMP-DEfAULT-NEXT:    [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 114210// OMP-DEfAULT-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP20]], align 44211// OMP-DEfAULT-NEXT:    [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 124212// OMP-DEfAULT-NEXT:    store i32 0, ptr [[TMP21]], align 44213// OMP-DEfAULT-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SCC1Ev_l148.region_id, ptr [[KERNEL_ARGS]])4214// OMP-DEfAULT-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 04215// OMP-DEfAULT-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]4216// OMP-DEfAULT:       omp_offload.failed:4217// OMP-DEfAULT-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SCC1Ev_l148(i32 [[TMP3]]) #[[ATTR2]]4218// OMP-DEfAULT-NEXT:    br label [[OMP_OFFLOAD_CONT]]4219// OMP-DEfAULT:       omp_offload.cont:4220// OMP-DEfAULT-NEXT:    [[TMP24:%.*]] = load i32, ptr [[A]], align 44221// OMP-DEfAULT-NEXT:    [[TMP25:%.*]] = load ptr, ptr @R, align 44222// OMP-DEfAULT-NEXT:    store i32 [[TMP24]], ptr [[TMP25]], align 44223// OMP-DEfAULT-NEXT:    ret void4224//4225//4226// OMP-DEfAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SCC1Ev_l1484227// OMP-DEfAULT-SAME: (i32 noundef [[A:%.*]]) #[[ATTR3:[0-9]+]] {4228// OMP-DEfAULT-NEXT:  entry:4229// OMP-DEfAULT-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 44230// OMP-DEfAULT-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 44231// OMP-DEfAULT-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 44232// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 44233// OMP-DEfAULT-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 44234// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 44235// OMP-DEfAULT-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SCC1Ev_l148.omp_outlined, i32 [[TMP1]])4236// OMP-DEfAULT-NEXT:    ret void4237//4238//4239// OMP-DEfAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SCC1Ev_l148.omp_outlined4240// OMP-DEfAULT-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] {4241// OMP-DEfAULT-NEXT:  entry:4242// OMP-DEfAULT-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 44243// OMP-DEfAULT-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 44244// OMP-DEfAULT-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 44245// OMP-DEfAULT-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 44246// OMP-DEfAULT-NEXT:    [[TMP:%.*]] = alloca i32, align 44247// OMP-DEfAULT-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 44248// OMP-DEfAULT-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 44249// OMP-DEfAULT-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 44250// OMP-DEfAULT-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 44251// OMP-DEfAULT-NEXT:    [[I:%.*]] = alloca i32, align 44252// OMP-DEfAULT-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 44253// OMP-DEfAULT-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 44254// OMP-DEfAULT-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 44255// OMP-DEfAULT-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 44256// OMP-DEfAULT-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 44257// OMP-DEfAULT-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 44258// OMP-DEfAULT-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 44259// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 44260// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 44261// OMP-DEfAULT-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)4262// OMP-DEfAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44263// OMP-DEfAULT-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 94264// OMP-DEfAULT-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]4265// OMP-DEfAULT:       cond.true:4266// OMP-DEfAULT-NEXT:    br label [[COND_END:%.*]]4267// OMP-DEfAULT:       cond.false:4268// OMP-DEfAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44269// OMP-DEfAULT-NEXT:    br label [[COND_END]]4270// OMP-DEfAULT:       cond.end:4271// OMP-DEfAULT-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]4272// OMP-DEfAULT-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 44273// OMP-DEfAULT-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 44274// OMP-DEfAULT-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 44275// OMP-DEfAULT-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]4276// OMP-DEfAULT:       omp.inner.for.cond:4277// OMP-DEfAULT-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44278// OMP-DEfAULT-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44279// OMP-DEfAULT-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]4280// OMP-DEfAULT-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]4281// OMP-DEfAULT:       omp.inner.for.body:4282// OMP-DEfAULT-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44283// OMP-DEfAULT-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 14284// OMP-DEfAULT-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]4285// OMP-DEfAULT-NEXT:    store i32 [[ADD]], ptr [[I]], align 44286// OMP-DEfAULT-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 44287// OMP-DEfAULT-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 84288// OMP-DEfAULT-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 44289// OMP-DEfAULT-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]4290// OMP-DEfAULT:       omp.body.continue:4291// OMP-DEfAULT-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]4292// OMP-DEfAULT:       omp.inner.for.inc:4293// OMP-DEfAULT-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44294// OMP-DEfAULT-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 14295// OMP-DEfAULT-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 44296// OMP-DEfAULT-NEXT:    br label [[OMP_INNER_FOR_COND]]4297// OMP-DEfAULT:       omp.inner.for.end:4298// OMP-DEfAULT-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]4299// OMP-DEfAULT:       omp.loop.exit:4300// OMP-DEfAULT-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])4301// OMP-DEfAULT-NEXT:    ret void4302//4303//4304// OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2SCD2Ev4305// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(64) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {4306// OMP-DEfAULT-NEXT:  entry:4307// OMP-DEfAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 44308// OMP-DEfAULT-NEXT:    [[A:%.*]] = alloca i32, align 44309// OMP-DEfAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 44310// OMP-DEfAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 44311// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 44312// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 44313// OMP-DEfAULT-NEXT:    store i32 [[TMP1]], ptr [[A]], align 44314// OMP-DEfAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 44315// OMP-DEfAULT-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP2]], 94316// OMP-DEfAULT-NEXT:    store i32 [[ADD]], ptr [[A]], align 44317// OMP-DEfAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 44318// OMP-DEfAULT-NEXT:    [[TMP4:%.*]] = load ptr, ptr @R, align 44319// OMP-DEfAULT-NEXT:    store i32 [[TMP3]], ptr [[TMP4]], align 44320// OMP-DEfAULT-NEXT:    ret void4321//4322//4323// OMP-DEfAULT-LABEL: define {{[^@]+}}@__cxx_global_var_init.54324// OMP-DEfAULT-SAME: () #[[ATTR0]] {4325// OMP-DEfAULT-NEXT:  entry:4326// OMP-DEfAULT-NEXT:    call void @_ZN2SDC1Ev(ptr noundef nonnull align 4 dereferenceable(128) @d1)4327// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SDD1Ev, ptr @d1, ptr @__dso_handle) #[[ATTR2]]4328// OMP-DEfAULT-NEXT:    ret void4329//4330//4331// OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2SDC1Ev4332// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(128) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {4333// OMP-DEfAULT-NEXT:  entry:4334// OMP-DEfAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 44335// OMP-DEfAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 44336// OMP-DEfAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 44337// OMP-DEfAULT-NEXT:    call void @_ZN2SDC2Ev(ptr noundef nonnull align 4 dereferenceable(128) [[THIS1]])4338// OMP-DEfAULT-NEXT:    ret void4339//4340//4341// OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2SDD1Ev4342// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(128) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {4343// OMP-DEfAULT-NEXT:  entry:4344// OMP-DEfAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 44345// OMP-DEfAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 44346// OMP-DEfAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 44347// OMP-DEfAULT-NEXT:    call void @_ZN2SDD2Ev(ptr noundef nonnull align 4 dereferenceable(128) [[THIS1]]) #[[ATTR2]]4348// OMP-DEfAULT-NEXT:    ret void4349//4350//4351// OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2SDC2Ev4352// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(128) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {4353// OMP-DEfAULT-NEXT:  entry:4354// OMP-DEfAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 44355// OMP-DEfAULT-NEXT:    [[A:%.*]] = alloca i32, align 44356// OMP-DEfAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 44357// OMP-DEfAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 44358// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 44359// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 44360// OMP-DEfAULT-NEXT:    store i32 [[TMP1]], ptr [[A]], align 44361// OMP-DEfAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 44362// OMP-DEfAULT-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP2]], 114363// OMP-DEfAULT-NEXT:    store i32 [[ADD]], ptr [[A]], align 44364// OMP-DEfAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 44365// OMP-DEfAULT-NEXT:    [[TMP4:%.*]] = load ptr, ptr @R, align 44366// OMP-DEfAULT-NEXT:    store i32 [[TMP3]], ptr [[TMP4]], align 44367// OMP-DEfAULT-NEXT:    ret void4368//4369//4370// OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2SDD2Ev4371// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(128) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {4372// OMP-DEfAULT-NEXT:  entry:4373// OMP-DEfAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 44374// OMP-DEfAULT-NEXT:    [[A:%.*]] = alloca i32, align 44375// OMP-DEfAULT-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 44376// OMP-DEfAULT-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 44377// OMP-DEfAULT-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 44378// OMP-DEfAULT-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 44379// OMP-DEfAULT-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 84380// OMP-DEfAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 44381// OMP-DEfAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 44382// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 44383// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 44384// OMP-DEfAULT-NEXT:    store i32 [[TMP1]], ptr [[A]], align 44385// OMP-DEfAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 44386// OMP-DEfAULT-NEXT:    store i32 [[TMP2]], ptr [[A_CASTED]], align 44387// OMP-DEfAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A_CASTED]], align 44388// OMP-DEfAULT-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 04389// OMP-DEfAULT-NEXT:    store i32 [[TMP3]], ptr [[TMP4]], align 44390// OMP-DEfAULT-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 04391// OMP-DEfAULT-NEXT:    store i32 [[TMP3]], ptr [[TMP5]], align 44392// OMP-DEfAULT-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 04393// OMP-DEfAULT-NEXT:    store ptr null, ptr [[TMP6]], align 44394// OMP-DEfAULT-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 04395// OMP-DEfAULT-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 04396// OMP-DEfAULT-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 04397// OMP-DEfAULT-NEXT:    store i32 3, ptr [[TMP9]], align 44398// OMP-DEfAULT-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 14399// OMP-DEfAULT-NEXT:    store i32 1, ptr [[TMP10]], align 44400// OMP-DEfAULT-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 24401// OMP-DEfAULT-NEXT:    store ptr [[TMP7]], ptr [[TMP11]], align 44402// OMP-DEfAULT-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 34403// OMP-DEfAULT-NEXT:    store ptr [[TMP8]], ptr [[TMP12]], align 44404// OMP-DEfAULT-NEXT:    [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 44405// OMP-DEfAULT-NEXT:    store ptr @.offload_sizes.6, ptr [[TMP13]], align 44406// OMP-DEfAULT-NEXT:    [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 54407// OMP-DEfAULT-NEXT:    store ptr @.offload_maptypes.7, ptr [[TMP14]], align 44408// OMP-DEfAULT-NEXT:    [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 64409// OMP-DEfAULT-NEXT:    store ptr null, ptr [[TMP15]], align 44410// OMP-DEfAULT-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 74411// OMP-DEfAULT-NEXT:    store ptr null, ptr [[TMP16]], align 44412// OMP-DEfAULT-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 84413// OMP-DEfAULT-NEXT:    store i64 0, ptr [[TMP17]], align 84414// OMP-DEfAULT-NEXT:    [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 94415// OMP-DEfAULT-NEXT:    store i64 0, ptr [[TMP18]], align 84416// OMP-DEfAULT-NEXT:    [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 104417// OMP-DEfAULT-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP19]], align 44418// OMP-DEfAULT-NEXT:    [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 114419// OMP-DEfAULT-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP20]], align 44420// OMP-DEfAULT-NEXT:    [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 124421// OMP-DEfAULT-NEXT:    store i32 0, ptr [[TMP21]], align 44422// OMP-DEfAULT-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SDD1Ev_l174.region_id, ptr [[KERNEL_ARGS]])4423// OMP-DEfAULT-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 04424// OMP-DEfAULT-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]4425// OMP-DEfAULT:       omp_offload.failed:4426// OMP-DEfAULT-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SDD1Ev_l174(i32 [[TMP3]]) #[[ATTR2]]4427// OMP-DEfAULT-NEXT:    br label [[OMP_OFFLOAD_CONT]]4428// OMP-DEfAULT:       omp_offload.cont:4429// OMP-DEfAULT-NEXT:    [[TMP24:%.*]] = load i32, ptr [[A]], align 44430// OMP-DEfAULT-NEXT:    [[TMP25:%.*]] = load ptr, ptr @R, align 44431// OMP-DEfAULT-NEXT:    store i32 [[TMP24]], ptr [[TMP25]], align 44432// OMP-DEfAULT-NEXT:    ret void4433//4434//4435// OMP-DEfAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SDD1Ev_l1744436// OMP-DEfAULT-SAME: (i32 noundef [[A:%.*]]) #[[ATTR3]] {4437// OMP-DEfAULT-NEXT:  entry:4438// OMP-DEfAULT-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 44439// OMP-DEfAULT-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 44440// OMP-DEfAULT-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 44441// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 44442// OMP-DEfAULT-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 44443// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 44444// OMP-DEfAULT-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SDD1Ev_l174.omp_outlined, i32 [[TMP1]])4445// OMP-DEfAULT-NEXT:    ret void4446//4447//4448// OMP-DEfAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SDD1Ev_l174.omp_outlined4449// OMP-DEfAULT-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] {4450// OMP-DEfAULT-NEXT:  entry:4451// OMP-DEfAULT-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 44452// OMP-DEfAULT-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 44453// OMP-DEfAULT-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 44454// OMP-DEfAULT-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 44455// OMP-DEfAULT-NEXT:    [[TMP:%.*]] = alloca i32, align 44456// OMP-DEfAULT-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 44457// OMP-DEfAULT-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 44458// OMP-DEfAULT-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 44459// OMP-DEfAULT-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 44460// OMP-DEfAULT-NEXT:    [[I:%.*]] = alloca i32, align 44461// OMP-DEfAULT-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 44462// OMP-DEfAULT-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 44463// OMP-DEfAULT-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 44464// OMP-DEfAULT-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 44465// OMP-DEfAULT-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 44466// OMP-DEfAULT-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 44467// OMP-DEfAULT-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 44468// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 44469// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 44470// OMP-DEfAULT-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)4471// OMP-DEfAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44472// OMP-DEfAULT-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 94473// OMP-DEfAULT-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]4474// OMP-DEfAULT:       cond.true:4475// OMP-DEfAULT-NEXT:    br label [[COND_END:%.*]]4476// OMP-DEfAULT:       cond.false:4477// OMP-DEfAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44478// OMP-DEfAULT-NEXT:    br label [[COND_END]]4479// OMP-DEfAULT:       cond.end:4480// OMP-DEfAULT-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]4481// OMP-DEfAULT-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 44482// OMP-DEfAULT-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 44483// OMP-DEfAULT-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 44484// OMP-DEfAULT-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]4485// OMP-DEfAULT:       omp.inner.for.cond:4486// OMP-DEfAULT-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44487// OMP-DEfAULT-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44488// OMP-DEfAULT-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]4489// OMP-DEfAULT-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]4490// OMP-DEfAULT:       omp.inner.for.body:4491// OMP-DEfAULT-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44492// OMP-DEfAULT-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 14493// OMP-DEfAULT-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]4494// OMP-DEfAULT-NEXT:    store i32 [[ADD]], ptr [[I]], align 44495// OMP-DEfAULT-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 44496// OMP-DEfAULT-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 124497// OMP-DEfAULT-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 44498// OMP-DEfAULT-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]4499// OMP-DEfAULT:       omp.body.continue:4500// OMP-DEfAULT-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]4501// OMP-DEfAULT:       omp.inner.for.inc:4502// OMP-DEfAULT-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44503// OMP-DEfAULT-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 14504// OMP-DEfAULT-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 44505// OMP-DEfAULT-NEXT:    br label [[OMP_INNER_FOR_COND]]4506// OMP-DEfAULT:       omp.inner.for.end:4507// OMP-DEfAULT-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]4508// OMP-DEfAULT:       omp.loop.exit:4509// OMP-DEfAULT-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])4510// OMP-DEfAULT-NEXT:    ret void4511//4512//4513// OMP-DEfAULT-LABEL: define {{[^@]+}}@__cxx_global_var_init.84514// OMP-DEfAULT-SAME: () #[[ATTR0]] {4515// OMP-DEfAULT-NEXT:  entry:4516// OMP-DEfAULT-NEXT:    call void @_ZN2SEC1Ev(ptr noundef nonnull align 4 dereferenceable(256) @e1)4517// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SED1Ev, ptr @e1, ptr @__dso_handle) #[[ATTR2]]4518// OMP-DEfAULT-NEXT:    ret void4519//4520//4521// OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2SEC1Ev4522// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(256) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {4523// OMP-DEfAULT-NEXT:  entry:4524// OMP-DEfAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 44525// OMP-DEfAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 44526// OMP-DEfAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 44527// OMP-DEfAULT-NEXT:    call void @_ZN2SEC2Ev(ptr noundef nonnull align 4 dereferenceable(256) [[THIS1]])4528// OMP-DEfAULT-NEXT:    ret void4529//4530//4531// OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2SED1Ev4532// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(256) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {4533// OMP-DEfAULT-NEXT:  entry:4534// OMP-DEfAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 44535// OMP-DEfAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 44536// OMP-DEfAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 44537// OMP-DEfAULT-NEXT:    call void @_ZN2SED2Ev(ptr noundef nonnull align 4 dereferenceable(256) [[THIS1]]) #[[ATTR2]]4538// OMP-DEfAULT-NEXT:    ret void4539//4540//4541// OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2SEC2Ev4542// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(256) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {4543// OMP-DEfAULT-NEXT:  entry:4544// OMP-DEfAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 44545// OMP-DEfAULT-NEXT:    [[A:%.*]] = alloca i32, align 44546// OMP-DEfAULT-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 44547// OMP-DEfAULT-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 44548// OMP-DEfAULT-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 44549// OMP-DEfAULT-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 44550// OMP-DEfAULT-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 84551// OMP-DEfAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 44552// OMP-DEfAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 44553// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 44554// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 44555// OMP-DEfAULT-NEXT:    store i32 [[TMP1]], ptr [[A]], align 44556// OMP-DEfAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 44557// OMP-DEfAULT-NEXT:    store i32 [[TMP2]], ptr [[A_CASTED]], align 44558// OMP-DEfAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A_CASTED]], align 44559// OMP-DEfAULT-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 04560// OMP-DEfAULT-NEXT:    store i32 [[TMP3]], ptr [[TMP4]], align 44561// OMP-DEfAULT-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 04562// OMP-DEfAULT-NEXT:    store i32 [[TMP3]], ptr [[TMP5]], align 44563// OMP-DEfAULT-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 04564// OMP-DEfAULT-NEXT:    store ptr null, ptr [[TMP6]], align 44565// OMP-DEfAULT-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 04566// OMP-DEfAULT-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 04567// OMP-DEfAULT-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 04568// OMP-DEfAULT-NEXT:    store i32 3, ptr [[TMP9]], align 44569// OMP-DEfAULT-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 14570// OMP-DEfAULT-NEXT:    store i32 1, ptr [[TMP10]], align 44571// OMP-DEfAULT-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 24572// OMP-DEfAULT-NEXT:    store ptr [[TMP7]], ptr [[TMP11]], align 44573// OMP-DEfAULT-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 34574// OMP-DEfAULT-NEXT:    store ptr [[TMP8]], ptr [[TMP12]], align 44575// OMP-DEfAULT-NEXT:    [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 44576// OMP-DEfAULT-NEXT:    store ptr @.offload_sizes.9, ptr [[TMP13]], align 44577// OMP-DEfAULT-NEXT:    [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 54578// OMP-DEfAULT-NEXT:    store ptr @.offload_maptypes.10, ptr [[TMP14]], align 44579// OMP-DEfAULT-NEXT:    [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 64580// OMP-DEfAULT-NEXT:    store ptr null, ptr [[TMP15]], align 44581// OMP-DEfAULT-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 74582// OMP-DEfAULT-NEXT:    store ptr null, ptr [[TMP16]], align 44583// OMP-DEfAULT-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 84584// OMP-DEfAULT-NEXT:    store i64 0, ptr [[TMP17]], align 84585// OMP-DEfAULT-NEXT:    [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 94586// OMP-DEfAULT-NEXT:    store i64 0, ptr [[TMP18]], align 84587// OMP-DEfAULT-NEXT:    [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 104588// OMP-DEfAULT-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP19]], align 44589// OMP-DEfAULT-NEXT:    [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 114590// OMP-DEfAULT-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP20]], align 44591// OMP-DEfAULT-NEXT:    [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 124592// OMP-DEfAULT-NEXT:    store i32 0, ptr [[TMP21]], align 44593// OMP-DEfAULT-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SEC1Ev_l192.region_id, ptr [[KERNEL_ARGS]])4594// OMP-DEfAULT-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 04595// OMP-DEfAULT-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]4596// OMP-DEfAULT:       omp_offload.failed:4597// OMP-DEfAULT-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SEC1Ev_l192(i32 [[TMP3]]) #[[ATTR2]]4598// OMP-DEfAULT-NEXT:    br label [[OMP_OFFLOAD_CONT]]4599// OMP-DEfAULT:       omp_offload.cont:4600// OMP-DEfAULT-NEXT:    [[TMP24:%.*]] = load i32, ptr [[A]], align 44601// OMP-DEfAULT-NEXT:    [[TMP25:%.*]] = load ptr, ptr @R, align 44602// OMP-DEfAULT-NEXT:    store i32 [[TMP24]], ptr [[TMP25]], align 44603// OMP-DEfAULT-NEXT:    ret void4604//4605//4606// OMP-DEfAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SEC1Ev_l1924607// OMP-DEfAULT-SAME: (i32 noundef [[A:%.*]]) #[[ATTR3]] {4608// OMP-DEfAULT-NEXT:  entry:4609// OMP-DEfAULT-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 44610// OMP-DEfAULT-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 44611// OMP-DEfAULT-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 44612// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 44613// OMP-DEfAULT-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 44614// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 44615// OMP-DEfAULT-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SEC1Ev_l192.omp_outlined, i32 [[TMP1]])4616// OMP-DEfAULT-NEXT:    ret void4617//4618//4619// OMP-DEfAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SEC1Ev_l192.omp_outlined4620// OMP-DEfAULT-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] {4621// OMP-DEfAULT-NEXT:  entry:4622// OMP-DEfAULT-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 44623// OMP-DEfAULT-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 44624// OMP-DEfAULT-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 44625// OMP-DEfAULT-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 44626// OMP-DEfAULT-NEXT:    [[TMP:%.*]] = alloca i32, align 44627// OMP-DEfAULT-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 44628// OMP-DEfAULT-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 44629// OMP-DEfAULT-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 44630// OMP-DEfAULT-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 44631// OMP-DEfAULT-NEXT:    [[I:%.*]] = alloca i32, align 44632// OMP-DEfAULT-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 44633// OMP-DEfAULT-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 44634// OMP-DEfAULT-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 44635// OMP-DEfAULT-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 44636// OMP-DEfAULT-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 44637// OMP-DEfAULT-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 44638// OMP-DEfAULT-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 44639// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 44640// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 44641// OMP-DEfAULT-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)4642// OMP-DEfAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44643// OMP-DEfAULT-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 94644// OMP-DEfAULT-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]4645// OMP-DEfAULT:       cond.true:4646// OMP-DEfAULT-NEXT:    br label [[COND_END:%.*]]4647// OMP-DEfAULT:       cond.false:4648// OMP-DEfAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44649// OMP-DEfAULT-NEXT:    br label [[COND_END]]4650// OMP-DEfAULT:       cond.end:4651// OMP-DEfAULT-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]4652// OMP-DEfAULT-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 44653// OMP-DEfAULT-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 44654// OMP-DEfAULT-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 44655// OMP-DEfAULT-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]4656// OMP-DEfAULT:       omp.inner.for.cond:4657// OMP-DEfAULT-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44658// OMP-DEfAULT-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44659// OMP-DEfAULT-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]4660// OMP-DEfAULT-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]4661// OMP-DEfAULT:       omp.inner.for.body:4662// OMP-DEfAULT-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44663// OMP-DEfAULT-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 14664// OMP-DEfAULT-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]4665// OMP-DEfAULT-NEXT:    store i32 [[ADD]], ptr [[I]], align 44666// OMP-DEfAULT-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 44667// OMP-DEfAULT-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 144668// OMP-DEfAULT-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 44669// OMP-DEfAULT-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]4670// OMP-DEfAULT:       omp.body.continue:4671// OMP-DEfAULT-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]4672// OMP-DEfAULT:       omp.inner.for.inc:4673// OMP-DEfAULT-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44674// OMP-DEfAULT-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 14675// OMP-DEfAULT-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 44676// OMP-DEfAULT-NEXT:    br label [[OMP_INNER_FOR_COND]]4677// OMP-DEfAULT:       omp.inner.for.end:4678// OMP-DEfAULT-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]4679// OMP-DEfAULT:       omp.loop.exit:4680// OMP-DEfAULT-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])4681// OMP-DEfAULT-NEXT:    ret void4682//4683//4684// OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2SED2Ev4685// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(256) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {4686// OMP-DEfAULT-NEXT:  entry:4687// OMP-DEfAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 44688// OMP-DEfAULT-NEXT:    [[A:%.*]] = alloca i32, align 44689// OMP-DEfAULT-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 44690// OMP-DEfAULT-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 44691// OMP-DEfAULT-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 44692// OMP-DEfAULT-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 44693// OMP-DEfAULT-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 84694// OMP-DEfAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 44695// OMP-DEfAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 44696// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 44697// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 44698// OMP-DEfAULT-NEXT:    store i32 [[TMP1]], ptr [[A]], align 44699// OMP-DEfAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 44700// OMP-DEfAULT-NEXT:    store i32 [[TMP2]], ptr [[A_CASTED]], align 44701// OMP-DEfAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A_CASTED]], align 44702// OMP-DEfAULT-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 04703// OMP-DEfAULT-NEXT:    store i32 [[TMP3]], ptr [[TMP4]], align 44704// OMP-DEfAULT-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 04705// OMP-DEfAULT-NEXT:    store i32 [[TMP3]], ptr [[TMP5]], align 44706// OMP-DEfAULT-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 04707// OMP-DEfAULT-NEXT:    store ptr null, ptr [[TMP6]], align 44708// OMP-DEfAULT-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 04709// OMP-DEfAULT-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 04710// OMP-DEfAULT-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 04711// OMP-DEfAULT-NEXT:    store i32 3, ptr [[TMP9]], align 44712// OMP-DEfAULT-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 14713// OMP-DEfAULT-NEXT:    store i32 1, ptr [[TMP10]], align 44714// OMP-DEfAULT-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 24715// OMP-DEfAULT-NEXT:    store ptr [[TMP7]], ptr [[TMP11]], align 44716// OMP-DEfAULT-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 34717// OMP-DEfAULT-NEXT:    store ptr [[TMP8]], ptr [[TMP12]], align 44718// OMP-DEfAULT-NEXT:    [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 44719// OMP-DEfAULT-NEXT:    store ptr @.offload_sizes.11, ptr [[TMP13]], align 44720// OMP-DEfAULT-NEXT:    [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 54721// OMP-DEfAULT-NEXT:    store ptr @.offload_maptypes.12, ptr [[TMP14]], align 44722// OMP-DEfAULT-NEXT:    [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 64723// OMP-DEfAULT-NEXT:    store ptr null, ptr [[TMP15]], align 44724// OMP-DEfAULT-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 74725// OMP-DEfAULT-NEXT:    store ptr null, ptr [[TMP16]], align 44726// OMP-DEfAULT-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 84727// OMP-DEfAULT-NEXT:    store i64 0, ptr [[TMP17]], align 84728// OMP-DEfAULT-NEXT:    [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 94729// OMP-DEfAULT-NEXT:    store i64 0, ptr [[TMP18]], align 84730// OMP-DEfAULT-NEXT:    [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 104731// OMP-DEfAULT-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP19]], align 44732// OMP-DEfAULT-NEXT:    [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 114733// OMP-DEfAULT-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP20]], align 44734// OMP-DEfAULT-NEXT:    [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 124735// OMP-DEfAULT-NEXT:    store i32 0, ptr [[TMP21]], align 44736// OMP-DEfAULT-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SED1Ev_l199.region_id, ptr [[KERNEL_ARGS]])4737// OMP-DEfAULT-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 04738// OMP-DEfAULT-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]4739// OMP-DEfAULT:       omp_offload.failed:4740// OMP-DEfAULT-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SED1Ev_l199(i32 [[TMP3]]) #[[ATTR2]]4741// OMP-DEfAULT-NEXT:    br label [[OMP_OFFLOAD_CONT]]4742// OMP-DEfAULT:       omp_offload.cont:4743// OMP-DEfAULT-NEXT:    [[TMP24:%.*]] = load i32, ptr [[A]], align 44744// OMP-DEfAULT-NEXT:    [[TMP25:%.*]] = load ptr, ptr @R, align 44745// OMP-DEfAULT-NEXT:    store i32 [[TMP24]], ptr [[TMP25]], align 44746// OMP-DEfAULT-NEXT:    ret void4747//4748//4749// OMP-DEfAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SED1Ev_l1994750// OMP-DEfAULT-SAME: (i32 noundef [[A:%.*]]) #[[ATTR3]] {4751// OMP-DEfAULT-NEXT:  entry:4752// OMP-DEfAULT-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 44753// OMP-DEfAULT-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 44754// OMP-DEfAULT-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 44755// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 44756// OMP-DEfAULT-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 44757// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 44758// OMP-DEfAULT-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SED1Ev_l199.omp_outlined, i32 [[TMP1]])4759// OMP-DEfAULT-NEXT:    ret void4760//4761//4762// OMP-DEfAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SED1Ev_l199.omp_outlined4763// OMP-DEfAULT-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] {4764// OMP-DEfAULT-NEXT:  entry:4765// OMP-DEfAULT-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 44766// OMP-DEfAULT-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 44767// OMP-DEfAULT-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 44768// OMP-DEfAULT-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 44769// OMP-DEfAULT-NEXT:    [[TMP:%.*]] = alloca i32, align 44770// OMP-DEfAULT-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 44771// OMP-DEfAULT-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 44772// OMP-DEfAULT-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 44773// OMP-DEfAULT-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 44774// OMP-DEfAULT-NEXT:    [[I:%.*]] = alloca i32, align 44775// OMP-DEfAULT-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 44776// OMP-DEfAULT-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 44777// OMP-DEfAULT-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 44778// OMP-DEfAULT-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 44779// OMP-DEfAULT-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 44780// OMP-DEfAULT-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 44781// OMP-DEfAULT-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 44782// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 44783// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 44784// OMP-DEfAULT-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)4785// OMP-DEfAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44786// OMP-DEfAULT-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 94787// OMP-DEfAULT-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]4788// OMP-DEfAULT:       cond.true:4789// OMP-DEfAULT-NEXT:    br label [[COND_END:%.*]]4790// OMP-DEfAULT:       cond.false:4791// OMP-DEfAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44792// OMP-DEfAULT-NEXT:    br label [[COND_END]]4793// OMP-DEfAULT:       cond.end:4794// OMP-DEfAULT-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]4795// OMP-DEfAULT-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 44796// OMP-DEfAULT-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 44797// OMP-DEfAULT-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 44798// OMP-DEfAULT-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]4799// OMP-DEfAULT:       omp.inner.for.cond:4800// OMP-DEfAULT-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44801// OMP-DEfAULT-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44802// OMP-DEfAULT-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]4803// OMP-DEfAULT-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]4804// OMP-DEfAULT:       omp.inner.for.body:4805// OMP-DEfAULT-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44806// OMP-DEfAULT-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 14807// OMP-DEfAULT-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]4808// OMP-DEfAULT-NEXT:    store i32 [[ADD]], ptr [[I]], align 44809// OMP-DEfAULT-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 44810// OMP-DEfAULT-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 154811// OMP-DEfAULT-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 44812// OMP-DEfAULT-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]4813// OMP-DEfAULT:       omp.body.continue:4814// OMP-DEfAULT-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]4815// OMP-DEfAULT:       omp.inner.for.inc:4816// OMP-DEfAULT-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44817// OMP-DEfAULT-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 14818// OMP-DEfAULT-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 44819// OMP-DEfAULT-NEXT:    br label [[OMP_INNER_FOR_COND]]4820// OMP-DEfAULT:       omp.inner.for.end:4821// OMP-DEfAULT-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]4822// OMP-DEfAULT:       omp.loop.exit:4823// OMP-DEfAULT-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])4824// OMP-DEfAULT-NEXT:    ret void4825//4826//4827// OMP-DEfAULT-LABEL: define {{[^@]+}}@__cxx_global_var_init.134828// OMP-DEfAULT-SAME: () #[[ATTR0]] {4829// OMP-DEfAULT-NEXT:  entry:4830// OMP-DEfAULT-NEXT:    call void @_ZN2STILi100EEC1Ev(ptr noundef nonnull align 4 dereferenceable(912) @t1)4831// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2STILi100EED1Ev, ptr @t1, ptr @__dso_handle) #[[ATTR2]]4832// OMP-DEfAULT-NEXT:    ret void4833//4834//4835// OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2STILi100EEC1Ev4836// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(912) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {4837// OMP-DEfAULT-NEXT:  entry:4838// OMP-DEfAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 44839// OMP-DEfAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 44840// OMP-DEfAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 44841// OMP-DEfAULT-NEXT:    call void @_ZN2STILi100EEC2Ev(ptr noundef nonnull align 4 dereferenceable(912) [[THIS1]])4842// OMP-DEfAULT-NEXT:    ret void4843//4844//4845// OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2STILi100EED1Ev4846// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(912) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {4847// OMP-DEfAULT-NEXT:  entry:4848// OMP-DEfAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 44849// OMP-DEfAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 44850// OMP-DEfAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 44851// OMP-DEfAULT-NEXT:    call void @_ZN2STILi100EED2Ev(ptr noundef nonnull align 4 dereferenceable(912) [[THIS1]]) #[[ATTR2]]4852// OMP-DEfAULT-NEXT:    ret void4853//4854//4855// OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2STILi100EEC2Ev4856// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(912) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {4857// OMP-DEfAULT-NEXT:  entry:4858// OMP-DEfAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 44859// OMP-DEfAULT-NEXT:    [[A:%.*]] = alloca i32, align 44860// OMP-DEfAULT-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 44861// OMP-DEfAULT-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 44862// OMP-DEfAULT-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 44863// OMP-DEfAULT-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 44864// OMP-DEfAULT-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 84865// OMP-DEfAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 44866// OMP-DEfAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 44867// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 44868// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 44869// OMP-DEfAULT-NEXT:    store i32 [[TMP1]], ptr [[A]], align 44870// OMP-DEfAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 44871// OMP-DEfAULT-NEXT:    store i32 [[TMP2]], ptr [[A_CASTED]], align 44872// OMP-DEfAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A_CASTED]], align 44873// OMP-DEfAULT-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 04874// OMP-DEfAULT-NEXT:    store i32 [[TMP3]], ptr [[TMP4]], align 44875// OMP-DEfAULT-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 04876// OMP-DEfAULT-NEXT:    store i32 [[TMP3]], ptr [[TMP5]], align 44877// OMP-DEfAULT-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 04878// OMP-DEfAULT-NEXT:    store ptr null, ptr [[TMP6]], align 44879// OMP-DEfAULT-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 04880// OMP-DEfAULT-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 04881// OMP-DEfAULT-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 04882// OMP-DEfAULT-NEXT:    store i32 3, ptr [[TMP9]], align 44883// OMP-DEfAULT-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 14884// OMP-DEfAULT-NEXT:    store i32 1, ptr [[TMP10]], align 44885// OMP-DEfAULT-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 24886// OMP-DEfAULT-NEXT:    store ptr [[TMP7]], ptr [[TMP11]], align 44887// OMP-DEfAULT-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 34888// OMP-DEfAULT-NEXT:    store ptr [[TMP8]], ptr [[TMP12]], align 44889// OMP-DEfAULT-NEXT:    [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 44890// OMP-DEfAULT-NEXT:    store ptr @.offload_sizes.14, ptr [[TMP13]], align 44891// OMP-DEfAULT-NEXT:    [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 54892// OMP-DEfAULT-NEXT:    store ptr @.offload_maptypes.15, ptr [[TMP14]], align 44893// OMP-DEfAULT-NEXT:    [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 64894// OMP-DEfAULT-NEXT:    store ptr null, ptr [[TMP15]], align 44895// OMP-DEfAULT-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 74896// OMP-DEfAULT-NEXT:    store ptr null, ptr [[TMP16]], align 44897// OMP-DEfAULT-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 84898// OMP-DEfAULT-NEXT:    store i64 0, ptr [[TMP17]], align 84899// OMP-DEfAULT-NEXT:    [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 94900// OMP-DEfAULT-NEXT:    store i64 0, ptr [[TMP18]], align 84901// OMP-DEfAULT-NEXT:    [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 104902// OMP-DEfAULT-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP19]], align 44903// OMP-DEfAULT-NEXT:    [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 114904// OMP-DEfAULT-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP20]], align 44905// OMP-DEfAULT-NEXT:    [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 124906// OMP-DEfAULT-NEXT:    store i32 0, ptr [[TMP21]], align 44907// OMP-DEfAULT-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi100EEC1Ev_l218.region_id, ptr [[KERNEL_ARGS]])4908// OMP-DEfAULT-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 04909// OMP-DEfAULT-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]4910// OMP-DEfAULT:       omp_offload.failed:4911// OMP-DEfAULT-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi100EEC1Ev_l218(i32 [[TMP3]]) #[[ATTR2]]4912// OMP-DEfAULT-NEXT:    br label [[OMP_OFFLOAD_CONT]]4913// OMP-DEfAULT:       omp_offload.cont:4914// OMP-DEfAULT-NEXT:    [[TMP24:%.*]] = load i32, ptr [[A]], align 44915// OMP-DEfAULT-NEXT:    [[TMP25:%.*]] = load ptr, ptr @R, align 44916// OMP-DEfAULT-NEXT:    store i32 [[TMP24]], ptr [[TMP25]], align 44917// OMP-DEfAULT-NEXT:    ret void4918//4919//4920// OMP-DEfAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi100EEC1Ev_l2184921// OMP-DEfAULT-SAME: (i32 noundef [[A:%.*]]) #[[ATTR3]] {4922// OMP-DEfAULT-NEXT:  entry:4923// OMP-DEfAULT-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 44924// OMP-DEfAULT-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 44925// OMP-DEfAULT-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 44926// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 44927// OMP-DEfAULT-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 44928// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 44929// OMP-DEfAULT-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi100EEC1Ev_l218.omp_outlined, i32 [[TMP1]])4930// OMP-DEfAULT-NEXT:    ret void4931//4932//4933// OMP-DEfAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi100EEC1Ev_l218.omp_outlined4934// OMP-DEfAULT-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] {4935// OMP-DEfAULT-NEXT:  entry:4936// OMP-DEfAULT-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 44937// OMP-DEfAULT-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 44938// OMP-DEfAULT-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 44939// OMP-DEfAULT-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 44940// OMP-DEfAULT-NEXT:    [[TMP:%.*]] = alloca i32, align 44941// OMP-DEfAULT-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 44942// OMP-DEfAULT-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 44943// OMP-DEfAULT-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 44944// OMP-DEfAULT-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 44945// OMP-DEfAULT-NEXT:    [[I:%.*]] = alloca i32, align 44946// OMP-DEfAULT-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 44947// OMP-DEfAULT-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 44948// OMP-DEfAULT-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 44949// OMP-DEfAULT-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 44950// OMP-DEfAULT-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 44951// OMP-DEfAULT-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 44952// OMP-DEfAULT-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 44953// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 44954// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 44955// OMP-DEfAULT-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)4956// OMP-DEfAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44957// OMP-DEfAULT-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 94958// OMP-DEfAULT-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]4959// OMP-DEfAULT:       cond.true:4960// OMP-DEfAULT-NEXT:    br label [[COND_END:%.*]]4961// OMP-DEfAULT:       cond.false:4962// OMP-DEfAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44963// OMP-DEfAULT-NEXT:    br label [[COND_END]]4964// OMP-DEfAULT:       cond.end:4965// OMP-DEfAULT-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]4966// OMP-DEfAULT-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 44967// OMP-DEfAULT-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 44968// OMP-DEfAULT-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 44969// OMP-DEfAULT-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]4970// OMP-DEfAULT:       omp.inner.for.cond:4971// OMP-DEfAULT-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44972// OMP-DEfAULT-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44973// OMP-DEfAULT-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]4974// OMP-DEfAULT-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]4975// OMP-DEfAULT:       omp.inner.for.body:4976// OMP-DEfAULT-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44977// OMP-DEfAULT-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 14978// OMP-DEfAULT-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]4979// OMP-DEfAULT-NEXT:    store i32 [[ADD]], ptr [[I]], align 44980// OMP-DEfAULT-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 44981// OMP-DEfAULT-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1174982// OMP-DEfAULT-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 44983// OMP-DEfAULT-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]4984// OMP-DEfAULT:       omp.body.continue:4985// OMP-DEfAULT-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]4986// OMP-DEfAULT:       omp.inner.for.inc:4987// OMP-DEfAULT-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44988// OMP-DEfAULT-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 14989// OMP-DEfAULT-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 44990// OMP-DEfAULT-NEXT:    br label [[OMP_INNER_FOR_COND]]4991// OMP-DEfAULT:       omp.inner.for.end:4992// OMP-DEfAULT-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]4993// OMP-DEfAULT:       omp.loop.exit:4994// OMP-DEfAULT-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])4995// OMP-DEfAULT-NEXT:    ret void4996//4997//4998// OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2STILi100EED2Ev4999// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(912) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {5000// OMP-DEfAULT-NEXT:  entry:5001// OMP-DEfAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 45002// OMP-DEfAULT-NEXT:    [[A:%.*]] = alloca i32, align 45003// OMP-DEfAULT-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 45004// OMP-DEfAULT-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 45005// OMP-DEfAULT-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 45006// OMP-DEfAULT-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 45007// OMP-DEfAULT-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 85008// OMP-DEfAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 45009// OMP-DEfAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 45010// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 45011// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 45012// OMP-DEfAULT-NEXT:    store i32 [[TMP1]], ptr [[A]], align 45013// OMP-DEfAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 45014// OMP-DEfAULT-NEXT:    store i32 [[TMP2]], ptr [[A_CASTED]], align 45015// OMP-DEfAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A_CASTED]], align 45016// OMP-DEfAULT-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 05017// OMP-DEfAULT-NEXT:    store i32 [[TMP3]], ptr [[TMP4]], align 45018// OMP-DEfAULT-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 05019// OMP-DEfAULT-NEXT:    store i32 [[TMP3]], ptr [[TMP5]], align 45020// OMP-DEfAULT-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 05021// OMP-DEfAULT-NEXT:    store ptr null, ptr [[TMP6]], align 45022// OMP-DEfAULT-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 05023// OMP-DEfAULT-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 05024// OMP-DEfAULT-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 05025// OMP-DEfAULT-NEXT:    store i32 3, ptr [[TMP9]], align 45026// OMP-DEfAULT-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 15027// OMP-DEfAULT-NEXT:    store i32 1, ptr [[TMP10]], align 45028// OMP-DEfAULT-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 25029// OMP-DEfAULT-NEXT:    store ptr [[TMP7]], ptr [[TMP11]], align 45030// OMP-DEfAULT-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 35031// OMP-DEfAULT-NEXT:    store ptr [[TMP8]], ptr [[TMP12]], align 45032// OMP-DEfAULT-NEXT:    [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 45033// OMP-DEfAULT-NEXT:    store ptr @.offload_sizes.16, ptr [[TMP13]], align 45034// OMP-DEfAULT-NEXT:    [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 55035// OMP-DEfAULT-NEXT:    store ptr @.offload_maptypes.17, ptr [[TMP14]], align 45036// OMP-DEfAULT-NEXT:    [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 65037// OMP-DEfAULT-NEXT:    store ptr null, ptr [[TMP15]], align 45038// OMP-DEfAULT-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 75039// OMP-DEfAULT-NEXT:    store ptr null, ptr [[TMP16]], align 45040// OMP-DEfAULT-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 85041// OMP-DEfAULT-NEXT:    store i64 0, ptr [[TMP17]], align 85042// OMP-DEfAULT-NEXT:    [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 95043// OMP-DEfAULT-NEXT:    store i64 0, ptr [[TMP18]], align 85044// OMP-DEfAULT-NEXT:    [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 105045// OMP-DEfAULT-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP19]], align 45046// OMP-DEfAULT-NEXT:    [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 115047// OMP-DEfAULT-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP20]], align 45048// OMP-DEfAULT-NEXT:    [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 125049// OMP-DEfAULT-NEXT:    store i32 0, ptr [[TMP21]], align 45050// OMP-DEfAULT-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi100EED1Ev_l225.region_id, ptr [[KERNEL_ARGS]])5051// OMP-DEfAULT-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 05052// OMP-DEfAULT-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]5053// OMP-DEfAULT:       omp_offload.failed:5054// OMP-DEfAULT-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi100EED1Ev_l225(i32 [[TMP3]]) #[[ATTR2]]5055// OMP-DEfAULT-NEXT:    br label [[OMP_OFFLOAD_CONT]]5056// OMP-DEfAULT:       omp_offload.cont:5057// OMP-DEfAULT-NEXT:    [[TMP24:%.*]] = load i32, ptr [[A]], align 45058// OMP-DEfAULT-NEXT:    [[TMP25:%.*]] = load ptr, ptr @R, align 45059// OMP-DEfAULT-NEXT:    store i32 [[TMP24]], ptr [[TMP25]], align 45060// OMP-DEfAULT-NEXT:    ret void5061//5062//5063// OMP-DEfAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi100EED1Ev_l2255064// OMP-DEfAULT-SAME: (i32 noundef [[A:%.*]]) #[[ATTR3]] {5065// OMP-DEfAULT-NEXT:  entry:5066// OMP-DEfAULT-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 45067// OMP-DEfAULT-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 45068// OMP-DEfAULT-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 45069// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 45070// OMP-DEfAULT-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 45071// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 45072// OMP-DEfAULT-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi100EED1Ev_l225.omp_outlined, i32 [[TMP1]])5073// OMP-DEfAULT-NEXT:    ret void5074//5075//5076// OMP-DEfAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi100EED1Ev_l225.omp_outlined5077// OMP-DEfAULT-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] {5078// OMP-DEfAULT-NEXT:  entry:5079// OMP-DEfAULT-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 45080// OMP-DEfAULT-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 45081// OMP-DEfAULT-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 45082// OMP-DEfAULT-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 45083// OMP-DEfAULT-NEXT:    [[TMP:%.*]] = alloca i32, align 45084// OMP-DEfAULT-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 45085// OMP-DEfAULT-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 45086// OMP-DEfAULT-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 45087// OMP-DEfAULT-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 45088// OMP-DEfAULT-NEXT:    [[I:%.*]] = alloca i32, align 45089// OMP-DEfAULT-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 45090// OMP-DEfAULT-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 45091// OMP-DEfAULT-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 45092// OMP-DEfAULT-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 45093// OMP-DEfAULT-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 45094// OMP-DEfAULT-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 45095// OMP-DEfAULT-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 45096// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 45097// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 45098// OMP-DEfAULT-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)5099// OMP-DEfAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 45100// OMP-DEfAULT-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 95101// OMP-DEfAULT-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]5102// OMP-DEfAULT:       cond.true:5103// OMP-DEfAULT-NEXT:    br label [[COND_END:%.*]]5104// OMP-DEfAULT:       cond.false:5105// OMP-DEfAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 45106// OMP-DEfAULT-NEXT:    br label [[COND_END]]5107// OMP-DEfAULT:       cond.end:5108// OMP-DEfAULT-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]5109// OMP-DEfAULT-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 45110// OMP-DEfAULT-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 45111// OMP-DEfAULT-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 45112// OMP-DEfAULT-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]5113// OMP-DEfAULT:       omp.inner.for.cond:5114// OMP-DEfAULT-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 45115// OMP-DEfAULT-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 45116// OMP-DEfAULT-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]5117// OMP-DEfAULT-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]5118// OMP-DEfAULT:       omp.inner.for.body:5119// OMP-DEfAULT-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 45120// OMP-DEfAULT-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 15121// OMP-DEfAULT-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]5122// OMP-DEfAULT-NEXT:    store i32 [[ADD]], ptr [[I]], align 45123// OMP-DEfAULT-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 45124// OMP-DEfAULT-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1185125// OMP-DEfAULT-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 45126// OMP-DEfAULT-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]5127// OMP-DEfAULT:       omp.body.continue:5128// OMP-DEfAULT-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]5129// OMP-DEfAULT:       omp.inner.for.inc:5130// OMP-DEfAULT-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 45131// OMP-DEfAULT-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 15132// OMP-DEfAULT-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 45133// OMP-DEfAULT-NEXT:    br label [[OMP_INNER_FOR_COND]]5134// OMP-DEfAULT:       omp.inner.for.end:5135// OMP-DEfAULT-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]5136// OMP-DEfAULT:       omp.loop.exit:5137// OMP-DEfAULT-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])5138// OMP-DEfAULT-NEXT:    ret void5139//5140//5141// OMP-DEfAULT-LABEL: define {{[^@]+}}@__cxx_global_var_init.185142// OMP-DEfAULT-SAME: () #[[ATTR0]] {5143// OMP-DEfAULT-NEXT:  entry:5144// OMP-DEfAULT-NEXT:    call void @_ZN2STILi1000EEC1Ev(ptr noundef nonnull align 4 dereferenceable(4512) @t2)5145// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2STILi1000EED1Ev, ptr @t2, ptr @__dso_handle) #[[ATTR2]]5146// OMP-DEfAULT-NEXT:    ret void5147//5148//5149// OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2STILi1000EEC1Ev5150// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(4512) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {5151// OMP-DEfAULT-NEXT:  entry:5152// OMP-DEfAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 45153// OMP-DEfAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 45154// OMP-DEfAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 45155// OMP-DEfAULT-NEXT:    call void @_ZN2STILi1000EEC2Ev(ptr noundef nonnull align 4 dereferenceable(4512) [[THIS1]])5156// OMP-DEfAULT-NEXT:    ret void5157//5158//5159// OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2STILi1000EED1Ev5160// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(4512) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {5161// OMP-DEfAULT-NEXT:  entry:5162// OMP-DEfAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 45163// OMP-DEfAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 45164// OMP-DEfAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 45165// OMP-DEfAULT-NEXT:    call void @_ZN2STILi1000EED2Ev(ptr noundef nonnull align 4 dereferenceable(4512) [[THIS1]]) #[[ATTR2]]5166// OMP-DEfAULT-NEXT:    ret void5167//5168//5169// OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2STILi1000EEC2Ev5170// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(4512) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {5171// OMP-DEfAULT-NEXT:  entry:5172// OMP-DEfAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 45173// OMP-DEfAULT-NEXT:    [[A:%.*]] = alloca i32, align 45174// OMP-DEfAULT-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 45175// OMP-DEfAULT-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 45176// OMP-DEfAULT-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 45177// OMP-DEfAULT-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 45178// OMP-DEfAULT-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 85179// OMP-DEfAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 45180// OMP-DEfAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 45181// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 45182// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 45183// OMP-DEfAULT-NEXT:    store i32 [[TMP1]], ptr [[A]], align 45184// OMP-DEfAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 45185// OMP-DEfAULT-NEXT:    store i32 [[TMP2]], ptr [[A_CASTED]], align 45186// OMP-DEfAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A_CASTED]], align 45187// OMP-DEfAULT-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 05188// OMP-DEfAULT-NEXT:    store i32 [[TMP3]], ptr [[TMP4]], align 45189// OMP-DEfAULT-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 05190// OMP-DEfAULT-NEXT:    store i32 [[TMP3]], ptr [[TMP5]], align 45191// OMP-DEfAULT-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 05192// OMP-DEfAULT-NEXT:    store ptr null, ptr [[TMP6]], align 45193// OMP-DEfAULT-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 05194// OMP-DEfAULT-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 05195// OMP-DEfAULT-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 05196// OMP-DEfAULT-NEXT:    store i32 3, ptr [[TMP9]], align 45197// OMP-DEfAULT-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 15198// OMP-DEfAULT-NEXT:    store i32 1, ptr [[TMP10]], align 45199// OMP-DEfAULT-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 25200// OMP-DEfAULT-NEXT:    store ptr [[TMP7]], ptr [[TMP11]], align 45201// OMP-DEfAULT-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 35202// OMP-DEfAULT-NEXT:    store ptr [[TMP8]], ptr [[TMP12]], align 45203// OMP-DEfAULT-NEXT:    [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 45204// OMP-DEfAULT-NEXT:    store ptr @.offload_sizes.19, ptr [[TMP13]], align 45205// OMP-DEfAULT-NEXT:    [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 55206// OMP-DEfAULT-NEXT:    store ptr @.offload_maptypes.20, ptr [[TMP14]], align 45207// OMP-DEfAULT-NEXT:    [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 65208// OMP-DEfAULT-NEXT:    store ptr null, ptr [[TMP15]], align 45209// OMP-DEfAULT-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 75210// OMP-DEfAULT-NEXT:    store ptr null, ptr [[TMP16]], align 45211// OMP-DEfAULT-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 85212// OMP-DEfAULT-NEXT:    store i64 0, ptr [[TMP17]], align 85213// OMP-DEfAULT-NEXT:    [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 95214// OMP-DEfAULT-NEXT:    store i64 0, ptr [[TMP18]], align 85215// OMP-DEfAULT-NEXT:    [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 105216// OMP-DEfAULT-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP19]], align 45217// OMP-DEfAULT-NEXT:    [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 115218// OMP-DEfAULT-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP20]], align 45219// OMP-DEfAULT-NEXT:    [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 125220// OMP-DEfAULT-NEXT:    store i32 0, ptr [[TMP21]], align 45221// OMP-DEfAULT-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi1000EEC1Ev_l218.region_id, ptr [[KERNEL_ARGS]])5222// OMP-DEfAULT-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 05223// OMP-DEfAULT-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]5224// OMP-DEfAULT:       omp_offload.failed:5225// OMP-DEfAULT-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi1000EEC1Ev_l218(i32 [[TMP3]]) #[[ATTR2]]5226// OMP-DEfAULT-NEXT:    br label [[OMP_OFFLOAD_CONT]]5227// OMP-DEfAULT:       omp_offload.cont:5228// OMP-DEfAULT-NEXT:    [[TMP24:%.*]] = load i32, ptr [[A]], align 45229// OMP-DEfAULT-NEXT:    [[TMP25:%.*]] = load ptr, ptr @R, align 45230// OMP-DEfAULT-NEXT:    store i32 [[TMP24]], ptr [[TMP25]], align 45231// OMP-DEfAULT-NEXT:    ret void5232//5233//5234// OMP-DEfAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi1000EEC1Ev_l2185235// OMP-DEfAULT-SAME: (i32 noundef [[A:%.*]]) #[[ATTR3]] {5236// OMP-DEfAULT-NEXT:  entry:5237// OMP-DEfAULT-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 45238// OMP-DEfAULT-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 45239// OMP-DEfAULT-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 45240// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 45241// OMP-DEfAULT-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 45242// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 45243// OMP-DEfAULT-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi1000EEC1Ev_l218.omp_outlined, i32 [[TMP1]])5244// OMP-DEfAULT-NEXT:    ret void5245//5246//5247// OMP-DEfAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi1000EEC1Ev_l218.omp_outlined5248// OMP-DEfAULT-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] {5249// OMP-DEfAULT-NEXT:  entry:5250// OMP-DEfAULT-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 45251// OMP-DEfAULT-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 45252// OMP-DEfAULT-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 45253// OMP-DEfAULT-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 45254// OMP-DEfAULT-NEXT:    [[TMP:%.*]] = alloca i32, align 45255// OMP-DEfAULT-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 45256// OMP-DEfAULT-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 45257// OMP-DEfAULT-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 45258// OMP-DEfAULT-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 45259// OMP-DEfAULT-NEXT:    [[I:%.*]] = alloca i32, align 45260// OMP-DEfAULT-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 45261// OMP-DEfAULT-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 45262// OMP-DEfAULT-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 45263// OMP-DEfAULT-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 45264// OMP-DEfAULT-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 45265// OMP-DEfAULT-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 45266// OMP-DEfAULT-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 45267// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 45268// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 45269// OMP-DEfAULT-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)5270// OMP-DEfAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 45271// OMP-DEfAULT-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 95272// OMP-DEfAULT-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]5273// OMP-DEfAULT:       cond.true:5274// OMP-DEfAULT-NEXT:    br label [[COND_END:%.*]]5275// OMP-DEfAULT:       cond.false:5276// OMP-DEfAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 45277// OMP-DEfAULT-NEXT:    br label [[COND_END]]5278// OMP-DEfAULT:       cond.end:5279// OMP-DEfAULT-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]5280// OMP-DEfAULT-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 45281// OMP-DEfAULT-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 45282// OMP-DEfAULT-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 45283// OMP-DEfAULT-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]5284// OMP-DEfAULT:       omp.inner.for.cond:5285// OMP-DEfAULT-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 45286// OMP-DEfAULT-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 45287// OMP-DEfAULT-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]5288// OMP-DEfAULT-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]5289// OMP-DEfAULT:       omp.inner.for.body:5290// OMP-DEfAULT-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 45291// OMP-DEfAULT-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 15292// OMP-DEfAULT-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]5293// OMP-DEfAULT-NEXT:    store i32 [[ADD]], ptr [[I]], align 45294// OMP-DEfAULT-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 45295// OMP-DEfAULT-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 10175296// OMP-DEfAULT-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 45297// OMP-DEfAULT-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]5298// OMP-DEfAULT:       omp.body.continue:5299// OMP-DEfAULT-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]5300// OMP-DEfAULT:       omp.inner.for.inc:5301// OMP-DEfAULT-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 45302// OMP-DEfAULT-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 15303// OMP-DEfAULT-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 45304// OMP-DEfAULT-NEXT:    br label [[OMP_INNER_FOR_COND]]5305// OMP-DEfAULT:       omp.inner.for.end:5306// OMP-DEfAULT-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]5307// OMP-DEfAULT:       omp.loop.exit:5308// OMP-DEfAULT-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])5309// OMP-DEfAULT-NEXT:    ret void5310//5311//5312// OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2STILi1000EED2Ev5313// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(4512) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {5314// OMP-DEfAULT-NEXT:  entry:5315// OMP-DEfAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 45316// OMP-DEfAULT-NEXT:    [[A:%.*]] = alloca i32, align 45317// OMP-DEfAULT-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 45318// OMP-DEfAULT-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 45319// OMP-DEfAULT-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 45320// OMP-DEfAULT-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 45321// OMP-DEfAULT-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 85322// OMP-DEfAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 45323// OMP-DEfAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 45324// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 45325// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 45326// OMP-DEfAULT-NEXT:    store i32 [[TMP1]], ptr [[A]], align 45327// OMP-DEfAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 45328// OMP-DEfAULT-NEXT:    store i32 [[TMP2]], ptr [[A_CASTED]], align 45329// OMP-DEfAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A_CASTED]], align 45330// OMP-DEfAULT-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 05331// OMP-DEfAULT-NEXT:    store i32 [[TMP3]], ptr [[TMP4]], align 45332// OMP-DEfAULT-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 05333// OMP-DEfAULT-NEXT:    store i32 [[TMP3]], ptr [[TMP5]], align 45334// OMP-DEfAULT-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 05335// OMP-DEfAULT-NEXT:    store ptr null, ptr [[TMP6]], align 45336// OMP-DEfAULT-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 05337// OMP-DEfAULT-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 05338// OMP-DEfAULT-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 05339// OMP-DEfAULT-NEXT:    store i32 3, ptr [[TMP9]], align 45340// OMP-DEfAULT-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 15341// OMP-DEfAULT-NEXT:    store i32 1, ptr [[TMP10]], align 45342// OMP-DEfAULT-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 25343// OMP-DEfAULT-NEXT:    store ptr [[TMP7]], ptr [[TMP11]], align 45344// OMP-DEfAULT-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 35345// OMP-DEfAULT-NEXT:    store ptr [[TMP8]], ptr [[TMP12]], align 45346// OMP-DEfAULT-NEXT:    [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 45347// OMP-DEfAULT-NEXT:    store ptr @.offload_sizes.21, ptr [[TMP13]], align 45348// OMP-DEfAULT-NEXT:    [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 55349// OMP-DEfAULT-NEXT:    store ptr @.offload_maptypes.22, ptr [[TMP14]], align 45350// OMP-DEfAULT-NEXT:    [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 65351// OMP-DEfAULT-NEXT:    store ptr null, ptr [[TMP15]], align 45352// OMP-DEfAULT-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 75353// OMP-DEfAULT-NEXT:    store ptr null, ptr [[TMP16]], align 45354// OMP-DEfAULT-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 85355// OMP-DEfAULT-NEXT:    store i64 0, ptr [[TMP17]], align 85356// OMP-DEfAULT-NEXT:    [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 95357// OMP-DEfAULT-NEXT:    store i64 0, ptr [[TMP18]], align 85358// OMP-DEfAULT-NEXT:    [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 105359// OMP-DEfAULT-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP19]], align 45360// OMP-DEfAULT-NEXT:    [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 115361// OMP-DEfAULT-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP20]], align 45362// OMP-DEfAULT-NEXT:    [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 125363// OMP-DEfAULT-NEXT:    store i32 0, ptr [[TMP21]], align 45364// OMP-DEfAULT-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi1000EED1Ev_l225.region_id, ptr [[KERNEL_ARGS]])5365// OMP-DEfAULT-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 05366// OMP-DEfAULT-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]5367// OMP-DEfAULT:       omp_offload.failed:5368// OMP-DEfAULT-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi1000EED1Ev_l225(i32 [[TMP3]]) #[[ATTR2]]5369// OMP-DEfAULT-NEXT:    br label [[OMP_OFFLOAD_CONT]]5370// OMP-DEfAULT:       omp_offload.cont:5371// OMP-DEfAULT-NEXT:    [[TMP24:%.*]] = load i32, ptr [[A]], align 45372// OMP-DEfAULT-NEXT:    [[TMP25:%.*]] = load ptr, ptr @R, align 45373// OMP-DEfAULT-NEXT:    store i32 [[TMP24]], ptr [[TMP25]], align 45374// OMP-DEfAULT-NEXT:    ret void5375//5376//5377// OMP-DEfAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi1000EED1Ev_l2255378// OMP-DEfAULT-SAME: (i32 noundef [[A:%.*]]) #[[ATTR3]] {5379// OMP-DEfAULT-NEXT:  entry:5380// OMP-DEfAULT-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 45381// OMP-DEfAULT-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 45382// OMP-DEfAULT-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 45383// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 45384// OMP-DEfAULT-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 45385// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 45386// OMP-DEfAULT-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi1000EED1Ev_l225.omp_outlined, i32 [[TMP1]])5387// OMP-DEfAULT-NEXT:    ret void5388//5389//5390// OMP-DEfAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi1000EED1Ev_l225.omp_outlined5391// OMP-DEfAULT-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] {5392// OMP-DEfAULT-NEXT:  entry:5393// OMP-DEfAULT-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 45394// OMP-DEfAULT-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 45395// OMP-DEfAULT-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 45396// OMP-DEfAULT-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 45397// OMP-DEfAULT-NEXT:    [[TMP:%.*]] = alloca i32, align 45398// OMP-DEfAULT-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 45399// OMP-DEfAULT-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 45400// OMP-DEfAULT-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 45401// OMP-DEfAULT-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 45402// OMP-DEfAULT-NEXT:    [[I:%.*]] = alloca i32, align 45403// OMP-DEfAULT-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 45404// OMP-DEfAULT-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 45405// OMP-DEfAULT-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 45406// OMP-DEfAULT-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 45407// OMP-DEfAULT-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 45408// OMP-DEfAULT-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 45409// OMP-DEfAULT-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 45410// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 45411// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 45412// OMP-DEfAULT-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)5413// OMP-DEfAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 45414// OMP-DEfAULT-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 95415// OMP-DEfAULT-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]5416// OMP-DEfAULT:       cond.true:5417// OMP-DEfAULT-NEXT:    br label [[COND_END:%.*]]5418// OMP-DEfAULT:       cond.false:5419// OMP-DEfAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 45420// OMP-DEfAULT-NEXT:    br label [[COND_END]]5421// OMP-DEfAULT:       cond.end:5422// OMP-DEfAULT-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]5423// OMP-DEfAULT-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 45424// OMP-DEfAULT-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 45425// OMP-DEfAULT-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 45426// OMP-DEfAULT-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]5427// OMP-DEfAULT:       omp.inner.for.cond:5428// OMP-DEfAULT-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 45429// OMP-DEfAULT-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 45430// OMP-DEfAULT-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]5431// OMP-DEfAULT-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]5432// OMP-DEfAULT:       omp.inner.for.body:5433// OMP-DEfAULT-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 45434// OMP-DEfAULT-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 15435// OMP-DEfAULT-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]5436// OMP-DEfAULT-NEXT:    store i32 [[ADD]], ptr [[I]], align 45437// OMP-DEfAULT-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 45438// OMP-DEfAULT-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 10185439// OMP-DEfAULT-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 45440// OMP-DEfAULT-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]5441// OMP-DEfAULT:       omp.body.continue:5442// OMP-DEfAULT-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]5443// OMP-DEfAULT:       omp.inner.for.inc:5444// OMP-DEfAULT-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 45445// OMP-DEfAULT-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 15446// OMP-DEfAULT-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 45447// OMP-DEfAULT-NEXT:    br label [[OMP_INNER_FOR_COND]]5448// OMP-DEfAULT:       omp.inner.for.end:5449// OMP-DEfAULT-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]5450// OMP-DEfAULT:       omp.loop.exit:5451// OMP-DEfAULT-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])5452// OMP-DEfAULT-NEXT:    ret void5453//5454//5455// OMP-DEfAULT-LABEL: define {{[^@]+}}@_Z3bari5456// OMP-DEfAULT-SAME: (i32 noundef [[A:%.*]]) #[[ATTR1]] {5457// OMP-DEfAULT-NEXT:  entry:5458// OMP-DEfAULT-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 45459// OMP-DEfAULT-NEXT:    [[R:%.*]] = alloca i32, align 45460// OMP-DEfAULT-NEXT:    [[R_CASTED:%.*]] = alloca i32, align 45461// OMP-DEfAULT-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 45462// OMP-DEfAULT-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 45463// OMP-DEfAULT-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 45464// OMP-DEfAULT-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 85465// OMP-DEfAULT-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 45466// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 45467// OMP-DEfAULT-NEXT:    store i32 [[TMP0]], ptr [[R]], align 45468// OMP-DEfAULT-NEXT:    call void @_ZN2SA3fooEv(ptr noundef nonnull align 4 dereferenceable(16) @_ZL2a1)5469// OMP-DEfAULT-NEXT:    call void @_ZN2SA3fooEv(ptr noundef nonnull align 4 dereferenceable(16) @a2)5470// OMP-DEfAULT-NEXT:    call void @_ZN2SB3fooEv(ptr noundef nonnull align 4 dereferenceable(32) @b1)5471// OMP-DEfAULT-NEXT:    call void @_ZN2SB3fooEv(ptr noundef nonnull align 4 dereferenceable(32) @b2)5472// OMP-DEfAULT-NEXT:    call void @_ZN2SC3fooEv(ptr noundef nonnull align 4 dereferenceable(64) @_ZL2c1)5473// OMP-DEfAULT-NEXT:    call void @_ZN2SD3fooEv(ptr noundef nonnull align 4 dereferenceable(128) @d1)5474// OMP-DEfAULT-NEXT:    call void @_ZN2SE3fooEv(ptr noundef nonnull align 4 dereferenceable(256) @e1)5475// OMP-DEfAULT-NEXT:    call void @_ZN2STILi100EE3fooEv(ptr noundef nonnull align 4 dereferenceable(912) @t1)5476// OMP-DEfAULT-NEXT:    call void @_ZN2STILi1000EE3fooEv(ptr noundef nonnull align 4 dereferenceable(4512) @t2)5477// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[R]], align 45478// OMP-DEfAULT-NEXT:    store i32 [[TMP1]], ptr [[R_CASTED]], align 45479// OMP-DEfAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[R_CASTED]], align 45480// OMP-DEfAULT-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 05481// OMP-DEfAULT-NEXT:    store i32 [[TMP2]], ptr [[TMP3]], align 45482// OMP-DEfAULT-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 05483// OMP-DEfAULT-NEXT:    store i32 [[TMP2]], ptr [[TMP4]], align 45484// OMP-DEfAULT-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 05485// OMP-DEfAULT-NEXT:    store ptr null, ptr [[TMP5]], align 45486// OMP-DEfAULT-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 05487// OMP-DEfAULT-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 05488// OMP-DEfAULT-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 05489// OMP-DEfAULT-NEXT:    store i32 3, ptr [[TMP8]], align 45490// OMP-DEfAULT-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 15491// OMP-DEfAULT-NEXT:    store i32 1, ptr [[TMP9]], align 45492// OMP-DEfAULT-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 25493// OMP-DEfAULT-NEXT:    store ptr [[TMP6]], ptr [[TMP10]], align 45494// OMP-DEfAULT-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 35495// OMP-DEfAULT-NEXT:    store ptr [[TMP7]], ptr [[TMP11]], align 45496// OMP-DEfAULT-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 45497// OMP-DEfAULT-NEXT:    store ptr @.offload_sizes.23, ptr [[TMP12]], align 45498// OMP-DEfAULT-NEXT:    [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 55499// OMP-DEfAULT-NEXT:    store ptr @.offload_maptypes.24, ptr [[TMP13]], align 45500// OMP-DEfAULT-NEXT:    [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 65501// OMP-DEfAULT-NEXT:    store ptr null, ptr [[TMP14]], align 45502// OMP-DEfAULT-NEXT:    [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 75503// OMP-DEfAULT-NEXT:    store ptr null, ptr [[TMP15]], align 45504// OMP-DEfAULT-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 85505// OMP-DEfAULT-NEXT:    store i64 0, ptr [[TMP16]], align 85506// OMP-DEfAULT-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 95507// OMP-DEfAULT-NEXT:    store i64 0, ptr [[TMP17]], align 85508// OMP-DEfAULT-NEXT:    [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 105509// OMP-DEfAULT-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP18]], align 45510// OMP-DEfAULT-NEXT:    [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 115511// OMP-DEfAULT-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP19]], align 45512// OMP-DEfAULT-NEXT:    [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 125513// OMP-DEfAULT-NEXT:    store i32 0, ptr [[TMP20]], align 45514// OMP-DEfAULT-NEXT:    [[TMP21:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3bari_l267.region_id, ptr [[KERNEL_ARGS]])5515// OMP-DEfAULT-NEXT:    [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 05516// OMP-DEfAULT-NEXT:    br i1 [[TMP22]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]5517// OMP-DEfAULT:       omp_offload.failed:5518// OMP-DEfAULT-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3bari_l267(i32 [[TMP2]]) #[[ATTR2]]5519// OMP-DEfAULT-NEXT:    br label [[OMP_OFFLOAD_CONT]]5520// OMP-DEfAULT:       omp_offload.cont:5521// OMP-DEfAULT-NEXT:    [[TMP23:%.*]] = load i32, ptr [[R]], align 45522// OMP-DEfAULT-NEXT:    [[TMP24:%.*]] = load ptr, ptr @R, align 45523// OMP-DEfAULT-NEXT:    [[TMP25:%.*]] = load i32, ptr [[TMP24]], align 45524// OMP-DEfAULT-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP23]], [[TMP25]]5525// OMP-DEfAULT-NEXT:    ret i32 [[ADD]]5526//5527//5528// OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2SA3fooEv5529// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(16) [[THIS:%.*]]) #[[ATTR1]] comdat align 2 {5530// OMP-DEfAULT-NEXT:  entry:5531// OMP-DEfAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 45532// OMP-DEfAULT-NEXT:    [[A:%.*]] = alloca i32, align 45533// OMP-DEfAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 45534// OMP-DEfAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 45535// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 45536// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 45537// OMP-DEfAULT-NEXT:    store i32 [[TMP1]], ptr [[A]], align 45538// OMP-DEfAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 45539// OMP-DEfAULT-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP2]], 15540// OMP-DEfAULT-NEXT:    store i32 [[ADD]], ptr [[A]], align 45541// OMP-DEfAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 45542// OMP-DEfAULT-NEXT:    [[TMP4:%.*]] = load ptr, ptr @R, align 45543// OMP-DEfAULT-NEXT:    store i32 [[TMP3]], ptr [[TMP4]], align 45544// OMP-DEfAULT-NEXT:    ret void5545//5546//5547// OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2SB3fooEv5548// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(32) [[THIS:%.*]]) #[[ATTR1]] comdat align 2 {5549// OMP-DEfAULT-NEXT:  entry:5550// OMP-DEfAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 45551// OMP-DEfAULT-NEXT:    [[A:%.*]] = alloca i32, align 45552// OMP-DEfAULT-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 45553// OMP-DEfAULT-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 45554// OMP-DEfAULT-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 45555// OMP-DEfAULT-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 45556// OMP-DEfAULT-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 85557// OMP-DEfAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 45558// OMP-DEfAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 45559// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 45560// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 45561// OMP-DEfAULT-NEXT:    store i32 [[TMP1]], ptr [[A]], align 45562// OMP-DEfAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 45563// OMP-DEfAULT-NEXT:    store i32 [[TMP2]], ptr [[A_CASTED]], align 45564// OMP-DEfAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A_CASTED]], align 45565// OMP-DEfAULT-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 05566// OMP-DEfAULT-NEXT:    store i32 [[TMP3]], ptr [[TMP4]], align 45567// OMP-DEfAULT-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 05568// OMP-DEfAULT-NEXT:    store i32 [[TMP3]], ptr [[TMP5]], align 45569// OMP-DEfAULT-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 05570// OMP-DEfAULT-NEXT:    store ptr null, ptr [[TMP6]], align 45571// OMP-DEfAULT-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 05572// OMP-DEfAULT-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 05573// OMP-DEfAULT-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 05574// OMP-DEfAULT-NEXT:    store i32 3, ptr [[TMP9]], align 45575// OMP-DEfAULT-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 15576// OMP-DEfAULT-NEXT:    store i32 1, ptr [[TMP10]], align 45577// OMP-DEfAULT-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 25578// OMP-DEfAULT-NEXT:    store ptr [[TMP7]], ptr [[TMP11]], align 45579// OMP-DEfAULT-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 35580// OMP-DEfAULT-NEXT:    store ptr [[TMP8]], ptr [[TMP12]], align 45581// OMP-DEfAULT-NEXT:    [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 45582// OMP-DEfAULT-NEXT:    store ptr @.offload_sizes.25, ptr [[TMP13]], align 45583// OMP-DEfAULT-NEXT:    [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 55584// OMP-DEfAULT-NEXT:    store ptr @.offload_maptypes.26, ptr [[TMP14]], align 45585// OMP-DEfAULT-NEXT:    [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 65586// OMP-DEfAULT-NEXT:    store ptr null, ptr [[TMP15]], align 45587// OMP-DEfAULT-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 75588// OMP-DEfAULT-NEXT:    store ptr null, ptr [[TMP16]], align 45589// OMP-DEfAULT-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 85590// OMP-DEfAULT-NEXT:    store i64 0, ptr [[TMP17]], align 85591// OMP-DEfAULT-NEXT:    [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 95592// OMP-DEfAULT-NEXT:    store i64 0, ptr [[TMP18]], align 85593// OMP-DEfAULT-NEXT:    [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 105594// OMP-DEfAULT-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP19]], align 45595// OMP-DEfAULT-NEXT:    [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 115596// OMP-DEfAULT-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP20]], align 45597// OMP-DEfAULT-NEXT:    [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 125598// OMP-DEfAULT-NEXT:    store i32 0, ptr [[TMP21]], align 45599// OMP-DEfAULT-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SB3fooEv_l122.region_id, ptr [[KERNEL_ARGS]])5600// OMP-DEfAULT-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 05601// OMP-DEfAULT-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]5602// OMP-DEfAULT:       omp_offload.failed:5603// OMP-DEfAULT-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SB3fooEv_l122(i32 [[TMP3]]) #[[ATTR2]]5604// OMP-DEfAULT-NEXT:    br label [[OMP_OFFLOAD_CONT]]5605// OMP-DEfAULT:       omp_offload.cont:5606// OMP-DEfAULT-NEXT:    [[TMP24:%.*]] = load i32, ptr [[A]], align 45607// OMP-DEfAULT-NEXT:    [[TMP25:%.*]] = load ptr, ptr @R, align 45608// OMP-DEfAULT-NEXT:    store i32 [[TMP24]], ptr [[TMP25]], align 45609// OMP-DEfAULT-NEXT:    ret void5610//5611//5612// OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2SC3fooEv5613// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(64) [[THIS:%.*]]) #[[ATTR1]] comdat align 2 {5614// OMP-DEfAULT-NEXT:  entry:5615// OMP-DEfAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 45616// OMP-DEfAULT-NEXT:    [[A:%.*]] = alloca i32, align 45617// OMP-DEfAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 45618// OMP-DEfAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 45619// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 45620// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 45621// OMP-DEfAULT-NEXT:    store i32 [[TMP1]], ptr [[A]], align 45622// OMP-DEfAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 45623// OMP-DEfAULT-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP2]], 75624// OMP-DEfAULT-NEXT:    store i32 [[ADD]], ptr [[A]], align 45625// OMP-DEfAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 45626// OMP-DEfAULT-NEXT:    [[TMP4:%.*]] = load ptr, ptr @R, align 45627// OMP-DEfAULT-NEXT:    store i32 [[TMP3]], ptr [[TMP4]], align 45628// OMP-DEfAULT-NEXT:    ret void5629//5630//5631// OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2SD3fooEv5632// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(128) [[THIS:%.*]]) #[[ATTR1]] comdat align 2 {5633// OMP-DEfAULT-NEXT:  entry:5634// OMP-DEfAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 45635// OMP-DEfAULT-NEXT:    [[A:%.*]] = alloca i32, align 45636// OMP-DEfAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 45637// OMP-DEfAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 45638// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 45639// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 45640// OMP-DEfAULT-NEXT:    store i32 [[TMP1]], ptr [[A]], align 45641// OMP-DEfAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 45642// OMP-DEfAULT-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP2]], 105643// OMP-DEfAULT-NEXT:    store i32 [[ADD]], ptr [[A]], align 45644// OMP-DEfAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 45645// OMP-DEfAULT-NEXT:    [[TMP4:%.*]] = load ptr, ptr @R, align 45646// OMP-DEfAULT-NEXT:    store i32 [[TMP3]], ptr [[TMP4]], align 45647// OMP-DEfAULT-NEXT:    ret void5648//5649//5650// OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2SE3fooEv5651// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(256) [[THIS:%.*]]) #[[ATTR1]] comdat align 2 {5652// OMP-DEfAULT-NEXT:  entry:5653// OMP-DEfAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 45654// OMP-DEfAULT-NEXT:    [[A:%.*]] = alloca i32, align 45655// OMP-DEfAULT-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 45656// OMP-DEfAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 45657// OMP-DEfAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 45658// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 45659// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 45660// OMP-DEfAULT-NEXT:    store i32 [[TMP1]], ptr [[A]], align 45661// OMP-DEfAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 45662// OMP-DEfAULT-NEXT:    store i32 [[TMP2]], ptr [[A_CASTED]], align 45663// OMP-DEfAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A_CASTED]], align 45664// OMP-DEfAULT-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SE3fooEv_l185(i32 [[TMP3]]) #[[ATTR2]]5665// OMP-DEfAULT-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A]], align 45666// OMP-DEfAULT-NEXT:    [[TMP5:%.*]] = load ptr, ptr @R, align 45667// OMP-DEfAULT-NEXT:    store i32 [[TMP4]], ptr [[TMP5]], align 45668// OMP-DEfAULT-NEXT:    ret void5669//5670//5671// OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2STILi100EE3fooEv5672// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(912) [[THIS:%.*]]) #[[ATTR1]] comdat align 2 {5673// OMP-DEfAULT-NEXT:  entry:5674// OMP-DEfAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 45675// OMP-DEfAULT-NEXT:    [[A:%.*]] = alloca i32, align 45676// OMP-DEfAULT-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 45677// OMP-DEfAULT-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 45678// OMP-DEfAULT-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 45679// OMP-DEfAULT-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 45680// OMP-DEfAULT-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 85681// OMP-DEfAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 45682// OMP-DEfAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 45683// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 45684// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 45685// OMP-DEfAULT-NEXT:    store i32 [[TMP1]], ptr [[A]], align 45686// OMP-DEfAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 45687// OMP-DEfAULT-NEXT:    store i32 [[TMP2]], ptr [[A_CASTED]], align 45688// OMP-DEfAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A_CASTED]], align 45689// OMP-DEfAULT-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 05690// OMP-DEfAULT-NEXT:    store i32 [[TMP3]], ptr [[TMP4]], align 45691// OMP-DEfAULT-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 05692// OMP-DEfAULT-NEXT:    store i32 [[TMP3]], ptr [[TMP5]], align 45693// OMP-DEfAULT-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 05694// OMP-DEfAULT-NEXT:    store ptr null, ptr [[TMP6]], align 45695// OMP-DEfAULT-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 05696// OMP-DEfAULT-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 05697// OMP-DEfAULT-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 05698// OMP-DEfAULT-NEXT:    store i32 3, ptr [[TMP9]], align 45699// OMP-DEfAULT-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 15700// OMP-DEfAULT-NEXT:    store i32 1, ptr [[TMP10]], align 45701// OMP-DEfAULT-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 25702// OMP-DEfAULT-NEXT:    store ptr [[TMP7]], ptr [[TMP11]], align 45703// OMP-DEfAULT-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 35704// OMP-DEfAULT-NEXT:    store ptr [[TMP8]], ptr [[TMP12]], align 45705// OMP-DEfAULT-NEXT:    [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 45706// OMP-DEfAULT-NEXT:    store ptr @.offload_sizes.27, ptr [[TMP13]], align 45707// OMP-DEfAULT-NEXT:    [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 55708// OMP-DEfAULT-NEXT:    store ptr @.offload_maptypes.28, ptr [[TMP14]], align 45709// OMP-DEfAULT-NEXT:    [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 65710// OMP-DEfAULT-NEXT:    store ptr null, ptr [[TMP15]], align 45711// OMP-DEfAULT-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 75712// OMP-DEfAULT-NEXT:    store ptr null, ptr [[TMP16]], align 45713// OMP-DEfAULT-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 85714// OMP-DEfAULT-NEXT:    store i64 0, ptr [[TMP17]], align 85715// OMP-DEfAULT-NEXT:    [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 95716// OMP-DEfAULT-NEXT:    store i64 0, ptr [[TMP18]], align 85717// OMP-DEfAULT-NEXT:    [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 105718// OMP-DEfAULT-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP19]], align 45719// OMP-DEfAULT-NEXT:    [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 115720// OMP-DEfAULT-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP20]], align 45721// OMP-DEfAULT-NEXT:    [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 125722// OMP-DEfAULT-NEXT:    store i32 0, ptr [[TMP21]], align 45723// OMP-DEfAULT-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi100EE3fooEv_l211.region_id, ptr [[KERNEL_ARGS]])5724// OMP-DEfAULT-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 05725// OMP-DEfAULT-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]5726// OMP-DEfAULT:       omp_offload.failed:5727// OMP-DEfAULT-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi100EE3fooEv_l211(i32 [[TMP3]]) #[[ATTR2]]5728// OMP-DEfAULT-NEXT:    br label [[OMP_OFFLOAD_CONT]]5729// OMP-DEfAULT:       omp_offload.cont:5730// OMP-DEfAULT-NEXT:    [[TMP24:%.*]] = load i32, ptr [[A]], align 45731// OMP-DEfAULT-NEXT:    [[TMP25:%.*]] = load ptr, ptr @R, align 45732// OMP-DEfAULT-NEXT:    store i32 [[TMP24]], ptr [[TMP25]], align 45733// OMP-DEfAULT-NEXT:    ret void5734//5735//5736// OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2STILi1000EE3fooEv5737// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(4512) [[THIS:%.*]]) #[[ATTR1]] comdat align 2 {5738// OMP-DEfAULT-NEXT:  entry:5739// OMP-DEfAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 45740// OMP-DEfAULT-NEXT:    [[A:%.*]] = alloca i32, align 45741// OMP-DEfAULT-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 45742// OMP-DEfAULT-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 45743// OMP-DEfAULT-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 45744// OMP-DEfAULT-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 45745// OMP-DEfAULT-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 85746// OMP-DEfAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 45747// OMP-DEfAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 45748// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 45749// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 45750// OMP-DEfAULT-NEXT:    store i32 [[TMP1]], ptr [[A]], align 45751// OMP-DEfAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 45752// OMP-DEfAULT-NEXT:    store i32 [[TMP2]], ptr [[A_CASTED]], align 45753// OMP-DEfAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A_CASTED]], align 45754// OMP-DEfAULT-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 05755// OMP-DEfAULT-NEXT:    store i32 [[TMP3]], ptr [[TMP4]], align 45756// OMP-DEfAULT-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 05757// OMP-DEfAULT-NEXT:    store i32 [[TMP3]], ptr [[TMP5]], align 45758// OMP-DEfAULT-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 05759// OMP-DEfAULT-NEXT:    store ptr null, ptr [[TMP6]], align 45760// OMP-DEfAULT-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 05761// OMP-DEfAULT-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 05762// OMP-DEfAULT-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 05763// OMP-DEfAULT-NEXT:    store i32 3, ptr [[TMP9]], align 45764// OMP-DEfAULT-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 15765// OMP-DEfAULT-NEXT:    store i32 1, ptr [[TMP10]], align 45766// OMP-DEfAULT-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 25767// OMP-DEfAULT-NEXT:    store ptr [[TMP7]], ptr [[TMP11]], align 45768// OMP-DEfAULT-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 35769// OMP-DEfAULT-NEXT:    store ptr [[TMP8]], ptr [[TMP12]], align 45770// OMP-DEfAULT-NEXT:    [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 45771// OMP-DEfAULT-NEXT:    store ptr @.offload_sizes.29, ptr [[TMP13]], align 45772// OMP-DEfAULT-NEXT:    [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 55773// OMP-DEfAULT-NEXT:    store ptr @.offload_maptypes.30, ptr [[TMP14]], align 45774// OMP-DEfAULT-NEXT:    [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 65775// OMP-DEfAULT-NEXT:    store ptr null, ptr [[TMP15]], align 45776// OMP-DEfAULT-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 75777// OMP-DEfAULT-NEXT:    store ptr null, ptr [[TMP16]], align 45778// OMP-DEfAULT-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 85779// OMP-DEfAULT-NEXT:    store i64 0, ptr [[TMP17]], align 85780// OMP-DEfAULT-NEXT:    [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 95781// OMP-DEfAULT-NEXT:    store i64 0, ptr [[TMP18]], align 85782// OMP-DEfAULT-NEXT:    [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 105783// OMP-DEfAULT-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP19]], align 45784// OMP-DEfAULT-NEXT:    [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 115785// OMP-DEfAULT-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP20]], align 45786// OMP-DEfAULT-NEXT:    [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 125787// OMP-DEfAULT-NEXT:    store i32 0, ptr [[TMP21]], align 45788// OMP-DEfAULT-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi1000EE3fooEv_l211.region_id, ptr [[KERNEL_ARGS]])5789// OMP-DEfAULT-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 05790// OMP-DEfAULT-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]5791// OMP-DEfAULT:       omp_offload.failed:5792// OMP-DEfAULT-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi1000EE3fooEv_l211(i32 [[TMP3]]) #[[ATTR2]]5793// OMP-DEfAULT-NEXT:    br label [[OMP_OFFLOAD_CONT]]5794// OMP-DEfAULT:       omp_offload.cont:5795// OMP-DEfAULT-NEXT:    [[TMP24:%.*]] = load i32, ptr [[A]], align 45796// OMP-DEfAULT-NEXT:    [[TMP25:%.*]] = load ptr, ptr @R, align 45797// OMP-DEfAULT-NEXT:    store i32 [[TMP24]], ptr [[TMP25]], align 45798// OMP-DEfAULT-NEXT:    ret void5799//5800//5801// OMP-DEfAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3bari_l2675802// OMP-DEfAULT-SAME: (i32 noundef [[R:%.*]]) #[[ATTR3]] {5803// OMP-DEfAULT-NEXT:  entry:5804// OMP-DEfAULT-NEXT:    [[R_ADDR:%.*]] = alloca i32, align 45805// OMP-DEfAULT-NEXT:    [[R_CASTED:%.*]] = alloca i32, align 45806// OMP-DEfAULT-NEXT:    store i32 [[R]], ptr [[R_ADDR]], align 45807// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load i32, ptr [[R_ADDR]], align 45808// OMP-DEfAULT-NEXT:    store i32 [[TMP0]], ptr [[R_CASTED]], align 45809// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[R_CASTED]], align 45810// OMP-DEfAULT-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3bari_l267.omp_outlined, i32 [[TMP1]])5811// OMP-DEfAULT-NEXT:    ret void5812//5813//5814// OMP-DEfAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3bari_l267.omp_outlined5815// OMP-DEfAULT-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[R:%.*]]) #[[ATTR3]] {5816// OMP-DEfAULT-NEXT:  entry:5817// OMP-DEfAULT-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 45818// OMP-DEfAULT-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 45819// OMP-DEfAULT-NEXT:    [[R_ADDR:%.*]] = alloca i32, align 45820// OMP-DEfAULT-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 45821// OMP-DEfAULT-NEXT:    [[TMP:%.*]] = alloca i32, align 45822// OMP-DEfAULT-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 45823// OMP-DEfAULT-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 45824// OMP-DEfAULT-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 45825// OMP-DEfAULT-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 45826// OMP-DEfAULT-NEXT:    [[I:%.*]] = alloca i32, align 45827// OMP-DEfAULT-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 45828// OMP-DEfAULT-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 45829// OMP-DEfAULT-NEXT:    store i32 [[R]], ptr [[R_ADDR]], align 45830// OMP-DEfAULT-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 45831// OMP-DEfAULT-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 45832// OMP-DEfAULT-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 45833// OMP-DEfAULT-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 45834// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 45835// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 45836// OMP-DEfAULT-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)5837// OMP-DEfAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 45838// OMP-DEfAULT-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 95839// OMP-DEfAULT-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]5840// OMP-DEfAULT:       cond.true:5841// OMP-DEfAULT-NEXT:    br label [[COND_END:%.*]]5842// OMP-DEfAULT:       cond.false:5843// OMP-DEfAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 45844// OMP-DEfAULT-NEXT:    br label [[COND_END]]5845// OMP-DEfAULT:       cond.end:5846// OMP-DEfAULT-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]5847// OMP-DEfAULT-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 45848// OMP-DEfAULT-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 45849// OMP-DEfAULT-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 45850// OMP-DEfAULT-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]5851// OMP-DEfAULT:       omp.inner.for.cond:5852// OMP-DEfAULT-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 45853// OMP-DEfAULT-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 45854// OMP-DEfAULT-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]5855// OMP-DEfAULT-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]5856// OMP-DEfAULT:       omp.inner.for.body:5857// OMP-DEfAULT-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 45858// OMP-DEfAULT-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 15859// OMP-DEfAULT-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]5860// OMP-DEfAULT-NEXT:    store i32 [[ADD]], ptr [[I]], align 45861// OMP-DEfAULT-NEXT:    [[TMP8:%.*]] = load i32, ptr [[R_ADDR]], align 45862// OMP-DEfAULT-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP8]], 15863// OMP-DEfAULT-NEXT:    store i32 [[INC]], ptr [[R_ADDR]], align 45864// OMP-DEfAULT-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]5865// OMP-DEfAULT:       omp.body.continue:5866// OMP-DEfAULT-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]5867// OMP-DEfAULT:       omp.inner.for.inc:5868// OMP-DEfAULT-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 45869// OMP-DEfAULT-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 15870// OMP-DEfAULT-NEXT:    store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 45871// OMP-DEfAULT-NEXT:    br label [[OMP_INNER_FOR_COND]]5872// OMP-DEfAULT:       omp.inner.for.end:5873// OMP-DEfAULT-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]5874// OMP-DEfAULT:       omp.loop.exit:5875// OMP-DEfAULT-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])5876// OMP-DEfAULT-NEXT:    ret void5877//5878//5879// OMP-DEfAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SB3fooEv_l1225880// OMP-DEfAULT-SAME: (i32 noundef [[A:%.*]]) #[[ATTR3]] {5881// OMP-DEfAULT-NEXT:  entry:5882// OMP-DEfAULT-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 45883// OMP-DEfAULT-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 45884// OMP-DEfAULT-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 45885// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 45886// OMP-DEfAULT-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 45887// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 45888// OMP-DEfAULT-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SB3fooEv_l122.omp_outlined, i32 [[TMP1]])5889// OMP-DEfAULT-NEXT:    ret void5890//5891//5892// OMP-DEfAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SB3fooEv_l122.omp_outlined5893// OMP-DEfAULT-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] {5894// OMP-DEfAULT-NEXT:  entry:5895// OMP-DEfAULT-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 45896// OMP-DEfAULT-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 45897// OMP-DEfAULT-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 45898// OMP-DEfAULT-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 45899// OMP-DEfAULT-NEXT:    [[TMP:%.*]] = alloca i32, align 45900// OMP-DEfAULT-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 45901// OMP-DEfAULT-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 45902// OMP-DEfAULT-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 45903// OMP-DEfAULT-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 45904// OMP-DEfAULT-NEXT:    [[I:%.*]] = alloca i32, align 45905// OMP-DEfAULT-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 45906// OMP-DEfAULT-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 45907// OMP-DEfAULT-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 45908// OMP-DEfAULT-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 45909// OMP-DEfAULT-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 45910// OMP-DEfAULT-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 45911// OMP-DEfAULT-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 45912// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 45913// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 45914// OMP-DEfAULT-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)5915// OMP-DEfAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 45916// OMP-DEfAULT-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 95917// OMP-DEfAULT-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]5918// OMP-DEfAULT:       cond.true:5919// OMP-DEfAULT-NEXT:    br label [[COND_END:%.*]]5920// OMP-DEfAULT:       cond.false:5921// OMP-DEfAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 45922// OMP-DEfAULT-NEXT:    br label [[COND_END]]5923// OMP-DEfAULT:       cond.end:5924// OMP-DEfAULT-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]5925// OMP-DEfAULT-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 45926// OMP-DEfAULT-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 45927// OMP-DEfAULT-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 45928// OMP-DEfAULT-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]5929// OMP-DEfAULT:       omp.inner.for.cond:5930// OMP-DEfAULT-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 45931// OMP-DEfAULT-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 45932// OMP-DEfAULT-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]5933// OMP-DEfAULT-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]5934// OMP-DEfAULT:       omp.inner.for.body:5935// OMP-DEfAULT-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 45936// OMP-DEfAULT-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 15937// OMP-DEfAULT-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]5938// OMP-DEfAULT-NEXT:    store i32 [[ADD]], ptr [[I]], align 45939// OMP-DEfAULT-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 45940// OMP-DEfAULT-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 45941// OMP-DEfAULT-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 45942// OMP-DEfAULT-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]5943// OMP-DEfAULT:       omp.body.continue:5944// OMP-DEfAULT-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]5945// OMP-DEfAULT:       omp.inner.for.inc:5946// OMP-DEfAULT-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 45947// OMP-DEfAULT-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 15948// OMP-DEfAULT-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 45949// OMP-DEfAULT-NEXT:    br label [[OMP_INNER_FOR_COND]]5950// OMP-DEfAULT:       omp.inner.for.end:5951// OMP-DEfAULT-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]5952// OMP-DEfAULT:       omp.loop.exit:5953// OMP-DEfAULT-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])5954// OMP-DEfAULT-NEXT:    ret void5955//5956//5957// OMP-DEfAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SE3fooEv_l1855958// OMP-DEfAULT-SAME: (i32 noundef [[A:%.*]]) #[[ATTR3]] {5959// OMP-DEfAULT-NEXT:  entry:5960// OMP-DEfAULT-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 45961// OMP-DEfAULT-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 45962// OMP-DEfAULT-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 45963// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 45964// OMP-DEfAULT-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 45965// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 45966// OMP-DEfAULT-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SE3fooEv_l185.omp_outlined, i32 [[TMP1]])5967// OMP-DEfAULT-NEXT:    ret void5968//5969//5970// OMP-DEfAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SE3fooEv_l185.omp_outlined5971// OMP-DEfAULT-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] {5972// OMP-DEfAULT-NEXT:  entry:5973// OMP-DEfAULT-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 45974// OMP-DEfAULT-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 45975// OMP-DEfAULT-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 45976// OMP-DEfAULT-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 45977// OMP-DEfAULT-NEXT:    [[TMP:%.*]] = alloca i32, align 45978// OMP-DEfAULT-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 45979// OMP-DEfAULT-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 45980// OMP-DEfAULT-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 45981// OMP-DEfAULT-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 45982// OMP-DEfAULT-NEXT:    [[I:%.*]] = alloca i32, align 45983// OMP-DEfAULT-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 45984// OMP-DEfAULT-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 45985// OMP-DEfAULT-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 45986// OMP-DEfAULT-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 45987// OMP-DEfAULT-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 45988// OMP-DEfAULT-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 45989// OMP-DEfAULT-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 45990// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 45991// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 45992// OMP-DEfAULT-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)5993// OMP-DEfAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 45994// OMP-DEfAULT-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 95995// OMP-DEfAULT-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]5996// OMP-DEfAULT:       cond.true:5997// OMP-DEfAULT-NEXT:    br label [[COND_END:%.*]]5998// OMP-DEfAULT:       cond.false:5999// OMP-DEfAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 46000// OMP-DEfAULT-NEXT:    br label [[COND_END]]6001// OMP-DEfAULT:       cond.end:6002// OMP-DEfAULT-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]6003// OMP-DEfAULT-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 46004// OMP-DEfAULT-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 46005// OMP-DEfAULT-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 46006// OMP-DEfAULT-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]6007// OMP-DEfAULT:       omp.inner.for.cond:6008// OMP-DEfAULT-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 46009// OMP-DEfAULT-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 46010// OMP-DEfAULT-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]6011// OMP-DEfAULT-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]6012// OMP-DEfAULT:       omp.inner.for.body:6013// OMP-DEfAULT-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 46014// OMP-DEfAULT-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 16015// OMP-DEfAULT-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]6016// OMP-DEfAULT-NEXT:    store i32 [[ADD]], ptr [[I]], align 46017// OMP-DEfAULT-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 46018// OMP-DEfAULT-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 136019// OMP-DEfAULT-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 46020// OMP-DEfAULT-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]6021// OMP-DEfAULT:       omp.body.continue:6022// OMP-DEfAULT-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]6023// OMP-DEfAULT:       omp.inner.for.inc:6024// OMP-DEfAULT-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 46025// OMP-DEfAULT-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 16026// OMP-DEfAULT-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 46027// OMP-DEfAULT-NEXT:    br label [[OMP_INNER_FOR_COND]]6028// OMP-DEfAULT:       omp.inner.for.end:6029// OMP-DEfAULT-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]6030// OMP-DEfAULT:       omp.loop.exit:6031// OMP-DEfAULT-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])6032// OMP-DEfAULT-NEXT:    ret void6033//6034//6035// OMP-DEfAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi100EE3fooEv_l2116036// OMP-DEfAULT-SAME: (i32 noundef [[A:%.*]]) #[[ATTR3]] {6037// OMP-DEfAULT-NEXT:  entry:6038// OMP-DEfAULT-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 46039// OMP-DEfAULT-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 46040// OMP-DEfAULT-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 46041// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 46042// OMP-DEfAULT-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 46043// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 46044// OMP-DEfAULT-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi100EE3fooEv_l211.omp_outlined, i32 [[TMP1]])6045// OMP-DEfAULT-NEXT:    ret void6046//6047//6048// OMP-DEfAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi100EE3fooEv_l211.omp_outlined6049// OMP-DEfAULT-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] {6050// OMP-DEfAULT-NEXT:  entry:6051// OMP-DEfAULT-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 46052// OMP-DEfAULT-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 46053// OMP-DEfAULT-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 46054// OMP-DEfAULT-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 46055// OMP-DEfAULT-NEXT:    [[TMP:%.*]] = alloca i32, align 46056// OMP-DEfAULT-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 46057// OMP-DEfAULT-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 46058// OMP-DEfAULT-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 46059// OMP-DEfAULT-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 46060// OMP-DEfAULT-NEXT:    [[I:%.*]] = alloca i32, align 46061// OMP-DEfAULT-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 46062// OMP-DEfAULT-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 46063// OMP-DEfAULT-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 46064// OMP-DEfAULT-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 46065// OMP-DEfAULT-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 46066// OMP-DEfAULT-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 46067// OMP-DEfAULT-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 46068// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 46069// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 46070// OMP-DEfAULT-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)6071// OMP-DEfAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 46072// OMP-DEfAULT-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 96073// OMP-DEfAULT-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]6074// OMP-DEfAULT:       cond.true:6075// OMP-DEfAULT-NEXT:    br label [[COND_END:%.*]]6076// OMP-DEfAULT:       cond.false:6077// OMP-DEfAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 46078// OMP-DEfAULT-NEXT:    br label [[COND_END]]6079// OMP-DEfAULT:       cond.end:6080// OMP-DEfAULT-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]6081// OMP-DEfAULT-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 46082// OMP-DEfAULT-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 46083// OMP-DEfAULT-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 46084// OMP-DEfAULT-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]6085// OMP-DEfAULT:       omp.inner.for.cond:6086// OMP-DEfAULT-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 46087// OMP-DEfAULT-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 46088// OMP-DEfAULT-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]6089// OMP-DEfAULT-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]6090// OMP-DEfAULT:       omp.inner.for.body:6091// OMP-DEfAULT-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 46092// OMP-DEfAULT-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 16093// OMP-DEfAULT-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]6094// OMP-DEfAULT-NEXT:    store i32 [[ADD]], ptr [[I]], align 46095// OMP-DEfAULT-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 46096// OMP-DEfAULT-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1166097// OMP-DEfAULT-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 46098// OMP-DEfAULT-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]6099// OMP-DEfAULT:       omp.body.continue:6100// OMP-DEfAULT-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]6101// OMP-DEfAULT:       omp.inner.for.inc:6102// OMP-DEfAULT-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 46103// OMP-DEfAULT-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 16104// OMP-DEfAULT-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 46105// OMP-DEfAULT-NEXT:    br label [[OMP_INNER_FOR_COND]]6106// OMP-DEfAULT:       omp.inner.for.end:6107// OMP-DEfAULT-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]6108// OMP-DEfAULT:       omp.loop.exit:6109// OMP-DEfAULT-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])6110// OMP-DEfAULT-NEXT:    ret void6111//6112//6113// OMP-DEfAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi1000EE3fooEv_l2116114// OMP-DEfAULT-SAME: (i32 noundef [[A:%.*]]) #[[ATTR3]] {6115// OMP-DEfAULT-NEXT:  entry:6116// OMP-DEfAULT-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 46117// OMP-DEfAULT-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 46118// OMP-DEfAULT-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 46119// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 46120// OMP-DEfAULT-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 46121// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 46122// OMP-DEfAULT-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi1000EE3fooEv_l211.omp_outlined, i32 [[TMP1]])6123// OMP-DEfAULT-NEXT:    ret void6124//6125//6126// OMP-DEfAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi1000EE3fooEv_l211.omp_outlined6127// OMP-DEfAULT-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] {6128// OMP-DEfAULT-NEXT:  entry:6129// OMP-DEfAULT-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 46130// OMP-DEfAULT-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 46131// OMP-DEfAULT-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 46132// OMP-DEfAULT-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 46133// OMP-DEfAULT-NEXT:    [[TMP:%.*]] = alloca i32, align 46134// OMP-DEfAULT-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 46135// OMP-DEfAULT-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 46136// OMP-DEfAULT-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 46137// OMP-DEfAULT-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 46138// OMP-DEfAULT-NEXT:    [[I:%.*]] = alloca i32, align 46139// OMP-DEfAULT-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 46140// OMP-DEfAULT-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 46141// OMP-DEfAULT-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 46142// OMP-DEfAULT-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 46143// OMP-DEfAULT-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 46144// OMP-DEfAULT-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 46145// OMP-DEfAULT-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 46146// OMP-DEfAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 46147// OMP-DEfAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 46148// OMP-DEfAULT-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)6149// OMP-DEfAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 46150// OMP-DEfAULT-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 96151// OMP-DEfAULT-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]6152// OMP-DEfAULT:       cond.true:6153// OMP-DEfAULT-NEXT:    br label [[COND_END:%.*]]6154// OMP-DEfAULT:       cond.false:6155// OMP-DEfAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 46156// OMP-DEfAULT-NEXT:    br label [[COND_END]]6157// OMP-DEfAULT:       cond.end:6158// OMP-DEfAULT-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]6159// OMP-DEfAULT-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 46160// OMP-DEfAULT-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 46161// OMP-DEfAULT-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 46162// OMP-DEfAULT-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]6163// OMP-DEfAULT:       omp.inner.for.cond:6164// OMP-DEfAULT-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 46165// OMP-DEfAULT-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 46166// OMP-DEfAULT-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]6167// OMP-DEfAULT-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]6168// OMP-DEfAULT:       omp.inner.for.body:6169// OMP-DEfAULT-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 46170// OMP-DEfAULT-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 16171// OMP-DEfAULT-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]6172// OMP-DEfAULT-NEXT:    store i32 [[ADD]], ptr [[I]], align 46173// OMP-DEfAULT-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 46174// OMP-DEfAULT-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 10166175// OMP-DEfAULT-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 46176// OMP-DEfAULT-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]6177// OMP-DEfAULT:       omp.body.continue:6178// OMP-DEfAULT-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]6179// OMP-DEfAULT:       omp.inner.for.inc:6180// OMP-DEfAULT-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 46181// OMP-DEfAULT-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 16182// OMP-DEfAULT-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 46183// OMP-DEfAULT-NEXT:    br label [[OMP_INNER_FOR_COND]]6184// OMP-DEfAULT:       omp.inner.for.end:6185// OMP-DEfAULT-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]6186// OMP-DEfAULT:       omp.loop.exit:6187// OMP-DEfAULT-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])6188// OMP-DEfAULT-NEXT:    ret void6189//6190//6191// OMP-DEfAULT-LABEL: define {{[^@]+}}@_GLOBAL__I_0005006192// OMP-DEfAULT-SAME: () #[[ATTR0]] {6193// OMP-DEfAULT-NEXT:  entry:6194// OMP-DEfAULT-NEXT:    call void @__cxx_global_var_init()6195// OMP-DEfAULT-NEXT:    call void @__cxx_global_var_init.2()6196// OMP-DEfAULT-NEXT:    ret void6197//6198//6199// OMP-DEfAULT-LABEL: define {{[^@]+}}@_GLOBAL__I_0005016200// OMP-DEfAULT-SAME: () #[[ATTR0]] {6201// OMP-DEfAULT-NEXT:  entry:6202// OMP-DEfAULT-NEXT:    call void @__cxx_global_var_init.3()6203// OMP-DEfAULT-NEXT:    ret void6204//6205//6206// OMP-DEfAULT-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_parallel_generic_loop_codegen_1.cpp6207// OMP-DEfAULT-SAME: () #[[ATTR0]] {6208// OMP-DEfAULT-NEXT:  entry:6209// OMP-DEfAULT-NEXT:    call void @__cxx_global_var_init.1()6210// OMP-DEfAULT-NEXT:    call void @__cxx_global_var_init.4()6211// OMP-DEfAULT-NEXT:    call void @__cxx_global_var_init.5()6212// OMP-DEfAULT-NEXT:    call void @__cxx_global_var_init.8()6213// OMP-DEfAULT-NEXT:    call void @__cxx_global_var_init.13()6214// OMP-DEfAULT-NEXT:    call void @__cxx_global_var_init.18()6215// OMP-DEfAULT-NEXT:    ret void6216//6217//6218//6219//6220//6221//6222//6223//6224//6225//6226//6227//6228//6229//6230//6231//6232//6233//6234//6235//6236//6237//6238//6239//6240//6241//6242//6243//6244//6245//6246//6247//6248//6249//6250//6251//6252//6253//6254//6255//6256//6257//6258//6259//6260//6261//6262//6263//6264//6265//6266//6267//6268//6269//6270//6271//6272//6273//6274//6275//6276//6277//6278//6279//6280//6281//6282//6283//6284//6285//6286//6287//6288//6289//6290//6291//6292//6293//6294//6295//6296//6297//6298//6299//6300//6301//6302//6303//6304//6305//6306//6307//6308//6309//6310//6311//6312//6313//6314//6315//6316//6317//6318//6319//6320//6321//6322//6323//6324//6325//6326//6327//6328//6329//6330//6331//6332//6333//6334//6335//6336//6337//6338//6339//6340//6341//6342//6343//6344//6345//6346//6347//6348//6349//6350//6351//6352//6353//6354//6355//6356//6357//6358//6359//6360//6361//6362//6363//6364//6365//6366//6367//6368//6369//6370//6371//6372//6373//6374//6375//6376//6377//6378//6379//6380//6381//6382//6383//6384//6385//6386//6387//6388//6389//6390//6391//6392//6393//6394//6395//6396//6397//6398//6399//6400//6401//6402//6403//6404//6405//6406//6407//6408//6409//6410//6411//6412//6413//6414//6415//6416//6417//6418//6419//6420//6421//6422//6423//6424//6425//6426//6427//6428//6429//6430//6431//6432//6433//6434//6435//6436//6437//6438//6439//6440//6441//6442//6443//6444//6445//6446//6447//6448//6449//6450//6451//6452//6453//6454//6455//6456//6457//6458//6459//6460//6461//6462//6463//6464//6465//6466//6467//6468//6469//6470//6471//6472//6473//6474//6475//6476//6477//6478//6479//6480//6481//6482//6483//6484//6485//6486//6487//6488//6489//6490//6491//6492//6493//6494//6495//6496//6497//6498//6499//6500//6501//6502//6503//6504//6505//6506//6507//6508//6509//6510//6511//6512//6513//6514//6515//6516//6517//6518//6519//6520//6521//6522//6523//6524//6525//6526//6527//6528//6529//6530//6531//6532//6533//6534//6535//6536//6537//6538//6539//6540//6541//6542//6543//6544//6545//6546//6547//6548//6549//6550//6551//6552//6553//6554//6555//6556//6557//6558//6559//6560//6561//6562//6563//6564//6565//6566//6567//6568//6569//6570//6571//6572//6573//6574//6575//6576//6577//6578//6579//6580//6581//6582//6583//6584//6585//6586//6587//6588//6589//6590//6591//6592//6593//6594//6595//6596//6597//6598//6599//6600//6601//6602//6603//6604//6605//6606//6607//6608//6609//6610//6611//6612//6613//6614//6615//6616//6617//6618//6619//6620//6621//6622//6623//6624//6625//6626//6627//6628//6629//6630//6631//6632//6633//6634//6635//6636//6637//6638//6639//6640//6641//6642//6643//6644//6645//6646//6647//6648//6649//6650//6651//6652//6653//6654//6655//6656//6657//6658//6659//6660//6661//6662//6663//6664// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@__cxx_global_var_init6665// CHECK-NTARGET-OMP-DEFAULT-SAME: () #[[ATTR0:[0-9]+]] {6666// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:6667// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @_ZN2SAC1Ev(ptr noundef nonnull align 4 dereferenceable(16) @_ZL2a1)6668// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SAD1Ev, ptr @_ZL2a1, ptr @__dso_handle) #[[ATTR2:[0-9]+]]6669// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void6670//6671//6672// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2SAC1Ev6673// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {6674// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:6675// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 86676// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 86677// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 86678// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @_ZN2SAC2Ev(ptr noundef nonnull align 4 dereferenceable(16) [[THIS1]])6679// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void6680//6681//6682// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2SAD1Ev6683// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {6684// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:6685// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 86686// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 86687// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 86688// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @_ZN2SAD2Ev(ptr noundef nonnull align 4 dereferenceable(16) [[THIS1]]) #[[ATTR2]]6689// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void6690//6691//6692// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2SAC2Ev6693// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {6694// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:6695// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 86696// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A:%.*]] = alloca i32, align 46697// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 86698// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 86699// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 86700// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 46701// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP1]], ptr [[A]], align 46702// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 46703// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP2]], 26704// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[ADD]], ptr [[A]], align 46705// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 46706// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP4:%.*]] = load ptr, ptr @R, align 86707// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP3]], ptr [[TMP4]], align 46708// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void6709//6710//6711// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2SAD2Ev6712// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {6713// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:6714// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 86715// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A:%.*]] = alloca i32, align 46716// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 86717// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 86718// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 86719// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 46720// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP1]], ptr [[A]], align 46721// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 46722// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP2]], 36723// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[ADD]], ptr [[A]], align 46724// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 46725// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP4:%.*]] = load ptr, ptr @R, align 86726// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP3]], ptr [[TMP4]], align 46727// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void6728//6729//6730// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@__cxx_global_var_init.16731// CHECK-NTARGET-OMP-DEFAULT-SAME: () #[[ATTR0]] {6732// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:6733// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @_ZN2SAC1Ev(ptr noundef nonnull align 4 dereferenceable(16) @a2)6734// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SAD1Ev, ptr @a2, ptr @__dso_handle) #[[ATTR2]]6735// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void6736//6737//6738// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@__cxx_global_var_init.26739// CHECK-NTARGET-OMP-DEFAULT-SAME: () #[[ATTR0]] {6740// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:6741// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @_ZN2SBC1Ev(ptr noundef nonnull align 4 dereferenceable(32) @b1)6742// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SBD1Ev, ptr @b1, ptr @__dso_handle) #[[ATTR2]]6743// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void6744//6745//6746// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2SBC1Ev6747// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(32) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {6748// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:6749// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 86750// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 86751// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 86752// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @_ZN2SBC2Ev(ptr noundef nonnull align 4 dereferenceable(32) [[THIS1]])6753// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void6754//6755//6756// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2SBD1Ev6757// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(32) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {6758// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:6759// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 86760// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 86761// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 86762// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @_ZN2SBD2Ev(ptr noundef nonnull align 4 dereferenceable(32) [[THIS1]]) #[[ATTR2]]6763// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void6764//6765//6766// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2SBC2Ev6767// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(32) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {6768// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:6769// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 86770// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A:%.*]] = alloca i32, align 46771// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 86772// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 86773// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 86774// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 46775// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP1]], ptr [[A]], align 46776// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 46777// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP2]], 56778// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[ADD]], ptr [[A]], align 46779// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 46780// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP4:%.*]] = load ptr, ptr @R, align 86781// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP3]], ptr [[TMP4]], align 46782// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void6783//6784//6785// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2SBD2Ev6786// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(32) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {6787// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:6788// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 86789// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A:%.*]] = alloca i32, align 46790// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 86791// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 86792// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 86793// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 46794// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP1]], ptr [[A]], align 46795// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 46796// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP2]], 66797// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[ADD]], ptr [[A]], align 46798// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 46799// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP4:%.*]] = load ptr, ptr @R, align 86800// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP3]], ptr [[TMP4]], align 46801// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void6802//6803//6804// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@__cxx_global_var_init.36805// CHECK-NTARGET-OMP-DEFAULT-SAME: () #[[ATTR0]] {6806// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:6807// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @_ZN2SBC1Ev(ptr noundef nonnull align 4 dereferenceable(32) @b2)6808// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SBD1Ev, ptr @b2, ptr @__dso_handle) #[[ATTR2]]6809// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void6810//6811//6812// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@__cxx_global_var_init.46813// CHECK-NTARGET-OMP-DEFAULT-SAME: () #[[ATTR0]] {6814// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:6815// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @_ZN2SCC1Ev(ptr noundef nonnull align 4 dereferenceable(64) @_ZL2c1)6816// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SCD1Ev, ptr @_ZL2c1, ptr @__dso_handle) #[[ATTR2]]6817// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void6818//6819//6820// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2SCC1Ev6821// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(64) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {6822// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:6823// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 86824// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 86825// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 86826// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @_ZN2SCC2Ev(ptr noundef nonnull align 4 dereferenceable(64) [[THIS1]])6827// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void6828//6829//6830// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2SCD1Ev6831// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(64) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {6832// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:6833// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 86834// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 86835// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 86836// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @_ZN2SCD2Ev(ptr noundef nonnull align 4 dereferenceable(64) [[THIS1]]) #[[ATTR2]]6837// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void6838//6839//6840// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2SCC2Ev6841// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(64) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {6842// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:6843// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 86844// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A:%.*]] = alloca i32, align 46845// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 86846// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 86847// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 86848// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 86849// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 46850// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP1]], ptr [[A]], align 46851// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 46852// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP2]], ptr [[A_CASTED]], align 46853// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP3:%.*]] = load i64, ptr [[A_CASTED]], align 86854// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SCC1Ev_l148(i64 [[TMP3]]) #[[ATTR2]]6855// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A]], align 46856// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP5:%.*]] = load ptr, ptr @R, align 86857// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP4]], ptr [[TMP5]], align 46858// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void6859//6860//6861// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SCC1Ev_l1486862// CHECK-NTARGET-OMP-DEFAULT-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3:[0-9]+]] {6863// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:6864// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 86865// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 86866// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 86867// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 46868// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 46869// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 86870// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SCC1Ev_l148.omp_outlined, i64 [[TMP1]])6871// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void6872//6873//6874// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SCC1Ev_l148.omp_outlined6875// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] {6876// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:6877// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 86878// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 86879// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 86880// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 46881// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP:%.*]] = alloca i32, align 46882// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 46883// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 46884// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 46885// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 46886// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[I:%.*]] = alloca i32, align 46887// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 86888// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 86889// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 86890// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 46891// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 46892// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 46893// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 46894// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 86895// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 46896// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)6897// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 46898// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 96899// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]6900// CHECK-NTARGET-OMP-DEFAULT:       cond.true:6901// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[COND_END:%.*]]6902// CHECK-NTARGET-OMP-DEFAULT:       cond.false:6903// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 46904// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[COND_END]]6905// CHECK-NTARGET-OMP-DEFAULT:       cond.end:6906// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]6907// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 46908// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 46909// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 46910// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]6911// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.cond:6912// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 46913// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 46914// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]6915// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]6916// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.body:6917// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 46918// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 16919// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]6920// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[ADD]], ptr [[I]], align 46921// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 46922// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 86923// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 46924// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]6925// CHECK-NTARGET-OMP-DEFAULT:       omp.body.continue:6926// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]6927// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.inc:6928// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 46929// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 16930// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 46931// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_INNER_FOR_COND]]6932// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.end:6933// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]6934// CHECK-NTARGET-OMP-DEFAULT:       omp.loop.exit:6935// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])6936// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void6937//6938//6939// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2SCD2Ev6940// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(64) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {6941// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:6942// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 86943// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A:%.*]] = alloca i32, align 46944// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 86945// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 86946// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 86947// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 46948// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP1]], ptr [[A]], align 46949// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 46950// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP2]], 96951// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[ADD]], ptr [[A]], align 46952// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 46953// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP4:%.*]] = load ptr, ptr @R, align 86954// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP3]], ptr [[TMP4]], align 46955// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void6956//6957//6958// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@__cxx_global_var_init.56959// CHECK-NTARGET-OMP-DEFAULT-SAME: () #[[ATTR0]] {6960// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:6961// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @_ZN2SDC1Ev(ptr noundef nonnull align 4 dereferenceable(128) @d1)6962// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SDD1Ev, ptr @d1, ptr @__dso_handle) #[[ATTR2]]6963// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void6964//6965//6966// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2SDC1Ev6967// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(128) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {6968// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:6969// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 86970// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 86971// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 86972// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @_ZN2SDC2Ev(ptr noundef nonnull align 4 dereferenceable(128) [[THIS1]])6973// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void6974//6975//6976// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2SDD1Ev6977// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(128) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {6978// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:6979// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 86980// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 86981// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 86982// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @_ZN2SDD2Ev(ptr noundef nonnull align 4 dereferenceable(128) [[THIS1]]) #[[ATTR2]]6983// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void6984//6985//6986// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2SDC2Ev6987// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(128) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {6988// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:6989// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 86990// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A:%.*]] = alloca i32, align 46991// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 86992// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 86993// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 86994// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 46995// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP1]], ptr [[A]], align 46996// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 46997// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP2]], 116998// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[ADD]], ptr [[A]], align 46999// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 47000// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP4:%.*]] = load ptr, ptr @R, align 87001// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP3]], ptr [[TMP4]], align 47002// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void7003//7004//7005// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2SDD2Ev7006// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(128) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {7007// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:7008// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 87009// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A:%.*]] = alloca i32, align 47010// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 87011// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 87012// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 87013// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 87014// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 47015// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP1]], ptr [[A]], align 47016// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 47017// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP2]], ptr [[A_CASTED]], align 47018// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP3:%.*]] = load i64, ptr [[A_CASTED]], align 87019// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SDD1Ev_l174(i64 [[TMP3]]) #[[ATTR2]]7020// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A]], align 47021// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP5:%.*]] = load ptr, ptr @R, align 87022// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP4]], ptr [[TMP5]], align 47023// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void7024//7025//7026// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SDD1Ev_l1747027// CHECK-NTARGET-OMP-DEFAULT-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] {7028// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:7029// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 87030// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 87031// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 87032// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 47033// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 47034// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 87035// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SDD1Ev_l174.omp_outlined, i64 [[TMP1]])7036// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void7037//7038//7039// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SDD1Ev_l174.omp_outlined7040// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] {7041// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:7042// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 87043// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 87044// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 87045// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 47046// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP:%.*]] = alloca i32, align 47047// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 47048// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 47049// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 47050// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 47051// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[I:%.*]] = alloca i32, align 47052// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 87053// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 87054// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 87055// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 47056// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 47057// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 47058// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 47059// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 87060// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 47061// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)7062// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 47063// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 97064// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]7065// CHECK-NTARGET-OMP-DEFAULT:       cond.true:7066// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[COND_END:%.*]]7067// CHECK-NTARGET-OMP-DEFAULT:       cond.false:7068// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 47069// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[COND_END]]7070// CHECK-NTARGET-OMP-DEFAULT:       cond.end:7071// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]7072// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 47073// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 47074// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 47075// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]7076// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.cond:7077// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 47078// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 47079// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]7080// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]7081// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.body:7082// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 47083// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 17084// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]7085// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[ADD]], ptr [[I]], align 47086// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 47087// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 127088// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 47089// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]7090// CHECK-NTARGET-OMP-DEFAULT:       omp.body.continue:7091// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]7092// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.inc:7093// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 47094// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 17095// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 47096// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_INNER_FOR_COND]]7097// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.end:7098// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]7099// CHECK-NTARGET-OMP-DEFAULT:       omp.loop.exit:7100// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])7101// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void7102//7103//7104// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@__cxx_global_var_init.67105// CHECK-NTARGET-OMP-DEFAULT-SAME: () #[[ATTR0]] {7106// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:7107// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @_ZN2SEC1Ev(ptr noundef nonnull align 4 dereferenceable(256) @e1)7108// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2SED1Ev, ptr @e1, ptr @__dso_handle) #[[ATTR2]]7109// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void7110//7111//7112// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2SEC1Ev7113// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(256) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {7114// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:7115// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 87116// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 87117// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 87118// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @_ZN2SEC2Ev(ptr noundef nonnull align 4 dereferenceable(256) [[THIS1]])7119// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void7120//7121//7122// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2SED1Ev7123// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(256) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {7124// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:7125// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 87126// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 87127// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 87128// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @_ZN2SED2Ev(ptr noundef nonnull align 4 dereferenceable(256) [[THIS1]]) #[[ATTR2]]7129// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void7130//7131//7132// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2SEC2Ev7133// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(256) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {7134// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:7135// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 87136// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A:%.*]] = alloca i32, align 47137// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 87138// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 87139// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 87140// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 87141// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 47142// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP1]], ptr [[A]], align 47143// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 47144// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP2]], ptr [[A_CASTED]], align 47145// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP3:%.*]] = load i64, ptr [[A_CASTED]], align 87146// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SEC1Ev_l192(i64 [[TMP3]]) #[[ATTR2]]7147// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A]], align 47148// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP5:%.*]] = load ptr, ptr @R, align 87149// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP4]], ptr [[TMP5]], align 47150// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void7151//7152//7153// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SEC1Ev_l1927154// CHECK-NTARGET-OMP-DEFAULT-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] {7155// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:7156// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 87157// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 87158// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 87159// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 47160// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 47161// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 87162// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SEC1Ev_l192.omp_outlined, i64 [[TMP1]])7163// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void7164//7165//7166// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SEC1Ev_l192.omp_outlined7167// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] {7168// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:7169// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 87170// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 87171// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 87172// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 47173// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP:%.*]] = alloca i32, align 47174// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 47175// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 47176// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 47177// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 47178// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[I:%.*]] = alloca i32, align 47179// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 87180// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 87181// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 87182// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 47183// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 47184// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 47185// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 47186// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 87187// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 47188// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)7189// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 47190// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 97191// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]7192// CHECK-NTARGET-OMP-DEFAULT:       cond.true:7193// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[COND_END:%.*]]7194// CHECK-NTARGET-OMP-DEFAULT:       cond.false:7195// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 47196// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[COND_END]]7197// CHECK-NTARGET-OMP-DEFAULT:       cond.end:7198// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]7199// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 47200// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 47201// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 47202// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]7203// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.cond:7204// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 47205// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 47206// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]7207// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]7208// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.body:7209// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 47210// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 17211// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]7212// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[ADD]], ptr [[I]], align 47213// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 47214// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 147215// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 47216// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]7217// CHECK-NTARGET-OMP-DEFAULT:       omp.body.continue:7218// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]7219// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.inc:7220// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 47221// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 17222// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 47223// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_INNER_FOR_COND]]7224// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.end:7225// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]7226// CHECK-NTARGET-OMP-DEFAULT:       omp.loop.exit:7227// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])7228// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void7229//7230//7231// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2SED2Ev7232// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(256) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {7233// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:7234// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 87235// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A:%.*]] = alloca i32, align 47236// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 87237// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 87238// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 87239// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 87240// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 47241// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP1]], ptr [[A]], align 47242// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 47243// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP2]], ptr [[A_CASTED]], align 47244// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP3:%.*]] = load i64, ptr [[A_CASTED]], align 87245// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SED1Ev_l199(i64 [[TMP3]]) #[[ATTR2]]7246// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A]], align 47247// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP5:%.*]] = load ptr, ptr @R, align 87248// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP4]], ptr [[TMP5]], align 47249// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void7250//7251//7252// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SED1Ev_l1997253// CHECK-NTARGET-OMP-DEFAULT-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] {7254// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:7255// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 87256// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 87257// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 87258// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 47259// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 47260// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 87261// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SED1Ev_l199.omp_outlined, i64 [[TMP1]])7262// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void7263//7264//7265// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SED1Ev_l199.omp_outlined7266// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] {7267// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:7268// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 87269// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 87270// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 87271// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 47272// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP:%.*]] = alloca i32, align 47273// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 47274// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 47275// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 47276// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 47277// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[I:%.*]] = alloca i32, align 47278// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 87279// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 87280// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 87281// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 47282// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 47283// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 47284// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 47285// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 87286// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 47287// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)7288// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 47289// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 97290// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]7291// CHECK-NTARGET-OMP-DEFAULT:       cond.true:7292// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[COND_END:%.*]]7293// CHECK-NTARGET-OMP-DEFAULT:       cond.false:7294// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 47295// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[COND_END]]7296// CHECK-NTARGET-OMP-DEFAULT:       cond.end:7297// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]7298// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 47299// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 47300// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 47301// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]7302// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.cond:7303// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 47304// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 47305// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]7306// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]7307// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.body:7308// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 47309// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 17310// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]7311// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[ADD]], ptr [[I]], align 47312// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 47313// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 157314// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 47315// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]7316// CHECK-NTARGET-OMP-DEFAULT:       omp.body.continue:7317// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]7318// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.inc:7319// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 47320// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 17321// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 47322// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_INNER_FOR_COND]]7323// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.end:7324// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]7325// CHECK-NTARGET-OMP-DEFAULT:       omp.loop.exit:7326// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])7327// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void7328//7329//7330// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@__cxx_global_var_init.77331// CHECK-NTARGET-OMP-DEFAULT-SAME: () #[[ATTR0]] {7332// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:7333// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @_ZN2STILi100EEC1Ev(ptr noundef nonnull align 4 dereferenceable(912) @t1)7334// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2STILi100EED1Ev, ptr @t1, ptr @__dso_handle) #[[ATTR2]]7335// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void7336//7337//7338// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2STILi100EEC1Ev7339// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(912) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {7340// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:7341// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 87342// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 87343// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 87344// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @_ZN2STILi100EEC2Ev(ptr noundef nonnull align 4 dereferenceable(912) [[THIS1]])7345// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void7346//7347//7348// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2STILi100EED1Ev7349// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(912) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {7350// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:7351// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 87352// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 87353// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 87354// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @_ZN2STILi100EED2Ev(ptr noundef nonnull align 4 dereferenceable(912) [[THIS1]]) #[[ATTR2]]7355// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void7356//7357//7358// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2STILi100EEC2Ev7359// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(912) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {7360// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:7361// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 87362// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A:%.*]] = alloca i32, align 47363// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 87364// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 87365// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 87366// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 87367// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 47368// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP1]], ptr [[A]], align 47369// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 47370// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP2]], ptr [[A_CASTED]], align 47371// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP3:%.*]] = load i64, ptr [[A_CASTED]], align 87372// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi100EEC1Ev_l218(i64 [[TMP3]]) #[[ATTR2]]7373// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A]], align 47374// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP5:%.*]] = load ptr, ptr @R, align 87375// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP4]], ptr [[TMP5]], align 47376// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void7377//7378//7379// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi100EEC1Ev_l2187380// CHECK-NTARGET-OMP-DEFAULT-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] {7381// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:7382// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 87383// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 87384// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 87385// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 47386// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 47387// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 87388// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi100EEC1Ev_l218.omp_outlined, i64 [[TMP1]])7389// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void7390//7391//7392// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi100EEC1Ev_l218.omp_outlined7393// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] {7394// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:7395// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 87396// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 87397// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 87398// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 47399// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP:%.*]] = alloca i32, align 47400// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 47401// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 47402// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 47403// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 47404// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[I:%.*]] = alloca i32, align 47405// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 87406// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 87407// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 87408// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 47409// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 47410// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 47411// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 47412// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 87413// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 47414// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)7415// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 47416// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 97417// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]7418// CHECK-NTARGET-OMP-DEFAULT:       cond.true:7419// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[COND_END:%.*]]7420// CHECK-NTARGET-OMP-DEFAULT:       cond.false:7421// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 47422// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[COND_END]]7423// CHECK-NTARGET-OMP-DEFAULT:       cond.end:7424// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]7425// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 47426// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 47427// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 47428// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]7429// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.cond:7430// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 47431// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 47432// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]7433// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]7434// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.body:7435// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 47436// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 17437// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]7438// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[ADD]], ptr [[I]], align 47439// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 47440// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1177441// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 47442// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]7443// CHECK-NTARGET-OMP-DEFAULT:       omp.body.continue:7444// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]7445// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.inc:7446// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 47447// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 17448// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 47449// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_INNER_FOR_COND]]7450// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.end:7451// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]7452// CHECK-NTARGET-OMP-DEFAULT:       omp.loop.exit:7453// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])7454// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void7455//7456//7457// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2STILi100EED2Ev7458// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(912) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {7459// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:7460// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 87461// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A:%.*]] = alloca i32, align 47462// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 87463// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 87464// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 87465// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 87466// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 47467// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP1]], ptr [[A]], align 47468// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 47469// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP2]], ptr [[A_CASTED]], align 47470// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP3:%.*]] = load i64, ptr [[A_CASTED]], align 87471// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi100EED1Ev_l225(i64 [[TMP3]]) #[[ATTR2]]7472// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A]], align 47473// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP5:%.*]] = load ptr, ptr @R, align 87474// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP4]], ptr [[TMP5]], align 47475// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void7476//7477//7478// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi100EED1Ev_l2257479// CHECK-NTARGET-OMP-DEFAULT-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] {7480// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:7481// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 87482// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 87483// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 87484// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 47485// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 47486// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 87487// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi100EED1Ev_l225.omp_outlined, i64 [[TMP1]])7488// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void7489//7490//7491// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi100EED1Ev_l225.omp_outlined7492// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] {7493// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:7494// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 87495// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 87496// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 87497// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 47498// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP:%.*]] = alloca i32, align 47499// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 47500// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 47501// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 47502// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 47503// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[I:%.*]] = alloca i32, align 47504// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 87505// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 87506// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 87507// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 47508// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 47509// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 47510// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 47511// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 87512// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 47513// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)7514// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 47515// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 97516// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]7517// CHECK-NTARGET-OMP-DEFAULT:       cond.true:7518// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[COND_END:%.*]]7519// CHECK-NTARGET-OMP-DEFAULT:       cond.false:7520// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 47521// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[COND_END]]7522// CHECK-NTARGET-OMP-DEFAULT:       cond.end:7523// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]7524// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 47525// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 47526// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 47527// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]7528// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.cond:7529// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 47530// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 47531// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]7532// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]7533// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.body:7534// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 47535// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 17536// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]7537// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[ADD]], ptr [[I]], align 47538// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 47539// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1187540// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 47541// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]7542// CHECK-NTARGET-OMP-DEFAULT:       omp.body.continue:7543// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]7544// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.inc:7545// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 47546// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 17547// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 47548// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_INNER_FOR_COND]]7549// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.end:7550// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]7551// CHECK-NTARGET-OMP-DEFAULT:       omp.loop.exit:7552// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])7553// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void7554//7555//7556// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@__cxx_global_var_init.87557// CHECK-NTARGET-OMP-DEFAULT-SAME: () #[[ATTR0]] {7558// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:7559// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @_ZN2STILi1000EEC1Ev(ptr noundef nonnull align 4 dereferenceable(4512) @t2)7560// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2STILi1000EED1Ev, ptr @t2, ptr @__dso_handle) #[[ATTR2]]7561// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void7562//7563//7564// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2STILi1000EEC1Ev7565// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(4512) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {7566// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:7567// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 87568// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 87569// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 87570// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @_ZN2STILi1000EEC2Ev(ptr noundef nonnull align 4 dereferenceable(4512) [[THIS1]])7571// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void7572//7573//7574// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2STILi1000EED1Ev7575// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(4512) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {7576// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:7577// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 87578// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 87579// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 87580// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @_ZN2STILi1000EED2Ev(ptr noundef nonnull align 4 dereferenceable(4512) [[THIS1]]) #[[ATTR2]]7581// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void7582//7583//7584// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2STILi1000EEC2Ev7585// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(4512) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {7586// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:7587// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 87588// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A:%.*]] = alloca i32, align 47589// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 87590// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 87591// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 87592// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 87593// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 47594// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP1]], ptr [[A]], align 47595// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 47596// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP2]], ptr [[A_CASTED]], align 47597// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP3:%.*]] = load i64, ptr [[A_CASTED]], align 87598// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi1000EEC1Ev_l218(i64 [[TMP3]]) #[[ATTR2]]7599// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A]], align 47600// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP5:%.*]] = load ptr, ptr @R, align 87601// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP4]], ptr [[TMP5]], align 47602// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void7603//7604//7605// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi1000EEC1Ev_l2187606// CHECK-NTARGET-OMP-DEFAULT-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] {7607// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:7608// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 87609// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 87610// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 87611// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 47612// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 47613// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 87614// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi1000EEC1Ev_l218.omp_outlined, i64 [[TMP1]])7615// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void7616//7617//7618// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi1000EEC1Ev_l218.omp_outlined7619// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] {7620// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:7621// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 87622// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 87623// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 87624// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 47625// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP:%.*]] = alloca i32, align 47626// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 47627// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 47628// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 47629// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 47630// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[I:%.*]] = alloca i32, align 47631// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 87632// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 87633// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 87634// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 47635// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 47636// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 47637// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 47638// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 87639// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 47640// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)7641// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 47642// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 97643// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]7644// CHECK-NTARGET-OMP-DEFAULT:       cond.true:7645// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[COND_END:%.*]]7646// CHECK-NTARGET-OMP-DEFAULT:       cond.false:7647// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 47648// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[COND_END]]7649// CHECK-NTARGET-OMP-DEFAULT:       cond.end:7650// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]7651// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 47652// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 47653// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 47654// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]7655// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.cond:7656// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 47657// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 47658// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]7659// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]7660// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.body:7661// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 47662// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 17663// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]7664// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[ADD]], ptr [[I]], align 47665// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 47666// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 10177667// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 47668// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]7669// CHECK-NTARGET-OMP-DEFAULT:       omp.body.continue:7670// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]7671// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.inc:7672// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 47673// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 17674// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 47675// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_INNER_FOR_COND]]7676// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.end:7677// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]7678// CHECK-NTARGET-OMP-DEFAULT:       omp.loop.exit:7679// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])7680// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void7681//7682//7683// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2STILi1000EED2Ev7684// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(4512) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {7685// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:7686// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 87687// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A:%.*]] = alloca i32, align 47688// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 87689// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 87690// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 87691// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 87692// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 47693// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP1]], ptr [[A]], align 47694// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 47695// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP2]], ptr [[A_CASTED]], align 47696// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP3:%.*]] = load i64, ptr [[A_CASTED]], align 87697// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi1000EED1Ev_l225(i64 [[TMP3]]) #[[ATTR2]]7698// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A]], align 47699// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP5:%.*]] = load ptr, ptr @R, align 87700// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP4]], ptr [[TMP5]], align 47701// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void7702//7703//7704// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi1000EED1Ev_l2257705// CHECK-NTARGET-OMP-DEFAULT-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] {7706// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:7707// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 87708// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 87709// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 87710// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 47711// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 47712// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 87713// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi1000EED1Ev_l225.omp_outlined, i64 [[TMP1]])7714// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void7715//7716//7717// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi1000EED1Ev_l225.omp_outlined7718// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] {7719// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:7720// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 87721// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 87722// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 87723// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 47724// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP:%.*]] = alloca i32, align 47725// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 47726// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 47727// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 47728// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 47729// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[I:%.*]] = alloca i32, align 47730// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 87731// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 87732// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 87733// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 47734// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 47735// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 47736// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 47737// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 87738// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 47739// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)7740// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 47741// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 97742// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]7743// CHECK-NTARGET-OMP-DEFAULT:       cond.true:7744// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[COND_END:%.*]]7745// CHECK-NTARGET-OMP-DEFAULT:       cond.false:7746// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 47747// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[COND_END]]7748// CHECK-NTARGET-OMP-DEFAULT:       cond.end:7749// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]7750// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 47751// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 47752// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 47753// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]7754// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.cond:7755// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 47756// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 47757// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]7758// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]7759// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.body:7760// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 47761// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 17762// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]7763// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[ADD]], ptr [[I]], align 47764// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 47765// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 10187766// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 47767// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]7768// CHECK-NTARGET-OMP-DEFAULT:       omp.body.continue:7769// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]7770// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.inc:7771// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 47772// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 17773// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 47774// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_INNER_FOR_COND]]7775// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.end:7776// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]7777// CHECK-NTARGET-OMP-DEFAULT:       omp.loop.exit:7778// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])7779// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void7780//7781//7782// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_Z3bari7783// CHECK-NTARGET-OMP-DEFAULT-SAME: (i32 noundef signext [[A:%.*]]) #[[ATTR1]] {7784// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:7785// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 47786// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[R:%.*]] = alloca i32, align 47787// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[R_CASTED:%.*]] = alloca i64, align 87788// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 47789// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 47790// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP0]], ptr [[R]], align 47791// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @_ZN2SA3fooEv(ptr noundef nonnull align 4 dereferenceable(16) @_ZL2a1)7792// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @_ZN2SA3fooEv(ptr noundef nonnull align 4 dereferenceable(16) @a2)7793// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @_ZN2SB3fooEv(ptr noundef nonnull align 4 dereferenceable(32) @b1)7794// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @_ZN2SB3fooEv(ptr noundef nonnull align 4 dereferenceable(32) @b2)7795// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @_ZN2SC3fooEv(ptr noundef nonnull align 4 dereferenceable(64) @_ZL2c1)7796// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @_ZN2SD3fooEv(ptr noundef nonnull align 4 dereferenceable(128) @d1)7797// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @_ZN2SE3fooEv(ptr noundef nonnull align 4 dereferenceable(256) @e1)7798// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @_ZN2STILi100EE3fooEv(ptr noundef nonnull align 4 dereferenceable(912) @t1)7799// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @_ZN2STILi1000EE3fooEv(ptr noundef nonnull align 4 dereferenceable(4512) @t2)7800// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[R]], align 47801// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP1]], ptr [[R_CASTED]], align 47802// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP2:%.*]] = load i64, ptr [[R_CASTED]], align 87803// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3bari_l267(i64 [[TMP2]]) #[[ATTR2]]7804// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[R]], align 47805// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP4:%.*]] = load ptr, ptr @R, align 87806// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 47807// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP5]]7808// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret i32 [[ADD]]7809//7810//7811// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2SA3fooEv7812// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(16) [[THIS:%.*]]) #[[ATTR1]] comdat {7813// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:7814// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 87815// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A:%.*]] = alloca i32, align 47816// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 87817// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 87818// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 87819// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 47820// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP1]], ptr [[A]], align 47821// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 47822// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP2]], 17823// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[ADD]], ptr [[A]], align 47824// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 47825// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP4:%.*]] = load ptr, ptr @R, align 87826// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP3]], ptr [[TMP4]], align 47827// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void7828//7829//7830// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2SB3fooEv7831// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(32) [[THIS:%.*]]) #[[ATTR1]] comdat {7832// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:7833// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 87834// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A:%.*]] = alloca i32, align 47835// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 87836// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 87837// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 87838// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 87839// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 47840// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP1]], ptr [[A]], align 47841// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 47842// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP2]], ptr [[A_CASTED]], align 47843// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP3:%.*]] = load i64, ptr [[A_CASTED]], align 87844// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SB3fooEv_l122(i64 [[TMP3]]) #[[ATTR2]]7845// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A]], align 47846// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP5:%.*]] = load ptr, ptr @R, align 87847// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP4]], ptr [[TMP5]], align 47848// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void7849//7850//7851// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2SC3fooEv7852// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(64) [[THIS:%.*]]) #[[ATTR1]] comdat {7853// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:7854// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 87855// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A:%.*]] = alloca i32, align 47856// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 87857// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 87858// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 87859// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 47860// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP1]], ptr [[A]], align 47861// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 47862// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP2]], 77863// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[ADD]], ptr [[A]], align 47864// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 47865// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP4:%.*]] = load ptr, ptr @R, align 87866// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP3]], ptr [[TMP4]], align 47867// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void7868//7869//7870// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2SD3fooEv7871// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(128) [[THIS:%.*]]) #[[ATTR1]] comdat {7872// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:7873// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 87874// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A:%.*]] = alloca i32, align 47875// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 87876// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 87877// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 87878// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 47879// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP1]], ptr [[A]], align 47880// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 47881// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP2]], 107882// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[ADD]], ptr [[A]], align 47883// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 47884// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP4:%.*]] = load ptr, ptr @R, align 87885// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP3]], ptr [[TMP4]], align 47886// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void7887//7888//7889// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2SE3fooEv7890// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(256) [[THIS:%.*]]) #[[ATTR1]] comdat {7891// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:7892// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 87893// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A:%.*]] = alloca i32, align 47894// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 87895// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 87896// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 87897// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 87898// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 47899// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP1]], ptr [[A]], align 47900// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 47901// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP2]], ptr [[A_CASTED]], align 47902// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP3:%.*]] = load i64, ptr [[A_CASTED]], align 87903// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SE3fooEv_l185(i64 [[TMP3]]) #[[ATTR2]]7904// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A]], align 47905// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP5:%.*]] = load ptr, ptr @R, align 87906// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP4]], ptr [[TMP5]], align 47907// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void7908//7909//7910// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2STILi100EE3fooEv7911// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(912) [[THIS:%.*]]) #[[ATTR1]] comdat {7912// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:7913// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 87914// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A:%.*]] = alloca i32, align 47915// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 87916// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 87917// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 87918// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 87919// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 47920// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP1]], ptr [[A]], align 47921// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 47922// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP2]], ptr [[A_CASTED]], align 47923// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP3:%.*]] = load i64, ptr [[A_CASTED]], align 87924// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi100EE3fooEv_l211(i64 [[TMP3]]) #[[ATTR2]]7925// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A]], align 47926// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP5:%.*]] = load ptr, ptr @R, align 87927// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP4]], ptr [[TMP5]], align 47928// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void7929//7930//7931// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2STILi1000EE3fooEv7932// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(4512) [[THIS:%.*]]) #[[ATTR1]] comdat {7933// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:7934// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 87935// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A:%.*]] = alloca i32, align 47936// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 87937// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 87938// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 87939// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr @R, align 87940// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 47941// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP1]], ptr [[A]], align 47942// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 47943// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP2]], ptr [[A_CASTED]], align 47944// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP3:%.*]] = load i64, ptr [[A_CASTED]], align 87945// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi1000EE3fooEv_l211(i64 [[TMP3]]) #[[ATTR2]]7946// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A]], align 47947// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP5:%.*]] = load ptr, ptr @R, align 87948// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP4]], ptr [[TMP5]], align 47949// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void7950//7951//7952// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3bari_l2677953// CHECK-NTARGET-OMP-DEFAULT-SAME: (i64 noundef [[R:%.*]]) #[[ATTR3]] {7954// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:7955// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[R_ADDR:%.*]] = alloca i64, align 87956// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[R_CASTED:%.*]] = alloca i64, align 87957// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i64 [[R]], ptr [[R_ADDR]], align 87958// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load i32, ptr [[R_ADDR]], align 47959// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP0]], ptr [[R_CASTED]], align 47960// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i64, ptr [[R_CASTED]], align 87961// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3bari_l267.omp_outlined, i64 [[TMP1]])7962// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void7963//7964//7965// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3bari_l267.omp_outlined7966// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[R:%.*]]) #[[ATTR3]] {7967// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:7968// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 87969// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 87970// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[R_ADDR:%.*]] = alloca i64, align 87971// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 47972// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP:%.*]] = alloca i32, align 47973// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 47974// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 47975// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 47976// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 47977// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[I:%.*]] = alloca i32, align 47978// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 87979// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 87980// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i64 [[R]], ptr [[R_ADDR]], align 87981// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 47982// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 47983// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 47984// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 47985// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 87986// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 47987// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)7988// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 47989// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 97990// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]7991// CHECK-NTARGET-OMP-DEFAULT:       cond.true:7992// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[COND_END:%.*]]7993// CHECK-NTARGET-OMP-DEFAULT:       cond.false:7994// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 47995// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[COND_END]]7996// CHECK-NTARGET-OMP-DEFAULT:       cond.end:7997// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]7998// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 47999// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 48000// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 48001// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]8002// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.cond:8003// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 48004// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 48005// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]8006// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]8007// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.body:8008// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 48009// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 18010// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]8011// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[ADD]], ptr [[I]], align 48012// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP8:%.*]] = load i32, ptr [[R_ADDR]], align 48013// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP8]], 18014// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[INC]], ptr [[R_ADDR]], align 48015// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]8016// CHECK-NTARGET-OMP-DEFAULT:       omp.body.continue:8017// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]8018// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.inc:8019// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 48020// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 18021// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 48022// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_INNER_FOR_COND]]8023// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.end:8024// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]8025// CHECK-NTARGET-OMP-DEFAULT:       omp.loop.exit:8026// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])8027// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void8028//8029//8030// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SB3fooEv_l1228031// CHECK-NTARGET-OMP-DEFAULT-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] {8032// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:8033// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 88034// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 88035// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 88036// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 48037// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 48038// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 88039// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SB3fooEv_l122.omp_outlined, i64 [[TMP1]])8040// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void8041//8042//8043// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SB3fooEv_l122.omp_outlined8044// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] {8045// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:8046// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 88047// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 88048// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 88049// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 48050// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP:%.*]] = alloca i32, align 48051// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 48052// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 48053// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 48054// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 48055// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[I:%.*]] = alloca i32, align 48056// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 88057// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 88058// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 88059// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 48060// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 48061// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 48062// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 48063// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 88064// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 48065// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)8066// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 48067// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 98068// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]8069// CHECK-NTARGET-OMP-DEFAULT:       cond.true:8070// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[COND_END:%.*]]8071// CHECK-NTARGET-OMP-DEFAULT:       cond.false:8072// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 48073// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[COND_END]]8074// CHECK-NTARGET-OMP-DEFAULT:       cond.end:8075// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]8076// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 48077// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 48078// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 48079// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]8080// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.cond:8081// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 48082// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 48083// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]8084// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]8085// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.body:8086// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 48087// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 18088// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]8089// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[ADD]], ptr [[I]], align 48090// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 48091// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 48092// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 48093// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]8094// CHECK-NTARGET-OMP-DEFAULT:       omp.body.continue:8095// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]8096// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.inc:8097// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 48098// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 18099// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 48100// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_INNER_FOR_COND]]8101// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.end:8102// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]8103// CHECK-NTARGET-OMP-DEFAULT:       omp.loop.exit:8104// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])8105// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void8106//8107//8108// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SE3fooEv_l1858109// CHECK-NTARGET-OMP-DEFAULT-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] {8110// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:8111// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 88112// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 88113// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 88114// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 48115// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 48116// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 88117// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SE3fooEv_l185.omp_outlined, i64 [[TMP1]])8118// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void8119//8120//8121// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SE3fooEv_l185.omp_outlined8122// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] {8123// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:8124// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 88125// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 88126// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 88127// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 48128// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP:%.*]] = alloca i32, align 48129// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 48130// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 48131// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 48132// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 48133// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[I:%.*]] = alloca i32, align 48134// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 88135// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 88136// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 88137// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 48138// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 48139// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 48140// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 48141// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 88142// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 48143// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)8144// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 48145// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 98146// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]8147// CHECK-NTARGET-OMP-DEFAULT:       cond.true:8148// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[COND_END:%.*]]8149// CHECK-NTARGET-OMP-DEFAULT:       cond.false:8150// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 48151// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[COND_END]]8152// CHECK-NTARGET-OMP-DEFAULT:       cond.end:8153// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]8154// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 48155// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 48156// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 48157// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]8158// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.cond:8159// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 48160// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 48161// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]8162// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]8163// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.body:8164// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 48165// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 18166// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]8167// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[ADD]], ptr [[I]], align 48168// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 48169// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 138170// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 48171// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]8172// CHECK-NTARGET-OMP-DEFAULT:       omp.body.continue:8173// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]8174// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.inc:8175// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 48176// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 18177// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 48178// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_INNER_FOR_COND]]8179// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.end:8180// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]8181// CHECK-NTARGET-OMP-DEFAULT:       omp.loop.exit:8182// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])8183// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void8184//8185//8186// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi100EE3fooEv_l2118187// CHECK-NTARGET-OMP-DEFAULT-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] {8188// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:8189// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 88190// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 88191// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 88192// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 48193// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 48194// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 88195// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi100EE3fooEv_l211.omp_outlined, i64 [[TMP1]])8196// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void8197//8198//8199// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi100EE3fooEv_l211.omp_outlined8200// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] {8201// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:8202// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 88203// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 88204// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 88205// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 48206// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP:%.*]] = alloca i32, align 48207// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 48208// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 48209// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 48210// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 48211// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[I:%.*]] = alloca i32, align 48212// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 88213// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 88214// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 88215// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 48216// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 48217// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 48218// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 48219// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 88220// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 48221// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)8222// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 48223// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 98224// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]8225// CHECK-NTARGET-OMP-DEFAULT:       cond.true:8226// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[COND_END:%.*]]8227// CHECK-NTARGET-OMP-DEFAULT:       cond.false:8228// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 48229// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[COND_END]]8230// CHECK-NTARGET-OMP-DEFAULT:       cond.end:8231// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]8232// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 48233// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 48234// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 48235// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]8236// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.cond:8237// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 48238// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 48239// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]8240// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]8241// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.body:8242// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 48243// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 18244// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]8245// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[ADD]], ptr [[I]], align 48246// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 48247// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1168248// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 48249// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]8250// CHECK-NTARGET-OMP-DEFAULT:       omp.body.continue:8251// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]8252// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.inc:8253// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 48254// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 18255// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 48256// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_INNER_FOR_COND]]8257// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.end:8258// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]8259// CHECK-NTARGET-OMP-DEFAULT:       omp.loop.exit:8260// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])8261// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void8262//8263//8264// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi1000EE3fooEv_l2118265// CHECK-NTARGET-OMP-DEFAULT-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] {8266// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:8267// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 88268// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 88269// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 88270// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 48271// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 48272// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 88273// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi1000EE3fooEv_l211.omp_outlined, i64 [[TMP1]])8274// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void8275//8276//8277// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STILi1000EE3fooEv_l211.omp_outlined8278// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] {8279// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:8280// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 88281// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 88282// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 88283// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 48284// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP:%.*]] = alloca i32, align 48285// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 48286// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 48287// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 48288// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 48289// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[I:%.*]] = alloca i32, align 48290// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 88291// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 88292// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 88293// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 48294// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 48295// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 48296// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 48297// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 88298// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 48299// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)8300// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 48301// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 98302// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]8303// CHECK-NTARGET-OMP-DEFAULT:       cond.true:8304// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[COND_END:%.*]]8305// CHECK-NTARGET-OMP-DEFAULT:       cond.false:8306// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 48307// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[COND_END]]8308// CHECK-NTARGET-OMP-DEFAULT:       cond.end:8309// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]8310// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 48311// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 48312// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 48313// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]8314// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.cond:8315// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 48316// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 48317// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]8318// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]8319// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.body:8320// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 48321// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 18322// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]8323// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[ADD]], ptr [[I]], align 48324// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 48325// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 10168326// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 48327// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]8328// CHECK-NTARGET-OMP-DEFAULT:       omp.body.continue:8329// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]8330// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.inc:8331// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 48332// CHECK-NTARGET-OMP-DEFAULT-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 18333// CHECK-NTARGET-OMP-DEFAULT-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 48334// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_INNER_FOR_COND]]8335// CHECK-NTARGET-OMP-DEFAULT:       omp.inner.for.end:8336// CHECK-NTARGET-OMP-DEFAULT-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]8337// CHECK-NTARGET-OMP-DEFAULT:       omp.loop.exit:8338// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])8339// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void8340//8341//8342// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_GLOBAL__I_0005008343// CHECK-NTARGET-OMP-DEFAULT-SAME: () #[[ATTR0]] {8344// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:8345// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @__cxx_global_var_init()8346// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @__cxx_global_var_init.2()8347// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void8348//8349//8350// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_GLOBAL__I_0005018351// CHECK-NTARGET-OMP-DEFAULT-SAME: () #[[ATTR0]] {8352// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:8353// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @__cxx_global_var_init.3()8354// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void8355//8356//8357// CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_parallel_generic_loop_codegen_1.cpp8358// CHECK-NTARGET-OMP-DEFAULT-SAME: () #[[ATTR0]] {8359// CHECK-NTARGET-OMP-DEFAULT-NEXT:  entry:8360// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @__cxx_global_var_init.1()8361// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @__cxx_global_var_init.4()8362// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @__cxx_global_var_init.5()8363// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @__cxx_global_var_init.6()8364// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @__cxx_global_var_init.7()8365// CHECK-NTARGET-OMP-DEFAULT-NEXT:    call void @__cxx_global_var_init.8()8366// CHECK-NTARGET-OMP-DEFAULT-NEXT:    ret void8367//8368//// NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:8369// TCHECK: {{.*}}8370