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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _2// Test host codegen.3// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK14// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s5// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK16// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK37// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s8// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK39 10// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"11// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s12// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"13// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"14// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s15// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"16 17// Test target codegen - host bc file has to be created first.18// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc19// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK920// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s21// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK922// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc23// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK1124// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s25// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK1126 27// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc28// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"29// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s30// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"31// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc32// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"33// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s34// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"35 36// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK137// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s38// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK139// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK340// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s41// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK342 43// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"44// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s45// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"46// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"47// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s48// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"49 50// Test target codegen - host bc file has to be created first.51// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc52// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK953// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s54// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK955// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc56// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK1157// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s58// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK1159 60// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc61// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"62// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s63// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"64// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc65// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"66// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s67// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"68 69// expected-no-diagnostics70#ifndef HEADER71#define HEADER72 73 74 75 76// We have 8 target regions, but only 6 that actually will generate offloading77// code and have mapped arguments, and only 4 have all-constant map sizes.78 79 80 81// Check target registration is registered as a Ctor.82 83 84template<typename tx, typename ty>85struct TT{86  tx X;87  ty Y;88};89 90int global;91 92int foo(int n) {93  int a = 0;94  short aa = 0;95  float b[10];96  float bn[n];97  double c[5][10];98  double cn[5][n];99  TT<long long, char> d;100 101  #pragma omp target teams num_teams(a) thread_limit(a) firstprivate(aa) nowait102  {103  }104 105  #pragma omp target teams if(target: 0)106  {107    a += 1;108  }109 110 111  #pragma omp target teams if(target: 1)112  {113    aa += 1;114  }115 116 117 118  #pragma omp target teams if(target: n>10)119  {120    a += 1;121    aa += 1;122  }123 124  #pragma omp target teams ompx_bare num_teams(1) thread_limit(1)125  {126    a += 1;127    aa += 1;128  }129 130  #pragma omp target teams ompx_bare num_teams(1, 2) thread_limit(1, 2)131  {132    a += 1;133    aa += 1;134  }135 136  #pragma omp target teams ompx_bare num_teams(1, 2, 3) thread_limit(1, 2, 3)137  {138    a += 1;139    aa += 1;140  }141 142  // We capture 3 VLA sizes in this target region143 144 145 146 147 148  // The names below are not necessarily consistent with the names used for the149  // addresses above as some are repeated.150 151 152 153 154 155 156 157 158 159 160  #pragma omp target teams if(target: n>20)161  {162    a += 1;163    b[2] += 1.0;164    bn[3] += 1.0;165    c[1][2] += 1.0;166    cn[1][3] += 1.0;167    d.X += 1;168    d.Y += 1;169  }170 171  const int nn = 0;172  #pragma omp target teams shared(nn)173  #pragma omp parallel firstprivate(nn)174  (void)nn;175  #pragma omp target teams firstprivate(nn)176  #pragma omp parallel shared(nn)177  (void)nn;178  return a;179}180 181// Check that the offloading functions are emitted and that the arguments are182// correct and loaded correctly for the target regions in foo().183 184 185 186// Create stack storage and store argument in there.187 188// Create stack storage and store argument in there.189 190// Create stack storage and store argument in there.191 192// Create local storage for each capture.193 194 195 196// To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.197 198 199void bazzzz(int n, int f[n]) {200#pragma omp target teams private(f)201  ;202}203 204template<typename tx>205tx ftemplate(int n) {206  tx a = 0;207  short aa = 0;208  tx b[10];209 210  #pragma omp target teams if(target: n>40)211  {212    a += 1;213    aa += 1;214    b[2] += 1;215  }216 217  return a;218}219 220static221int fstatic(int n) {222  int a = 0;223  short aa = 0;224  char aaa = 0;225  int b[10];226 227  #pragma omp target teams if(target: n>50)228  {229    a += 1;230    aa += 1;231    aaa += 1;232    b[2] += 1;233  }234 235  return a;236}237 238struct S1 {239  double a;240 241  int r1(int n){242    int b = n+1;243    short int c[2][n];244 245    #pragma omp target teams if(target: n>60)246    {247      this->a = (double)b + 1.5;248      c[1][1] = ++a;249    }250 251    return c[1][1] + (int)b;252  }253};254 255int bar(int n){256  int a = 0;257 258  a += foo(n);259 260  S1 S;261  a += S.r1(n);262 263  a += fstatic(n);264 265  a += ftemplate<int>(n);266 267  return a;268}269 270 271 272// We capture 2 VLA sizes in this target region273 274 275// The names below are not necessarily consistent with the names used for the276// addresses above as some are repeated.277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297// Check that the offloading functions are emitted and that the arguments are298// correct and loaded correctly for the target regions of the callees of bar().299 300// Create local storage for each capture.301// Store captures in the context.302 303 304// To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.305 306 307// Create local storage for each capture.308// Store captures in the context.309 310 311 312 313// To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.314 315// Create local storage for each capture.316// Store captures in the context.317 318 319 320// To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.321 322#endif323// CHECK1-LABEL: define {{[^@]+}}@_Z3fooi324// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {325// CHECK1-NEXT:  entry:326// CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4327// CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 4328// CHECK1-NEXT:    [[AA:%.*]] = alloca i16, align 2329// CHECK1-NEXT:    [[B:%.*]] = alloca [10 x float], align 4330// CHECK1-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 8331// CHECK1-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8332// CHECK1-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8333// CHECK1-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8334// CHECK1-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8335// CHECK1-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4336// CHECK1-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4337// CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8338// CHECK1-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8339// CHECK1-NEXT:    [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i64, align 8340// CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8341// CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8342// CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8343// CHECK1-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4344// CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8345// CHECK1-NEXT:    [[AA_CASTED4:%.*]] = alloca i64, align 8346// CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [1 x ptr], align 8347// CHECK1-NEXT:    [[DOTOFFLOAD_PTRS6:%.*]] = alloca [1 x ptr], align 8348// CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [1 x ptr], align 8349// CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8350// CHECK1-NEXT:    [[A_CASTED8:%.*]] = alloca i64, align 8351// CHECK1-NEXT:    [[AA_CASTED9:%.*]] = alloca i64, align 8352// CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x ptr], align 8353// CHECK1-NEXT:    [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x ptr], align 8354// CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x ptr], align 8355// CHECK1-NEXT:    [[KERNEL_ARGS13:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8356// CHECK1-NEXT:    [[A_CASTED16:%.*]] = alloca i64, align 8357// CHECK1-NEXT:    [[AA_CASTED17:%.*]] = alloca i64, align 8358// CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS18:%.*]] = alloca [2 x ptr], align 8359// CHECK1-NEXT:    [[DOTOFFLOAD_PTRS19:%.*]] = alloca [2 x ptr], align 8360// CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS20:%.*]] = alloca [2 x ptr], align 8361// CHECK1-NEXT:    [[KERNEL_ARGS21:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8362// CHECK1-NEXT:    [[A_CASTED24:%.*]] = alloca i64, align 8363// CHECK1-NEXT:    [[AA_CASTED25:%.*]] = alloca i64, align 8364// CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS26:%.*]] = alloca [2 x ptr], align 8365// CHECK1-NEXT:    [[DOTOFFLOAD_PTRS27:%.*]] = alloca [2 x ptr], align 8366// CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS28:%.*]] = alloca [2 x ptr], align 8367// CHECK1-NEXT:    [[KERNEL_ARGS29:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8368// CHECK1-NEXT:    [[A_CASTED32:%.*]] = alloca i64, align 8369// CHECK1-NEXT:    [[AA_CASTED33:%.*]] = alloca i64, align 8370// CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS34:%.*]] = alloca [2 x ptr], align 8371// CHECK1-NEXT:    [[DOTOFFLOAD_PTRS35:%.*]] = alloca [2 x ptr], align 8372// CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS36:%.*]] = alloca [2 x ptr], align 8373// CHECK1-NEXT:    [[KERNEL_ARGS37:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8374// CHECK1-NEXT:    [[A_CASTED40:%.*]] = alloca i64, align 8375// CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS43:%.*]] = alloca [9 x ptr], align 8376// CHECK1-NEXT:    [[DOTOFFLOAD_PTRS44:%.*]] = alloca [9 x ptr], align 8377// CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS45:%.*]] = alloca [9 x ptr], align 8378// CHECK1-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8379// CHECK1-NEXT:    [[KERNEL_ARGS46:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8380// CHECK1-NEXT:    [[NN:%.*]] = alloca i32, align 4381// CHECK1-NEXT:    [[NN_CASTED:%.*]] = alloca i64, align 8382// CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS51:%.*]] = alloca [1 x ptr], align 8383// CHECK1-NEXT:    [[DOTOFFLOAD_PTRS52:%.*]] = alloca [1 x ptr], align 8384// CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS53:%.*]] = alloca [1 x ptr], align 8385// CHECK1-NEXT:    [[KERNEL_ARGS54:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8386// CHECK1-NEXT:    [[NN_CASTED57:%.*]] = alloca i64, align 8387// CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS58:%.*]] = alloca [1 x ptr], align 8388// CHECK1-NEXT:    [[DOTOFFLOAD_PTRS59:%.*]] = alloca [1 x ptr], align 8389// CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS60:%.*]] = alloca [1 x ptr], align 8390// CHECK1-NEXT:    [[KERNEL_ARGS61:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8391// CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])392// CHECK1-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4393// CHECK1-NEXT:    store i32 0, ptr [[A]], align 4394// CHECK1-NEXT:    store i16 0, ptr [[AA]], align 2395// CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4396// CHECK1-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64397// CHECK1-NEXT:    [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()398// CHECK1-NEXT:    store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8399// CHECK1-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4400// CHECK1-NEXT:    store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8401// CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4402// CHECK1-NEXT:    [[TMP5:%.*]] = zext i32 [[TMP4]] to i64403// CHECK1-NEXT:    [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]404// CHECK1-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8405// CHECK1-NEXT:    store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8406// CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[A]], align 4407// CHECK1-NEXT:    store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 4408// CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A]], align 4409// CHECK1-NEXT:    store i32 [[TMP8]], ptr [[DOTCAPTURE_EXPR_2]], align 4410// CHECK1-NEXT:    [[TMP9:%.*]] = load i16, ptr [[AA]], align 2411// CHECK1-NEXT:    store i16 [[TMP9]], ptr [[AA_CASTED]], align 2412// CHECK1-NEXT:    [[TMP10:%.*]] = load i64, ptr [[AA_CASTED]], align 8413// CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4414// CHECK1-NEXT:    store i32 [[TMP11]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4415// CHECK1-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8416// CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4417// CHECK1-NEXT:    store i32 [[TMP13]], ptr [[DOTCAPTURE_EXPR__CASTED3]], align 4418// CHECK1-NEXT:    [[TMP14:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED3]], align 8419// CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0420// CHECK1-NEXT:    store i64 [[TMP10]], ptr [[TMP15]], align 8421// CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0422// CHECK1-NEXT:    store i64 [[TMP10]], ptr [[TMP16]], align 8423// CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0424// CHECK1-NEXT:    store ptr null, ptr [[TMP17]], align 8425// CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1426// CHECK1-NEXT:    store i64 [[TMP12]], ptr [[TMP18]], align 8427// CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1428// CHECK1-NEXT:    store i64 [[TMP12]], ptr [[TMP19]], align 8429// CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1430// CHECK1-NEXT:    store ptr null, ptr [[TMP20]], align 8431// CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2432// CHECK1-NEXT:    store i64 [[TMP14]], ptr [[TMP21]], align 8433// CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2434// CHECK1-NEXT:    store i64 [[TMP14]], ptr [[TMP22]], align 8435// CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2436// CHECK1-NEXT:    store ptr null, ptr [[TMP23]], align 8437// CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0438// CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0439// CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0440// CHECK1-NEXT:    [[TMP27:%.*]] = load i16, ptr [[AA]], align 2441// CHECK1-NEXT:    store i16 [[TMP27]], ptr [[TMP26]], align 4442// CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1443// CHECK1-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4444// CHECK1-NEXT:    store i32 [[TMP29]], ptr [[TMP28]], align 4445// CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 2446// CHECK1-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4447// CHECK1-NEXT:    store i32 [[TMP31]], ptr [[TMP30]], align 4448// CHECK1-NEXT:    [[TMP32:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i64 120, i64 12, ptr @.omp_task_entry., i64 -1)449// CHECK1-NEXT:    [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP32]], i32 0, i32 0450// CHECK1-NEXT:    [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP33]], i32 0, i32 0451// CHECK1-NEXT:    [[TMP35:%.*]] = load ptr, ptr [[TMP34]], align 8452// CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP35]], ptr align 4 [[AGG_CAPTURED]], i64 12, i1 false)453// CHECK1-NEXT:    [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP32]], i32 0, i32 1454// CHECK1-NEXT:    [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP36]], i32 0, i32 0455// CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP37]], ptr align 8 [[TMP24]], i64 24, i1 false)456// CHECK1-NEXT:    [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP36]], i32 0, i32 1457// CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP38]], ptr align 8 [[TMP25]], i64 24, i1 false)458// CHECK1-NEXT:    [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP36]], i32 0, i32 2459// CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP39]], ptr align 8 @.offload_sizes, i64 24, i1 false)460// CHECK1-NEXT:    [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP36]], i32 0, i32 3461// CHECK1-NEXT:    [[TMP41:%.*]] = load i16, ptr [[AA]], align 2462// CHECK1-NEXT:    store i16 [[TMP41]], ptr [[TMP40]], align 8463// CHECK1-NEXT:    [[TMP42:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP32]])464// CHECK1-NEXT:    [[TMP43:%.*]] = load i32, ptr [[A]], align 4465// CHECK1-NEXT:    store i32 [[TMP43]], ptr [[A_CASTED]], align 4466// CHECK1-NEXT:    [[TMP44:%.*]] = load i64, ptr [[A_CASTED]], align 8467// CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105(i64 [[TMP44]]) #[[ATTR3:[0-9]+]]468// CHECK1-NEXT:    [[TMP45:%.*]] = load i16, ptr [[AA]], align 2469// CHECK1-NEXT:    store i16 [[TMP45]], ptr [[AA_CASTED4]], align 2470// CHECK1-NEXT:    [[TMP46:%.*]] = load i64, ptr [[AA_CASTED4]], align 8471// CHECK1-NEXT:    [[TMP47:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0472// CHECK1-NEXT:    store i64 [[TMP46]], ptr [[TMP47]], align 8473// CHECK1-NEXT:    [[TMP48:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0474// CHECK1-NEXT:    store i64 [[TMP46]], ptr [[TMP48]], align 8475// CHECK1-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0476// CHECK1-NEXT:    store ptr null, ptr [[TMP49]], align 8477// CHECK1-NEXT:    [[TMP50:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0478// CHECK1-NEXT:    [[TMP51:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0479// CHECK1-NEXT:    [[TMP52:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0480// CHECK1-NEXT:    store i32 3, ptr [[TMP52]], align 4481// CHECK1-NEXT:    [[TMP53:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1482// CHECK1-NEXT:    store i32 1, ptr [[TMP53]], align 4483// CHECK1-NEXT:    [[TMP54:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2484// CHECK1-NEXT:    store ptr [[TMP50]], ptr [[TMP54]], align 8485// CHECK1-NEXT:    [[TMP55:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3486// CHECK1-NEXT:    store ptr [[TMP51]], ptr [[TMP55]], align 8487// CHECK1-NEXT:    [[TMP56:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4488// CHECK1-NEXT:    store ptr @.offload_sizes.1, ptr [[TMP56]], align 8489// CHECK1-NEXT:    [[TMP57:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5490// CHECK1-NEXT:    store ptr @.offload_maptypes.2, ptr [[TMP57]], align 8491// CHECK1-NEXT:    [[TMP58:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6492// CHECK1-NEXT:    store ptr null, ptr [[TMP58]], align 8493// CHECK1-NEXT:    [[TMP59:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7494// CHECK1-NEXT:    store ptr null, ptr [[TMP59]], align 8495// CHECK1-NEXT:    [[TMP60:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8496// CHECK1-NEXT:    store i64 0, ptr [[TMP60]], align 8497// CHECK1-NEXT:    [[TMP61:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9498// CHECK1-NEXT:    store i64 0, ptr [[TMP61]], align 8499// CHECK1-NEXT:    [[TMP62:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10500// CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP62]], align 4501// CHECK1-NEXT:    [[TMP63:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11502// CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP63]], align 4503// CHECK1-NEXT:    [[TMP64:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12504// CHECK1-NEXT:    store i32 0, ptr [[TMP64]], align 4505// CHECK1-NEXT:    [[TMP65:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, ptr [[KERNEL_ARGS]])506// CHECK1-NEXT:    [[TMP66:%.*]] = icmp ne i32 [[TMP65]], 0507// CHECK1-NEXT:    br i1 [[TMP66]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]508// CHECK1:       omp_offload.failed:509// CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i64 [[TMP46]]) #[[ATTR3]]510// CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]511// CHECK1:       omp_offload.cont:512// CHECK1-NEXT:    [[TMP67:%.*]] = load i32, ptr [[A]], align 4513// CHECK1-NEXT:    store i32 [[TMP67]], ptr [[A_CASTED8]], align 4514// CHECK1-NEXT:    [[TMP68:%.*]] = load i64, ptr [[A_CASTED8]], align 8515// CHECK1-NEXT:    [[TMP69:%.*]] = load i16, ptr [[AA]], align 2516// CHECK1-NEXT:    store i16 [[TMP69]], ptr [[AA_CASTED9]], align 2517// CHECK1-NEXT:    [[TMP70:%.*]] = load i64, ptr [[AA_CASTED9]], align 8518// CHECK1-NEXT:    [[TMP71:%.*]] = load i32, ptr [[N_ADDR]], align 4519// CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP71]], 10520// CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]521// CHECK1:       omp_if.then:522// CHECK1-NEXT:    [[TMP72:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0523// CHECK1-NEXT:    store i64 [[TMP68]], ptr [[TMP72]], align 8524// CHECK1-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 0525// CHECK1-NEXT:    store i64 [[TMP68]], ptr [[TMP73]], align 8526// CHECK1-NEXT:    [[TMP74:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0527// CHECK1-NEXT:    store ptr null, ptr [[TMP74]], align 8528// CHECK1-NEXT:    [[TMP75:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1529// CHECK1-NEXT:    store i64 [[TMP70]], ptr [[TMP75]], align 8530// CHECK1-NEXT:    [[TMP76:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 1531// CHECK1-NEXT:    store i64 [[TMP70]], ptr [[TMP76]], align 8532// CHECK1-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1533// CHECK1-NEXT:    store ptr null, ptr [[TMP77]], align 8534// CHECK1-NEXT:    [[TMP78:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0535// CHECK1-NEXT:    [[TMP79:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 0536// CHECK1-NEXT:    [[TMP80:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 0537// CHECK1-NEXT:    store i32 3, ptr [[TMP80]], align 4538// CHECK1-NEXT:    [[TMP81:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 1539// CHECK1-NEXT:    store i32 2, ptr [[TMP81]], align 4540// CHECK1-NEXT:    [[TMP82:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 2541// CHECK1-NEXT:    store ptr [[TMP78]], ptr [[TMP82]], align 8542// CHECK1-NEXT:    [[TMP83:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 3543// CHECK1-NEXT:    store ptr [[TMP79]], ptr [[TMP83]], align 8544// CHECK1-NEXT:    [[TMP84:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 4545// CHECK1-NEXT:    store ptr @.offload_sizes.3, ptr [[TMP84]], align 8546// CHECK1-NEXT:    [[TMP85:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 5547// CHECK1-NEXT:    store ptr @.offload_maptypes.4, ptr [[TMP85]], align 8548// CHECK1-NEXT:    [[TMP86:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 6549// CHECK1-NEXT:    store ptr null, ptr [[TMP86]], align 8550// CHECK1-NEXT:    [[TMP87:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 7551// CHECK1-NEXT:    store ptr null, ptr [[TMP87]], align 8552// CHECK1-NEXT:    [[TMP88:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 8553// CHECK1-NEXT:    store i64 0, ptr [[TMP88]], align 8554// CHECK1-NEXT:    [[TMP89:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 9555// CHECK1-NEXT:    store i64 0, ptr [[TMP89]], align 8556// CHECK1-NEXT:    [[TMP90:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 10557// CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP90]], align 4558// CHECK1-NEXT:    [[TMP91:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 11559// CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP91]], align 4560// CHECK1-NEXT:    [[TMP92:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 12561// CHECK1-NEXT:    store i32 0, ptr [[TMP92]], align 4562// CHECK1-NEXT:    [[TMP93:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, ptr [[KERNEL_ARGS13]])563// CHECK1-NEXT:    [[TMP94:%.*]] = icmp ne i32 [[TMP93]], 0564// CHECK1-NEXT:    br i1 [[TMP94]], label [[OMP_OFFLOAD_FAILED14:%.*]], label [[OMP_OFFLOAD_CONT15:%.*]]565// CHECK1:       omp_offload.failed14:566// CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP68]], i64 [[TMP70]]) #[[ATTR3]]567// CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT15]]568// CHECK1:       omp_offload.cont15:569// CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]570// CHECK1:       omp_if.else:571// CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP68]], i64 [[TMP70]]) #[[ATTR3]]572// CHECK1-NEXT:    br label [[OMP_IF_END]]573// CHECK1:       omp_if.end:574// CHECK1-NEXT:    [[TMP95:%.*]] = load i32, ptr [[A]], align 4575// CHECK1-NEXT:    store i32 [[TMP95]], ptr [[A_CASTED16]], align 4576// CHECK1-NEXT:    [[TMP96:%.*]] = load i64, ptr [[A_CASTED16]], align 8577// CHECK1-NEXT:    [[TMP97:%.*]] = load i16, ptr [[AA]], align 2578// CHECK1-NEXT:    store i16 [[TMP97]], ptr [[AA_CASTED17]], align 2579// CHECK1-NEXT:    [[TMP98:%.*]] = load i64, ptr [[AA_CASTED17]], align 8580// CHECK1-NEXT:    [[TMP99:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 0581// CHECK1-NEXT:    store i64 [[TMP96]], ptr [[TMP99]], align 8582// CHECK1-NEXT:    [[TMP100:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS19]], i32 0, i32 0583// CHECK1-NEXT:    store i64 [[TMP96]], ptr [[TMP100]], align 8584// CHECK1-NEXT:    [[TMP101:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS20]], i64 0, i64 0585// CHECK1-NEXT:    store ptr null, ptr [[TMP101]], align 8586// CHECK1-NEXT:    [[TMP102:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 1587// CHECK1-NEXT:    store i64 [[TMP98]], ptr [[TMP102]], align 8588// CHECK1-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS19]], i32 0, i32 1589// CHECK1-NEXT:    store i64 [[TMP98]], ptr [[TMP103]], align 8590// CHECK1-NEXT:    [[TMP104:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS20]], i64 0, i64 1591// CHECK1-NEXT:    store ptr null, ptr [[TMP104]], align 8592// CHECK1-NEXT:    [[TMP105:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 0593// CHECK1-NEXT:    [[TMP106:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS19]], i32 0, i32 0594// CHECK1-NEXT:    [[TMP107:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 0595// CHECK1-NEXT:    store i32 3, ptr [[TMP107]], align 4596// CHECK1-NEXT:    [[TMP108:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 1597// CHECK1-NEXT:    store i32 2, ptr [[TMP108]], align 4598// CHECK1-NEXT:    [[TMP109:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 2599// CHECK1-NEXT:    store ptr [[TMP105]], ptr [[TMP109]], align 8600// CHECK1-NEXT:    [[TMP110:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 3601// CHECK1-NEXT:    store ptr [[TMP106]], ptr [[TMP110]], align 8602// CHECK1-NEXT:    [[TMP111:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 4603// CHECK1-NEXT:    store ptr @.offload_sizes.5, ptr [[TMP111]], align 8604// CHECK1-NEXT:    [[TMP112:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 5605// CHECK1-NEXT:    store ptr @.offload_maptypes.6, ptr [[TMP112]], align 8606// CHECK1-NEXT:    [[TMP113:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 6607// CHECK1-NEXT:    store ptr null, ptr [[TMP113]], align 8608// CHECK1-NEXT:    [[TMP114:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 7609// CHECK1-NEXT:    store ptr null, ptr [[TMP114]], align 8610// CHECK1-NEXT:    [[TMP115:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 8611// CHECK1-NEXT:    store i64 0, ptr [[TMP115]], align 8612// CHECK1-NEXT:    [[TMP116:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 9613// CHECK1-NEXT:    store i64 0, ptr [[TMP116]], align 8614// CHECK1-NEXT:    [[TMP117:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 10615// CHECK1-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP117]], align 4616// CHECK1-NEXT:    [[TMP118:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 11617// CHECK1-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP118]], align 4618// CHECK1-NEXT:    [[TMP119:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 12619// CHECK1-NEXT:    store i32 0, ptr [[TMP119]], align 4620// CHECK1-NEXT:    [[TMP120:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 1, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124.region_id, ptr [[KERNEL_ARGS21]])621// CHECK1-NEXT:    [[TMP121:%.*]] = icmp ne i32 [[TMP120]], 0622// CHECK1-NEXT:    br i1 [[TMP121]], label [[OMP_OFFLOAD_FAILED22:%.*]], label [[OMP_OFFLOAD_CONT23:%.*]]623// CHECK1:       omp_offload.failed22:624// CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124(i64 [[TMP96]], i64 [[TMP98]]) #[[ATTR3]]625// CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT23]]626// CHECK1:       omp_offload.cont23:627// CHECK1-NEXT:    [[TMP122:%.*]] = load i32, ptr [[A]], align 4628// CHECK1-NEXT:    store i32 [[TMP122]], ptr [[A_CASTED24]], align 4629// CHECK1-NEXT:    [[TMP123:%.*]] = load i64, ptr [[A_CASTED24]], align 8630// CHECK1-NEXT:    [[TMP124:%.*]] = load i16, ptr [[AA]], align 2631// CHECK1-NEXT:    store i16 [[TMP124]], ptr [[AA_CASTED25]], align 2632// CHECK1-NEXT:    [[TMP125:%.*]] = load i64, ptr [[AA_CASTED25]], align 8633// CHECK1-NEXT:    [[TMP126:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 0634// CHECK1-NEXT:    store i64 [[TMP123]], ptr [[TMP126]], align 8635// CHECK1-NEXT:    [[TMP127:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS27]], i32 0, i32 0636// CHECK1-NEXT:    store i64 [[TMP123]], ptr [[TMP127]], align 8637// CHECK1-NEXT:    [[TMP128:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 0638// CHECK1-NEXT:    store ptr null, ptr [[TMP128]], align 8639// CHECK1-NEXT:    [[TMP129:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 1640// CHECK1-NEXT:    store i64 [[TMP125]], ptr [[TMP129]], align 8641// CHECK1-NEXT:    [[TMP130:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS27]], i32 0, i32 1642// CHECK1-NEXT:    store i64 [[TMP125]], ptr [[TMP130]], align 8643// CHECK1-NEXT:    [[TMP131:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 1644// CHECK1-NEXT:    store ptr null, ptr [[TMP131]], align 8645// CHECK1-NEXT:    [[TMP132:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 0646// CHECK1-NEXT:    [[TMP133:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS27]], i32 0, i32 0647// CHECK1-NEXT:    [[TMP134:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 0648// CHECK1-NEXT:    store i32 3, ptr [[TMP134]], align 4649// CHECK1-NEXT:    [[TMP135:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 1650// CHECK1-NEXT:    store i32 2, ptr [[TMP135]], align 4651// CHECK1-NEXT:    [[TMP136:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 2652// CHECK1-NEXT:    store ptr [[TMP132]], ptr [[TMP136]], align 8653// CHECK1-NEXT:    [[TMP137:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 3654// CHECK1-NEXT:    store ptr [[TMP133]], ptr [[TMP137]], align 8655// CHECK1-NEXT:    [[TMP138:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 4656// CHECK1-NEXT:    store ptr @.offload_sizes.7, ptr [[TMP138]], align 8657// CHECK1-NEXT:    [[TMP139:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 5658// CHECK1-NEXT:    store ptr @.offload_maptypes.8, ptr [[TMP139]], align 8659// CHECK1-NEXT:    [[TMP140:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 6660// CHECK1-NEXT:    store ptr null, ptr [[TMP140]], align 8661// CHECK1-NEXT:    [[TMP141:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 7662// CHECK1-NEXT:    store ptr null, ptr [[TMP141]], align 8663// CHECK1-NEXT:    [[TMP142:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 8664// CHECK1-NEXT:    store i64 0, ptr [[TMP142]], align 8665// CHECK1-NEXT:    [[TMP143:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 9666// CHECK1-NEXT:    store i64 0, ptr [[TMP143]], align 8667// CHECK1-NEXT:    [[TMP144:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 10668// CHECK1-NEXT:    store [3 x i32] [i32 1, i32 2, i32 0], ptr [[TMP144]], align 4669// CHECK1-NEXT:    [[TMP145:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 11670// CHECK1-NEXT:    store [3 x i32] [i32 1, i32 2, i32 0], ptr [[TMP145]], align 4671// CHECK1-NEXT:    [[TMP146:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 12672// CHECK1-NEXT:    store i32 0, ptr [[TMP146]], align 4673// CHECK1-NEXT:    [[TMP147:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 1, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l130.region_id, ptr [[KERNEL_ARGS29]])674// CHECK1-NEXT:    [[TMP148:%.*]] = icmp ne i32 [[TMP147]], 0675// CHECK1-NEXT:    br i1 [[TMP148]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]]676// CHECK1:       omp_offload.failed30:677// CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l130(i64 [[TMP123]], i64 [[TMP125]]) #[[ATTR3]]678// CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT31]]679// CHECK1:       omp_offload.cont31:680// CHECK1-NEXT:    [[TMP149:%.*]] = load i32, ptr [[A]], align 4681// CHECK1-NEXT:    store i32 [[TMP149]], ptr [[A_CASTED32]], align 4682// CHECK1-NEXT:    [[TMP150:%.*]] = load i64, ptr [[A_CASTED32]], align 8683// CHECK1-NEXT:    [[TMP151:%.*]] = load i16, ptr [[AA]], align 2684// CHECK1-NEXT:    store i16 [[TMP151]], ptr [[AA_CASTED33]], align 2685// CHECK1-NEXT:    [[TMP152:%.*]] = load i64, ptr [[AA_CASTED33]], align 8686// CHECK1-NEXT:    [[TMP153:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 0687// CHECK1-NEXT:    store i64 [[TMP150]], ptr [[TMP153]], align 8688// CHECK1-NEXT:    [[TMP154:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS35]], i32 0, i32 0689// CHECK1-NEXT:    store i64 [[TMP150]], ptr [[TMP154]], align 8690// CHECK1-NEXT:    [[TMP155:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS36]], i64 0, i64 0691// CHECK1-NEXT:    store ptr null, ptr [[TMP155]], align 8692// CHECK1-NEXT:    [[TMP156:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 1693// CHECK1-NEXT:    store i64 [[TMP152]], ptr [[TMP156]], align 8694// CHECK1-NEXT:    [[TMP157:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS35]], i32 0, i32 1695// CHECK1-NEXT:    store i64 [[TMP152]], ptr [[TMP157]], align 8696// CHECK1-NEXT:    [[TMP158:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS36]], i64 0, i64 1697// CHECK1-NEXT:    store ptr null, ptr [[TMP158]], align 8698// CHECK1-NEXT:    [[TMP159:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 0699// CHECK1-NEXT:    [[TMP160:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS35]], i32 0, i32 0700// CHECK1-NEXT:    [[TMP161:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 0701// CHECK1-NEXT:    store i32 3, ptr [[TMP161]], align 4702// CHECK1-NEXT:    [[TMP162:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 1703// CHECK1-NEXT:    store i32 2, ptr [[TMP162]], align 4704// CHECK1-NEXT:    [[TMP163:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 2705// CHECK1-NEXT:    store ptr [[TMP159]], ptr [[TMP163]], align 8706// CHECK1-NEXT:    [[TMP164:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 3707// CHECK1-NEXT:    store ptr [[TMP160]], ptr [[TMP164]], align 8708// CHECK1-NEXT:    [[TMP165:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 4709// CHECK1-NEXT:    store ptr @.offload_sizes.9, ptr [[TMP165]], align 8710// CHECK1-NEXT:    [[TMP166:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 5711// CHECK1-NEXT:    store ptr @.offload_maptypes.10, ptr [[TMP166]], align 8712// CHECK1-NEXT:    [[TMP167:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 6713// CHECK1-NEXT:    store ptr null, ptr [[TMP167]], align 8714// CHECK1-NEXT:    [[TMP168:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 7715// CHECK1-NEXT:    store ptr null, ptr [[TMP168]], align 8716// CHECK1-NEXT:    [[TMP169:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 8717// CHECK1-NEXT:    store i64 0, ptr [[TMP169]], align 8718// CHECK1-NEXT:    [[TMP170:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 9719// CHECK1-NEXT:    store i64 0, ptr [[TMP170]], align 8720// CHECK1-NEXT:    [[TMP171:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 10721// CHECK1-NEXT:    store [3 x i32] [i32 1, i32 2, i32 3], ptr [[TMP171]], align 4722// CHECK1-NEXT:    [[TMP172:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 11723// CHECK1-NEXT:    store [3 x i32] [i32 1, i32 2, i32 3], ptr [[TMP172]], align 4724// CHECK1-NEXT:    [[TMP173:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 12725// CHECK1-NEXT:    store i32 0, ptr [[TMP173]], align 4726// CHECK1-NEXT:    [[TMP174:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 1, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.region_id, ptr [[KERNEL_ARGS37]])727// CHECK1-NEXT:    [[TMP175:%.*]] = icmp ne i32 [[TMP174]], 0728// CHECK1-NEXT:    br i1 [[TMP175]], label [[OMP_OFFLOAD_FAILED38:%.*]], label [[OMP_OFFLOAD_CONT39:%.*]]729// CHECK1:       omp_offload.failed38:730// CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136(i64 [[TMP150]], i64 [[TMP152]]) #[[ATTR3]]731// CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT39]]732// CHECK1:       omp_offload.cont39:733// CHECK1-NEXT:    [[TMP176:%.*]] = load i32, ptr [[A]], align 4734// CHECK1-NEXT:    store i32 [[TMP176]], ptr [[A_CASTED40]], align 4735// CHECK1-NEXT:    [[TMP177:%.*]] = load i64, ptr [[A_CASTED40]], align 8736// CHECK1-NEXT:    [[TMP178:%.*]] = load i32, ptr [[N_ADDR]], align 4737// CHECK1-NEXT:    [[CMP41:%.*]] = icmp sgt i32 [[TMP178]], 20738// CHECK1-NEXT:    br i1 [[CMP41]], label [[OMP_IF_THEN42:%.*]], label [[OMP_IF_ELSE49:%.*]]739// CHECK1:       omp_if.then42:740// CHECK1-NEXT:    [[TMP179:%.*]] = mul nuw i64 [[TMP2]], 4741// CHECK1-NEXT:    [[TMP180:%.*]] = mul nuw i64 5, [[TMP5]]742// CHECK1-NEXT:    [[TMP181:%.*]] = mul nuw i64 [[TMP180]], 8743// CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.11, i64 72, i1 false)744// CHECK1-NEXT:    [[TMP182:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS43]], i32 0, i32 0745// CHECK1-NEXT:    store i64 [[TMP177]], ptr [[TMP182]], align 8746// CHECK1-NEXT:    [[TMP183:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS44]], i32 0, i32 0747// CHECK1-NEXT:    store i64 [[TMP177]], ptr [[TMP183]], align 8748// CHECK1-NEXT:    [[TMP184:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS45]], i64 0, i64 0749// CHECK1-NEXT:    store ptr null, ptr [[TMP184]], align 8750// CHECK1-NEXT:    [[TMP185:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS43]], i32 0, i32 1751// CHECK1-NEXT:    store ptr [[B]], ptr [[TMP185]], align 8752// CHECK1-NEXT:    [[TMP186:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS44]], i32 0, i32 1753// CHECK1-NEXT:    store ptr [[B]], ptr [[TMP186]], align 8754// CHECK1-NEXT:    [[TMP187:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS45]], i64 0, i64 1755// CHECK1-NEXT:    store ptr null, ptr [[TMP187]], align 8756// CHECK1-NEXT:    [[TMP188:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS43]], i32 0, i32 2757// CHECK1-NEXT:    store i64 [[TMP2]], ptr [[TMP188]], align 8758// CHECK1-NEXT:    [[TMP189:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS44]], i32 0, i32 2759// CHECK1-NEXT:    store i64 [[TMP2]], ptr [[TMP189]], align 8760// CHECK1-NEXT:    [[TMP190:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS45]], i64 0, i64 2761// CHECK1-NEXT:    store ptr null, ptr [[TMP190]], align 8762// CHECK1-NEXT:    [[TMP191:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS43]], i32 0, i32 3763// CHECK1-NEXT:    store ptr [[VLA]], ptr [[TMP191]], align 8764// CHECK1-NEXT:    [[TMP192:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS44]], i32 0, i32 3765// CHECK1-NEXT:    store ptr [[VLA]], ptr [[TMP192]], align 8766// CHECK1-NEXT:    [[TMP193:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3767// CHECK1-NEXT:    store i64 [[TMP179]], ptr [[TMP193]], align 8768// CHECK1-NEXT:    [[TMP194:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS45]], i64 0, i64 3769// CHECK1-NEXT:    store ptr null, ptr [[TMP194]], align 8770// CHECK1-NEXT:    [[TMP195:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS43]], i32 0, i32 4771// CHECK1-NEXT:    store ptr [[C]], ptr [[TMP195]], align 8772// CHECK1-NEXT:    [[TMP196:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS44]], i32 0, i32 4773// CHECK1-NEXT:    store ptr [[C]], ptr [[TMP196]], align 8774// CHECK1-NEXT:    [[TMP197:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS45]], i64 0, i64 4775// CHECK1-NEXT:    store ptr null, ptr [[TMP197]], align 8776// CHECK1-NEXT:    [[TMP198:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS43]], i32 0, i32 5777// CHECK1-NEXT:    store i64 5, ptr [[TMP198]], align 8778// CHECK1-NEXT:    [[TMP199:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS44]], i32 0, i32 5779// CHECK1-NEXT:    store i64 5, ptr [[TMP199]], align 8780// CHECK1-NEXT:    [[TMP200:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS45]], i64 0, i64 5781// CHECK1-NEXT:    store ptr null, ptr [[TMP200]], align 8782// CHECK1-NEXT:    [[TMP201:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS43]], i32 0, i32 6783// CHECK1-NEXT:    store i64 [[TMP5]], ptr [[TMP201]], align 8784// CHECK1-NEXT:    [[TMP202:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS44]], i32 0, i32 6785// CHECK1-NEXT:    store i64 [[TMP5]], ptr [[TMP202]], align 8786// CHECK1-NEXT:    [[TMP203:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS45]], i64 0, i64 6787// CHECK1-NEXT:    store ptr null, ptr [[TMP203]], align 8788// CHECK1-NEXT:    [[TMP204:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS43]], i32 0, i32 7789// CHECK1-NEXT:    store ptr [[VLA1]], ptr [[TMP204]], align 8790// CHECK1-NEXT:    [[TMP205:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS44]], i32 0, i32 7791// CHECK1-NEXT:    store ptr [[VLA1]], ptr [[TMP205]], align 8792// CHECK1-NEXT:    [[TMP206:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 7793// CHECK1-NEXT:    store i64 [[TMP181]], ptr [[TMP206]], align 8794// CHECK1-NEXT:    [[TMP207:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS45]], i64 0, i64 7795// CHECK1-NEXT:    store ptr null, ptr [[TMP207]], align 8796// CHECK1-NEXT:    [[TMP208:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS43]], i32 0, i32 8797// CHECK1-NEXT:    store ptr [[D]], ptr [[TMP208]], align 8798// CHECK1-NEXT:    [[TMP209:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS44]], i32 0, i32 8799// CHECK1-NEXT:    store ptr [[D]], ptr [[TMP209]], align 8800// CHECK1-NEXT:    [[TMP210:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS45]], i64 0, i64 8801// CHECK1-NEXT:    store ptr null, ptr [[TMP210]], align 8802// CHECK1-NEXT:    [[TMP211:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS43]], i32 0, i32 0803// CHECK1-NEXT:    [[TMP212:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS44]], i32 0, i32 0804// CHECK1-NEXT:    [[TMP213:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0805// CHECK1-NEXT:    [[TMP214:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 0806// CHECK1-NEXT:    store i32 3, ptr [[TMP214]], align 4807// CHECK1-NEXT:    [[TMP215:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 1808// CHECK1-NEXT:    store i32 9, ptr [[TMP215]], align 4809// CHECK1-NEXT:    [[TMP216:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 2810// CHECK1-NEXT:    store ptr [[TMP211]], ptr [[TMP216]], align 8811// CHECK1-NEXT:    [[TMP217:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 3812// CHECK1-NEXT:    store ptr [[TMP212]], ptr [[TMP217]], align 8813// CHECK1-NEXT:    [[TMP218:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 4814// CHECK1-NEXT:    store ptr [[TMP213]], ptr [[TMP218]], align 8815// CHECK1-NEXT:    [[TMP219:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 5816// CHECK1-NEXT:    store ptr @.offload_maptypes.12, ptr [[TMP219]], align 8817// CHECK1-NEXT:    [[TMP220:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 6818// CHECK1-NEXT:    store ptr null, ptr [[TMP220]], align 8819// CHECK1-NEXT:    [[TMP221:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 7820// CHECK1-NEXT:    store ptr null, ptr [[TMP221]], align 8821// CHECK1-NEXT:    [[TMP222:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 8822// CHECK1-NEXT:    store i64 0, ptr [[TMP222]], align 8823// CHECK1-NEXT:    [[TMP223:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 9824// CHECK1-NEXT:    store i64 0, ptr [[TMP223]], align 8825// CHECK1-NEXT:    [[TMP224:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 10826// CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP224]], align 4827// CHECK1-NEXT:    [[TMP225:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 11828// CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP225]], align 4829// CHECK1-NEXT:    [[TMP226:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 12830// CHECK1-NEXT:    store i32 0, ptr [[TMP226]], align 4831// CHECK1-NEXT:    [[TMP227:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.region_id, ptr [[KERNEL_ARGS46]])832// CHECK1-NEXT:    [[TMP228:%.*]] = icmp ne i32 [[TMP227]], 0833// CHECK1-NEXT:    br i1 [[TMP228]], label [[OMP_OFFLOAD_FAILED47:%.*]], label [[OMP_OFFLOAD_CONT48:%.*]]834// CHECK1:       omp_offload.failed47:835// CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i64 [[TMP177]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]]836// CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT48]]837// CHECK1:       omp_offload.cont48:838// CHECK1-NEXT:    br label [[OMP_IF_END50:%.*]]839// CHECK1:       omp_if.else49:840// CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i64 [[TMP177]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]]841// CHECK1-NEXT:    br label [[OMP_IF_END50]]842// CHECK1:       omp_if.end50:843// CHECK1-NEXT:    store i32 0, ptr [[NN]], align 4844// CHECK1-NEXT:    [[TMP229:%.*]] = load i32, ptr [[NN]], align 4845// CHECK1-NEXT:    store i32 [[TMP229]], ptr [[NN_CASTED]], align 4846// CHECK1-NEXT:    [[TMP230:%.*]] = load i64, ptr [[NN_CASTED]], align 8847// CHECK1-NEXT:    [[TMP231:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS51]], i32 0, i32 0848// CHECK1-NEXT:    store i64 [[TMP230]], ptr [[TMP231]], align 8849// CHECK1-NEXT:    [[TMP232:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS52]], i32 0, i32 0850// CHECK1-NEXT:    store i64 [[TMP230]], ptr [[TMP232]], align 8851// CHECK1-NEXT:    [[TMP233:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS53]], i64 0, i64 0852// CHECK1-NEXT:    store ptr null, ptr [[TMP233]], align 8853// CHECK1-NEXT:    [[TMP234:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS51]], i32 0, i32 0854// CHECK1-NEXT:    [[TMP235:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS52]], i32 0, i32 0855// CHECK1-NEXT:    [[TMP236:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 0856// CHECK1-NEXT:    store i32 3, ptr [[TMP236]], align 4857// CHECK1-NEXT:    [[TMP237:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 1858// CHECK1-NEXT:    store i32 1, ptr [[TMP237]], align 4859// CHECK1-NEXT:    [[TMP238:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 2860// CHECK1-NEXT:    store ptr [[TMP234]], ptr [[TMP238]], align 8861// CHECK1-NEXT:    [[TMP239:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 3862// CHECK1-NEXT:    store ptr [[TMP235]], ptr [[TMP239]], align 8863// CHECK1-NEXT:    [[TMP240:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 4864// CHECK1-NEXT:    store ptr @.offload_sizes.13, ptr [[TMP240]], align 8865// CHECK1-NEXT:    [[TMP241:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 5866// CHECK1-NEXT:    store ptr @.offload_maptypes.14, ptr [[TMP241]], align 8867// CHECK1-NEXT:    [[TMP242:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 6868// CHECK1-NEXT:    store ptr null, ptr [[TMP242]], align 8869// CHECK1-NEXT:    [[TMP243:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 7870// CHECK1-NEXT:    store ptr null, ptr [[TMP243]], align 8871// CHECK1-NEXT:    [[TMP244:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 8872// CHECK1-NEXT:    store i64 0, ptr [[TMP244]], align 8873// CHECK1-NEXT:    [[TMP245:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 9874// CHECK1-NEXT:    store i64 0, ptr [[TMP245]], align 8875// CHECK1-NEXT:    [[TMP246:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 10876// CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP246]], align 4877// CHECK1-NEXT:    [[TMP247:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 11878// CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP247]], align 4879// CHECK1-NEXT:    [[TMP248:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 12880// CHECK1-NEXT:    store i32 0, ptr [[TMP248]], align 4881// CHECK1-NEXT:    [[TMP249:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172.region_id, ptr [[KERNEL_ARGS54]])882// CHECK1-NEXT:    [[TMP250:%.*]] = icmp ne i32 [[TMP249]], 0883// CHECK1-NEXT:    br i1 [[TMP250]], label [[OMP_OFFLOAD_FAILED55:%.*]], label [[OMP_OFFLOAD_CONT56:%.*]]884// CHECK1:       omp_offload.failed55:885// CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172(i64 [[TMP230]]) #[[ATTR3]]886// CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT56]]887// CHECK1:       omp_offload.cont56:888// CHECK1-NEXT:    [[TMP251:%.*]] = load i32, ptr [[NN]], align 4889// CHECK1-NEXT:    store i32 [[TMP251]], ptr [[NN_CASTED57]], align 4890// CHECK1-NEXT:    [[TMP252:%.*]] = load i64, ptr [[NN_CASTED57]], align 8891// CHECK1-NEXT:    [[TMP253:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS58]], i32 0, i32 0892// CHECK1-NEXT:    store i64 [[TMP252]], ptr [[TMP253]], align 8893// CHECK1-NEXT:    [[TMP254:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS59]], i32 0, i32 0894// CHECK1-NEXT:    store i64 [[TMP252]], ptr [[TMP254]], align 8895// CHECK1-NEXT:    [[TMP255:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS60]], i64 0, i64 0896// CHECK1-NEXT:    store ptr null, ptr [[TMP255]], align 8897// CHECK1-NEXT:    [[TMP256:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS58]], i32 0, i32 0898// CHECK1-NEXT:    [[TMP257:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS59]], i32 0, i32 0899// CHECK1-NEXT:    [[TMP258:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 0900// CHECK1-NEXT:    store i32 3, ptr [[TMP258]], align 4901// CHECK1-NEXT:    [[TMP259:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 1902// CHECK1-NEXT:    store i32 1, ptr [[TMP259]], align 4903// CHECK1-NEXT:    [[TMP260:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 2904// CHECK1-NEXT:    store ptr [[TMP256]], ptr [[TMP260]], align 8905// CHECK1-NEXT:    [[TMP261:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 3906// CHECK1-NEXT:    store ptr [[TMP257]], ptr [[TMP261]], align 8907// CHECK1-NEXT:    [[TMP262:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 4908// CHECK1-NEXT:    store ptr @.offload_sizes.15, ptr [[TMP262]], align 8909// CHECK1-NEXT:    [[TMP263:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 5910// CHECK1-NEXT:    store ptr @.offload_maptypes.16, ptr [[TMP263]], align 8911// CHECK1-NEXT:    [[TMP264:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 6912// CHECK1-NEXT:    store ptr null, ptr [[TMP264]], align 8913// CHECK1-NEXT:    [[TMP265:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 7914// CHECK1-NEXT:    store ptr null, ptr [[TMP265]], align 8915// CHECK1-NEXT:    [[TMP266:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 8916// CHECK1-NEXT:    store i64 0, ptr [[TMP266]], align 8917// CHECK1-NEXT:    [[TMP267:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 9918// CHECK1-NEXT:    store i64 0, ptr [[TMP267]], align 8919// CHECK1-NEXT:    [[TMP268:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 10920// CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP268]], align 4921// CHECK1-NEXT:    [[TMP269:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 11922// CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP269]], align 4923// CHECK1-NEXT:    [[TMP270:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 12924// CHECK1-NEXT:    store i32 0, ptr [[TMP270]], align 4925// CHECK1-NEXT:    [[TMP271:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175.region_id, ptr [[KERNEL_ARGS61]])926// CHECK1-NEXT:    [[TMP272:%.*]] = icmp ne i32 [[TMP271]], 0927// CHECK1-NEXT:    br i1 [[TMP272]], label [[OMP_OFFLOAD_FAILED62:%.*]], label [[OMP_OFFLOAD_CONT63:%.*]]928// CHECK1:       omp_offload.failed62:929// CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175(i64 [[TMP252]]) #[[ATTR3]]930// CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT63]]931// CHECK1:       omp_offload.cont63:932// CHECK1-NEXT:    [[TMP273:%.*]] = load i32, ptr [[A]], align 4933// CHECK1-NEXT:    [[TMP274:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8934// CHECK1-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP274]])935// CHECK1-NEXT:    ret i32 [[TMP273]]936//937//938// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101939// CHECK1-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {940// CHECK1-NEXT:  entry:941// CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8942// CHECK1-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8943// CHECK1-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8944// CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8945// CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])946// CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8947// CHECK1-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8948// CHECK1-NEXT:    store i64 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 8949// CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4950// CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4951// CHECK1-NEXT:    call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])952// CHECK1-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2953// CHECK1-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2954// CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8955// CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined, i64 [[TMP4]])956// CHECK1-NEXT:    ret void957//958//959// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined960// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {961// CHECK1-NEXT:  entry:962// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8963// CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8964// CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8965// CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8966// CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8967// CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8968// CHECK1-NEXT:    ret void969//970//971// CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map.972// CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] {973// CHECK1-NEXT:  entry:974// CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8975// CHECK1-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 8976// CHECK1-NEXT:    [[DOTADDR2:%.*]] = alloca ptr, align 8977// CHECK1-NEXT:    [[DOTADDR3:%.*]] = alloca ptr, align 8978// CHECK1-NEXT:    [[DOTADDR4:%.*]] = alloca ptr, align 8979// CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8980// CHECK1-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 8981// CHECK1-NEXT:    store ptr [[TMP2]], ptr [[DOTADDR2]], align 8982// CHECK1-NEXT:    store ptr [[TMP3]], ptr [[DOTADDR3]], align 8983// CHECK1-NEXT:    store ptr [[TMP4]], ptr [[DOTADDR4]], align 8984// CHECK1-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 8985// CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP5]], i32 0, i32 0986// CHECK1-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTADDR2]], align 8987// CHECK1-NEXT:    store ptr [[TMP6]], ptr [[TMP7]], align 8988// CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 1989// CHECK1-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[DOTADDR3]], align 8990// CHECK1-NEXT:    store ptr [[TMP8]], ptr [[TMP9]], align 8991// CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 2992// CHECK1-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[DOTADDR4]], align 8993// CHECK1-NEXT:    store ptr [[TMP10]], ptr [[TMP11]], align 8994// CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 3995// CHECK1-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[DOTADDR1]], align 8996// CHECK1-NEXT:    store ptr [[TMP12]], ptr [[TMP13]], align 8997// CHECK1-NEXT:    ret void998//999//1000// CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry.1001// CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {1002// CHECK1-NEXT:  entry:1003// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 41004// CHECK1-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 81005// CHECK1-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 81006// CHECK1-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 81007// CHECK1-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 81008// CHECK1-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 81009// CHECK1-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 81010// CHECK1-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 81011// CHECK1-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca ptr, align 81012// CHECK1-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca ptr, align 81013// CHECK1-NEXT:    [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81014// CHECK1-NEXT:    [[AA_CASTED_I:%.*]] = alloca i64, align 81015// CHECK1-NEXT:    [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 81016// CHECK1-NEXT:    [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i64, align 81017// CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 41018// CHECK1-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 81019// CHECK1-NEXT:    store i32 [[TMP0]], ptr [[DOTADDR]], align 41020// CHECK1-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 81021// CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 41022// CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 81023// CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 01024// CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 21025// CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 01026// CHECK1-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 81027// CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 11028// CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])1029// CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])1030// CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])1031// CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]])1032// CHECK1-NEXT:    store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META27:![0-9]+]]1033// CHECK1-NEXT:    store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META27]]1034// CHECK1-NEXT:    store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META27]]1035// CHECK1-NEXT:    store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META27]]1036// CHECK1-NEXT:    store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META27]]1037// CHECK1-NEXT:    store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META27]]1038// CHECK1-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META27]]1039// CHECK1-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META27]]1040// CHECK1-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META27]]1041// CHECK1-NEXT:    call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]1042// CHECK1-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META27]]1043// CHECK1-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META27]]1044// CHECK1-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias [[META27]]1045// CHECK1-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias [[META27]]1046// CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP9]], i32 0, i32 11047// CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 21048// CHECK1-NEXT:    [[TMP18:%.*]] = load i32, ptr [[TMP16]], align 41049// CHECK1-NEXT:    [[TMP19:%.*]] = load i32, ptr [[TMP17]], align 41050// CHECK1-NEXT:    [[TMP20:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP18]], 01051// CHECK1-NEXT:    [[TMP21:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP19]], 01052// CHECK1-NEXT:    store i32 3, ptr [[KERNEL_ARGS_I]], align 4, !noalias [[META27]]1053// CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 11054// CHECK1-NEXT:    store i32 3, ptr [[TMP22]], align 4, !noalias [[META27]]1055// CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 21056// CHECK1-NEXT:    store ptr [[TMP13]], ptr [[TMP23]], align 8, !noalias [[META27]]1057// CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 31058// CHECK1-NEXT:    store ptr [[TMP14]], ptr [[TMP24]], align 8, !noalias [[META27]]1059// CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 41060// CHECK1-NEXT:    store ptr [[TMP15]], ptr [[TMP25]], align 8, !noalias [[META27]]1061// CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 51062// CHECK1-NEXT:    store ptr @.offload_maptypes, ptr [[TMP26]], align 8, !noalias [[META27]]1063// CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 61064// CHECK1-NEXT:    store ptr null, ptr [[TMP27]], align 8, !noalias [[META27]]1065// CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 71066// CHECK1-NEXT:    store ptr null, ptr [[TMP28]], align 8, !noalias [[META27]]1067// CHECK1-NEXT:    [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 81068// CHECK1-NEXT:    store i64 0, ptr [[TMP29]], align 8, !noalias [[META27]]1069// CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 91070// CHECK1-NEXT:    store i64 1, ptr [[TMP30]], align 8, !noalias [[META27]]1071// CHECK1-NEXT:    [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 101072// CHECK1-NEXT:    store [3 x i32] [[TMP20]], ptr [[TMP31]], align 4, !noalias [[META27]]1073// CHECK1-NEXT:    [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 111074// CHECK1-NEXT:    store [3 x i32] [[TMP21]], ptr [[TMP32]], align 4, !noalias [[META27]]1075// CHECK1-NEXT:    [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 121076// CHECK1-NEXT:    store i32 0, ptr [[TMP33]], align 4, !noalias [[META27]]1077// CHECK1-NEXT:    [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 [[TMP18]], i32 [[TMP19]], ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, ptr [[KERNEL_ARGS_I]])1078// CHECK1-NEXT:    [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 01079// CHECK1-NEXT:    br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]]1080// CHECK1:       omp_offload.failed.i:1081// CHECK1-NEXT:    [[TMP36:%.*]] = load i16, ptr [[TMP12]], align 21082// CHECK1-NEXT:    store i16 [[TMP36]], ptr [[AA_CASTED_I]], align 2, !noalias [[META27]]1083// CHECK1-NEXT:    [[TMP37:%.*]] = load i64, ptr [[AA_CASTED_I]], align 8, !noalias [[META27]]1084// CHECK1-NEXT:    [[TMP38:%.*]] = load i32, ptr [[TMP16]], align 41085// CHECK1-NEXT:    store i32 [[TMP38]], ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias [[META27]]1086// CHECK1-NEXT:    [[TMP39:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias [[META27]]1087// CHECK1-NEXT:    [[TMP40:%.*]] = load i32, ptr [[TMP17]], align 41088// CHECK1-NEXT:    store i32 [[TMP40]], ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias [[META27]]1089// CHECK1-NEXT:    [[TMP41:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 8, !noalias [[META27]]1090// CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP37]], i64 [[TMP39]], i64 [[TMP41]]) #[[ATTR3]]1091// CHECK1-NEXT:    br label [[DOTOMP_OUTLINED__EXIT]]1092// CHECK1:       .omp_outlined..exit:1093// CHECK1-NEXT:    ret i32 01094//1095//1096// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1051097// CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR2]] {1098// CHECK1-NEXT:  entry:1099// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 81100// CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 81101// CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 81102// CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41103// CHECK1-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 41104// CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 81105// CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105.omp_outlined, i64 [[TMP1]])1106// CHECK1-NEXT:    ret void1107//1108//1109// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105.omp_outlined1110// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] {1111// CHECK1-NEXT:  entry:1112// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81113// CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81114// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 81115// CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81116// CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81117// CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 81118// CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41119// CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 11120// CHECK1-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 41121// CHECK1-NEXT:    ret void1122//1123//1124// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1111125// CHECK1-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] {1126// CHECK1-NEXT:  entry:1127// CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 81128// CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 81129// CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 81130// CHECK1-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 21131// CHECK1-NEXT:    store i16 [[TMP0]], ptr [[AA_CASTED]], align 21132// CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 81133// CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i64 [[TMP1]])1134// CHECK1-NEXT:    ret void1135//1136//1137// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined1138// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {1139// CHECK1-NEXT:  entry:1140// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81141// CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81142// CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 81143// CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81144// CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81145// CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 81146// CHECK1-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 21147// CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP0]] to i321148// CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 11149// CHECK1-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i161150// CHECK1-NEXT:    store i16 [[CONV1]], ptr [[AA_ADDR]], align 21151// CHECK1-NEXT:    ret void1152//1153//1154// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1181155// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {1156// CHECK1-NEXT:  entry:1157// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 81158// CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 81159// CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 81160// CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 81161// CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 81162// CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 81163// CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41164// CHECK1-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 41165// CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 81166// CHECK1-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 21167// CHECK1-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 21168// CHECK1-NEXT:    [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 81169// CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i64 [[TMP1]], i64 [[TMP3]])1170// CHECK1-NEXT:    ret void1171//1172//1173// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined1174// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {1175// CHECK1-NEXT:  entry:1176// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81177// CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81178// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 81179// CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 81180// CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81181// CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81182// CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 81183// CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 81184// CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41185// CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 11186// CHECK1-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 41187// CHECK1-NEXT:    [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 21188// CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i321189// CHECK1-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 11190// CHECK1-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i161191// CHECK1-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 21192// CHECK1-NEXT:    ret void1193//1194//1195// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1241196// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {1197// CHECK1-NEXT:  entry:1198// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 81199// CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 81200// CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 81201// CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 81202// CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])1203// CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 81204// CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 81205// CHECK1-NEXT:    call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 1)1206// CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 41207// CHECK1-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 41208// CHECK1-NEXT:    [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 81209// CHECK1-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 21210// CHECK1-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 21211// CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 81212// CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124.omp_outlined, i64 [[TMP2]], i64 [[TMP4]])1213// CHECK1-NEXT:    ret void1214//1215//1216// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124.omp_outlined1217// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {1218// CHECK1-NEXT:  entry:1219// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81220// CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81221// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 81222// CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 81223// CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81224// CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81225// CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 81226// CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 81227// CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41228// CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 11229// CHECK1-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 41230// CHECK1-NEXT:    [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 21231// CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i321232// CHECK1-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 11233// CHECK1-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i161234// CHECK1-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 21235// CHECK1-NEXT:    ret void1236//1237//1238// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1301239// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {1240// CHECK1-NEXT:  entry:1241// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 81242// CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 81243// CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 81244// CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 81245// CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])1246// CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 81247// CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 81248// CHECK1-NEXT:    call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 1)1249// CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 41250// CHECK1-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 41251// CHECK1-NEXT:    [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 81252// CHECK1-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 21253// CHECK1-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 21254// CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 81255// CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l130.omp_outlined, i64 [[TMP2]], i64 [[TMP4]])1256// CHECK1-NEXT:    ret void1257//1258//1259// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l130.omp_outlined1260// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {1261// CHECK1-NEXT:  entry:1262// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81263// CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81264// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 81265// CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 81266// CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81267// CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81268// CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 81269// CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 81270// CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41271// CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 11272// CHECK1-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 41273// CHECK1-NEXT:    [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 21274// CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i321275// CHECK1-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 11276// CHECK1-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i161277// CHECK1-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 21278// CHECK1-NEXT:    ret void1279//1280//1281// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1361282// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {1283// CHECK1-NEXT:  entry:1284// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 81285// CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 81286// CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 81287// CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 81288// CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])1289// CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 81290// CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 81291// CHECK1-NEXT:    call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 1)1292// CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 41293// CHECK1-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 41294// CHECK1-NEXT:    [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 81295// CHECK1-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 21296// CHECK1-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 21297// CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 81298// CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined, i64 [[TMP2]], i64 [[TMP4]])1299// CHECK1-NEXT:    ret void1300//1301//1302// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined1303// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {1304// CHECK1-NEXT:  entry:1305// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81306// CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81307// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 81308// CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 81309// CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81310// CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81311// CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 81312// CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 81313// CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41314// CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 11315// CHECK1-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 41316// CHECK1-NEXT:    [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 21317// CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i321318// CHECK1-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 11319// CHECK1-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i161320// CHECK1-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 21321// CHECK1-NEXT:    ret void1322//1323//1324// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1601325// CHECK1-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {1326// CHECK1-NEXT:  entry:1327// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 81328// CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 81329// CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 81330// CHECK1-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 81331// CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 81332// CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 81333// CHECK1-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 81334// CHECK1-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 81335// CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 81336// CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 81337// CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 81338// CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 81339// CHECK1-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 81340// CHECK1-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 81341// CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 81342// CHECK1-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 81343// CHECK1-NEXT:    store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 81344// CHECK1-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 81345// CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 81346// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 81347// CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 81348// CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 81349// CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 81350// CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 81351// CHECK1-NEXT:    [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 81352// CHECK1-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 81353// CHECK1-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 81354// CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 41355// CHECK1-NEXT:    store i32 [[TMP8]], ptr [[A_CASTED]], align 41356// CHECK1-NEXT:    [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 81357// CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]])1358// CHECK1-NEXT:    ret void1359//1360//1361// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined1362// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {1363// CHECK1-NEXT:  entry:1364// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81365// CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81366// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 81367// CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 81368// CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 81369// CHECK1-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 81370// CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 81371// CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 81372// CHECK1-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 81373// CHECK1-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 81374// CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 81375// CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81376// CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81377// CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 81378// CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 81379// CHECK1-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 81380// CHECK1-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 81381// CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 81382// CHECK1-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 81383// CHECK1-NEXT:    store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 81384// CHECK1-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 81385// CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 81386// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 81387// CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 81388// CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 81389// CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 81390// CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 81391// CHECK1-NEXT:    [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 81392// CHECK1-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 81393// CHECK1-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 81394// CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 41395// CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP8]], 11396// CHECK1-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 41397// CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 21398// CHECK1-NEXT:    [[TMP9:%.*]] = load float, ptr [[ARRAYIDX]], align 41399// CHECK1-NEXT:    [[CONV:%.*]] = fpext float [[TMP9]] to double1400// CHECK1-NEXT:    [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+001401// CHECK1-NEXT:    [[CONV6:%.*]] = fptrunc double [[ADD5]] to float1402// CHECK1-NEXT:    store float [[CONV6]], ptr [[ARRAYIDX]], align 41403// CHECK1-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 31404// CHECK1-NEXT:    [[TMP10:%.*]] = load float, ptr [[ARRAYIDX7]], align 41405// CHECK1-NEXT:    [[CONV8:%.*]] = fpext float [[TMP10]] to double1406// CHECK1-NEXT:    [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+001407// CHECK1-NEXT:    [[CONV10:%.*]] = fptrunc double [[ADD9]] to float1408// CHECK1-NEXT:    store float [[CONV10]], ptr [[ARRAYIDX7]], align 41409// CHECK1-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 11410// CHECK1-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX11]], i64 0, i64 21411// CHECK1-NEXT:    [[TMP11:%.*]] = load double, ptr [[ARRAYIDX12]], align 81412// CHECK1-NEXT:    [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+001413// CHECK1-NEXT:    store double [[ADD13]], ptr [[ARRAYIDX12]], align 81414// CHECK1-NEXT:    [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]]1415// CHECK1-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP12]]1416// CHECK1-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i64 31417// CHECK1-NEXT:    [[TMP13:%.*]] = load double, ptr [[ARRAYIDX15]], align 81418// CHECK1-NEXT:    [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+001419// CHECK1-NEXT:    store double [[ADD16]], ptr [[ARRAYIDX15]], align 81420// CHECK1-NEXT:    [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 01421// CHECK1-NEXT:    [[TMP14:%.*]] = load i64, ptr [[X]], align 81422// CHECK1-NEXT:    [[ADD17:%.*]] = add nsw i64 [[TMP14]], 11423// CHECK1-NEXT:    store i64 [[ADD17]], ptr [[X]], align 81424// CHECK1-NEXT:    [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 11425// CHECK1-NEXT:    [[TMP15:%.*]] = load i8, ptr [[Y]], align 81426// CHECK1-NEXT:    [[CONV18:%.*]] = sext i8 [[TMP15]] to i321427// CHECK1-NEXT:    [[ADD19:%.*]] = add nsw i32 [[CONV18]], 11428// CHECK1-NEXT:    [[CONV20:%.*]] = trunc i32 [[ADD19]] to i81429// CHECK1-NEXT:    store i8 [[CONV20]], ptr [[Y]], align 81430// CHECK1-NEXT:    ret void1431//1432//1433// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1721434// CHECK1-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR2]] {1435// CHECK1-NEXT:  entry:1436// CHECK1-NEXT:    [[NN_ADDR:%.*]] = alloca i64, align 81437// CHECK1-NEXT:    [[NN_CASTED:%.*]] = alloca i64, align 81438// CHECK1-NEXT:    store i64 [[NN]], ptr [[NN_ADDR]], align 81439// CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[NN_ADDR]], align 41440// CHECK1-NEXT:    store i32 [[TMP0]], ptr [[NN_CASTED]], align 41441// CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[NN_CASTED]], align 81442// CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172.omp_outlined, i64 [[TMP1]])1443// CHECK1-NEXT:    ret void1444//1445//1446// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172.omp_outlined1447// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR2]] {1448// CHECK1-NEXT:  entry:1449// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81450// CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81451// CHECK1-NEXT:    [[NN_ADDR:%.*]] = alloca i64, align 81452// CHECK1-NEXT:    [[NN_CASTED:%.*]] = alloca i64, align 81453// CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81454// CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81455// CHECK1-NEXT:    store i64 [[NN]], ptr [[NN_ADDR]], align 81456// CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[NN_ADDR]], align 41457// CHECK1-NEXT:    store i32 [[TMP0]], ptr [[NN_CASTED]], align 41458// CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[NN_CASTED]], align 81459// CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172.omp_outlined.omp_outlined, i64 [[TMP1]])1460// CHECK1-NEXT:    ret void1461//1462//1463// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172.omp_outlined.omp_outlined1464// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR2]] {1465// CHECK1-NEXT:  entry:1466// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81467// CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81468// CHECK1-NEXT:    [[NN_ADDR:%.*]] = alloca i64, align 81469// CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81470// CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81471// CHECK1-NEXT:    store i64 [[NN]], ptr [[NN_ADDR]], align 81472// CHECK1-NEXT:    ret void1473//1474//1475// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1751476// CHECK1-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR2]] {1477// CHECK1-NEXT:  entry:1478// CHECK1-NEXT:    [[NN_ADDR:%.*]] = alloca i64, align 81479// CHECK1-NEXT:    [[NN_CASTED:%.*]] = alloca i64, align 81480// CHECK1-NEXT:    store i64 [[NN]], ptr [[NN_ADDR]], align 81481// CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[NN_ADDR]], align 41482// CHECK1-NEXT:    store i32 [[TMP0]], ptr [[NN_CASTED]], align 41483// CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[NN_CASTED]], align 81484// CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175.omp_outlined, i64 [[TMP1]])1485// CHECK1-NEXT:    ret void1486//1487//1488// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175.omp_outlined1489// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR2]] {1490// CHECK1-NEXT:  entry:1491// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81492// CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81493// CHECK1-NEXT:    [[NN_ADDR:%.*]] = alloca i64, align 81494// CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81495// CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81496// CHECK1-NEXT:    store i64 [[NN]], ptr [[NN_ADDR]], align 81497// CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175.omp_outlined.omp_outlined, ptr [[NN_ADDR]])1498// CHECK1-NEXT:    ret void1499//1500//1501// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175.omp_outlined.omp_outlined1502// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] {1503// CHECK1-NEXT:  entry:1504// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81505// CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81506// CHECK1-NEXT:    [[NN_ADDR:%.*]] = alloca ptr, align 81507// CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81508// CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81509// CHECK1-NEXT:    store ptr [[NN]], ptr [[NN_ADDR]], align 81510// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[NN_ADDR]], align 81511// CHECK1-NEXT:    ret void1512//1513//1514// CHECK1-LABEL: define {{[^@]+}}@_Z6bazzzziPi1515// CHECK1-SAME: (i32 noundef signext [[N:%.*]], ptr noundef [[F:%.*]]) #[[ATTR0]] {1516// CHECK1-NEXT:  entry:1517// CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 41518// CHECK1-NEXT:    [[F_ADDR:%.*]] = alloca ptr, align 81519// CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 81520// CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 81521// CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 81522// CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81523// CHECK1-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 41524// CHECK1-NEXT:    store ptr [[F]], ptr [[F_ADDR]], align 81525// CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 41526// CHECK1-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i641527// CHECK1-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01528// CHECK1-NEXT:    store i64 [[TMP1]], ptr [[TMP2]], align 81529// CHECK1-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01530// CHECK1-NEXT:    store i64 [[TMP1]], ptr [[TMP3]], align 81531// CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 01532// CHECK1-NEXT:    store ptr null, ptr [[TMP4]], align 81533// CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01534// CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01535// CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 01536// CHECK1-NEXT:    store i32 3, ptr [[TMP7]], align 41537// CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11538// CHECK1-NEXT:    store i32 1, ptr [[TMP8]], align 41539// CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 21540// CHECK1-NEXT:    store ptr [[TMP5]], ptr [[TMP9]], align 81541// CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 31542// CHECK1-NEXT:    store ptr [[TMP6]], ptr [[TMP10]], align 81543// CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 41544// CHECK1-NEXT:    store ptr @.offload_sizes.17, ptr [[TMP11]], align 81545// CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 51546// CHECK1-NEXT:    store ptr @.offload_maptypes.18, ptr [[TMP12]], align 81547// CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 61548// CHECK1-NEXT:    store ptr null, ptr [[TMP13]], align 81549// CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 71550// CHECK1-NEXT:    store ptr null, ptr [[TMP14]], align 81551// CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 81552// CHECK1-NEXT:    store i64 0, ptr [[TMP15]], align 81553// CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 91554// CHECK1-NEXT:    store i64 0, ptr [[TMP16]], align 81555// CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 101556// CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP17]], align 41557// CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 111558// CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP18]], align 41559// CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 121560// CHECK1-NEXT:    store i32 0, ptr [[TMP19]], align 41561// CHECK1-NEXT:    [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l200.region_id, ptr [[KERNEL_ARGS]])1562// CHECK1-NEXT:    [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 01563// CHECK1-NEXT:    br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]1564// CHECK1:       omp_offload.failed:1565// CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l200(i64 [[TMP1]]) #[[ATTR3]]1566// CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]1567// CHECK1:       omp_offload.cont:1568// CHECK1-NEXT:    ret void1569//1570//1571// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l2001572// CHECK1-SAME: (i64 noundef [[VLA:%.*]]) #[[ATTR2]] {1573// CHECK1-NEXT:  entry:1574// CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 81575// CHECK1-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 81576// CHECK1-NEXT:    [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 81577// CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l200.omp_outlined, i64 [[TMP0]])1578// CHECK1-NEXT:    ret void1579//1580//1581// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l200.omp_outlined1582// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR2]] {1583// CHECK1-NEXT:  entry:1584// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81585// CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81586// CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 81587// CHECK1-NEXT:    [[F:%.*]] = alloca ptr, align 81588// CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81589// CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81590// CHECK1-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 81591// CHECK1-NEXT:    [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 81592// CHECK1-NEXT:    ret void1593//1594//1595// CHECK1-LABEL: define {{[^@]+}}@_Z3bari1596// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {1597// CHECK1-NEXT:  entry:1598// CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 41599// CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 41600// CHECK1-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 81601// CHECK1-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 41602// CHECK1-NEXT:    store i32 0, ptr [[A]], align 41603// CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 41604// CHECK1-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]])1605// CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A]], align 41606// CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]1607// CHECK1-NEXT:    store i32 [[ADD]], ptr [[A]], align 41608// CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 41609// CHECK1-NEXT:    [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]])1610// CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 41611// CHECK1-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]1612// CHECK1-NEXT:    store i32 [[ADD2]], ptr [[A]], align 41613// CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 41614// CHECK1-NEXT:    [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]])1615// CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A]], align 41616// CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]1617// CHECK1-NEXT:    store i32 [[ADD4]], ptr [[A]], align 41618// CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 41619// CHECK1-NEXT:    [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]])1620// CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[A]], align 41621// CHECK1-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]1622// CHECK1-NEXT:    store i32 [[ADD6]], ptr [[A]], align 41623// CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A]], align 41624// CHECK1-NEXT:    ret i32 [[TMP8]]1625//1626//1627// CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei1628// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {1629// CHECK1-NEXT:  entry:1630// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81631// CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 41632// CHECK1-NEXT:    [[B:%.*]] = alloca i32, align 41633// CHECK1-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 81634// CHECK1-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 81635// CHECK1-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 81636// CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 81637// CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 81638// CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 81639// CHECK1-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 81640// CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81641// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81642// CHECK1-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 41643// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81644// CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 41645// CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 11646// CHECK1-NEXT:    store i32 [[ADD]], ptr [[B]], align 41647// CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 41648// CHECK1-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i641649// CHECK1-NEXT:    [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()1650// CHECK1-NEXT:    store ptr [[TMP3]], ptr [[SAVED_STACK]], align 81651// CHECK1-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]1652// CHECK1-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 21653// CHECK1-NEXT:    store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 81654// CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B]], align 41655// CHECK1-NEXT:    store i32 [[TMP5]], ptr [[B_CASTED]], align 41656// CHECK1-NEXT:    [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 81657// CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 41658// CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 601659// CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]1660// CHECK1:       omp_if.then:1661// CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 01662// CHECK1-NEXT:    [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]]1663// CHECK1-NEXT:    [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 21664// CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.19, i64 40, i1 false)1665// CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01666// CHECK1-NEXT:    store ptr [[THIS1]], ptr [[TMP10]], align 81667// CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01668// CHECK1-NEXT:    store ptr [[A]], ptr [[TMP11]], align 81669// CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 01670// CHECK1-NEXT:    store ptr null, ptr [[TMP12]], align 81671// CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 11672// CHECK1-NEXT:    store i64 [[TMP6]], ptr [[TMP13]], align 81673// CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 11674// CHECK1-NEXT:    store i64 [[TMP6]], ptr [[TMP14]], align 81675// CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 11676// CHECK1-NEXT:    store ptr null, ptr [[TMP15]], align 81677// CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 21678// CHECK1-NEXT:    store i64 2, ptr [[TMP16]], align 81679// CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 21680// CHECK1-NEXT:    store i64 2, ptr [[TMP17]], align 81681// CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 21682// CHECK1-NEXT:    store ptr null, ptr [[TMP18]], align 81683// CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 31684// CHECK1-NEXT:    store i64 [[TMP2]], ptr [[TMP19]], align 81685// CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 31686// CHECK1-NEXT:    store i64 [[TMP2]], ptr [[TMP20]], align 81687// CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 31688// CHECK1-NEXT:    store ptr null, ptr [[TMP21]], align 81689// CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 41690// CHECK1-NEXT:    store ptr [[VLA]], ptr [[TMP22]], align 81691// CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 41692// CHECK1-NEXT:    store ptr [[VLA]], ptr [[TMP23]], align 81693// CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 41694// CHECK1-NEXT:    store i64 [[TMP9]], ptr [[TMP24]], align 81695// CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 41696// CHECK1-NEXT:    store ptr null, ptr [[TMP25]], align 81697// CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01698// CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01699// CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 01700// CHECK1-NEXT:    [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 01701// CHECK1-NEXT:    store i32 3, ptr [[TMP29]], align 41702// CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11703// CHECK1-NEXT:    store i32 5, ptr [[TMP30]], align 41704// CHECK1-NEXT:    [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 21705// CHECK1-NEXT:    store ptr [[TMP26]], ptr [[TMP31]], align 81706// CHECK1-NEXT:    [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 31707// CHECK1-NEXT:    store ptr [[TMP27]], ptr [[TMP32]], align 81708// CHECK1-NEXT:    [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 41709// CHECK1-NEXT:    store ptr [[TMP28]], ptr [[TMP33]], align 81710// CHECK1-NEXT:    [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 51711// CHECK1-NEXT:    store ptr @.offload_maptypes.20, ptr [[TMP34]], align 81712// CHECK1-NEXT:    [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 61713// CHECK1-NEXT:    store ptr null, ptr [[TMP35]], align 81714// CHECK1-NEXT:    [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 71715// CHECK1-NEXT:    store ptr null, ptr [[TMP36]], align 81716// CHECK1-NEXT:    [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 81717// CHECK1-NEXT:    store i64 0, ptr [[TMP37]], align 81718// CHECK1-NEXT:    [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 91719// CHECK1-NEXT:    store i64 0, ptr [[TMP38]], align 81720// CHECK1-NEXT:    [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 101721// CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP39]], align 41722// CHECK1-NEXT:    [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 111723// CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP40]], align 41724// CHECK1-NEXT:    [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 121725// CHECK1-NEXT:    store i32 0, ptr [[TMP41]], align 41726// CHECK1-NEXT:    [[TMP42:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l245.region_id, ptr [[KERNEL_ARGS]])1727// CHECK1-NEXT:    [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 01728// CHECK1-NEXT:    br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]1729// CHECK1:       omp_offload.failed:1730// CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l245(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR3]]1731// CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]1732// CHECK1:       omp_offload.cont:1733// CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]1734// CHECK1:       omp_if.else:1735// CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l245(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR3]]1736// CHECK1-NEXT:    br label [[OMP_IF_END]]1737// CHECK1:       omp_if.end:1738// CHECK1-NEXT:    [[TMP44:%.*]] = mul nsw i64 1, [[TMP2]]1739// CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP44]]1740// CHECK1-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 11741// CHECK1-NEXT:    [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 21742// CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP45]] to i321743// CHECK1-NEXT:    [[TMP46:%.*]] = load i32, ptr [[B]], align 41744// CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]]1745// CHECK1-NEXT:    [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 81746// CHECK1-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP47]])1747// CHECK1-NEXT:    ret i32 [[ADD3]]1748//1749//1750// CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici1751// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {1752// CHECK1-NEXT:  entry:1753// CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 41754// CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 41755// CHECK1-NEXT:    [[AA:%.*]] = alloca i16, align 21756// CHECK1-NEXT:    [[AAA:%.*]] = alloca i8, align 11757// CHECK1-NEXT:    [[B:%.*]] = alloca [10 x i32], align 41758// CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 81759// CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 81760// CHECK1-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 81761// CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 81762// CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 81763// CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 81764// CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81765// CHECK1-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 41766// CHECK1-NEXT:    store i32 0, ptr [[A]], align 41767// CHECK1-NEXT:    store i16 0, ptr [[AA]], align 21768// CHECK1-NEXT:    store i8 0, ptr [[AAA]], align 11769// CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A]], align 41770// CHECK1-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 41771// CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 81772// CHECK1-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA]], align 21773// CHECK1-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 21774// CHECK1-NEXT:    [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 81775// CHECK1-NEXT:    [[TMP4:%.*]] = load i8, ptr [[AAA]], align 11776// CHECK1-NEXT:    store i8 [[TMP4]], ptr [[AAA_CASTED]], align 11777// CHECK1-NEXT:    [[TMP5:%.*]] = load i64, ptr [[AAA_CASTED]], align 81778// CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 41779// CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 501780// CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]1781// CHECK1:       omp_if.then:1782// CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01783// CHECK1-NEXT:    store i64 [[TMP1]], ptr [[TMP7]], align 81784// CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01785// CHECK1-NEXT:    store i64 [[TMP1]], ptr [[TMP8]], align 81786// CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 01787// CHECK1-NEXT:    store ptr null, ptr [[TMP9]], align 81788// CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 11789// CHECK1-NEXT:    store i64 [[TMP3]], ptr [[TMP10]], align 81790// CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 11791// CHECK1-NEXT:    store i64 [[TMP3]], ptr [[TMP11]], align 81792// CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 11793// CHECK1-NEXT:    store ptr null, ptr [[TMP12]], align 81794// CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 21795// CHECK1-NEXT:    store i64 [[TMP5]], ptr [[TMP13]], align 81796// CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 21797// CHECK1-NEXT:    store i64 [[TMP5]], ptr [[TMP14]], align 81798// CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 21799// CHECK1-NEXT:    store ptr null, ptr [[TMP15]], align 81800// CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 31801// CHECK1-NEXT:    store ptr [[B]], ptr [[TMP16]], align 81802// CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 31803// CHECK1-NEXT:    store ptr [[B]], ptr [[TMP17]], align 81804// CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 31805// CHECK1-NEXT:    store ptr null, ptr [[TMP18]], align 81806// CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01807// CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01808// CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 01809// CHECK1-NEXT:    store i32 3, ptr [[TMP21]], align 41810// CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11811// CHECK1-NEXT:    store i32 4, ptr [[TMP22]], align 41812// CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 21813// CHECK1-NEXT:    store ptr [[TMP19]], ptr [[TMP23]], align 81814// CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 31815// CHECK1-NEXT:    store ptr [[TMP20]], ptr [[TMP24]], align 81816// CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 41817// CHECK1-NEXT:    store ptr @.offload_sizes.21, ptr [[TMP25]], align 81818// CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 51819// CHECK1-NEXT:    store ptr @.offload_maptypes.22, ptr [[TMP26]], align 81820// CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 61821// CHECK1-NEXT:    store ptr null, ptr [[TMP27]], align 81822// CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 71823// CHECK1-NEXT:    store ptr null, ptr [[TMP28]], align 81824// CHECK1-NEXT:    [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 81825// CHECK1-NEXT:    store i64 0, ptr [[TMP29]], align 81826// CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 91827// CHECK1-NEXT:    store i64 0, ptr [[TMP30]], align 81828// CHECK1-NEXT:    [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 101829// CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP31]], align 41830// CHECK1-NEXT:    [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 111831// CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP32]], align 41832// CHECK1-NEXT:    [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 121833// CHECK1-NEXT:    store i32 0, ptr [[TMP33]], align 41834// CHECK1-NEXT:    [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l227.region_id, ptr [[KERNEL_ARGS]])1835// CHECK1-NEXT:    [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 01836// CHECK1-NEXT:    br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]1837// CHECK1:       omp_offload.failed:1838// CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l227(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR3]]1839// CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]1840// CHECK1:       omp_offload.cont:1841// CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]1842// CHECK1:       omp_if.else:1843// CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l227(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR3]]1844// CHECK1-NEXT:    br label [[OMP_IF_END]]1845// CHECK1:       omp_if.end:1846// CHECK1-NEXT:    [[TMP36:%.*]] = load i32, ptr [[A]], align 41847// CHECK1-NEXT:    ret i32 [[TMP36]]1848//1849//1850// CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i1851// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {1852// CHECK1-NEXT:  entry:1853// CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 41854// CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 41855// CHECK1-NEXT:    [[AA:%.*]] = alloca i16, align 21856// CHECK1-NEXT:    [[B:%.*]] = alloca [10 x i32], align 41857// CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 81858// CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 81859// CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 81860// CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 81861// CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 81862// CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81863// CHECK1-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 41864// CHECK1-NEXT:    store i32 0, ptr [[A]], align 41865// CHECK1-NEXT:    store i16 0, ptr [[AA]], align 21866// CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A]], align 41867// CHECK1-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 41868// CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 81869// CHECK1-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA]], align 21870// CHECK1-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 21871// CHECK1-NEXT:    [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 81872// CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 41873// CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 401874// CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]1875// CHECK1:       omp_if.then:1876// CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01877// CHECK1-NEXT:    store i64 [[TMP1]], ptr [[TMP5]], align 81878// CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01879// CHECK1-NEXT:    store i64 [[TMP1]], ptr [[TMP6]], align 81880// CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 01881// CHECK1-NEXT:    store ptr null, ptr [[TMP7]], align 81882// CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 11883// CHECK1-NEXT:    store i64 [[TMP3]], ptr [[TMP8]], align 81884// CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 11885// CHECK1-NEXT:    store i64 [[TMP3]], ptr [[TMP9]], align 81886// CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 11887// CHECK1-NEXT:    store ptr null, ptr [[TMP10]], align 81888// CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 21889// CHECK1-NEXT:    store ptr [[B]], ptr [[TMP11]], align 81890// CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 21891// CHECK1-NEXT:    store ptr [[B]], ptr [[TMP12]], align 81892// CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 21893// CHECK1-NEXT:    store ptr null, ptr [[TMP13]], align 81894// CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01895// CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01896// CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 01897// CHECK1-NEXT:    store i32 3, ptr [[TMP16]], align 41898// CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11899// CHECK1-NEXT:    store i32 3, ptr [[TMP17]], align 41900// CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 21901// CHECK1-NEXT:    store ptr [[TMP14]], ptr [[TMP18]], align 81902// CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 31903// CHECK1-NEXT:    store ptr [[TMP15]], ptr [[TMP19]], align 81904// CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 41905// CHECK1-NEXT:    store ptr @.offload_sizes.23, ptr [[TMP20]], align 81906// CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 51907// CHECK1-NEXT:    store ptr @.offload_maptypes.24, ptr [[TMP21]], align 81908// CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 61909// CHECK1-NEXT:    store ptr null, ptr [[TMP22]], align 81910// CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 71911// CHECK1-NEXT:    store ptr null, ptr [[TMP23]], align 81912// CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 81913// CHECK1-NEXT:    store i64 0, ptr [[TMP24]], align 81914// CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 91915// CHECK1-NEXT:    store i64 0, ptr [[TMP25]], align 81916// CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 101917// CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP26]], align 41918// CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 111919// CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP27]], align 41920// CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 121921// CHECK1-NEXT:    store i32 0, ptr [[TMP28]], align 41922// CHECK1-NEXT:    [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l210.region_id, ptr [[KERNEL_ARGS]])1923// CHECK1-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 01924// CHECK1-NEXT:    br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]1925// CHECK1:       omp_offload.failed:1926// CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l210(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]]1927// CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]1928// CHECK1:       omp_offload.cont:1929// CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]1930// CHECK1:       omp_if.else:1931// CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l210(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]]1932// CHECK1-NEXT:    br label [[OMP_IF_END]]1933// CHECK1:       omp_if.end:1934// CHECK1-NEXT:    [[TMP31:%.*]] = load i32, ptr [[A]], align 41935// CHECK1-NEXT:    ret i32 [[TMP31]]1936//1937//1938// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l2451939// CHECK1-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {1940// CHECK1-NEXT:  entry:1941// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81942// CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 81943// CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 81944// CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 81945// CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 81946// CHECK1-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 81947// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81948// CHECK1-NEXT:    store i64 [[B]], ptr [[B_ADDR]], align 81949// CHECK1-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 81950// CHECK1-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 81951// CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 81952// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81953// CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 81954// CHECK1-NEXT:    [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 81955// CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 81956// CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 41957// CHECK1-NEXT:    store i32 [[TMP4]], ptr [[B_CASTED]], align 41958// CHECK1-NEXT:    [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 81959// CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l245.omp_outlined, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]])1960// CHECK1-NEXT:    ret void1961//1962//1963// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l245.omp_outlined1964// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {1965// CHECK1-NEXT:  entry:1966// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81967// CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81968// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81969// CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 81970// CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 81971// CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 81972// CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 81973// CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81974// CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81975// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81976// CHECK1-NEXT:    store i64 [[B]], ptr [[B_ADDR]], align 81977// CHECK1-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 81978// CHECK1-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 81979// CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 81980// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81981// CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 81982// CHECK1-NEXT:    [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 81983// CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 81984// CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 41985// CHECK1-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP4]] to double1986// CHECK1-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+001987// CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 01988// CHECK1-NEXT:    store double [[ADD]], ptr [[A]], align 81989// CHECK1-NEXT:    [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 01990// CHECK1-NEXT:    [[TMP5:%.*]] = load double, ptr [[A3]], align 81991// CHECK1-NEXT:    [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+001992// CHECK1-NEXT:    store double [[INC]], ptr [[A3]], align 81993// CHECK1-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i161994// CHECK1-NEXT:    [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]]1995// CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP6]]1996// CHECK1-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 11997// CHECK1-NEXT:    store i16 [[CONV4]], ptr [[ARRAYIDX5]], align 21998// CHECK1-NEXT:    ret void1999//2000//2001// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l2272002// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {2003// CHECK1-NEXT:  entry:2004// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 82005// CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 82006// CHECK1-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 82007// CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 82008// CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 82009// CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 82010// CHECK1-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 82011// CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 82012// CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 82013// CHECK1-NEXT:    store i64 [[AAA]], ptr [[AAA_ADDR]], align 82014// CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 82015// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 82016// CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 42017// CHECK1-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 42018// CHECK1-NEXT:    [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 82019// CHECK1-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 22020// CHECK1-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 22021// CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 82022// CHECK1-NEXT:    [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 12023// CHECK1-NEXT:    store i8 [[TMP5]], ptr [[AAA_CASTED]], align 12024// CHECK1-NEXT:    [[TMP6:%.*]] = load i64, ptr [[AAA_CASTED]], align 82025// CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l227.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], ptr [[TMP0]])2026// CHECK1-NEXT:    ret void2027//2028//2029// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l227.omp_outlined2030// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {2031// CHECK1-NEXT:  entry:2032// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 82033// CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 82034// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 82035// CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 82036// CHECK1-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 82037// CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 82038// CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 82039// CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 82040// CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 82041// CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 82042// CHECK1-NEXT:    store i64 [[AAA]], ptr [[AAA_ADDR]], align 82043// CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 82044// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 82045// CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 42046// CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 12047// CHECK1-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 42048// CHECK1-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 22049// CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i322050// CHECK1-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 12051// CHECK1-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i162052// CHECK1-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 22053// CHECK1-NEXT:    [[TMP3:%.*]] = load i8, ptr [[AAA_ADDR]], align 12054// CHECK1-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP3]] to i322055// CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 12056// CHECK1-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i82057// CHECK1-NEXT:    store i8 [[CONV5]], ptr [[AAA_ADDR]], align 12058// CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 22059// CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX]], align 42060// CHECK1-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP4]], 12061// CHECK1-NEXT:    store i32 [[ADD6]], ptr [[ARRAYIDX]], align 42062// CHECK1-NEXT:    ret void2063//2064//2065// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l2102066// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {2067// CHECK1-NEXT:  entry:2068// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 82069// CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 82070// CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 82071// CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 82072// CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 82073// CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 82074// CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 82075// CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 82076// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 82077// CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 42078// CHECK1-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 42079// CHECK1-NEXT:    [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 82080// CHECK1-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 22081// CHECK1-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 22082// CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 82083// CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l210.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]])2084// CHECK1-NEXT:    ret void2085//2086//2087// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l210.omp_outlined2088// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {2089// CHECK1-NEXT:  entry:2090// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 82091// CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 82092// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 82093// CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 82094// CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 82095// CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 82096// CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 82097// CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 82098// CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 82099// CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 82100// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 82101// CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 42102// CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 12103// CHECK1-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 42104// CHECK1-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 22105// CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i322106// CHECK1-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 12107// CHECK1-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i162108// CHECK1-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 22109// CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 22110// CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 42111// CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 12112// CHECK1-NEXT:    store i32 [[ADD3]], ptr [[ARRAYIDX]], align 42113// CHECK1-NEXT:    ret void2114//2115//2116// CHECK3-LABEL: define {{[^@]+}}@_Z3fooi2117// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] {2118// CHECK3-NEXT:  entry:2119// CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 42120// CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 42121// CHECK3-NEXT:    [[AA:%.*]] = alloca i16, align 22122// CHECK3-NEXT:    [[B:%.*]] = alloca [10 x float], align 42123// CHECK3-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 42124// CHECK3-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 42125// CHECK3-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 82126// CHECK3-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 42127// CHECK3-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 42128// CHECK3-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 42129// CHECK3-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 42130// CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 42131// CHECK3-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 42132// CHECK3-NEXT:    [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 42133// CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 42134// CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 42135// CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 42136// CHECK3-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 42137// CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 42138// CHECK3-NEXT:    [[AA_CASTED4:%.*]] = alloca i32, align 42139// CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [1 x ptr], align 42140// CHECK3-NEXT:    [[DOTOFFLOAD_PTRS6:%.*]] = alloca [1 x ptr], align 42141// CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [1 x ptr], align 42142// CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 82143// CHECK3-NEXT:    [[A_CASTED8:%.*]] = alloca i32, align 42144// CHECK3-NEXT:    [[AA_CASTED9:%.*]] = alloca i32, align 42145// CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x ptr], align 42146// CHECK3-NEXT:    [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x ptr], align 42147// CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x ptr], align 42148// CHECK3-NEXT:    [[KERNEL_ARGS13:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 82149// CHECK3-NEXT:    [[A_CASTED16:%.*]] = alloca i32, align 42150// CHECK3-NEXT:    [[AA_CASTED17:%.*]] = alloca i32, align 42151// CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS18:%.*]] = alloca [2 x ptr], align 42152// CHECK3-NEXT:    [[DOTOFFLOAD_PTRS19:%.*]] = alloca [2 x ptr], align 42153// CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS20:%.*]] = alloca [2 x ptr], align 42154// CHECK3-NEXT:    [[KERNEL_ARGS21:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 82155// CHECK3-NEXT:    [[A_CASTED24:%.*]] = alloca i32, align 42156// CHECK3-NEXT:    [[AA_CASTED25:%.*]] = alloca i32, align 42157// CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS26:%.*]] = alloca [2 x ptr], align 42158// CHECK3-NEXT:    [[DOTOFFLOAD_PTRS27:%.*]] = alloca [2 x ptr], align 42159// CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS28:%.*]] = alloca [2 x ptr], align 42160// CHECK3-NEXT:    [[KERNEL_ARGS29:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 82161// CHECK3-NEXT:    [[A_CASTED32:%.*]] = alloca i32, align 42162// CHECK3-NEXT:    [[AA_CASTED33:%.*]] = alloca i32, align 42163// CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS34:%.*]] = alloca [2 x ptr], align 42164// CHECK3-NEXT:    [[DOTOFFLOAD_PTRS35:%.*]] = alloca [2 x ptr], align 42165// CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS36:%.*]] = alloca [2 x ptr], align 42166// CHECK3-NEXT:    [[KERNEL_ARGS37:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 82167// CHECK3-NEXT:    [[A_CASTED40:%.*]] = alloca i32, align 42168// CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS43:%.*]] = alloca [9 x ptr], align 42169// CHECK3-NEXT:    [[DOTOFFLOAD_PTRS44:%.*]] = alloca [9 x ptr], align 42170// CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS45:%.*]] = alloca [9 x ptr], align 42171// CHECK3-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 42172// CHECK3-NEXT:    [[KERNEL_ARGS46:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 82173// CHECK3-NEXT:    [[NN:%.*]] = alloca i32, align 42174// CHECK3-NEXT:    [[NN_CASTED:%.*]] = alloca i32, align 42175// CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS51:%.*]] = alloca [1 x ptr], align 42176// CHECK3-NEXT:    [[DOTOFFLOAD_PTRS52:%.*]] = alloca [1 x ptr], align 42177// CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS53:%.*]] = alloca [1 x ptr], align 42178// CHECK3-NEXT:    [[KERNEL_ARGS54:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 82179// CHECK3-NEXT:    [[NN_CASTED57:%.*]] = alloca i32, align 42180// CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS58:%.*]] = alloca [1 x ptr], align 42181// CHECK3-NEXT:    [[DOTOFFLOAD_PTRS59:%.*]] = alloca [1 x ptr], align 42182// CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS60:%.*]] = alloca [1 x ptr], align 42183// CHECK3-NEXT:    [[KERNEL_ARGS61:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 82184// CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])2185// CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 42186// CHECK3-NEXT:    store i32 0, ptr [[A]], align 42187// CHECK3-NEXT:    store i16 0, ptr [[AA]], align 22188// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 42189// CHECK3-NEXT:    [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()2190// CHECK3-NEXT:    store ptr [[TMP2]], ptr [[SAVED_STACK]], align 42191// CHECK3-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 42192// CHECK3-NEXT:    store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 42193// CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 42194// CHECK3-NEXT:    [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]2195// CHECK3-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 82196// CHECK3-NEXT:    store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 42197// CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A]], align 42198// CHECK3-NEXT:    store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 42199// CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[A]], align 42200// CHECK3-NEXT:    store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_2]], align 42201// CHECK3-NEXT:    [[TMP7:%.*]] = load i16, ptr [[AA]], align 22202// CHECK3-NEXT:    store i16 [[TMP7]], ptr [[AA_CASTED]], align 22203// CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[AA_CASTED]], align 42204// CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 42205// CHECK3-NEXT:    store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 42206// CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 42207// CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 42208// CHECK3-NEXT:    store i32 [[TMP11]], ptr [[DOTCAPTURE_EXPR__CASTED3]], align 42209// CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED3]], align 42210// CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 02211// CHECK3-NEXT:    store i32 [[TMP8]], ptr [[TMP13]], align 42212// CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 02213// CHECK3-NEXT:    store i32 [[TMP8]], ptr [[TMP14]], align 42214// CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 02215// CHECK3-NEXT:    store ptr null, ptr [[TMP15]], align 42216// CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 12217// CHECK3-NEXT:    store i32 [[TMP10]], ptr [[TMP16]], align 42218// CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 12219// CHECK3-NEXT:    store i32 [[TMP10]], ptr [[TMP17]], align 42220// CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 12221// CHECK3-NEXT:    store ptr null, ptr [[TMP18]], align 42222// CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 22223// CHECK3-NEXT:    store i32 [[TMP12]], ptr [[TMP19]], align 42224// CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 22225// CHECK3-NEXT:    store i32 [[TMP12]], ptr [[TMP20]], align 42226// CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 22227// CHECK3-NEXT:    store ptr null, ptr [[TMP21]], align 42228// CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 02229// CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 02230// CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 02231// CHECK3-NEXT:    [[TMP25:%.*]] = load i16, ptr [[AA]], align 22232// CHECK3-NEXT:    store i16 [[TMP25]], ptr [[TMP24]], align 42233// CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 12234// CHECK3-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 42235// CHECK3-NEXT:    store i32 [[TMP27]], ptr [[TMP26]], align 42236// CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 22237// CHECK3-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 42238// CHECK3-NEXT:    store i32 [[TMP29]], ptr [[TMP28]], align 42239// CHECK3-NEXT:    [[TMP30:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 72, i32 12, ptr @.omp_task_entry., i64 -1)2240// CHECK3-NEXT:    [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP30]], i32 0, i32 02241// CHECK3-NEXT:    [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP31]], i32 0, i32 02242// CHECK3-NEXT:    [[TMP33:%.*]] = load ptr, ptr [[TMP32]], align 42243// CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP33]], ptr align 4 [[AGG_CAPTURED]], i32 12, i1 false)2244// CHECK3-NEXT:    [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP30]], i32 0, i32 12245// CHECK3-NEXT:    [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP34]], i32 0, i32 02246// CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP35]], ptr align 4 @.offload_sizes, i32 24, i1 false)2247// CHECK3-NEXT:    [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP34]], i32 0, i32 12248// CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP36]], ptr align 4 [[TMP22]], i32 12, i1 false)2249// CHECK3-NEXT:    [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP34]], i32 0, i32 22250// CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP37]], ptr align 4 [[TMP23]], i32 12, i1 false)2251// CHECK3-NEXT:    [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP34]], i32 0, i32 32252// CHECK3-NEXT:    [[TMP39:%.*]] = load i16, ptr [[AA]], align 22253// CHECK3-NEXT:    store i16 [[TMP39]], ptr [[TMP38]], align 42254// CHECK3-NEXT:    [[TMP40:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP30]])2255// CHECK3-NEXT:    [[TMP41:%.*]] = load i32, ptr [[A]], align 42256// CHECK3-NEXT:    store i32 [[TMP41]], ptr [[A_CASTED]], align 42257// CHECK3-NEXT:    [[TMP42:%.*]] = load i32, ptr [[A_CASTED]], align 42258// CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105(i32 [[TMP42]]) #[[ATTR3:[0-9]+]]2259// CHECK3-NEXT:    [[TMP43:%.*]] = load i16, ptr [[AA]], align 22260// CHECK3-NEXT:    store i16 [[TMP43]], ptr [[AA_CASTED4]], align 22261// CHECK3-NEXT:    [[TMP44:%.*]] = load i32, ptr [[AA_CASTED4]], align 42262// CHECK3-NEXT:    [[TMP45:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 02263// CHECK3-NEXT:    store i32 [[TMP44]], ptr [[TMP45]], align 42264// CHECK3-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 02265// CHECK3-NEXT:    store i32 [[TMP44]], ptr [[TMP46]], align 42266// CHECK3-NEXT:    [[TMP47:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 02267// CHECK3-NEXT:    store ptr null, ptr [[TMP47]], align 42268// CHECK3-NEXT:    [[TMP48:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 02269// CHECK3-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 02270// CHECK3-NEXT:    [[TMP50:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 02271// CHECK3-NEXT:    store i32 3, ptr [[TMP50]], align 42272// CHECK3-NEXT:    [[TMP51:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12273// CHECK3-NEXT:    store i32 1, ptr [[TMP51]], align 42274// CHECK3-NEXT:    [[TMP52:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 22275// CHECK3-NEXT:    store ptr [[TMP48]], ptr [[TMP52]], align 42276// CHECK3-NEXT:    [[TMP53:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 32277// CHECK3-NEXT:    store ptr [[TMP49]], ptr [[TMP53]], align 42278// CHECK3-NEXT:    [[TMP54:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 42279// CHECK3-NEXT:    store ptr @.offload_sizes.1, ptr [[TMP54]], align 42280// CHECK3-NEXT:    [[TMP55:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 52281// CHECK3-NEXT:    store ptr @.offload_maptypes.2, ptr [[TMP55]], align 42282// CHECK3-NEXT:    [[TMP56:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 62283// CHECK3-NEXT:    store ptr null, ptr [[TMP56]], align 42284// CHECK3-NEXT:    [[TMP57:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 72285// CHECK3-NEXT:    store ptr null, ptr [[TMP57]], align 42286// CHECK3-NEXT:    [[TMP58:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 82287// CHECK3-NEXT:    store i64 0, ptr [[TMP58]], align 82288// CHECK3-NEXT:    [[TMP59:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 92289// CHECK3-NEXT:    store i64 0, ptr [[TMP59]], align 82290// CHECK3-NEXT:    [[TMP60:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 102291// CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP60]], align 42292// CHECK3-NEXT:    [[TMP61:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 112293// CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP61]], align 42294// CHECK3-NEXT:    [[TMP62:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 122295// CHECK3-NEXT:    store i32 0, ptr [[TMP62]], align 42296// CHECK3-NEXT:    [[TMP63:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, ptr [[KERNEL_ARGS]])2297// CHECK3-NEXT:    [[TMP64:%.*]] = icmp ne i32 [[TMP63]], 02298// CHECK3-NEXT:    br i1 [[TMP64]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]2299// CHECK3:       omp_offload.failed:2300// CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i32 [[TMP44]]) #[[ATTR3]]2301// CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]2302// CHECK3:       omp_offload.cont:2303// CHECK3-NEXT:    [[TMP65:%.*]] = load i32, ptr [[A]], align 42304// CHECK3-NEXT:    store i32 [[TMP65]], ptr [[A_CASTED8]], align 42305// CHECK3-NEXT:    [[TMP66:%.*]] = load i32, ptr [[A_CASTED8]], align 42306// CHECK3-NEXT:    [[TMP67:%.*]] = load i16, ptr [[AA]], align 22307// CHECK3-NEXT:    store i16 [[TMP67]], ptr [[AA_CASTED9]], align 22308// CHECK3-NEXT:    [[TMP68:%.*]] = load i32, ptr [[AA_CASTED9]], align 42309// CHECK3-NEXT:    [[TMP69:%.*]] = load i32, ptr [[N_ADDR]], align 42310// CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP69]], 102311// CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]2312// CHECK3:       omp_if.then:2313// CHECK3-NEXT:    [[TMP70:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 02314// CHECK3-NEXT:    store i32 [[TMP66]], ptr [[TMP70]], align 42315// CHECK3-NEXT:    [[TMP71:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 02316// CHECK3-NEXT:    store i32 [[TMP66]], ptr [[TMP71]], align 42317// CHECK3-NEXT:    [[TMP72:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i32 0, i32 02318// CHECK3-NEXT:    store ptr null, ptr [[TMP72]], align 42319// CHECK3-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 12320// CHECK3-NEXT:    store i32 [[TMP68]], ptr [[TMP73]], align 42321// CHECK3-NEXT:    [[TMP74:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 12322// CHECK3-NEXT:    store i32 [[TMP68]], ptr [[TMP74]], align 42323// CHECK3-NEXT:    [[TMP75:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i32 0, i32 12324// CHECK3-NEXT:    store ptr null, ptr [[TMP75]], align 42325// CHECK3-NEXT:    [[TMP76:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 02326// CHECK3-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 02327// CHECK3-NEXT:    [[TMP78:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 02328// CHECK3-NEXT:    store i32 3, ptr [[TMP78]], align 42329// CHECK3-NEXT:    [[TMP79:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 12330// CHECK3-NEXT:    store i32 2, ptr [[TMP79]], align 42331// CHECK3-NEXT:    [[TMP80:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 22332// CHECK3-NEXT:    store ptr [[TMP76]], ptr [[TMP80]], align 42333// CHECK3-NEXT:    [[TMP81:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 32334// CHECK3-NEXT:    store ptr [[TMP77]], ptr [[TMP81]], align 42335// CHECK3-NEXT:    [[TMP82:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 42336// CHECK3-NEXT:    store ptr @.offload_sizes.3, ptr [[TMP82]], align 42337// CHECK3-NEXT:    [[TMP83:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 52338// CHECK3-NEXT:    store ptr @.offload_maptypes.4, ptr [[TMP83]], align 42339// CHECK3-NEXT:    [[TMP84:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 62340// CHECK3-NEXT:    store ptr null, ptr [[TMP84]], align 42341// CHECK3-NEXT:    [[TMP85:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 72342// CHECK3-NEXT:    store ptr null, ptr [[TMP85]], align 42343// CHECK3-NEXT:    [[TMP86:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 82344// CHECK3-NEXT:    store i64 0, ptr [[TMP86]], align 82345// CHECK3-NEXT:    [[TMP87:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 92346// CHECK3-NEXT:    store i64 0, ptr [[TMP87]], align 82347// CHECK3-NEXT:    [[TMP88:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 102348// CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP88]], align 42349// CHECK3-NEXT:    [[TMP89:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 112350// CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP89]], align 42351// CHECK3-NEXT:    [[TMP90:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 122352// CHECK3-NEXT:    store i32 0, ptr [[TMP90]], align 42353// CHECK3-NEXT:    [[TMP91:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, ptr [[KERNEL_ARGS13]])2354// CHECK3-NEXT:    [[TMP92:%.*]] = icmp ne i32 [[TMP91]], 02355// CHECK3-NEXT:    br i1 [[TMP92]], label [[OMP_OFFLOAD_FAILED14:%.*]], label [[OMP_OFFLOAD_CONT15:%.*]]2356// CHECK3:       omp_offload.failed14:2357// CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP66]], i32 [[TMP68]]) #[[ATTR3]]2358// CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT15]]2359// CHECK3:       omp_offload.cont15:2360// CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]2361// CHECK3:       omp_if.else:2362// CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP66]], i32 [[TMP68]]) #[[ATTR3]]2363// CHECK3-NEXT:    br label [[OMP_IF_END]]2364// CHECK3:       omp_if.end:2365// CHECK3-NEXT:    [[TMP93:%.*]] = load i32, ptr [[A]], align 42366// CHECK3-NEXT:    store i32 [[TMP93]], ptr [[A_CASTED16]], align 42367// CHECK3-NEXT:    [[TMP94:%.*]] = load i32, ptr [[A_CASTED16]], align 42368// CHECK3-NEXT:    [[TMP95:%.*]] = load i16, ptr [[AA]], align 22369// CHECK3-NEXT:    store i16 [[TMP95]], ptr [[AA_CASTED17]], align 22370// CHECK3-NEXT:    [[TMP96:%.*]] = load i32, ptr [[AA_CASTED17]], align 42371// CHECK3-NEXT:    [[TMP97:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 02372// CHECK3-NEXT:    store i32 [[TMP94]], ptr [[TMP97]], align 42373// CHECK3-NEXT:    [[TMP98:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS19]], i32 0, i32 02374// CHECK3-NEXT:    store i32 [[TMP94]], ptr [[TMP98]], align 42375// CHECK3-NEXT:    [[TMP99:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 02376// CHECK3-NEXT:    store ptr null, ptr [[TMP99]], align 42377// CHECK3-NEXT:    [[TMP100:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 12378// CHECK3-NEXT:    store i32 [[TMP96]], ptr [[TMP100]], align 42379// CHECK3-NEXT:    [[TMP101:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS19]], i32 0, i32 12380// CHECK3-NEXT:    store i32 [[TMP96]], ptr [[TMP101]], align 42381// CHECK3-NEXT:    [[TMP102:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 12382// CHECK3-NEXT:    store ptr null, ptr [[TMP102]], align 42383// CHECK3-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 02384// CHECK3-NEXT:    [[TMP104:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS19]], i32 0, i32 02385// CHECK3-NEXT:    [[TMP105:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 02386// CHECK3-NEXT:    store i32 3, ptr [[TMP105]], align 42387// CHECK3-NEXT:    [[TMP106:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 12388// CHECK3-NEXT:    store i32 2, ptr [[TMP106]], align 42389// CHECK3-NEXT:    [[TMP107:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 22390// CHECK3-NEXT:    store ptr [[TMP103]], ptr [[TMP107]], align 42391// CHECK3-NEXT:    [[TMP108:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 32392// CHECK3-NEXT:    store ptr [[TMP104]], ptr [[TMP108]], align 42393// CHECK3-NEXT:    [[TMP109:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 42394// CHECK3-NEXT:    store ptr @.offload_sizes.5, ptr [[TMP109]], align 42395// CHECK3-NEXT:    [[TMP110:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 52396// CHECK3-NEXT:    store ptr @.offload_maptypes.6, ptr [[TMP110]], align 42397// CHECK3-NEXT:    [[TMP111:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 62398// CHECK3-NEXT:    store ptr null, ptr [[TMP111]], align 42399// CHECK3-NEXT:    [[TMP112:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 72400// CHECK3-NEXT:    store ptr null, ptr [[TMP112]], align 42401// CHECK3-NEXT:    [[TMP113:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 82402// CHECK3-NEXT:    store i64 0, ptr [[TMP113]], align 82403// CHECK3-NEXT:    [[TMP114:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 92404// CHECK3-NEXT:    store i64 0, ptr [[TMP114]], align 82405// CHECK3-NEXT:    [[TMP115:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 102406// CHECK3-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP115]], align 42407// CHECK3-NEXT:    [[TMP116:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 112408// CHECK3-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP116]], align 42409// CHECK3-NEXT:    [[TMP117:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 122410// CHECK3-NEXT:    store i32 0, ptr [[TMP117]], align 42411// CHECK3-NEXT:    [[TMP118:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 1, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124.region_id, ptr [[KERNEL_ARGS21]])2412// CHECK3-NEXT:    [[TMP119:%.*]] = icmp ne i32 [[TMP118]], 02413// CHECK3-NEXT:    br i1 [[TMP119]], label [[OMP_OFFLOAD_FAILED22:%.*]], label [[OMP_OFFLOAD_CONT23:%.*]]2414// CHECK3:       omp_offload.failed22:2415// CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124(i32 [[TMP94]], i32 [[TMP96]]) #[[ATTR3]]2416// CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT23]]2417// CHECK3:       omp_offload.cont23:2418// CHECK3-NEXT:    [[TMP120:%.*]] = load i32, ptr [[A]], align 42419// CHECK3-NEXT:    store i32 [[TMP120]], ptr [[A_CASTED24]], align 42420// CHECK3-NEXT:    [[TMP121:%.*]] = load i32, ptr [[A_CASTED24]], align 42421// CHECK3-NEXT:    [[TMP122:%.*]] = load i16, ptr [[AA]], align 22422// CHECK3-NEXT:    store i16 [[TMP122]], ptr [[AA_CASTED25]], align 22423// CHECK3-NEXT:    [[TMP123:%.*]] = load i32, ptr [[AA_CASTED25]], align 42424// CHECK3-NEXT:    [[TMP124:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 02425// CHECK3-NEXT:    store i32 [[TMP121]], ptr [[TMP124]], align 42426// CHECK3-NEXT:    [[TMP125:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS27]], i32 0, i32 02427// CHECK3-NEXT:    store i32 [[TMP121]], ptr [[TMP125]], align 42428// CHECK3-NEXT:    [[TMP126:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS28]], i32 0, i32 02429// CHECK3-NEXT:    store ptr null, ptr [[TMP126]], align 42430// CHECK3-NEXT:    [[TMP127:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 12431// CHECK3-NEXT:    store i32 [[TMP123]], ptr [[TMP127]], align 42432// CHECK3-NEXT:    [[TMP128:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS27]], i32 0, i32 12433// CHECK3-NEXT:    store i32 [[TMP123]], ptr [[TMP128]], align 42434// CHECK3-NEXT:    [[TMP129:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS28]], i32 0, i32 12435// CHECK3-NEXT:    store ptr null, ptr [[TMP129]], align 42436// CHECK3-NEXT:    [[TMP130:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 02437// CHECK3-NEXT:    [[TMP131:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS27]], i32 0, i32 02438// CHECK3-NEXT:    [[TMP132:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 02439// CHECK3-NEXT:    store i32 3, ptr [[TMP132]], align 42440// CHECK3-NEXT:    [[TMP133:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 12441// CHECK3-NEXT:    store i32 2, ptr [[TMP133]], align 42442// CHECK3-NEXT:    [[TMP134:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 22443// CHECK3-NEXT:    store ptr [[TMP130]], ptr [[TMP134]], align 42444// CHECK3-NEXT:    [[TMP135:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 32445// CHECK3-NEXT:    store ptr [[TMP131]], ptr [[TMP135]], align 42446// CHECK3-NEXT:    [[TMP136:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 42447// CHECK3-NEXT:    store ptr @.offload_sizes.7, ptr [[TMP136]], align 42448// CHECK3-NEXT:    [[TMP137:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 52449// CHECK3-NEXT:    store ptr @.offload_maptypes.8, ptr [[TMP137]], align 42450// CHECK3-NEXT:    [[TMP138:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 62451// CHECK3-NEXT:    store ptr null, ptr [[TMP138]], align 42452// CHECK3-NEXT:    [[TMP139:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 72453// CHECK3-NEXT:    store ptr null, ptr [[TMP139]], align 42454// CHECK3-NEXT:    [[TMP140:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 82455// CHECK3-NEXT:    store i64 0, ptr [[TMP140]], align 82456// CHECK3-NEXT:    [[TMP141:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 92457// CHECK3-NEXT:    store i64 0, ptr [[TMP141]], align 82458// CHECK3-NEXT:    [[TMP142:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 102459// CHECK3-NEXT:    store [3 x i32] [i32 1, i32 2, i32 0], ptr [[TMP142]], align 42460// CHECK3-NEXT:    [[TMP143:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 112461// CHECK3-NEXT:    store [3 x i32] [i32 1, i32 2, i32 0], ptr [[TMP143]], align 42462// CHECK3-NEXT:    [[TMP144:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS29]], i32 0, i32 122463// CHECK3-NEXT:    store i32 0, ptr [[TMP144]], align 42464// CHECK3-NEXT:    [[TMP145:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 1, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l130.region_id, ptr [[KERNEL_ARGS29]])2465// CHECK3-NEXT:    [[TMP146:%.*]] = icmp ne i32 [[TMP145]], 02466// CHECK3-NEXT:    br i1 [[TMP146]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]]2467// CHECK3:       omp_offload.failed30:2468// CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l130(i32 [[TMP121]], i32 [[TMP123]]) #[[ATTR3]]2469// CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT31]]2470// CHECK3:       omp_offload.cont31:2471// CHECK3-NEXT:    [[TMP147:%.*]] = load i32, ptr [[A]], align 42472// CHECK3-NEXT:    store i32 [[TMP147]], ptr [[A_CASTED32]], align 42473// CHECK3-NEXT:    [[TMP148:%.*]] = load i32, ptr [[A_CASTED32]], align 42474// CHECK3-NEXT:    [[TMP149:%.*]] = load i16, ptr [[AA]], align 22475// CHECK3-NEXT:    store i16 [[TMP149]], ptr [[AA_CASTED33]], align 22476// CHECK3-NEXT:    [[TMP150:%.*]] = load i32, ptr [[AA_CASTED33]], align 42477// CHECK3-NEXT:    [[TMP151:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 02478// CHECK3-NEXT:    store i32 [[TMP148]], ptr [[TMP151]], align 42479// CHECK3-NEXT:    [[TMP152:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS35]], i32 0, i32 02480// CHECK3-NEXT:    store i32 [[TMP148]], ptr [[TMP152]], align 42481// CHECK3-NEXT:    [[TMP153:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS36]], i32 0, i32 02482// CHECK3-NEXT:    store ptr null, ptr [[TMP153]], align 42483// CHECK3-NEXT:    [[TMP154:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 12484// CHECK3-NEXT:    store i32 [[TMP150]], ptr [[TMP154]], align 42485// CHECK3-NEXT:    [[TMP155:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS35]], i32 0, i32 12486// CHECK3-NEXT:    store i32 [[TMP150]], ptr [[TMP155]], align 42487// CHECK3-NEXT:    [[TMP156:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS36]], i32 0, i32 12488// CHECK3-NEXT:    store ptr null, ptr [[TMP156]], align 42489// CHECK3-NEXT:    [[TMP157:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS34]], i32 0, i32 02490// CHECK3-NEXT:    [[TMP158:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS35]], i32 0, i32 02491// CHECK3-NEXT:    [[TMP159:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 02492// CHECK3-NEXT:    store i32 3, ptr [[TMP159]], align 42493// CHECK3-NEXT:    [[TMP160:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 12494// CHECK3-NEXT:    store i32 2, ptr [[TMP160]], align 42495// CHECK3-NEXT:    [[TMP161:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 22496// CHECK3-NEXT:    store ptr [[TMP157]], ptr [[TMP161]], align 42497// CHECK3-NEXT:    [[TMP162:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 32498// CHECK3-NEXT:    store ptr [[TMP158]], ptr [[TMP162]], align 42499// CHECK3-NEXT:    [[TMP163:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 42500// CHECK3-NEXT:    store ptr @.offload_sizes.9, ptr [[TMP163]], align 42501// CHECK3-NEXT:    [[TMP164:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 52502// CHECK3-NEXT:    store ptr @.offload_maptypes.10, ptr [[TMP164]], align 42503// CHECK3-NEXT:    [[TMP165:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 62504// CHECK3-NEXT:    store ptr null, ptr [[TMP165]], align 42505// CHECK3-NEXT:    [[TMP166:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 72506// CHECK3-NEXT:    store ptr null, ptr [[TMP166]], align 42507// CHECK3-NEXT:    [[TMP167:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 82508// CHECK3-NEXT:    store i64 0, ptr [[TMP167]], align 82509// CHECK3-NEXT:    [[TMP168:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 92510// CHECK3-NEXT:    store i64 0, ptr [[TMP168]], align 82511// CHECK3-NEXT:    [[TMP169:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 102512// CHECK3-NEXT:    store [3 x i32] [i32 1, i32 2, i32 3], ptr [[TMP169]], align 42513// CHECK3-NEXT:    [[TMP170:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 112514// CHECK3-NEXT:    store [3 x i32] [i32 1, i32 2, i32 3], ptr [[TMP170]], align 42515// CHECK3-NEXT:    [[TMP171:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS37]], i32 0, i32 122516// CHECK3-NEXT:    store i32 0, ptr [[TMP171]], align 42517// CHECK3-NEXT:    [[TMP172:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 1, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.region_id, ptr [[KERNEL_ARGS37]])2518// CHECK3-NEXT:    [[TMP173:%.*]] = icmp ne i32 [[TMP172]], 02519// CHECK3-NEXT:    br i1 [[TMP173]], label [[OMP_OFFLOAD_FAILED38:%.*]], label [[OMP_OFFLOAD_CONT39:%.*]]2520// CHECK3:       omp_offload.failed38:2521// CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136(i32 [[TMP148]], i32 [[TMP150]]) #[[ATTR3]]2522// CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT39]]2523// CHECK3:       omp_offload.cont39:2524// CHECK3-NEXT:    [[TMP174:%.*]] = load i32, ptr [[A]], align 42525// CHECK3-NEXT:    store i32 [[TMP174]], ptr [[A_CASTED40]], align 42526// CHECK3-NEXT:    [[TMP175:%.*]] = load i32, ptr [[A_CASTED40]], align 42527// CHECK3-NEXT:    [[TMP176:%.*]] = load i32, ptr [[N_ADDR]], align 42528// CHECK3-NEXT:    [[CMP41:%.*]] = icmp sgt i32 [[TMP176]], 202529// CHECK3-NEXT:    br i1 [[CMP41]], label [[OMP_IF_THEN42:%.*]], label [[OMP_IF_ELSE49:%.*]]2530// CHECK3:       omp_if.then42:2531// CHECK3-NEXT:    [[TMP177:%.*]] = mul nuw i32 [[TMP1]], 42532// CHECK3-NEXT:    [[TMP178:%.*]] = sext i32 [[TMP177]] to i642533// CHECK3-NEXT:    [[TMP179:%.*]] = mul nuw i32 5, [[TMP3]]2534// CHECK3-NEXT:    [[TMP180:%.*]] = mul nuw i32 [[TMP179]], 82535// CHECK3-NEXT:    [[TMP181:%.*]] = sext i32 [[TMP180]] to i642536// CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.11, i32 72, i1 false)2537// CHECK3-NEXT:    [[TMP182:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS43]], i32 0, i32 02538// CHECK3-NEXT:    store i32 [[TMP175]], ptr [[TMP182]], align 42539// CHECK3-NEXT:    [[TMP183:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS44]], i32 0, i32 02540// CHECK3-NEXT:    store i32 [[TMP175]], ptr [[TMP183]], align 42541// CHECK3-NEXT:    [[TMP184:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS45]], i32 0, i32 02542// CHECK3-NEXT:    store ptr null, ptr [[TMP184]], align 42543// CHECK3-NEXT:    [[TMP185:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS43]], i32 0, i32 12544// CHECK3-NEXT:    store ptr [[B]], ptr [[TMP185]], align 42545// CHECK3-NEXT:    [[TMP186:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS44]], i32 0, i32 12546// CHECK3-NEXT:    store ptr [[B]], ptr [[TMP186]], align 42547// CHECK3-NEXT:    [[TMP187:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS45]], i32 0, i32 12548// CHECK3-NEXT:    store ptr null, ptr [[TMP187]], align 42549// CHECK3-NEXT:    [[TMP188:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS43]], i32 0, i32 22550// CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP188]], align 42551// CHECK3-NEXT:    [[TMP189:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS44]], i32 0, i32 22552// CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP189]], align 42553// CHECK3-NEXT:    [[TMP190:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS45]], i32 0, i32 22554// CHECK3-NEXT:    store ptr null, ptr [[TMP190]], align 42555// CHECK3-NEXT:    [[TMP191:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS43]], i32 0, i32 32556// CHECK3-NEXT:    store ptr [[VLA]], ptr [[TMP191]], align 42557// CHECK3-NEXT:    [[TMP192:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS44]], i32 0, i32 32558// CHECK3-NEXT:    store ptr [[VLA]], ptr [[TMP192]], align 42559// CHECK3-NEXT:    [[TMP193:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 32560// CHECK3-NEXT:    store i64 [[TMP178]], ptr [[TMP193]], align 42561// CHECK3-NEXT:    [[TMP194:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS45]], i32 0, i32 32562// CHECK3-NEXT:    store ptr null, ptr [[TMP194]], align 42563// CHECK3-NEXT:    [[TMP195:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS43]], i32 0, i32 42564// CHECK3-NEXT:    store ptr [[C]], ptr [[TMP195]], align 42565// CHECK3-NEXT:    [[TMP196:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS44]], i32 0, i32 42566// CHECK3-NEXT:    store ptr [[C]], ptr [[TMP196]], align 42567// CHECK3-NEXT:    [[TMP197:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS45]], i32 0, i32 42568// CHECK3-NEXT:    store ptr null, ptr [[TMP197]], align 42569// CHECK3-NEXT:    [[TMP198:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS43]], i32 0, i32 52570// CHECK3-NEXT:    store i32 5, ptr [[TMP198]], align 42571// CHECK3-NEXT:    [[TMP199:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS44]], i32 0, i32 52572// CHECK3-NEXT:    store i32 5, ptr [[TMP199]], align 42573// CHECK3-NEXT:    [[TMP200:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS45]], i32 0, i32 52574// CHECK3-NEXT:    store ptr null, ptr [[TMP200]], align 42575// CHECK3-NEXT:    [[TMP201:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS43]], i32 0, i32 62576// CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP201]], align 42577// CHECK3-NEXT:    [[TMP202:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS44]], i32 0, i32 62578// CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP202]], align 42579// CHECK3-NEXT:    [[TMP203:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS45]], i32 0, i32 62580// CHECK3-NEXT:    store ptr null, ptr [[TMP203]], align 42581// CHECK3-NEXT:    [[TMP204:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS43]], i32 0, i32 72582// CHECK3-NEXT:    store ptr [[VLA1]], ptr [[TMP204]], align 42583// CHECK3-NEXT:    [[TMP205:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS44]], i32 0, i32 72584// CHECK3-NEXT:    store ptr [[VLA1]], ptr [[TMP205]], align 42585// CHECK3-NEXT:    [[TMP206:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 72586// CHECK3-NEXT:    store i64 [[TMP181]], ptr [[TMP206]], align 42587// CHECK3-NEXT:    [[TMP207:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS45]], i32 0, i32 72588// CHECK3-NEXT:    store ptr null, ptr [[TMP207]], align 42589// CHECK3-NEXT:    [[TMP208:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS43]], i32 0, i32 82590// CHECK3-NEXT:    store ptr [[D]], ptr [[TMP208]], align 42591// CHECK3-NEXT:    [[TMP209:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS44]], i32 0, i32 82592// CHECK3-NEXT:    store ptr [[D]], ptr [[TMP209]], align 42593// CHECK3-NEXT:    [[TMP210:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS45]], i32 0, i32 82594// CHECK3-NEXT:    store ptr null, ptr [[TMP210]], align 42595// CHECK3-NEXT:    [[TMP211:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS43]], i32 0, i32 02596// CHECK3-NEXT:    [[TMP212:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS44]], i32 0, i32 02597// CHECK3-NEXT:    [[TMP213:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 02598// CHECK3-NEXT:    [[TMP214:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 02599// CHECK3-NEXT:    store i32 3, ptr [[TMP214]], align 42600// CHECK3-NEXT:    [[TMP215:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 12601// CHECK3-NEXT:    store i32 9, ptr [[TMP215]], align 42602// CHECK3-NEXT:    [[TMP216:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 22603// CHECK3-NEXT:    store ptr [[TMP211]], ptr [[TMP216]], align 42604// CHECK3-NEXT:    [[TMP217:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 32605// CHECK3-NEXT:    store ptr [[TMP212]], ptr [[TMP217]], align 42606// CHECK3-NEXT:    [[TMP218:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 42607// CHECK3-NEXT:    store ptr [[TMP213]], ptr [[TMP218]], align 42608// CHECK3-NEXT:    [[TMP219:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 52609// CHECK3-NEXT:    store ptr @.offload_maptypes.12, ptr [[TMP219]], align 42610// CHECK3-NEXT:    [[TMP220:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 62611// CHECK3-NEXT:    store ptr null, ptr [[TMP220]], align 42612// CHECK3-NEXT:    [[TMP221:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 72613// CHECK3-NEXT:    store ptr null, ptr [[TMP221]], align 42614// CHECK3-NEXT:    [[TMP222:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 82615// CHECK3-NEXT:    store i64 0, ptr [[TMP222]], align 82616// CHECK3-NEXT:    [[TMP223:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 92617// CHECK3-NEXT:    store i64 0, ptr [[TMP223]], align 82618// CHECK3-NEXT:    [[TMP224:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 102619// CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP224]], align 42620// CHECK3-NEXT:    [[TMP225:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 112621// CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP225]], align 42622// CHECK3-NEXT:    [[TMP226:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS46]], i32 0, i32 122623// CHECK3-NEXT:    store i32 0, ptr [[TMP226]], align 42624// CHECK3-NEXT:    [[TMP227:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.region_id, ptr [[KERNEL_ARGS46]])2625// CHECK3-NEXT:    [[TMP228:%.*]] = icmp ne i32 [[TMP227]], 02626// CHECK3-NEXT:    br i1 [[TMP228]], label [[OMP_OFFLOAD_FAILED47:%.*]], label [[OMP_OFFLOAD_CONT48:%.*]]2627// CHECK3:       omp_offload.failed47:2628// CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i32 [[TMP175]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]]2629// CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT48]]2630// CHECK3:       omp_offload.cont48:2631// CHECK3-NEXT:    br label [[OMP_IF_END50:%.*]]2632// CHECK3:       omp_if.else49:2633// CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i32 [[TMP175]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]]2634// CHECK3-NEXT:    br label [[OMP_IF_END50]]2635// CHECK3:       omp_if.end50:2636// CHECK3-NEXT:    store i32 0, ptr [[NN]], align 42637// CHECK3-NEXT:    [[TMP229:%.*]] = load i32, ptr [[NN]], align 42638// CHECK3-NEXT:    store i32 [[TMP229]], ptr [[NN_CASTED]], align 42639// CHECK3-NEXT:    [[TMP230:%.*]] = load i32, ptr [[NN_CASTED]], align 42640// CHECK3-NEXT:    [[TMP231:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS51]], i32 0, i32 02641// CHECK3-NEXT:    store i32 [[TMP230]], ptr [[TMP231]], align 42642// CHECK3-NEXT:    [[TMP232:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS52]], i32 0, i32 02643// CHECK3-NEXT:    store i32 [[TMP230]], ptr [[TMP232]], align 42644// CHECK3-NEXT:    [[TMP233:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS53]], i32 0, i32 02645// CHECK3-NEXT:    store ptr null, ptr [[TMP233]], align 42646// CHECK3-NEXT:    [[TMP234:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS51]], i32 0, i32 02647// CHECK3-NEXT:    [[TMP235:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS52]], i32 0, i32 02648// CHECK3-NEXT:    [[TMP236:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 02649// CHECK3-NEXT:    store i32 3, ptr [[TMP236]], align 42650// CHECK3-NEXT:    [[TMP237:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 12651// CHECK3-NEXT:    store i32 1, ptr [[TMP237]], align 42652// CHECK3-NEXT:    [[TMP238:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 22653// CHECK3-NEXT:    store ptr [[TMP234]], ptr [[TMP238]], align 42654// CHECK3-NEXT:    [[TMP239:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 32655// CHECK3-NEXT:    store ptr [[TMP235]], ptr [[TMP239]], align 42656// CHECK3-NEXT:    [[TMP240:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 42657// CHECK3-NEXT:    store ptr @.offload_sizes.13, ptr [[TMP240]], align 42658// CHECK3-NEXT:    [[TMP241:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 52659// CHECK3-NEXT:    store ptr @.offload_maptypes.14, ptr [[TMP241]], align 42660// CHECK3-NEXT:    [[TMP242:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 62661// CHECK3-NEXT:    store ptr null, ptr [[TMP242]], align 42662// CHECK3-NEXT:    [[TMP243:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 72663// CHECK3-NEXT:    store ptr null, ptr [[TMP243]], align 42664// CHECK3-NEXT:    [[TMP244:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 82665// CHECK3-NEXT:    store i64 0, ptr [[TMP244]], align 82666// CHECK3-NEXT:    [[TMP245:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 92667// CHECK3-NEXT:    store i64 0, ptr [[TMP245]], align 82668// CHECK3-NEXT:    [[TMP246:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 102669// CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP246]], align 42670// CHECK3-NEXT:    [[TMP247:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 112671// CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP247]], align 42672// CHECK3-NEXT:    [[TMP248:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS54]], i32 0, i32 122673// CHECK3-NEXT:    store i32 0, ptr [[TMP248]], align 42674// CHECK3-NEXT:    [[TMP249:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172.region_id, ptr [[KERNEL_ARGS54]])2675// CHECK3-NEXT:    [[TMP250:%.*]] = icmp ne i32 [[TMP249]], 02676// CHECK3-NEXT:    br i1 [[TMP250]], label [[OMP_OFFLOAD_FAILED55:%.*]], label [[OMP_OFFLOAD_CONT56:%.*]]2677// CHECK3:       omp_offload.failed55:2678// CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172(i32 [[TMP230]]) #[[ATTR3]]2679// CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT56]]2680// CHECK3:       omp_offload.cont56:2681// CHECK3-NEXT:    [[TMP251:%.*]] = load i32, ptr [[NN]], align 42682// CHECK3-NEXT:    store i32 [[TMP251]], ptr [[NN_CASTED57]], align 42683// CHECK3-NEXT:    [[TMP252:%.*]] = load i32, ptr [[NN_CASTED57]], align 42684// CHECK3-NEXT:    [[TMP253:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS58]], i32 0, i32 02685// CHECK3-NEXT:    store i32 [[TMP252]], ptr [[TMP253]], align 42686// CHECK3-NEXT:    [[TMP254:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS59]], i32 0, i32 02687// CHECK3-NEXT:    store i32 [[TMP252]], ptr [[TMP254]], align 42688// CHECK3-NEXT:    [[TMP255:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS60]], i32 0, i32 02689// CHECK3-NEXT:    store ptr null, ptr [[TMP255]], align 42690// CHECK3-NEXT:    [[TMP256:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS58]], i32 0, i32 02691// CHECK3-NEXT:    [[TMP257:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS59]], i32 0, i32 02692// CHECK3-NEXT:    [[TMP258:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 02693// CHECK3-NEXT:    store i32 3, ptr [[TMP258]], align 42694// CHECK3-NEXT:    [[TMP259:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 12695// CHECK3-NEXT:    store i32 1, ptr [[TMP259]], align 42696// CHECK3-NEXT:    [[TMP260:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 22697// CHECK3-NEXT:    store ptr [[TMP256]], ptr [[TMP260]], align 42698// CHECK3-NEXT:    [[TMP261:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 32699// CHECK3-NEXT:    store ptr [[TMP257]], ptr [[TMP261]], align 42700// CHECK3-NEXT:    [[TMP262:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 42701// CHECK3-NEXT:    store ptr @.offload_sizes.15, ptr [[TMP262]], align 42702// CHECK3-NEXT:    [[TMP263:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 52703// CHECK3-NEXT:    store ptr @.offload_maptypes.16, ptr [[TMP263]], align 42704// CHECK3-NEXT:    [[TMP264:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 62705// CHECK3-NEXT:    store ptr null, ptr [[TMP264]], align 42706// CHECK3-NEXT:    [[TMP265:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 72707// CHECK3-NEXT:    store ptr null, ptr [[TMP265]], align 42708// CHECK3-NEXT:    [[TMP266:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 82709// CHECK3-NEXT:    store i64 0, ptr [[TMP266]], align 82710// CHECK3-NEXT:    [[TMP267:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 92711// CHECK3-NEXT:    store i64 0, ptr [[TMP267]], align 82712// CHECK3-NEXT:    [[TMP268:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 102713// CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP268]], align 42714// CHECK3-NEXT:    [[TMP269:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 112715// CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP269]], align 42716// CHECK3-NEXT:    [[TMP270:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS61]], i32 0, i32 122717// CHECK3-NEXT:    store i32 0, ptr [[TMP270]], align 42718// CHECK3-NEXT:    [[TMP271:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175.region_id, ptr [[KERNEL_ARGS61]])2719// CHECK3-NEXT:    [[TMP272:%.*]] = icmp ne i32 [[TMP271]], 02720// CHECK3-NEXT:    br i1 [[TMP272]], label [[OMP_OFFLOAD_FAILED62:%.*]], label [[OMP_OFFLOAD_CONT63:%.*]]2721// CHECK3:       omp_offload.failed62:2722// CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175(i32 [[TMP252]]) #[[ATTR3]]2723// CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT63]]2724// CHECK3:       omp_offload.cont63:2725// CHECK3-NEXT:    [[TMP273:%.*]] = load i32, ptr [[A]], align 42726// CHECK3-NEXT:    [[TMP274:%.*]] = load ptr, ptr [[SAVED_STACK]], align 42727// CHECK3-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP274]])2728// CHECK3-NEXT:    ret i32 [[TMP273]]2729//2730//2731// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1012732// CHECK3-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {2733// CHECK3-NEXT:  entry:2734// CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 42735// CHECK3-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 42736// CHECK3-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 42737// CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 42738// CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])2739// CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 42740// CHECK3-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 42741// CHECK3-NEXT:    store i32 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 42742// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 42743// CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 42744// CHECK3-NEXT:    call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])2745// CHECK3-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 22746// CHECK3-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 22747// CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 42748// CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined, i32 [[TMP4]])2749// CHECK3-NEXT:    ret void2750//2751//2752// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined2753// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {2754// CHECK3-NEXT:  entry:2755// CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 42756// CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 42757// CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 42758// CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 42759// CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 42760// CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 42761// CHECK3-NEXT:    ret void2762//2763//2764// CHECK3-LABEL: define {{[^@]+}}@.omp_task_privates_map.2765// CHECK3-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] {2766// CHECK3-NEXT:  entry:2767// CHECK3-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 42768// CHECK3-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 42769// CHECK3-NEXT:    [[DOTADDR2:%.*]] = alloca ptr, align 42770// CHECK3-NEXT:    [[DOTADDR3:%.*]] = alloca ptr, align 42771// CHECK3-NEXT:    [[DOTADDR4:%.*]] = alloca ptr, align 42772// CHECK3-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 42773// CHECK3-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 42774// CHECK3-NEXT:    store ptr [[TMP2]], ptr [[DOTADDR2]], align 42775// CHECK3-NEXT:    store ptr [[TMP3]], ptr [[DOTADDR3]], align 42776// CHECK3-NEXT:    store ptr [[TMP4]], ptr [[DOTADDR4]], align 42777// CHECK3-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 42778// CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP5]], i32 0, i32 02779// CHECK3-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTADDR4]], align 42780// CHECK3-NEXT:    store ptr [[TMP6]], ptr [[TMP7]], align 42781// CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 12782// CHECK3-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[DOTADDR2]], align 42783// CHECK3-NEXT:    store ptr [[TMP8]], ptr [[TMP9]], align 42784// CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 22785// CHECK3-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[DOTADDR3]], align 42786// CHECK3-NEXT:    store ptr [[TMP10]], ptr [[TMP11]], align 42787// CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 32788// CHECK3-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[DOTADDR1]], align 42789// CHECK3-NEXT:    store ptr [[TMP12]], ptr [[TMP13]], align 42790// CHECK3-NEXT:    ret void2791//2792//2793// CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry.2794// CHECK3-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {2795// CHECK3-NEXT:  entry:2796// CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 42797// CHECK3-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 42798// CHECK3-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 42799// CHECK3-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 42800// CHECK3-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 42801// CHECK3-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 42802// CHECK3-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 42803// CHECK3-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 42804// CHECK3-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca ptr, align 42805// CHECK3-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca ptr, align 42806// CHECK3-NEXT:    [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 82807// CHECK3-NEXT:    [[AA_CASTED_I:%.*]] = alloca i32, align 42808// CHECK3-NEXT:    [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 42809// CHECK3-NEXT:    [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 42810// CHECK3-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 42811// CHECK3-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 42812// CHECK3-NEXT:    store i32 [[TMP0]], ptr [[DOTADDR]], align 42813// CHECK3-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 42814// CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 42815// CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 42816// CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 02817// CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 22818// CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 02819// CHECK3-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 42820// CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 12821// CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])2822// CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])2823// CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]])2824// CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META26:![0-9]+]])2825// CHECK3-NEXT:    store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META28:![0-9]+]]2826// CHECK3-NEXT:    store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 4, !noalias [[META28]]2827// CHECK3-NEXT:    store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias [[META28]]2828// CHECK3-NEXT:    store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias [[META28]]2829// CHECK3-NEXT:    store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 4, !noalias [[META28]]2830// CHECK3-NEXT:    store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 4, !noalias [[META28]]2831// CHECK3-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias [[META28]]2832// CHECK3-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias [[META28]]2833// CHECK3-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias [[META28]]2834// CHECK3-NEXT:    call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]2835// CHECK3-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias [[META28]]2836// CHECK3-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias [[META28]]2837// CHECK3-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias [[META28]]2838// CHECK3-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias [[META28]]2839// CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP9]], i32 0, i32 12840// CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 22841// CHECK3-NEXT:    [[TMP18:%.*]] = load i32, ptr [[TMP16]], align 42842// CHECK3-NEXT:    [[TMP19:%.*]] = load i32, ptr [[TMP17]], align 42843// CHECK3-NEXT:    [[TMP20:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP18]], 02844// CHECK3-NEXT:    [[TMP21:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP19]], 02845// CHECK3-NEXT:    store i32 3, ptr [[KERNEL_ARGS_I]], align 4, !noalias [[META28]]2846// CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 12847// CHECK3-NEXT:    store i32 3, ptr [[TMP22]], align 4, !noalias [[META28]]2848// CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 22849// CHECK3-NEXT:    store ptr [[TMP13]], ptr [[TMP23]], align 4, !noalias [[META28]]2850// CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 32851// CHECK3-NEXT:    store ptr [[TMP14]], ptr [[TMP24]], align 4, !noalias [[META28]]2852// CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 42853// CHECK3-NEXT:    store ptr [[TMP15]], ptr [[TMP25]], align 4, !noalias [[META28]]2854// CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 52855// CHECK3-NEXT:    store ptr @.offload_maptypes, ptr [[TMP26]], align 4, !noalias [[META28]]2856// CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 62857// CHECK3-NEXT:    store ptr null, ptr [[TMP27]], align 4, !noalias [[META28]]2858// CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 72859// CHECK3-NEXT:    store ptr null, ptr [[TMP28]], align 4, !noalias [[META28]]2860// CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 82861// CHECK3-NEXT:    store i64 0, ptr [[TMP29]], align 8, !noalias [[META28]]2862// CHECK3-NEXT:    [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 92863// CHECK3-NEXT:    store i64 1, ptr [[TMP30]], align 8, !noalias [[META28]]2864// CHECK3-NEXT:    [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 102865// CHECK3-NEXT:    store [3 x i32] [[TMP20]], ptr [[TMP31]], align 4, !noalias [[META28]]2866// CHECK3-NEXT:    [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 112867// CHECK3-NEXT:    store [3 x i32] [[TMP21]], ptr [[TMP32]], align 4, !noalias [[META28]]2868// CHECK3-NEXT:    [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 122869// CHECK3-NEXT:    store i32 0, ptr [[TMP33]], align 4, !noalias [[META28]]2870// CHECK3-NEXT:    [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 [[TMP18]], i32 [[TMP19]], ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, ptr [[KERNEL_ARGS_I]])2871// CHECK3-NEXT:    [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 02872// CHECK3-NEXT:    br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]]2873// CHECK3:       omp_offload.failed.i:2874// CHECK3-NEXT:    [[TMP36:%.*]] = load i16, ptr [[TMP12]], align 22875// CHECK3-NEXT:    store i16 [[TMP36]], ptr [[AA_CASTED_I]], align 2, !noalias [[META28]]2876// CHECK3-NEXT:    [[TMP37:%.*]] = load i32, ptr [[AA_CASTED_I]], align 4, !noalias [[META28]]2877// CHECK3-NEXT:    [[TMP38:%.*]] = load i32, ptr [[TMP16]], align 42878// CHECK3-NEXT:    store i32 [[TMP38]], ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias [[META28]]2879// CHECK3-NEXT:    [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias [[META28]]2880// CHECK3-NEXT:    [[TMP40:%.*]] = load i32, ptr [[TMP17]], align 42881// CHECK3-NEXT:    store i32 [[TMP40]], ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias [[META28]]2882// CHECK3-NEXT:    [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias [[META28]]2883// CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP37]], i32 [[TMP39]], i32 [[TMP41]]) #[[ATTR3]]2884// CHECK3-NEXT:    br label [[DOTOMP_OUTLINED__EXIT]]2885// CHECK3:       .omp_outlined..exit:2886// CHECK3-NEXT:    ret i32 02887//2888//2889// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1052890// CHECK3-SAME: (i32 noundef [[A:%.*]]) #[[ATTR2]] {2891// CHECK3-NEXT:  entry:2892// CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 42893// CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 42894// CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 42895// CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 42896// CHECK3-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 42897// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 42898// CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105.omp_outlined, i32 [[TMP1]])2899// CHECK3-NEXT:    ret void2900//2901//2902// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105.omp_outlined2903// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] {2904// CHECK3-NEXT:  entry:2905// CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 42906// CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 42907// CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 42908// CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 42909// CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 42910// CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 42911// CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 42912// CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 12913// CHECK3-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 42914// CHECK3-NEXT:    ret void2915//2916//2917// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1112918// CHECK3-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] {2919// CHECK3-NEXT:  entry:2920// CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 42921// CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 42922// CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 42923// CHECK3-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 22924// CHECK3-NEXT:    store i16 [[TMP0]], ptr [[AA_CASTED]], align 22925// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 42926// CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i32 [[TMP1]])2927// CHECK3-NEXT:    ret void2928//2929//2930// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined2931// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {2932// CHECK3-NEXT:  entry:2933// CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 42934// CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 42935// CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 42936// CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 42937// CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 42938// CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 42939// CHECK3-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 22940// CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP0]] to i322941// CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 12942// CHECK3-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i162943// CHECK3-NEXT:    store i16 [[CONV1]], ptr [[AA_ADDR]], align 22944// CHECK3-NEXT:    ret void2945//2946//2947// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1182948// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {2949// CHECK3-NEXT:  entry:2950// CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 42951// CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 42952// CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 42953// CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 42954// CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 42955// CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 42956// CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 42957// CHECK3-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 42958// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 42959// CHECK3-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 22960// CHECK3-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 22961// CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 42962// CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i32 [[TMP1]], i32 [[TMP3]])2963// CHECK3-NEXT:    ret void2964//2965//2966// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined2967// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {2968// CHECK3-NEXT:  entry:2969// CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 42970// CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 42971// CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 42972// CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 42973// CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 42974// CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 42975// CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 42976// CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 42977// CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 42978// CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 12979// CHECK3-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 42980// CHECK3-NEXT:    [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 22981// CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i322982// CHECK3-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 12983// CHECK3-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i162984// CHECK3-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 22985// CHECK3-NEXT:    ret void2986//2987//2988// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1242989// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {2990// CHECK3-NEXT:  entry:2991// CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 42992// CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 42993// CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 42994// CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 42995// CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])2996// CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 42997// CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 42998// CHECK3-NEXT:    call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 1)2999// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 43000// CHECK3-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 43001// CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 43002// CHECK3-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 23003// CHECK3-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 23004// CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 43005// CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124.omp_outlined, i32 [[TMP2]], i32 [[TMP4]])3006// CHECK3-NEXT:    ret void3007//3008//3009// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124.omp_outlined3010// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {3011// CHECK3-NEXT:  entry:3012// CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 43013// CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 43014// CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 43015// CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 43016// CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 43017// CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 43018// CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 43019// CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 43020// CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 43021// CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 13022// CHECK3-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 43023// CHECK3-NEXT:    [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 23024// CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i323025// CHECK3-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 13026// CHECK3-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i163027// CHECK3-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 23028// CHECK3-NEXT:    ret void3029//3030//3031// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1303032// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {3033// CHECK3-NEXT:  entry:3034// CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 43035// CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 43036// CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 43037// CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 43038// CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])3039// CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 43040// CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 43041// CHECK3-NEXT:    call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 1)3042// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 43043// CHECK3-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 43044// CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 43045// CHECK3-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 23046// CHECK3-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 23047// CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 43048// CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l130.omp_outlined, i32 [[TMP2]], i32 [[TMP4]])3049// CHECK3-NEXT:    ret void3050//3051//3052// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l130.omp_outlined3053// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {3054// CHECK3-NEXT:  entry:3055// CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 43056// CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 43057// CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 43058// CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 43059// CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 43060// CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 43061// CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 43062// CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 43063// CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 43064// CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 13065// CHECK3-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 43066// CHECK3-NEXT:    [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 23067// CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i323068// CHECK3-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 13069// CHECK3-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i163070// CHECK3-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 23071// CHECK3-NEXT:    ret void3072//3073//3074// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1363075// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {3076// CHECK3-NEXT:  entry:3077// CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 43078// CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 43079// CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 43080// CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 43081// CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])3082// CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 43083// CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 43084// CHECK3-NEXT:    call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 1)3085// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 43086// CHECK3-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 43087// CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 43088// CHECK3-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 23089// CHECK3-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 23090// CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 43091// CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined, i32 [[TMP2]], i32 [[TMP4]])3092// CHECK3-NEXT:    ret void3093//3094//3095// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined3096// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {3097// CHECK3-NEXT:  entry:3098// CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 43099// CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 43100// CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 43101// CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 43102// CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 43103// CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 43104// CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 43105// CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 43106// CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 43107// CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 13108// CHECK3-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 43109// CHECK3-NEXT:    [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 23110// CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i323111// CHECK3-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 13112// CHECK3-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i163113// CHECK3-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 23114// CHECK3-NEXT:    ret void3115//3116//3117// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1603118// CHECK3-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {3119// CHECK3-NEXT:  entry:3120// CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 43121// CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 43122// CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 43123// CHECK3-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 43124// CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 43125// CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 43126// CHECK3-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 43127// CHECK3-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 43128// CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 43129// CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 43130// CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 43131// CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 43132// CHECK3-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 43133// CHECK3-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 43134// CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 43135// CHECK3-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 43136// CHECK3-NEXT:    store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 43137// CHECK3-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 43138// CHECK3-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 43139// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 43140// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 43141// CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 43142// CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 43143// CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 43144// CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 43145// CHECK3-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 43146// CHECK3-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 43147// CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 43148// CHECK3-NEXT:    store i32 [[TMP8]], ptr [[A_CASTED]], align 43149// CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 43150// CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]])3151// CHECK3-NEXT:    ret void3152//3153//3154// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined3155// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {3156// CHECK3-NEXT:  entry:3157// CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 43158// CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 43159// CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 43160// CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 43161// CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 43162// CHECK3-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 43163// CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 43164// CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 43165// CHECK3-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 43166// CHECK3-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 43167// CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 43168// CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 43169// CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 43170// CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 43171// CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 43172// CHECK3-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 43173// CHECK3-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 43174// CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 43175// CHECK3-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 43176// CHECK3-NEXT:    store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 43177// CHECK3-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 43178// CHECK3-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 43179// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 43180// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 43181// CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 43182// CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 43183// CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 43184// CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 43185// CHECK3-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 43186// CHECK3-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 43187// CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 43188// CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP8]], 13189// CHECK3-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 43190// CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 23191// CHECK3-NEXT:    [[TMP9:%.*]] = load float, ptr [[ARRAYIDX]], align 43192// CHECK3-NEXT:    [[CONV:%.*]] = fpext float [[TMP9]] to double3193// CHECK3-NEXT:    [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+003194// CHECK3-NEXT:    [[CONV6:%.*]] = fptrunc double [[ADD5]] to float3195// CHECK3-NEXT:    store float [[CONV6]], ptr [[ARRAYIDX]], align 43196// CHECK3-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 33197// CHECK3-NEXT:    [[TMP10:%.*]] = load float, ptr [[ARRAYIDX7]], align 43198// CHECK3-NEXT:    [[CONV8:%.*]] = fpext float [[TMP10]] to double3199// CHECK3-NEXT:    [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+003200// CHECK3-NEXT:    [[CONV10:%.*]] = fptrunc double [[ADD9]] to float3201// CHECK3-NEXT:    store float [[CONV10]], ptr [[ARRAYIDX7]], align 43202// CHECK3-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 13203// CHECK3-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX11]], i32 0, i32 23204// CHECK3-NEXT:    [[TMP11:%.*]] = load double, ptr [[ARRAYIDX12]], align 83205// CHECK3-NEXT:    [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+003206// CHECK3-NEXT:    store double [[ADD13]], ptr [[ARRAYIDX12]], align 83207// CHECK3-NEXT:    [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]]3208// CHECK3-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP12]]3209// CHECK3-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i32 33210// CHECK3-NEXT:    [[TMP13:%.*]] = load double, ptr [[ARRAYIDX15]], align 83211// CHECK3-NEXT:    [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+003212// CHECK3-NEXT:    store double [[ADD16]], ptr [[ARRAYIDX15]], align 83213// CHECK3-NEXT:    [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 03214// CHECK3-NEXT:    [[TMP14:%.*]] = load i64, ptr [[X]], align 43215// CHECK3-NEXT:    [[ADD17:%.*]] = add nsw i64 [[TMP14]], 13216// CHECK3-NEXT:    store i64 [[ADD17]], ptr [[X]], align 43217// CHECK3-NEXT:    [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 13218// CHECK3-NEXT:    [[TMP15:%.*]] = load i8, ptr [[Y]], align 43219// CHECK3-NEXT:    [[CONV18:%.*]] = sext i8 [[TMP15]] to i323220// CHECK3-NEXT:    [[ADD19:%.*]] = add nsw i32 [[CONV18]], 13221// CHECK3-NEXT:    [[CONV20:%.*]] = trunc i32 [[ADD19]] to i83222// CHECK3-NEXT:    store i8 [[CONV20]], ptr [[Y]], align 43223// CHECK3-NEXT:    ret void3224//3225//3226// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1723227// CHECK3-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR2]] {3228// CHECK3-NEXT:  entry:3229// CHECK3-NEXT:    [[NN_ADDR:%.*]] = alloca i32, align 43230// CHECK3-NEXT:    [[NN_CASTED:%.*]] = alloca i32, align 43231// CHECK3-NEXT:    store i32 [[NN]], ptr [[NN_ADDR]], align 43232// CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[NN_ADDR]], align 43233// CHECK3-NEXT:    store i32 [[TMP0]], ptr [[NN_CASTED]], align 43234// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[NN_CASTED]], align 43235// CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172.omp_outlined, i32 [[TMP1]])3236// CHECK3-NEXT:    ret void3237//3238//3239// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172.omp_outlined3240// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR2]] {3241// CHECK3-NEXT:  entry:3242// CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 43243// CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 43244// CHECK3-NEXT:    [[NN_ADDR:%.*]] = alloca i32, align 43245// CHECK3-NEXT:    [[NN_CASTED:%.*]] = alloca i32, align 43246// CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 43247// CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 43248// CHECK3-NEXT:    store i32 [[NN]], ptr [[NN_ADDR]], align 43249// CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[NN_ADDR]], align 43250// CHECK3-NEXT:    store i32 [[TMP0]], ptr [[NN_CASTED]], align 43251// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[NN_CASTED]], align 43252// CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172.omp_outlined.omp_outlined, i32 [[TMP1]])3253// CHECK3-NEXT:    ret void3254//3255//3256// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172.omp_outlined.omp_outlined3257// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR2]] {3258// CHECK3-NEXT:  entry:3259// CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 43260// CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 43261// CHECK3-NEXT:    [[NN_ADDR:%.*]] = alloca i32, align 43262// CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 43263// CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 43264// CHECK3-NEXT:    store i32 [[NN]], ptr [[NN_ADDR]], align 43265// CHECK3-NEXT:    ret void3266//3267//3268// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1753269// CHECK3-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR2]] {3270// CHECK3-NEXT:  entry:3271// CHECK3-NEXT:    [[NN_ADDR:%.*]] = alloca i32, align 43272// CHECK3-NEXT:    [[NN_CASTED:%.*]] = alloca i32, align 43273// CHECK3-NEXT:    store i32 [[NN]], ptr [[NN_ADDR]], align 43274// CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[NN_ADDR]], align 43275// CHECK3-NEXT:    store i32 [[TMP0]], ptr [[NN_CASTED]], align 43276// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[NN_CASTED]], align 43277// CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175.omp_outlined, i32 [[TMP1]])3278// CHECK3-NEXT:    ret void3279//3280//3281// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175.omp_outlined3282// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR2]] {3283// CHECK3-NEXT:  entry:3284// CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 43285// CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 43286// CHECK3-NEXT:    [[NN_ADDR:%.*]] = alloca i32, align 43287// CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 43288// CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 43289// CHECK3-NEXT:    store i32 [[NN]], ptr [[NN_ADDR]], align 43290// CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175.omp_outlined.omp_outlined, ptr [[NN_ADDR]])3291// CHECK3-NEXT:    ret void3292//3293//3294// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175.omp_outlined.omp_outlined3295// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] {3296// CHECK3-NEXT:  entry:3297// CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 43298// CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 43299// CHECK3-NEXT:    [[NN_ADDR:%.*]] = alloca ptr, align 43300// CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 43301// CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 43302// CHECK3-NEXT:    store ptr [[NN]], ptr [[NN_ADDR]], align 43303// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[NN_ADDR]], align 43304// CHECK3-NEXT:    ret void3305//3306//3307// CHECK3-LABEL: define {{[^@]+}}@_Z6bazzzziPi3308// CHECK3-SAME: (i32 noundef [[N:%.*]], ptr noundef [[F:%.*]]) #[[ATTR0]] {3309// CHECK3-NEXT:  entry:3310// CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 43311// CHECK3-NEXT:    [[F_ADDR:%.*]] = alloca ptr, align 43312// CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 43313// CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 43314// CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 43315// CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 83316// CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 43317// CHECK3-NEXT:    store ptr [[F]], ptr [[F_ADDR]], align 43318// CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 43319// CHECK3-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 03320// CHECK3-NEXT:    store i32 [[TMP0]], ptr [[TMP1]], align 43321// CHECK3-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 03322// CHECK3-NEXT:    store i32 [[TMP0]], ptr [[TMP2]], align 43323// CHECK3-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 03324// CHECK3-NEXT:    store ptr null, ptr [[TMP3]], align 43325// CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 03326// CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 03327// CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 03328// CHECK3-NEXT:    store i32 3, ptr [[TMP6]], align 43329// CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 13330// CHECK3-NEXT:    store i32 1, ptr [[TMP7]], align 43331// CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 23332// CHECK3-NEXT:    store ptr [[TMP4]], ptr [[TMP8]], align 43333// CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 33334// CHECK3-NEXT:    store ptr [[TMP5]], ptr [[TMP9]], align 43335// CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 43336// CHECK3-NEXT:    store ptr @.offload_sizes.17, ptr [[TMP10]], align 43337// CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 53338// CHECK3-NEXT:    store ptr @.offload_maptypes.18, ptr [[TMP11]], align 43339// CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 63340// CHECK3-NEXT:    store ptr null, ptr [[TMP12]], align 43341// CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 73342// CHECK3-NEXT:    store ptr null, ptr [[TMP13]], align 43343// CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 83344// CHECK3-NEXT:    store i64 0, ptr [[TMP14]], align 83345// CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 93346// CHECK3-NEXT:    store i64 0, ptr [[TMP15]], align 83347// CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 103348// CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP16]], align 43349// CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 113350// CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP17]], align 43351// CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 123352// CHECK3-NEXT:    store i32 0, ptr [[TMP18]], align 43353// CHECK3-NEXT:    [[TMP19:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l200.region_id, ptr [[KERNEL_ARGS]])3354// CHECK3-NEXT:    [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 03355// CHECK3-NEXT:    br i1 [[TMP20]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]3356// CHECK3:       omp_offload.failed:3357// CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l200(i32 [[TMP0]]) #[[ATTR3]]3358// CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]3359// CHECK3:       omp_offload.cont:3360// CHECK3-NEXT:    ret void3361//3362//3363// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l2003364// CHECK3-SAME: (i32 noundef [[VLA:%.*]]) #[[ATTR2]] {3365// CHECK3-NEXT:  entry:3366// CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 43367// CHECK3-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 43368// CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[VLA_ADDR]], align 43369// CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l200.omp_outlined, i32 [[TMP0]])3370// CHECK3-NEXT:    ret void3371//3372//3373// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l200.omp_outlined3374// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[VLA:%.*]]) #[[ATTR2]] {3375// CHECK3-NEXT:  entry:3376// CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 43377// CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 43378// CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 43379// CHECK3-NEXT:    [[F:%.*]] = alloca ptr, align 43380// CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 43381// CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 43382// CHECK3-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 43383// CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[VLA_ADDR]], align 43384// CHECK3-NEXT:    ret void3385//3386//3387// CHECK3-LABEL: define {{[^@]+}}@_Z3bari3388// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {3389// CHECK3-NEXT:  entry:3390// CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 43391// CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 43392// CHECK3-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 43393// CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 43394// CHECK3-NEXT:    store i32 0, ptr [[A]], align 43395// CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 43396// CHECK3-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]])3397// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A]], align 43398// CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]3399// CHECK3-NEXT:    store i32 [[ADD]], ptr [[A]], align 43400// CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 43401// CHECK3-NEXT:    [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]])3402// CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 43403// CHECK3-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]3404// CHECK3-NEXT:    store i32 [[ADD2]], ptr [[A]], align 43405// CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 43406// CHECK3-NEXT:    [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]])3407// CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A]], align 43408// CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]3409// CHECK3-NEXT:    store i32 [[ADD4]], ptr [[A]], align 43410// CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 43411// CHECK3-NEXT:    [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]])3412// CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[A]], align 43413// CHECK3-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]3414// CHECK3-NEXT:    store i32 [[ADD6]], ptr [[A]], align 43415// CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A]], align 43416// CHECK3-NEXT:    ret i32 [[TMP8]]3417//3418//3419// CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei3420// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {3421// CHECK3-NEXT:  entry:3422// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 43423// CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 43424// CHECK3-NEXT:    [[B:%.*]] = alloca i32, align 43425// CHECK3-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 43426// CHECK3-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 43427// CHECK3-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 43428// CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 43429// CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 43430// CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 43431// CHECK3-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 43432// CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 83433// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 43434// CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 43435// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 43436// CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 43437// CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 13438// CHECK3-NEXT:    store i32 [[ADD]], ptr [[B]], align 43439// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 43440// CHECK3-NEXT:    [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()3441// CHECK3-NEXT:    store ptr [[TMP2]], ptr [[SAVED_STACK]], align 43442// CHECK3-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]3443// CHECK3-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 23444// CHECK3-NEXT:    store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 43445// CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B]], align 43446// CHECK3-NEXT:    store i32 [[TMP4]], ptr [[B_CASTED]], align 43447// CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 43448// CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 43449// CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 603450// CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]3451// CHECK3:       omp_if.then:3452// CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 03453// CHECK3-NEXT:    [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]]3454// CHECK3-NEXT:    [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 23455// CHECK3-NEXT:    [[TMP9:%.*]] = sext i32 [[TMP8]] to i643456// CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.19, i32 40, i1 false)3457// CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 03458// CHECK3-NEXT:    store ptr [[THIS1]], ptr [[TMP10]], align 43459// CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 03460// CHECK3-NEXT:    store ptr [[A]], ptr [[TMP11]], align 43461// CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 03462// CHECK3-NEXT:    store ptr null, ptr [[TMP12]], align 43463// CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 13464// CHECK3-NEXT:    store i32 [[TMP5]], ptr [[TMP13]], align 43465// CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 13466// CHECK3-NEXT:    store i32 [[TMP5]], ptr [[TMP14]], align 43467// CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 13468// CHECK3-NEXT:    store ptr null, ptr [[TMP15]], align 43469// CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 23470// CHECK3-NEXT:    store i32 2, ptr [[TMP16]], align 43471// CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 23472// CHECK3-NEXT:    store i32 2, ptr [[TMP17]], align 43473// CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 23474// CHECK3-NEXT:    store ptr null, ptr [[TMP18]], align 43475// CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 33476// CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP19]], align 43477// CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 33478// CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP20]], align 43479// CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 33480// CHECK3-NEXT:    store ptr null, ptr [[TMP21]], align 43481// CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 43482// CHECK3-NEXT:    store ptr [[VLA]], ptr [[TMP22]], align 43483// CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 43484// CHECK3-NEXT:    store ptr [[VLA]], ptr [[TMP23]], align 43485// CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 43486// CHECK3-NEXT:    store i64 [[TMP9]], ptr [[TMP24]], align 43487// CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 43488// CHECK3-NEXT:    store ptr null, ptr [[TMP25]], align 43489// CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 03490// CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 03491// CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 03492// CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 03493// CHECK3-NEXT:    store i32 3, ptr [[TMP29]], align 43494// CHECK3-NEXT:    [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 13495// CHECK3-NEXT:    store i32 5, ptr [[TMP30]], align 43496// CHECK3-NEXT:    [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 23497// CHECK3-NEXT:    store ptr [[TMP26]], ptr [[TMP31]], align 43498// CHECK3-NEXT:    [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 33499// CHECK3-NEXT:    store ptr [[TMP27]], ptr [[TMP32]], align 43500// CHECK3-NEXT:    [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 43501// CHECK3-NEXT:    store ptr [[TMP28]], ptr [[TMP33]], align 43502// CHECK3-NEXT:    [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 53503// CHECK3-NEXT:    store ptr @.offload_maptypes.20, ptr [[TMP34]], align 43504// CHECK3-NEXT:    [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 63505// CHECK3-NEXT:    store ptr null, ptr [[TMP35]], align 43506// CHECK3-NEXT:    [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 73507// CHECK3-NEXT:    store ptr null, ptr [[TMP36]], align 43508// CHECK3-NEXT:    [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 83509// CHECK3-NEXT:    store i64 0, ptr [[TMP37]], align 83510// CHECK3-NEXT:    [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 93511// CHECK3-NEXT:    store i64 0, ptr [[TMP38]], align 83512// CHECK3-NEXT:    [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 103513// CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP39]], align 43514// CHECK3-NEXT:    [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 113515// CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP40]], align 43516// CHECK3-NEXT:    [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 123517// CHECK3-NEXT:    store i32 0, ptr [[TMP41]], align 43518// CHECK3-NEXT:    [[TMP42:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l245.region_id, ptr [[KERNEL_ARGS]])3519// CHECK3-NEXT:    [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 03520// CHECK3-NEXT:    br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]3521// CHECK3:       omp_offload.failed:3522// CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l245(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3]]3523// CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]3524// CHECK3:       omp_offload.cont:3525// CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]3526// CHECK3:       omp_if.else:3527// CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l245(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3]]3528// CHECK3-NEXT:    br label [[OMP_IF_END]]3529// CHECK3:       omp_if.end:3530// CHECK3-NEXT:    [[TMP44:%.*]] = mul nsw i32 1, [[TMP1]]3531// CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP44]]3532// CHECK3-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 13533// CHECK3-NEXT:    [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 23534// CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP45]] to i323535// CHECK3-NEXT:    [[TMP46:%.*]] = load i32, ptr [[B]], align 43536// CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]]3537// CHECK3-NEXT:    [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 43538// CHECK3-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP47]])3539// CHECK3-NEXT:    ret i32 [[ADD3]]3540//3541//3542// CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici3543// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {3544// CHECK3-NEXT:  entry:3545// CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 43546// CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 43547// CHECK3-NEXT:    [[AA:%.*]] = alloca i16, align 23548// CHECK3-NEXT:    [[AAA:%.*]] = alloca i8, align 13549// CHECK3-NEXT:    [[B:%.*]] = alloca [10 x i32], align 43550// CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 43551// CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 43552// CHECK3-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 43553// CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 43554// CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 43555// CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 43556// CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 83557// CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 43558// CHECK3-NEXT:    store i32 0, ptr [[A]], align 43559// CHECK3-NEXT:    store i16 0, ptr [[AA]], align 23560// CHECK3-NEXT:    store i8 0, ptr [[AAA]], align 13561// CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A]], align 43562// CHECK3-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 43563// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 43564// CHECK3-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA]], align 23565// CHECK3-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 23566// CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 43567// CHECK3-NEXT:    [[TMP4:%.*]] = load i8, ptr [[AAA]], align 13568// CHECK3-NEXT:    store i8 [[TMP4]], ptr [[AAA_CASTED]], align 13569// CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[AAA_CASTED]], align 43570// CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 43571// CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 503572// CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]3573// CHECK3:       omp_if.then:3574// CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 03575// CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP7]], align 43576// CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 03577// CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP8]], align 43578// CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 03579// CHECK3-NEXT:    store ptr null, ptr [[TMP9]], align 43580// CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 13581// CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP10]], align 43582// CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 13583// CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP11]], align 43584// CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 13585// CHECK3-NEXT:    store ptr null, ptr [[TMP12]], align 43586// CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 23587// CHECK3-NEXT:    store i32 [[TMP5]], ptr [[TMP13]], align 43588// CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 23589// CHECK3-NEXT:    store i32 [[TMP5]], ptr [[TMP14]], align 43590// CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 23591// CHECK3-NEXT:    store ptr null, ptr [[TMP15]], align 43592// CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 33593// CHECK3-NEXT:    store ptr [[B]], ptr [[TMP16]], align 43594// CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 33595// CHECK3-NEXT:    store ptr [[B]], ptr [[TMP17]], align 43596// CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 33597// CHECK3-NEXT:    store ptr null, ptr [[TMP18]], align 43598// CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 03599// CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 03600// CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 03601// CHECK3-NEXT:    store i32 3, ptr [[TMP21]], align 43602// CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 13603// CHECK3-NEXT:    store i32 4, ptr [[TMP22]], align 43604// CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 23605// CHECK3-NEXT:    store ptr [[TMP19]], ptr [[TMP23]], align 43606// CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 33607// CHECK3-NEXT:    store ptr [[TMP20]], ptr [[TMP24]], align 43608// CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 43609// CHECK3-NEXT:    store ptr @.offload_sizes.21, ptr [[TMP25]], align 43610// CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 53611// CHECK3-NEXT:    store ptr @.offload_maptypes.22, ptr [[TMP26]], align 43612// CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 63613// CHECK3-NEXT:    store ptr null, ptr [[TMP27]], align 43614// CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 73615// CHECK3-NEXT:    store ptr null, ptr [[TMP28]], align 43616// CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 83617// CHECK3-NEXT:    store i64 0, ptr [[TMP29]], align 83618// CHECK3-NEXT:    [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 93619// CHECK3-NEXT:    store i64 0, ptr [[TMP30]], align 83620// CHECK3-NEXT:    [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 103621// CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP31]], align 43622// CHECK3-NEXT:    [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 113623// CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP32]], align 43624// CHECK3-NEXT:    [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 123625// CHECK3-NEXT:    store i32 0, ptr [[TMP33]], align 43626// CHECK3-NEXT:    [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l227.region_id, ptr [[KERNEL_ARGS]])3627// CHECK3-NEXT:    [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 03628// CHECK3-NEXT:    br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]3629// CHECK3:       omp_offload.failed:3630// CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l227(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR3]]3631// CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]3632// CHECK3:       omp_offload.cont:3633// CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]3634// CHECK3:       omp_if.else:3635// CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l227(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR3]]3636// CHECK3-NEXT:    br label [[OMP_IF_END]]3637// CHECK3:       omp_if.end:3638// CHECK3-NEXT:    [[TMP36:%.*]] = load i32, ptr [[A]], align 43639// CHECK3-NEXT:    ret i32 [[TMP36]]3640//3641//3642// CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i3643// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {3644// CHECK3-NEXT:  entry:3645// CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 43646// CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 43647// CHECK3-NEXT:    [[AA:%.*]] = alloca i16, align 23648// CHECK3-NEXT:    [[B:%.*]] = alloca [10 x i32], align 43649// CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 43650// CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 43651// CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 43652// CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 43653// CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 43654// CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 83655// CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 43656// CHECK3-NEXT:    store i32 0, ptr [[A]], align 43657// CHECK3-NEXT:    store i16 0, ptr [[AA]], align 23658// CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A]], align 43659// CHECK3-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 43660// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 43661// CHECK3-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA]], align 23662// CHECK3-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 23663// CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 43664// CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 43665// CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 403666// CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]3667// CHECK3:       omp_if.then:3668// CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 03669// CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP5]], align 43670// CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 03671// CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP6]], align 43672// CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 03673// CHECK3-NEXT:    store ptr null, ptr [[TMP7]], align 43674// CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 13675// CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP8]], align 43676// CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 13677// CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP9]], align 43678// CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 13679// CHECK3-NEXT:    store ptr null, ptr [[TMP10]], align 43680// CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 23681// CHECK3-NEXT:    store ptr [[B]], ptr [[TMP11]], align 43682// CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 23683// CHECK3-NEXT:    store ptr [[B]], ptr [[TMP12]], align 43684// CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 23685// CHECK3-NEXT:    store ptr null, ptr [[TMP13]], align 43686// CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 03687// CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 03688// CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 03689// CHECK3-NEXT:    store i32 3, ptr [[TMP16]], align 43690// CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 13691// CHECK3-NEXT:    store i32 3, ptr [[TMP17]], align 43692// CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 23693// CHECK3-NEXT:    store ptr [[TMP14]], ptr [[TMP18]], align 43694// CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 33695// CHECK3-NEXT:    store ptr [[TMP15]], ptr [[TMP19]], align 43696// CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 43697// CHECK3-NEXT:    store ptr @.offload_sizes.23, ptr [[TMP20]], align 43698// CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 53699// CHECK3-NEXT:    store ptr @.offload_maptypes.24, ptr [[TMP21]], align 43700// CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 63701// CHECK3-NEXT:    store ptr null, ptr [[TMP22]], align 43702// CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 73703// CHECK3-NEXT:    store ptr null, ptr [[TMP23]], align 43704// CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 83705// CHECK3-NEXT:    store i64 0, ptr [[TMP24]], align 83706// CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 93707// CHECK3-NEXT:    store i64 0, ptr [[TMP25]], align 83708// CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 103709// CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP26]], align 43710// CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 113711// CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP27]], align 43712// CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 123713// CHECK3-NEXT:    store i32 0, ptr [[TMP28]], align 43714// CHECK3-NEXT:    [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l210.region_id, ptr [[KERNEL_ARGS]])3715// CHECK3-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 03716// CHECK3-NEXT:    br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]3717// CHECK3:       omp_offload.failed:3718// CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l210(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]]3719// CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]3720// CHECK3:       omp_offload.cont:3721// CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]3722// CHECK3:       omp_if.else:3723// CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l210(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]]3724// CHECK3-NEXT:    br label [[OMP_IF_END]]3725// CHECK3:       omp_if.end:3726// CHECK3-NEXT:    [[TMP31:%.*]] = load i32, ptr [[A]], align 43727// CHECK3-NEXT:    ret i32 [[TMP31]]3728//3729//3730// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l2453731// CHECK3-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {3732// CHECK3-NEXT:  entry:3733// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 43734// CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 43735// CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 43736// CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 43737// CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 43738// CHECK3-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 43739// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 43740// CHECK3-NEXT:    store i32 [[B]], ptr [[B_ADDR]], align 43741// CHECK3-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 43742// CHECK3-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 43743// CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 43744// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 43745// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 43746// CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 43747// CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 43748// CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 43749// CHECK3-NEXT:    store i32 [[TMP4]], ptr [[B_CASTED]], align 43750// CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 43751// CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l245.omp_outlined, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]])3752// CHECK3-NEXT:    ret void3753//3754//3755// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l245.omp_outlined3756// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {3757// CHECK3-NEXT:  entry:3758// CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 43759// CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 43760// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 43761// CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 43762// CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 43763// CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 43764// CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 43765// CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 43766// CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 43767// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 43768// CHECK3-NEXT:    store i32 [[B]], ptr [[B_ADDR]], align 43769// CHECK3-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 43770// CHECK3-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 43771// CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 43772// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 43773// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 43774// CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 43775// CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 43776// CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 43777// CHECK3-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP4]] to double3778// CHECK3-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+003779// CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 03780// CHECK3-NEXT:    store double [[ADD]], ptr [[A]], align 43781// CHECK3-NEXT:    [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 03782// CHECK3-NEXT:    [[TMP5:%.*]] = load double, ptr [[A3]], align 43783// CHECK3-NEXT:    [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+003784// CHECK3-NEXT:    store double [[INC]], ptr [[A3]], align 43785// CHECK3-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i163786// CHECK3-NEXT:    [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]]3787// CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP6]]3788// CHECK3-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 13789// CHECK3-NEXT:    store i16 [[CONV4]], ptr [[ARRAYIDX5]], align 23790// CHECK3-NEXT:    ret void3791//3792//3793// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l2273794// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {3795// CHECK3-NEXT:  entry:3796// CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 43797// CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 43798// CHECK3-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 43799// CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 43800// CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 43801// CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 43802// CHECK3-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 43803// CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 43804// CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 43805// CHECK3-NEXT:    store i32 [[AAA]], ptr [[AAA_ADDR]], align 43806// CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 43807// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 43808// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 43809// CHECK3-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 43810// CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 43811// CHECK3-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 23812// CHECK3-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 23813// CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 43814// CHECK3-NEXT:    [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 13815// CHECK3-NEXT:    store i8 [[TMP5]], ptr [[AAA_CASTED]], align 13816// CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[AAA_CASTED]], align 43817// CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l227.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], ptr [[TMP0]])3818// CHECK3-NEXT:    ret void3819//3820//3821// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l227.omp_outlined3822// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {3823// CHECK3-NEXT:  entry:3824// CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 43825// CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 43826// CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 43827// CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 43828// CHECK3-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 43829// CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 43830// CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 43831// CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 43832// CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 43833// CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 43834// CHECK3-NEXT:    store i32 [[AAA]], ptr [[AAA_ADDR]], align 43835// CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 43836// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 43837// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 43838// CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 13839// CHECK3-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 43840// CHECK3-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 23841// CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i323842// CHECK3-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 13843// CHECK3-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i163844// CHECK3-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 23845// CHECK3-NEXT:    [[TMP3:%.*]] = load i8, ptr [[AAA_ADDR]], align 13846// CHECK3-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP3]] to i323847// CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 13848// CHECK3-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i83849// CHECK3-NEXT:    store i8 [[CONV5]], ptr [[AAA_ADDR]], align 13850// CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 23851// CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX]], align 43852// CHECK3-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP4]], 13853// CHECK3-NEXT:    store i32 [[ADD6]], ptr [[ARRAYIDX]], align 43854// CHECK3-NEXT:    ret void3855//3856//3857// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l2103858// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {3859// CHECK3-NEXT:  entry:3860// CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 43861// CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 43862// CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 43863// CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 43864// CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 43865// CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 43866// CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 43867// CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 43868// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 43869// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 43870// CHECK3-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 43871// CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 43872// CHECK3-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 23873// CHECK3-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 23874// CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 43875// CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l210.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]])3876// CHECK3-NEXT:    ret void3877//3878//3879// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l210.omp_outlined3880// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {3881// CHECK3-NEXT:  entry:3882// CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 43883// CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 43884// CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 43885// CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 43886// CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 43887// CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 43888// CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 43889// CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 43890// CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 43891// CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 43892// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 43893// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 43894// CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 13895// CHECK3-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 43896// CHECK3-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 23897// CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i323898// CHECK3-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 13899// CHECK3-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i163900// CHECK3-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 23901// CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 23902// CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 43903// CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 13904// CHECK3-NEXT:    store i32 [[ADD3]], ptr [[ARRAYIDX]], align 43905// CHECK3-NEXT:    ret void3906//3907//3908// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1013909// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {3910// CHECK9-NEXT:  entry:3911// CHECK9-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 83912// CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 83913// CHECK9-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 83914// CHECK9-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 83915// CHECK9-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 83916// CHECK9-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])3917// CHECK9-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 83918// CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 83919// CHECK9-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 83920// CHECK9-NEXT:    store i64 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 83921// CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 43922// CHECK9-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 43923// CHECK9-NEXT:    call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])3924// CHECK9-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 23925// CHECK9-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 23926// CHECK9-NEXT:    [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 83927// CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined, i64 [[TMP4]])3928// CHECK9-NEXT:    ret void3929//3930//3931// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined3932// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {3933// CHECK9-NEXT:  entry:3934// CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 83935// CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 83936// CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 83937// CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 83938// CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 83939// CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 83940// CHECK9-NEXT:    ret void3941//3942//3943// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1113944// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {3945// CHECK9-NEXT:  entry:3946// CHECK9-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 83947// CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 83948// CHECK9-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 83949// CHECK9-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 83950// CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 83951// CHECK9-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 23952// CHECK9-NEXT:    store i16 [[TMP0]], ptr [[AA_CASTED]], align 23953// CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 83954// CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i64 [[TMP1]])3955// CHECK9-NEXT:    ret void3956//3957//3958// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined3959// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {3960// CHECK9-NEXT:  entry:3961// CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 83962// CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 83963// CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 83964// CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 83965// CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 83966// CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 83967// CHECK9-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 23968// CHECK9-NEXT:    [[CONV:%.*]] = sext i16 [[TMP0]] to i323969// CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 13970// CHECK9-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i163971// CHECK9-NEXT:    store i16 [[CONV1]], ptr [[AA_ADDR]], align 23972// CHECK9-NEXT:    ret void3973//3974//3975// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1183976// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {3977// CHECK9-NEXT:  entry:3978// CHECK9-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 83979// CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 83980// CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 83981// CHECK9-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 83982// CHECK9-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 83983// CHECK9-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 83984// CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 83985// CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 83986// CHECK9-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 43987// CHECK9-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 43988// CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 83989// CHECK9-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 23990// CHECK9-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 23991// CHECK9-NEXT:    [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 83992// CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i64 [[TMP1]], i64 [[TMP3]])3993// CHECK9-NEXT:    ret void3994//3995//3996// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined3997// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {3998// CHECK9-NEXT:  entry:3999// CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 84000// CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 84001// CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 84002// CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 84003// CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 84004// CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 84005// CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 84006// CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 84007// CHECK9-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 44008// CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 14009// CHECK9-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 44010// CHECK9-NEXT:    [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 24011// CHECK9-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i324012// CHECK9-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 14013// CHECK9-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i164014// CHECK9-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 24015// CHECK9-NEXT:    ret void4016//4017//4018// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1244019// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {4020// CHECK9-NEXT:  entry:4021// CHECK9-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 84022// CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 84023// CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 84024// CHECK9-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 84025// CHECK9-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 84026// CHECK9-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])4027// CHECK9-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 84028// CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 84029// CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 84030// CHECK9-NEXT:    call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 1)4031// CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 44032// CHECK9-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 44033// CHECK9-NEXT:    [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 84034// CHECK9-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 24035// CHECK9-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 24036// CHECK9-NEXT:    [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 84037// CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124.omp_outlined, i64 [[TMP2]], i64 [[TMP4]])4038// CHECK9-NEXT:    ret void4039//4040//4041// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124.omp_outlined4042// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {4043// CHECK9-NEXT:  entry:4044// CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 84045// CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 84046// CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 84047// CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 84048// CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 84049// CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 84050// CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 84051// CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 84052// CHECK9-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 44053// CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 14054// CHECK9-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 44055// CHECK9-NEXT:    [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 24056// CHECK9-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i324057// CHECK9-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 14058// CHECK9-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i164059// CHECK9-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 24060// CHECK9-NEXT:    ret void4061//4062//4063// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1304064// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {4065// CHECK9-NEXT:  entry:4066// CHECK9-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 84067// CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 84068// CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 84069// CHECK9-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 84070// CHECK9-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 84071// CHECK9-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])4072// CHECK9-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 84073// CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 84074// CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 84075// CHECK9-NEXT:    call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 1)4076// CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 44077// CHECK9-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 44078// CHECK9-NEXT:    [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 84079// CHECK9-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 24080// CHECK9-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 24081// CHECK9-NEXT:    [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 84082// CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l130.omp_outlined, i64 [[TMP2]], i64 [[TMP4]])4083// CHECK9-NEXT:    ret void4084//4085//4086// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l130.omp_outlined4087// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {4088// CHECK9-NEXT:  entry:4089// CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 84090// CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 84091// CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 84092// CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 84093// CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 84094// CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 84095// CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 84096// CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 84097// CHECK9-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 44098// CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 14099// CHECK9-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 44100// CHECK9-NEXT:    [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 24101// CHECK9-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i324102// CHECK9-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 14103// CHECK9-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i164104// CHECK9-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 24105// CHECK9-NEXT:    ret void4106//4107//4108// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1364109// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {4110// CHECK9-NEXT:  entry:4111// CHECK9-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 84112// CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 84113// CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 84114// CHECK9-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 84115// CHECK9-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 84116// CHECK9-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])4117// CHECK9-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 84118// CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 84119// CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 84120// CHECK9-NEXT:    call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 1)4121// CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 44122// CHECK9-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 44123// CHECK9-NEXT:    [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 84124// CHECK9-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 24125// CHECK9-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 24126// CHECK9-NEXT:    [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 84127// CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined, i64 [[TMP2]], i64 [[TMP4]])4128// CHECK9-NEXT:    ret void4129//4130//4131// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined4132// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {4133// CHECK9-NEXT:  entry:4134// CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 84135// CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 84136// CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 84137// CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 84138// CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 84139// CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 84140// CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 84141// CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 84142// CHECK9-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 44143// CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 14144// CHECK9-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 44145// CHECK9-NEXT:    [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 24146// CHECK9-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i324147// CHECK9-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 14148// CHECK9-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i164149// CHECK9-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 24150// CHECK9-NEXT:    ret void4151//4152//4153// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1604154// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {4155// CHECK9-NEXT:  entry:4156// CHECK9-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 84157// CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 84158// CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 84159// CHECK9-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 84160// CHECK9-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 84161// CHECK9-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 84162// CHECK9-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 84163// CHECK9-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 84164// CHECK9-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 84165// CHECK9-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 84166// CHECK9-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 84167// CHECK9-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 84168// CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 84169// CHECK9-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 84170// CHECK9-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 84171// CHECK9-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 84172// CHECK9-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 84173// CHECK9-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 84174// CHECK9-NEXT:    store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 84175// CHECK9-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 84176// CHECK9-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 84177// CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 84178// CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 84179// CHECK9-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 84180// CHECK9-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 84181// CHECK9-NEXT:    [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 84182// CHECK9-NEXT:    [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 84183// CHECK9-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 84184// CHECK9-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 84185// CHECK9-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 44186// CHECK9-NEXT:    store i32 [[TMP8]], ptr [[A_CASTED]], align 44187// CHECK9-NEXT:    [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 84188// CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]])4189// CHECK9-NEXT:    ret void4190//4191//4192// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined4193// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {4194// CHECK9-NEXT:  entry:4195// CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 84196// CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 84197// CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 84198// CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 84199// CHECK9-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 84200// CHECK9-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 84201// CHECK9-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 84202// CHECK9-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 84203// CHECK9-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 84204// CHECK9-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 84205// CHECK9-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 84206// CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 84207// CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 84208// CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 84209// CHECK9-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 84210// CHECK9-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 84211// CHECK9-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 84212// CHECK9-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 84213// CHECK9-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 84214// CHECK9-NEXT:    store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 84215// CHECK9-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 84216// CHECK9-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 84217// CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 84218// CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 84219// CHECK9-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 84220// CHECK9-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 84221// CHECK9-NEXT:    [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 84222// CHECK9-NEXT:    [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 84223// CHECK9-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 84224// CHECK9-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 84225// CHECK9-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 44226// CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP8]], 14227// CHECK9-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 44228// CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 24229// CHECK9-NEXT:    [[TMP9:%.*]] = load float, ptr [[ARRAYIDX]], align 44230// CHECK9-NEXT:    [[CONV:%.*]] = fpext float [[TMP9]] to double4231// CHECK9-NEXT:    [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+004232// CHECK9-NEXT:    [[CONV6:%.*]] = fptrunc double [[ADD5]] to float4233// CHECK9-NEXT:    store float [[CONV6]], ptr [[ARRAYIDX]], align 44234// CHECK9-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 34235// CHECK9-NEXT:    [[TMP10:%.*]] = load float, ptr [[ARRAYIDX7]], align 44236// CHECK9-NEXT:    [[CONV8:%.*]] = fpext float [[TMP10]] to double4237// CHECK9-NEXT:    [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+004238// CHECK9-NEXT:    [[CONV10:%.*]] = fptrunc double [[ADD9]] to float4239// CHECK9-NEXT:    store float [[CONV10]], ptr [[ARRAYIDX7]], align 44240// CHECK9-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 14241// CHECK9-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX11]], i64 0, i64 24242// CHECK9-NEXT:    [[TMP11:%.*]] = load double, ptr [[ARRAYIDX12]], align 84243// CHECK9-NEXT:    [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+004244// CHECK9-NEXT:    store double [[ADD13]], ptr [[ARRAYIDX12]], align 84245// CHECK9-NEXT:    [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]]4246// CHECK9-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP12]]4247// CHECK9-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i64 34248// CHECK9-NEXT:    [[TMP13:%.*]] = load double, ptr [[ARRAYIDX15]], align 84249// CHECK9-NEXT:    [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+004250// CHECK9-NEXT:    store double [[ADD16]], ptr [[ARRAYIDX15]], align 84251// CHECK9-NEXT:    [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 04252// CHECK9-NEXT:    [[TMP14:%.*]] = load i64, ptr [[X]], align 84253// CHECK9-NEXT:    [[ADD17:%.*]] = add nsw i64 [[TMP14]], 14254// CHECK9-NEXT:    store i64 [[ADD17]], ptr [[X]], align 84255// CHECK9-NEXT:    [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 14256// CHECK9-NEXT:    [[TMP15:%.*]] = load i8, ptr [[Y]], align 84257// CHECK9-NEXT:    [[CONV18:%.*]] = sext i8 [[TMP15]] to i324258// CHECK9-NEXT:    [[ADD19:%.*]] = add nsw i32 [[CONV18]], 14259// CHECK9-NEXT:    [[CONV20:%.*]] = trunc i32 [[ADD19]] to i84260// CHECK9-NEXT:    store i8 [[CONV20]], ptr [[Y]], align 84261// CHECK9-NEXT:    ret void4262//4263//4264// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1724265// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] {4266// CHECK9-NEXT:  entry:4267// CHECK9-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 84268// CHECK9-NEXT:    [[NN_ADDR:%.*]] = alloca i64, align 84269// CHECK9-NEXT:    [[NN_CASTED:%.*]] = alloca i64, align 84270// CHECK9-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 84271// CHECK9-NEXT:    store i64 [[NN]], ptr [[NN_ADDR]], align 84272// CHECK9-NEXT:    [[TMP0:%.*]] = load i32, ptr [[NN_ADDR]], align 44273// CHECK9-NEXT:    store i32 [[TMP0]], ptr [[NN_CASTED]], align 44274// CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[NN_CASTED]], align 84275// CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172.omp_outlined, i64 [[TMP1]])4276// CHECK9-NEXT:    ret void4277//4278//4279// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172.omp_outlined4280// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] {4281// CHECK9-NEXT:  entry:4282// CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 84283// CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 84284// CHECK9-NEXT:    [[NN_ADDR:%.*]] = alloca i64, align 84285// CHECK9-NEXT:    [[NN_CASTED:%.*]] = alloca i64, align 84286// CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 84287// CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 84288// CHECK9-NEXT:    store i64 [[NN]], ptr [[NN_ADDR]], align 84289// CHECK9-NEXT:    [[TMP0:%.*]] = load i32, ptr [[NN_ADDR]], align 44290// CHECK9-NEXT:    store i32 [[TMP0]], ptr [[NN_CASTED]], align 44291// CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[NN_CASTED]], align 84292// CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172.omp_outlined.omp_outlined, i64 [[TMP1]])4293// CHECK9-NEXT:    ret void4294//4295//4296// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172.omp_outlined.omp_outlined4297// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] {4298// CHECK9-NEXT:  entry:4299// CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 84300// CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 84301// CHECK9-NEXT:    [[NN_ADDR:%.*]] = alloca i64, align 84302// CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 84303// CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 84304// CHECK9-NEXT:    store i64 [[NN]], ptr [[NN_ADDR]], align 84305// CHECK9-NEXT:    ret void4306//4307//4308// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1754309// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] {4310// CHECK9-NEXT:  entry:4311// CHECK9-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 84312// CHECK9-NEXT:    [[NN_ADDR:%.*]] = alloca i64, align 84313// CHECK9-NEXT:    [[NN_CASTED:%.*]] = alloca i64, align 84314// CHECK9-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 84315// CHECK9-NEXT:    store i64 [[NN]], ptr [[NN_ADDR]], align 84316// CHECK9-NEXT:    [[TMP0:%.*]] = load i32, ptr [[NN_ADDR]], align 44317// CHECK9-NEXT:    store i32 [[TMP0]], ptr [[NN_CASTED]], align 44318// CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[NN_CASTED]], align 84319// CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175.omp_outlined, i64 [[TMP1]])4320// CHECK9-NEXT:    ret void4321//4322//4323// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175.omp_outlined4324// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] {4325// CHECK9-NEXT:  entry:4326// CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 84327// CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 84328// CHECK9-NEXT:    [[NN_ADDR:%.*]] = alloca i64, align 84329// CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 84330// CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 84331// CHECK9-NEXT:    store i64 [[NN]], ptr [[NN_ADDR]], align 84332// CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175.omp_outlined.omp_outlined, ptr [[NN_ADDR]])4333// CHECK9-NEXT:    ret void4334//4335//4336// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175.omp_outlined.omp_outlined4337// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] {4338// CHECK9-NEXT:  entry:4339// CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 84340// CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 84341// CHECK9-NEXT:    [[NN_ADDR:%.*]] = alloca ptr, align 84342// CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 84343// CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 84344// CHECK9-NEXT:    store ptr [[NN]], ptr [[NN_ADDR]], align 84345// CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[NN_ADDR]], align 84346// CHECK9-NEXT:    ret void4347//4348//4349// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l2004350// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR0]] {4351// CHECK9-NEXT:  entry:4352// CHECK9-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 84353// CHECK9-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 84354// CHECK9-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 84355// CHECK9-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 84356// CHECK9-NEXT:    [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 84357// CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l200.omp_outlined, i64 [[TMP0]])4358// CHECK9-NEXT:    ret void4359//4360//4361// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l200.omp_outlined4362// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR0]] {4363// CHECK9-NEXT:  entry:4364// CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 84365// CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 84366// CHECK9-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 84367// CHECK9-NEXT:    [[F:%.*]] = alloca ptr, align 84368// CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 84369// CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 84370// CHECK9-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 84371// CHECK9-NEXT:    [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 84372// CHECK9-NEXT:    ret void4373//4374//4375// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l2274376// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {4377// CHECK9-NEXT:  entry:4378// CHECK9-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 84379// CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 84380// CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 84381// CHECK9-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 84382// CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 84383// CHECK9-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 84384// CHECK9-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 84385// CHECK9-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 84386// CHECK9-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 84387// CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 84388// CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 84389// CHECK9-NEXT:    store i64 [[AAA]], ptr [[AAA_ADDR]], align 84390// CHECK9-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 84391// CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 84392// CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 44393// CHECK9-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 44394// CHECK9-NEXT:    [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 84395// CHECK9-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 24396// CHECK9-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 24397// CHECK9-NEXT:    [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 84398// CHECK9-NEXT:    [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 14399// CHECK9-NEXT:    store i8 [[TMP5]], ptr [[AAA_CASTED]], align 14400// CHECK9-NEXT:    [[TMP6:%.*]] = load i64, ptr [[AAA_CASTED]], align 84401// CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l227.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], ptr [[TMP0]])4402// CHECK9-NEXT:    ret void4403//4404//4405// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l227.omp_outlined4406// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {4407// CHECK9-NEXT:  entry:4408// CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 84409// CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 84410// CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 84411// CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 84412// CHECK9-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 84413// CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 84414// CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 84415// CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 84416// CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 84417// CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 84418// CHECK9-NEXT:    store i64 [[AAA]], ptr [[AAA_ADDR]], align 84419// CHECK9-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 84420// CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 84421// CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 44422// CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 14423// CHECK9-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 44424// CHECK9-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 24425// CHECK9-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i324426// CHECK9-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 14427// CHECK9-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i164428// CHECK9-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 24429// CHECK9-NEXT:    [[TMP3:%.*]] = load i8, ptr [[AAA_ADDR]], align 14430// CHECK9-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP3]] to i324431// CHECK9-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 14432// CHECK9-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i84433// CHECK9-NEXT:    store i8 [[CONV5]], ptr [[AAA_ADDR]], align 14434// CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 24435// CHECK9-NEXT:    [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX]], align 44436// CHECK9-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP4]], 14437// CHECK9-NEXT:    store i32 [[ADD6]], ptr [[ARRAYIDX]], align 44438// CHECK9-NEXT:    ret void4439//4440//4441// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l2454442// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {4443// CHECK9-NEXT:  entry:4444// CHECK9-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 84445// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 84446// CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 84447// CHECK9-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 84448// CHECK9-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 84449// CHECK9-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 84450// CHECK9-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 84451// CHECK9-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 84452// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 84453// CHECK9-NEXT:    store i64 [[B]], ptr [[B_ADDR]], align 84454// CHECK9-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 84455// CHECK9-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 84456// CHECK9-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 84457// CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 84458// CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 84459// CHECK9-NEXT:    [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 84460// CHECK9-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 84461// CHECK9-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 44462// CHECK9-NEXT:    store i32 [[TMP4]], ptr [[B_CASTED]], align 44463// CHECK9-NEXT:    [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 84464// CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l245.omp_outlined, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]])4465// CHECK9-NEXT:    ret void4466//4467//4468// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l245.omp_outlined4469// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {4470// CHECK9-NEXT:  entry:4471// CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 84472// CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 84473// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 84474// CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 84475// CHECK9-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 84476// CHECK9-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 84477// CHECK9-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 84478// CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 84479// CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 84480// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 84481// CHECK9-NEXT:    store i64 [[B]], ptr [[B_ADDR]], align 84482// CHECK9-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 84483// CHECK9-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 84484// CHECK9-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 84485// CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 84486// CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 84487// CHECK9-NEXT:    [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 84488// CHECK9-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 84489// CHECK9-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 44490// CHECK9-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP4]] to double4491// CHECK9-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+004492// CHECK9-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 04493// CHECK9-NEXT:    store double [[ADD]], ptr [[A]], align 84494// CHECK9-NEXT:    [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 04495// CHECK9-NEXT:    [[TMP5:%.*]] = load double, ptr [[A3]], align 84496// CHECK9-NEXT:    [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+004497// CHECK9-NEXT:    store double [[INC]], ptr [[A3]], align 84498// CHECK9-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i164499// CHECK9-NEXT:    [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]]4500// CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP6]]4501// CHECK9-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 14502// CHECK9-NEXT:    store i16 [[CONV4]], ptr [[ARRAYIDX5]], align 24503// CHECK9-NEXT:    ret void4504//4505//4506// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l2104507// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {4508// CHECK9-NEXT:  entry:4509// CHECK9-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 84510// CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 84511// CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 84512// CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 84513// CHECK9-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 84514// CHECK9-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 84515// CHECK9-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 84516// CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 84517// CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 84518// CHECK9-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 84519// CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 84520// CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 44521// CHECK9-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 44522// CHECK9-NEXT:    [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 84523// CHECK9-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 24524// CHECK9-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 24525// CHECK9-NEXT:    [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 84526// CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l210.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]])4527// CHECK9-NEXT:    ret void4528//4529//4530// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l210.omp_outlined4531// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {4532// CHECK9-NEXT:  entry:4533// CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 84534// CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 84535// CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 84536// CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 84537// CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 84538// CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 84539// CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 84540// CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 84541// CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 84542// CHECK9-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 84543// CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 84544// CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 44545// CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 14546// CHECK9-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 44547// CHECK9-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 24548// CHECK9-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i324549// CHECK9-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 14550// CHECK9-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i164551// CHECK9-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 24552// CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 24553// CHECK9-NEXT:    [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 44554// CHECK9-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 14555// CHECK9-NEXT:    store i32 [[ADD3]], ptr [[ARRAYIDX]], align 44556// CHECK9-NEXT:    ret void4557//4558//4559// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1014560// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {4561// CHECK11-NEXT:  entry:4562// CHECK11-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 44563// CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 44564// CHECK11-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 44565// CHECK11-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 44566// CHECK11-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 44567// CHECK11-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])4568// CHECK11-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 44569// CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 44570// CHECK11-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 44571// CHECK11-NEXT:    store i32 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 44572// CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 44573// CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 44574// CHECK11-NEXT:    call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])4575// CHECK11-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 24576// CHECK11-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 24577// CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 44578// CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined, i32 [[TMP4]])4579// CHECK11-NEXT:    ret void4580//4581//4582// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined4583// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {4584// CHECK11-NEXT:  entry:4585// CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 44586// CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 44587// CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 44588// CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 44589// CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 44590// CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 44591// CHECK11-NEXT:    ret void4592//4593//4594// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1114595// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {4596// CHECK11-NEXT:  entry:4597// CHECK11-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 44598// CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 44599// CHECK11-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 44600// CHECK11-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 44601// CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 44602// CHECK11-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 24603// CHECK11-NEXT:    store i16 [[TMP0]], ptr [[AA_CASTED]], align 24604// CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 44605// CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i32 [[TMP1]])4606// CHECK11-NEXT:    ret void4607//4608//4609// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined4610// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {4611// CHECK11-NEXT:  entry:4612// CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 44613// CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 44614// CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 44615// CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 44616// CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 44617// CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 44618// CHECK11-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 24619// CHECK11-NEXT:    [[CONV:%.*]] = sext i16 [[TMP0]] to i324620// CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 14621// CHECK11-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i164622// CHECK11-NEXT:    store i16 [[CONV1]], ptr [[AA_ADDR]], align 24623// CHECK11-NEXT:    ret void4624//4625//4626// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1184627// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {4628// CHECK11-NEXT:  entry:4629// CHECK11-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 44630// CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 44631// CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 44632// CHECK11-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 44633// CHECK11-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 44634// CHECK11-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 44635// CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 44636// CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 44637// CHECK11-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 44638// CHECK11-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 44639// CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 44640// CHECK11-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 24641// CHECK11-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 24642// CHECK11-NEXT:    [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 44643// CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i32 [[TMP1]], i32 [[TMP3]])4644// CHECK11-NEXT:    ret void4645//4646//4647// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined4648// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {4649// CHECK11-NEXT:  entry:4650// CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 44651// CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 44652// CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 44653// CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 44654// CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 44655// CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 44656// CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 44657// CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 44658// CHECK11-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 44659// CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 14660// CHECK11-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 44661// CHECK11-NEXT:    [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 24662// CHECK11-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i324663// CHECK11-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 14664// CHECK11-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i164665// CHECK11-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 24666// CHECK11-NEXT:    ret void4667//4668//4669// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1244670// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {4671// CHECK11-NEXT:  entry:4672// CHECK11-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 44673// CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 44674// CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 44675// CHECK11-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 44676// CHECK11-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 44677// CHECK11-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])4678// CHECK11-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 44679// CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 44680// CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 44681// CHECK11-NEXT:    call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 1)4682// CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 44683// CHECK11-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 44684// CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 44685// CHECK11-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 24686// CHECK11-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 24687// CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 44688// CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124.omp_outlined, i32 [[TMP2]], i32 [[TMP4]])4689// CHECK11-NEXT:    ret void4690//4691//4692// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124.omp_outlined4693// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {4694// CHECK11-NEXT:  entry:4695// CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 44696// CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 44697// CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 44698// CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 44699// CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 44700// CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 44701// CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 44702// CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 44703// CHECK11-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 44704// CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 14705// CHECK11-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 44706// CHECK11-NEXT:    [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 24707// CHECK11-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i324708// CHECK11-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 14709// CHECK11-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i164710// CHECK11-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 24711// CHECK11-NEXT:    ret void4712//4713//4714// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1304715// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {4716// CHECK11-NEXT:  entry:4717// CHECK11-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 44718// CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 44719// CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 44720// CHECK11-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 44721// CHECK11-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 44722// CHECK11-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])4723// CHECK11-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 44724// CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 44725// CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 44726// CHECK11-NEXT:    call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 1)4727// CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 44728// CHECK11-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 44729// CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 44730// CHECK11-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 24731// CHECK11-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 24732// CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 44733// CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l130.omp_outlined, i32 [[TMP2]], i32 [[TMP4]])4734// CHECK11-NEXT:    ret void4735//4736//4737// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l130.omp_outlined4738// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {4739// CHECK11-NEXT:  entry:4740// CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 44741// CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 44742// CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 44743// CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 44744// CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 44745// CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 44746// CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 44747// CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 44748// CHECK11-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 44749// CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 14750// CHECK11-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 44751// CHECK11-NEXT:    [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 24752// CHECK11-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i324753// CHECK11-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 14754// CHECK11-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i164755// CHECK11-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 24756// CHECK11-NEXT:    ret void4757//4758//4759// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1364760// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {4761// CHECK11-NEXT:  entry:4762// CHECK11-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 44763// CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 44764// CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 44765// CHECK11-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 44766// CHECK11-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 44767// CHECK11-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])4768// CHECK11-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 44769// CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 44770// CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 44771// CHECK11-NEXT:    call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 1)4772// CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 44773// CHECK11-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 44774// CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 44775// CHECK11-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 24776// CHECK11-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 24777// CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 44778// CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined, i32 [[TMP2]], i32 [[TMP4]])4779// CHECK11-NEXT:    ret void4780//4781//4782// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined4783// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {4784// CHECK11-NEXT:  entry:4785// CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 44786// CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 44787// CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 44788// CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 44789// CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 44790// CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 44791// CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 44792// CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 44793// CHECK11-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 44794// CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 14795// CHECK11-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 44796// CHECK11-NEXT:    [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 24797// CHECK11-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i324798// CHECK11-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 14799// CHECK11-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i164800// CHECK11-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 24801// CHECK11-NEXT:    ret void4802//4803//4804// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1604805// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {4806// CHECK11-NEXT:  entry:4807// CHECK11-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 44808// CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 44809// CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 44810// CHECK11-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 44811// CHECK11-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 44812// CHECK11-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 44813// CHECK11-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 44814// CHECK11-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 44815// CHECK11-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 44816// CHECK11-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 44817// CHECK11-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 44818// CHECK11-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 44819// CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 44820// CHECK11-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 44821// CHECK11-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 44822// CHECK11-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 44823// CHECK11-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 44824// CHECK11-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 44825// CHECK11-NEXT:    store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 44826// CHECK11-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 44827// CHECK11-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 44828// CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 44829// CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 44830// CHECK11-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 44831// CHECK11-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 44832// CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 44833// CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 44834// CHECK11-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 44835// CHECK11-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 44836// CHECK11-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 44837// CHECK11-NEXT:    store i32 [[TMP8]], ptr [[A_CASTED]], align 44838// CHECK11-NEXT:    [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 44839// CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]])4840// CHECK11-NEXT:    ret void4841//4842//4843// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined4844// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {4845// CHECK11-NEXT:  entry:4846// CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 44847// CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 44848// CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 44849// CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 44850// CHECK11-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 44851// CHECK11-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 44852// CHECK11-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 44853// CHECK11-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 44854// CHECK11-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 44855// CHECK11-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 44856// CHECK11-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 44857// CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 44858// CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 44859// CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 44860// CHECK11-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 44861// CHECK11-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 44862// CHECK11-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 44863// CHECK11-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 44864// CHECK11-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 44865// CHECK11-NEXT:    store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 44866// CHECK11-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 44867// CHECK11-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 44868// CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 44869// CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 44870// CHECK11-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 44871// CHECK11-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 44872// CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 44873// CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 44874// CHECK11-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 44875// CHECK11-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 44876// CHECK11-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 44877// CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP8]], 14878// CHECK11-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 44879// CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 24880// CHECK11-NEXT:    [[TMP9:%.*]] = load float, ptr [[ARRAYIDX]], align 44881// CHECK11-NEXT:    [[CONV:%.*]] = fpext float [[TMP9]] to double4882// CHECK11-NEXT:    [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+004883// CHECK11-NEXT:    [[CONV6:%.*]] = fptrunc double [[ADD5]] to float4884// CHECK11-NEXT:    store float [[CONV6]], ptr [[ARRAYIDX]], align 44885// CHECK11-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 34886// CHECK11-NEXT:    [[TMP10:%.*]] = load float, ptr [[ARRAYIDX7]], align 44887// CHECK11-NEXT:    [[CONV8:%.*]] = fpext float [[TMP10]] to double4888// CHECK11-NEXT:    [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+004889// CHECK11-NEXT:    [[CONV10:%.*]] = fptrunc double [[ADD9]] to float4890// CHECK11-NEXT:    store float [[CONV10]], ptr [[ARRAYIDX7]], align 44891// CHECK11-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 14892// CHECK11-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX11]], i32 0, i32 24893// CHECK11-NEXT:    [[TMP11:%.*]] = load double, ptr [[ARRAYIDX12]], align 84894// CHECK11-NEXT:    [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+004895// CHECK11-NEXT:    store double [[ADD13]], ptr [[ARRAYIDX12]], align 84896// CHECK11-NEXT:    [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]]4897// CHECK11-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP12]]4898// CHECK11-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i32 34899// CHECK11-NEXT:    [[TMP13:%.*]] = load double, ptr [[ARRAYIDX15]], align 84900// CHECK11-NEXT:    [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+004901// CHECK11-NEXT:    store double [[ADD16]], ptr [[ARRAYIDX15]], align 84902// CHECK11-NEXT:    [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 04903// CHECK11-NEXT:    [[TMP14:%.*]] = load i64, ptr [[X]], align 44904// CHECK11-NEXT:    [[ADD17:%.*]] = add nsw i64 [[TMP14]], 14905// CHECK11-NEXT:    store i64 [[ADD17]], ptr [[X]], align 44906// CHECK11-NEXT:    [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 14907// CHECK11-NEXT:    [[TMP15:%.*]] = load i8, ptr [[Y]], align 44908// CHECK11-NEXT:    [[CONV18:%.*]] = sext i8 [[TMP15]] to i324909// CHECK11-NEXT:    [[ADD19:%.*]] = add nsw i32 [[CONV18]], 14910// CHECK11-NEXT:    [[CONV20:%.*]] = trunc i32 [[ADD19]] to i84911// CHECK11-NEXT:    store i8 [[CONV20]], ptr [[Y]], align 44912// CHECK11-NEXT:    ret void4913//4914//4915// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1724916// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] {4917// CHECK11-NEXT:  entry:4918// CHECK11-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 44919// CHECK11-NEXT:    [[NN_ADDR:%.*]] = alloca i32, align 44920// CHECK11-NEXT:    [[NN_CASTED:%.*]] = alloca i32, align 44921// CHECK11-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 44922// CHECK11-NEXT:    store i32 [[NN]], ptr [[NN_ADDR]], align 44923// CHECK11-NEXT:    [[TMP0:%.*]] = load i32, ptr [[NN_ADDR]], align 44924// CHECK11-NEXT:    store i32 [[TMP0]], ptr [[NN_CASTED]], align 44925// CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[NN_CASTED]], align 44926// CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172.omp_outlined, i32 [[TMP1]])4927// CHECK11-NEXT:    ret void4928//4929//4930// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172.omp_outlined4931// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] {4932// CHECK11-NEXT:  entry:4933// CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 44934// CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 44935// CHECK11-NEXT:    [[NN_ADDR:%.*]] = alloca i32, align 44936// CHECK11-NEXT:    [[NN_CASTED:%.*]] = alloca i32, align 44937// CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 44938// CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 44939// CHECK11-NEXT:    store i32 [[NN]], ptr [[NN_ADDR]], align 44940// CHECK11-NEXT:    [[TMP0:%.*]] = load i32, ptr [[NN_ADDR]], align 44941// CHECK11-NEXT:    store i32 [[TMP0]], ptr [[NN_CASTED]], align 44942// CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[NN_CASTED]], align 44943// CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172.omp_outlined.omp_outlined, i32 [[TMP1]])4944// CHECK11-NEXT:    ret void4945//4946//4947// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172.omp_outlined.omp_outlined4948// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] {4949// CHECK11-NEXT:  entry:4950// CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 44951// CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 44952// CHECK11-NEXT:    [[NN_ADDR:%.*]] = alloca i32, align 44953// CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 44954// CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 44955// CHECK11-NEXT:    store i32 [[NN]], ptr [[NN_ADDR]], align 44956// CHECK11-NEXT:    ret void4957//4958//4959// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1754960// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] {4961// CHECK11-NEXT:  entry:4962// CHECK11-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 44963// CHECK11-NEXT:    [[NN_ADDR:%.*]] = alloca i32, align 44964// CHECK11-NEXT:    [[NN_CASTED:%.*]] = alloca i32, align 44965// CHECK11-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 44966// CHECK11-NEXT:    store i32 [[NN]], ptr [[NN_ADDR]], align 44967// CHECK11-NEXT:    [[TMP0:%.*]] = load i32, ptr [[NN_ADDR]], align 44968// CHECK11-NEXT:    store i32 [[TMP0]], ptr [[NN_CASTED]], align 44969// CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[NN_CASTED]], align 44970// CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175.omp_outlined, i32 [[TMP1]])4971// CHECK11-NEXT:    ret void4972//4973//4974// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175.omp_outlined4975// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] {4976// CHECK11-NEXT:  entry:4977// CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 44978// CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 44979// CHECK11-NEXT:    [[NN_ADDR:%.*]] = alloca i32, align 44980// CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 44981// CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 44982// CHECK11-NEXT:    store i32 [[NN]], ptr [[NN_ADDR]], align 44983// CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175.omp_outlined.omp_outlined, ptr [[NN_ADDR]])4984// CHECK11-NEXT:    ret void4985//4986//4987// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175.omp_outlined.omp_outlined4988// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] {4989// CHECK11-NEXT:  entry:4990// CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 44991// CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 44992// CHECK11-NEXT:    [[NN_ADDR:%.*]] = alloca ptr, align 44993// CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 44994// CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 44995// CHECK11-NEXT:    store ptr [[NN]], ptr [[NN_ADDR]], align 44996// CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[NN_ADDR]], align 44997// CHECK11-NEXT:    ret void4998//4999//5000// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l2005001// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[VLA:%.*]]) #[[ATTR0]] {5002// CHECK11-NEXT:  entry:5003// CHECK11-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 45004// CHECK11-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 45005// CHECK11-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 45006// CHECK11-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 45007// CHECK11-NEXT:    [[TMP0:%.*]] = load i32, ptr [[VLA_ADDR]], align 45008// CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l200.omp_outlined, i32 [[TMP0]])5009// CHECK11-NEXT:    ret void5010//5011//5012// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l200.omp_outlined5013// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[VLA:%.*]]) #[[ATTR0]] {5014// CHECK11-NEXT:  entry:5015// CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 45016// CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 45017// CHECK11-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 45018// CHECK11-NEXT:    [[F:%.*]] = alloca ptr, align 45019// CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 45020// CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 45021// CHECK11-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 45022// CHECK11-NEXT:    [[TMP0:%.*]] = load i32, ptr [[VLA_ADDR]], align 45023// CHECK11-NEXT:    ret void5024//5025//5026// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l2275027// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {5028// CHECK11-NEXT:  entry:5029// CHECK11-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 45030// CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 45031// CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 45032// CHECK11-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 45033// CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 45034// CHECK11-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 45035// CHECK11-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 45036// CHECK11-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 45037// CHECK11-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 45038// CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 45039// CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 45040// CHECK11-NEXT:    store i32 [[AAA]], ptr [[AAA_ADDR]], align 45041// CHECK11-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 45042// CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 45043// CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 45044// CHECK11-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 45045// CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 45046// CHECK11-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 25047// CHECK11-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 25048// CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 45049// CHECK11-NEXT:    [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 15050// CHECK11-NEXT:    store i8 [[TMP5]], ptr [[AAA_CASTED]], align 15051// CHECK11-NEXT:    [[TMP6:%.*]] = load i32, ptr [[AAA_CASTED]], align 45052// CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l227.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], ptr [[TMP0]])5053// CHECK11-NEXT:    ret void5054//5055//5056// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l227.omp_outlined5057// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {5058// CHECK11-NEXT:  entry:5059// CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 45060// CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 45061// CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 45062// CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 45063// CHECK11-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 45064// CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 45065// CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 45066// CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 45067// CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 45068// CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 45069// CHECK11-NEXT:    store i32 [[AAA]], ptr [[AAA_ADDR]], align 45070// CHECK11-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 45071// CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 45072// CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 45073// CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 15074// CHECK11-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 45075// CHECK11-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 25076// CHECK11-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i325077// CHECK11-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 15078// CHECK11-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i165079// CHECK11-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 25080// CHECK11-NEXT:    [[TMP3:%.*]] = load i8, ptr [[AAA_ADDR]], align 15081// CHECK11-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP3]] to i325082// CHECK11-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 15083// CHECK11-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i85084// CHECK11-NEXT:    store i8 [[CONV5]], ptr [[AAA_ADDR]], align 15085// CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 25086// CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX]], align 45087// CHECK11-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP4]], 15088// CHECK11-NEXT:    store i32 [[ADD6]], ptr [[ARRAYIDX]], align 45089// CHECK11-NEXT:    ret void5090//5091//5092// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l2455093// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {5094// CHECK11-NEXT:  entry:5095// CHECK11-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 45096// CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 45097// CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 45098// CHECK11-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 45099// CHECK11-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 45100// CHECK11-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 45101// CHECK11-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 45102// CHECK11-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 45103// CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 45104// CHECK11-NEXT:    store i32 [[B]], ptr [[B_ADDR]], align 45105// CHECK11-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 45106// CHECK11-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 45107// CHECK11-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 45108// CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 45109// CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 45110// CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 45111// CHECK11-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 45112// CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 45113// CHECK11-NEXT:    store i32 [[TMP4]], ptr [[B_CASTED]], align 45114// CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 45115// CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l245.omp_outlined, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]])5116// CHECK11-NEXT:    ret void5117//5118//5119// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l245.omp_outlined5120// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {5121// CHECK11-NEXT:  entry:5122// CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 45123// CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 45124// CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 45125// CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 45126// CHECK11-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 45127// CHECK11-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 45128// CHECK11-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 45129// CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 45130// CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 45131// CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 45132// CHECK11-NEXT:    store i32 [[B]], ptr [[B_ADDR]], align 45133// CHECK11-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 45134// CHECK11-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 45135// CHECK11-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 45136// CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 45137// CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 45138// CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 45139// CHECK11-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 45140// CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 45141// CHECK11-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP4]] to double5142// CHECK11-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+005143// CHECK11-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 05144// CHECK11-NEXT:    store double [[ADD]], ptr [[A]], align 45145// CHECK11-NEXT:    [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 05146// CHECK11-NEXT:    [[TMP5:%.*]] = load double, ptr [[A3]], align 45147// CHECK11-NEXT:    [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+005148// CHECK11-NEXT:    store double [[INC]], ptr [[A3]], align 45149// CHECK11-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i165150// CHECK11-NEXT:    [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]]5151// CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP6]]5152// CHECK11-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 15153// CHECK11-NEXT:    store i16 [[CONV4]], ptr [[ARRAYIDX5]], align 25154// CHECK11-NEXT:    ret void5155//5156//5157// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l2105158// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {5159// CHECK11-NEXT:  entry:5160// CHECK11-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 45161// CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 45162// CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 45163// CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 45164// CHECK11-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 45165// CHECK11-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 45166// CHECK11-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 45167// CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 45168// CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 45169// CHECK11-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 45170// CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 45171// CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 45172// CHECK11-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 45173// CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 45174// CHECK11-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 25175// CHECK11-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 25176// CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 45177// CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l210.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]])5178// CHECK11-NEXT:    ret void5179//5180//5181// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l210.omp_outlined5182// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {5183// CHECK11-NEXT:  entry:5184// CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 45185// CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 45186// CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 45187// CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 45188// CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 45189// CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 45190// CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 45191// CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 45192// CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 45193// CHECK11-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 45194// CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 45195// CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 45196// CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 15197// CHECK11-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 45198// CHECK11-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 25199// CHECK11-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i325200// CHECK11-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 15201// CHECK11-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i165202// CHECK11-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 25203// CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 25204// CHECK11-NEXT:    [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 45205// CHECK11-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 15206// CHECK11-NEXT:    store i32 [[ADD3]], ptr [[ARRAYIDX]], align 45207// CHECK11-NEXT:    ret void5208//5209