5414 lines · cpp
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _2// Test host codegen.3// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK14// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s5// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK16// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK37// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s8// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK39 10// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"11// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s12// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"13// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"14// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s15// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"16 17// Test target codegen - host bc file has to be created first.18// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc19// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK920// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s21// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK922// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc23// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1124// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s25// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1126 27// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc28// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"29// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s30// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"31// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc32// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"33// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s34// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"35 36// Test host codegen.37// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK138// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s39// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK140// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK341// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s42// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK343 44// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"45// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s46// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"47// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"48// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s49// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"50 51// Test target codegen - host bc file has to be created first.52// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc53// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK954// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s55// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK956// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc57// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1158// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s59// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1160 61// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc62// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"63// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s64// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"65// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc66// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"67// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s68// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"69 70// expected-no-diagnostics71#ifndef HEADER72#define HEADER73 74 75 76 77// We have 8 target regions, but only 7 that actually will generate offloading78// code, only 6 will have mapped arguments, and only 4 have all-constant map79// sizes.80 81 82 83// Check target registration is registered as a Ctor.84 85 86template<typename tx, typename ty>87struct TT{88 tx X;89 ty Y;90};91 92int global;93 94int foo(int n) {95 int a = 0;96 short aa = 0;97 float b[10];98 float bn[n];99 double c[5][10];100 double cn[5][n];101 TT<long long, char> d;102 103 #pragma omp target teams distribute num_teams(a) thread_limit(a) firstprivate(aa) nowait104 for (int i = 0; i < 10; ++i) {105 }106 107 #pragma omp target teams distribute if(target: 0)108 for (int i = 0; i < 10; ++i) {109 a += 1;110 }111 112 113 #pragma omp target teams distribute if(target: 1)114 for (int i = 0; i < 10; ++i) {115 aa += 1;116 }117 118 119 120 #pragma omp target teams distribute if(target: n>10)121 for (int i = 0; i < 10; ++i) {122 a += 1;123 aa += 1;124 }125 126 // We capture 3 VLA sizes in this target region127 128 129 130 131 132 // The names below are not necessarily consistent with the names used for the133 // addresses above as some are repeated.134 135 136 137 138 139 140 141 142 143 144 145 #pragma omp target teams distribute if(target: n>20) dist_schedule(static, n)146 for (int i = 0; i < 10; ++i) {147 a += 1;148 b[2] += 1.0;149 bn[3] += 1.0;150 c[1][2] += 1.0;151 cn[1][3] += 1.0;152 d.X += 1;153 d.Y += 1;154 }155 156 return a;157}158 159// Check that the offloading functions are emitted and that the arguments are160// correct and loaded correctly for the target regions in foo().161 162 163 164 165// Create stack storage and store argument in there.166 167// Create stack storage and store argument in there.168 169// Create stack storage and store argument in there.170 171// Create local storage for each capture.172 173 174 175// To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.176 177template<typename tx>178tx ftemplate(int n) {179 tx a = 0;180 short aa = 0;181 tx b[10];182 183 #pragma omp target teams distribute if(target: n>40)184 for (int i = 0; i < 10; ++i) {185 a += 1;186 aa += 1;187 b[2] += 1;188 }189 190 return a;191}192 193static194int fstatic(int n) {195 int a = 0;196 short aa = 0;197 char aaa = 0;198 int b[10];199 200 #pragma omp target teams distribute if(target: n>50)201 for (int i = a; i < n; ++i) {202 a += 1;203 aa += 1;204 aaa += 1;205 b[2] += 1;206 }207 208 return a;209}210 211struct S1 {212 double a;213 214 int r1(int n){215 int b = n+1;216 short int c[2][n];217 218 #pragma omp target teams distribute if(target: n>60)219 for (int i = 0; i < 10; ++i) {220 this->a = (double)b + 1.5;221 c[1][1] = ++a;222 }223 224 return c[1][1] + (int)b;225 }226};227 228int bar(int n){229 int a = 0;230 231 a += foo(n);232 233 S1 S;234 a += S.r1(n);235 236 a += fstatic(n);237 238 a += ftemplate<int>(n);239 240 return a;241}242 243 244 245// We capture 2 VLA sizes in this target region246 247 248// The names below are not necessarily consistent with the names used for the249// addresses above as some are repeated.250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271// Check that the offloading functions are emitted and that the arguments are272// correct and loaded correctly for the target regions of the callees of bar().273 274// Create local storage for each capture.275// Store captures in the context.276 277 278// To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.279 280 281// Create local storage for each capture.282// Store captures in the context.283 284 285 286 287// To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.288 289// Create local storage for each capture.290// Store captures in the context.291 292 293 294// To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.295 296#endif297// CHECK1-LABEL: define {{[^@]+}}@_Z3fooi298// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {299// CHECK1-NEXT: entry:300// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4301// CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4302// CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2303// CHECK1-NEXT: [[B:%.*]] = alloca [10 x float], align 4304// CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8305// CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8306// CHECK1-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8307// CHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8308// CHECK1-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8309// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4310// CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4311// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8312// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8313// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i64, align 8314// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8315// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8316// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8317// CHECK1-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4318// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8319// CHECK1-NEXT: [[AA_CASTED4:%.*]] = alloca i64, align 8320// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [1 x ptr], align 8321// CHECK1-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [1 x ptr], align 8322// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [1 x ptr], align 8323// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4324// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8325// CHECK1-NEXT: [[A_CASTED8:%.*]] = alloca i64, align 8326// CHECK1-NEXT: [[AA_CASTED9:%.*]] = alloca i64, align 8327// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x ptr], align 8328// CHECK1-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x ptr], align 8329// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x ptr], align 8330// CHECK1-NEXT: [[_TMP13:%.*]] = alloca i32, align 4331// CHECK1-NEXT: [[KERNEL_ARGS14:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8332// CHECK1-NEXT: [[DOTCAPTURE_EXPR_17:%.*]] = alloca i32, align 4333// CHECK1-NEXT: [[A_CASTED18:%.*]] = alloca i64, align 8334// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED19:%.*]] = alloca i64, align 8335// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS22:%.*]] = alloca [10 x ptr], align 8336// CHECK1-NEXT: [[DOTOFFLOAD_PTRS23:%.*]] = alloca [10 x ptr], align 8337// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS24:%.*]] = alloca [10 x ptr], align 8338// CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8339// CHECK1-NEXT: [[_TMP25:%.*]] = alloca i32, align 4340// CHECK1-NEXT: [[KERNEL_ARGS26:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8341// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])342// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4343// CHECK1-NEXT: store i32 0, ptr [[A]], align 4344// CHECK1-NEXT: store i16 0, ptr [[AA]], align 2345// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4346// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64347// CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()348// CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8349// CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4350// CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8351// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4352// CHECK1-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64353// CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]354// CHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8355// CHECK1-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8356// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4357// CHECK1-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 4358// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4359// CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTCAPTURE_EXPR_2]], align 4360// CHECK1-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA]], align 2361// CHECK1-NEXT: store i16 [[TMP9]], ptr [[AA_CASTED]], align 2362// CHECK1-NEXT: [[TMP10:%.*]] = load i64, ptr [[AA_CASTED]], align 8363// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4364// CHECK1-NEXT: store i32 [[TMP11]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4365// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8366// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4367// CHECK1-NEXT: store i32 [[TMP13]], ptr [[DOTCAPTURE_EXPR__CASTED3]], align 4368// CHECK1-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED3]], align 8369// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0370// CHECK1-NEXT: store i64 [[TMP10]], ptr [[TMP15]], align 8371// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0372// CHECK1-NEXT: store i64 [[TMP10]], ptr [[TMP16]], align 8373// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0374// CHECK1-NEXT: store ptr null, ptr [[TMP17]], align 8375// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1376// CHECK1-NEXT: store i64 [[TMP12]], ptr [[TMP18]], align 8377// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1378// CHECK1-NEXT: store i64 [[TMP12]], ptr [[TMP19]], align 8379// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1380// CHECK1-NEXT: store ptr null, ptr [[TMP20]], align 8381// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2382// CHECK1-NEXT: store i64 [[TMP14]], ptr [[TMP21]], align 8383// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2384// CHECK1-NEXT: store i64 [[TMP14]], ptr [[TMP22]], align 8385// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2386// CHECK1-NEXT: store ptr null, ptr [[TMP23]], align 8387// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0388// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0389// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0390// CHECK1-NEXT: [[TMP27:%.*]] = load i16, ptr [[AA]], align 2391// CHECK1-NEXT: store i16 [[TMP27]], ptr [[TMP26]], align 4392// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1393// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4394// CHECK1-NEXT: store i32 [[TMP29]], ptr [[TMP28]], align 4395// CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 2396// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4397// CHECK1-NEXT: store i32 [[TMP31]], ptr [[TMP30]], align 4398// CHECK1-NEXT: [[TMP32:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, ptr @.omp_task_entry., i64 -1)399// CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP32]], i32 0, i32 0400// CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP33]], i32 0, i32 0401// CHECK1-NEXT: [[TMP35:%.*]] = load ptr, ptr [[TMP34]], align 8402// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP35]], ptr align 4 [[AGG_CAPTURED]], i64 12, i1 false)403// CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP32]], i32 0, i32 1404// CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP36]], i32 0, i32 0405// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP37]], ptr align 8 [[TMP24]], i64 24, i1 false)406// CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP36]], i32 0, i32 1407// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP38]], ptr align 8 [[TMP25]], i64 24, i1 false)408// CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP36]], i32 0, i32 2409// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP39]], ptr align 8 @.offload_sizes, i64 24, i1 false)410// CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP36]], i32 0, i32 3411// CHECK1-NEXT: [[TMP41:%.*]] = load i16, ptr [[AA]], align 2412// CHECK1-NEXT: store i16 [[TMP41]], ptr [[TMP40]], align 8413// CHECK1-NEXT: [[TMP42:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB2]], i32 [[TMP0]], ptr [[TMP32]])414// CHECK1-NEXT: [[TMP43:%.*]] = load i32, ptr [[A]], align 4415// CHECK1-NEXT: store i32 [[TMP43]], ptr [[A_CASTED]], align 4416// CHECK1-NEXT: [[TMP44:%.*]] = load i64, ptr [[A_CASTED]], align 8417// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107(i64 [[TMP44]]) #[[ATTR3:[0-9]+]]418// CHECK1-NEXT: [[TMP45:%.*]] = load i16, ptr [[AA]], align 2419// CHECK1-NEXT: store i16 [[TMP45]], ptr [[AA_CASTED4]], align 2420// CHECK1-NEXT: [[TMP46:%.*]] = load i64, ptr [[AA_CASTED4]], align 8421// CHECK1-NEXT: [[TMP47:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0422// CHECK1-NEXT: store i64 [[TMP46]], ptr [[TMP47]], align 8423// CHECK1-NEXT: [[TMP48:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0424// CHECK1-NEXT: store i64 [[TMP46]], ptr [[TMP48]], align 8425// CHECK1-NEXT: [[TMP49:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0426// CHECK1-NEXT: store ptr null, ptr [[TMP49]], align 8427// CHECK1-NEXT: [[TMP50:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0428// CHECK1-NEXT: [[TMP51:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0429// CHECK1-NEXT: [[TMP52:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0430// CHECK1-NEXT: store i32 3, ptr [[TMP52]], align 4431// CHECK1-NEXT: [[TMP53:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1432// CHECK1-NEXT: store i32 1, ptr [[TMP53]], align 4433// CHECK1-NEXT: [[TMP54:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2434// CHECK1-NEXT: store ptr [[TMP50]], ptr [[TMP54]], align 8435// CHECK1-NEXT: [[TMP55:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3436// CHECK1-NEXT: store ptr [[TMP51]], ptr [[TMP55]], align 8437// CHECK1-NEXT: [[TMP56:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4438// CHECK1-NEXT: store ptr @.offload_sizes.1, ptr [[TMP56]], align 8439// CHECK1-NEXT: [[TMP57:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5440// CHECK1-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP57]], align 8441// CHECK1-NEXT: [[TMP58:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6442// CHECK1-NEXT: store ptr null, ptr [[TMP58]], align 8443// CHECK1-NEXT: [[TMP59:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7444// CHECK1-NEXT: store ptr null, ptr [[TMP59]], align 8445// CHECK1-NEXT: [[TMP60:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8446// CHECK1-NEXT: store i64 10, ptr [[TMP60]], align 8447// CHECK1-NEXT: [[TMP61:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9448// CHECK1-NEXT: store i64 0, ptr [[TMP61]], align 8449// CHECK1-NEXT: [[TMP62:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10450// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP62]], align 4451// CHECK1-NEXT: [[TMP63:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11452// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP63]], align 4453// CHECK1-NEXT: [[TMP64:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12454// CHECK1-NEXT: store i32 0, ptr [[TMP64]], align 4455// CHECK1-NEXT: [[TMP65:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.region_id, ptr [[KERNEL_ARGS]])456// CHECK1-NEXT: [[TMP66:%.*]] = icmp ne i32 [[TMP65]], 0457// CHECK1-NEXT: br i1 [[TMP66]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]458// CHECK1: omp_offload.failed:459// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113(i64 [[TMP46]]) #[[ATTR3]]460// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]461// CHECK1: omp_offload.cont:462// CHECK1-NEXT: [[TMP67:%.*]] = load i32, ptr [[A]], align 4463// CHECK1-NEXT: store i32 [[TMP67]], ptr [[A_CASTED8]], align 4464// CHECK1-NEXT: [[TMP68:%.*]] = load i64, ptr [[A_CASTED8]], align 8465// CHECK1-NEXT: [[TMP69:%.*]] = load i16, ptr [[AA]], align 2466// CHECK1-NEXT: store i16 [[TMP69]], ptr [[AA_CASTED9]], align 2467// CHECK1-NEXT: [[TMP70:%.*]] = load i64, ptr [[AA_CASTED9]], align 8468// CHECK1-NEXT: [[TMP71:%.*]] = load i32, ptr [[N_ADDR]], align 4469// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP71]], 10470// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]471// CHECK1: omp_if.then:472// CHECK1-NEXT: [[TMP72:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0473// CHECK1-NEXT: store i64 [[TMP68]], ptr [[TMP72]], align 8474// CHECK1-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 0475// CHECK1-NEXT: store i64 [[TMP68]], ptr [[TMP73]], align 8476// CHECK1-NEXT: [[TMP74:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0477// CHECK1-NEXT: store ptr null, ptr [[TMP74]], align 8478// CHECK1-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1479// CHECK1-NEXT: store i64 [[TMP70]], ptr [[TMP75]], align 8480// CHECK1-NEXT: [[TMP76:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 1481// CHECK1-NEXT: store i64 [[TMP70]], ptr [[TMP76]], align 8482// CHECK1-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1483// CHECK1-NEXT: store ptr null, ptr [[TMP77]], align 8484// CHECK1-NEXT: [[TMP78:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0485// CHECK1-NEXT: [[TMP79:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 0486// CHECK1-NEXT: [[TMP80:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 0487// CHECK1-NEXT: store i32 3, ptr [[TMP80]], align 4488// CHECK1-NEXT: [[TMP81:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 1489// CHECK1-NEXT: store i32 2, ptr [[TMP81]], align 4490// CHECK1-NEXT: [[TMP82:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 2491// CHECK1-NEXT: store ptr [[TMP78]], ptr [[TMP82]], align 8492// CHECK1-NEXT: [[TMP83:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 3493// CHECK1-NEXT: store ptr [[TMP79]], ptr [[TMP83]], align 8494// CHECK1-NEXT: [[TMP84:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 4495// CHECK1-NEXT: store ptr @.offload_sizes.3, ptr [[TMP84]], align 8496// CHECK1-NEXT: [[TMP85:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 5497// CHECK1-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP85]], align 8498// CHECK1-NEXT: [[TMP86:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 6499// CHECK1-NEXT: store ptr null, ptr [[TMP86]], align 8500// CHECK1-NEXT: [[TMP87:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 7501// CHECK1-NEXT: store ptr null, ptr [[TMP87]], align 8502// CHECK1-NEXT: [[TMP88:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 8503// CHECK1-NEXT: store i64 10, ptr [[TMP88]], align 8504// CHECK1-NEXT: [[TMP89:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 9505// CHECK1-NEXT: store i64 0, ptr [[TMP89]], align 8506// CHECK1-NEXT: [[TMP90:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 10507// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP90]], align 4508// CHECK1-NEXT: [[TMP91:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 11509// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP91]], align 4510// CHECK1-NEXT: [[TMP92:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 12511// CHECK1-NEXT: store i32 0, ptr [[TMP92]], align 4512// CHECK1-NEXT: [[TMP93:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.region_id, ptr [[KERNEL_ARGS14]])513// CHECK1-NEXT: [[TMP94:%.*]] = icmp ne i32 [[TMP93]], 0514// CHECK1-NEXT: br i1 [[TMP94]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]]515// CHECK1: omp_offload.failed15:516// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i64 [[TMP68]], i64 [[TMP70]]) #[[ATTR3]]517// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT16]]518// CHECK1: omp_offload.cont16:519// CHECK1-NEXT: br label [[OMP_IF_END:%.*]]520// CHECK1: omp_if.else:521// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i64 [[TMP68]], i64 [[TMP70]]) #[[ATTR3]]522// CHECK1-NEXT: br label [[OMP_IF_END]]523// CHECK1: omp_if.end:524// CHECK1-NEXT: [[TMP95:%.*]] = load i32, ptr [[N_ADDR]], align 4525// CHECK1-NEXT: store i32 [[TMP95]], ptr [[DOTCAPTURE_EXPR_17]], align 4526// CHECK1-NEXT: [[TMP96:%.*]] = load i32, ptr [[A]], align 4527// CHECK1-NEXT: store i32 [[TMP96]], ptr [[A_CASTED18]], align 4528// CHECK1-NEXT: [[TMP97:%.*]] = load i64, ptr [[A_CASTED18]], align 8529// CHECK1-NEXT: [[TMP98:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4530// CHECK1-NEXT: store i32 [[TMP98]], ptr [[DOTCAPTURE_EXPR__CASTED19]], align 4531// CHECK1-NEXT: [[TMP99:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED19]], align 8532// CHECK1-NEXT: [[TMP100:%.*]] = load i32, ptr [[N_ADDR]], align 4533// CHECK1-NEXT: [[CMP20:%.*]] = icmp sgt i32 [[TMP100]], 20534// CHECK1-NEXT: br i1 [[CMP20]], label [[OMP_IF_THEN21:%.*]], label [[OMP_IF_ELSE29:%.*]]535// CHECK1: omp_if.then21:536// CHECK1-NEXT: [[TMP101:%.*]] = mul nuw i64 [[TMP2]], 4537// CHECK1-NEXT: [[TMP102:%.*]] = mul nuw i64 5, [[TMP5]]538// CHECK1-NEXT: [[TMP103:%.*]] = mul nuw i64 [[TMP102]], 8539// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.5, i64 80, i1 false)540// CHECK1-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 0541// CHECK1-NEXT: store i64 [[TMP97]], ptr [[TMP104]], align 8542// CHECK1-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 0543// CHECK1-NEXT: store i64 [[TMP97]], ptr [[TMP105]], align 8544// CHECK1-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 0545// CHECK1-NEXT: store ptr null, ptr [[TMP106]], align 8546// CHECK1-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 1547// CHECK1-NEXT: store ptr [[B]], ptr [[TMP107]], align 8548// CHECK1-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 1549// CHECK1-NEXT: store ptr [[B]], ptr [[TMP108]], align 8550// CHECK1-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 1551// CHECK1-NEXT: store ptr null, ptr [[TMP109]], align 8552// CHECK1-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 2553// CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP110]], align 8554// CHECK1-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 2555// CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP111]], align 8556// CHECK1-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 2557// CHECK1-NEXT: store ptr null, ptr [[TMP112]], align 8558// CHECK1-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 3559// CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP113]], align 8560// CHECK1-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 3561// CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP114]], align 8562// CHECK1-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3563// CHECK1-NEXT: store i64 [[TMP101]], ptr [[TMP115]], align 8564// CHECK1-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 3565// CHECK1-NEXT: store ptr null, ptr [[TMP116]], align 8566// CHECK1-NEXT: [[TMP117:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 4567// CHECK1-NEXT: store ptr [[C]], ptr [[TMP117]], align 8568// CHECK1-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 4569// CHECK1-NEXT: store ptr [[C]], ptr [[TMP118]], align 8570// CHECK1-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 4571// CHECK1-NEXT: store ptr null, ptr [[TMP119]], align 8572// CHECK1-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 5573// CHECK1-NEXT: store i64 5, ptr [[TMP120]], align 8574// CHECK1-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 5575// CHECK1-NEXT: store i64 5, ptr [[TMP121]], align 8576// CHECK1-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 5577// CHECK1-NEXT: store ptr null, ptr [[TMP122]], align 8578// CHECK1-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 6579// CHECK1-NEXT: store i64 [[TMP5]], ptr [[TMP123]], align 8580// CHECK1-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 6581// CHECK1-NEXT: store i64 [[TMP5]], ptr [[TMP124]], align 8582// CHECK1-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 6583// CHECK1-NEXT: store ptr null, ptr [[TMP125]], align 8584// CHECK1-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 7585// CHECK1-NEXT: store ptr [[VLA1]], ptr [[TMP126]], align 8586// CHECK1-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 7587// CHECK1-NEXT: store ptr [[VLA1]], ptr [[TMP127]], align 8588// CHECK1-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 7589// CHECK1-NEXT: store i64 [[TMP103]], ptr [[TMP128]], align 8590// CHECK1-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 7591// CHECK1-NEXT: store ptr null, ptr [[TMP129]], align 8592// CHECK1-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 8593// CHECK1-NEXT: store ptr [[D]], ptr [[TMP130]], align 8594// CHECK1-NEXT: [[TMP131:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 8595// CHECK1-NEXT: store ptr [[D]], ptr [[TMP131]], align 8596// CHECK1-NEXT: [[TMP132:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 8597// CHECK1-NEXT: store ptr null, ptr [[TMP132]], align 8598// CHECK1-NEXT: [[TMP133:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 9599// CHECK1-NEXT: store i64 [[TMP99]], ptr [[TMP133]], align 8600// CHECK1-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 9601// CHECK1-NEXT: store i64 [[TMP99]], ptr [[TMP134]], align 8602// CHECK1-NEXT: [[TMP135:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 9603// CHECK1-NEXT: store ptr null, ptr [[TMP135]], align 8604// CHECK1-NEXT: [[TMP136:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 0605// CHECK1-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 0606// CHECK1-NEXT: [[TMP138:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0607// CHECK1-NEXT: [[TMP139:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 0608// CHECK1-NEXT: store i32 3, ptr [[TMP139]], align 4609// CHECK1-NEXT: [[TMP140:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 1610// CHECK1-NEXT: store i32 10, ptr [[TMP140]], align 4611// CHECK1-NEXT: [[TMP141:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 2612// CHECK1-NEXT: store ptr [[TMP136]], ptr [[TMP141]], align 8613// CHECK1-NEXT: [[TMP142:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 3614// CHECK1-NEXT: store ptr [[TMP137]], ptr [[TMP142]], align 8615// CHECK1-NEXT: [[TMP143:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 4616// CHECK1-NEXT: store ptr [[TMP138]], ptr [[TMP143]], align 8617// CHECK1-NEXT: [[TMP144:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 5618// CHECK1-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP144]], align 8619// CHECK1-NEXT: [[TMP145:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 6620// CHECK1-NEXT: store ptr null, ptr [[TMP145]], align 8621// CHECK1-NEXT: [[TMP146:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 7622// CHECK1-NEXT: store ptr null, ptr [[TMP146]], align 8623// CHECK1-NEXT: [[TMP147:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 8624// CHECK1-NEXT: store i64 10, ptr [[TMP147]], align 8625// CHECK1-NEXT: [[TMP148:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 9626// CHECK1-NEXT: store i64 0, ptr [[TMP148]], align 8627// CHECK1-NEXT: [[TMP149:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 10628// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP149]], align 4629// CHECK1-NEXT: [[TMP150:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 11630// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP150]], align 4631// CHECK1-NEXT: [[TMP151:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 12632// CHECK1-NEXT: store i32 0, ptr [[TMP151]], align 4633// CHECK1-NEXT: [[TMP152:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.region_id, ptr [[KERNEL_ARGS26]])634// CHECK1-NEXT: [[TMP153:%.*]] = icmp ne i32 [[TMP152]], 0635// CHECK1-NEXT: br i1 [[TMP153]], label [[OMP_OFFLOAD_FAILED27:%.*]], label [[OMP_OFFLOAD_CONT28:%.*]]636// CHECK1: omp_offload.failed27:637// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i64 [[TMP97]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP99]]) #[[ATTR3]]638// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT28]]639// CHECK1: omp_offload.cont28:640// CHECK1-NEXT: br label [[OMP_IF_END30:%.*]]641// CHECK1: omp_if.else29:642// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i64 [[TMP97]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP99]]) #[[ATTR3]]643// CHECK1-NEXT: br label [[OMP_IF_END30]]644// CHECK1: omp_if.end30:645// CHECK1-NEXT: [[TMP154:%.*]] = load i32, ptr [[A]], align 4646// CHECK1-NEXT: [[TMP155:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8647// CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP155]])648// CHECK1-NEXT: ret i32 [[TMP154]]649//650//651// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103652// CHECK1-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {653// CHECK1-NEXT: entry:654// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8655// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8656// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8657// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8658// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])659// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8660// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8661// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 8662// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4663// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4664// CHECK1-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])665// CHECK1-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2666// CHECK1-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2667// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8668// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined, i64 [[TMP4]])669// CHECK1-NEXT: ret void670//671//672// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined673// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {674// CHECK1-NEXT: entry:675// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8676// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8677// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8678// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4679// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4680// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4681// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4682// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4683// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4684// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4685// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8686// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8687// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8688// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4689// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4690// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4691// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4692// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8693// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4694// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)695// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4696// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9697// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]698// CHECK1: cond.true:699// CHECK1-NEXT: br label [[COND_END:%.*]]700// CHECK1: cond.false:701// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4702// CHECK1-NEXT: br label [[COND_END]]703// CHECK1: cond.end:704// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]705// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4706// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4707// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4708// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]709// CHECK1: omp.inner.for.cond:710// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4711// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4712// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]713// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]714// CHECK1: omp.inner.for.body:715// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4716// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1717// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]718// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4719// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]720// CHECK1: omp.body.continue:721// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]722// CHECK1: omp.inner.for.inc:723// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4724// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1725// CHECK1-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4726// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]727// CHECK1: omp.inner.for.end:728// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]729// CHECK1: omp.loop.exit:730// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])731// CHECK1-NEXT: ret void732//733//734// CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map.735// CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] {736// CHECK1-NEXT: entry:737// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8738// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8739// CHECK1-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8740// CHECK1-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8741// CHECK1-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8742// CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8743// CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8744// CHECK1-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 8745// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3]], align 8746// CHECK1-NEXT: store ptr [[TMP4]], ptr [[DOTADDR4]], align 8747// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 8748// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP5]], i32 0, i32 0749// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTADDR2]], align 8750// CHECK1-NEXT: store ptr [[TMP6]], ptr [[TMP7]], align 8751// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 1752// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTADDR3]], align 8753// CHECK1-NEXT: store ptr [[TMP8]], ptr [[TMP9]], align 8754// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 2755// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTADDR4]], align 8756// CHECK1-NEXT: store ptr [[TMP10]], ptr [[TMP11]], align 8757// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 3758// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTADDR1]], align 8759// CHECK1-NEXT: store ptr [[TMP12]], ptr [[TMP13]], align 8760// CHECK1-NEXT: ret void761//762//763// CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry.764// CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {765// CHECK1-NEXT: entry:766// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4767// CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8768// CHECK1-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8769// CHECK1-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8770// CHECK1-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8771// CHECK1-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8772// CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 8773// CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 8774// CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca ptr, align 8775// CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca ptr, align 8776// CHECK1-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8777// CHECK1-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8778// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 8779// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i64, align 8780// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4781// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8782// CHECK1-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4783// CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8784// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4785// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8786// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0787// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2788// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0789// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8790// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1791// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])792// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])793// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])794// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])795// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META21:![0-9]+]]796// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META21]]797// CHECK1-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META21]]798// CHECK1-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META21]]799// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META21]]800// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META21]]801// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META21]]802// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META21]]803// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META21]]804// CHECK1-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]805// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META21]]806// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META21]]807// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias [[META21]]808// CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias [[META21]]809// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP9]], i32 0, i32 1810// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 2811// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP16]], align 4812// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP17]], align 4813// CHECK1-NEXT: [[TMP20:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP18]], 0814// CHECK1-NEXT: [[TMP21:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP19]], 0815// CHECK1-NEXT: store i32 3, ptr [[KERNEL_ARGS_I]], align 4, !noalias [[META21]]816// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 1817// CHECK1-NEXT: store i32 3, ptr [[TMP22]], align 4, !noalias [[META21]]818// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 2819// CHECK1-NEXT: store ptr [[TMP13]], ptr [[TMP23]], align 8, !noalias [[META21]]820// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 3821// CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP24]], align 8, !noalias [[META21]]822// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 4823// CHECK1-NEXT: store ptr [[TMP15]], ptr [[TMP25]], align 8, !noalias [[META21]]824// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 5825// CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP26]], align 8, !noalias [[META21]]826// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 6827// CHECK1-NEXT: store ptr null, ptr [[TMP27]], align 8, !noalias [[META21]]828// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 7829// CHECK1-NEXT: store ptr null, ptr [[TMP28]], align 8, !noalias [[META21]]830// CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 8831// CHECK1-NEXT: store i64 10, ptr [[TMP29]], align 8, !noalias [[META21]]832// CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 9833// CHECK1-NEXT: store i64 1, ptr [[TMP30]], align 8, !noalias [[META21]]834// CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 10835// CHECK1-NEXT: store [3 x i32] [[TMP20]], ptr [[TMP31]], align 4, !noalias [[META21]]836// CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 11837// CHECK1-NEXT: store [3 x i32] [[TMP21]], ptr [[TMP32]], align 4, !noalias [[META21]]838// CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 12839// CHECK1-NEXT: store i32 0, ptr [[TMP33]], align 4, !noalias [[META21]]840// CHECK1-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 [[TMP18]], i32 [[TMP19]], ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, ptr [[KERNEL_ARGS_I]])841// CHECK1-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0842// CHECK1-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]]843// CHECK1: omp_offload.failed.i:844// CHECK1-NEXT: [[TMP36:%.*]] = load i16, ptr [[TMP12]], align 2845// CHECK1-NEXT: store i16 [[TMP36]], ptr [[AA_CASTED_I]], align 2, !noalias [[META21]]846// CHECK1-NEXT: [[TMP37:%.*]] = load i64, ptr [[AA_CASTED_I]], align 8, !noalias [[META21]]847// CHECK1-NEXT: [[TMP38:%.*]] = load i32, ptr [[TMP16]], align 4848// CHECK1-NEXT: store i32 [[TMP38]], ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias [[META21]]849// CHECK1-NEXT: [[TMP39:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias [[META21]]850// CHECK1-NEXT: [[TMP40:%.*]] = load i32, ptr [[TMP17]], align 4851// CHECK1-NEXT: store i32 [[TMP40]], ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias [[META21]]852// CHECK1-NEXT: [[TMP41:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 8, !noalias [[META21]]853// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103(i64 [[TMP37]], i64 [[TMP39]], i64 [[TMP41]]) #[[ATTR3]]854// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__EXIT]]855// CHECK1: .omp_outlined..exit:856// CHECK1-NEXT: ret i32 0857//858//859// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107860// CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR2]] {861// CHECK1-NEXT: entry:862// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8863// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8864// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8865// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4866// CHECK1-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4867// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8868// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107.omp_outlined, i64 [[TMP1]])869// CHECK1-NEXT: ret void870//871//872// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107.omp_outlined873// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] {874// CHECK1-NEXT: entry:875// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8876// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8877// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8878// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4879// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4880// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4881// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4882// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4883// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4884// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4885// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8886// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8887// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8888// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4889// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4890// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4891// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4892// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8893// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4894// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)895// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4896// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9897// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]898// CHECK1: cond.true:899// CHECK1-NEXT: br label [[COND_END:%.*]]900// CHECK1: cond.false:901// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4902// CHECK1-NEXT: br label [[COND_END]]903// CHECK1: cond.end:904// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]905// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4906// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4907// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4908// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]909// CHECK1: omp.inner.for.cond:910// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4911// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4912// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]913// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]914// CHECK1: omp.inner.for.body:915// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4916// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1917// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]918// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4919// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4920// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1921// CHECK1-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4922// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]923// CHECK1: omp.body.continue:924// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]925// CHECK1: omp.inner.for.inc:926// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4927// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1928// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4929// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]930// CHECK1: omp.inner.for.end:931// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]932// CHECK1: omp.loop.exit:933// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])934// CHECK1-NEXT: ret void935//936//937// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113938// CHECK1-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] {939// CHECK1-NEXT: entry:940// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8941// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8942// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8943// CHECK1-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2944// CHECK1-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2945// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8946// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.omp_outlined, i64 [[TMP1]])947// CHECK1-NEXT: ret void948//949//950// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.omp_outlined951// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {952// CHECK1-NEXT: entry:953// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8954// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8955// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8956// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4957// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4958// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4959// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4960// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4961// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4962// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4963// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8964// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8965// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8966// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4967// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4968// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4969// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4970// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8971// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4972// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)973// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4974// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9975// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]976// CHECK1: cond.true:977// CHECK1-NEXT: br label [[COND_END:%.*]]978// CHECK1: cond.false:979// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4980// CHECK1-NEXT: br label [[COND_END]]981// CHECK1: cond.end:982// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]983// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4984// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4985// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4986// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]987// CHECK1: omp.inner.for.cond:988// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4989// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4990// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]991// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]992// CHECK1: omp.inner.for.body:993// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4994// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1995// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]996// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4997// CHECK1-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2998// CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP8]] to i32999// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 11000// CHECK1-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i161001// CHECK1-NEXT: store i16 [[CONV3]], ptr [[AA_ADDR]], align 21002// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1003// CHECK1: omp.body.continue:1004// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1005// CHECK1: omp.inner.for.inc:1006// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41007// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 11008// CHECK1-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 41009// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]1010// CHECK1: omp.inner.for.end:1011// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]1012// CHECK1: omp.loop.exit:1013// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])1014// CHECK1-NEXT: ret void1015//1016//1017// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1201018// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {1019// CHECK1-NEXT: entry:1020// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 81021// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 81022// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 81023// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 81024// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 81025// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 81026// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41027// CHECK1-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 41028// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 81029// CHECK1-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 21030// CHECK1-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 21031// CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 81032// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.omp_outlined, i64 [[TMP1]], i64 [[TMP3]])1033// CHECK1-NEXT: ret void1034//1035//1036// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.omp_outlined1037// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {1038// CHECK1-NEXT: entry:1039// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81040// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81041// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 81042// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 81043// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41044// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 41045// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 41046// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 41047// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41048// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41049// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 41050// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81051// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81052// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 81053// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 81054// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 41055// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 41056// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 41057// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41058// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81059// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 41060// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1061// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41062// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 91063// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1064// CHECK1: cond.true:1065// CHECK1-NEXT: br label [[COND_END:%.*]]1066// CHECK1: cond.false:1067// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41068// CHECK1-NEXT: br label [[COND_END]]1069// CHECK1: cond.end:1070// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]1071// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 41072// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41073// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 41074// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1075// CHECK1: omp.inner.for.cond:1076// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41077// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41078// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]1079// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1080// CHECK1: omp.inner.for.body:1081// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41082// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 11083// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]1084// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 41085// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 41086// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 11087// CHECK1-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 41088// CHECK1-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 21089// CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i321090// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 11091// CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i161092// CHECK1-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 21093// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1094// CHECK1: omp.body.continue:1095// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1096// CHECK1: omp.inner.for.inc:1097// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41098// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 11099// CHECK1-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 41100// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]1101// CHECK1: omp.inner.for.end:1102// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]1103// CHECK1: omp.loop.exit:1104// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])1105// CHECK1-NEXT: ret void1106//1107//1108// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1451109// CHECK1-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {1110// CHECK1-NEXT: entry:1111// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 81112// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 81113// CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 81114// CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 81115// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 81116// CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 81117// CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 81118// CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 81119// CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 81120// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 81121// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 81122// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 81123// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 81124// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 81125// CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 81126// CHECK1-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 81127// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 81128// CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 81129// CHECK1-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 81130// CHECK1-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 81131// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 81132// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 81133// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 81134// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 81135// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 81136// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 81137// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 81138// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 81139// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 81140// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 81141// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 41142// CHECK1-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 41143// CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 81144// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 41145// CHECK1-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 41146// CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 81147// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i64 [[TMP11]])1148// CHECK1-NEXT: ret void1149//1150//1151// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.omp_outlined1152// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {1153// CHECK1-NEXT: entry:1154// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81155// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81156// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 81157// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 81158// CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 81159// CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 81160// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 81161// CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 81162// CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 81163// CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 81164// CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 81165// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 81166// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41167// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 41168// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 41169// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 41170// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41171// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41172// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 41173// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81174// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81175// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 81176// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 81177// CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 81178// CHECK1-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 81179// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 81180// CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 81181// CHECK1-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 81182// CHECK1-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 81183// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 81184// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 81185// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 81186// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 81187// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 81188// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 81189// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 81190// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 81191// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 81192// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 81193// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 41194// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 41195// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 41196// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41197// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 41198// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81199// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 41200// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])1201// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]]1202// CHECK1: omp.dispatch.cond:1203// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41204// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 91205// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1206// CHECK1: cond.true:1207// CHECK1-NEXT: br label [[COND_END:%.*]]1208// CHECK1: cond.false:1209// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41210// CHECK1-NEXT: br label [[COND_END]]1211// CHECK1: cond.end:1212// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]1213// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 41214// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41215// CHECK1-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 41216// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41217// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41218// CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]1219// CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]1220// CHECK1: omp.dispatch.body:1221// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1222// CHECK1: omp.inner.for.cond:1223// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22:![0-9]+]]1224// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP22]]1225// CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]1226// CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1227// CHECK1: omp.inner.for.body:1228// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]1229// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 11230// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]1231// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]]1232// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP22]]1233// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 11234// CHECK1-NEXT: store i32 [[ADD7]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP22]]1235// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 21236// CHECK1-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]]1237// CHECK1-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double1238// CHECK1-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+001239// CHECK1-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float1240// CHECK1-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]]1241// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 31242// CHECK1-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP22]]1243// CHECK1-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double1244// CHECK1-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+001245// CHECK1-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float1246// CHECK1-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP22]]1247// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 11248// CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i64 0, i64 21249// CHECK1-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP22]]1250// CHECK1-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+001251// CHECK1-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP22]]1252// CHECK1-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]1253// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP23]]1254// CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i64 31255// CHECK1-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP22]]1256// CHECK1-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+001257// CHECK1-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP22]]1258// CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 01259// CHECK1-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP22]]1260// CHECK1-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 11261// CHECK1-NEXT: store i64 [[ADD20]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP22]]1262// CHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 11263// CHECK1-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP22]]1264// CHECK1-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i321265// CHECK1-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 11266// CHECK1-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i81267// CHECK1-NEXT: store i8 [[CONV23]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP22]]1268// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1269// CHECK1: omp.body.continue:1270// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1271// CHECK1: omp.inner.for.inc:1272// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]1273// CHECK1-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 11274// CHECK1-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]1275// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]1276// CHECK1: omp.inner.for.end:1277// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]1278// CHECK1: omp.dispatch.inc:1279// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41280// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 41281// CHECK1-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]1282// CHECK1-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 41283// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41284// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 41285// CHECK1-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]1286// CHECK1-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 41287// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]1288// CHECK1: omp.dispatch.end:1289// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]])1290// CHECK1-NEXT: ret void1291//1292//1293// CHECK1-LABEL: define {{[^@]+}}@_Z3bari1294// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {1295// CHECK1-NEXT: entry:1296// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 41297// CHECK1-NEXT: [[A:%.*]] = alloca i32, align 41298// CHECK1-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 81299// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 41300// CHECK1-NEXT: store i32 0, ptr [[A]], align 41301// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 41302// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]])1303// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 41304// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]1305// CHECK1-NEXT: store i32 [[ADD]], ptr [[A]], align 41306// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 41307// CHECK1-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]])1308// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 41309// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]1310// CHECK1-NEXT: store i32 [[ADD2]], ptr [[A]], align 41311// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 41312// CHECK1-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]])1313// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 41314// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]1315// CHECK1-NEXT: store i32 [[ADD4]], ptr [[A]], align 41316// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 41317// CHECK1-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]])1318// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 41319// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]1320// CHECK1-NEXT: store i32 [[ADD6]], ptr [[A]], align 41321// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 41322// CHECK1-NEXT: ret i32 [[TMP8]]1323//1324//1325// CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei1326// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {1327// CHECK1-NEXT: entry:1328// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81329// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 41330// CHECK1-NEXT: [[B:%.*]] = alloca i32, align 41331// CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 81332// CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 81333// CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 81334// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 81335// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 81336// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 81337// CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 81338// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 41339// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81340// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81341// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 41342// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81343// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 41344// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 11345// CHECK1-NEXT: store i32 [[ADD]], ptr [[B]], align 41346// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 41347// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i641348// CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()1349// CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 81350// CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]1351// CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 21352// CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 81353// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 41354// CHECK1-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 41355// CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 81356// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 41357// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 601358// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]1359// CHECK1: omp_if.then:1360// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 01361// CHECK1-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]]1362// CHECK1-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 21363// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.7, i64 40, i1 false)1364// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01365// CHECK1-NEXT: store ptr [[THIS1]], ptr [[TMP10]], align 81366// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01367// CHECK1-NEXT: store ptr [[A]], ptr [[TMP11]], align 81368// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 01369// CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 81370// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 11371// CHECK1-NEXT: store i64 [[TMP6]], ptr [[TMP13]], align 81372// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 11373// CHECK1-NEXT: store i64 [[TMP6]], ptr [[TMP14]], align 81374// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 11375// CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 81376// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 21377// CHECK1-NEXT: store i64 2, ptr [[TMP16]], align 81378// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 21379// CHECK1-NEXT: store i64 2, ptr [[TMP17]], align 81380// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 21381// CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 81382// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 31383// CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP19]], align 81384// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 31385// CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP20]], align 81386// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 31387// CHECK1-NEXT: store ptr null, ptr [[TMP21]], align 81388// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 41389// CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP22]], align 81390// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 41391// CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP23]], align 81392// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 41393// CHECK1-NEXT: store i64 [[TMP9]], ptr [[TMP24]], align 81394// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 41395// CHECK1-NEXT: store ptr null, ptr [[TMP25]], align 81396// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01397// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01398// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 01399// CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 01400// CHECK1-NEXT: store i32 3, ptr [[TMP29]], align 41401// CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11402// CHECK1-NEXT: store i32 5, ptr [[TMP30]], align 41403// CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 21404// CHECK1-NEXT: store ptr [[TMP26]], ptr [[TMP31]], align 81405// CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 31406// CHECK1-NEXT: store ptr [[TMP27]], ptr [[TMP32]], align 81407// CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 41408// CHECK1-NEXT: store ptr [[TMP28]], ptr [[TMP33]], align 81409// CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 51410// CHECK1-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP34]], align 81411// CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 61412// CHECK1-NEXT: store ptr null, ptr [[TMP35]], align 81413// CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 71414// CHECK1-NEXT: store ptr null, ptr [[TMP36]], align 81415// CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 81416// CHECK1-NEXT: store i64 10, ptr [[TMP37]], align 81417// CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 91418// CHECK1-NEXT: store i64 0, ptr [[TMP38]], align 81419// CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 101420// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP39]], align 41421// CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 111422// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP40]], align 41423// CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 121424// CHECK1-NEXT: store i32 0, ptr [[TMP41]], align 41425// CHECK1-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.region_id, ptr [[KERNEL_ARGS]])1426// CHECK1-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 01427// CHECK1-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]1428// CHECK1: omp_offload.failed:1429// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR3]]1430// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]1431// CHECK1: omp_offload.cont:1432// CHECK1-NEXT: br label [[OMP_IF_END:%.*]]1433// CHECK1: omp_if.else:1434// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR3]]1435// CHECK1-NEXT: br label [[OMP_IF_END]]1436// CHECK1: omp_if.end:1437// CHECK1-NEXT: [[TMP44:%.*]] = mul nsw i64 1, [[TMP2]]1438// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP44]]1439// CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 11440// CHECK1-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 21441// CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i321442// CHECK1-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 41443// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]]1444// CHECK1-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 81445// CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP47]])1446// CHECK1-NEXT: ret i32 [[ADD3]]1447//1448//1449// CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici1450// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {1451// CHECK1-NEXT: entry:1452// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 41453// CHECK1-NEXT: [[A:%.*]] = alloca i32, align 41454// CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 21455// CHECK1-NEXT: [[AAA:%.*]] = alloca i8, align 11456// CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 41457// CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 81458// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 81459// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 81460// CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 81461// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 81462// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 81463// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 81464// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 41465// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 41466// CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 41467// CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 41468// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81469// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 41470// CHECK1-NEXT: store i32 0, ptr [[A]], align 41471// CHECK1-NEXT: store i16 0, ptr [[AA]], align 21472// CHECK1-NEXT: store i8 0, ptr [[AAA]], align 11473// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 41474// CHECK1-NEXT: store i32 [[TMP0]], ptr [[N_CASTED]], align 41475// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[N_CASTED]], align 81476// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 41477// CHECK1-NEXT: store i32 [[TMP2]], ptr [[A_CASTED]], align 41478// CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[A_CASTED]], align 81479// CHECK1-NEXT: [[TMP4:%.*]] = load i16, ptr [[AA]], align 21480// CHECK1-NEXT: store i16 [[TMP4]], ptr [[AA_CASTED]], align 21481// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[AA_CASTED]], align 81482// CHECK1-NEXT: [[TMP6:%.*]] = load i8, ptr [[AAA]], align 11483// CHECK1-NEXT: store i8 [[TMP6]], ptr [[AAA_CASTED]], align 11484// CHECK1-NEXT: [[TMP7:%.*]] = load i64, ptr [[AAA_CASTED]], align 81485// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[N_ADDR]], align 41486// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 501487// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]1488// CHECK1: omp_if.then:1489// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01490// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP9]], align 81491// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01492// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP10]], align 81493// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 01494// CHECK1-NEXT: store ptr null, ptr [[TMP11]], align 81495// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 11496// CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP12]], align 81497// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 11498// CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP13]], align 81499// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 11500// CHECK1-NEXT: store ptr null, ptr [[TMP14]], align 81501// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 21502// CHECK1-NEXT: store i64 [[TMP5]], ptr [[TMP15]], align 81503// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 21504// CHECK1-NEXT: store i64 [[TMP5]], ptr [[TMP16]], align 81505// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 21506// CHECK1-NEXT: store ptr null, ptr [[TMP17]], align 81507// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 31508// CHECK1-NEXT: store i64 [[TMP7]], ptr [[TMP18]], align 81509// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 31510// CHECK1-NEXT: store i64 [[TMP7]], ptr [[TMP19]], align 81511// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 31512// CHECK1-NEXT: store ptr null, ptr [[TMP20]], align 81513// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 41514// CHECK1-NEXT: store ptr [[B]], ptr [[TMP21]], align 81515// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 41516// CHECK1-NEXT: store ptr [[B]], ptr [[TMP22]], align 81517// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 41518// CHECK1-NEXT: store ptr null, ptr [[TMP23]], align 81519// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01520// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01521// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[A]], align 41522// CHECK1-NEXT: store i32 [[TMP26]], ptr [[DOTCAPTURE_EXPR_]], align 41523// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[N_ADDR]], align 41524// CHECK1-NEXT: store i32 [[TMP27]], ptr [[DOTCAPTURE_EXPR_1]], align 41525// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 41526// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41527// CHECK1-NEXT: [[SUB:%.*]] = sub i32 [[TMP28]], [[TMP29]]1528// CHECK1-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 11529// CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 11530// CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 11531// CHECK1-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 11532// CHECK1-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 41533// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 41534// CHECK1-NEXT: [[ADD5:%.*]] = add i32 [[TMP30]], 11535// CHECK1-NEXT: [[TMP31:%.*]] = zext i32 [[ADD5]] to i641536// CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 01537// CHECK1-NEXT: store i32 3, ptr [[TMP32]], align 41538// CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11539// CHECK1-NEXT: store i32 5, ptr [[TMP33]], align 41540// CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 21541// CHECK1-NEXT: store ptr [[TMP24]], ptr [[TMP34]], align 81542// CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 31543// CHECK1-NEXT: store ptr [[TMP25]], ptr [[TMP35]], align 81544// CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 41545// CHECK1-NEXT: store ptr @.offload_sizes.9, ptr [[TMP36]], align 81546// CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 51547// CHECK1-NEXT: store ptr @.offload_maptypes.10, ptr [[TMP37]], align 81548// CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 61549// CHECK1-NEXT: store ptr null, ptr [[TMP38]], align 81550// CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 71551// CHECK1-NEXT: store ptr null, ptr [[TMP39]], align 81552// CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 81553// CHECK1-NEXT: store i64 [[TMP31]], ptr [[TMP40]], align 81554// CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 91555// CHECK1-NEXT: store i64 0, ptr [[TMP41]], align 81556// CHECK1-NEXT: [[TMP42:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 101557// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP42]], align 41558// CHECK1-NEXT: [[TMP43:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 111559// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP43]], align 41560// CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 121561// CHECK1-NEXT: store i32 0, ptr [[TMP44]], align 41562// CHECK1-NEXT: [[TMP45:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.region_id, ptr [[KERNEL_ARGS]])1563// CHECK1-NEXT: [[TMP46:%.*]] = icmp ne i32 [[TMP45]], 01564// CHECK1-NEXT: br i1 [[TMP46]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]1565// CHECK1: omp_offload.failed:1566// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], ptr [[B]]) #[[ATTR3]]1567// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]1568// CHECK1: omp_offload.cont:1569// CHECK1-NEXT: br label [[OMP_IF_END:%.*]]1570// CHECK1: omp_if.else:1571// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], ptr [[B]]) #[[ATTR3]]1572// CHECK1-NEXT: br label [[OMP_IF_END]]1573// CHECK1: omp_if.end:1574// CHECK1-NEXT: [[TMP47:%.*]] = load i32, ptr [[A]], align 41575// CHECK1-NEXT: ret i32 [[TMP47]]1576//1577//1578// CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i1579// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {1580// CHECK1-NEXT: entry:1581// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 41582// CHECK1-NEXT: [[A:%.*]] = alloca i32, align 41583// CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 21584// CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 41585// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 81586// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 81587// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 81588// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 81589// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 81590// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 41591// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81592// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 41593// CHECK1-NEXT: store i32 0, ptr [[A]], align 41594// CHECK1-NEXT: store i16 0, ptr [[AA]], align 21595// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 41596// CHECK1-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 41597// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 81598// CHECK1-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 21599// CHECK1-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 21600// CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 81601// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 41602// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 401603// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]1604// CHECK1: omp_if.then:1605// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01606// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP5]], align 81607// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01608// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP6]], align 81609// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 01610// CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 81611// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 11612// CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP8]], align 81613// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 11614// CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP9]], align 81615// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 11616// CHECK1-NEXT: store ptr null, ptr [[TMP10]], align 81617// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 21618// CHECK1-NEXT: store ptr [[B]], ptr [[TMP11]], align 81619// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 21620// CHECK1-NEXT: store ptr [[B]], ptr [[TMP12]], align 81621// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 21622// CHECK1-NEXT: store ptr null, ptr [[TMP13]], align 81623// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01624// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01625// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 01626// CHECK1-NEXT: store i32 3, ptr [[TMP16]], align 41627// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11628// CHECK1-NEXT: store i32 3, ptr [[TMP17]], align 41629// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 21630// CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 81631// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 31632// CHECK1-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 81633// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 41634// CHECK1-NEXT: store ptr @.offload_sizes.11, ptr [[TMP20]], align 81635// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 51636// CHECK1-NEXT: store ptr @.offload_maptypes.12, ptr [[TMP21]], align 81637// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 61638// CHECK1-NEXT: store ptr null, ptr [[TMP22]], align 81639// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 71640// CHECK1-NEXT: store ptr null, ptr [[TMP23]], align 81641// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 81642// CHECK1-NEXT: store i64 10, ptr [[TMP24]], align 81643// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 91644// CHECK1-NEXT: store i64 0, ptr [[TMP25]], align 81645// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 101646// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP26]], align 41647// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 111648// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP27]], align 41649// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 121650// CHECK1-NEXT: store i32 0, ptr [[TMP28]], align 41651// CHECK1-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.region_id, ptr [[KERNEL_ARGS]])1652// CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 01653// CHECK1-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]1654// CHECK1: omp_offload.failed:1655// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]]1656// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]1657// CHECK1: omp_offload.cont:1658// CHECK1-NEXT: br label [[OMP_IF_END:%.*]]1659// CHECK1: omp_if.else:1660// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]]1661// CHECK1-NEXT: br label [[OMP_IF_END]]1662// CHECK1: omp_if.end:1663// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[A]], align 41664// CHECK1-NEXT: ret i32 [[TMP31]]1665//1666//1667// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l2181668// CHECK1-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {1669// CHECK1-NEXT: entry:1670// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81671// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 81672// CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 81673// CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 81674// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 81675// CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 81676// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81677// CHECK1-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 81678// CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 81679// CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 81680// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 81681// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81682// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 81683// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 81684// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 81685// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 41686// CHECK1-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 41687// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 81688// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.omp_outlined, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]])1689// CHECK1-NEXT: ret void1690//1691//1692// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.omp_outlined1693// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {1694// CHECK1-NEXT: entry:1695// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81696// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81697// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81698// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 81699// CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 81700// CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 81701// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 81702// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41703// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 41704// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 41705// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 41706// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41707// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41708// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 41709// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81710// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81711// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81712// CHECK1-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 81713// CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 81714// CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 81715// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 81716// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81717// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 81718// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 81719// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 81720// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 41721// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 41722// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 41723// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41724// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81725// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 41726// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1727// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41728// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 91729// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1730// CHECK1: cond.true:1731// CHECK1-NEXT: br label [[COND_END:%.*]]1732// CHECK1: cond.false:1733// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41734// CHECK1-NEXT: br label [[COND_END]]1735// CHECK1: cond.end:1736// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]1737// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 41738// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41739// CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 41740// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1741// CHECK1: omp.inner.for.cond:1742// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41743// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41744// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]1745// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1746// CHECK1: omp.inner.for.body:1747// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41748// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 11749// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]1750// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 41751// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 41752// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double1753// CHECK1-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+001754// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 01755// CHECK1-NEXT: store double [[ADD4]], ptr [[A]], align 81756// CHECK1-NEXT: [[A5:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 01757// CHECK1-NEXT: [[TMP13:%.*]] = load double, ptr [[A5]], align 81758// CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+001759// CHECK1-NEXT: store double [[INC]], ptr [[A5]], align 81760// CHECK1-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i161761// CHECK1-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]1762// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP14]]1763// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 11764// CHECK1-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 21765// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1766// CHECK1: omp.body.continue:1767// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1768// CHECK1: omp.inner.for.inc:1769// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41770// CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 11771// CHECK1-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 41772// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]1773// CHECK1: omp.inner.for.end:1774// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]1775// CHECK1: omp.loop.exit:1776// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])1777// CHECK1-NEXT: ret void1778//1779//1780// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l2001781// CHECK1-SAME: (i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {1782// CHECK1-NEXT: entry:1783// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 81784// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 81785// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 81786// CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 81787// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 81788// CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 81789// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 81790// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 81791// CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 81792// CHECK1-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 81793// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 81794// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 81795// CHECK1-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 81796// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 81797// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 81798// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 41799// CHECK1-NEXT: store i32 [[TMP1]], ptr [[N_CASTED]], align 41800// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[N_CASTED]], align 81801// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[A_ADDR]], align 41802// CHECK1-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 41803// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[A_CASTED]], align 81804// CHECK1-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA_ADDR]], align 21805// CHECK1-NEXT: store i16 [[TMP5]], ptr [[AA_CASTED]], align 21806// CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[AA_CASTED]], align 81807// CHECK1-NEXT: [[TMP7:%.*]] = load i8, ptr [[AAA_ADDR]], align 11808// CHECK1-NEXT: store i8 [[TMP7]], ptr [[AAA_CASTED]], align 11809// CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[AAA_CASTED]], align 81810// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], ptr [[TMP0]])1811// CHECK1-NEXT: ret void1812//1813//1814// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.omp_outlined1815// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {1816// CHECK1-NEXT: entry:1817// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81818// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81819// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 81820// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 81821// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 81822// CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 81823// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 81824// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41825// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 41826// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 41827// CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 41828// CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 41829// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 41830// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 41831// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 41832// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41833// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41834// CHECK1-NEXT: [[I5:%.*]] = alloca i32, align 41835// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81836// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81837// CHECK1-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 81838// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 81839// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 81840// CHECK1-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 81841// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 81842// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 81843// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 41844// CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 41845// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 41846// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_1]], align 41847// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 41848// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41849// CHECK1-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]1850// CHECK1-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 11851// CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 11852// CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 11853// CHECK1-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 11854// CHECK1-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 41855// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41856// CHECK1-NEXT: store i32 [[TMP5]], ptr [[I]], align 41857// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41858// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 41859// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]1860// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]1861// CHECK1: omp.precond.then:1862// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 41863// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 41864// CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_UB]], align 41865// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 41866// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41867// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81868// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 41869// CHECK1-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP10]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1870// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41871// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 41872// CHECK1-NEXT: [[CMP6:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]1873// CHECK1-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1874// CHECK1: cond.true:1875// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 41876// CHECK1-NEXT: br label [[COND_END:%.*]]1877// CHECK1: cond.false:1878// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41879// CHECK1-NEXT: br label [[COND_END]]1880// CHECK1: cond.end:1881// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]1882// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 41883// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41884// CHECK1-NEXT: store i32 [[TMP15]], ptr [[DOTOMP_IV]], align 41885// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1886// CHECK1: omp.inner.for.cond:1887// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41888// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41889// CHECK1-NEXT: [[ADD7:%.*]] = add i32 [[TMP17]], 11890// CHECK1-NEXT: [[CMP8:%.*]] = icmp ult i32 [[TMP16]], [[ADD7]]1891// CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1892// CHECK1: omp.inner.for.body:1893// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41894// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41895// CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 11896// CHECK1-NEXT: [[ADD9:%.*]] = add i32 [[TMP18]], [[MUL]]1897// CHECK1-NEXT: store i32 [[ADD9]], ptr [[I5]], align 41898// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 41899// CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 11900// CHECK1-NEXT: store i32 [[ADD10]], ptr [[A_ADDR]], align 41901// CHECK1-NEXT: [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 21902// CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP21]] to i321903// CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[CONV]], 11904// CHECK1-NEXT: [[CONV12:%.*]] = trunc i32 [[ADD11]] to i161905// CHECK1-NEXT: store i16 [[CONV12]], ptr [[AA_ADDR]], align 21906// CHECK1-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 11907// CHECK1-NEXT: [[CONV13:%.*]] = sext i8 [[TMP22]] to i321908// CHECK1-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV13]], 11909// CHECK1-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i81910// CHECK1-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 11911// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 21912// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 41913// CHECK1-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP23]], 11914// CHECK1-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 41915// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1916// CHECK1: omp.body.continue:1917// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1918// CHECK1: omp.inner.for.inc:1919// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41920// CHECK1-NEXT: [[ADD17:%.*]] = add i32 [[TMP24]], 11921// CHECK1-NEXT: store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 41922// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]1923// CHECK1: omp.inner.for.end:1924// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]1925// CHECK1: omp.loop.exit:1926// CHECK1-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81927// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 41928// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP26]])1929// CHECK1-NEXT: br label [[OMP_PRECOND_END]]1930// CHECK1: omp.precond.end:1931// CHECK1-NEXT: ret void1932//1933//1934// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l1831935// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {1936// CHECK1-NEXT: entry:1937// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 81938// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 81939// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 81940// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 81941// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 81942// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 81943// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 81944// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 81945// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 81946// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 41947// CHECK1-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 41948// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 81949// CHECK1-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 21950// CHECK1-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 21951// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 81952// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]])1953// CHECK1-NEXT: ret void1954//1955//1956// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.omp_outlined1957// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {1958// CHECK1-NEXT: entry:1959// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81960// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81961// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 81962// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 81963// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 81964// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41965// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 41966// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 41967// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 41968// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41969// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41970// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 41971// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81972// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81973// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 81974// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 81975// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 81976// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 81977// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 41978// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 41979// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 41980// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41981// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81982// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 41983// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1984// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41985// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 91986// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1987// CHECK1: cond.true:1988// CHECK1-NEXT: br label [[COND_END:%.*]]1989// CHECK1: cond.false:1990// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41991// CHECK1-NEXT: br label [[COND_END]]1992// CHECK1: cond.end:1993// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]1994// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 41995// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41996// CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 41997// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1998// CHECK1: omp.inner.for.cond:1999// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42000// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42001// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]2002// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2003// CHECK1: omp.inner.for.body:2004// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42005// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 12006// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]2007// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 42008// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 42009// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 12010// CHECK1-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 42011// CHECK1-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 22012// CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i322013// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 12014// CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i162015// CHECK1-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 22016// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 22017// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 42018// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 12019// CHECK1-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 42020// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]2021// CHECK1: omp.body.continue:2022// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]2023// CHECK1: omp.inner.for.inc:2024// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42025// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 12026// CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 42027// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]2028// CHECK1: omp.inner.for.end:2029// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]2030// CHECK1: omp.loop.exit:2031// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])2032// CHECK1-NEXT: ret void2033//2034//2035// CHECK3-LABEL: define {{[^@]+}}@_Z3fooi2036// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] {2037// CHECK3-NEXT: entry:2038// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 42039// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 42040// CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 22041// CHECK3-NEXT: [[B:%.*]] = alloca [10 x float], align 42042// CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 42043// CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 42044// CHECK3-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 82045// CHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 42046// CHECK3-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 42047// CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 42048// CHECK3-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 42049// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 42050// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 42051// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 42052// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 42053// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 42054// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 42055// CHECK3-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 42056// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 42057// CHECK3-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 42058// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [1 x ptr], align 42059// CHECK3-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [1 x ptr], align 42060// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [1 x ptr], align 42061// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 42062// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 82063// CHECK3-NEXT: [[A_CASTED8:%.*]] = alloca i32, align 42064// CHECK3-NEXT: [[AA_CASTED9:%.*]] = alloca i32, align 42065// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x ptr], align 42066// CHECK3-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x ptr], align 42067// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x ptr], align 42068// CHECK3-NEXT: [[_TMP13:%.*]] = alloca i32, align 42069// CHECK3-NEXT: [[KERNEL_ARGS14:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 82070// CHECK3-NEXT: [[DOTCAPTURE_EXPR_17:%.*]] = alloca i32, align 42071// CHECK3-NEXT: [[A_CASTED18:%.*]] = alloca i32, align 42072// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED19:%.*]] = alloca i32, align 42073// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS22:%.*]] = alloca [10 x ptr], align 42074// CHECK3-NEXT: [[DOTOFFLOAD_PTRS23:%.*]] = alloca [10 x ptr], align 42075// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS24:%.*]] = alloca [10 x ptr], align 42076// CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 42077// CHECK3-NEXT: [[_TMP25:%.*]] = alloca i32, align 42078// CHECK3-NEXT: [[KERNEL_ARGS26:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 82079// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])2080// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 42081// CHECK3-NEXT: store i32 0, ptr [[A]], align 42082// CHECK3-NEXT: store i16 0, ptr [[AA]], align 22083// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 42084// CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()2085// CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 42086// CHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 42087// CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 42088// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 42089// CHECK3-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]2090// CHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 82091// CHECK3-NEXT: store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 42092// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 42093// CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 42094// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 42095// CHECK3-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_2]], align 42096// CHECK3-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 22097// CHECK3-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 22098// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[AA_CASTED]], align 42099// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 42100// CHECK3-NEXT: store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 42101// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 42102// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 42103// CHECK3-NEXT: store i32 [[TMP11]], ptr [[DOTCAPTURE_EXPR__CASTED3]], align 42104// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED3]], align 42105// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 02106// CHECK3-NEXT: store i32 [[TMP8]], ptr [[TMP13]], align 42107// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 02108// CHECK3-NEXT: store i32 [[TMP8]], ptr [[TMP14]], align 42109// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 02110// CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 42111// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 12112// CHECK3-NEXT: store i32 [[TMP10]], ptr [[TMP16]], align 42113// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 12114// CHECK3-NEXT: store i32 [[TMP10]], ptr [[TMP17]], align 42115// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 12116// CHECK3-NEXT: store ptr null, ptr [[TMP18]], align 42117// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 22118// CHECK3-NEXT: store i32 [[TMP12]], ptr [[TMP19]], align 42119// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 22120// CHECK3-NEXT: store i32 [[TMP12]], ptr [[TMP20]], align 42121// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 22122// CHECK3-NEXT: store ptr null, ptr [[TMP21]], align 42123// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 02124// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 02125// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 02126// CHECK3-NEXT: [[TMP25:%.*]] = load i16, ptr [[AA]], align 22127// CHECK3-NEXT: store i16 [[TMP25]], ptr [[TMP24]], align 42128// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 12129// CHECK3-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 42130// CHECK3-NEXT: store i32 [[TMP27]], ptr [[TMP26]], align 42131// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 22132// CHECK3-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 42133// CHECK3-NEXT: store i32 [[TMP29]], ptr [[TMP28]], align 42134// CHECK3-NEXT: [[TMP30:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, ptr @.omp_task_entry., i64 -1)2135// CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP30]], i32 0, i32 02136// CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP31]], i32 0, i32 02137// CHECK3-NEXT: [[TMP33:%.*]] = load ptr, ptr [[TMP32]], align 42138// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP33]], ptr align 4 [[AGG_CAPTURED]], i32 12, i1 false)2139// CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP30]], i32 0, i32 12140// CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP34]], i32 0, i32 02141// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP35]], ptr align 4 @.offload_sizes, i32 24, i1 false)2142// CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP34]], i32 0, i32 12143// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP36]], ptr align 4 [[TMP22]], i32 12, i1 false)2144// CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP34]], i32 0, i32 22145// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP37]], ptr align 4 [[TMP23]], i32 12, i1 false)2146// CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP34]], i32 0, i32 32147// CHECK3-NEXT: [[TMP39:%.*]] = load i16, ptr [[AA]], align 22148// CHECK3-NEXT: store i16 [[TMP39]], ptr [[TMP38]], align 42149// CHECK3-NEXT: [[TMP40:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB2]], i32 [[TMP0]], ptr [[TMP30]])2150// CHECK3-NEXT: [[TMP41:%.*]] = load i32, ptr [[A]], align 42151// CHECK3-NEXT: store i32 [[TMP41]], ptr [[A_CASTED]], align 42152// CHECK3-NEXT: [[TMP42:%.*]] = load i32, ptr [[A_CASTED]], align 42153// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107(i32 [[TMP42]]) #[[ATTR3:[0-9]+]]2154// CHECK3-NEXT: [[TMP43:%.*]] = load i16, ptr [[AA]], align 22155// CHECK3-NEXT: store i16 [[TMP43]], ptr [[AA_CASTED4]], align 22156// CHECK3-NEXT: [[TMP44:%.*]] = load i32, ptr [[AA_CASTED4]], align 42157// CHECK3-NEXT: [[TMP45:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 02158// CHECK3-NEXT: store i32 [[TMP44]], ptr [[TMP45]], align 42159// CHECK3-NEXT: [[TMP46:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 02160// CHECK3-NEXT: store i32 [[TMP44]], ptr [[TMP46]], align 42161// CHECK3-NEXT: [[TMP47:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 02162// CHECK3-NEXT: store ptr null, ptr [[TMP47]], align 42163// CHECK3-NEXT: [[TMP48:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 02164// CHECK3-NEXT: [[TMP49:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 02165// CHECK3-NEXT: [[TMP50:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 02166// CHECK3-NEXT: store i32 3, ptr [[TMP50]], align 42167// CHECK3-NEXT: [[TMP51:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12168// CHECK3-NEXT: store i32 1, ptr [[TMP51]], align 42169// CHECK3-NEXT: [[TMP52:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 22170// CHECK3-NEXT: store ptr [[TMP48]], ptr [[TMP52]], align 42171// CHECK3-NEXT: [[TMP53:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 32172// CHECK3-NEXT: store ptr [[TMP49]], ptr [[TMP53]], align 42173// CHECK3-NEXT: [[TMP54:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 42174// CHECK3-NEXT: store ptr @.offload_sizes.1, ptr [[TMP54]], align 42175// CHECK3-NEXT: [[TMP55:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 52176// CHECK3-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP55]], align 42177// CHECK3-NEXT: [[TMP56:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 62178// CHECK3-NEXT: store ptr null, ptr [[TMP56]], align 42179// CHECK3-NEXT: [[TMP57:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 72180// CHECK3-NEXT: store ptr null, ptr [[TMP57]], align 42181// CHECK3-NEXT: [[TMP58:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 82182// CHECK3-NEXT: store i64 10, ptr [[TMP58]], align 82183// CHECK3-NEXT: [[TMP59:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 92184// CHECK3-NEXT: store i64 0, ptr [[TMP59]], align 82185// CHECK3-NEXT: [[TMP60:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 102186// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP60]], align 42187// CHECK3-NEXT: [[TMP61:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 112188// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP61]], align 42189// CHECK3-NEXT: [[TMP62:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 122190// CHECK3-NEXT: store i32 0, ptr [[TMP62]], align 42191// CHECK3-NEXT: [[TMP63:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.region_id, ptr [[KERNEL_ARGS]])2192// CHECK3-NEXT: [[TMP64:%.*]] = icmp ne i32 [[TMP63]], 02193// CHECK3-NEXT: br i1 [[TMP64]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]2194// CHECK3: omp_offload.failed:2195// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113(i32 [[TMP44]]) #[[ATTR3]]2196// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]2197// CHECK3: omp_offload.cont:2198// CHECK3-NEXT: [[TMP65:%.*]] = load i32, ptr [[A]], align 42199// CHECK3-NEXT: store i32 [[TMP65]], ptr [[A_CASTED8]], align 42200// CHECK3-NEXT: [[TMP66:%.*]] = load i32, ptr [[A_CASTED8]], align 42201// CHECK3-NEXT: [[TMP67:%.*]] = load i16, ptr [[AA]], align 22202// CHECK3-NEXT: store i16 [[TMP67]], ptr [[AA_CASTED9]], align 22203// CHECK3-NEXT: [[TMP68:%.*]] = load i32, ptr [[AA_CASTED9]], align 42204// CHECK3-NEXT: [[TMP69:%.*]] = load i32, ptr [[N_ADDR]], align 42205// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP69]], 102206// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]2207// CHECK3: omp_if.then:2208// CHECK3-NEXT: [[TMP70:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 02209// CHECK3-NEXT: store i32 [[TMP66]], ptr [[TMP70]], align 42210// CHECK3-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 02211// CHECK3-NEXT: store i32 [[TMP66]], ptr [[TMP71]], align 42212// CHECK3-NEXT: [[TMP72:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i32 0, i32 02213// CHECK3-NEXT: store ptr null, ptr [[TMP72]], align 42214// CHECK3-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 12215// CHECK3-NEXT: store i32 [[TMP68]], ptr [[TMP73]], align 42216// CHECK3-NEXT: [[TMP74:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 12217// CHECK3-NEXT: store i32 [[TMP68]], ptr [[TMP74]], align 42218// CHECK3-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i32 0, i32 12219// CHECK3-NEXT: store ptr null, ptr [[TMP75]], align 42220// CHECK3-NEXT: [[TMP76:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 02221// CHECK3-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 02222// CHECK3-NEXT: [[TMP78:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 02223// CHECK3-NEXT: store i32 3, ptr [[TMP78]], align 42224// CHECK3-NEXT: [[TMP79:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 12225// CHECK3-NEXT: store i32 2, ptr [[TMP79]], align 42226// CHECK3-NEXT: [[TMP80:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 22227// CHECK3-NEXT: store ptr [[TMP76]], ptr [[TMP80]], align 42228// CHECK3-NEXT: [[TMP81:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 32229// CHECK3-NEXT: store ptr [[TMP77]], ptr [[TMP81]], align 42230// CHECK3-NEXT: [[TMP82:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 42231// CHECK3-NEXT: store ptr @.offload_sizes.3, ptr [[TMP82]], align 42232// CHECK3-NEXT: [[TMP83:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 52233// CHECK3-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP83]], align 42234// CHECK3-NEXT: [[TMP84:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 62235// CHECK3-NEXT: store ptr null, ptr [[TMP84]], align 42236// CHECK3-NEXT: [[TMP85:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 72237// CHECK3-NEXT: store ptr null, ptr [[TMP85]], align 42238// CHECK3-NEXT: [[TMP86:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 82239// CHECK3-NEXT: store i64 10, ptr [[TMP86]], align 82240// CHECK3-NEXT: [[TMP87:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 92241// CHECK3-NEXT: store i64 0, ptr [[TMP87]], align 82242// CHECK3-NEXT: [[TMP88:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 102243// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP88]], align 42244// CHECK3-NEXT: [[TMP89:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 112245// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP89]], align 42246// CHECK3-NEXT: [[TMP90:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 122247// CHECK3-NEXT: store i32 0, ptr [[TMP90]], align 42248// CHECK3-NEXT: [[TMP91:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.region_id, ptr [[KERNEL_ARGS14]])2249// CHECK3-NEXT: [[TMP92:%.*]] = icmp ne i32 [[TMP91]], 02250// CHECK3-NEXT: br i1 [[TMP92]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]]2251// CHECK3: omp_offload.failed15:2252// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i32 [[TMP66]], i32 [[TMP68]]) #[[ATTR3]]2253// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT16]]2254// CHECK3: omp_offload.cont16:2255// CHECK3-NEXT: br label [[OMP_IF_END:%.*]]2256// CHECK3: omp_if.else:2257// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i32 [[TMP66]], i32 [[TMP68]]) #[[ATTR3]]2258// CHECK3-NEXT: br label [[OMP_IF_END]]2259// CHECK3: omp_if.end:2260// CHECK3-NEXT: [[TMP93:%.*]] = load i32, ptr [[N_ADDR]], align 42261// CHECK3-NEXT: store i32 [[TMP93]], ptr [[DOTCAPTURE_EXPR_17]], align 42262// CHECK3-NEXT: [[TMP94:%.*]] = load i32, ptr [[A]], align 42263// CHECK3-NEXT: store i32 [[TMP94]], ptr [[A_CASTED18]], align 42264// CHECK3-NEXT: [[TMP95:%.*]] = load i32, ptr [[A_CASTED18]], align 42265// CHECK3-NEXT: [[TMP96:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 42266// CHECK3-NEXT: store i32 [[TMP96]], ptr [[DOTCAPTURE_EXPR__CASTED19]], align 42267// CHECK3-NEXT: [[TMP97:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED19]], align 42268// CHECK3-NEXT: [[TMP98:%.*]] = load i32, ptr [[N_ADDR]], align 42269// CHECK3-NEXT: [[CMP20:%.*]] = icmp sgt i32 [[TMP98]], 202270// CHECK3-NEXT: br i1 [[CMP20]], label [[OMP_IF_THEN21:%.*]], label [[OMP_IF_ELSE29:%.*]]2271// CHECK3: omp_if.then21:2272// CHECK3-NEXT: [[TMP99:%.*]] = mul nuw i32 [[TMP1]], 42273// CHECK3-NEXT: [[TMP100:%.*]] = sext i32 [[TMP99]] to i642274// CHECK3-NEXT: [[TMP101:%.*]] = mul nuw i32 5, [[TMP3]]2275// CHECK3-NEXT: [[TMP102:%.*]] = mul nuw i32 [[TMP101]], 82276// CHECK3-NEXT: [[TMP103:%.*]] = sext i32 [[TMP102]] to i642277// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.5, i32 80, i1 false)2278// CHECK3-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 02279// CHECK3-NEXT: store i32 [[TMP95]], ptr [[TMP104]], align 42280// CHECK3-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 02281// CHECK3-NEXT: store i32 [[TMP95]], ptr [[TMP105]], align 42282// CHECK3-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 02283// CHECK3-NEXT: store ptr null, ptr [[TMP106]], align 42284// CHECK3-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 12285// CHECK3-NEXT: store ptr [[B]], ptr [[TMP107]], align 42286// CHECK3-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 12287// CHECK3-NEXT: store ptr [[B]], ptr [[TMP108]], align 42288// CHECK3-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 12289// CHECK3-NEXT: store ptr null, ptr [[TMP109]], align 42290// CHECK3-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 22291// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP110]], align 42292// CHECK3-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 22293// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP111]], align 42294// CHECK3-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 22295// CHECK3-NEXT: store ptr null, ptr [[TMP112]], align 42296// CHECK3-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 32297// CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP113]], align 42298// CHECK3-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 32299// CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP114]], align 42300// CHECK3-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 32301// CHECK3-NEXT: store i64 [[TMP100]], ptr [[TMP115]], align 42302// CHECK3-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 32303// CHECK3-NEXT: store ptr null, ptr [[TMP116]], align 42304// CHECK3-NEXT: [[TMP117:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 42305// CHECK3-NEXT: store ptr [[C]], ptr [[TMP117]], align 42306// CHECK3-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 42307// CHECK3-NEXT: store ptr [[C]], ptr [[TMP118]], align 42308// CHECK3-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 42309// CHECK3-NEXT: store ptr null, ptr [[TMP119]], align 42310// CHECK3-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 52311// CHECK3-NEXT: store i32 5, ptr [[TMP120]], align 42312// CHECK3-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 52313// CHECK3-NEXT: store i32 5, ptr [[TMP121]], align 42314// CHECK3-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 52315// CHECK3-NEXT: store ptr null, ptr [[TMP122]], align 42316// CHECK3-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 62317// CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP123]], align 42318// CHECK3-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 62319// CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP124]], align 42320// CHECK3-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 62321// CHECK3-NEXT: store ptr null, ptr [[TMP125]], align 42322// CHECK3-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 72323// CHECK3-NEXT: store ptr [[VLA1]], ptr [[TMP126]], align 42324// CHECK3-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 72325// CHECK3-NEXT: store ptr [[VLA1]], ptr [[TMP127]], align 42326// CHECK3-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 72327// CHECK3-NEXT: store i64 [[TMP103]], ptr [[TMP128]], align 42328// CHECK3-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 72329// CHECK3-NEXT: store ptr null, ptr [[TMP129]], align 42330// CHECK3-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 82331// CHECK3-NEXT: store ptr [[D]], ptr [[TMP130]], align 42332// CHECK3-NEXT: [[TMP131:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 82333// CHECK3-NEXT: store ptr [[D]], ptr [[TMP131]], align 42334// CHECK3-NEXT: [[TMP132:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 82335// CHECK3-NEXT: store ptr null, ptr [[TMP132]], align 42336// CHECK3-NEXT: [[TMP133:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 92337// CHECK3-NEXT: store i32 [[TMP97]], ptr [[TMP133]], align 42338// CHECK3-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 92339// CHECK3-NEXT: store i32 [[TMP97]], ptr [[TMP134]], align 42340// CHECK3-NEXT: [[TMP135:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 92341// CHECK3-NEXT: store ptr null, ptr [[TMP135]], align 42342// CHECK3-NEXT: [[TMP136:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 02343// CHECK3-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 02344// CHECK3-NEXT: [[TMP138:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 02345// CHECK3-NEXT: [[TMP139:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 02346// CHECK3-NEXT: store i32 3, ptr [[TMP139]], align 42347// CHECK3-NEXT: [[TMP140:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 12348// CHECK3-NEXT: store i32 10, ptr [[TMP140]], align 42349// CHECK3-NEXT: [[TMP141:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 22350// CHECK3-NEXT: store ptr [[TMP136]], ptr [[TMP141]], align 42351// CHECK3-NEXT: [[TMP142:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 32352// CHECK3-NEXT: store ptr [[TMP137]], ptr [[TMP142]], align 42353// CHECK3-NEXT: [[TMP143:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 42354// CHECK3-NEXT: store ptr [[TMP138]], ptr [[TMP143]], align 42355// CHECK3-NEXT: [[TMP144:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 52356// CHECK3-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP144]], align 42357// CHECK3-NEXT: [[TMP145:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 62358// CHECK3-NEXT: store ptr null, ptr [[TMP145]], align 42359// CHECK3-NEXT: [[TMP146:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 72360// CHECK3-NEXT: store ptr null, ptr [[TMP146]], align 42361// CHECK3-NEXT: [[TMP147:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 82362// CHECK3-NEXT: store i64 10, ptr [[TMP147]], align 82363// CHECK3-NEXT: [[TMP148:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 92364// CHECK3-NEXT: store i64 0, ptr [[TMP148]], align 82365// CHECK3-NEXT: [[TMP149:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 102366// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP149]], align 42367// CHECK3-NEXT: [[TMP150:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 112368// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP150]], align 42369// CHECK3-NEXT: [[TMP151:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 122370// CHECK3-NEXT: store i32 0, ptr [[TMP151]], align 42371// CHECK3-NEXT: [[TMP152:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.region_id, ptr [[KERNEL_ARGS26]])2372// CHECK3-NEXT: [[TMP153:%.*]] = icmp ne i32 [[TMP152]], 02373// CHECK3-NEXT: br i1 [[TMP153]], label [[OMP_OFFLOAD_FAILED27:%.*]], label [[OMP_OFFLOAD_CONT28:%.*]]2374// CHECK3: omp_offload.failed27:2375// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i32 [[TMP95]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP97]]) #[[ATTR3]]2376// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT28]]2377// CHECK3: omp_offload.cont28:2378// CHECK3-NEXT: br label [[OMP_IF_END30:%.*]]2379// CHECK3: omp_if.else29:2380// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i32 [[TMP95]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP97]]) #[[ATTR3]]2381// CHECK3-NEXT: br label [[OMP_IF_END30]]2382// CHECK3: omp_if.end30:2383// CHECK3-NEXT: [[TMP154:%.*]] = load i32, ptr [[A]], align 42384// CHECK3-NEXT: [[TMP155:%.*]] = load ptr, ptr [[SAVED_STACK]], align 42385// CHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP155]])2386// CHECK3-NEXT: ret i32 [[TMP154]]2387//2388//2389// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1032390// CHECK3-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {2391// CHECK3-NEXT: entry:2392// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 42393// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 42394// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 42395// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 42396// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])2397// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 42398// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 42399// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 42400// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 42401// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 42402// CHECK3-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])2403// CHECK3-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 22404// CHECK3-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 22405// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 42406// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined, i32 [[TMP4]])2407// CHECK3-NEXT: ret void2408//2409//2410// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined2411// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {2412// CHECK3-NEXT: entry:2413// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 42414// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 42415// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 42416// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 42417// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 42418// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 42419// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 42420// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42421// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42422// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 42423// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 42424// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 42425// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 42426// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 42427// CHECK3-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 42428// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 42429// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 42430// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 42431// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 42432// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)2433// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42434// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 92435// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2436// CHECK3: cond.true:2437// CHECK3-NEXT: br label [[COND_END:%.*]]2438// CHECK3: cond.false:2439// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42440// CHECK3-NEXT: br label [[COND_END]]2441// CHECK3: cond.end:2442// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]2443// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 42444// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42445// CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 42446// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]2447// CHECK3: omp.inner.for.cond:2448// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42449// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42450// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]2451// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2452// CHECK3: omp.inner.for.body:2453// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42454// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 12455// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]2456// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 42457// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]2458// CHECK3: omp.body.continue:2459// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]2460// CHECK3: omp.inner.for.inc:2461// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42462// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 12463// CHECK3-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 42464// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]2465// CHECK3: omp.inner.for.end:2466// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]2467// CHECK3: omp.loop.exit:2468// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])2469// CHECK3-NEXT: ret void2470//2471//2472// CHECK3-LABEL: define {{[^@]+}}@.omp_task_privates_map.2473// CHECK3-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] {2474// CHECK3-NEXT: entry:2475// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 42476// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 42477// CHECK3-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 42478// CHECK3-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 42479// CHECK3-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 42480// CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 42481// CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 42482// CHECK3-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 42483// CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3]], align 42484// CHECK3-NEXT: store ptr [[TMP4]], ptr [[DOTADDR4]], align 42485// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 42486// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP5]], i32 0, i32 02487// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTADDR4]], align 42488// CHECK3-NEXT: store ptr [[TMP6]], ptr [[TMP7]], align 42489// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 12490// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTADDR2]], align 42491// CHECK3-NEXT: store ptr [[TMP8]], ptr [[TMP9]], align 42492// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 22493// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTADDR3]], align 42494// CHECK3-NEXT: store ptr [[TMP10]], ptr [[TMP11]], align 42495// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 32496// CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTADDR1]], align 42497// CHECK3-NEXT: store ptr [[TMP12]], ptr [[TMP13]], align 42498// CHECK3-NEXT: ret void2499//2500//2501// CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry.2502// CHECK3-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {2503// CHECK3-NEXT: entry:2504// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 42505// CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 42506// CHECK3-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 42507// CHECK3-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 42508// CHECK3-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 42509// CHECK3-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 42510// CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 42511// CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 42512// CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca ptr, align 42513// CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca ptr, align 42514// CHECK3-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 82515// CHECK3-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 42516// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 42517// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 42518// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i32, align 42519// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 42520// CHECK3-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 42521// CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 42522// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 42523// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 42524// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 02525// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 22526// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 02527// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 42528// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 12529// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]])2530// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])2531// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])2532// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])2533// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META22:![0-9]+]]2534// CHECK3-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 4, !noalias [[META22]]2535// CHECK3-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias [[META22]]2536// CHECK3-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias [[META22]]2537// CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 4, !noalias [[META22]]2538// CHECK3-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 4, !noalias [[META22]]2539// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias [[META22]]2540// CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias [[META22]]2541// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias [[META22]]2542// CHECK3-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]2543// CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias [[META22]]2544// CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias [[META22]]2545// CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias [[META22]]2546// CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias [[META22]]2547// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP9]], i32 0, i32 12548// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 22549// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP16]], align 42550// CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP17]], align 42551// CHECK3-NEXT: [[TMP20:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP18]], 02552// CHECK3-NEXT: [[TMP21:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP19]], 02553// CHECK3-NEXT: store i32 3, ptr [[KERNEL_ARGS_I]], align 4, !noalias [[META22]]2554// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 12555// CHECK3-NEXT: store i32 3, ptr [[TMP22]], align 4, !noalias [[META22]]2556// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 22557// CHECK3-NEXT: store ptr [[TMP13]], ptr [[TMP23]], align 4, !noalias [[META22]]2558// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 32559// CHECK3-NEXT: store ptr [[TMP14]], ptr [[TMP24]], align 4, !noalias [[META22]]2560// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 42561// CHECK3-NEXT: store ptr [[TMP15]], ptr [[TMP25]], align 4, !noalias [[META22]]2562// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 52563// CHECK3-NEXT: store ptr @.offload_maptypes, ptr [[TMP26]], align 4, !noalias [[META22]]2564// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 62565// CHECK3-NEXT: store ptr null, ptr [[TMP27]], align 4, !noalias [[META22]]2566// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 72567// CHECK3-NEXT: store ptr null, ptr [[TMP28]], align 4, !noalias [[META22]]2568// CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 82569// CHECK3-NEXT: store i64 10, ptr [[TMP29]], align 8, !noalias [[META22]]2570// CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 92571// CHECK3-NEXT: store i64 1, ptr [[TMP30]], align 8, !noalias [[META22]]2572// CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 102573// CHECK3-NEXT: store [3 x i32] [[TMP20]], ptr [[TMP31]], align 4, !noalias [[META22]]2574// CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 112575// CHECK3-NEXT: store [3 x i32] [[TMP21]], ptr [[TMP32]], align 4, !noalias [[META22]]2576// CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 122577// CHECK3-NEXT: store i32 0, ptr [[TMP33]], align 4, !noalias [[META22]]2578// CHECK3-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 [[TMP18]], i32 [[TMP19]], ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, ptr [[KERNEL_ARGS_I]])2579// CHECK3-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 02580// CHECK3-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]]2581// CHECK3: omp_offload.failed.i:2582// CHECK3-NEXT: [[TMP36:%.*]] = load i16, ptr [[TMP12]], align 22583// CHECK3-NEXT: store i16 [[TMP36]], ptr [[AA_CASTED_I]], align 2, !noalias [[META22]]2584// CHECK3-NEXT: [[TMP37:%.*]] = load i32, ptr [[AA_CASTED_I]], align 4, !noalias [[META22]]2585// CHECK3-NEXT: [[TMP38:%.*]] = load i32, ptr [[TMP16]], align 42586// CHECK3-NEXT: store i32 [[TMP38]], ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias [[META22]]2587// CHECK3-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias [[META22]]2588// CHECK3-NEXT: [[TMP40:%.*]] = load i32, ptr [[TMP17]], align 42589// CHECK3-NEXT: store i32 [[TMP40]], ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias [[META22]]2590// CHECK3-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias [[META22]]2591// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103(i32 [[TMP37]], i32 [[TMP39]], i32 [[TMP41]]) #[[ATTR3]]2592// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__EXIT]]2593// CHECK3: .omp_outlined..exit:2594// CHECK3-NEXT: ret i32 02595//2596//2597// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1072598// CHECK3-SAME: (i32 noundef [[A:%.*]]) #[[ATTR2]] {2599// CHECK3-NEXT: entry:2600// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 42601// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 42602// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 42603// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 42604// CHECK3-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 42605// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 42606// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107.omp_outlined, i32 [[TMP1]])2607// CHECK3-NEXT: ret void2608//2609//2610// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107.omp_outlined2611// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] {2612// CHECK3-NEXT: entry:2613// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 42614// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 42615// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 42616// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 42617// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 42618// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 42619// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 42620// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42621// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42622// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 42623// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 42624// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 42625// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 42626// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 42627// CHECK3-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 42628// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 42629// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 42630// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 42631// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 42632// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)2633// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42634// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 92635// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2636// CHECK3: cond.true:2637// CHECK3-NEXT: br label [[COND_END:%.*]]2638// CHECK3: cond.false:2639// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42640// CHECK3-NEXT: br label [[COND_END]]2641// CHECK3: cond.end:2642// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]2643// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 42644// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42645// CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 42646// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]2647// CHECK3: omp.inner.for.cond:2648// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42649// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42650// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]2651// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2652// CHECK3: omp.inner.for.body:2653// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42654// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 12655// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]2656// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 42657// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 42658// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 12659// CHECK3-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 42660// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]2661// CHECK3: omp.body.continue:2662// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]2663// CHECK3: omp.inner.for.inc:2664// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42665// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 12666// CHECK3-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 42667// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]2668// CHECK3: omp.inner.for.end:2669// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]2670// CHECK3: omp.loop.exit:2671// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])2672// CHECK3-NEXT: ret void2673//2674//2675// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1132676// CHECK3-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] {2677// CHECK3-NEXT: entry:2678// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 42679// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 42680// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 42681// CHECK3-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 22682// CHECK3-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 22683// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 42684// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.omp_outlined, i32 [[TMP1]])2685// CHECK3-NEXT: ret void2686//2687//2688// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.omp_outlined2689// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {2690// CHECK3-NEXT: entry:2691// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 42692// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 42693// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 42694// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 42695// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 42696// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 42697// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 42698// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42699// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42700// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 42701// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 42702// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 42703// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 42704// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 42705// CHECK3-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 42706// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 42707// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 42708// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 42709// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 42710// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)2711// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42712// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 92713// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2714// CHECK3: cond.true:2715// CHECK3-NEXT: br label [[COND_END:%.*]]2716// CHECK3: cond.false:2717// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42718// CHECK3-NEXT: br label [[COND_END]]2719// CHECK3: cond.end:2720// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]2721// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 42722// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42723// CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 42724// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]2725// CHECK3: omp.inner.for.cond:2726// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42727// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42728// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]2729// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2730// CHECK3: omp.inner.for.body:2731// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42732// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 12733// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]2734// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 42735// CHECK3-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 22736// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP8]] to i322737// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 12738// CHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i162739// CHECK3-NEXT: store i16 [[CONV3]], ptr [[AA_ADDR]], align 22740// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]2741// CHECK3: omp.body.continue:2742// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]2743// CHECK3: omp.inner.for.inc:2744// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42745// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 12746// CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 42747// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]2748// CHECK3: omp.inner.for.end:2749// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]2750// CHECK3: omp.loop.exit:2751// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])2752// CHECK3-NEXT: ret void2753//2754//2755// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1202756// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {2757// CHECK3-NEXT: entry:2758// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 42759// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 42760// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 42761// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 42762// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 42763// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 42764// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 42765// CHECK3-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 42766// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 42767// CHECK3-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 22768// CHECK3-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 22769// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 42770// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.omp_outlined, i32 [[TMP1]], i32 [[TMP3]])2771// CHECK3-NEXT: ret void2772//2773//2774// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.omp_outlined2775// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {2776// CHECK3-NEXT: entry:2777// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 42778// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 42779// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 42780// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 42781// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 42782// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 42783// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 42784// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 42785// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42786// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42787// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 42788// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 42789// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 42790// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 42791// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 42792// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 42793// CHECK3-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 42794// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 42795// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 42796// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 42797// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 42798// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)2799// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42800// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 92801// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2802// CHECK3: cond.true:2803// CHECK3-NEXT: br label [[COND_END:%.*]]2804// CHECK3: cond.false:2805// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42806// CHECK3-NEXT: br label [[COND_END]]2807// CHECK3: cond.end:2808// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]2809// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 42810// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42811// CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 42812// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]2813// CHECK3: omp.inner.for.cond:2814// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42815// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42816// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]2817// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2818// CHECK3: omp.inner.for.body:2819// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42820// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 12821// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]2822// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 42823// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 42824// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 12825// CHECK3-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 42826// CHECK3-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 22827// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i322828// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 12829// CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i162830// CHECK3-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 22831// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]2832// CHECK3: omp.body.continue:2833// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]2834// CHECK3: omp.inner.for.inc:2835// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42836// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 12837// CHECK3-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 42838// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]2839// CHECK3: omp.inner.for.end:2840// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]2841// CHECK3: omp.loop.exit:2842// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])2843// CHECK3-NEXT: ret void2844//2845//2846// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1452847// CHECK3-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {2848// CHECK3-NEXT: entry:2849// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 42850// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 42851// CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 42852// CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 42853// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 42854// CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 42855// CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 42856// CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 42857// CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 42858// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 42859// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 42860// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 42861// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 42862// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 42863// CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 42864// CHECK3-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 42865// CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 42866// CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 42867// CHECK3-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 42868// CHECK3-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 42869// CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 42870// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 42871// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 42872// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 42873// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 42874// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 42875// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 42876// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 42877// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 42878// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 42879// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 42880// CHECK3-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 42881// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 42882// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 42883// CHECK3-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 42884// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 42885// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i32 [[TMP11]])2886// CHECK3-NEXT: ret void2887//2888//2889// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.omp_outlined2890// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {2891// CHECK3-NEXT: entry:2892// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 42893// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 42894// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 42895// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 42896// CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 42897// CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 42898// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 42899// CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 42900// CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 42901// CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 42902// CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 42903// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 42904// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 42905// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 42906// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 42907// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 42908// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42909// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42910// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 42911// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 42912// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 42913// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 42914// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 42915// CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 42916// CHECK3-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 42917// CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 42918// CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 42919// CHECK3-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 42920// CHECK3-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 42921// CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 42922// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 42923// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 42924// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 42925// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 42926// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 42927// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 42928// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 42929// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 42930// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 42931// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 42932// CHECK3-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 42933// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 42934// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 42935// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 42936// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 42937// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 42938// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])2939// CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]]2940// CHECK3: omp.dispatch.cond:2941// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42942// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 92943// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2944// CHECK3: cond.true:2945// CHECK3-NEXT: br label [[COND_END:%.*]]2946// CHECK3: cond.false:2947// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42948// CHECK3-NEXT: br label [[COND_END]]2949// CHECK3: cond.end:2950// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]2951// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 42952// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42953// CHECK3-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 42954// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42955// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42956// CHECK3-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]2957// CHECK3-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]2958// CHECK3: omp.dispatch.body:2959// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]2960// CHECK3: omp.inner.for.cond:2961// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23:![0-9]+]]2962// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP23]]2963// CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]2964// CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2965// CHECK3: omp.inner.for.body:2966// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]]2967// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 12968// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]2969// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP23]]2970// CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP23]]2971// CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 12972// CHECK3-NEXT: store i32 [[ADD7]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP23]]2973// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 22974// CHECK3-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP23]]2975// CHECK3-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double2976// CHECK3-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+002977// CHECK3-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float2978// CHECK3-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP23]]2979// CHECK3-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 32980// CHECK3-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP23]]2981// CHECK3-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double2982// CHECK3-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+002983// CHECK3-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float2984// CHECK3-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP23]]2985// CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 12986// CHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i32 0, i32 22987// CHECK3-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP23]]2988// CHECK3-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+002989// CHECK3-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP23]]2990// CHECK3-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]2991// CHECK3-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP23]]2992// CHECK3-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i32 32993// CHECK3-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP23]]2994// CHECK3-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+002995// CHECK3-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP23]]2996// CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 02997// CHECK3-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP23]]2998// CHECK3-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 12999// CHECK3-NEXT: store i64 [[ADD20]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP23]]3000// CHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 13001// CHECK3-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP23]]3002// CHECK3-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i323003// CHECK3-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 13004// CHECK3-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i83005// CHECK3-NEXT: store i8 [[CONV23]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP23]]3006// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]3007// CHECK3: omp.body.continue:3008// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]3009// CHECK3: omp.inner.for.inc:3010// CHECK3-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]]3011// CHECK3-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 13012// CHECK3-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]]3013// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]3014// CHECK3: omp.inner.for.end:3015// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]3016// CHECK3: omp.dispatch.inc:3017// CHECK3-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 43018// CHECK3-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 43019// CHECK3-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]3020// CHECK3-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 43021// CHECK3-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43022// CHECK3-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 43023// CHECK3-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]3024// CHECK3-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 43025// CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]3026// CHECK3: omp.dispatch.end:3027// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]])3028// CHECK3-NEXT: ret void3029//3030//3031// CHECK3-LABEL: define {{[^@]+}}@_Z3bari3032// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {3033// CHECK3-NEXT: entry:3034// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 43035// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 43036// CHECK3-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 43037// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 43038// CHECK3-NEXT: store i32 0, ptr [[A]], align 43039// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 43040// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]])3041// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 43042// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]3043// CHECK3-NEXT: store i32 [[ADD]], ptr [[A]], align 43044// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 43045// CHECK3-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]])3046// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 43047// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]3048// CHECK3-NEXT: store i32 [[ADD2]], ptr [[A]], align 43049// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 43050// CHECK3-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]])3051// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 43052// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]3053// CHECK3-NEXT: store i32 [[ADD4]], ptr [[A]], align 43054// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 43055// CHECK3-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]])3056// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 43057// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]3058// CHECK3-NEXT: store i32 [[ADD6]], ptr [[A]], align 43059// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 43060// CHECK3-NEXT: ret i32 [[TMP8]]3061//3062//3063// CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei3064// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {3065// CHECK3-NEXT: entry:3066// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 43067// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 43068// CHECK3-NEXT: [[B:%.*]] = alloca i32, align 43069// CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 43070// CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 43071// CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 43072// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 43073// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 43074// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 43075// CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 43076// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 43077// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 83078// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 43079// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 43080// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 43081// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 43082// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 13083// CHECK3-NEXT: store i32 [[ADD]], ptr [[B]], align 43084// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 43085// CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()3086// CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 43087// CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]3088// CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 23089// CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 43090// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 43091// CHECK3-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 43092// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 43093// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 43094// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 603095// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]3096// CHECK3: omp_if.then:3097// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 03098// CHECK3-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]]3099// CHECK3-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 23100// CHECK3-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i643101// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.7, i32 40, i1 false)3102// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 03103// CHECK3-NEXT: store ptr [[THIS1]], ptr [[TMP10]], align 43104// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 03105// CHECK3-NEXT: store ptr [[A]], ptr [[TMP11]], align 43106// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 03107// CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 43108// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 13109// CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP13]], align 43110// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 13111// CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP14]], align 43112// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 13113// CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 43114// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 23115// CHECK3-NEXT: store i32 2, ptr [[TMP16]], align 43116// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 23117// CHECK3-NEXT: store i32 2, ptr [[TMP17]], align 43118// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 23119// CHECK3-NEXT: store ptr null, ptr [[TMP18]], align 43120// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 33121// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP19]], align 43122// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 33123// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP20]], align 43124// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 33125// CHECK3-NEXT: store ptr null, ptr [[TMP21]], align 43126// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 43127// CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP22]], align 43128// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 43129// CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP23]], align 43130// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 43131// CHECK3-NEXT: store i64 [[TMP9]], ptr [[TMP24]], align 43132// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 43133// CHECK3-NEXT: store ptr null, ptr [[TMP25]], align 43134// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 03135// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 03136// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 03137// CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 03138// CHECK3-NEXT: store i32 3, ptr [[TMP29]], align 43139// CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 13140// CHECK3-NEXT: store i32 5, ptr [[TMP30]], align 43141// CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 23142// CHECK3-NEXT: store ptr [[TMP26]], ptr [[TMP31]], align 43143// CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 33144// CHECK3-NEXT: store ptr [[TMP27]], ptr [[TMP32]], align 43145// CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 43146// CHECK3-NEXT: store ptr [[TMP28]], ptr [[TMP33]], align 43147// CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 53148// CHECK3-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP34]], align 43149// CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 63150// CHECK3-NEXT: store ptr null, ptr [[TMP35]], align 43151// CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 73152// CHECK3-NEXT: store ptr null, ptr [[TMP36]], align 43153// CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 83154// CHECK3-NEXT: store i64 10, ptr [[TMP37]], align 83155// CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 93156// CHECK3-NEXT: store i64 0, ptr [[TMP38]], align 83157// CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 103158// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP39]], align 43159// CHECK3-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 113160// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP40]], align 43161// CHECK3-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 123162// CHECK3-NEXT: store i32 0, ptr [[TMP41]], align 43163// CHECK3-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.region_id, ptr [[KERNEL_ARGS]])3164// CHECK3-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 03165// CHECK3-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]3166// CHECK3: omp_offload.failed:3167// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3]]3168// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]3169// CHECK3: omp_offload.cont:3170// CHECK3-NEXT: br label [[OMP_IF_END:%.*]]3171// CHECK3: omp_if.else:3172// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3]]3173// CHECK3-NEXT: br label [[OMP_IF_END]]3174// CHECK3: omp_if.end:3175// CHECK3-NEXT: [[TMP44:%.*]] = mul nsw i32 1, [[TMP1]]3176// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP44]]3177// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 13178// CHECK3-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 23179// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i323180// CHECK3-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 43181// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]]3182// CHECK3-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 43183// CHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP47]])3184// CHECK3-NEXT: ret i32 [[ADD3]]3185//3186//3187// CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici3188// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {3189// CHECK3-NEXT: entry:3190// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 43191// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 43192// CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 23193// CHECK3-NEXT: [[AAA:%.*]] = alloca i8, align 13194// CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 43195// CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i32, align 43196// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 43197// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 43198// CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 43199// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 43200// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 43201// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 43202// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 43203// CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 43204// CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 43205// CHECK3-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 43206// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 83207// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 43208// CHECK3-NEXT: store i32 0, ptr [[A]], align 43209// CHECK3-NEXT: store i16 0, ptr [[AA]], align 23210// CHECK3-NEXT: store i8 0, ptr [[AAA]], align 13211// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 43212// CHECK3-NEXT: store i32 [[TMP0]], ptr [[N_CASTED]], align 43213// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_CASTED]], align 43214// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 43215// CHECK3-NEXT: store i32 [[TMP2]], ptr [[A_CASTED]], align 43216// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[A_CASTED]], align 43217// CHECK3-NEXT: [[TMP4:%.*]] = load i16, ptr [[AA]], align 23218// CHECK3-NEXT: store i16 [[TMP4]], ptr [[AA_CASTED]], align 23219// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[AA_CASTED]], align 43220// CHECK3-NEXT: [[TMP6:%.*]] = load i8, ptr [[AAA]], align 13221// CHECK3-NEXT: store i8 [[TMP6]], ptr [[AAA_CASTED]], align 13222// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[AAA_CASTED]], align 43223// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[N_ADDR]], align 43224// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 503225// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]3226// CHECK3: omp_if.then:3227// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 03228// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP9]], align 43229// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 03230// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP10]], align 43231// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 03232// CHECK3-NEXT: store ptr null, ptr [[TMP11]], align 43233// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 13234// CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP12]], align 43235// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 13236// CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP13]], align 43237// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 13238// CHECK3-NEXT: store ptr null, ptr [[TMP14]], align 43239// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 23240// CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP15]], align 43241// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 23242// CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP16]], align 43243// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 23244// CHECK3-NEXT: store ptr null, ptr [[TMP17]], align 43245// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 33246// CHECK3-NEXT: store i32 [[TMP7]], ptr [[TMP18]], align 43247// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 33248// CHECK3-NEXT: store i32 [[TMP7]], ptr [[TMP19]], align 43249// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 33250// CHECK3-NEXT: store ptr null, ptr [[TMP20]], align 43251// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 43252// CHECK3-NEXT: store ptr [[B]], ptr [[TMP21]], align 43253// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 43254// CHECK3-NEXT: store ptr [[B]], ptr [[TMP22]], align 43255// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 43256// CHECK3-NEXT: store ptr null, ptr [[TMP23]], align 43257// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 03258// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 03259// CHECK3-NEXT: [[TMP26:%.*]] = load i32, ptr [[A]], align 43260// CHECK3-NEXT: store i32 [[TMP26]], ptr [[DOTCAPTURE_EXPR_]], align 43261// CHECK3-NEXT: [[TMP27:%.*]] = load i32, ptr [[N_ADDR]], align 43262// CHECK3-NEXT: store i32 [[TMP27]], ptr [[DOTCAPTURE_EXPR_1]], align 43263// CHECK3-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 43264// CHECK3-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 43265// CHECK3-NEXT: [[SUB:%.*]] = sub i32 [[TMP28]], [[TMP29]]3266// CHECK3-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 13267// CHECK3-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 13268// CHECK3-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 13269// CHECK3-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 13270// CHECK3-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 43271// CHECK3-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 43272// CHECK3-NEXT: [[ADD5:%.*]] = add i32 [[TMP30]], 13273// CHECK3-NEXT: [[TMP31:%.*]] = zext i32 [[ADD5]] to i643274// CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 03275// CHECK3-NEXT: store i32 3, ptr [[TMP32]], align 43276// CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 13277// CHECK3-NEXT: store i32 5, ptr [[TMP33]], align 43278// CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 23279// CHECK3-NEXT: store ptr [[TMP24]], ptr [[TMP34]], align 43280// CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 33281// CHECK3-NEXT: store ptr [[TMP25]], ptr [[TMP35]], align 43282// CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 43283// CHECK3-NEXT: store ptr @.offload_sizes.9, ptr [[TMP36]], align 43284// CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 53285// CHECK3-NEXT: store ptr @.offload_maptypes.10, ptr [[TMP37]], align 43286// CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 63287// CHECK3-NEXT: store ptr null, ptr [[TMP38]], align 43288// CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 73289// CHECK3-NEXT: store ptr null, ptr [[TMP39]], align 43290// CHECK3-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 83291// CHECK3-NEXT: store i64 [[TMP31]], ptr [[TMP40]], align 83292// CHECK3-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 93293// CHECK3-NEXT: store i64 0, ptr [[TMP41]], align 83294// CHECK3-NEXT: [[TMP42:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 103295// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP42]], align 43296// CHECK3-NEXT: [[TMP43:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 113297// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP43]], align 43298// CHECK3-NEXT: [[TMP44:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 123299// CHECK3-NEXT: store i32 0, ptr [[TMP44]], align 43300// CHECK3-NEXT: [[TMP45:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.region_id, ptr [[KERNEL_ARGS]])3301// CHECK3-NEXT: [[TMP46:%.*]] = icmp ne i32 [[TMP45]], 03302// CHECK3-NEXT: br i1 [[TMP46]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]3303// CHECK3: omp_offload.failed:3304// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], ptr [[B]]) #[[ATTR3]]3305// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]3306// CHECK3: omp_offload.cont:3307// CHECK3-NEXT: br label [[OMP_IF_END:%.*]]3308// CHECK3: omp_if.else:3309// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], ptr [[B]]) #[[ATTR3]]3310// CHECK3-NEXT: br label [[OMP_IF_END]]3311// CHECK3: omp_if.end:3312// CHECK3-NEXT: [[TMP47:%.*]] = load i32, ptr [[A]], align 43313// CHECK3-NEXT: ret i32 [[TMP47]]3314//3315//3316// CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i3317// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {3318// CHECK3-NEXT: entry:3319// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 43320// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 43321// CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 23322// CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 43323// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 43324// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 43325// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 43326// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 43327// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 43328// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 43329// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 83330// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 43331// CHECK3-NEXT: store i32 0, ptr [[A]], align 43332// CHECK3-NEXT: store i16 0, ptr [[AA]], align 23333// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 43334// CHECK3-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 43335// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 43336// CHECK3-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 23337// CHECK3-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 23338// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 43339// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 43340// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 403341// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]3342// CHECK3: omp_if.then:3343// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 03344// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP5]], align 43345// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 03346// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP6]], align 43347// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 03348// CHECK3-NEXT: store ptr null, ptr [[TMP7]], align 43349// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 13350// CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP8]], align 43351// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 13352// CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP9]], align 43353// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 13354// CHECK3-NEXT: store ptr null, ptr [[TMP10]], align 43355// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 23356// CHECK3-NEXT: store ptr [[B]], ptr [[TMP11]], align 43357// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 23358// CHECK3-NEXT: store ptr [[B]], ptr [[TMP12]], align 43359// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 23360// CHECK3-NEXT: store ptr null, ptr [[TMP13]], align 43361// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 03362// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 03363// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 03364// CHECK3-NEXT: store i32 3, ptr [[TMP16]], align 43365// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 13366// CHECK3-NEXT: store i32 3, ptr [[TMP17]], align 43367// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 23368// CHECK3-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 43369// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 33370// CHECK3-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 43371// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 43372// CHECK3-NEXT: store ptr @.offload_sizes.11, ptr [[TMP20]], align 43373// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 53374// CHECK3-NEXT: store ptr @.offload_maptypes.12, ptr [[TMP21]], align 43375// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 63376// CHECK3-NEXT: store ptr null, ptr [[TMP22]], align 43377// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 73378// CHECK3-NEXT: store ptr null, ptr [[TMP23]], align 43379// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 83380// CHECK3-NEXT: store i64 10, ptr [[TMP24]], align 83381// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 93382// CHECK3-NEXT: store i64 0, ptr [[TMP25]], align 83383// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 103384// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP26]], align 43385// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 113386// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP27]], align 43387// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 123388// CHECK3-NEXT: store i32 0, ptr [[TMP28]], align 43389// CHECK3-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.region_id, ptr [[KERNEL_ARGS]])3390// CHECK3-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 03391// CHECK3-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]3392// CHECK3: omp_offload.failed:3393// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]]3394// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]3395// CHECK3: omp_offload.cont:3396// CHECK3-NEXT: br label [[OMP_IF_END:%.*]]3397// CHECK3: omp_if.else:3398// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]]3399// CHECK3-NEXT: br label [[OMP_IF_END]]3400// CHECK3: omp_if.end:3401// CHECK3-NEXT: [[TMP31:%.*]] = load i32, ptr [[A]], align 43402// CHECK3-NEXT: ret i32 [[TMP31]]3403//3404//3405// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l2183406// CHECK3-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {3407// CHECK3-NEXT: entry:3408// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 43409// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 43410// CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 43411// CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 43412// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 43413// CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 43414// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 43415// CHECK3-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 43416// CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 43417// CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 43418// CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 43419// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 43420// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 43421// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 43422// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 43423// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 43424// CHECK3-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 43425// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 43426// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.omp_outlined, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]])3427// CHECK3-NEXT: ret void3428//3429//3430// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.omp_outlined3431// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {3432// CHECK3-NEXT: entry:3433// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 43434// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 43435// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 43436// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 43437// CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 43438// CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 43439// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 43440// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 43441// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 43442// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 43443// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 43444// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 43445// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 43446// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 43447// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 43448// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 43449// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 43450// CHECK3-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 43451// CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 43452// CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 43453// CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 43454// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 43455// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 43456// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 43457// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 43458// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 43459// CHECK3-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 43460// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 43461// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 43462// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 43463// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 43464// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)3465// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43466// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 93467// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]3468// CHECK3: cond.true:3469// CHECK3-NEXT: br label [[COND_END:%.*]]3470// CHECK3: cond.false:3471// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43472// CHECK3-NEXT: br label [[COND_END]]3473// CHECK3: cond.end:3474// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]3475// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 43476// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 43477// CHECK3-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 43478// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]3479// CHECK3: omp.inner.for.cond:3480// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43481// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43482// CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]3483// CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]3484// CHECK3: omp.inner.for.body:3485// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43486// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 13487// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]3488// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 43489// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 43490// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double3491// CHECK3-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+003492// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 03493// CHECK3-NEXT: store double [[ADD4]], ptr [[A]], align 43494// CHECK3-NEXT: [[A5:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 03495// CHECK3-NEXT: [[TMP13:%.*]] = load double, ptr [[A5]], align 43496// CHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+003497// CHECK3-NEXT: store double [[INC]], ptr [[A5]], align 43498// CHECK3-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i163499// CHECK3-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]3500// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP14]]3501// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 13502// CHECK3-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 23503// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]3504// CHECK3: omp.body.continue:3505// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]3506// CHECK3: omp.inner.for.inc:3507// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43508// CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 13509// CHECK3-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 43510// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]3511// CHECK3: omp.inner.for.end:3512// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]3513// CHECK3: omp.loop.exit:3514// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])3515// CHECK3-NEXT: ret void3516//3517//3518// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l2003519// CHECK3-SAME: (i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {3520// CHECK3-NEXT: entry:3521// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 43522// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 43523// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 43524// CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 43525// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 43526// CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i32, align 43527// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 43528// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 43529// CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 43530// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 43531// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 43532// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 43533// CHECK3-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 43534// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 43535// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 43536// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 43537// CHECK3-NEXT: store i32 [[TMP1]], ptr [[N_CASTED]], align 43538// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_CASTED]], align 43539// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[A_ADDR]], align 43540// CHECK3-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 43541// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_CASTED]], align 43542// CHECK3-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA_ADDR]], align 23543// CHECK3-NEXT: store i16 [[TMP5]], ptr [[AA_CASTED]], align 23544// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[AA_CASTED]], align 43545// CHECK3-NEXT: [[TMP7:%.*]] = load i8, ptr [[AAA_ADDR]], align 13546// CHECK3-NEXT: store i8 [[TMP7]], ptr [[AAA_CASTED]], align 13547// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[AAA_CASTED]], align 43548// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], ptr [[TMP0]])3549// CHECK3-NEXT: ret void3550//3551//3552// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.omp_outlined3553// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {3554// CHECK3-NEXT: entry:3555// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 43556// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 43557// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 43558// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 43559// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 43560// CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 43561// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 43562// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 43563// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 43564// CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 43565// CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 43566// CHECK3-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 43567// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 43568// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 43569// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 43570// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 43571// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 43572// CHECK3-NEXT: [[I5:%.*]] = alloca i32, align 43573// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 43574// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 43575// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 43576// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 43577// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 43578// CHECK3-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 43579// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 43580// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 43581// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 43582// CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 43583// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 43584// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_1]], align 43585// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 43586// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 43587// CHECK3-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]3588// CHECK3-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 13589// CHECK3-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 13590// CHECK3-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 13591// CHECK3-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 13592// CHECK3-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 43593// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 43594// CHECK3-NEXT: store i32 [[TMP5]], ptr [[I]], align 43595// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 43596// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 43597// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]3598// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]3599// CHECK3: omp.precond.then:3600// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 43601// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 43602// CHECK3-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_UB]], align 43603// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 43604// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 43605// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 43606// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 43607// CHECK3-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP10]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)3608// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43609// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 43610// CHECK3-NEXT: [[CMP6:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]3611// CHECK3-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]3612// CHECK3: cond.true:3613// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 43614// CHECK3-NEXT: br label [[COND_END:%.*]]3615// CHECK3: cond.false:3616// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43617// CHECK3-NEXT: br label [[COND_END]]3618// CHECK3: cond.end:3619// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]3620// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 43621// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_LB]], align 43622// CHECK3-NEXT: store i32 [[TMP15]], ptr [[DOTOMP_IV]], align 43623// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]3624// CHECK3: omp.inner.for.cond:3625// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43626// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43627// CHECK3-NEXT: [[ADD7:%.*]] = add i32 [[TMP17]], 13628// CHECK3-NEXT: [[CMP8:%.*]] = icmp ult i32 [[TMP16]], [[ADD7]]3629// CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]3630// CHECK3: omp.inner.for.body:3631// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 43632// CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43633// CHECK3-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 13634// CHECK3-NEXT: [[ADD9:%.*]] = add i32 [[TMP18]], [[MUL]]3635// CHECK3-NEXT: store i32 [[ADD9]], ptr [[I5]], align 43636// CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 43637// CHECK3-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 13638// CHECK3-NEXT: store i32 [[ADD10]], ptr [[A_ADDR]], align 43639// CHECK3-NEXT: [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 23640// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP21]] to i323641// CHECK3-NEXT: [[ADD11:%.*]] = add nsw i32 [[CONV]], 13642// CHECK3-NEXT: [[CONV12:%.*]] = trunc i32 [[ADD11]] to i163643// CHECK3-NEXT: store i16 [[CONV12]], ptr [[AA_ADDR]], align 23644// CHECK3-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 13645// CHECK3-NEXT: [[CONV13:%.*]] = sext i8 [[TMP22]] to i323646// CHECK3-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV13]], 13647// CHECK3-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i83648// CHECK3-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 13649// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 23650// CHECK3-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 43651// CHECK3-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP23]], 13652// CHECK3-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 43653// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]3654// CHECK3: omp.body.continue:3655// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]3656// CHECK3: omp.inner.for.inc:3657// CHECK3-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43658// CHECK3-NEXT: [[ADD17:%.*]] = add i32 [[TMP24]], 13659// CHECK3-NEXT: store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 43660// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]3661// CHECK3: omp.inner.for.end:3662// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]3663// CHECK3: omp.loop.exit:3664// CHECK3-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 43665// CHECK3-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 43666// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP26]])3667// CHECK3-NEXT: br label [[OMP_PRECOND_END]]3668// CHECK3: omp.precond.end:3669// CHECK3-NEXT: ret void3670//3671//3672// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l1833673// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {3674// CHECK3-NEXT: entry:3675// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 43676// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 43677// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 43678// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 43679// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 43680// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 43681// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 43682// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 43683// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 43684// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 43685// CHECK3-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 43686// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 43687// CHECK3-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 23688// CHECK3-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 23689// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 43690// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]])3691// CHECK3-NEXT: ret void3692//3693//3694// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.omp_outlined3695// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {3696// CHECK3-NEXT: entry:3697// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 43698// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 43699// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 43700// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 43701// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 43702// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 43703// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 43704// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 43705// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 43706// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 43707// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 43708// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 43709// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 43710// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 43711// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 43712// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 43713// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 43714// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 43715// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 43716// CHECK3-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 43717// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 43718// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 43719// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 43720// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 43721// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)3722// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43723// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 93724// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]3725// CHECK3: cond.true:3726// CHECK3-NEXT: br label [[COND_END:%.*]]3727// CHECK3: cond.false:3728// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43729// CHECK3-NEXT: br label [[COND_END]]3730// CHECK3: cond.end:3731// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]3732// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 43733// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 43734// CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 43735// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]3736// CHECK3: omp.inner.for.cond:3737// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43738// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43739// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]3740// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]3741// CHECK3: omp.inner.for.body:3742// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43743// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 13744// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]3745// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 43746// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 43747// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 13748// CHECK3-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 43749// CHECK3-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 23750// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i323751// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 13752// CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i163753// CHECK3-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 23754// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 23755// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 43756// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 13757// CHECK3-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 43758// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]3759// CHECK3: omp.body.continue:3760// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]3761// CHECK3: omp.inner.for.inc:3762// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43763// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 13764// CHECK3-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 43765// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]3766// CHECK3: omp.inner.for.end:3767// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]3768// CHECK3: omp.loop.exit:3769// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])3770// CHECK3-NEXT: ret void3771//3772//3773// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1033774// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {3775// CHECK9-NEXT: entry:3776// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 83777// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 83778// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 83779// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 83780// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 83781// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])3782// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 83783// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 83784// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 83785// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 83786// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 43787// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 43788// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])3789// CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 23790// CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 23791// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 83792// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined, i64 [[TMP4]])3793// CHECK9-NEXT: ret void3794//3795//3796// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined3797// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {3798// CHECK9-NEXT: entry:3799// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 83800// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 83801// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 83802// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 43803// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 43804// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 43805// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 43806// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 43807// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 43808// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 43809// CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 83810// CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 83811// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 83812// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 43813// CHECK9-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 43814// CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 43815// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 43816// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 83817// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 43818// CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)3819// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43820// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 93821// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]3822// CHECK9: cond.true:3823// CHECK9-NEXT: br label [[COND_END:%.*]]3824// CHECK9: cond.false:3825// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43826// CHECK9-NEXT: br label [[COND_END]]3827// CHECK9: cond.end:3828// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]3829// CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 43830// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 43831// CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 43832// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]3833// CHECK9: omp.inner.for.cond:3834// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43835// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43836// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]3837// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]3838// CHECK9: omp.inner.for.body:3839// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43840// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 13841// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]3842// CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 43843// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]3844// CHECK9: omp.body.continue:3845// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]3846// CHECK9: omp.inner.for.inc:3847// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43848// CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 13849// CHECK9-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 43850// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]3851// CHECK9: omp.inner.for.end:3852// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]3853// CHECK9: omp.loop.exit:3854// CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])3855// CHECK9-NEXT: ret void3856//3857//3858// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1133859// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {3860// CHECK9-NEXT: entry:3861// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 83862// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 83863// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 83864// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 83865// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 83866// CHECK9-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 23867// CHECK9-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 23868// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 83869// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.omp_outlined, i64 [[TMP1]])3870// CHECK9-NEXT: ret void3871//3872//3873// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.omp_outlined3874// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {3875// CHECK9-NEXT: entry:3876// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 83877// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 83878// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 83879// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 43880// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 43881// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 43882// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 43883// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 43884// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 43885// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 43886// CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 83887// CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 83888// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 83889// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 43890// CHECK9-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 43891// CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 43892// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 43893// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 83894// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 43895// CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)3896// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43897// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 93898// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]3899// CHECK9: cond.true:3900// CHECK9-NEXT: br label [[COND_END:%.*]]3901// CHECK9: cond.false:3902// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43903// CHECK9-NEXT: br label [[COND_END]]3904// CHECK9: cond.end:3905// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]3906// CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 43907// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 43908// CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 43909// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]3910// CHECK9: omp.inner.for.cond:3911// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43912// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43913// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]3914// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]3915// CHECK9: omp.inner.for.body:3916// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43917// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 13918// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]3919// CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 43920// CHECK9-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 23921// CHECK9-NEXT: [[CONV:%.*]] = sext i16 [[TMP8]] to i323922// CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 13923// CHECK9-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i163924// CHECK9-NEXT: store i16 [[CONV3]], ptr [[AA_ADDR]], align 23925// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]3926// CHECK9: omp.body.continue:3927// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]3928// CHECK9: omp.inner.for.inc:3929// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 43930// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 13931// CHECK9-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 43932// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]3933// CHECK9: omp.inner.for.end:3934// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]3935// CHECK9: omp.loop.exit:3936// CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])3937// CHECK9-NEXT: ret void3938//3939//3940// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1203941// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {3942// CHECK9-NEXT: entry:3943// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 83944// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 83945// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 83946// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 83947// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 83948// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 83949// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 83950// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 83951// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 43952// CHECK9-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 43953// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 83954// CHECK9-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 23955// CHECK9-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 23956// CHECK9-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 83957// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.omp_outlined, i64 [[TMP1]], i64 [[TMP3]])3958// CHECK9-NEXT: ret void3959//3960//3961// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.omp_outlined3962// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {3963// CHECK9-NEXT: entry:3964// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 83965// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 83966// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 83967// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 83968// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 43969// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 43970// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 43971// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 43972// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 43973// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 43974// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 43975// CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 83976// CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 83977// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 83978// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 83979// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 43980// CHECK9-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 43981// CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 43982// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 43983// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 83984// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 43985// CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)3986// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43987// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 93988// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]3989// CHECK9: cond.true:3990// CHECK9-NEXT: br label [[COND_END:%.*]]3991// CHECK9: cond.false:3992// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43993// CHECK9-NEXT: br label [[COND_END]]3994// CHECK9: cond.end:3995// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]3996// CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 43997// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 43998// CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 43999// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]4000// CHECK9: omp.inner.for.cond:4001// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44002// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44003// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]4004// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]4005// CHECK9: omp.inner.for.body:4006// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44007// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 14008// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]4009// CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 44010// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 44011// CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 14012// CHECK9-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 44013// CHECK9-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 24014// CHECK9-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i324015// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 14016// CHECK9-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i164017// CHECK9-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 24018// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]4019// CHECK9: omp.body.continue:4020// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]4021// CHECK9: omp.inner.for.inc:4022// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44023// CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 14024// CHECK9-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 44025// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]4026// CHECK9: omp.inner.for.end:4027// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]4028// CHECK9: omp.loop.exit:4029// CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])4030// CHECK9-NEXT: ret void4031//4032//4033// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1454034// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {4035// CHECK9-NEXT: entry:4036// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 84037// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 84038// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 84039// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 84040// CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 84041// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 84042// CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 84043// CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 84044// CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 84045// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 84046// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 84047// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 84048// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 84049// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 84050// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 84051// CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 84052// CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 84053// CHECK9-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 84054// CHECK9-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 84055// CHECK9-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 84056// CHECK9-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 84057// CHECK9-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 84058// CHECK9-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 84059// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 84060// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 84061// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 84062// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 84063// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 84064// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 84065// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 84066// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 84067// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 84068// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 44069// CHECK9-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 44070// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 84071// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 44072// CHECK9-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 44073// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 84074// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i64 [[TMP11]])4075// CHECK9-NEXT: ret void4076//4077//4078// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.omp_outlined4079// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {4080// CHECK9-NEXT: entry:4081// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 84082// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 84083// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 84084// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 84085// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 84086// CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 84087// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 84088// CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 84089// CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 84090// CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 84091// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 84092// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 84093// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 44094// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 44095// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 44096// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 44097// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 44098// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 44099// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 44100// CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 84101// CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 84102// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 84103// CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 84104// CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 84105// CHECK9-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 84106// CHECK9-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 84107// CHECK9-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 84108// CHECK9-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 84109// CHECK9-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 84110// CHECK9-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 84111// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 84112// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 84113// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 84114// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 84115// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 84116// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 84117// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 84118// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 84119// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 84120// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 44121// CHECK9-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 44122// CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 44123// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 44124// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 44125// CHECK9-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 84126// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 44127// CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])4128// CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]]4129// CHECK9: omp.dispatch.cond:4130// CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44131// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 94132// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]4133// CHECK9: cond.true:4134// CHECK9-NEXT: br label [[COND_END:%.*]]4135// CHECK9: cond.false:4136// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44137// CHECK9-NEXT: br label [[COND_END]]4138// CHECK9: cond.end:4139// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]4140// CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 44141// CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 44142// CHECK9-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 44143// CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44144// CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44145// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]4146// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]4147// CHECK9: omp.dispatch.body:4148// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]4149// CHECK9: omp.inner.for.cond:4150// CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13:![0-9]+]]4151// CHECK9-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP13]]4152// CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]4153// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]4154// CHECK9: omp.inner.for.body:4155// CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]4156// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 14157// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]4158// CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]]4159// CHECK9-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP13]]4160// CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 14161// CHECK9-NEXT: store i32 [[ADD7]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP13]]4162// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 24163// CHECK9-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP13]]4164// CHECK9-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double4165// CHECK9-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+004166// CHECK9-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float4167// CHECK9-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP13]]4168// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 34169// CHECK9-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP13]]4170// CHECK9-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double4171// CHECK9-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+004172// CHECK9-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float4173// CHECK9-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP13]]4174// CHECK9-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 14175// CHECK9-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i64 0, i64 24176// CHECK9-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP13]]4177// CHECK9-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+004178// CHECK9-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP13]]4179// CHECK9-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]4180// CHECK9-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP23]]4181// CHECK9-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i64 34182// CHECK9-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP13]]4183// CHECK9-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+004184// CHECK9-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP13]]4185// CHECK9-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 04186// CHECK9-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP13]]4187// CHECK9-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 14188// CHECK9-NEXT: store i64 [[ADD20]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP13]]4189// CHECK9-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 14190// CHECK9-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP13]]4191// CHECK9-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i324192// CHECK9-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 14193// CHECK9-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i84194// CHECK9-NEXT: store i8 [[CONV23]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP13]]4195// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]4196// CHECK9: omp.body.continue:4197// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]4198// CHECK9: omp.inner.for.inc:4199// CHECK9-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]4200// CHECK9-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 14201// CHECK9-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]4202// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]4203// CHECK9: omp.inner.for.end:4204// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]]4205// CHECK9: omp.dispatch.inc:4206// CHECK9-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 44207// CHECK9-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 44208// CHECK9-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]4209// CHECK9-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 44210// CHECK9-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44211// CHECK9-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 44212// CHECK9-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]4213// CHECK9-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 44214// CHECK9-NEXT: br label [[OMP_DISPATCH_COND]]4215// CHECK9: omp.dispatch.end:4216// CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]])4217// CHECK9-NEXT: ret void4218//4219//4220// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l2004221// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {4222// CHECK9-NEXT: entry:4223// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 84224// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 84225// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 84226// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 84227// CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 84228// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 84229// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 84230// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 84231// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 84232// CHECK9-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 84233// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 84234// CHECK9-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 84235// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 84236// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 84237// CHECK9-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 84238// CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 84239// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 84240// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 44241// CHECK9-NEXT: store i32 [[TMP1]], ptr [[N_CASTED]], align 44242// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[N_CASTED]], align 84243// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[A_ADDR]], align 44244// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 44245// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[A_CASTED]], align 84246// CHECK9-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA_ADDR]], align 24247// CHECK9-NEXT: store i16 [[TMP5]], ptr [[AA_CASTED]], align 24248// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[AA_CASTED]], align 84249// CHECK9-NEXT: [[TMP7:%.*]] = load i8, ptr [[AAA_ADDR]], align 14250// CHECK9-NEXT: store i8 [[TMP7]], ptr [[AAA_CASTED]], align 14251// CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[AAA_CASTED]], align 84252// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], ptr [[TMP0]])4253// CHECK9-NEXT: ret void4254//4255//4256// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.omp_outlined4257// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {4258// CHECK9-NEXT: entry:4259// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 84260// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 84261// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 84262// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 84263// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 84264// CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 84265// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 84266// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 44267// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 44268// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 44269// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 44270// CHECK9-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 44271// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 44272// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 44273// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 44274// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 44275// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 44276// CHECK9-NEXT: [[I5:%.*]] = alloca i32, align 44277// CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 84278// CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 84279// CHECK9-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 84280// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 84281// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 84282// CHECK9-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 84283// CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 84284// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 84285// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 44286// CHECK9-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 44287// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 44288// CHECK9-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_1]], align 44289// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 44290// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 44291// CHECK9-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]4292// CHECK9-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 14293// CHECK9-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 14294// CHECK9-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 14295// CHECK9-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 14296// CHECK9-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 44297// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 44298// CHECK9-NEXT: store i32 [[TMP5]], ptr [[I]], align 44299// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 44300// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 44301// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]4302// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]4303// CHECK9: omp.precond.then:4304// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 44305// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 44306// CHECK9-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_UB]], align 44307// CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 44308// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 44309// CHECK9-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 84310// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 44311// CHECK9-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP10]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)4312// CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44313// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 44314// CHECK9-NEXT: [[CMP6:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]4315// CHECK9-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]4316// CHECK9: cond.true:4317// CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 44318// CHECK9-NEXT: br label [[COND_END:%.*]]4319// CHECK9: cond.false:4320// CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44321// CHECK9-NEXT: br label [[COND_END]]4322// CHECK9: cond.end:4323// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]4324// CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 44325// CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_LB]], align 44326// CHECK9-NEXT: store i32 [[TMP15]], ptr [[DOTOMP_IV]], align 44327// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]4328// CHECK9: omp.inner.for.cond:4329// CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44330// CHECK9-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44331// CHECK9-NEXT: [[ADD7:%.*]] = add i32 [[TMP17]], 14332// CHECK9-NEXT: [[CMP8:%.*]] = icmp ult i32 [[TMP16]], [[ADD7]]4333// CHECK9-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]4334// CHECK9: omp.inner.for.body:4335// CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 44336// CHECK9-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44337// CHECK9-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 14338// CHECK9-NEXT: [[ADD9:%.*]] = add i32 [[TMP18]], [[MUL]]4339// CHECK9-NEXT: store i32 [[ADD9]], ptr [[I5]], align 44340// CHECK9-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 44341// CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 14342// CHECK9-NEXT: store i32 [[ADD10]], ptr [[A_ADDR]], align 44343// CHECK9-NEXT: [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 24344// CHECK9-NEXT: [[CONV:%.*]] = sext i16 [[TMP21]] to i324345// CHECK9-NEXT: [[ADD11:%.*]] = add nsw i32 [[CONV]], 14346// CHECK9-NEXT: [[CONV12:%.*]] = trunc i32 [[ADD11]] to i164347// CHECK9-NEXT: store i16 [[CONV12]], ptr [[AA_ADDR]], align 24348// CHECK9-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 14349// CHECK9-NEXT: [[CONV13:%.*]] = sext i8 [[TMP22]] to i324350// CHECK9-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV13]], 14351// CHECK9-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i84352// CHECK9-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 14353// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 24354// CHECK9-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 44355// CHECK9-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP23]], 14356// CHECK9-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 44357// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]4358// CHECK9: omp.body.continue:4359// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]4360// CHECK9: omp.inner.for.inc:4361// CHECK9-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44362// CHECK9-NEXT: [[ADD17:%.*]] = add i32 [[TMP24]], 14363// CHECK9-NEXT: store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 44364// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]4365// CHECK9: omp.inner.for.end:4366// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]4367// CHECK9: omp.loop.exit:4368// CHECK9-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 84369// CHECK9-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 44370// CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP26]])4371// CHECK9-NEXT: br label [[OMP_PRECOND_END]]4372// CHECK9: omp.precond.end:4373// CHECK9-NEXT: ret void4374//4375//4376// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l2184377// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {4378// CHECK9-NEXT: entry:4379// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 84380// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 84381// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 84382// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 84383// CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 84384// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 84385// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 84386// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 84387// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 84388// CHECK9-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 84389// CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 84390// CHECK9-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 84391// CHECK9-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 84392// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 84393// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 84394// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 84395// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 84396// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 44397// CHECK9-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 44398// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 84399// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.omp_outlined, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]])4400// CHECK9-NEXT: ret void4401//4402//4403// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.omp_outlined4404// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {4405// CHECK9-NEXT: entry:4406// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 84407// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 84408// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 84409// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 84410// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 84411// CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 84412// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 84413// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 44414// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 44415// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 44416// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 44417// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 44418// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 44419// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 44420// CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 84421// CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 84422// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 84423// CHECK9-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 84424// CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 84425// CHECK9-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 84426// CHECK9-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 84427// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 84428// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 84429// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 84430// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 84431// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 44432// CHECK9-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 44433// CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 44434// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 44435// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 84436// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 44437// CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)4438// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44439// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 94440// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]4441// CHECK9: cond.true:4442// CHECK9-NEXT: br label [[COND_END:%.*]]4443// CHECK9: cond.false:4444// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44445// CHECK9-NEXT: br label [[COND_END]]4446// CHECK9: cond.end:4447// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]4448// CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 44449// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 44450// CHECK9-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 44451// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]4452// CHECK9: omp.inner.for.cond:4453// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44454// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44455// CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]4456// CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]4457// CHECK9: omp.inner.for.body:4458// CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44459// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 14460// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]4461// CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 44462// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 44463// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double4464// CHECK9-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+004465// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 04466// CHECK9-NEXT: store double [[ADD4]], ptr [[A]], align 84467// CHECK9-NEXT: [[A5:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 04468// CHECK9-NEXT: [[TMP13:%.*]] = load double, ptr [[A5]], align 84469// CHECK9-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+004470// CHECK9-NEXT: store double [[INC]], ptr [[A5]], align 84471// CHECK9-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i164472// CHECK9-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]4473// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP14]]4474// CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 14475// CHECK9-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 24476// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]4477// CHECK9: omp.body.continue:4478// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]4479// CHECK9: omp.inner.for.inc:4480// CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44481// CHECK9-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 14482// CHECK9-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 44483// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]4484// CHECK9: omp.inner.for.end:4485// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]4486// CHECK9: omp.loop.exit:4487// CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])4488// CHECK9-NEXT: ret void4489//4490//4491// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l1834492// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {4493// CHECK9-NEXT: entry:4494// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 84495// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 84496// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 84497// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 84498// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 84499// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 84500// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 84501// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 84502// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 84503// CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 84504// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 84505// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 44506// CHECK9-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 44507// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 84508// CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 24509// CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 24510// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 84511// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]])4512// CHECK9-NEXT: ret void4513//4514//4515// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.omp_outlined4516// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {4517// CHECK9-NEXT: entry:4518// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 84519// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 84520// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 84521// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 84522// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 84523// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 44524// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 44525// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 44526// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 44527// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 44528// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 44529// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 44530// CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 84531// CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 84532// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 84533// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 84534// CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 84535// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 84536// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 44537// CHECK9-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 44538// CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 44539// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 44540// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 84541// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 44542// CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)4543// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44544// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 94545// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]4546// CHECK9: cond.true:4547// CHECK9-NEXT: br label [[COND_END:%.*]]4548// CHECK9: cond.false:4549// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44550// CHECK9-NEXT: br label [[COND_END]]4551// CHECK9: cond.end:4552// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]4553// CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 44554// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 44555// CHECK9-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 44556// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]4557// CHECK9: omp.inner.for.cond:4558// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44559// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44560// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]4561// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]4562// CHECK9: omp.inner.for.body:4563// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44564// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 14565// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]4566// CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 44567// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 44568// CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 14569// CHECK9-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 44570// CHECK9-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 24571// CHECK9-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i324572// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 14573// CHECK9-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i164574// CHECK9-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 24575// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 24576// CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 44577// CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 14578// CHECK9-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 44579// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]4580// CHECK9: omp.body.continue:4581// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]4582// CHECK9: omp.inner.for.inc:4583// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44584// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 14585// CHECK9-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 44586// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]4587// CHECK9: omp.inner.for.end:4588// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]4589// CHECK9: omp.loop.exit:4590// CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])4591// CHECK9-NEXT: ret void4592//4593//4594// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1034595// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {4596// CHECK11-NEXT: entry:4597// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 44598// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 44599// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 44600// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 44601// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 44602// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])4603// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 44604// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 44605// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 44606// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 44607// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 44608// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 44609// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])4610// CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 24611// CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 24612// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 44613// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined, i32 [[TMP4]])4614// CHECK11-NEXT: ret void4615//4616//4617// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined4618// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {4619// CHECK11-NEXT: entry:4620// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 44621// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 44622// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 44623// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 44624// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 44625// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 44626// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 44627// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 44628// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 44629// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 44630// CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 44631// CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 44632// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 44633// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 44634// CHECK11-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 44635// CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 44636// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 44637// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 44638// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 44639// CHECK11-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)4640// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44641// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 94642// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]4643// CHECK11: cond.true:4644// CHECK11-NEXT: br label [[COND_END:%.*]]4645// CHECK11: cond.false:4646// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44647// CHECK11-NEXT: br label [[COND_END]]4648// CHECK11: cond.end:4649// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]4650// CHECK11-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 44651// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 44652// CHECK11-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 44653// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]4654// CHECK11: omp.inner.for.cond:4655// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44656// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44657// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]4658// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]4659// CHECK11: omp.inner.for.body:4660// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44661// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 14662// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]4663// CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 44664// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]4665// CHECK11: omp.body.continue:4666// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]4667// CHECK11: omp.inner.for.inc:4668// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44669// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 14670// CHECK11-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 44671// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]4672// CHECK11: omp.inner.for.end:4673// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]4674// CHECK11: omp.loop.exit:4675// CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])4676// CHECK11-NEXT: ret void4677//4678//4679// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1134680// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {4681// CHECK11-NEXT: entry:4682// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 44683// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 44684// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 44685// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 44686// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 44687// CHECK11-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 24688// CHECK11-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 24689// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 44690// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.omp_outlined, i32 [[TMP1]])4691// CHECK11-NEXT: ret void4692//4693//4694// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.omp_outlined4695// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {4696// CHECK11-NEXT: entry:4697// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 44698// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 44699// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 44700// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 44701// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 44702// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 44703// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 44704// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 44705// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 44706// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 44707// CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 44708// CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 44709// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 44710// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 44711// CHECK11-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 44712// CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 44713// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 44714// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 44715// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 44716// CHECK11-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)4717// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44718// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 94719// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]4720// CHECK11: cond.true:4721// CHECK11-NEXT: br label [[COND_END:%.*]]4722// CHECK11: cond.false:4723// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44724// CHECK11-NEXT: br label [[COND_END]]4725// CHECK11: cond.end:4726// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]4727// CHECK11-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 44728// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 44729// CHECK11-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 44730// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]4731// CHECK11: omp.inner.for.cond:4732// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44733// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44734// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]4735// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]4736// CHECK11: omp.inner.for.body:4737// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44738// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 14739// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]4740// CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 44741// CHECK11-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 24742// CHECK11-NEXT: [[CONV:%.*]] = sext i16 [[TMP8]] to i324743// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 14744// CHECK11-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i164745// CHECK11-NEXT: store i16 [[CONV3]], ptr [[AA_ADDR]], align 24746// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]4747// CHECK11: omp.body.continue:4748// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]4749// CHECK11: omp.inner.for.inc:4750// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44751// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 14752// CHECK11-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 44753// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]4754// CHECK11: omp.inner.for.end:4755// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]4756// CHECK11: omp.loop.exit:4757// CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])4758// CHECK11-NEXT: ret void4759//4760//4761// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1204762// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {4763// CHECK11-NEXT: entry:4764// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 44765// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 44766// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 44767// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 44768// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 44769// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 44770// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 44771// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 44772// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 44773// CHECK11-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 44774// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 44775// CHECK11-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 24776// CHECK11-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 24777// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 44778// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.omp_outlined, i32 [[TMP1]], i32 [[TMP3]])4779// CHECK11-NEXT: ret void4780//4781//4782// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.omp_outlined4783// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {4784// CHECK11-NEXT: entry:4785// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 44786// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 44787// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 44788// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 44789// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 44790// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 44791// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 44792// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 44793// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 44794// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 44795// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 44796// CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 44797// CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 44798// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 44799// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 44800// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 44801// CHECK11-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 44802// CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 44803// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 44804// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 44805// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 44806// CHECK11-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)4807// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44808// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 94809// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]4810// CHECK11: cond.true:4811// CHECK11-NEXT: br label [[COND_END:%.*]]4812// CHECK11: cond.false:4813// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44814// CHECK11-NEXT: br label [[COND_END]]4815// CHECK11: cond.end:4816// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]4817// CHECK11-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 44818// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 44819// CHECK11-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 44820// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]4821// CHECK11: omp.inner.for.cond:4822// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44823// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44824// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]4825// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]4826// CHECK11: omp.inner.for.body:4827// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44828// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 14829// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]4830// CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 44831// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 44832// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 14833// CHECK11-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 44834// CHECK11-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 24835// CHECK11-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i324836// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 14837// CHECK11-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i164838// CHECK11-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 24839// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]4840// CHECK11: omp.body.continue:4841// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]4842// CHECK11: omp.inner.for.inc:4843// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44844// CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 14845// CHECK11-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 44846// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]4847// CHECK11: omp.inner.for.end:4848// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]4849// CHECK11: omp.loop.exit:4850// CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])4851// CHECK11-NEXT: ret void4852//4853//4854// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1454855// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {4856// CHECK11-NEXT: entry:4857// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 44858// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 44859// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 44860// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 44861// CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 44862// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 44863// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 44864// CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 44865// CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 44866// CHECK11-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 44867// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 44868// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 44869// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 44870// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 44871// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 44872// CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 44873// CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 44874// CHECK11-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 44875// CHECK11-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 44876// CHECK11-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 44877// CHECK11-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 44878// CHECK11-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 44879// CHECK11-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 44880// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 44881// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 44882// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 44883// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 44884// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 44885// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 44886// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 44887// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 44888// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 44889// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 44890// CHECK11-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 44891// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 44892// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 44893// CHECK11-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 44894// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 44895// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i32 [[TMP11]])4896// CHECK11-NEXT: ret void4897//4898//4899// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.omp_outlined4900// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {4901// CHECK11-NEXT: entry:4902// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 44903// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 44904// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 44905// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 44906// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 44907// CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 44908// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 44909// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 44910// CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 44911// CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 44912// CHECK11-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 44913// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 44914// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 44915// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 44916// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 44917// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 44918// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 44919// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 44920// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 44921// CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 44922// CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 44923// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 44924// CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 44925// CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 44926// CHECK11-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 44927// CHECK11-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 44928// CHECK11-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 44929// CHECK11-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 44930// CHECK11-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 44931// CHECK11-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 44932// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 44933// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 44934// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 44935// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 44936// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 44937// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 44938// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 44939// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 44940// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 44941// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 44942// CHECK11-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 44943// CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 44944// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 44945// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 44946// CHECK11-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 44947// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 44948// CHECK11-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])4949// CHECK11-NEXT: br label [[OMP_DISPATCH_COND:%.*]]4950// CHECK11: omp.dispatch.cond:4951// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44952// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 94953// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]4954// CHECK11: cond.true:4955// CHECK11-NEXT: br label [[COND_END:%.*]]4956// CHECK11: cond.false:4957// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44958// CHECK11-NEXT: br label [[COND_END]]4959// CHECK11: cond.end:4960// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]4961// CHECK11-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 44962// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 44963// CHECK11-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 44964// CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44965// CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44966// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]4967// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]4968// CHECK11: omp.dispatch.body:4969// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]4970// CHECK11: omp.inner.for.cond:4971// CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14:![0-9]+]]4972// CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP14]]4973// CHECK11-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]4974// CHECK11-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]4975// CHECK11: omp.inner.for.body:4976// CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]4977// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 14978// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]4979// CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]]4980// CHECK11-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP14]]4981// CHECK11-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 14982// CHECK11-NEXT: store i32 [[ADD7]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP14]]4983// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 24984// CHECK11-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP14]]4985// CHECK11-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double4986// CHECK11-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+004987// CHECK11-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float4988// CHECK11-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP14]]4989// CHECK11-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 34990// CHECK11-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP14]]4991// CHECK11-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double4992// CHECK11-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+004993// CHECK11-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float4994// CHECK11-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP14]]4995// CHECK11-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 14996// CHECK11-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i32 0, i32 24997// CHECK11-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP14]]4998// CHECK11-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+004999// CHECK11-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP14]]5000// CHECK11-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]5001// CHECK11-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP23]]5002// CHECK11-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i32 35003// CHECK11-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP14]]5004// CHECK11-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+005005// CHECK11-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP14]]5006// CHECK11-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 05007// CHECK11-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP14]]5008// CHECK11-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 15009// CHECK11-NEXT: store i64 [[ADD20]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP14]]5010// CHECK11-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 15011// CHECK11-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP14]]5012// CHECK11-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i325013// CHECK11-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 15014// CHECK11-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i85015// CHECK11-NEXT: store i8 [[CONV23]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP14]]5016// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]5017// CHECK11: omp.body.continue:5018// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]5019// CHECK11: omp.inner.for.inc:5020// CHECK11-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]5021// CHECK11-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 15022// CHECK11-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]5023// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]5024// CHECK11: omp.inner.for.end:5025// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]]5026// CHECK11: omp.dispatch.inc:5027// CHECK11-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 45028// CHECK11-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 45029// CHECK11-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]5030// CHECK11-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 45031// CHECK11-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 45032// CHECK11-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 45033// CHECK11-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]5034// CHECK11-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 45035// CHECK11-NEXT: br label [[OMP_DISPATCH_COND]]5036// CHECK11: omp.dispatch.end:5037// CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]])5038// CHECK11-NEXT: ret void5039//5040//5041// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l2005042// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {5043// CHECK11-NEXT: entry:5044// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 45045// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 45046// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 45047// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 45048// CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 45049// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 45050// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 45051// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 45052// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 45053// CHECK11-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 45054// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 45055// CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 45056// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 45057// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 45058// CHECK11-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 45059// CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 45060// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 45061// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 45062// CHECK11-NEXT: store i32 [[TMP1]], ptr [[N_CASTED]], align 45063// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_CASTED]], align 45064// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[A_ADDR]], align 45065// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 45066// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_CASTED]], align 45067// CHECK11-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA_ADDR]], align 25068// CHECK11-NEXT: store i16 [[TMP5]], ptr [[AA_CASTED]], align 25069// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[AA_CASTED]], align 45070// CHECK11-NEXT: [[TMP7:%.*]] = load i8, ptr [[AAA_ADDR]], align 15071// CHECK11-NEXT: store i8 [[TMP7]], ptr [[AAA_CASTED]], align 15072// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[AAA_CASTED]], align 45073// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], ptr [[TMP0]])5074// CHECK11-NEXT: ret void5075//5076//5077// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.omp_outlined5078// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {5079// CHECK11-NEXT: entry:5080// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 45081// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 45082// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 45083// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 45084// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 45085// CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 45086// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 45087// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 45088// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 45089// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 45090// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 45091// CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 45092// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 45093// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 45094// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 45095// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 45096// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 45097// CHECK11-NEXT: [[I5:%.*]] = alloca i32, align 45098// CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 45099// CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 45100// CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 45101// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 45102// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 45103// CHECK11-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 45104// CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 45105// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 45106// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 45107// CHECK11-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 45108// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 45109// CHECK11-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_1]], align 45110// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 45111// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 45112// CHECK11-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]5113// CHECK11-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 15114// CHECK11-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 15115// CHECK11-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 15116// CHECK11-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 15117// CHECK11-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 45118// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 45119// CHECK11-NEXT: store i32 [[TMP5]], ptr [[I]], align 45120// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 45121// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 45122// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]5123// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]5124// CHECK11: omp.precond.then:5125// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 45126// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 45127// CHECK11-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_UB]], align 45128// CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 45129// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 45130// CHECK11-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 45131// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 45132// CHECK11-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP10]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)5133// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 45134// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 45135// CHECK11-NEXT: [[CMP6:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]5136// CHECK11-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]5137// CHECK11: cond.true:5138// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 45139// CHECK11-NEXT: br label [[COND_END:%.*]]5140// CHECK11: cond.false:5141// CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 45142// CHECK11-NEXT: br label [[COND_END]]5143// CHECK11: cond.end:5144// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]5145// CHECK11-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 45146// CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_LB]], align 45147// CHECK11-NEXT: store i32 [[TMP15]], ptr [[DOTOMP_IV]], align 45148// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]5149// CHECK11: omp.inner.for.cond:5150// CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 45151// CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 45152// CHECK11-NEXT: [[ADD7:%.*]] = add i32 [[TMP17]], 15153// CHECK11-NEXT: [[CMP8:%.*]] = icmp ult i32 [[TMP16]], [[ADD7]]5154// CHECK11-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]5155// CHECK11: omp.inner.for.body:5156// CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 45157// CHECK11-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 45158// CHECK11-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 15159// CHECK11-NEXT: [[ADD9:%.*]] = add i32 [[TMP18]], [[MUL]]5160// CHECK11-NEXT: store i32 [[ADD9]], ptr [[I5]], align 45161// CHECK11-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 45162// CHECK11-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 15163// CHECK11-NEXT: store i32 [[ADD10]], ptr [[A_ADDR]], align 45164// CHECK11-NEXT: [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 25165// CHECK11-NEXT: [[CONV:%.*]] = sext i16 [[TMP21]] to i325166// CHECK11-NEXT: [[ADD11:%.*]] = add nsw i32 [[CONV]], 15167// CHECK11-NEXT: [[CONV12:%.*]] = trunc i32 [[ADD11]] to i165168// CHECK11-NEXT: store i16 [[CONV12]], ptr [[AA_ADDR]], align 25169// CHECK11-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 15170// CHECK11-NEXT: [[CONV13:%.*]] = sext i8 [[TMP22]] to i325171// CHECK11-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV13]], 15172// CHECK11-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i85173// CHECK11-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 15174// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 25175// CHECK11-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 45176// CHECK11-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP23]], 15177// CHECK11-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 45178// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]5179// CHECK11: omp.body.continue:5180// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]5181// CHECK11: omp.inner.for.inc:5182// CHECK11-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 45183// CHECK11-NEXT: [[ADD17:%.*]] = add i32 [[TMP24]], 15184// CHECK11-NEXT: store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 45185// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]5186// CHECK11: omp.inner.for.end:5187// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]5188// CHECK11: omp.loop.exit:5189// CHECK11-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 45190// CHECK11-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 45191// CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP26]])5192// CHECK11-NEXT: br label [[OMP_PRECOND_END]]5193// CHECK11: omp.precond.end:5194// CHECK11-NEXT: ret void5195//5196//5197// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l2185198// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {5199// CHECK11-NEXT: entry:5200// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 45201// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 45202// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 45203// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 45204// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 45205// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 45206// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 45207// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 45208// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 45209// CHECK11-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 45210// CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 45211// CHECK11-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 45212// CHECK11-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 45213// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 45214// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 45215// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 45216// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 45217// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 45218// CHECK11-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 45219// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 45220// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.omp_outlined, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]])5221// CHECK11-NEXT: ret void5222//5223//5224// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.omp_outlined5225// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {5226// CHECK11-NEXT: entry:5227// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 45228// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 45229// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 45230// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 45231// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 45232// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 45233// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 45234// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 45235// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 45236// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 45237// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 45238// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 45239// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 45240// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 45241// CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 45242// CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 45243// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 45244// CHECK11-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 45245// CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 45246// CHECK11-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 45247// CHECK11-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 45248// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 45249// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 45250// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 45251// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 45252// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 45253// CHECK11-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 45254// CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 45255// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 45256// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 45257// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 45258// CHECK11-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)5259// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 45260// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 95261// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]5262// CHECK11: cond.true:5263// CHECK11-NEXT: br label [[COND_END:%.*]]5264// CHECK11: cond.false:5265// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 45266// CHECK11-NEXT: br label [[COND_END]]5267// CHECK11: cond.end:5268// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]5269// CHECK11-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 45270// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 45271// CHECK11-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 45272// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]5273// CHECK11: omp.inner.for.cond:5274// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 45275// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 45276// CHECK11-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]5277// CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]5278// CHECK11: omp.inner.for.body:5279// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 45280// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 15281// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]5282// CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 45283// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 45284// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double5285// CHECK11-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+005286// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 05287// CHECK11-NEXT: store double [[ADD4]], ptr [[A]], align 45288// CHECK11-NEXT: [[A5:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 05289// CHECK11-NEXT: [[TMP13:%.*]] = load double, ptr [[A5]], align 45290// CHECK11-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+005291// CHECK11-NEXT: store double [[INC]], ptr [[A5]], align 45292// CHECK11-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i165293// CHECK11-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]5294// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP14]]5295// CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 15296// CHECK11-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 25297// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]5298// CHECK11: omp.body.continue:5299// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]5300// CHECK11: omp.inner.for.inc:5301// CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 45302// CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 15303// CHECK11-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 45304// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]5305// CHECK11: omp.inner.for.end:5306// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]5307// CHECK11: omp.loop.exit:5308// CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])5309// CHECK11-NEXT: ret void5310//5311//5312// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l1835313// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {5314// CHECK11-NEXT: entry:5315// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 45316// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 45317// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 45318// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 45319// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 45320// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 45321// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 45322// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 45323// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 45324// CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 45325// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 45326// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 45327// CHECK11-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 45328// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 45329// CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 25330// CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 25331// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 45332// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]])5333// CHECK11-NEXT: ret void5334//5335//5336// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.omp_outlined5337// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {5338// CHECK11-NEXT: entry:5339// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 45340// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 45341// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 45342// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 45343// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 45344// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 45345// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 45346// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 45347// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 45348// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 45349// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 45350// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 45351// CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 45352// CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 45353// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 45354// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 45355// CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 45356// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 45357// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 45358// CHECK11-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 45359// CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 45360// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 45361// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 45362// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 45363// CHECK11-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)5364// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 45365// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 95366// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]5367// CHECK11: cond.true:5368// CHECK11-NEXT: br label [[COND_END:%.*]]5369// CHECK11: cond.false:5370// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 45371// CHECK11-NEXT: br label [[COND_END]]5372// CHECK11: cond.end:5373// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]5374// CHECK11-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 45375// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 45376// CHECK11-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 45377// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]5378// CHECK11: omp.inner.for.cond:5379// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 45380// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 45381// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]5382// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]5383// CHECK11: omp.inner.for.body:5384// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 45385// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 15386// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]5387// CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 45388// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 45389// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 15390// CHECK11-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 45391// CHECK11-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 25392// CHECK11-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i325393// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 15394// CHECK11-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i165395// CHECK11-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 25396// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 25397// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 45398// CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 15399// CHECK11-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 45400// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]5401// CHECK11: omp.body.continue:5402// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]5403// CHECK11: omp.inner.for.inc:5404// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 45405// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 15406// CHECK11-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 45407// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]5408// CHECK11: omp.inner.for.end:5409// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]5410// CHECK11: omp.loop.exit:5411// CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])5412// CHECK11-NEXT: ret void5413//5414